Diff: targets/cmsis/TARGET_Freescale/TARGET_KL27Z/system_MKL27Z644.c

Revision:

121:7f86b4238bec

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL27Z/system_MKL27Z644.c	Tue May 03 00:15:16 2016 +0100
@@ -0,0 +1,155 @@
+/*
+** ###################################################################
+**     Processors:          MKL27Z32VDA4
+**                          MKL27Z32VFM4
+**                          MKL27Z32VFT4
+**                          MKL27Z32VLH4
+**                          MKL27Z32VMP4
+**                          MKL27Z64VDA4
+**                          MKL27Z64VFM4
+**                          MKL27Z64VFT4
+**                          MKL27Z64VLH4
+**                          MKL27Z64VMP4
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL27P64M48SF2RM, Rev. 1, Sep 2014
+**     Version:             rev. 1.4, 2014-09-22
+**     Build:               b151217
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-05-12)
+**         Initial version.
+**     - rev. 1.1 (2014-07-10)
+**         UART0 - UART0 module renamed to UART2.
+**     - rev. 1.2 (2014-08-12)
+**         CRC - CRC register renamed to DATA.
+**     - rev. 1.3 (2014-09-02)
+**         USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+**         USB - USB0_CTL1 was renamed to USB0_CTL register.
+**         USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register.
+**     - rev. 1.4 (2014-09-22)
+**         FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers.
+**         SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+**         SIM - Removed bitfield DIEID in SDID register.
+**         UART2 - Removed ED register.
+**         UART2 - Removed MODEM register.
+**         UART2 - Removed IR register.
+**         UART2 - Removed PFIFO register.
+**         UART2 - Removed CFIFO register.
+**         UART2 - Removed SFIFO register.
+**         UART2 - Removed TWFIFO register.
+**         UART2 - Removed TCFIFO register.
+**         UART2 - Removed RWFIFO register.
+**         UART2 - Removed RCFIFO register.
+**         USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+**         USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL27Z644
+ * @version 1.4
+ * @date 2014-09-22
+ * @brief Device specific configuration file for MKL27Z644 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+
+#if (ACK_ISOLATION)
+  if(PMC->REGSC &  PMC_REGSC_ACKISO_MASK) {
+    PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
+  }
+#endif
+#if (DISABLE_WDOG)
+  /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
+  SIM->COPC = (uint32_t)0x00u;
+#endif /* (DISABLE_WDOG) */
+
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+  uint32_t MCGOUTClock;                                 /* Variable to store output clock frequency of the MCG module */
+  uint16_t Divider;
+
+  if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) {
+    /* High internal reference clock is selected */
+    MCGOUTClock = CPU_INT_FAST_CLK_HZ;                                  /* Fast internal reference clock selected */
+  } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) {
+    /* Internal reference clock is selected */
+    Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+    MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider);           /* Slow internal reference clock 8MHz selected */
+  } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) {
+    /* External reference clock is selected */
+    MCGOUTClock = CPU_XTAL_CLK_HZ;
+  } else {
+    /* Reserved value */
+    return;
+  } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
+  SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+
+}