en 129
fix LPC812 PWM
Fork of
mbed-dev
by 
mbed official
Diff: targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_fsmc.h
- Revision:
- 124:6a4a5b7d7324
- Parent:
- 0:9b334a45a8ff
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_fsmc.h Thu May 05 21:00:11 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_fsmc.h Mon May 09 18:30:12 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_ll_fsmc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 15-December-2014
+ * @version V1.0.4
+ * @date 29-April-2016
* @brief Header file of FSMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,14 +33,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_FSMC_H
#define __STM32F1xx_LL_FSMC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -50,11 +50,11 @@
* @{
*/
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
+#if defined(FSMC_BANK1)
/** @addtogroup FSMC_LL
* @{
- */
+ */
/** @addtogroup FSMC_LL_Private_Macros
* @{
@@ -76,65 +76,69 @@
((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
+ ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
+
#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
((__MODE__) == FSMC_ACCESS_MODE_B) || \
((__MODE__) == FSMC_ACCESS_MODE_C) || \
((__MODE__) == FSMC_ACCESS_MODE_D))
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
- ((BANK) == FSMC_NAND_BANK3))
+#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \
+ ((__BANK__) == FSMC_NAND_BANK3))
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+
+#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
-#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
- ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
-
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
- ((STATE) == FSMC_NAND_ECC_ENABLE))
-
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
-/** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time
+#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
+ ((__STATE__) == FSMC_NAND_ECC_ENABLE))
+
+#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+
+/** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time
* @{
*/
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
+#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
/**
* @}
*/
-/** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time
+/** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time
* @{
*/
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
+#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
/**
* @}
*/
-/** @defgroup FSMC_Setup_Time FSMC_Setup_Time
+/** @defgroup FSMC_Setup_Time FSMC_Setup_Time
* @{
*/
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
+#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
/**
* @}
*/
-/** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time
+/** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time
* @{
*/
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
+#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
/**
* @}
*/
-/** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time
+/** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time
* @{
*/
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
+#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
/**
* @}
*/
@@ -142,15 +146,15 @@
/** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time
* @{
*/
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
+#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
/**
* @}
- */
-
+ */
+
/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
* @{
*/
-
+
#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
/**
@@ -160,30 +164,29 @@
/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
* @{
*/
-
+
#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
/**
* @}
*/
-/** @defgroup FSMC_NAND_Device_Instance FSMC_NAND_Device_Instance
+/** @defgroup FSMC_NAND_Device_Instance FSMC NAND Device Instance
* @{
*/
-#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
+#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
/**
* @}
- */
+ */
-/** @defgroup FSMC_PCCARD_Device_Instance FSMC_PCCARD_Device_Instance
+/** @defgroup FSMC_PCCARD_Device_Instance FSMC PCCARD Device Instance
* @{
*/
-#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
+#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
/**
* @}
- */
-
+ */
#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
@@ -191,16 +194,16 @@
((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
- ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
+ ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
- ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
+ ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
- ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
+ ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
- ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
+ ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
@@ -208,23 +211,19 @@
#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
-#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
/** @defgroup FSMC_Data_Latency FSMC Data Latency
* @{
*/
-
#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
/**
* @}
- */
+ */
-#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
- ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
* @{
*/
-
#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
/**
* @}
@@ -233,7 +232,6 @@
/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
* @{
*/
-
#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
/**
* @}
@@ -242,7 +240,6 @@
/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
* @{
*/
-
#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
/**
* @}
@@ -251,7 +248,6 @@
/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
* @{
*/
-
#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
/**
* @}
@@ -261,109 +257,108 @@
* @}
*/
-/* Exported typedef ----------------------------------------------------------*/
+/* Exported typedef ----------------------------------------------------------*/
/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types
* @{
- */
-
+ */
+
#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
-#define FSMC_NORSRAM_DEVICE FSMC_Bank1
-#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
-#define FSMC_NAND_DEVICE FSMC_Bank2_3
-#define FSMC_PCCARD_DEVICE FSMC_Bank4
+#define FSMC_NORSRAM_DEVICE FSMC_Bank1
+#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
+#define FSMC_NAND_DEVICE FSMC_Bank2_3
+#define FSMC_PCCARD_DEVICE FSMC_Bank4
-/**
- * @brief FSMC_NORSRAM Configuration Structure definition
- */
+/**
+ * @brief FSMC_NORSRAM Configuration Structure definition
+ */
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the data bus or not.
+ multiplexed on the data bus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
+
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
This parameter can be a value of @ref FSMC_Memory_Type */
-
+
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
-
+
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-
+
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
+
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FSMC_Wrap_Mode */
-
+
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
+ valid only when accessing memories in burst mode.
This parameter can be a value of @ref FSMC_Wait_Timing */
-
- uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
+
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */
-
+
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
- signal, valid for Flash memory access in burst mode.
+ signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */
-
+
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FSMC_Extended_Mode */
-
+
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FSMC_AsynchronousWait */
-
+
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
+ This parameter can be a value of @ref FSMC_Write_Burst */
}FSMC_NORSRAM_InitTypeDef;
-
-/**
- * @brief FSMC_NORSRAM Timing parameters structure definition
+/**
+ * @brief FSMC_NORSRAM Timing parameters structure definition
*/
typedef struct
{
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
+ the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
-
+
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
- This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
-
+
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories. */
-
+
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is only used for multiplexed NOR Flash memories. */
-
- uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
+
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
accesses. */
-
+
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
@@ -371,44 +366,44 @@
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
with synchronous burst mode enable */
-
- uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
+
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FSMC_Access_Mode */
-
+
}FSMC_NORSRAM_TimingTypeDef;
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
-/**
- * @brief FSMC_NAND Configuration Structure definition
- */
+#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
+/**
+ * @brief FSMC_NAND Configuration Structure definition
+ */
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FSMC_NAND_Bank */
-
+ This parameter can be a value of @ref FSMC_NAND_Bank */
+
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
This parameter can be any value of @ref FSMC_Wait_feature */
-
+
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FSMC_NAND_Data_Width */
-
+
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FSMC_ECC */
-
+
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
+
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FSMC_NAND_InitTypeDef;
-/**
+}FSMC_NAND_InitTypeDef;
+
+/**
* @brief FSMC_NAND_PCCARD Timing parameters structure definition
*/
typedef struct
@@ -418,45 +413,47 @@
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
+ memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
data bus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
}FSMC_NAND_PCC_TimingTypeDef;
-/**
- * @brief FSMC_NAND Configuration Structure definition
- */
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
+#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
+/**
+ * @brief FSMC_NAND Configuration Structure definition
+ */
typedef struct
{
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
This parameter can be any value of @ref FSMC_Wait_feature */
-
+
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FSMC_PCCARD_InitTypeDef;
+
+}FSMC_PCCARD_InitTypeDef;
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
/**
@@ -467,12 +464,12 @@
/** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants
* @{
- */
-
+ */
+
/** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
* @{
- */
-
+ */
+
/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
* @{
*/
@@ -504,7 +501,6 @@
#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0)
#define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1)
-
/**
* @}
*/
@@ -524,7 +520,7 @@
/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
* @{
*/
-
+
#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN)
#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
/**
@@ -535,18 +531,18 @@
* @{
*/
-#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN)
/**
* @}
*/
-
+
/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
* @{
*/
-
+
#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL)
@@ -557,7 +553,7 @@
/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
* @{
*/
-
+
#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
#define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD)
@@ -568,7 +564,7 @@
/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
* @{
*/
-
+
#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG)
@@ -579,7 +575,7 @@
/** @defgroup FSMC_Write_Operation FSMC Write Operation
* @{
*/
-
+
#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN)
@@ -590,7 +586,7 @@
/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
* @{
*/
-
+
#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN)
@@ -601,7 +597,7 @@
/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
* @{
*/
-
+
#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD)
@@ -612,13 +608,13 @@
/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
* @{
*/
-
+
#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT)
/**
* @}
- */
+ */
/** @defgroup FSMC_Write_Burst FSMC Write Burst
* @{
@@ -634,29 +630,28 @@
/** @defgroup FSMC_Access_Mode FSMC Access Mode
* @{
*/
-
+
#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
-#define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0)
+#define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0)
#define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1)
#define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
/**
* @}
*/
-
/**
* @}
*/
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
+#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
/** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller
* @{
*/
-/** @defgroup FSMC_NAND_Bank FSMC_NAND_Bank
+/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
* @{
- */
+ */
#define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
#define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
@@ -664,17 +659,17 @@
* @}
*/
-/** @defgroup FSMC_Wait_feature FSMC_Wait_feature
+/** @defgroup FSMC_Wait_feature FSMC Wait feature
* @{
*/
#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
-#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
+#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FSMC_PCRx_PWAITEN)
/**
* @}
*/
-/** @defgroup FSMC_PCR_Memory_Type FSMC_PCR_Memory_Type
+/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
* @{
*/
#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
@@ -683,7 +678,7 @@
* @}
*/
-/** @defgroup FSMC_NAND_Data_Width FSMC_NAND_Data_Width
+/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
* @{
*/
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
@@ -693,7 +688,7 @@
* @}
*/
-/** @defgroup FSMC_ECC FSMC_ECC
+/** @defgroup FSMC_ECC FSMC NAND ECC
* @{
*/
#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
@@ -703,7 +698,7 @@
* @}
*/
-/** @defgroup FSMC_ECC_Page_Size FSMC_ECC_Page_Size
+/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
* @{
*/
#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
@@ -717,10 +712,10 @@
* @}
*/
-/** @defgroup FSMC_Interrupt_definition FSMC_Interrupt_definition
+/** @defgroup FSMC_Interrupt_definition FSMC Interrupt definition
* @brief FSMC Interrupt definition
* @{
- */
+ */
#define FSMC_IT_RISING_EDGE ((uint32_t)FSMC_SRx_IREN)
#define FSMC_IT_LEVEL ((uint32_t)FSMC_SRx_ILEN)
#define FSMC_IT_FALLING_EDGE ((uint32_t)FSMC_SRx_IFEN)
@@ -728,11 +723,11 @@
/**
* @}
*/
-
-/** @defgroup FSMC_Flag_definition FSMC_Flag_definition
+
+/** @defgroup FSMC_Flag_definition FSMC Flag definition
* @brief FSMC Flag definition
* @{
- */
+ */
#define FSMC_FLAG_RISING_EDGE ((uint32_t)FSMC_SRx_IRS)
#define FSMC_FLAG_LEVEL ((uint32_t)FSMC_SRx_ILS)
#define FSMC_FLAG_FALLING_EDGE ((uint32_t)FSMC_SRx_IFS)
@@ -755,202 +750,205 @@
/** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros
* @{
- */
-
+ */
+
/** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros
* @brief macros to handle NOR device enable/disable and read/write operations
* @{
*/
-
+
/**
* @brief Enable the NORSRAM device access.
- * @param __INSTANCE__: FSMC_NORSRAM Instance
- * @param __BANK__: FSMC_NORSRAM Bank
+ * @param __INSTANCE__ FSMC_NORSRAM Instance
+ * @param __BANK__ FSMC_NORSRAM Bank
* @retval none
- */
+ */
#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
- * @param __INSTANCE__: FSMC_NORSRAM Instance
- * @param __BANK__: FSMC_NORSRAM Bank
+ * @param __INSTANCE__ FSMC_NORSRAM Instance
+ * @param __BANK__ FSMC_NORSRAM Bank
* @retval none
- */
+ */
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
/**
* @}
- */
+ */
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
-/** @defgroup FSMC_NAND_Macros FSMC_NAND_Macros
+#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
+/** @defgroup FSMC_NAND_Macros FSMC NAND Macros
* @brief macros to handle NAND device enable/disable
* @{
*/
-
+
/**
* @brief Enable the NAND device access.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
+ * @param __INSTANCE__ FSMC_NAND Instance
+ * @param __BANK__ FSMC_NAND Bank
* @retval None
- */
+ */
#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
- SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
+ SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
/**
* @brief Disable the NAND device access.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
+ * @param __INSTANCE__ FSMC_NAND Instance
+ * @param __BANK__ FSMC_NAND Bank
* @retval None
- */
+ */
#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
- CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
+ CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
+
/**
* @}
- */
-
-/** @defgroup FSMC_PCCARD_Macros FSMC_PCCARD_Macros
- * @brief macros to handle SRAM read/write operations
+ */
+
+/** @defgroup FSMC_PCCARD_Macros FSMC PCCARD Macros
+ * @brief macros to handle PCCARD read/write operations
* @{
*/
/**
* @brief Enable the PCCARD device access.
- * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __INSTANCE__ FSMC_PCCARD Instance
* @retval None
- */
+ */
#define __FSMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
/**
* @brief Disable the PCCARD device access.
- * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __INSTANCE__ FSMC_PCCARD Instance
* @retval None
- */
+ */
#define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
/**
* @}
*/
-
-/** @defgroup FSMC_Interrupt FSMC_Interrupt
+
+/** @defgroup FSMC_Interrupt FSMC Interrupt
* @brief macros to handle FSMC interrupts
* @{
- */
+ */
/**
* @brief Enable the NAND device interrupt.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @param __INTERRUPT__: FSMC_NAND interrupt
+ * @param __INSTANCE__ FSMC_NAND Instance
+ * @param __BANK__ FSMC_NAND Bank
+ * @param __INTERRUPT__ FSMC_NAND interrupt
* This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
* @retval None
- */
+ */
#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
/**
* @brief Disable the NAND device interrupt.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @param __INTERRUPT__: FSMC_NAND interrupt
+ * @param __INSTANCE__ FSMC_NAND Instance
+ * @param __BANK__ FSMC_NAND Bank
+ * @param __INTERRUPT__ FSMC_NAND interrupt
* This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
* @retval None
*/
#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
- CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
-
+ CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
+
/**
* @brief Get flag status of the NAND device.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @param __FLAG__: FSMC_NAND flag
+ * @param __INSTANCE__ FSMC_NAND Instance
+ * @param __BANK__ FSMC_NAND Bank
+ * @param __FLAG__ FSMC_NAND flag
* This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+
/**
* @brief Clear flag status of the NAND device.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @param __FLAG__: FSMC_NAND flag
+ * @param __INSTANCE__ FSMC_NAND Instance
+ * @param __BANK__ FSMC_NAND Bank
+ * @param __FLAG__ FSMC_NAND flag
* This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT FIFO empty flag.
* @retval None
*/
#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
- CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
+ CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
+
/**
* @brief Enable the PCCARD device interrupt.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @param __INTERRUPT__: FSMC_PCCARD interrupt
+ * @param __INSTANCE__ FSMC_PCCARD Instance
+ * @param __INTERRUPT__ FSMC_PCCARD interrupt
* This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
* @retval None
- */
+ */
#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
/**
* @brief Disable the PCCARD device interrupt.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @param __INTERRUPT__: FSMC_PCCARD interrupt
+ * @param __INSTANCE__ FSMC_PCCARD Instance
+ * @param __INTERRUPT__ FSMC_PCCARD interrupt
* This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
* @retval None
- */
-#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
+ */
+#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
/**
* @brief Get flag status of the PCCARD device.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @param __FLAG__: FSMC_PCCARD flag
+ * @param __INSTANCE__ FSMC_PCCARD Instance
+ * @param __FLAG__ FSMC_PCCARD flag
* This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
/**
* @brief Clear flag status of the PCCARD device.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @param __FLAG__: FSMC_PCCARD flag
+ * @param __INSTANCE__ FSMC_PCCARD Instance
+ * @param __FLAG__ FSMC_PCCARD flag
* This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT FIFO empty flag.
* @retval None
*/
#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
-
+
/**
* @}
- */
+ */
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
/**
* @}
- */
+ */
/* Exported functions --------------------------------------------------------*/
@@ -975,7 +973,7 @@
/**
* @}
- */
+ */
/** @addtogroup FSMC_NORSRAM_Group2
* @{
@@ -987,13 +985,13 @@
/**
* @}
- */
+ */
/**
* @}
- */
+ */
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
+#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
/** @addtogroup FSMC_NAND
* @{
*/
@@ -1011,7 +1009,7 @@
/**
* @}
- */
+ */
/* FSMC_NAND Control functions */
/** @addtogroup FSMC_NAND_Exported_Functions_Group2
@@ -1024,11 +1022,11 @@
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/** @addtogroup FSMC_PCCARD
* @{
@@ -1048,28 +1046,27 @@
/**
* @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
+ */
/**
* @}
*/
-
+
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FSMC_BANK1 */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif