en 129
fix LPC812 PWM
Fork of
mbed-dev
by 
mbed official
Diff: targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.c
- Revision:
- 124:6a4a5b7d7324
- Parent:
- 0:9b334a45a8ff
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.c Thu May 05 21:00:11 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.c Mon May 09 18:30:12 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 15-December-2014
+ * @version V1.0.4
+ * @date 29-April-2016
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -18,18 +18,16 @@
After reset the device is running from Internal High Speed oscillator
(HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
and all peripherals are off except internal SRAM, Flash and JTAG.
- (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
- all peripherals mapped on these busses are running at HSI speed.
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
+ all peripherals mapped on these buses are running at HSI speed.
(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
(+) All GPIOs are in input floating state, except the JTAG pins which
are assigned to be used for debug purpose.
-
- [..]
- Once the device started from reset, the user application has to:
+ [..] Once the device started from reset, the user application has to:
(+) Configure the clock source to be used to drive the System clock
(if the application needs higher frequency/performance)
(+) Configure the System clock frequency and Flash settings
- (+) Configure the AHB and APB busses prescalers
+ (+) Configure the AHB and APB buses prescalers
(+) Enable the clock for the peripheral(s) to be used
(+) Configure the clock source(s) for peripherals whose clocks are not
derived from the System clock (I2S, RTC, ADC, USB OTG FS)
@@ -52,7 +50,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -77,8 +75,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
-*/
-
+*/
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
@@ -98,6 +96,10 @@
/** @defgroup RCC_Private_Constants RCC Private Constants
* @{
*/
+/* Bits position in in the CFGR register */
+#define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
+#define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)
+#define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)
/**
* @}
*/
@@ -106,7 +108,7 @@
* @{
*/
-#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define MCO1_GPIO_PORT GPIOA
#define MCO1_PIN GPIO_PIN_8
@@ -118,14 +120,12 @@
/** @defgroup RCC_Private_Variables RCC Private Variables
* @{
*/
-const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
/** @defgroup RCC_Exported_Functions RCC Exported Functions
* @{
@@ -136,18 +136,17 @@
*
@verbatim
===============================================================================
-##### Initialization and de-initialization functions #####
+ ##### Initialization and de-initialization functions #####
===============================================================================
[..]
- This section provide functions allowing to configure the internal/external oscillators
- (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
+ This section provides functions allowing to configure the internal/external oscillators
+ (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
and APB2).
[..] Internal/external clock and PLL configuration
- (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
+ (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
the PLL as System clock source.
-
- (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
+ (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
clock source.
(#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
@@ -155,28 +154,28 @@
(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
- (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
+ (#) PLL (clocked by HSI or HSE), featuring different output clocks:
(++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
(++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
and if a HSE clock failure occurs(HSE used directly or through PLL as System
- clock source), the System clockis automatically switched to HSI and an interrupt
+ clock source), the System clocks automatically switched to HSI and an interrupt
is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
(Non-Maskable Interrupt) exception vector.
(#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
- [..] System, AHB and APB busses clocks configuration
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ [..] System, AHB and APB buses clocks configuration
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable
- prescaler and used to clock the CPU, memory and peripherals mapped
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
- from AHB clock through configurable prescalers and used to clock
- the peripherals mapped on these busses. You can use
- "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these buses. You can use
+ "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
(+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
@@ -188,7 +187,13 @@
(#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
- Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
+ Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
+ @endverbatim
+ * @{
+ */
+
+/*
+ Additional consideration on the SYSCLK based on Latency settings:
+-----------------------------------------------+
| Latency | SYSCLK clock frequency (MHz) |
|---------------|-------------------------------|
@@ -198,8 +203,6 @@
|---------------|-------------------------------|
|2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
+-----------------------------------------------+
- @endverbatim
- * @{
*/
/**
@@ -210,16 +213,16 @@
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS and MCO1 OFF
* - All interrupts disabled
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
+ * @note This function does not modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
* @retval None
*/
-__weak void HAL_RCC_DeInit(void)
+void HAL_RCC_DeInit(void)
{
/* Switch SYSCLK to HSI */
CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
-
+
/* Reset HSEON, CSSON, & PLLON bits */
CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
@@ -232,20 +235,34 @@
/* Set HSITRIM bits to the reset value */
MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
+#if (defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE))
+ /* Reset CFGR2 register */
+ CLEAR_REG(RCC->CFGR2);
+
+#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
/* Disable all interrupts */
CLEAR_REG(RCC->CIR);
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HSI_VALUE;
}
/**
* @brief Initializes the RCC Oscillators according to the specified parameters in the
* RCC_OscInitTypeDef.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC Oscillators.
* @note The PLL is not disabled when used as system clock.
* @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this macro. User should request a transition to LSE Off
+ * first and then LSE On or LSE Bypass.
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
* @retval HAL status
*/
-__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
uint32_t tickstart = 0;
@@ -263,38 +280,24 @@
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
{
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON) && (RCC_OscInitStruct->HSEState != RCC_HSE_BYPASS))
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
return HAL_ERROR;
}
}
else
{
- /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
- __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- /* Check the HSE State */
+
+ /* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
{
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
- /* Wait till HSE is ready */
+ /* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
@@ -305,7 +308,7 @@
}
else
{
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSE is disabled */
@@ -345,15 +348,15 @@
else
{
/* Check the HSI State */
- if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
{
- /* Enable the Internal High Speed oscillator (HSI). */
+ /* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
- /* Wait till HSI is ready */
+ /* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
@@ -370,10 +373,10 @@
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
- /* Wait till HSI is disabled */
+ /* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
@@ -391,12 +394,12 @@
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
- if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
@@ -407,7 +410,7 @@
return HAL_TIMEOUT;
}
}
- /* To have a fully stabilized clock in the specified range, a software temporization of 1ms
+ /* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
HAL_Delay(1);
}
@@ -416,7 +419,7 @@
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSI is disabled */
@@ -434,45 +437,30 @@
{
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR, PWR_CR_DBP);
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
while((PWR->CR & PWR_CR_DBP) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
- __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
}
- }
-
+
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
- if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
+ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
{
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
@@ -486,7 +474,7 @@
}
else
{
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSE is disabled */
@@ -500,6 +488,96 @@
}
}
+#if defined(RCC_CR_PLL2ON)
+ /*-------------------------------- PLL2 Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
+ if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
+ {
+ /* This bit can not be cleared if the PLL2 clock is used indirectly as system
+ clock (i.e. it is used as PLL clock entry that is used as system clock). */
+ if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
+ (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
+ ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
+ assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
+
+ /* Prediv2 can be written only when the PLLI2S is disabled. */
+ /* Return an error only if new value is different from the programmed value */
+ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
+ (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the main PLL2. */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the HSE prediv2 factor --------------------------------*/
+ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
+
+ /* Configure the main PLL2 multiplication factors. */
+ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
+
+ /* Enable the main PLL2. */
+ __HAL_RCC_PLL2_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Set PREDIV1 source to HSE */
+ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
+
+ /* Disable the main PLL2. */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL2 is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+
+#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
@@ -513,14 +591,14 @@
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
-
+
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
- /* Wait till PLL is ready */
+ /* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
@@ -528,14 +606,21 @@
return HAL_TIMEOUT;
}
}
-
- /* Configure the HSE prediv1 factor --------------------------------*/
+
+ /* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
{
- /* Check the parameters */
+ /* Check the parameter */
assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
+ /* Set PREDIV1 source */
+ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
+#endif /* RCC_CFGR2_PREDIV1SRC */
+
+ /* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
}
@@ -545,7 +630,7 @@
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
@@ -562,7 +647,7 @@
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till PLL is disabled */
@@ -585,33 +670,29 @@
}
/**
- * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
+ * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
* parameters in the RCC_ClkInitStruct.
- * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC peripheral.
- * @param FLatency: FLASH Latency
- * This parameter can be one of the following values:
- * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
- * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle
- * @arg FLASH_LATENCY_2: FLASH 2 Latency cycle
- *
+ * @param FLatency FLASH Latency
+ * The value of this parameter depend on device used within the same series
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated by HAL_RCC_GetHCLKFreq() function called within this function
+ * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
*
* @note The HSI is used (enabled by hardware) as system clock source after
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case
+ * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
* of failure of the HSE used directly or indirectly as system clock
* (if the Clock Security System CSS is enabled).
*
* @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
+ * clock source is ready (clock stable after start-up delay or PLL locked).
* If a clock source which is not yet ready is selected, the switch will
* occur when the clock source will be ready.
- * You can use HAL_RCC_GetClockConfig() function to know which clock is
+ * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
- * @retval None
+ * @retval HAL status
*/
-__weak HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
uint32_t tickstart = 0;
@@ -619,11 +700,27 @@
assert_param(RCC_ClkInitStruct != NULL);
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
assert_param(IS_FLASH_LATENCY(FLatency));
-
+
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
+#if defined(FLASH_ACR_LATENCY)
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
@@ -663,10 +760,9 @@
return HAL_ERROR;
}
}
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
@@ -700,7 +796,22 @@
}
}
}
-
+#if defined(FLASH_ACR_LATENCY)
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+#endif /* FLASH_ACR_LATENCY */
+
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
@@ -714,7 +825,10 @@
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
}
-
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
+
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
@@ -725,8 +839,8 @@
* @}
*/
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
- * @brief RCC clocks control functions
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
*
@verbatim
===============================================================================
@@ -743,46 +857,56 @@
/**
* @brief Selects the clock source to output on MCO pin.
* @note MCO pin should be configured in alternate function mode.
- * @param RCC_MCOx: specifies the output direction for the clock source.
+ * @param RCC_MCOx specifies the output direction for the clock source.
* This parameter can be one of the following values:
- * @arg RCC_MCO: Clock source to output on MCO1 pin(PA8).
- * @param RCC_MCOSource: specifies the clock source to output.
+ * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
+ * @param RCC_MCOSource specifies the clock source to output.
* This parameter can be one of the following values:
- * @arg RCC_MCO1SOURCE_NOCLOCK: No clock selected
- * @arg RCC_MCO1SOURCE_SYSCLK: System clock selected as MCO source
- * @arg RCC_MCO1SOURCE_HSI: HSI oscillator clock selected
- * @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected
- * @arg RCC_MCO1SOURCE_PLLCLK: PLL clock divided by 2 selected as MCO source
- * @arg RCC_MCO1SOURCE_PLL2CLK: PLL2 clock selected as MCO source (only for connectivity line devices)
- * @arg RCC_MCO1SOURCE_PLL3CLK_DIV2: PLL3 clock divided by 2 selected as MCO source (only for connectivity line devices)
- * @arg RCC_MCO1SOURCE_EXT_HSE: XT1 external 3-25 MHz oscillator clock selected as MCO source (only for connectivity line devices)
- * @arg RCC_MCO1SOURCE_PLL3CLK: PLL3 clock selected as MCO source (only for connectivity line devices)
- * @param RCC_MCODiv: specifies the MCO DIV.
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
+ @if STM32F105xC
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
+ @endif
+ @if STM32F107xC
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
+ * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
+ @endif
+ * @param RCC_MCODiv specifies the MCO DIV.
* This parameter can be one of the following values:
- * @arg RCC_MCODIV_1: no division applied to MCO clock
+ * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
* @retval None
*/
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
{
- GPIO_InitTypeDef gpio;
-
+ GPIO_InitTypeDef gpio = {0};
+
/* Check the parameters */
assert_param(IS_RCC_MCO(RCC_MCOx));
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
- /* MCO Clock Enable */
+ /* Configure the MCO1 pin in alternate function mode */
+ gpio.Mode = GPIO_MODE_AF_PP;
+ gpio.Speed = GPIO_SPEED_FREQ_HIGH;
+ gpio.Pull = GPIO_NOPULL;
+ gpio.Pin = MCO1_PIN;
+
+ /* MCO1 Clock Enable */
MCO1_CLK_ENABLE();
- /* Configure the MCO1 pin in alternate function mode */
- gpio.Pin = MCO1_PIN;
- gpio.Mode = GPIO_MODE_AF_PP;
- gpio.Speed = GPIO_SPEED_HIGH;
- gpio.Pull = GPIO_NOPULL;
HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
- /* Mask MCO and MCOPRE[2:0] bits then Select MCO clock source and prescaler */
- MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, RCC_MCOSource);
+ /* Configure the MCO clock source */
+ __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
}
/**
@@ -810,17 +934,17 @@
/**
* @brief Returns the SYSCLK frequency
- *
* @note The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
+ * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
* divided by PREDIV factor(**)
- * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
+ * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
* divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
* @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
- * 8 MHz).
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
* @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
@@ -830,40 +954,79 @@
* value for HSE crystal.
*
* @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other parameters.
+ * baud-rate for the communication peripherals or configure other parameters.
*
* @note Each time SYSCLK changes, this function must be called to update the
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
- *
* @retval SYSCLK frequency
*/
-__weak uint32_t HAL_RCC_GetSysClockFreq(void)
+uint32_t HAL_RCC_GetSysClockFreq(void)
{
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
+ const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
+#else
const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
+#if defined(RCC_CFGR2_PREDIV1)
+ const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
+#else
const uint8_t aPredivFactorTable[2] = { 1, 2};
+#endif /*RCC_CFGR2_PREDIV1*/
- uint32_t tmpreg = 0, prediv1 = 0, pllclk = 0, pllmul = 0;
+#endif
+ uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0;
uint32_t sysclockfreq = 0;
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ uint32_t prediv2 = 0, pll2mul = 0;
+#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
{
- case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
break;
}
- case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
{
- prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
+#if defined(RCC_CFGR2_PREDIV1)
+ prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
+#else
+ prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
+#endif /*RCC_CFGR2_PREDIV1*/
+#if defined(RCC_CFGR2_PREDIV1SRC)
+
+ if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
+ {
+ /* PLL2 selected as Prediv1 source */
+ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
+ pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
+ pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul);
+ }
+ else
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
+ pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
+ }
+
+ /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
+ /* In this case need to divide pllclk by 2 */
+ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
+ {
+ pllclk = pllclk / 2;
+ }
+#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
- pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
+ pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
+#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
@@ -873,8 +1036,8 @@
sysclockfreq = pllclk;
break;
}
- case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
- default: /* HSI used as system clock */
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
break;
@@ -894,7 +1057,6 @@
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
return SystemCoreClock;
}
@@ -907,7 +1069,7 @@
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
}
/**
@@ -919,17 +1081,17 @@
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
}
/**
* @brief Configures the RCC_OscInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
* will be configured.
* @retval None
*/
-__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Check the parameters */
assert_param(RCC_OscInitStruct != NULL);
@@ -937,7 +1099,12 @@
/* Set all possible values for the Oscillator type parameter ---------------*/
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
| RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-
+
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ /* Get the Prediv1 source --------------------------------------------------*/
+ RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
+#endif /* RCC_CFGR2_PREDIV1SRC */
+
/* Get the HSE configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
{
@@ -951,7 +1118,6 @@
{
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
}
-
RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
/* Get the HSI configuration -----------------------------------------------*/
@@ -990,6 +1156,7 @@
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
}
+
/* Get the PLL configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
{
@@ -1001,17 +1168,30 @@
}
RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
+#if defined(RCC_CR_PLL2ON)
+ /* Get the PLL2 configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
+ {
+ RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
+ }
+ RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
+ RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
+#endif /* RCC_CR_PLL2ON */
}
/**
- * @brief Configures the RCC_ClkInitStruct according to the internal
+ * @brief Get the RCC_ClkInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
- * will be configured.
- * @param pFLatency: Pointer on the Flash Latency.
+ * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
+ * contains the current clock configuration.
+ * @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
-__weak void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
/* Check the parameters */
assert_param(RCC_ClkInitStruct != NULL);
@@ -1032,8 +1212,13 @@
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
+#if defined(FLASH_ACR_LATENCY)
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+#else
/* For VALUE lines devices, only LATENCY_0 can be set*/
*pFLatency = (uint32_t)FLASH_LATENCY_0;
+#endif
}
/**