mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

Dependents: IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.h@113:b3775bf36a83, 2016-04-19 (annotated)

Committer:: mbed_official
Date:: Tue Apr 19 11:15:15 2016 +0100
Revision:: 113:b3775bf36a83
Parent:: 0:9b334a45a8ff

Synchronized with git revision 896981126b34b6d9441e3eea77881c67a1ae3dbd

Full URL: https://github.com/mbedmicro/mbed/commit/896981126b34b6d9441e3eea77881c67a1ae3dbd/

Exporter tool addition for e2 studio

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l0xx_hal_tim.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	113:b3775bf36a83	5	* @version V1.5.0
mbed_official	113:b3775bf36a83	6	* @date 8-January-2016
bogdanm	0:9b334a45a8ff	7	* @brief Header file of TIM HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
mbed_official	113:b3775bf36a83	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32L0xx_HAL_TIM_H
bogdanm	0:9b334a45a8ff	40	#define __STM32L0xx_HAL_TIM_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32l0xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @defgroup TIM TIM (Timer)
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58
bogdanm	0:9b334a45a8ff	59	/** @defgroup TIM_Exported_Types TIM Exported Types
bogdanm	0:9b334a45a8ff	60	* @{
bogdanm	0:9b334a45a8ff	61	*/
bogdanm	0:9b334a45a8ff	62
bogdanm	0:9b334a45a8ff	63	/** @defgroup TIM_Base_Configuration TIM base configuration structure
bogdanm	0:9b334a45a8ff	64	* @{
bogdanm	0:9b334a45a8ff	65	*/
bogdanm	0:9b334a45a8ff	66	/**
bogdanm	0:9b334a45a8ff	67	* @brief TIM Time base Configuration Structure definition
bogdanm	0:9b334a45a8ff	68	*/
bogdanm	0:9b334a45a8ff	69	typedef struct
bogdanm	0:9b334a45a8ff	70	{
bogdanm	0:9b334a45a8ff	71	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm	0:9b334a45a8ff	72	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	73
bogdanm	0:9b334a45a8ff	74	uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm	0:9b334a45a8ff	75	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	0:9b334a45a8ff	76
bogdanm	0:9b334a45a8ff	77	uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm	0:9b334a45a8ff	78	Auto-Reload Register at the next update event.
bogdanm	0:9b334a45a8ff	79	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm	0:9b334a45a8ff	80
bogdanm	0:9b334a45a8ff	81	uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm	0:9b334a45a8ff	82	This parameter can be a value of @ref TIM_ClockDivision */
bogdanm	0:9b334a45a8ff	83	} TIM_Base_InitTypeDef;
bogdanm	0:9b334a45a8ff	84	/**
bogdanm	0:9b334a45a8ff	85	* @}
bogdanm	0:9b334a45a8ff	86	*/
bogdanm	0:9b334a45a8ff	87
bogdanm	0:9b334a45a8ff	88	/** @defgroup TIM_Output_Configuration TIM output compare configuration structure
bogdanm	0:9b334a45a8ff	89	* @{
bogdanm	0:9b334a45a8ff	90	*/
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	/**
bogdanm	0:9b334a45a8ff	93	* @brief TIM Output Compare Configuration Structure definition
bogdanm	0:9b334a45a8ff	94	*/
bogdanm	0:9b334a45a8ff	95
bogdanm	0:9b334a45a8ff	96	typedef struct
bogdanm	0:9b334a45a8ff	97	{
bogdanm	0:9b334a45a8ff	98	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	0:9b334a45a8ff	99	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	102	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	0:9b334a45a8ff	105	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	0:9b334a45a8ff	106
bogdanm	0:9b334a45a8ff	107	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm	0:9b334a45a8ff	108	This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm	0:9b334a45a8ff	109	@note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111	} TIM_OC_InitTypeDef;
bogdanm	0:9b334a45a8ff	112	/**
bogdanm	0:9b334a45a8ff	113	* @}
bogdanm	0:9b334a45a8ff	114	*/
bogdanm	0:9b334a45a8ff	115
bogdanm	0:9b334a45a8ff	116	/** @defgroup TIM_OnePulse_Configuration TIM One Pulse configuration structure
bogdanm	0:9b334a45a8ff	117	* @{
bogdanm	0:9b334a45a8ff	118	*/
bogdanm	0:9b334a45a8ff	119	/**
bogdanm	0:9b334a45a8ff	120	* @brief TIM One Pulse Mode Configuration Structure definition
bogdanm	0:9b334a45a8ff	121	*/
bogdanm	0:9b334a45a8ff	122	typedef struct
bogdanm	0:9b334a45a8ff	123	{
bogdanm	0:9b334a45a8ff	124	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	0:9b334a45a8ff	125	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	0:9b334a45a8ff	126
bogdanm	0:9b334a45a8ff	127	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	128	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	129
bogdanm	0:9b334a45a8ff	130	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	0:9b334a45a8ff	131	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	135	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	136
bogdanm	0:9b334a45a8ff	137	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	138	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	141	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	142	} TIM_OnePulse_InitTypeDef;
bogdanm	0:9b334a45a8ff	143	/**
bogdanm	0:9b334a45a8ff	144	* @}
bogdanm	0:9b334a45a8ff	145	*/
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	/** @defgroup TIM_Input_Capture TIM input capture configuration structure
bogdanm	0:9b334a45a8ff	148	* @{
bogdanm	0:9b334a45a8ff	149	*/
bogdanm	0:9b334a45a8ff	150	/**
bogdanm	0:9b334a45a8ff	151	* @brief TIM Input Capture Configuration Structure definition
bogdanm	0:9b334a45a8ff	152	*/
bogdanm	0:9b334a45a8ff	153
bogdanm	0:9b334a45a8ff	154	typedef struct
bogdanm	0:9b334a45a8ff	155	{
bogdanm	0:9b334a45a8ff	156	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	157	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	160	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	163	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	164
bogdanm	0:9b334a45a8ff	165	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	166	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	167	} TIM_IC_InitTypeDef;
bogdanm	0:9b334a45a8ff	168	/**
bogdanm	0:9b334a45a8ff	169	* @}
bogdanm	0:9b334a45a8ff	170	*/
bogdanm	0:9b334a45a8ff	171
bogdanm	0:9b334a45a8ff	172	/** @defgroup TIM_Encoder TIM encoder configuration structure
bogdanm	0:9b334a45a8ff	173	* @{
bogdanm	0:9b334a45a8ff	174	*/
bogdanm	0:9b334a45a8ff	175	/**
bogdanm	0:9b334a45a8ff	176	* @brief TIM Encoder Configuration Structure definition
bogdanm	0:9b334a45a8ff	177	*/
bogdanm	0:9b334a45a8ff	178
bogdanm	0:9b334a45a8ff	179	typedef struct
bogdanm	0:9b334a45a8ff	180	{
bogdanm	0:9b334a45a8ff	181	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	182	This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	185	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	186
bogdanm	0:9b334a45a8ff	187	uint32_t IC1Selection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	188	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	189
bogdanm	0:9b334a45a8ff	190	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	191	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	194	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	197	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	198
bogdanm	0:9b334a45a8ff	199	uint32_t IC2Selection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	200	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	203	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	204
bogdanm	0:9b334a45a8ff	205	uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	206	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	207	} TIM_Encoder_InitTypeDef;
bogdanm	0:9b334a45a8ff	208	/**
bogdanm	0:9b334a45a8ff	209	* @}
bogdanm	0:9b334a45a8ff	210	*/
bogdanm	0:9b334a45a8ff	211
bogdanm	0:9b334a45a8ff	212	/** @defgroup TIM_Clock_Configuration TIM clock configuration structure
bogdanm	0:9b334a45a8ff	213	* @{
bogdanm	0:9b334a45a8ff	214	*/
bogdanm	0:9b334a45a8ff	215	/**
bogdanm	0:9b334a45a8ff	216	* @brief Clock Configuration Handle Structure definition
bogdanm	0:9b334a45a8ff	217	*/
bogdanm	0:9b334a45a8ff	218	typedef struct
bogdanm	0:9b334a45a8ff	219	{
bogdanm	0:9b334a45a8ff	220	uint32_t ClockSource; /*!< TIM clock sources.
bogdanm	0:9b334a45a8ff	221	This parameter can be a value of @ref TIM_Clock_Source */
bogdanm	0:9b334a45a8ff	222	uint32_t ClockPolarity; /*!< TIM clock polarity.
bogdanm	0:9b334a45a8ff	223	This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm	0:9b334a45a8ff	224	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
bogdanm	0:9b334a45a8ff	225	This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm	0:9b334a45a8ff	226	uint32_t ClockFilter; /*!< TIM clock filter.
bogdanm	0:9b334a45a8ff	227	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	228	}TIM_ClockConfigTypeDef;
bogdanm	0:9b334a45a8ff	229	/**
bogdanm	0:9b334a45a8ff	230	* @}
bogdanm	0:9b334a45a8ff	231	*/
bogdanm	0:9b334a45a8ff	232
bogdanm	0:9b334a45a8ff	233	/** @defgroup TIM_Clear_Input_Configuration TIM clear input configuration structure
bogdanm	0:9b334a45a8ff	234	* @{
bogdanm	0:9b334a45a8ff	235	*/
bogdanm	0:9b334a45a8ff	236	/**
bogdanm	0:9b334a45a8ff	237	* @brief Clear Input Configuration Handle Structure definition
bogdanm	0:9b334a45a8ff	238	*/
bogdanm	0:9b334a45a8ff	239	typedef struct
bogdanm	0:9b334a45a8ff	240	{
bogdanm	0:9b334a45a8ff	241	uint32_t ClearInputState; /*!< TIM clear Input state.
bogdanm	0:9b334a45a8ff	242	This parameter can be ENABLE or DISABLE */
bogdanm	0:9b334a45a8ff	243	uint32_t ClearInputSource; /*!< TIM clear Input sources.
bogdanm	0:9b334a45a8ff	244	This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm	0:9b334a45a8ff	245	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
bogdanm	0:9b334a45a8ff	246	This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm	0:9b334a45a8ff	247	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
bogdanm	0:9b334a45a8ff	248	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm	0:9b334a45a8ff	249	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
bogdanm	0:9b334a45a8ff	250	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	251	}TIM_ClearInputConfigTypeDef;
bogdanm	0:9b334a45a8ff	252	/**
bogdanm	0:9b334a45a8ff	253	* @}
bogdanm	0:9b334a45a8ff	254	*/
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	/** @defgroup TIM_Slave_Configuratio TIM slave configuration structure
bogdanm	0:9b334a45a8ff	257	* @{
bogdanm	0:9b334a45a8ff	258	*/
bogdanm	0:9b334a45a8ff	259	/**
bogdanm	0:9b334a45a8ff	260	* @brief TIM Slave configuration Structure definition
bogdanm	0:9b334a45a8ff	261	*/
bogdanm	0:9b334a45a8ff	262	typedef struct {
bogdanm	0:9b334a45a8ff	263	uint32_t SlaveMode; /*!< Slave mode selection.
bogdanm	0:9b334a45a8ff	264	This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm	0:9b334a45a8ff	265	uint32_t InputTrigger; /*!< Input Trigger source.
bogdanm	0:9b334a45a8ff	266	This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm	0:9b334a45a8ff	267	uint32_t TriggerPolarity; /*!< Input Trigger polarity.
bogdanm	0:9b334a45a8ff	268	This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm	0:9b334a45a8ff	269	uint32_t TriggerPrescaler; /*!< Input trigger prescaler.
bogdanm	0:9b334a45a8ff	270	This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm	0:9b334a45a8ff	271	uint32_t TriggerFilter; /*!< Input trigger filter.
bogdanm	0:9b334a45a8ff	272	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	273
bogdanm	0:9b334a45a8ff	274	}TIM_SlaveConfigTypeDef;
bogdanm	0:9b334a45a8ff	275	/**
bogdanm	0:9b334a45a8ff	276	* @}
bogdanm	0:9b334a45a8ff	277	*/
bogdanm	0:9b334a45a8ff	278
bogdanm	0:9b334a45a8ff	279	/** @defgroup TIM_State_Definition TIM state definition
bogdanm	0:9b334a45a8ff	280	* @{
bogdanm	0:9b334a45a8ff	281	*/
bogdanm	0:9b334a45a8ff	282	/**
bogdanm	0:9b334a45a8ff	283	* @brief HAL State structures definition
bogdanm	0:9b334a45a8ff	284	*/
bogdanm	0:9b334a45a8ff	285	typedef enum
bogdanm	0:9b334a45a8ff	286	{
bogdanm	0:9b334a45a8ff	287	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
bogdanm	0:9b334a45a8ff	288	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	0:9b334a45a8ff	289	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
bogdanm	0:9b334a45a8ff	290	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	0:9b334a45a8ff	291	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
bogdanm	0:9b334a45a8ff	292	}HAL_TIM_StateTypeDef;
bogdanm	0:9b334a45a8ff	293	/**
bogdanm	0:9b334a45a8ff	294	* @}
bogdanm	0:9b334a45a8ff	295	*/
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/** @defgroup TIM_Active_Channel TIM active channel definition
bogdanm	0:9b334a45a8ff	298	* @{
bogdanm	0:9b334a45a8ff	299	*/
bogdanm	0:9b334a45a8ff	300	/**
bogdanm	0:9b334a45a8ff	301	* @brief HAL Active channel structures definition
bogdanm	0:9b334a45a8ff	302	*/
bogdanm	0:9b334a45a8ff	303	typedef enum
bogdanm	0:9b334a45a8ff	304	{
bogdanm	0:9b334a45a8ff	305	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
bogdanm	0:9b334a45a8ff	306	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
bogdanm	0:9b334a45a8ff	307	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
bogdanm	0:9b334a45a8ff	308	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
bogdanm	0:9b334a45a8ff	309	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
bogdanm	0:9b334a45a8ff	310	}HAL_TIM_ActiveChannel;
bogdanm	0:9b334a45a8ff	311	/**
bogdanm	0:9b334a45a8ff	312	* @}
bogdanm	0:9b334a45a8ff	313	*/
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	/** @defgroup TIM_Handle TIM handler
bogdanm	0:9b334a45a8ff	316	* @{
bogdanm	0:9b334a45a8ff	317	*/
bogdanm	0:9b334a45a8ff	318	/**
bogdanm	0:9b334a45a8ff	319	* @brief TIM Time Base Handle Structure definition
bogdanm	0:9b334a45a8ff	320	*/
bogdanm	0:9b334a45a8ff	321	typedef struct
bogdanm	0:9b334a45a8ff	322	{
bogdanm	0:9b334a45a8ff	323	TIM_TypeDef Instance; /!< Register base address */
bogdanm	0:9b334a45a8ff	324	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
bogdanm	0:9b334a45a8ff	325	HAL_TIM_ActiveChannel Channel; /!< Active channel /
bogdanm	0:9b334a45a8ff	326	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
bogdanm	0:9b334a45a8ff	327	This array is accessed by a @ref DMA_Handle_index */
bogdanm	0:9b334a45a8ff	328	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	0:9b334a45a8ff	329	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
bogdanm	0:9b334a45a8ff	330	}TIM_HandleTypeDef;
bogdanm	0:9b334a45a8ff	331	/**
bogdanm	0:9b334a45a8ff	332	* @}
bogdanm	0:9b334a45a8ff	333	*/
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	/**
bogdanm	0:9b334a45a8ff	336	* @}
bogdanm	0:9b334a45a8ff	337	*/
bogdanm	0:9b334a45a8ff	338	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	339	/** @defgroup TIM_Exported_Constants TIM Exported Constants
bogdanm	0:9b334a45a8ff	340	* @{
bogdanm	0:9b334a45a8ff	341	*/
bogdanm	0:9b334a45a8ff	342
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	#define IS_TIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0xFFFF)
bogdanm	0:9b334a45a8ff	345
bogdanm	0:9b334a45a8ff	346	#define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFF)
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348
bogdanm	0:9b334a45a8ff	349	/** @defgroup TIM_Input_Channel_Polarity Input channel polarity
bogdanm	0:9b334a45a8ff	350	* @{
bogdanm	0:9b334a45a8ff	351	*/
bogdanm	0:9b334a45a8ff	352	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	353	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	354	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	355	/**
bogdanm	0:9b334a45a8ff	356	* @}
bogdanm	0:9b334a45a8ff	357	*/
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	/** @defgroup TIM_ETR_Polarity ETR polarity
bogdanm	0:9b334a45a8ff	360	* @{
bogdanm	0:9b334a45a8ff	361	*/
bogdanm	0:9b334a45a8ff	362	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
bogdanm	0:9b334a45a8ff	363	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
bogdanm	0:9b334a45a8ff	364	/**
bogdanm	0:9b334a45a8ff	365	* @}
bogdanm	0:9b334a45a8ff	366	*/
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/** @defgroup TIM_ETR_Prescaler ETR prescaler
bogdanm	0:9b334a45a8ff	369	* @{
bogdanm	0:9b334a45a8ff	370	*/
bogdanm	0:9b334a45a8ff	371	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	372	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
bogdanm	0:9b334a45a8ff	373	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
bogdanm	0:9b334a45a8ff	374	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
bogdanm	0:9b334a45a8ff	375	/**
bogdanm	0:9b334a45a8ff	376	* @}
bogdanm	0:9b334a45a8ff	377	*/
bogdanm	0:9b334a45a8ff	378
bogdanm	0:9b334a45a8ff	379	/** @defgroup TIM_Counter_Mode Counter mode
bogdanm	0:9b334a45a8ff	380	* @{
bogdanm	0:9b334a45a8ff	381	*/
bogdanm	0:9b334a45a8ff	382	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	383	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm	0:9b334a45a8ff	384	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm	0:9b334a45a8ff	385	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm	0:9b334a45a8ff	386	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm	0:9b334a45a8ff	387	/**
bogdanm	0:9b334a45a8ff	388	* @}
bogdanm	0:9b334a45a8ff	389	*/
bogdanm	0:9b334a45a8ff	390	#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) \|\| \
bogdanm	0:9b334a45a8ff	391	((__MODE__) == TIM_COUNTERMODE_DOWN) \|\| \
bogdanm	0:9b334a45a8ff	392	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
bogdanm	0:9b334a45a8ff	393	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
bogdanm	0:9b334a45a8ff	394	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm	0:9b334a45a8ff	395
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397
bogdanm	0:9b334a45a8ff	398
bogdanm	0:9b334a45a8ff	399	/** @defgroup TIM_ClockDivision Clock division
bogdanm	0:9b334a45a8ff	400	* @{
bogdanm	0:9b334a45a8ff	401	*/
bogdanm	0:9b334a45a8ff	402	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	403	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm	0:9b334a45a8ff	404	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm	0:9b334a45a8ff	405	/**
bogdanm	0:9b334a45a8ff	406	* @}
bogdanm	0:9b334a45a8ff	407	*/
bogdanm	0:9b334a45a8ff	408	#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	409	((__DIV__) == TIM_CLOCKDIVISION_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	410	((__DIV__) == TIM_CLOCKDIVISION_DIV4))
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412
bogdanm	0:9b334a45a8ff	413	/** @defgroup TIM_Output_Compare_and_PWM_modes Output compare and PWM modes
bogdanm	0:9b334a45a8ff	414	* @{
bogdanm	0:9b334a45a8ff	415	*/
bogdanm	0:9b334a45a8ff	416	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	417	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	418	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	419	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	420	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	421	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm	0:9b334a45a8ff	422	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	423	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	424	/**
bogdanm	0:9b334a45a8ff	425	* @}
bogdanm	0:9b334a45a8ff	426	*/
bogdanm	0:9b334a45a8ff	427
bogdanm	0:9b334a45a8ff	428	#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) \|\| \
bogdanm	0:9b334a45a8ff	429	((__MODE__) == TIM_OCMODE_PWM2))
bogdanm	0:9b334a45a8ff	430
bogdanm	0:9b334a45a8ff	431	#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) \|\| \
bogdanm	0:9b334a45a8ff	432	((__MODE__) == TIM_OCMODE_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	433	((__MODE__) == TIM_OCMODE_INACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	434	((__MODE__) == TIM_OCMODE_TOGGLE) \|\| \
bogdanm	0:9b334a45a8ff	435	((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	436	((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
bogdanm	0:9b334a45a8ff	437
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	/** @defgroup TIM_Output_Compare_State Output compare state
bogdanm	0:9b334a45a8ff	440	* @{
bogdanm	0:9b334a45a8ff	441	*/
bogdanm	0:9b334a45a8ff	442	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	443	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm	0:9b334a45a8ff	444	/**
bogdanm	0:9b334a45a8ff	445	* @}
bogdanm	0:9b334a45a8ff	446	*/
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448	/** @defgroup TIM_Output_Fast_State Output fast state
bogdanm	0:9b334a45a8ff	449	* @{
bogdanm	0:9b334a45a8ff	450	*/
bogdanm	0:9b334a45a8ff	451	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	452	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm	0:9b334a45a8ff	453	/**
bogdanm	0:9b334a45a8ff	454	* @}
bogdanm	0:9b334a45a8ff	455	*/
bogdanm	0:9b334a45a8ff	456	#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	457	((__STATE__) == TIM_OCFAST_ENABLE))
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	/** @defgroup TIM_Output_Compare_N_State Output compare N state
bogdanm	0:9b334a45a8ff	460	* @{
bogdanm	0:9b334a45a8ff	461	*/
bogdanm	0:9b334a45a8ff	462	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	463	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm	0:9b334a45a8ff	464	/**
bogdanm	0:9b334a45a8ff	465	* @}
bogdanm	0:9b334a45a8ff	466	*/
bogdanm	0:9b334a45a8ff	467
bogdanm	0:9b334a45a8ff	468	/** @defgroup TIM_Output_Compare_Polarity Output compare polarity
bogdanm	0:9b334a45a8ff	469	* @{
bogdanm	0:9b334a45a8ff	470	*/
bogdanm	0:9b334a45a8ff	471	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	472	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm	0:9b334a45a8ff	473	/**
bogdanm	0:9b334a45a8ff	474	* @}
bogdanm	0:9b334a45a8ff	475	*/
bogdanm	0:9b334a45a8ff	476	#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	477	((__POLARITY__) == TIM_OCPOLARITY_LOW))
bogdanm	0:9b334a45a8ff	478
bogdanm	0:9b334a45a8ff	479	/** @defgroup TIM_Channel TIM channels
bogdanm	0:9b334a45a8ff	480	* @{
bogdanm	0:9b334a45a8ff	481	*/
bogdanm	0:9b334a45a8ff	482	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	483	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	484	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm	0:9b334a45a8ff	485	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm	0:9b334a45a8ff	486	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm	0:9b334a45a8ff	487	/**
bogdanm	0:9b334a45a8ff	488	* @}
bogdanm	0:9b334a45a8ff	489	*/
bogdanm	0:9b334a45a8ff	490
bogdanm	0:9b334a45a8ff	491	#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	492	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	493	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	494	((__CHANNEL__) == TIM_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	495	((__CHANNEL__) == TIM_CHANNEL_ALL))
bogdanm	0:9b334a45a8ff	496
bogdanm	0:9b334a45a8ff	497	#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	498	((__CHANNEL__) == TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	499
bogdanm	0:9b334a45a8ff	500
bogdanm	0:9b334a45a8ff	501	/** @defgroup TIM_Input_Capture_Polarity Input capture polarity
bogdanm	0:9b334a45a8ff	502	* @{
bogdanm	0:9b334a45a8ff	503	*/
bogdanm	0:9b334a45a8ff	504	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm	0:9b334a45a8ff	505	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm	0:9b334a45a8ff	506	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm	0:9b334a45a8ff	507	/**
bogdanm	0:9b334a45a8ff	508	* @}
bogdanm	0:9b334a45a8ff	509	*/
bogdanm	0:9b334a45a8ff	510	#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	511	((__POLARITY__) == TIM_ICPOLARITY_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	512	((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm	0:9b334a45a8ff	513
bogdanm	0:9b334a45a8ff	514
bogdanm	0:9b334a45a8ff	515	/** @defgroup TIM_Input_Capture_Selection Input capture selection
bogdanm	0:9b334a45a8ff	516	* @{
bogdanm	0:9b334a45a8ff	517	*/
bogdanm	0:9b334a45a8ff	518	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	0:9b334a45a8ff	519	connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm	0:9b334a45a8ff	520	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	0:9b334a45a8ff	521	connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm	0:9b334a45a8ff	522	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
bogdanm	0:9b334a45a8ff	523
bogdanm	0:9b334a45a8ff	524	#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) \|\| \
bogdanm	0:9b334a45a8ff	525	((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) \|\| \
bogdanm	0:9b334a45a8ff	526	((__SELECTION__) == TIM_ICSELECTION_TRC))
bogdanm	0:9b334a45a8ff	527	/**
bogdanm	0:9b334a45a8ff	528	* @}
bogdanm	0:9b334a45a8ff	529	*/
bogdanm	0:9b334a45a8ff	530
bogdanm	0:9b334a45a8ff	531	/** @defgroup TIM_Input_Capture_Prescaler Input capture prescaler
bogdanm	0:9b334a45a8ff	532	* @{
bogdanm	0:9b334a45a8ff	533	*/
bogdanm	0:9b334a45a8ff	534	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
bogdanm	0:9b334a45a8ff	535	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
bogdanm	0:9b334a45a8ff	536	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
bogdanm	0:9b334a45a8ff	537	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
bogdanm	0:9b334a45a8ff	538	/**
bogdanm	0:9b334a45a8ff	539	* @}
bogdanm	0:9b334a45a8ff	540	*/
bogdanm	0:9b334a45a8ff	541	#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	542	((__PRESCALER__) == TIM_ICPSC_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	543	((__PRESCALER__) == TIM_ICPSC_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	544	((__PRESCALER__) == TIM_ICPSC_DIV8))
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	/** @defgroup TIM_One_Pulse_Mode One pulse mode
bogdanm	0:9b334a45a8ff	547	* @{
bogdanm	0:9b334a45a8ff	548	*/
bogdanm	0:9b334a45a8ff	549	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm	0:9b334a45a8ff	550	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	551	/**
bogdanm	0:9b334a45a8ff	552	* @}
bogdanm	0:9b334a45a8ff	553	*/
bogdanm	0:9b334a45a8ff	554	#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) \|\| \
bogdanm	0:9b334a45a8ff	555	((__MODE__) == TIM_OPMODE_REPETITIVE))
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	/** @defgroup TIM_Encoder_Mode Encoder_Mode
bogdanm	0:9b334a45a8ff	558	* @{
bogdanm	0:9b334a45a8ff	559	*/
bogdanm	0:9b334a45a8ff	560	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm	0:9b334a45a8ff	561	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm	0:9b334a45a8ff	562	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
bogdanm	0:9b334a45a8ff	563	/**
bogdanm	0:9b334a45a8ff	564	* @}
bogdanm	0:9b334a45a8ff	565	*/
bogdanm	0:9b334a45a8ff	566	#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) \|\| \
bogdanm	0:9b334a45a8ff	567	((__MODE__) == TIM_ENCODERMODE_TI2) \|\| \
bogdanm	0:9b334a45a8ff	568	((__MODE__) == TIM_ENCODERMODE_TI12))
bogdanm	0:9b334a45a8ff	569
bogdanm	0:9b334a45a8ff	570	/** @defgroup TIM_Interrupt_definition Interrupt definition
bogdanm	0:9b334a45a8ff	571	* @{
bogdanm	0:9b334a45a8ff	572	*/
bogdanm	0:9b334a45a8ff	573	#define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm	0:9b334a45a8ff	574	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm	0:9b334a45a8ff	575	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm	0:9b334a45a8ff	576	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm	0:9b334a45a8ff	577	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm	0:9b334a45a8ff	578	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm	0:9b334a45a8ff	579	/**
bogdanm	0:9b334a45a8ff	580	* @}
bogdanm	0:9b334a45a8ff	581	*/
bogdanm	0:9b334a45a8ff	582
bogdanm	0:9b334a45a8ff	583	/** @defgroup TIM_DMA_sources DMA sources
bogdanm	0:9b334a45a8ff	584	* @{
bogdanm	0:9b334a45a8ff	585	*/
bogdanm	0:9b334a45a8ff	586	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm	0:9b334a45a8ff	587	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm	0:9b334a45a8ff	588	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm	0:9b334a45a8ff	589	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm	0:9b334a45a8ff	590	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm	0:9b334a45a8ff	591	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm	0:9b334a45a8ff	592	/**
bogdanm	0:9b334a45a8ff	593	* @}
bogdanm	0:9b334a45a8ff	594	*/
bogdanm	0:9b334a45a8ff	595	#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
bogdanm	0:9b334a45a8ff	596
bogdanm	0:9b334a45a8ff	597
bogdanm	0:9b334a45a8ff	598
bogdanm	0:9b334a45a8ff	599	/** @defgroup TIM_Event_Source Event sources
bogdanm	0:9b334a45a8ff	600	* @{
bogdanm	0:9b334a45a8ff	601	*/
bogdanm	0:9b334a45a8ff	602	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
bogdanm	0:9b334a45a8ff	603	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
bogdanm	0:9b334a45a8ff	604	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
bogdanm	0:9b334a45a8ff	605	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
bogdanm	0:9b334a45a8ff	606	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
bogdanm	0:9b334a45a8ff	607	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
bogdanm	0:9b334a45a8ff	608	/**
bogdanm	0:9b334a45a8ff	609	* @}
bogdanm	0:9b334a45a8ff	610	*/
bogdanm	0:9b334a45a8ff	611	#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0) == 0x00000000) && ((__SOURCE__) != 0x00000000))
bogdanm	0:9b334a45a8ff	612
bogdanm	0:9b334a45a8ff	613
bogdanm	0:9b334a45a8ff	614	/** @defgroup TIM_Flag_definition Flag definition
bogdanm	0:9b334a45a8ff	615	* @{
bogdanm	0:9b334a45a8ff	616	*/
bogdanm	0:9b334a45a8ff	617	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm	0:9b334a45a8ff	618	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm	0:9b334a45a8ff	619	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm	0:9b334a45a8ff	620	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm	0:9b334a45a8ff	621	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm	0:9b334a45a8ff	622	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm	0:9b334a45a8ff	623	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm	0:9b334a45a8ff	624	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm	0:9b334a45a8ff	625	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm	0:9b334a45a8ff	626	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm	0:9b334a45a8ff	627	/**
bogdanm	0:9b334a45a8ff	628	* @}
bogdanm	0:9b334a45a8ff	629	*/
bogdanm	0:9b334a45a8ff	630
bogdanm	0:9b334a45a8ff	631	/** @defgroup TIM_Clock_Source Clock source
bogdanm	0:9b334a45a8ff	632	* @{
bogdanm	0:9b334a45a8ff	633	*/
bogdanm	0:9b334a45a8ff	634	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm	0:9b334a45a8ff	635	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm	0:9b334a45a8ff	636	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	637	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm	0:9b334a45a8ff	638	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm	0:9b334a45a8ff	639	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
bogdanm	0:9b334a45a8ff	640	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	641	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	642	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	643	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm	0:9b334a45a8ff	644	/**
bogdanm	0:9b334a45a8ff	645	* @}
bogdanm	0:9b334a45a8ff	646	*/
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
bogdanm	0:9b334a45a8ff	649	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
bogdanm	0:9b334a45a8ff	650	((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	651	((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	652	((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	653	((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	654	((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) \|\| \
bogdanm	0:9b334a45a8ff	655	((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \|\| \
bogdanm	0:9b334a45a8ff	656	((__CLOCK__) == TIM_CLOCKSOURCE_TI2) \|\| \
bogdanm	0:9b334a45a8ff	657	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm	0:9b334a45a8ff	658
bogdanm	0:9b334a45a8ff	659
bogdanm	0:9b334a45a8ff	660	/** @defgroup TIM_Clock_Polarity Clock polarity
bogdanm	0:9b334a45a8ff	661	* @{
bogdanm	0:9b334a45a8ff	662	*/
bogdanm	0:9b334a45a8ff	663	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
bogdanm	0:9b334a45a8ff	664	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
bogdanm	0:9b334a45a8ff	665	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	666	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	667	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	668	/**
bogdanm	0:9b334a45a8ff	669	* @}
bogdanm	0:9b334a45a8ff	670	*/
bogdanm	0:9b334a45a8ff	671	#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
bogdanm	0:9b334a45a8ff	672	((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
bogdanm	0:9b334a45a8ff	673	((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	674	((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	675	((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm	0:9b334a45a8ff	676
bogdanm	0:9b334a45a8ff	677	/** @defgroup TIM_Clock_Prescaler Clock prescaler
bogdanm	0:9b334a45a8ff	678	* @{
bogdanm	0:9b334a45a8ff	679	*/
bogdanm	0:9b334a45a8ff	680	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	681	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	682	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	683	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	684	/**
bogdanm	0:9b334a45a8ff	685	* @}
bogdanm	0:9b334a45a8ff	686	*/
bogdanm	0:9b334a45a8ff	687	#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	688	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	689	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	690	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692
bogdanm	0:9b334a45a8ff	693	/* Check clock filter */
bogdanm	0:9b334a45a8ff	694	#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	/** @defgroup TIM_ClearInput_Source Clear input source
bogdanm	0:9b334a45a8ff	697	* @{
bogdanm	0:9b334a45a8ff	698	*/
bogdanm	0:9b334a45a8ff	699	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	700	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	701	/**
bogdanm	0:9b334a45a8ff	702	* @}
bogdanm	0:9b334a45a8ff	703	*/
bogdanm	0:9b334a45a8ff	704
bogdanm	0:9b334a45a8ff	705	#define IS_TIM_CLEARINPUT_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	706	((__SOURCE__) == TIM_CLEARINPUTSOURCE_ETR))
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708
bogdanm	0:9b334a45a8ff	709	/** @defgroup TIM_ClearInput_Polarity Clear input polarity
bogdanm	0:9b334a45a8ff	710	* @{
bogdanm	0:9b334a45a8ff	711	*/
bogdanm	0:9b334a45a8ff	712	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
bogdanm	0:9b334a45a8ff	713	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
bogdanm	0:9b334a45a8ff	714	/**
bogdanm	0:9b334a45a8ff	715	* @}
bogdanm	0:9b334a45a8ff	716	*/
bogdanm	0:9b334a45a8ff	717	#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
bogdanm	0:9b334a45a8ff	718	((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm	0:9b334a45a8ff	719
bogdanm	0:9b334a45a8ff	720
bogdanm	0:9b334a45a8ff	721	/** @defgroup TIM_ClearInput_Prescaler Clear input prescaler
bogdanm	0:9b334a45a8ff	722	* @{
bogdanm	0:9b334a45a8ff	723	*/
bogdanm	0:9b334a45a8ff	724	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	725	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	726	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	727	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	728	/**
bogdanm	0:9b334a45a8ff	729	* @}
bogdanm	0:9b334a45a8ff	730	*/
bogdanm	0:9b334a45a8ff	731	#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	732	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	733	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	734	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	735
bogdanm	0:9b334a45a8ff	736
bogdanm	0:9b334a45a8ff	737	/* Check IC filter */
bogdanm	0:9b334a45a8ff	738	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740
bogdanm	0:9b334a45a8ff	741	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
bogdanm	0:9b334a45a8ff	742	* @{
bogdanm	0:9b334a45a8ff	743	*/
bogdanm	0:9b334a45a8ff	744	#define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	745	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm	0:9b334a45a8ff	746	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm	0:9b334a45a8ff	747	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	748	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm	0:9b334a45a8ff	749	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	750	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
bogdanm	0:9b334a45a8ff	751	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	752	/**
bogdanm	0:9b334a45a8ff	753	* @}
bogdanm	0:9b334a45a8ff	754	*/
bogdanm	0:9b334a45a8ff	755	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
bogdanm	0:9b334a45a8ff	756	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	757	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	758	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
bogdanm	0:9b334a45a8ff	759	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
bogdanm	0:9b334a45a8ff	760	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
bogdanm	0:9b334a45a8ff	761	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
bogdanm	0:9b334a45a8ff	762	((__SOURCE__) == TIM_TRGO_OC4REF))
bogdanm	0:9b334a45a8ff	763
bogdanm	0:9b334a45a8ff	764
bogdanm	0:9b334a45a8ff	765
bogdanm	0:9b334a45a8ff	766	/** @defgroup TIM_Slave_Mode Slave mode
bogdanm	0:9b334a45a8ff	767	* @{
bogdanm	0:9b334a45a8ff	768	*/
bogdanm	0:9b334a45a8ff	769	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	770	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	771	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
bogdanm	0:9b334a45a8ff	772	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
bogdanm	0:9b334a45a8ff	773	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
bogdanm	0:9b334a45a8ff	774	/**
bogdanm	0:9b334a45a8ff	775	* @}
bogdanm	0:9b334a45a8ff	776	*/
bogdanm	0:9b334a45a8ff	777	#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	778	((__MODE__) == TIM_SLAVEMODE_GATED) \|\| \
bogdanm	0:9b334a45a8ff	779	((__MODE__) == TIM_SLAVEMODE_RESET) \|\| \
bogdanm	0:9b334a45a8ff	780	((__MODE__) == TIM_SLAVEMODE_TRIGGER) \|\| \
bogdanm	0:9b334a45a8ff	781	((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm	0:9b334a45a8ff	782
bogdanm	0:9b334a45a8ff	783	/** @defgroup TIM_Master_Slave_Mode Master slave mode
bogdanm	0:9b334a45a8ff	784	* @{
bogdanm	0:9b334a45a8ff	785	*/
bogdanm	0:9b334a45a8ff	786
bogdanm	0:9b334a45a8ff	787	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm	0:9b334a45a8ff	788	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	789	/**
bogdanm	0:9b334a45a8ff	790	* @}
bogdanm	0:9b334a45a8ff	791	*/
bogdanm	0:9b334a45a8ff	792	#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	793	((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm	0:9b334a45a8ff	794
bogdanm	0:9b334a45a8ff	795	/** @defgroup TIM_Trigger_Selection Trigger selection
bogdanm	0:9b334a45a8ff	796	* @{
bogdanm	0:9b334a45a8ff	797	*/
bogdanm	0:9b334a45a8ff	798	#define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	799	#define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm	0:9b334a45a8ff	800	#define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm	0:9b334a45a8ff	801	#define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm	0:9b334a45a8ff	802	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm	0:9b334a45a8ff	803	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm	0:9b334a45a8ff	804	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm	0:9b334a45a8ff	805	#define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm	0:9b334a45a8ff	806	#define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm	0:9b334a45a8ff	807	/**
bogdanm	0:9b334a45a8ff	808	* @}
bogdanm	0:9b334a45a8ff	809	*/
bogdanm	0:9b334a45a8ff	810	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	811	((__SELECTION__) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	812	((__SELECTION__) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	813	((__SELECTION__) == TIM_TS_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	814	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
bogdanm	0:9b334a45a8ff	815	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
bogdanm	0:9b334a45a8ff	816	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
bogdanm	0:9b334a45a8ff	817	((__SELECTION__) == TIM_TS_ETRF))
bogdanm	0:9b334a45a8ff	818	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	819	((__SELECTION__) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	820	((__SELECTION__) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	821	((__SELECTION__) == TIM_TS_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	822	((__SELECTION__) == TIM_TS_NONE))
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	/** @defgroup TIM_Trigger_Polarity Trigger polarity
bogdanm	0:9b334a45a8ff	826	* @{
bogdanm	0:9b334a45a8ff	827	*/
bogdanm	0:9b334a45a8ff	828	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
bogdanm	0:9b334a45a8ff	829	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
bogdanm	0:9b334a45a8ff	830	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	831	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	832	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	833	/**
bogdanm	0:9b334a45a8ff	834	* @}
bogdanm	0:9b334a45a8ff	835	*/
bogdanm	0:9b334a45a8ff	836	#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
bogdanm	0:9b334a45a8ff	837	((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
bogdanm	0:9b334a45a8ff	838	((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
bogdanm	0:9b334a45a8ff	839	((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
bogdanm	0:9b334a45a8ff	840	((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm	0:9b334a45a8ff	841
bogdanm	0:9b334a45a8ff	842
bogdanm	0:9b334a45a8ff	843	/** @defgroup TIM_Trigger_Prescaler Trigger prescaler
bogdanm	0:9b334a45a8ff	844	* @{
bogdanm	0:9b334a45a8ff	845	*/
bogdanm	0:9b334a45a8ff	846	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	847	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	848	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	849	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	850	/**
bogdanm	0:9b334a45a8ff	851	* @}
bogdanm	0:9b334a45a8ff	852	*/
bogdanm	0:9b334a45a8ff	853	#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	854	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	855	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	856	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	/* Check trigger filter */
bogdanm	0:9b334a45a8ff	860	#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
bogdanm	0:9b334a45a8ff	861
bogdanm	0:9b334a45a8ff	862
bogdanm	0:9b334a45a8ff	863	/** @defgroup TIM_TI1_Selection TI1 selection
bogdanm	0:9b334a45a8ff	864	* @{
bogdanm	0:9b334a45a8ff	865	*/
bogdanm	0:9b334a45a8ff	866	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	867	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm	0:9b334a45a8ff	868	/**
bogdanm	0:9b334a45a8ff	869	* @}
bogdanm	0:9b334a45a8ff	870	*/
bogdanm	0:9b334a45a8ff	871	#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) \|\| \
bogdanm	0:9b334a45a8ff	872	((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm	0:9b334a45a8ff	873
bogdanm	0:9b334a45a8ff	874
bogdanm	0:9b334a45a8ff	875	/** @defgroup TIM_DMA_Base_address DMA base address
bogdanm	0:9b334a45a8ff	876	* @{
bogdanm	0:9b334a45a8ff	877	*/
bogdanm	0:9b334a45a8ff	878	#define TIM_DMABASE_CR1 (0x00000000)
bogdanm	0:9b334a45a8ff	879	#define TIM_DMABASE_CR2 (0x00000001)
bogdanm	0:9b334a45a8ff	880	#define TIM_DMABASE_SMCR (0x00000002)
bogdanm	0:9b334a45a8ff	881	#define TIM_DMABASE_DIER (0x00000003)
bogdanm	0:9b334a45a8ff	882	#define TIM_DMABASE_SR (0x00000004)
bogdanm	0:9b334a45a8ff	883	#define TIM_DMABASE_EGR (0x00000005)
bogdanm	0:9b334a45a8ff	884	#define TIM_DMABASE_CCMR1 (0x00000006)
bogdanm	0:9b334a45a8ff	885	#define TIM_DMABASE_CCMR2 (0x00000007)
bogdanm	0:9b334a45a8ff	886	#define TIM_DMABASE_CCER (0x00000008)
bogdanm	0:9b334a45a8ff	887	#define TIM_DMABASE_CNT (0x00000009)
bogdanm	0:9b334a45a8ff	888	#define TIM_DMABASE_PSC (0x0000000A)
bogdanm	0:9b334a45a8ff	889	#define TIM_DMABASE_ARR (0x0000000B)
bogdanm	0:9b334a45a8ff	890	#define TIM_DMABASE_CCR1 (0x0000000D)
bogdanm	0:9b334a45a8ff	891	#define TIM_DMABASE_CCR2 (0x0000000E)
bogdanm	0:9b334a45a8ff	892	#define TIM_DMABASE_CCR3 (0x0000000F)
bogdanm	0:9b334a45a8ff	893	#define TIM_DMABASE_CCR4 (0x00000010)
bogdanm	0:9b334a45a8ff	894	#define TIM_DMABASE_DCR (0x00000012)
bogdanm	0:9b334a45a8ff	895	#define TIM_DMABASE_OR (0x00000013)
bogdanm	0:9b334a45a8ff	896	/**
bogdanm	0:9b334a45a8ff	897	* @}
bogdanm	0:9b334a45a8ff	898	*/
bogdanm	0:9b334a45a8ff	899	#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) \|\| \
bogdanm	0:9b334a45a8ff	900	((__BASE__) == TIM_DMABASE_CR2) \|\| \
bogdanm	0:9b334a45a8ff	901	((__BASE__) == TIM_DMABASE_SMCR) \|\| \
bogdanm	0:9b334a45a8ff	902	((__BASE__) == TIM_DMABASE_DIER) \|\| \
bogdanm	0:9b334a45a8ff	903	((__BASE__) == TIM_DMABASE_SR) \|\| \
bogdanm	0:9b334a45a8ff	904	((__BASE__) == TIM_DMABASE_EGR) \|\| \
bogdanm	0:9b334a45a8ff	905	((__BASE__) == TIM_DMABASE_CCMR1) \|\| \
bogdanm	0:9b334a45a8ff	906	((__BASE__) == TIM_DMABASE_CCMR2 ) \|\| \
bogdanm	0:9b334a45a8ff	907	((__BASE__) == TIM_DMABASE_CCER) \|\| \
bogdanm	0:9b334a45a8ff	908	((__BASE__) == TIM_DMABASE_CNT) \|\| \
bogdanm	0:9b334a45a8ff	909	((__BASE__) == TIM_DMABASE_PSC) \|\| \
bogdanm	0:9b334a45a8ff	910	((__BASE__) == TIM_DMABASE_ARR) \|\| \
bogdanm	0:9b334a45a8ff	911	((__BASE__) == TIM_DMABASE_CCR1) \|\| \
bogdanm	0:9b334a45a8ff	912	((__BASE__) == TIM_DMABASE_CCR2) \|\| \
bogdanm	0:9b334a45a8ff	913	((__BASE__) == TIM_DMABASE_CCR3) \|\| \
bogdanm	0:9b334a45a8ff	914	((__BASE__) == TIM_DMABASE_CCR4) \|\| \
bogdanm	0:9b334a45a8ff	915	((__BASE__) == TIM_DMABASE_DCR) \|\| \
bogdanm	0:9b334a45a8ff	916	((__BASE__) == TIM_DMABASE_OR))
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918
bogdanm	0:9b334a45a8ff	919	/** @defgroup TIM_DMA_Burst_Length DMA burst length
bogdanm	0:9b334a45a8ff	920	* @{
bogdanm	0:9b334a45a8ff	921	*/
bogdanm	0:9b334a45a8ff	922	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
bogdanm	0:9b334a45a8ff	923	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
bogdanm	0:9b334a45a8ff	924	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
bogdanm	0:9b334a45a8ff	925	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
bogdanm	0:9b334a45a8ff	926	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
bogdanm	0:9b334a45a8ff	927	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
bogdanm	0:9b334a45a8ff	928	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
bogdanm	0:9b334a45a8ff	929	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
bogdanm	0:9b334a45a8ff	930	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
bogdanm	0:9b334a45a8ff	931	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
bogdanm	0:9b334a45a8ff	932	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
bogdanm	0:9b334a45a8ff	933	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
bogdanm	0:9b334a45a8ff	934	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
bogdanm	0:9b334a45a8ff	935	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
bogdanm	0:9b334a45a8ff	936	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
bogdanm	0:9b334a45a8ff	937	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
bogdanm	0:9b334a45a8ff	938	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
bogdanm	0:9b334a45a8ff	939	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
bogdanm	0:9b334a45a8ff	940	/**
bogdanm	0:9b334a45a8ff	941	* @}
bogdanm	0:9b334a45a8ff	942	*/
bogdanm	0:9b334a45a8ff	943	#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER ) \|\| \
bogdanm	0:9b334a45a8ff	944	((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	945	((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	946	((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	947	((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	948	((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	949	((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	950	((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	951	((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS ) \|\| \
bogdanm	0:9b334a45a8ff	952	((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	953	((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS ) \|\| \
bogdanm	0:9b334a45a8ff	954	((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	955	((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	956	((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	957	((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	958	((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	959	((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	960	((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS ))
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	/* Check IC filter */
bogdanm	0:9b334a45a8ff	964	#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
bogdanm	0:9b334a45a8ff	965
bogdanm	0:9b334a45a8ff	966	/** @defgroup DMA_Handle_index DMA handle index
bogdanm	0:9b334a45a8ff	967	* @{
bogdanm	0:9b334a45a8ff	968	*/
bogdanm	0:9b334a45a8ff	969	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
bogdanm	0:9b334a45a8ff	970	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
bogdanm	0:9b334a45a8ff	971	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
bogdanm	0:9b334a45a8ff	972	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
bogdanm	0:9b334a45a8ff	973	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
bogdanm	0:9b334a45a8ff	974	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5) /!< Index of the DMA handle used for Trigger DMA requests /
bogdanm	0:9b334a45a8ff	975	/**
bogdanm	0:9b334a45a8ff	976	* @}
bogdanm	0:9b334a45a8ff	977	*/
bogdanm	0:9b334a45a8ff	978
bogdanm	0:9b334a45a8ff	979	/** @defgroup Channel_CC_State Channel state
bogdanm	0:9b334a45a8ff	980	* @{
bogdanm	0:9b334a45a8ff	981	*/
bogdanm	0:9b334a45a8ff	982	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	983	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	984	/**
bogdanm	0:9b334a45a8ff	985	* @}
bogdanm	0:9b334a45a8ff	986	*/
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988	/**
bogdanm	0:9b334a45a8ff	989	* @}
bogdanm	0:9b334a45a8ff	990	*/
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	993	/** @defgroup TIM_Exported_Macro TIM Exported Macro
bogdanm	0:9b334a45a8ff	994	* @{
bogdanm	0:9b334a45a8ff	995	*/
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997	/** @brief Reset UART handle state
bogdanm	0:9b334a45a8ff	998	* @param __HANDLE__ : TIM handle
bogdanm	0:9b334a45a8ff	999	* @retval None
bogdanm	0:9b334a45a8ff	1000	*/
bogdanm	0:9b334a45a8ff	1001	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1002
bogdanm	0:9b334a45a8ff	1003	/**
bogdanm	0:9b334a45a8ff	1004	* @brief Enable the TIM peripheral.
bogdanm	0:9b334a45a8ff	1005	* @param __HANDLE__ : TIM handle
bogdanm	0:9b334a45a8ff	1006	* @retval None
bogdanm	0:9b334a45a8ff	1007	*/
bogdanm	0:9b334a45a8ff	1008	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
bogdanm	0:9b334a45a8ff	1009
bogdanm	0:9b334a45a8ff	1010	/* The counter of a timer instance is disabled only if all the CCx channels have
bogdanm	0:9b334a45a8ff	1011	been disabled */
bogdanm	0:9b334a45a8ff	1012	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	/**
bogdanm	0:9b334a45a8ff	1015	* @brief Disable the TIM peripheral.
bogdanm	0:9b334a45a8ff	1016	* @param __HANDLE__ : TIM handle
bogdanm	0:9b334a45a8ff	1017	* @retval None
bogdanm	0:9b334a45a8ff	1018	*/
bogdanm	0:9b334a45a8ff	1019	#define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1020	do { \
bogdanm	0:9b334a45a8ff	1021	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1022	{ \
bogdanm	0:9b334a45a8ff	1023	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm	0:9b334a45a8ff	1024	} \
bogdanm	0:9b334a45a8ff	1025	} while(0)
bogdanm	0:9b334a45a8ff	1026
bogdanm	0:9b334a45a8ff	1027	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1028	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
bogdanm	0:9b334a45a8ff	1029	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1030	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm	0:9b334a45a8ff	1031	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	1032	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm	0:9b334a45a8ff	1033
bogdanm	0:9b334a45a8ff	1034	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	0:9b334a45a8ff	1035	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1036
bogdanm	0:9b334a45a8ff	1037	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm	0:9b334a45a8ff	1038	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm	0:9b334a45a8ff	1039
bogdanm	0:9b334a45a8ff	1040	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	0:9b334a45a8ff	1041	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
bogdanm	0:9b334a45a8ff	1042	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
bogdanm	0:9b334a45a8ff	1043	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
bogdanm	0:9b334a45a8ff	1044	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
bogdanm	0:9b334a45a8ff	1045
bogdanm	0:9b334a45a8ff	1046	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1047	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm	0:9b334a45a8ff	1048	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm	0:9b334a45a8ff	1049	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm	0:9b334a45a8ff	1050	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm	0:9b334a45a8ff	1051
bogdanm	0:9b334a45a8ff	1052	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
bogdanm	0:9b334a45a8ff	1053	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
bogdanm	0:9b334a45a8ff	1054	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
bogdanm	0:9b334a45a8ff	1055	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
bogdanm	0:9b334a45a8ff	1056	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
bogdanm	0:9b334a45a8ff	1057
bogdanm	0:9b334a45a8ff	1058	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1059	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
bogdanm	0:9b334a45a8ff	1060	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
bogdanm	0:9b334a45a8ff	1061	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
bogdanm	0:9b334a45a8ff	1062	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	/**
bogdanm	0:9b334a45a8ff	1065	* @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm	0:9b334a45a8ff	1066	* calling another time ConfigChannel function.
bogdanm	0:9b334a45a8ff	1067	* @param __HANDLE__ : TIM handle.
bogdanm	0:9b334a45a8ff	1068	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1069	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1070	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1071	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1072	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1073	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1074	* @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm	0:9b334a45a8ff	1075	* @retval None
bogdanm	0:9b334a45a8ff	1076	*/
bogdanm	0:9b334a45a8ff	1077	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm	0:9b334a45a8ff	1078	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm	0:9b334a45a8ff	1079
bogdanm	0:9b334a45a8ff	1080	/**
bogdanm	0:9b334a45a8ff	1081	* @brief Gets the TIM Capture Compare Register value on runtime
bogdanm	0:9b334a45a8ff	1082	* @param __HANDLE__ : TIM handle.
bogdanm	0:9b334a45a8ff	1083	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm	0:9b334a45a8ff	1084	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1085	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm	0:9b334a45a8ff	1086	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm	0:9b334a45a8ff	1087	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm	0:9b334a45a8ff	1088	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm	0:9b334a45a8ff	1089	* @retval None
bogdanm	0:9b334a45a8ff	1090	*/
bogdanm	0:9b334a45a8ff	1091	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1092	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm	0:9b334a45a8ff	1093
bogdanm	0:9b334a45a8ff	1094	/**
bogdanm	0:9b334a45a8ff	1095	* @brief Sets the TIM Counter Register value on runtime.
bogdanm	0:9b334a45a8ff	1096	* @param __HANDLE__ : TIM handle.
bogdanm	0:9b334a45a8ff	1097	* @param __COUNTER__: specifies the Counter register new value.
bogdanm	0:9b334a45a8ff	1098	* @retval None
bogdanm	0:9b334a45a8ff	1099	*/
bogdanm	0:9b334a45a8ff	1100	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm	0:9b334a45a8ff	1101
bogdanm	0:9b334a45a8ff	1102	/**
bogdanm	0:9b334a45a8ff	1103	* @brief Gets the TIM Counter Register value on runtime.
bogdanm	0:9b334a45a8ff	1104	* @param __HANDLE__ : TIM handle.
bogdanm	0:9b334a45a8ff	1105	* @retval None
bogdanm	0:9b334a45a8ff	1106	*/
bogdanm	0:9b334a45a8ff	1107	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	/**
bogdanm	0:9b334a45a8ff	1110	* @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm	0:9b334a45a8ff	1111	* another time any Init function.
bogdanm	0:9b334a45a8ff	1112	* @param __HANDLE__ : TIM handle.
bogdanm	0:9b334a45a8ff	1113	* @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm	0:9b334a45a8ff	1114	* @retval None
bogdanm	0:9b334a45a8ff	1115	*/
bogdanm	0:9b334a45a8ff	1116	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
bogdanm	0:9b334a45a8ff	1117	do{ \
bogdanm	0:9b334a45a8ff	1118	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm	0:9b334a45a8ff	1119	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm	0:9b334a45a8ff	1120	} while(0)
bogdanm	0:9b334a45a8ff	1121	/**
bogdanm	0:9b334a45a8ff	1122	* @brief Gets the TIM Autoreload Register value on runtime
bogdanm	0:9b334a45a8ff	1123	* @param __HANDLE__ : TIM handle.
bogdanm	0:9b334a45a8ff	1124	* @retval None
bogdanm	0:9b334a45a8ff	1125	*/
bogdanm	0:9b334a45a8ff	1126	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
bogdanm	0:9b334a45a8ff	1127
bogdanm	0:9b334a45a8ff	1128	/**
bogdanm	0:9b334a45a8ff	1129	* @brief Sets the TIM Clock Division value on runtime without calling
bogdanm	0:9b334a45a8ff	1130	* another time any Init function.
bogdanm	0:9b334a45a8ff	1131	* @param __HANDLE__ : TIM handle.
bogdanm	0:9b334a45a8ff	1132	* @param __CKD__: specifies the clock division value.
bogdanm	0:9b334a45a8ff	1133	* This parameter can be one of the following value:
bogdanm	0:9b334a45a8ff	1134	* @arg TIM_CLOCKDIVISION_DIV1
bogdanm	0:9b334a45a8ff	1135	* @arg TIM_CLOCKDIVISION_DIV2
bogdanm	0:9b334a45a8ff	1136	* @arg TIM_CLOCKDIVISION_DIV4
bogdanm	0:9b334a45a8ff	1137	* @retval None
bogdanm	0:9b334a45a8ff	1138	*/
bogdanm	0:9b334a45a8ff	1139	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
bogdanm	0:9b334a45a8ff	1140	do{ \
bogdanm	0:9b334a45a8ff	1141	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm	0:9b334a45a8ff	1142	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
bogdanm	0:9b334a45a8ff	1143	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm	0:9b334a45a8ff	1144	} while(0)
bogdanm	0:9b334a45a8ff	1145	/**
bogdanm	0:9b334a45a8ff	1146	* @brief Gets the TIM Clock Division value on runtime
bogdanm	0:9b334a45a8ff	1147	* @param __HANDLE__ : TIM handle.
bogdanm	0:9b334a45a8ff	1148	* @retval None
bogdanm	0:9b334a45a8ff	1149	*/
bogdanm	0:9b334a45a8ff	1150	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm	0:9b334a45a8ff	1151
bogdanm	0:9b334a45a8ff	1152	/**
bogdanm	0:9b334a45a8ff	1153	* @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm	0:9b334a45a8ff	1154	* another time HAL_TIM_IC_ConfigChannel() function.
bogdanm	0:9b334a45a8ff	1155	* @param __HANDLE__ : TIM handle.
bogdanm	0:9b334a45a8ff	1156	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1157	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1158	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1159	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1160	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1161	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1162	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm	0:9b334a45a8ff	1163	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1164	* @arg TIM_ICPSC_DIV1: no prescaler
bogdanm	0:9b334a45a8ff	1165	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm	0:9b334a45a8ff	1166	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm	0:9b334a45a8ff	1167	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm	0:9b334a45a8ff	1168	* @retval None
bogdanm	0:9b334a45a8ff	1169	*/
bogdanm	0:9b334a45a8ff	1170	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	0:9b334a45a8ff	1171	do{ \
bogdanm	0:9b334a45a8ff	1172	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
bogdanm	0:9b334a45a8ff	1173	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm	0:9b334a45a8ff	1174	} while(0)
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	/**
bogdanm	0:9b334a45a8ff	1177	* @brief Gets the TIM Input Capture prescaler on runtime
bogdanm	0:9b334a45a8ff	1178	* @param __HANDLE__ : TIM handle.
bogdanm	0:9b334a45a8ff	1179	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1180	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1181	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm	0:9b334a45a8ff	1182	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm	0:9b334a45a8ff	1183	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm	0:9b334a45a8ff	1184	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm	0:9b334a45a8ff	1185	* @retval None
bogdanm	0:9b334a45a8ff	1186	*/
bogdanm	0:9b334a45a8ff	1187	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1188	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm	0:9b334a45a8ff	1189	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm	0:9b334a45a8ff	1190	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm	0:9b334a45a8ff	1191	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	/**
bogdanm	0:9b334a45a8ff	1195	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	0:9b334a45a8ff	1196	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1197	* @note When the URS bit of the TIMx_CR1 register is set, only counter
bogdanm	0:9b334a45a8ff	1198	* overflow/underflow generates an update interrupt or DMA request (if
bogdanm	0:9b334a45a8ff	1199	* enabled)
bogdanm	0:9b334a45a8ff	1200	* @retval None
bogdanm	0:9b334a45a8ff	1201	*/
bogdanm	0:9b334a45a8ff	1202	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1203	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
bogdanm	0:9b334a45a8ff	1204
bogdanm	0:9b334a45a8ff	1205	/**
bogdanm	0:9b334a45a8ff	1206	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	0:9b334a45a8ff	1207	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1208	* @note When the URS bit of the TIMx_CR1 register is reset, any of the
bogdanm	0:9b334a45a8ff	1209	* following events generate an update interrupt or DMA request (if
bogdanm	0:9b334a45a8ff	1210	* enabled):
mbed_official	113:b3775bf36a83	1211	* Counter overflow/underflow
mbed_official	113:b3775bf36a83	1212	* Setting the UG bit
mbed_official	113:b3775bf36a83	1213	* Update generation through the slave mode controller
bogdanm	0:9b334a45a8ff	1214	* @retval None
bogdanm	0:9b334a45a8ff	1215	*/
bogdanm	0:9b334a45a8ff	1216	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1217	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
bogdanm	0:9b334a45a8ff	1218
bogdanm	0:9b334a45a8ff	1219	/**
bogdanm	0:9b334a45a8ff	1220	* @brief Sets the TIM Capture x input polarity on runtime.
bogdanm	0:9b334a45a8ff	1221	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1222	* @param __CHANNEL__: TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1223	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1224	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1225	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1226	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1227	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1228	* @param __POLARITY__: Polarity for TIx source
bogdanm	0:9b334a45a8ff	1229	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
bogdanm	0:9b334a45a8ff	1230	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
bogdanm	0:9b334a45a8ff	1231	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
bogdanm	0:9b334a45a8ff	1232	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
bogdanm	0:9b334a45a8ff	1233	* @retval None
bogdanm	0:9b334a45a8ff	1234	*/
bogdanm	0:9b334a45a8ff	1235	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
bogdanm	0:9b334a45a8ff	1236	do{ \
bogdanm	0:9b334a45a8ff	1237	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
bogdanm	0:9b334a45a8ff	1238	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
bogdanm	0:9b334a45a8ff	1239	}while(0)
bogdanm	0:9b334a45a8ff	1240
bogdanm	0:9b334a45a8ff	1241	/**
bogdanm	0:9b334a45a8ff	1242	* @}
bogdanm	0:9b334a45a8ff	1243	*/
bogdanm	0:9b334a45a8ff	1244
bogdanm	0:9b334a45a8ff	1245	/* Include TIM HAL Extension module */
bogdanm	0:9b334a45a8ff	1246	#include "stm32l0xx_hal_tim_ex.h"
bogdanm	0:9b334a45a8ff	1247
bogdanm	0:9b334a45a8ff	1248	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1249	/** @defgroup TIM_Exported_Functions TIM Exported Functions
bogdanm	0:9b334a45a8ff	1250	* @{
bogdanm	0:9b334a45a8ff	1251	*/
bogdanm	0:9b334a45a8ff	1252
bogdanm	0:9b334a45a8ff	1253	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1254	/* Time Base functions ********************************************************/
bogdanm	0:9b334a45a8ff	1255
bogdanm	0:9b334a45a8ff	1256	/** @defgroup TIM_Exported_Functions_Group1 Timer Base functions
bogdanm	0:9b334a45a8ff	1257	* @brief Time Base functions
bogdanm	0:9b334a45a8ff	1258	* @{
bogdanm	0:9b334a45a8ff	1259	*/
bogdanm	0:9b334a45a8ff	1260	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1261	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1262	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1263	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1264	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1265	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1266	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1267	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1268	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1269	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1270	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1271	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1272	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/**
bogdanm	0:9b334a45a8ff	1275	* @}
bogdanm	0:9b334a45a8ff	1276	*/
bogdanm	0:9b334a45a8ff	1277
bogdanm	0:9b334a45a8ff	1278
bogdanm	0:9b334a45a8ff	1279	/* Timer Output Compare functions **********************************************/
bogdanm	0:9b334a45a8ff	1280
bogdanm	0:9b334a45a8ff	1281	/** @defgroup TIM_Exported_Functions_Group2 Timer Output Compare functions
bogdanm	0:9b334a45a8ff	1282	* @brief Timer Output Compare functions
bogdanm	0:9b334a45a8ff	1283	* @{
bogdanm	0:9b334a45a8ff	1284	*/
bogdanm	0:9b334a45a8ff	1285
bogdanm	0:9b334a45a8ff	1286	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1287	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1288	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1289	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1290	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1291	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1292	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1293	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1294	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1295	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1296	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1297	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1298	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1299	/**
bogdanm	0:9b334a45a8ff	1300	* @}
bogdanm	0:9b334a45a8ff	1301	*/
bogdanm	0:9b334a45a8ff	1302
bogdanm	0:9b334a45a8ff	1303
bogdanm	0:9b334a45a8ff	1304	/* Timer PWM functions *********************************************************/
bogdanm	0:9b334a45a8ff	1305
bogdanm	0:9b334a45a8ff	1306	/** @defgroup TIM_Exported_Functions_Group3 Timer PWM functions
bogdanm	0:9b334a45a8ff	1307	* @brief Timer PWM functions
bogdanm	0:9b334a45a8ff	1308	* @{
bogdanm	0:9b334a45a8ff	1309	*/
bogdanm	0:9b334a45a8ff	1310	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1311	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1312	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1313	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1314	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1315	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1316	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1317	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1318	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1319	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1320	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1321	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1322	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1323	/**
bogdanm	0:9b334a45a8ff	1324	* @}
bogdanm	0:9b334a45a8ff	1325	*/
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	/* Timer Input Capture functions ***********************************************/
bogdanm	0:9b334a45a8ff	1328
bogdanm	0:9b334a45a8ff	1329	/** @defgroup TIM_Exported_Functions_Group4 Timer Input Capture functions
bogdanm	0:9b334a45a8ff	1330	* @brief Timer Input Capture functions
bogdanm	0:9b334a45a8ff	1331	* @{
bogdanm	0:9b334a45a8ff	1332	*/
bogdanm	0:9b334a45a8ff	1333	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1334	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1335	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1336	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1337	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1338	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1339	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1340	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1341	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1342	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1343	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1344	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1345	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1346	/**
bogdanm	0:9b334a45a8ff	1347	* @}
bogdanm	0:9b334a45a8ff	1348	*/
bogdanm	0:9b334a45a8ff	1349
bogdanm	0:9b334a45a8ff	1350	/* Timer One Pulse functions ***************************************************/
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	/** @defgroup TIM_Exported_Functions_Group5 Timer One Pulse functions
bogdanm	0:9b334a45a8ff	1353	* @brief Timer One Pulse functions
bogdanm	0:9b334a45a8ff	1354	* @{
bogdanm	0:9b334a45a8ff	1355	*/
bogdanm	0:9b334a45a8ff	1356	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm	0:9b334a45a8ff	1357	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1358	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1359	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1360	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1361	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1362	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1363
bogdanm	0:9b334a45a8ff	1364	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1365	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1366	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1367
bogdanm	0:9b334a45a8ff	1368	/**
bogdanm	0:9b334a45a8ff	1369	* @}
bogdanm	0:9b334a45a8ff	1370	*/
bogdanm	0:9b334a45a8ff	1371
bogdanm	0:9b334a45a8ff	1372	/* Timer Encoder functions *****************************************************/
bogdanm	0:9b334a45a8ff	1373
bogdanm	0:9b334a45a8ff	1374	/** @defgroup TIM_Exported_Functions_Group6 Timer Encoder functions
bogdanm	0:9b334a45a8ff	1375	* @brief Timer Encoder functions
bogdanm	0:9b334a45a8ff	1376	* @{
bogdanm	0:9b334a45a8ff	1377	*/
bogdanm	0:9b334a45a8ff	1378	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
bogdanm	0:9b334a45a8ff	1379	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1380	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1381	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1382	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1383	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1384	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1385	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1386	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1387	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1388	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1389	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
bogdanm	0:9b334a45a8ff	1390	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1391
bogdanm	0:9b334a45a8ff	1392	/**
bogdanm	0:9b334a45a8ff	1393	* @}
bogdanm	0:9b334a45a8ff	1394	*/
bogdanm	0:9b334a45a8ff	1395
bogdanm	0:9b334a45a8ff	1396	/* Interrupt Handler functions **********************************************/
bogdanm	0:9b334a45a8ff	1397
bogdanm	0:9b334a45a8ff	1398	/** @defgroup TIM_Exported_Functions_Group7 Timer IRQ handler management
bogdanm	0:9b334a45a8ff	1399	* @brief Interrupt Handler functions
bogdanm	0:9b334a45a8ff	1400	* @{
bogdanm	0:9b334a45a8ff	1401	*/
bogdanm	0:9b334a45a8ff	1402	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1403	/**
bogdanm	0:9b334a45a8ff	1404	* @}
bogdanm	0:9b334a45a8ff	1405	*/
bogdanm	0:9b334a45a8ff	1406
bogdanm	0:9b334a45a8ff	1407	/* Control functions *********************************************************/
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1410	* @brief Control functions
bogdanm	0:9b334a45a8ff	1411	* @{
bogdanm	0:9b334a45a8ff	1412	*/
bogdanm	0:9b334a45a8ff	1413	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1414	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1415	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1416	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm	0:9b334a45a8ff	1417	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1418	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
bogdanm	0:9b334a45a8ff	1419	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm	0:9b334a45a8ff	1420	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	0:9b334a45a8ff	1421	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	0:9b334a45a8ff	1422	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	0:9b334a45a8ff	1423	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	0:9b334a45a8ff	1424	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	0:9b334a45a8ff	1425	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	0:9b334a45a8ff	1426	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	0:9b334a45a8ff	1427	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	0:9b334a45a8ff	1428	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm	0:9b334a45a8ff	1429	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1430
bogdanm	0:9b334a45a8ff	1431	/**
bogdanm	0:9b334a45a8ff	1432	* @}
bogdanm	0:9b334a45a8ff	1433	*/
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	/* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm	0:9b334a45a8ff	1436
bogdanm	0:9b334a45a8ff	1437	/** @defgroup TIM_Exported_Functions_Group9 Timer Callbacks functions
bogdanm	0:9b334a45a8ff	1438	* @brief Callback functions
bogdanm	0:9b334a45a8ff	1439	* @{
bogdanm	0:9b334a45a8ff	1440	*/
bogdanm	0:9b334a45a8ff	1441	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1442	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1443	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1444	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1445	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1446	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1447	/**
bogdanm	0:9b334a45a8ff	1448	* @}
bogdanm	0:9b334a45a8ff	1449	*/
bogdanm	0:9b334a45a8ff	1450
bogdanm	0:9b334a45a8ff	1451
bogdanm	0:9b334a45a8ff	1452	/* Peripheral State functions **************************************************/
bogdanm	0:9b334a45a8ff	1453
bogdanm	0:9b334a45a8ff	1454	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
bogdanm	0:9b334a45a8ff	1455	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	1456	* @{
bogdanm	0:9b334a45a8ff	1457	*/
bogdanm	0:9b334a45a8ff	1458	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1459	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1460	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1461	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1462	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1463	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1464	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1465	void TIM_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1466	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1467
bogdanm	0:9b334a45a8ff	1468	/**
bogdanm	0:9b334a45a8ff	1469	* @}
bogdanm	0:9b334a45a8ff	1470	*/
bogdanm	0:9b334a45a8ff	1471
bogdanm	0:9b334a45a8ff	1472	/**
bogdanm	0:9b334a45a8ff	1473	* @}
bogdanm	0:9b334a45a8ff	1474	*/
bogdanm	0:9b334a45a8ff	1475
mbed_official	113:b3775bf36a83	1476	/* Define the private group ***********************************/
mbed_official	113:b3775bf36a83	1477	/**************************************************************/
mbed_official	113:b3775bf36a83	1478	/** @defgroup TIM_Private TIM Private
mbed_official	113:b3775bf36a83	1479	* @{
mbed_official	113:b3775bf36a83	1480	*/
mbed_official	113:b3775bf36a83	1481	/**
mbed_official	113:b3775bf36a83	1482	* @}
mbed_official	113:b3775bf36a83	1483	*/
mbed_official	113:b3775bf36a83	1484	/**************************************************************/
mbed_official	113:b3775bf36a83	1485
bogdanm	0:9b334a45a8ff	1486	/**
bogdanm	0:9b334a45a8ff	1487	* @}
bogdanm	0:9b334a45a8ff	1488	*/
bogdanm	0:9b334a45a8ff	1489
bogdanm	0:9b334a45a8ff	1490	/**
bogdanm	0:9b334a45a8ff	1491	* @}
bogdanm	0:9b334a45a8ff	1492	*/
bogdanm	0:9b334a45a8ff	1493
bogdanm	0:9b334a45a8ff	1494	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1495	}
bogdanm	0:9b334a45a8ff	1496	#endif
bogdanm	0:9b334a45a8ff	1497
bogdanm	0:9b334a45a8ff	1498	#endif /* __STM32L0xx_HAL_TIM_H */
bogdanm	0:9b334a45a8ff	1499
bogdanm	0:9b334a45a8ff	1500	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	1501

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.h@113:b3775bf36a83, 2016-04-19 (annotated)

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