mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

Dependents: IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.c@113:b3775bf36a83, 2016-04-19 (annotated)

Committer:: mbed_official
Date:: Tue Apr 19 11:15:15 2016 +0100
Revision:: 113:b3775bf36a83
Parent:: 0:9b334a45a8ff

Synchronized with git revision 896981126b34b6d9441e3eea77881c67a1ae3dbd

Full URL: https://github.com/mbedmicro/mbed/commit/896981126b34b6d9441e3eea77881c67a1ae3dbd/

Exporter tool addition for e2 studio

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l0xx_hal_spi.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	113:b3775bf36a83	5	* @version V1.5.0
mbed_official	113:b3775bf36a83	6	* @date 8-January-2016
bogdanm	0:9b334a45a8ff	7	* @brief SPI HAL module driver.
bogdanm	0:9b334a45a8ff	8	*
bogdanm	0:9b334a45a8ff	9	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
bogdanm	0:9b334a45a8ff	11	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	12	* + IO operation functions
bogdanm	0:9b334a45a8ff	13	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	14	* + Peripheral State functions
bogdanm	0:9b334a45a8ff	15	@verbatim
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	18	==============================================================================
bogdanm	0:9b334a45a8ff	19	[..]
bogdanm	0:9b334a45a8ff	20	The SPI HAL driver can be used as follows:
bogdanm	0:9b334a45a8ff	21
bogdanm	0:9b334a45a8ff	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
bogdanm	0:9b334a45a8ff	23	SPI_HandleTypeDef hspi;
bogdanm	0:9b334a45a8ff	24
bogdanm	0:9b334a45a8ff	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
bogdanm	0:9b334a45a8ff	26	(##) Enable the SPIx interface clock
bogdanm	0:9b334a45a8ff	27	(##) SPI pins configuration
bogdanm	0:9b334a45a8ff	28	(+++) Enable the clock for the SPI GPIOs
bogdanm	0:9b334a45a8ff	29	(+++) Configure these SPI pins as alternate function push-pull
bogdanm	0:9b334a45a8ff	30	(##) NVIC configuration if you need to use interrupt process
bogdanm	0:9b334a45a8ff	31	(+++) Configure the SPIx interrupt priority
bogdanm	0:9b334a45a8ff	32	(+++) Enable the NVIC SPI IRQ handle
bogdanm	0:9b334a45a8ff	33	(##) DMA Configuration if you need to use DMA process
bogdanm	0:9b334a45a8ff	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
bogdanm	0:9b334a45a8ff	35	(+++) Enable the DMAx clock
bogdanm	0:9b334a45a8ff	36	(+++) Configure the DMA handle parameters
bogdanm	0:9b334a45a8ff	37	(+++) Configure the DMA Tx or Rx Channel
bogdanm	0:9b334a45a8ff	38	(+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
bogdanm	0:9b334a45a8ff	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
bogdanm	0:9b334a45a8ff	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
bogdanm	0:9b334a45a8ff	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
bogdanm	0:9b334a45a8ff	46	by calling the customed HAL_SPI_MspInit() API.
bogdanm	0:9b334a45a8ff	47	[..]
bogdanm	0:9b334a45a8ff	48	Circular mode restriction:
bogdanm	0:9b334a45a8ff	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
bogdanm	0:9b334a45a8ff	50	(##) Master 2Lines RxOnly
bogdanm	0:9b334a45a8ff	51	(##) Master 1Line Rx
bogdanm	0:9b334a45a8ff	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
bogdanm	0:9b334a45a8ff	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
bogdanm	0:9b334a45a8ff	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
bogdanm	0:9b334a45a8ff	55
bogdanm	0:9b334a45a8ff	56	[..]
bogdanm	0:9b334a45a8ff	57	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
bogdanm	0:9b334a45a8ff	58	the following table resume the max SPI frequency reached with data size 8bits/16bits,
bogdanm	0:9b334a45a8ff	59	according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
bogdanm	0:9b334a45a8ff	60
bogdanm	0:9b334a45a8ff	61	DataSize = SPI_DATASIZE_8BIT:
bogdanm	0:9b334a45a8ff	62	+----------------------------------------------------------------------------------------------+
bogdanm	0:9b334a45a8ff	63	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
bogdanm	0:9b334a45a8ff	64	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
bogdanm	0:9b334a45a8ff	65	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
bogdanm	0:9b334a45a8ff	66	\|==============================================================================================\|
bogdanm	0:9b334a45a8ff	67	\| T \| Polling \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	68	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
bogdanm	0:9b334a45a8ff	69	\| / \| Interrupt \| Fpclk/64 \| Fpclk/64 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	70	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
bogdanm	0:9b334a45a8ff	71	\| X \| DMA \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	72	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
bogdanm	0:9b334a45a8ff	73	\| \| Polling \| Fpclk/2 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \|
bogdanm	0:9b334a45a8ff	74	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
bogdanm	0:9b334a45a8ff	75	\| R \| Interrupt \| Fpclk/64 \| Fpclk/32 \| Fpclk/32 \| Fpclk/16 \| Fpclk/32 \| Fpclk/32 \|
bogdanm	0:9b334a45a8ff	76	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
bogdanm	0:9b334a45a8ff	77	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| Fpclk/16 \| Fpclk/2 \| Fpclk/16 \| Fpclk/2 \|
bogdanm	0:9b334a45a8ff	78	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
bogdanm	0:9b334a45a8ff	79	\| \| Polling \| Fpclk/8 \| Fpclk/8 \| NA \| NA \| Fpclk/4 \| Fpclk/16 \|
bogdanm	0:9b334a45a8ff	80	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
bogdanm	0:9b334a45a8ff	81	\| T \| Interrupt \| Fpclk/8 \| Fpclk/32 \| NA \| NA \| Fpclk/8 \| Fpclk/16 \|
bogdanm	0:9b334a45a8ff	82	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
bogdanm	0:9b334a45a8ff	83	\| \| DMA \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/2 \| Fpclk/2 \|
bogdanm	0:9b334a45a8ff	84	+----------------------------------------------------------------------------------------------+
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	DataSize = SPI_DATASIZE_16BIT:
bogdanm	0:9b334a45a8ff	87	+----------------------------------------------------------------------------------------------+
bogdanm	0:9b334a45a8ff	88	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
bogdanm	0:9b334a45a8ff	89	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
bogdanm	0:9b334a45a8ff	90	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
bogdanm	0:9b334a45a8ff	91	\|==============================================================================================\|
bogdanm	0:9b334a45a8ff	92	\| T \| Polling \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	93	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
bogdanm	0:9b334a45a8ff	94	\| / \| Interrupt \| Fpclk/32 \| Fpclk/16 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	95	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
bogdanm	0:9b334a45a8ff	96	\| X \| DMA \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| NA \| NA \|
bogdanm	0:9b334a45a8ff	97	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
bogdanm	0:9b334a45a8ff	98	\| \| Polling \| Fpclk/2 \| Fpclk/4 \| Fpclk/8 \| Fpclk/4 \| Fpclk/2 \| Fpclk/8 \|
bogdanm	0:9b334a45a8ff	99	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
bogdanm	0:9b334a45a8ff	100	\| R \| Interrupt \| Fpclk/32 \| Fpclk/8 \| Fpclk/16 \| Fpclk/16 \| Fpclk/16 \| Fpclk/8 \|
bogdanm	0:9b334a45a8ff	101	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
bogdanm	0:9b334a45a8ff	102	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| Fpclk/8 \| Fpclk/2 \| Fpclk/8 \| Fpclk/2 \|
bogdanm	0:9b334a45a8ff	103	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
bogdanm	0:9b334a45a8ff	104	\| \| Polling \| Fpclk/4 \| Fpclk/4 \| NA \| NA \| Fpclk/4 \| Fpclk/8 \|
bogdanm	0:9b334a45a8ff	105	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
bogdanm	0:9b334a45a8ff	106	\| T \| Interrupt \| Fpclk/4 \| Fpclk/16 \| NA \| NA \| Fpclk/8 \| Fpclk/8 \|
bogdanm	0:9b334a45a8ff	107	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
bogdanm	0:9b334a45a8ff	108	\| \| DMA \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/2 \| Fpclk/2 \|
bogdanm	0:9b334a45a8ff	109	+----------------------------------------------------------------------------------------------+
bogdanm	0:9b334a45a8ff	110	@note The max SPI frequency depend on SPI data size (8bits, 16bits),
bogdanm	0:9b334a45a8ff	111	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
bogdanm	0:9b334a45a8ff	112	@note
bogdanm	0:9b334a45a8ff	113	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
bogdanm	0:9b334a45a8ff	114	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
bogdanm	0:9b334a45a8ff	115	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	@endverbatim
bogdanm	0:9b334a45a8ff	118	******************************************************************************
bogdanm	0:9b334a45a8ff	119	* @attention
bogdanm	0:9b334a45a8ff	120	*
mbed_official	113:b3775bf36a83	121	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	122	*
bogdanm	0:9b334a45a8ff	123	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	124	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	125	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	126	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	127	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	128	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	129	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	130	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	131	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	132	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	133	*
bogdanm	0:9b334a45a8ff	134	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	135	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	136	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	137	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	138	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	139	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	140	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	141	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	142	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	143	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	144	*
bogdanm	0:9b334a45a8ff	145	******************************************************************************
bogdanm	0:9b334a45a8ff	146	*/
bogdanm	0:9b334a45a8ff	147
bogdanm	0:9b334a45a8ff	148	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	149	#include "stm32l0xx_hal.h"
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	152	* @{
bogdanm	0:9b334a45a8ff	153	*/
bogdanm	0:9b334a45a8ff	154
mbed_official	113:b3775bf36a83	155	#ifdef HAL_SPI_MODULE_ENABLED
mbed_official	113:b3775bf36a83	156
mbed_official	113:b3775bf36a83	157	/** @addtogroup SPI
bogdanm	0:9b334a45a8ff	158	* @brief SPI HAL module driver
bogdanm	0:9b334a45a8ff	159	* @{
bogdanm	0:9b334a45a8ff	160	*/
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	163	/* Private define ------------------------------------------------------------*/
mbed_official	113:b3775bf36a83	164	/** @addtogroup SPI_Private
bogdanm	0:9b334a45a8ff	165	* @{
bogdanm	0:9b334a45a8ff	166	*/
bogdanm	0:9b334a45a8ff	167	#define SPI_TIMEOUT_VALUE 10
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	170	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	171	/* Private function prototypes -----------------------------------------------*/
mbed_official	113:b3775bf36a83	172
bogdanm	0:9b334a45a8ff	173	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	174	static void SPI_TxISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	175	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	176	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	177	static void SPI_RxISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	178	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	179	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	180	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	181	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	182	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	183	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	184	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	185	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	186	/**
bogdanm	0:9b334a45a8ff	187	* @}
bogdanm	0:9b334a45a8ff	188	*/
bogdanm	0:9b334a45a8ff	189
bogdanm	0:9b334a45a8ff	190	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	191
mbed_official	113:b3775bf36a83	192	/** @addtogroup SPI_Exported_Functions SPI Exported Functions
bogdanm	0:9b334a45a8ff	193	* @{
bogdanm	0:9b334a45a8ff	194	*/
bogdanm	0:9b334a45a8ff	195
mbed_official	113:b3775bf36a83	196	/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	197	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	198	*
bogdanm	0:9b334a45a8ff	199	@verbatim
bogdanm	0:9b334a45a8ff	200	===============================================================================
bogdanm	0:9b334a45a8ff	201	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	202	===============================================================================
bogdanm	0:9b334a45a8ff	203	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	204	de-initialiaze the SPIx peripheral:
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	(+) User must implement HAL_SPI_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	207	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209	(+) Call the function HAL_SPI_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	210	the selected configuration:
bogdanm	0:9b334a45a8ff	211	(++) Mode
bogdanm	0:9b334a45a8ff	212	(++) Direction
bogdanm	0:9b334a45a8ff	213	(++) Data Size
bogdanm	0:9b334a45a8ff	214	(++) Clock Polarity and Phase
bogdanm	0:9b334a45a8ff	215	(++) NSS Management
bogdanm	0:9b334a45a8ff	216	(++) BaudRate Prescaler
bogdanm	0:9b334a45a8ff	217	(++) FirstBit
bogdanm	0:9b334a45a8ff	218	(++) TIMode
bogdanm	0:9b334a45a8ff	219	(++) CRC Calculation
bogdanm	0:9b334a45a8ff	220	(++) CRC Polynomial if CRC enabled
bogdanm	0:9b334a45a8ff	221
bogdanm	0:9b334a45a8ff	222	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	223	of the selected SPIx periperal.
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225	@endverbatim
bogdanm	0:9b334a45a8ff	226	* @{
bogdanm	0:9b334a45a8ff	227	*/
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	/**
bogdanm	0:9b334a45a8ff	230	* @brief Initializes the SPI according to the specified parameters
bogdanm	0:9b334a45a8ff	231	* in the SPI_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	232	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	233	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	234	* @retval HAL status
bogdanm	0:9b334a45a8ff	235	*/
bogdanm	0:9b334a45a8ff	236	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	237	{
bogdanm	0:9b334a45a8ff	238	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	239	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	240	{
bogdanm	0:9b334a45a8ff	241	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	242	}
bogdanm	0:9b334a45a8ff	243
bogdanm	0:9b334a45a8ff	244	/* Check the parameters */
bogdanm	0:9b334a45a8ff	245	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
bogdanm	0:9b334a45a8ff	246	assert_param(IS_SPI_MODE(hspi->Init.Mode));
bogdanm	0:9b334a45a8ff	247	assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	248	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
bogdanm	0:9b334a45a8ff	249	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
bogdanm	0:9b334a45a8ff	250	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
bogdanm	0:9b334a45a8ff	251	assert_param(IS_SPI_NSS(hspi->Init.NSS));
bogdanm	0:9b334a45a8ff	252	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
bogdanm	0:9b334a45a8ff	253	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
bogdanm	0:9b334a45a8ff	254	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
bogdanm	0:9b334a45a8ff	255	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
bogdanm	0:9b334a45a8ff	256	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	if(hspi->State == HAL_SPI_STATE_RESET)
bogdanm	0:9b334a45a8ff	259	{
mbed_official	113:b3775bf36a83	260	/* Allocate lock resource and initialize it */
mbed_official	113:b3775bf36a83	261	hspi->Lock = HAL_UNLOCKED;
mbed_official	113:b3775bf36a83	262
bogdanm	0:9b334a45a8ff	263	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	264	HAL_SPI_MspInit(hspi);
bogdanm	0:9b334a45a8ff	265	}
bogdanm	0:9b334a45a8ff	266
bogdanm	0:9b334a45a8ff	267	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	268
bogdanm	0:9b334a45a8ff	269	/* Disble the selected SPI peripheral */
bogdanm	0:9b334a45a8ff	270	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
bogdanm	0:9b334a45a8ff	273	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
bogdanm	0:9b334a45a8ff	274	Communication speed, First bit and CRC calculation state */
bogdanm	0:9b334a45a8ff	275	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
bogdanm	0:9b334a45a8ff	276	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
bogdanm	0:9b334a45a8ff	277	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation) );
bogdanm	0:9b334a45a8ff	278
bogdanm	0:9b334a45a8ff	279	/* Configure : NSS management */
bogdanm	0:9b334a45a8ff	280	WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode));
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282	/---------------------------- SPIx CRCPOLY Configuration ------------------/
bogdanm	0:9b334a45a8ff	283	/* Configure : CRC Polynomial */
bogdanm	0:9b334a45a8ff	284	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
bogdanm	0:9b334a45a8ff	285
mbed_official	113:b3775bf36a83	286	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
bogdanm	0:9b334a45a8ff	287	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
bogdanm	0:9b334a45a8ff	288	CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
mbed_official	113:b3775bf36a83	289	#endif
mbed_official	113:b3775bf36a83	290
bogdanm	0:9b334a45a8ff	291	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	292	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	293
bogdanm	0:9b334a45a8ff	294	return HAL_OK;
bogdanm	0:9b334a45a8ff	295	}
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/**
bogdanm	0:9b334a45a8ff	298	* @brief DeInitializes the SPI peripheral
bogdanm	0:9b334a45a8ff	299	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	300	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	301	* @retval HAL status
bogdanm	0:9b334a45a8ff	302	*/
bogdanm	0:9b334a45a8ff	303	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	304	{
bogdanm	0:9b334a45a8ff	305	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	306	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	307	{
bogdanm	0:9b334a45a8ff	308	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	309	}
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	/* Disable the SPI Peripheral Clock */
bogdanm	0:9b334a45a8ff	314	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	317	HAL_SPI_MspDeInit(hspi);
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	320	hspi->State = HAL_SPI_STATE_RESET;
bogdanm	0:9b334a45a8ff	321
bogdanm	0:9b334a45a8ff	322	/* Release Lock */
bogdanm	0:9b334a45a8ff	323	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	324
bogdanm	0:9b334a45a8ff	325	return HAL_OK;
bogdanm	0:9b334a45a8ff	326	}
bogdanm	0:9b334a45a8ff	327
bogdanm	0:9b334a45a8ff	328	/**
bogdanm	0:9b334a45a8ff	329	* @brief SPI MSP Init
bogdanm	0:9b334a45a8ff	330	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	331	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	332	* @retval None
bogdanm	0:9b334a45a8ff	333	*/
bogdanm	0:9b334a45a8ff	334	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	335	{
mbed_official	113:b3775bf36a83	336	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	337	UNUSED(hspi);
mbed_official	113:b3775bf36a83	338
mbed_official	113:b3775bf36a83	339	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	340	the HAL_SPI_MspInit could be implenetd in the user file
mbed_official	113:b3775bf36a83	341	*/
bogdanm	0:9b334a45a8ff	342	}
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	/**
bogdanm	0:9b334a45a8ff	345	* @brief SPI MSP DeInit
bogdanm	0:9b334a45a8ff	346	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	347	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	348	* @retval None
bogdanm	0:9b334a45a8ff	349	*/
bogdanm	0:9b334a45a8ff	350	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	351	{
mbed_official	113:b3775bf36a83	352	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	353	UNUSED(hspi);
mbed_official	113:b3775bf36a83	354
bogdanm	0:9b334a45a8ff	355	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	356	the HAL_SPI_MspDeInit could be implenetd in the user file
bogdanm	0:9b334a45a8ff	357	*/
bogdanm	0:9b334a45a8ff	358	}
bogdanm	0:9b334a45a8ff	359
bogdanm	0:9b334a45a8ff	360	/**
bogdanm	0:9b334a45a8ff	361	* @}
bogdanm	0:9b334a45a8ff	362	*/
bogdanm	0:9b334a45a8ff	363
mbed_official	113:b3775bf36a83	364	/** @addtogroup SPI_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	365	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	366	*
bogdanm	0:9b334a45a8ff	367	@verbatim
bogdanm	0:9b334a45a8ff	368	==============================================================================
bogdanm	0:9b334a45a8ff	369	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	370	===============================================================================
bogdanm	0:9b334a45a8ff	371	This subsection provides a set of functions allowing to manage the SPI
bogdanm	0:9b334a45a8ff	372	data transfers.
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	[..] The SPI supports master and slave mode :
bogdanm	0:9b334a45a8ff	375
bogdanm	0:9b334a45a8ff	376	(#) There are two modes of transfer:
bogdanm	0:9b334a45a8ff	377	(++) Blocking mode: The communication is performed in polling mode.
bogdanm	0:9b334a45a8ff	378	The HAL status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	379	after finishing transfer.
bogdanm	0:9b334a45a8ff	380	(++) No-Blocking mode: The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	381	or DMA, These APIs return the HAL status.
bogdanm	0:9b334a45a8ff	382	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	383	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	384	using DMA mode.
bogdanm	0:9b334a45a8ff	385	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
bogdanm	0:9b334a45a8ff	386	will be executed respectivelly at the end of the transmit or Receive process
bogdanm	0:9b334a45a8ff	387	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
bogdanm	0:9b334a45a8ff	388
bogdanm	0:9b334a45a8ff	389	(#) Blocking mode APIs are :
bogdanm	0:9b334a45a8ff	390	(++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
bogdanm	0:9b334a45a8ff	391	(++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
bogdanm	0:9b334a45a8ff	392	(++) HAL_SPI_TransmitReceive() in full duplex mode
bogdanm	0:9b334a45a8ff	393
bogdanm	0:9b334a45a8ff	394	(#) Non Blocking mode API's with Interrupt are :
bogdanm	0:9b334a45a8ff	395	(++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
bogdanm	0:9b334a45a8ff	396	(++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
bogdanm	0:9b334a45a8ff	397	(++) HAL_SPI_TransmitReceive_IT()in full duplex mode
bogdanm	0:9b334a45a8ff	398	(++) HAL_SPI_IRQHandler()
bogdanm	0:9b334a45a8ff	399
bogdanm	0:9b334a45a8ff	400	(#) Non Blocking mode functions with DMA are :
bogdanm	0:9b334a45a8ff	401	(++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
bogdanm	0:9b334a45a8ff	402	(++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
bogdanm	0:9b334a45a8ff	403	(++) HAL_SPI_TransmitReceive_DMA() in full duplex mode
bogdanm	0:9b334a45a8ff	404
bogdanm	0:9b334a45a8ff	405	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
bogdanm	0:9b334a45a8ff	406	(++) HAL_SPI_TxCpltCallback()
bogdanm	0:9b334a45a8ff	407	(++) HAL_SPI_RxCpltCallback()
bogdanm	0:9b334a45a8ff	408	(++) HAL_SPI_TxRxCpltCallback()
bogdanm	0:9b334a45a8ff	409	(++) HAL_SPI_TxHalfCpltCallback()
bogdanm	0:9b334a45a8ff	410	(++) HAL_SPI_RxHalfCpltCallback()
bogdanm	0:9b334a45a8ff	411	(++) HAL_SPI_TxRxHalfCpltCallback()
bogdanm	0:9b334a45a8ff	412	(++) HAL_SPI_ErrorCallback()
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414	@endverbatim
bogdanm	0:9b334a45a8ff	415	* @{
bogdanm	0:9b334a45a8ff	416	*/
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	/**
bogdanm	0:9b334a45a8ff	419	* @brief Transmit an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	420	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	421	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	422	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	423	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	424	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	425	* @retval HAL status
bogdanm	0:9b334a45a8ff	426	*/
bogdanm	0:9b334a45a8ff	427	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	428	{
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	431	{
bogdanm	0:9b334a45a8ff	432	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	433	{
bogdanm	0:9b334a45a8ff	434	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	435	}
bogdanm	0:9b334a45a8ff	436
bogdanm	0:9b334a45a8ff	437	/* Check the parameters */
bogdanm	0:9b334a45a8ff	438	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	439
bogdanm	0:9b334a45a8ff	440	/* Process Locked */
bogdanm	0:9b334a45a8ff	441	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	442
bogdanm	0:9b334a45a8ff	443	/* Configure communication */
bogdanm	0:9b334a45a8ff	444	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	445	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	446
bogdanm	0:9b334a45a8ff	447	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	448	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	449	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	450
bogdanm	0:9b334a45a8ff	451	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	452	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	453	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	454	hspi->pRxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	455	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	456	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	459	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	460	{
bogdanm	0:9b334a45a8ff	461	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	462	}
bogdanm	0:9b334a45a8ff	463
bogdanm	0:9b334a45a8ff	464	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	465	{
bogdanm	0:9b334a45a8ff	466	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	467	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	468	}
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	471	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	472	{
bogdanm	0:9b334a45a8ff	473	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	474	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	475	}
bogdanm	0:9b334a45a8ff	476
bogdanm	0:9b334a45a8ff	477	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	478	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	479	{
bogdanm	0:9b334a45a8ff	480	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
bogdanm	0:9b334a45a8ff	481	{
bogdanm	0:9b334a45a8ff	482	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	483	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	484	}
bogdanm	0:9b334a45a8ff	485
bogdanm	0:9b334a45a8ff	486	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	487	{
bogdanm	0:9b334a45a8ff	488	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	489	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	490	{
bogdanm	0:9b334a45a8ff	491	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	492	}
bogdanm	0:9b334a45a8ff	493	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	494	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	495	}
bogdanm	0:9b334a45a8ff	496	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	497	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	498	{
bogdanm	0:9b334a45a8ff	499	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	500	}
bogdanm	0:9b334a45a8ff	501	}
bogdanm	0:9b334a45a8ff	502	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	503	else
bogdanm	0:9b334a45a8ff	504	{
bogdanm	0:9b334a45a8ff	505	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
bogdanm	0:9b334a45a8ff	506	{
bogdanm	0:9b334a45a8ff	507	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	508	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	509	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	510	}
bogdanm	0:9b334a45a8ff	511
bogdanm	0:9b334a45a8ff	512	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	513	{
bogdanm	0:9b334a45a8ff	514	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	515	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	516	{
bogdanm	0:9b334a45a8ff	517	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	518	}
bogdanm	0:9b334a45a8ff	519	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	520	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	521	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	522	}
bogdanm	0:9b334a45a8ff	523	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	524	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	525	{
bogdanm	0:9b334a45a8ff	526	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	527	}
bogdanm	0:9b334a45a8ff	528	}
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	531	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	532	{
bogdanm	0:9b334a45a8ff	533	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	534	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	535	}
bogdanm	0:9b334a45a8ff	536
bogdanm	0:9b334a45a8ff	537	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	538	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	539	{
bogdanm	0:9b334a45a8ff	540	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	541	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	542	}
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	545	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	546	{
bogdanm	0:9b334a45a8ff	547	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	548	}
bogdanm	0:9b334a45a8ff	549
bogdanm	0:9b334a45a8ff	550	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	553	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	554
bogdanm	0:9b334a45a8ff	555	return HAL_OK;
bogdanm	0:9b334a45a8ff	556	}
bogdanm	0:9b334a45a8ff	557	else
bogdanm	0:9b334a45a8ff	558	{
bogdanm	0:9b334a45a8ff	559	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	560	}
bogdanm	0:9b334a45a8ff	561	}
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	/**
bogdanm	0:9b334a45a8ff	564	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	565	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	566	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	567	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	568	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	569	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	570	* @retval HAL status
bogdanm	0:9b334a45a8ff	571	*/
bogdanm	0:9b334a45a8ff	572	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	573	{
bogdanm	0:9b334a45a8ff	574	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	575
bogdanm	0:9b334a45a8ff	576	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	577	{
bogdanm	0:9b334a45a8ff	578	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	579	{
bogdanm	0:9b334a45a8ff	580	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	581	}
bogdanm	0:9b334a45a8ff	582
bogdanm	0:9b334a45a8ff	583	/* Process Locked */
bogdanm	0:9b334a45a8ff	584	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	585
bogdanm	0:9b334a45a8ff	586	/* Configure communication */
bogdanm	0:9b334a45a8ff	587	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	588	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	589
bogdanm	0:9b334a45a8ff	590	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	591	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	592	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	593
bogdanm	0:9b334a45a8ff	594	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	595	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	596	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	597	hspi->pTxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	598	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	599	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	602	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	603	{
bogdanm	0:9b334a45a8ff	604	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	605	}
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	608	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	609	{
bogdanm	0:9b334a45a8ff	610	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	611	}
bogdanm	0:9b334a45a8ff	612
bogdanm	0:9b334a45a8ff	613	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	614	{
bogdanm	0:9b334a45a8ff	615	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	616	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	617
bogdanm	0:9b334a45a8ff	618	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	619	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
bogdanm	0:9b334a45a8ff	620	}
bogdanm	0:9b334a45a8ff	621
bogdanm	0:9b334a45a8ff	622	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	623	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	624	{
bogdanm	0:9b334a45a8ff	625	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	626	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	627	}
bogdanm	0:9b334a45a8ff	628
bogdanm	0:9b334a45a8ff	629	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	630	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	631	{
bogdanm	0:9b334a45a8ff	632	while(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	633	{
bogdanm	0:9b334a45a8ff	634	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	635	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	636	{
bogdanm	0:9b334a45a8ff	637	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	638	}
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	641	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	642	}
bogdanm	0:9b334a45a8ff	643	/* Enable CRC Reception */
bogdanm	0:9b334a45a8ff	644	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	645	{
bogdanm	0:9b334a45a8ff	646	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	647	}
bogdanm	0:9b334a45a8ff	648	}
bogdanm	0:9b334a45a8ff	649	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	650	else
bogdanm	0:9b334a45a8ff	651	{
bogdanm	0:9b334a45a8ff	652	while(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	653	{
bogdanm	0:9b334a45a8ff	654	/* Wait until RXNE flag is set to read data */
bogdanm	0:9b334a45a8ff	655	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	656	{
bogdanm	0:9b334a45a8ff	657	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	658	}
bogdanm	0:9b334a45a8ff	659
bogdanm	0:9b334a45a8ff	660	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	661	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	662	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	663	}
bogdanm	0:9b334a45a8ff	664	/* Enable CRC Reception */
bogdanm	0:9b334a45a8ff	665	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	666	{
bogdanm	0:9b334a45a8ff	667	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	668	}
bogdanm	0:9b334a45a8ff	669	}
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	672	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	673	{
bogdanm	0:9b334a45a8ff	674	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	675	}
bogdanm	0:9b334a45a8ff	676
bogdanm	0:9b334a45a8ff	677	/* Receive last data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	678	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	679	{
bogdanm	0:9b334a45a8ff	680	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	681	}
bogdanm	0:9b334a45a8ff	682	/* Receive last data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	683	else
bogdanm	0:9b334a45a8ff	684	{
bogdanm	0:9b334a45a8ff	685	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	686	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	687	}
bogdanm	0:9b334a45a8ff	688	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	/* If CRC computation is enabled */
bogdanm	0:9b334a45a8ff	691	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	692	{
bogdanm	0:9b334a45a8ff	693	/* Wait until RXNE flag is set: CRC Received */
bogdanm	0:9b334a45a8ff	694	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	695	{
bogdanm	0:9b334a45a8ff	696	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	697	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	698	}
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	/* Read CRC to clear RXNE flag */
bogdanm	0:9b334a45a8ff	701	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	702	UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
bogdanm	0:9b334a45a8ff	703	}
bogdanm	0:9b334a45a8ff	704
bogdanm	0:9b334a45a8ff	705	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	706	{
bogdanm	0:9b334a45a8ff	707	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	708	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	709	}
bogdanm	0:9b334a45a8ff	710
bogdanm	0:9b334a45a8ff	711	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	712
bogdanm	0:9b334a45a8ff	713	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	714	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
bogdanm	0:9b334a45a8ff	715	{
bogdanm	0:9b334a45a8ff	716	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	717
bogdanm	0:9b334a45a8ff	718	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	719	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	720
bogdanm	0:9b334a45a8ff	721	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	722	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	725	}
bogdanm	0:9b334a45a8ff	726
bogdanm	0:9b334a45a8ff	727	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	728	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	729
bogdanm	0:9b334a45a8ff	730	return HAL_OK;
bogdanm	0:9b334a45a8ff	731	}
bogdanm	0:9b334a45a8ff	732	else
bogdanm	0:9b334a45a8ff	733	{
bogdanm	0:9b334a45a8ff	734	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	735	}
bogdanm	0:9b334a45a8ff	736	}
bogdanm	0:9b334a45a8ff	737
bogdanm	0:9b334a45a8ff	738	/**
bogdanm	0:9b334a45a8ff	739	* @brief Transmit and Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	740	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	741	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	742	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	743	* @param pRxData: pointer to reception data buffer to be
bogdanm	0:9b334a45a8ff	744	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	745	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	746	* @retval HAL status
bogdanm	0:9b334a45a8ff	747	*/
bogdanm	0:9b334a45a8ff	748	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	749	{
bogdanm	0:9b334a45a8ff	750	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	751
bogdanm	0:9b334a45a8ff	752	if((hspi->State == HAL_SPI_STATE_READY) \|\| (hspi->State == HAL_SPI_STATE_BUSY_RX))
bogdanm	0:9b334a45a8ff	753	{
bogdanm	0:9b334a45a8ff	754	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	755	{
bogdanm	0:9b334a45a8ff	756	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	757	}
bogdanm	0:9b334a45a8ff	758
bogdanm	0:9b334a45a8ff	759	/* Check the parameters */
bogdanm	0:9b334a45a8ff	760	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762	/* Process Locked */
bogdanm	0:9b334a45a8ff	763	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	764
bogdanm	0:9b334a45a8ff	765	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	766	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	767	{
bogdanm	0:9b334a45a8ff	768	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	769	}
bogdanm	0:9b334a45a8ff	770
bogdanm	0:9b334a45a8ff	771	/* Configure communication */
bogdanm	0:9b334a45a8ff	772	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	773
bogdanm	0:9b334a45a8ff	774	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	775	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	776	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	777
bogdanm	0:9b334a45a8ff	778	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	779	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	780	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	781
bogdanm	0:9b334a45a8ff	782	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	783	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	784	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	785
bogdanm	0:9b334a45a8ff	786	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	787	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	788	{
bogdanm	0:9b334a45a8ff	789	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	790	}
bogdanm	0:9b334a45a8ff	791
bogdanm	0:9b334a45a8ff	792	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	793	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	794	{
bogdanm	0:9b334a45a8ff	795	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	796	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	797	}
bogdanm	0:9b334a45a8ff	798
bogdanm	0:9b334a45a8ff	799	/* Transmit and Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	800	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
bogdanm	0:9b334a45a8ff	801	{
bogdanm	0:9b334a45a8ff	802	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
bogdanm	0:9b334a45a8ff	803	{
bogdanm	0:9b334a45a8ff	804	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	805	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	806	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	807	}
bogdanm	0:9b334a45a8ff	808	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	809	{
bogdanm	0:9b334a45a8ff	810	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	811	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	812	{
bogdanm	0:9b334a45a8ff	813	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	814	}
bogdanm	0:9b334a45a8ff	815
bogdanm	0:9b334a45a8ff	816	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	817	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	818	{
bogdanm	0:9b334a45a8ff	819	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	820	}
bogdanm	0:9b334a45a8ff	821
bogdanm	0:9b334a45a8ff	822	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	823	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	824	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	825	}
bogdanm	0:9b334a45a8ff	826	else
bogdanm	0:9b334a45a8ff	827	{
bogdanm	0:9b334a45a8ff	828	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	829	{
bogdanm	0:9b334a45a8ff	830	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	831	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	832	{
bogdanm	0:9b334a45a8ff	833	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	834	}
bogdanm	0:9b334a45a8ff	835
bogdanm	0:9b334a45a8ff	836	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	837	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	838	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	841	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	842	{
bogdanm	0:9b334a45a8ff	843	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	844	}
bogdanm	0:9b334a45a8ff	845
bogdanm	0:9b334a45a8ff	846	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	847	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	848	{
bogdanm	0:9b334a45a8ff	849	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	850	}
bogdanm	0:9b334a45a8ff	851
bogdanm	0:9b334a45a8ff	852	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	853	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	854	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	855	}
bogdanm	0:9b334a45a8ff	856	/* Receive the last byte */
bogdanm	0:9b334a45a8ff	857	if(hspi->Init.Mode == SPI_MODE_SLAVE)
bogdanm	0:9b334a45a8ff	858	{
bogdanm	0:9b334a45a8ff	859	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	860	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	861	{
bogdanm	0:9b334a45a8ff	862	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	863	}
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	866	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	867	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	868	}
bogdanm	0:9b334a45a8ff	869	}
bogdanm	0:9b334a45a8ff	870	}
bogdanm	0:9b334a45a8ff	871	/* Transmit and Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	872	else
bogdanm	0:9b334a45a8ff	873	{
bogdanm	0:9b334a45a8ff	874	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
bogdanm	0:9b334a45a8ff	875	{
bogdanm	0:9b334a45a8ff	876	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	877	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	878	}
bogdanm	0:9b334a45a8ff	879	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	880	{
bogdanm	0:9b334a45a8ff	881	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	882	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	883	{
bogdanm	0:9b334a45a8ff	884	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	885	}
bogdanm	0:9b334a45a8ff	886
bogdanm	0:9b334a45a8ff	887	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	888	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	889	{
bogdanm	0:9b334a45a8ff	890	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	891	}
bogdanm	0:9b334a45a8ff	892
bogdanm	0:9b334a45a8ff	893	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	894	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	895	}
bogdanm	0:9b334a45a8ff	896	else
bogdanm	0:9b334a45a8ff	897	{
bogdanm	0:9b334a45a8ff	898	while(hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	899	{
bogdanm	0:9b334a45a8ff	900	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	901	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	902	{
bogdanm	0:9b334a45a8ff	903	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	904	}
bogdanm	0:9b334a45a8ff	905
bogdanm	0:9b334a45a8ff	906	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	907	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	908
bogdanm	0:9b334a45a8ff	909	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	910	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	911	{
bogdanm	0:9b334a45a8ff	912	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	913	}
bogdanm	0:9b334a45a8ff	914
bogdanm	0:9b334a45a8ff	915	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	916	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	917	{
bogdanm	0:9b334a45a8ff	918	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	919	}
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	922	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	923	}
bogdanm	0:9b334a45a8ff	924	if(hspi->Init.Mode == SPI_MODE_SLAVE)
bogdanm	0:9b334a45a8ff	925	{
bogdanm	0:9b334a45a8ff	926	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	927	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	928	{
bogdanm	0:9b334a45a8ff	929	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	930	}
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	933	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	934	}
bogdanm	0:9b334a45a8ff	935	}
bogdanm	0:9b334a45a8ff	936	}
bogdanm	0:9b334a45a8ff	937
bogdanm	0:9b334a45a8ff	938	/* Read CRC from DR to close CRC calculation process */
bogdanm	0:9b334a45a8ff	939	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	940	{
bogdanm	0:9b334a45a8ff	941	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	942	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	943	{
bogdanm	0:9b334a45a8ff	944	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	945	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	946	}
bogdanm	0:9b334a45a8ff	947	/* Read CRC */
bogdanm	0:9b334a45a8ff	948	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	949	UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
bogdanm	0:9b334a45a8ff	950	}
bogdanm	0:9b334a45a8ff	951
bogdanm	0:9b334a45a8ff	952	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	953	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	954	{
bogdanm	0:9b334a45a8ff	955	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	956	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	957	}
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	960
bogdanm	0:9b334a45a8ff	961	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	962	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
bogdanm	0:9b334a45a8ff	963	{
bogdanm	0:9b334a45a8ff	964	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	965
bogdanm	0:9b334a45a8ff	966	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	967
bogdanm	0:9b334a45a8ff	968	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	969	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	970
bogdanm	0:9b334a45a8ff	971	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	972	}
bogdanm	0:9b334a45a8ff	973
bogdanm	0:9b334a45a8ff	974	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	975	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	976
bogdanm	0:9b334a45a8ff	977	return HAL_OK;
bogdanm	0:9b334a45a8ff	978	}
bogdanm	0:9b334a45a8ff	979	else
bogdanm	0:9b334a45a8ff	980	{
bogdanm	0:9b334a45a8ff	981	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	982	}
bogdanm	0:9b334a45a8ff	983	}
bogdanm	0:9b334a45a8ff	984
bogdanm	0:9b334a45a8ff	985	/**
bogdanm	0:9b334a45a8ff	986	* @brief Transmit an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	987	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	988	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	989	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	990	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	991	* @retval HAL status
bogdanm	0:9b334a45a8ff	992	*/
bogdanm	0:9b334a45a8ff	993	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	994	{
bogdanm	0:9b334a45a8ff	995	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	996	{
bogdanm	0:9b334a45a8ff	997	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	998	{
bogdanm	0:9b334a45a8ff	999	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1000	}
bogdanm	0:9b334a45a8ff	1001
bogdanm	0:9b334a45a8ff	1002	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1003	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1004
bogdanm	0:9b334a45a8ff	1005	/* Process Locked */
bogdanm	0:9b334a45a8ff	1006	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008	/* Configure communication */
bogdanm	0:9b334a45a8ff	1009	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	1010	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	hspi->TxISR = &SPI_TxISR;
bogdanm	0:9b334a45a8ff	1013	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1014	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1015	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1016
bogdanm	0:9b334a45a8ff	1017	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1018	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1019	hspi->pRxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1020	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	1021	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1024	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1025	{
bogdanm	0:9b334a45a8ff	1026	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1027	}
bogdanm	0:9b334a45a8ff	1028
bogdanm	0:9b334a45a8ff	1029	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1030	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1031	{
bogdanm	0:9b334a45a8ff	1032	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1033	}
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1036	{
bogdanm	0:9b334a45a8ff	1037	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
bogdanm	0:9b334a45a8ff	1038	}
bogdanm	0:9b334a45a8ff	1039	else
bogdanm	0:9b334a45a8ff	1040	{
bogdanm	0:9b334a45a8ff	1041	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1042	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1043	}
bogdanm	0:9b334a45a8ff	1044	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1045	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1046
bogdanm	0:9b334a45a8ff	1047	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1048	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1049	{
bogdanm	0:9b334a45a8ff	1050	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1051	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1052	}
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	return HAL_OK;
bogdanm	0:9b334a45a8ff	1055	}
bogdanm	0:9b334a45a8ff	1056	else
bogdanm	0:9b334a45a8ff	1057	{
bogdanm	0:9b334a45a8ff	1058	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1059	}
bogdanm	0:9b334a45a8ff	1060	}
bogdanm	0:9b334a45a8ff	1061
bogdanm	0:9b334a45a8ff	1062	/**
bogdanm	0:9b334a45a8ff	1063	* @brief Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1064	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1065	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1066	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1067	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1068	* @retval HAL status
bogdanm	0:9b334a45a8ff	1069	*/
bogdanm	0:9b334a45a8ff	1070	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1071	{
bogdanm	0:9b334a45a8ff	1072	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1073	{
bogdanm	0:9b334a45a8ff	1074	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1075	{
bogdanm	0:9b334a45a8ff	1076	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1077	}
bogdanm	0:9b334a45a8ff	1078
bogdanm	0:9b334a45a8ff	1079	/* Process Locked */
bogdanm	0:9b334a45a8ff	1080	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1081
bogdanm	0:9b334a45a8ff	1082	/* Configure communication */
bogdanm	0:9b334a45a8ff	1083	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1084	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1085
bogdanm	0:9b334a45a8ff	1086	hspi->RxISR = &SPI_RxISR;
bogdanm	0:9b334a45a8ff	1087	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1088	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1089	hspi->RxXferCount = Size ;
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1092	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1093	hspi->pTxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1094	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1095	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1096
bogdanm	0:9b334a45a8ff	1097	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1098	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1099	{
bogdanm	0:9b334a45a8ff	1100	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1101	}
bogdanm	0:9b334a45a8ff	1102	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
bogdanm	0:9b334a45a8ff	1103	{
bogdanm	0:9b334a45a8ff	1104	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1105	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1106
bogdanm	0:9b334a45a8ff	1107	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	1108	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
bogdanm	0:9b334a45a8ff	1109	}
bogdanm	0:9b334a45a8ff	1110
bogdanm	0:9b334a45a8ff	1111	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1112	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1113	{
bogdanm	0:9b334a45a8ff	1114	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1115	}
bogdanm	0:9b334a45a8ff	1116
bogdanm	0:9b334a45a8ff	1117	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1118	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1121	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	/* Note : The SPI must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1124	to avoid the risk of SPI interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1125	process unlock */
bogdanm	0:9b334a45a8ff	1126
bogdanm	0:9b334a45a8ff	1127	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1128	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1129	{
bogdanm	0:9b334a45a8ff	1130	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1131	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1132	}
bogdanm	0:9b334a45a8ff	1133
bogdanm	0:9b334a45a8ff	1134	return HAL_OK;
bogdanm	0:9b334a45a8ff	1135	}
bogdanm	0:9b334a45a8ff	1136	else
bogdanm	0:9b334a45a8ff	1137	{
bogdanm	0:9b334a45a8ff	1138	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1139	}
bogdanm	0:9b334a45a8ff	1140	}
bogdanm	0:9b334a45a8ff	1141
bogdanm	0:9b334a45a8ff	1142	/**
bogdanm	0:9b334a45a8ff	1143	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1144	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1145	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1146	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1147	* @param pRxData: pointer to reception data buffer to be
bogdanm	0:9b334a45a8ff	1148	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1149	* @retval HAL status
bogdanm	0:9b334a45a8ff	1150	*/
bogdanm	0:9b334a45a8ff	1151	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1152	{
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
bogdanm	0:9b334a45a8ff	1155	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1156	{
bogdanm	0:9b334a45a8ff	1157	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1158	{
bogdanm	0:9b334a45a8ff	1159	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1160	}
bogdanm	0:9b334a45a8ff	1161
bogdanm	0:9b334a45a8ff	1162	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1163	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	/* Process locked */
bogdanm	0:9b334a45a8ff	1166	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1167
bogdanm	0:9b334a45a8ff	1168	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	1169	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1170	{
bogdanm	0:9b334a45a8ff	1171	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1172	}
bogdanm	0:9b334a45a8ff	1173
bogdanm	0:9b334a45a8ff	1174	/* Configure communication */
bogdanm	0:9b334a45a8ff	1175	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1176
bogdanm	0:9b334a45a8ff	1177	hspi->TxISR = &SPI_TxISR;
bogdanm	0:9b334a45a8ff	1178	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	1179	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1180	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	hspi->RxISR = &SPI_2LinesRxISR;
bogdanm	0:9b334a45a8ff	1183	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	1184	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1185	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1188	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1189	{
bogdanm	0:9b334a45a8ff	1190	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1191	}
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	/* Enable TXE, RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1194	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1197	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1198
bogdanm	0:9b334a45a8ff	1199	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1200	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1201	{
bogdanm	0:9b334a45a8ff	1202	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1203	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1204	}
bogdanm	0:9b334a45a8ff	1205
bogdanm	0:9b334a45a8ff	1206	return HAL_OK;
bogdanm	0:9b334a45a8ff	1207	}
bogdanm	0:9b334a45a8ff	1208	else
bogdanm	0:9b334a45a8ff	1209	{
bogdanm	0:9b334a45a8ff	1210	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1211	}
bogdanm	0:9b334a45a8ff	1212	}
bogdanm	0:9b334a45a8ff	1213
bogdanm	0:9b334a45a8ff	1214	/**
bogdanm	0:9b334a45a8ff	1215	* @brief Transmit an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1216	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1217	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1218	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1219	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1220	* @retval HAL status
bogdanm	0:9b334a45a8ff	1221	*/
bogdanm	0:9b334a45a8ff	1222	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1223	{
bogdanm	0:9b334a45a8ff	1224	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1225	{
bogdanm	0:9b334a45a8ff	1226	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1227	{
bogdanm	0:9b334a45a8ff	1228	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1229	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1230	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1231	}
bogdanm	0:9b334a45a8ff	1232
bogdanm	0:9b334a45a8ff	1233	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1234	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1235
bogdanm	0:9b334a45a8ff	1236	/* Process Locked */
bogdanm	0:9b334a45a8ff	1237	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1238
bogdanm	0:9b334a45a8ff	1239	/* Configure communication */
bogdanm	0:9b334a45a8ff	1240	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	1241	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1242
bogdanm	0:9b334a45a8ff	1243	hspi->pTxBuffPtr = (uint8_t*)pData;
bogdanm	0:9b334a45a8ff	1244	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1245	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1246
bogdanm	0:9b334a45a8ff	1247	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1248	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1249	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1250
bogdanm	0:9b334a45a8ff	1251	hspi->pRxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1252	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	1253	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1254
bogdanm	0:9b334a45a8ff	1255	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1256	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1257	{
bogdanm	0:9b334a45a8ff	1258	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1259	}
bogdanm	0:9b334a45a8ff	1260
bogdanm	0:9b334a45a8ff	1261	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1262	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1263	{
bogdanm	0:9b334a45a8ff	1264	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1265	}
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267	/* Set the SPI TxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1268	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
bogdanm	0:9b334a45a8ff	1269
bogdanm	0:9b334a45a8ff	1270	/* Set the SPI TxDMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1271	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
bogdanm	0:9b334a45a8ff	1272
bogdanm	0:9b334a45a8ff	1273	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1274	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	/* Reset content of SPI RxDMA descriptor */
bogdanm	0:9b334a45a8ff	1277	hspi->hdmarx->XferHalfCpltCallback = (void ()(DMA_HandleTypeDef ))NULL;
bogdanm	0:9b334a45a8ff	1278	hspi->hdmarx->XferCpltCallback = (void ()(DMA_HandleTypeDef ))NULL;
bogdanm	0:9b334a45a8ff	1279	hspi->hdmarx->XferErrorCallback = (void ()(DMA_HandleTypeDef ))NULL;
bogdanm	0:9b334a45a8ff	1280
bogdanm	0:9b334a45a8ff	1281	/* Enable the Tx DMA Channel */
bogdanm	0:9b334a45a8ff	1282	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1283
bogdanm	0:9b334a45a8ff	1284	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1285	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1288	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1289
bogdanm	0:9b334a45a8ff	1290	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1291	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1292	{
bogdanm	0:9b334a45a8ff	1293	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1294	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1295	}
bogdanm	0:9b334a45a8ff	1296
bogdanm	0:9b334a45a8ff	1297	return HAL_OK;
bogdanm	0:9b334a45a8ff	1298	}
bogdanm	0:9b334a45a8ff	1299	else
bogdanm	0:9b334a45a8ff	1300	{
bogdanm	0:9b334a45a8ff	1301	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1302	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1303	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1304	}
bogdanm	0:9b334a45a8ff	1305	}
bogdanm	0:9b334a45a8ff	1306
bogdanm	0:9b334a45a8ff	1307	/**
bogdanm	0:9b334a45a8ff	1308	* @brief Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1309	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1310	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1311	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1312	* @note When the CRC feature is enabled the pData Length must be Size + 1.
bogdanm	0:9b334a45a8ff	1313	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1314	* @retval HAL status
bogdanm	0:9b334a45a8ff	1315	*/
bogdanm	0:9b334a45a8ff	1316	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1317	{
bogdanm	0:9b334a45a8ff	1318	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1319	{
bogdanm	0:9b334a45a8ff	1320	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1321	{
bogdanm	0:9b334a45a8ff	1322	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1323	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1324	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1325	}
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	/* Process Locked */
bogdanm	0:9b334a45a8ff	1328	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1329
bogdanm	0:9b334a45a8ff	1330	/* Configure communication */
bogdanm	0:9b334a45a8ff	1331	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1332	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	hspi->pRxBuffPtr = (uint8_t*)pData;
bogdanm	0:9b334a45a8ff	1335	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1336	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1337
bogdanm	0:9b334a45a8ff	1338	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1339	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1340	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	hspi->pTxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1343	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1344	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1345
bogdanm	0:9b334a45a8ff	1346	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1347	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1348	{
bogdanm	0:9b334a45a8ff	1349	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1350	}
bogdanm	0:9b334a45a8ff	1351	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
bogdanm	0:9b334a45a8ff	1352	{
bogdanm	0:9b334a45a8ff	1353	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1354	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1355
bogdanm	0:9b334a45a8ff	1356	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
bogdanm	0:9b334a45a8ff	1357	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
bogdanm	0:9b334a45a8ff	1358	}
bogdanm	0:9b334a45a8ff	1359
bogdanm	0:9b334a45a8ff	1360	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1361	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1362	{
bogdanm	0:9b334a45a8ff	1363	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1364	}
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	/* Set the SPI RxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1367	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1368
bogdanm	0:9b334a45a8ff	1369	/* Set the SPI Rx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1370	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1371
bogdanm	0:9b334a45a8ff	1372	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1373	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1374
bogdanm	0:9b334a45a8ff	1375	/* Reset content of SPI TxDMA descriptor */
bogdanm	0:9b334a45a8ff	1376	hspi->hdmatx->XferHalfCpltCallback = (void ()(DMA_HandleTypeDef ))NULL;
bogdanm	0:9b334a45a8ff	1377	hspi->hdmatx->XferCpltCallback = (void ()(DMA_HandleTypeDef ))NULL;
bogdanm	0:9b334a45a8ff	1378	hspi->hdmatx->XferErrorCallback = (void ()(DMA_HandleTypeDef ))NULL;
bogdanm	0:9b334a45a8ff	1379
bogdanm	0:9b334a45a8ff	1380	/* Enable the Rx DMA Channel */
bogdanm	0:9b334a45a8ff	1381	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1382
bogdanm	0:9b334a45a8ff	1383	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1384	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1385
bogdanm	0:9b334a45a8ff	1386	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1387	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1388
bogdanm	0:9b334a45a8ff	1389	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1390	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1391	{
bogdanm	0:9b334a45a8ff	1392	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1393	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1394	}
bogdanm	0:9b334a45a8ff	1395
bogdanm	0:9b334a45a8ff	1396	return HAL_OK;
bogdanm	0:9b334a45a8ff	1397	}
bogdanm	0:9b334a45a8ff	1398	else
bogdanm	0:9b334a45a8ff	1399	{
bogdanm	0:9b334a45a8ff	1400	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1401	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1402	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1403	}
bogdanm	0:9b334a45a8ff	1404	}
bogdanm	0:9b334a45a8ff	1405
bogdanm	0:9b334a45a8ff	1406	/**
bogdanm	0:9b334a45a8ff	1407	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1408	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1409	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1410	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1411	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	1412	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
bogdanm	0:9b334a45a8ff	1413	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1414	* @retval HAL status
bogdanm	0:9b334a45a8ff	1415	*/
bogdanm	0:9b334a45a8ff	1416	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1417	{
bogdanm	0:9b334a45a8ff	1418	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
bogdanm	0:9b334a45a8ff	1419	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1420	{
bogdanm	0:9b334a45a8ff	1421	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1422	{
bogdanm	0:9b334a45a8ff	1423	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1424	}
bogdanm	0:9b334a45a8ff	1425
bogdanm	0:9b334a45a8ff	1426	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1427	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1428
bogdanm	0:9b334a45a8ff	1429	/* Process locked */
bogdanm	0:9b334a45a8ff	1430	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1431
bogdanm	0:9b334a45a8ff	1432	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
bogdanm	0:9b334a45a8ff	1433	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1434	{
bogdanm	0:9b334a45a8ff	1435	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1436	}
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	/* Configure communication */
bogdanm	0:9b334a45a8ff	1439	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1440
bogdanm	0:9b334a45a8ff	1441	hspi->pTxBuffPtr = (uint8_t*)pTxData;
bogdanm	0:9b334a45a8ff	1442	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1443	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1444
bogdanm	0:9b334a45a8ff	1445	hspi->pRxBuffPtr = (uint8_t*)pRxData;
bogdanm	0:9b334a45a8ff	1446	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1447	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	/Init field not used in handle to zero /
bogdanm	0:9b334a45a8ff	1450	hspi->RxISR = 0;
bogdanm	0:9b334a45a8ff	1451	hspi->TxISR = 0;
bogdanm	0:9b334a45a8ff	1452
bogdanm	0:9b334a45a8ff	1453	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1454	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1455	{
bogdanm	0:9b334a45a8ff	1456	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1457	}
bogdanm	0:9b334a45a8ff	1458
bogdanm	0:9b334a45a8ff	1459	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1460	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1461	{
bogdanm	0:9b334a45a8ff	1462	/* Set the SPI Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1463	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1464
bogdanm	0:9b334a45a8ff	1465	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1466	}
bogdanm	0:9b334a45a8ff	1467	else
bogdanm	0:9b334a45a8ff	1468	{
bogdanm	0:9b334a45a8ff	1469	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1470	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1471
bogdanm	0:9b334a45a8ff	1472	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1473	}
bogdanm	0:9b334a45a8ff	1474
bogdanm	0:9b334a45a8ff	1475	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1476	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1477
bogdanm	0:9b334a45a8ff	1478	/* Enable the Rx DMA Channel */
bogdanm	0:9b334a45a8ff	1479	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1480
bogdanm	0:9b334a45a8ff	1481	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1482	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1483
bogdanm	0:9b334a45a8ff	1484	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
bogdanm	0:9b334a45a8ff	1485	is performed in DMA reception complete callback */
bogdanm	0:9b334a45a8ff	1486	hspi->hdmatx->XferHalfCpltCallback = (void ()(DMA_HandleTypeDef ))NULL;
bogdanm	0:9b334a45a8ff	1487	hspi->hdmatx->XferCpltCallback = (void ()(DMA_HandleTypeDef ))NULL;
bogdanm	0:9b334a45a8ff	1488
bogdanm	0:9b334a45a8ff	1489	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1490	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1491
bogdanm	0:9b334a45a8ff	1492	/* Enable the Tx DMA Channel */
bogdanm	0:9b334a45a8ff	1493	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1494
bogdanm	0:9b334a45a8ff	1495	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1496	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1497	{
bogdanm	0:9b334a45a8ff	1498	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1499	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1500	}
bogdanm	0:9b334a45a8ff	1501
bogdanm	0:9b334a45a8ff	1502	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1503	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1506	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1507
bogdanm	0:9b334a45a8ff	1508	return HAL_OK;
bogdanm	0:9b334a45a8ff	1509	}
bogdanm	0:9b334a45a8ff	1510	else
bogdanm	0:9b334a45a8ff	1511	{
bogdanm	0:9b334a45a8ff	1512	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1513	}
bogdanm	0:9b334a45a8ff	1514	}
bogdanm	0:9b334a45a8ff	1515
bogdanm	0:9b334a45a8ff	1516
bogdanm	0:9b334a45a8ff	1517	/**
bogdanm	0:9b334a45a8ff	1518	* @brief Pauses the DMA Transfer.
bogdanm	0:9b334a45a8ff	1519	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1520	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1521	* @retval HAL status
bogdanm	0:9b334a45a8ff	1522	*/
bogdanm	0:9b334a45a8ff	1523	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1524	{
bogdanm	0:9b334a45a8ff	1525	/* Process Locked */
bogdanm	0:9b334a45a8ff	1526	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1527
bogdanm	0:9b334a45a8ff	1528	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1529	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1530	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1531
bogdanm	0:9b334a45a8ff	1532	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1533	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1534
bogdanm	0:9b334a45a8ff	1535	return HAL_OK;
bogdanm	0:9b334a45a8ff	1536	}
bogdanm	0:9b334a45a8ff	1537
bogdanm	0:9b334a45a8ff	1538	/**
bogdanm	0:9b334a45a8ff	1539	* @brief Resumes the DMA Transfer.
bogdanm	0:9b334a45a8ff	1540	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1541	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1542	* @retval HAL status
bogdanm	0:9b334a45a8ff	1543	*/
bogdanm	0:9b334a45a8ff	1544	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1545	{
bogdanm	0:9b334a45a8ff	1546	/* Process Locked */
bogdanm	0:9b334a45a8ff	1547	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1548
bogdanm	0:9b334a45a8ff	1549	/* Enable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1550	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1551	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1552
bogdanm	0:9b334a45a8ff	1553	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1554	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1555
bogdanm	0:9b334a45a8ff	1556	return HAL_OK;
bogdanm	0:9b334a45a8ff	1557	}
bogdanm	0:9b334a45a8ff	1558
bogdanm	0:9b334a45a8ff	1559	/**
bogdanm	0:9b334a45a8ff	1560	* @brief Stops the DMA Transfer.
bogdanm	0:9b334a45a8ff	1561	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1562	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1563	* @retval HAL status
bogdanm	0:9b334a45a8ff	1564	*/
bogdanm	0:9b334a45a8ff	1565	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1566	{
bogdanm	0:9b334a45a8ff	1567	/* The Lock is not implemented on this API to allow the user application
bogdanm	0:9b334a45a8ff	1568	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
bogdanm	0:9b334a45a8ff	1569	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
bogdanm	0:9b334a45a8ff	1570	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
bogdanm	0:9b334a45a8ff	1571	*/
bogdanm	0:9b334a45a8ff	1572
bogdanm	0:9b334a45a8ff	1573	/* Abort the SPI DMA tx Channel */
bogdanm	0:9b334a45a8ff	1574	if(hspi->hdmatx != NULL)
bogdanm	0:9b334a45a8ff	1575	{
bogdanm	0:9b334a45a8ff	1576	HAL_DMA_Abort(hspi->hdmatx);
bogdanm	0:9b334a45a8ff	1577	}
bogdanm	0:9b334a45a8ff	1578	/* Abort the SPI DMA rx Channel */
bogdanm	0:9b334a45a8ff	1579	if(hspi->hdmarx != NULL)
bogdanm	0:9b334a45a8ff	1580	{
bogdanm	0:9b334a45a8ff	1581	HAL_DMA_Abort(hspi->hdmarx);
bogdanm	0:9b334a45a8ff	1582	}
bogdanm	0:9b334a45a8ff	1583
bogdanm	0:9b334a45a8ff	1584	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1585	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1586	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1587
bogdanm	0:9b334a45a8ff	1588	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1589
bogdanm	0:9b334a45a8ff	1590	return HAL_OK;
bogdanm	0:9b334a45a8ff	1591	}
bogdanm	0:9b334a45a8ff	1592
bogdanm	0:9b334a45a8ff	1593	/**
bogdanm	0:9b334a45a8ff	1594	* @brief This function handles SPI interrupt request.
bogdanm	0:9b334a45a8ff	1595	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1596	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1597	* @retval HAL status
bogdanm	0:9b334a45a8ff	1598	*/
bogdanm	0:9b334a45a8ff	1599	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1600	{
bogdanm	0:9b334a45a8ff	1601	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
bogdanm	0:9b334a45a8ff	1602	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
bogdanm	0:9b334a45a8ff	1603	{
bogdanm	0:9b334a45a8ff	1604	hspi->RxISR(hspi);
bogdanm	0:9b334a45a8ff	1605	return;
bogdanm	0:9b334a45a8ff	1606	}
bogdanm	0:9b334a45a8ff	1607
bogdanm	0:9b334a45a8ff	1608	/* SPI in mode Tramitter ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1609	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
bogdanm	0:9b334a45a8ff	1610	{
bogdanm	0:9b334a45a8ff	1611	hspi->TxISR(hspi);
bogdanm	0:9b334a45a8ff	1612	return;
bogdanm	0:9b334a45a8ff	1613	}
bogdanm	0:9b334a45a8ff	1614
bogdanm	0:9b334a45a8ff	1615	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
bogdanm	0:9b334a45a8ff	1616	{
bogdanm	0:9b334a45a8ff	1617	/* SPI CRC error interrupt occurred ---------------------------------------*/
bogdanm	0:9b334a45a8ff	1618	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1619	{
bogdanm	0:9b334a45a8ff	1620	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	1621	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1622	}
bogdanm	0:9b334a45a8ff	1623	/* SPI Mode Fault error interrupt occurred --------------------------------*/
bogdanm	0:9b334a45a8ff	1624	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
bogdanm	0:9b334a45a8ff	1625	{
bogdanm	0:9b334a45a8ff	1626	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
bogdanm	0:9b334a45a8ff	1627	__HAL_SPI_CLEAR_MODFFLAG(hspi);
bogdanm	0:9b334a45a8ff	1628	}
bogdanm	0:9b334a45a8ff	1629
bogdanm	0:9b334a45a8ff	1630	/* SPI Overrun error interrupt occurred -----------------------------------*/
bogdanm	0:9b334a45a8ff	1631	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
bogdanm	0:9b334a45a8ff	1632	{
bogdanm	0:9b334a45a8ff	1633	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	1634	{
bogdanm	0:9b334a45a8ff	1635	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
bogdanm	0:9b334a45a8ff	1636	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1637	}
bogdanm	0:9b334a45a8ff	1638	}
bogdanm	0:9b334a45a8ff	1639
bogdanm	0:9b334a45a8ff	1640	/* SPI Frame error interrupt occurred -------------------------------------*/
bogdanm	0:9b334a45a8ff	1641	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
bogdanm	0:9b334a45a8ff	1642	{
bogdanm	0:9b334a45a8ff	1643	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
bogdanm	0:9b334a45a8ff	1644	__HAL_SPI_CLEAR_FREFLAG(hspi);
bogdanm	0:9b334a45a8ff	1645	}
bogdanm	0:9b334a45a8ff	1646
bogdanm	0:9b334a45a8ff	1647	/* Call the Error call Back in case of Errors */
bogdanm	0:9b334a45a8ff	1648	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1649	{
bogdanm	0:9b334a45a8ff	1650	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
bogdanm	0:9b334a45a8ff	1651	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1652	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1653	}
bogdanm	0:9b334a45a8ff	1654	}
bogdanm	0:9b334a45a8ff	1655	}
bogdanm	0:9b334a45a8ff	1656
bogdanm	0:9b334a45a8ff	1657	/**
bogdanm	0:9b334a45a8ff	1658	* @brief Tx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1659	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1660	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1661	* @retval None
bogdanm	0:9b334a45a8ff	1662	*/
bogdanm	0:9b334a45a8ff	1663	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1664	{
mbed_official	113:b3775bf36a83	1665	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1666	UNUSED(hspi);
mbed_official	113:b3775bf36a83	1667
bogdanm	0:9b334a45a8ff	1668	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1669	the HAL_SPI_TxCpltCallback could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1670	*/
bogdanm	0:9b334a45a8ff	1671	}
bogdanm	0:9b334a45a8ff	1672
bogdanm	0:9b334a45a8ff	1673	/**
bogdanm	0:9b334a45a8ff	1674	* @brief Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1675	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1676	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1677	* @retval None
bogdanm	0:9b334a45a8ff	1678	*/
bogdanm	0:9b334a45a8ff	1679	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1680	{
mbed_official	113:b3775bf36a83	1681	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1682	UNUSED(hspi);
mbed_official	113:b3775bf36a83	1683
bogdanm	0:9b334a45a8ff	1684	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1685	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1686	*/
bogdanm	0:9b334a45a8ff	1687	}
bogdanm	0:9b334a45a8ff	1688
bogdanm	0:9b334a45a8ff	1689	/**
bogdanm	0:9b334a45a8ff	1690	* @brief Tx and Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1691	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1692	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1693	* @retval None
bogdanm	0:9b334a45a8ff	1694	*/
bogdanm	0:9b334a45a8ff	1695	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1696	{
mbed_official	113:b3775bf36a83	1697	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1698	UNUSED(hspi);
mbed_official	113:b3775bf36a83	1699
bogdanm	0:9b334a45a8ff	1700	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1701	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1702	*/
bogdanm	0:9b334a45a8ff	1703	}
bogdanm	0:9b334a45a8ff	1704
bogdanm	0:9b334a45a8ff	1705	/**
bogdanm	0:9b334a45a8ff	1706	* @brief Tx Half Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1707	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1708	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1709	* @retval None
bogdanm	0:9b334a45a8ff	1710	*/
bogdanm	0:9b334a45a8ff	1711	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1712	{
mbed_official	113:b3775bf36a83	1713	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1714	UNUSED(hspi);
mbed_official	113:b3775bf36a83	1715
bogdanm	0:9b334a45a8ff	1716	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1717	the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1718	*/
bogdanm	0:9b334a45a8ff	1719	}
bogdanm	0:9b334a45a8ff	1720
bogdanm	0:9b334a45a8ff	1721	/**
bogdanm	0:9b334a45a8ff	1722	* @brief Rx Half Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1723	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1724	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1725	* @retval None
bogdanm	0:9b334a45a8ff	1726	*/
bogdanm	0:9b334a45a8ff	1727	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1728	{
mbed_official	113:b3775bf36a83	1729	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1730	UNUSED(hspi);
mbed_official	113:b3775bf36a83	1731
bogdanm	0:9b334a45a8ff	1732	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1733	the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1734	*/
bogdanm	0:9b334a45a8ff	1735	}
bogdanm	0:9b334a45a8ff	1736
bogdanm	0:9b334a45a8ff	1737	/**
bogdanm	0:9b334a45a8ff	1738	* @brief Tx and Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1739	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1740	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1741	* @retval None
bogdanm	0:9b334a45a8ff	1742	*/
bogdanm	0:9b334a45a8ff	1743	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1744	{
mbed_official	113:b3775bf36a83	1745	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1746	UNUSED(hspi);
mbed_official	113:b3775bf36a83	1747
bogdanm	0:9b334a45a8ff	1748	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1749	the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
bogdanm	0:9b334a45a8ff	1750	*/
bogdanm	0:9b334a45a8ff	1751	}
bogdanm	0:9b334a45a8ff	1752
bogdanm	0:9b334a45a8ff	1753	/**
bogdanm	0:9b334a45a8ff	1754	* @brief SPI error callbacks
bogdanm	0:9b334a45a8ff	1755	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1756	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1757	* @retval None
bogdanm	0:9b334a45a8ff	1758	*/
bogdanm	0:9b334a45a8ff	1759	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1760	{
mbed_official	113:b3775bf36a83	1761	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1762	UNUSED(hspi);
mbed_official	113:b3775bf36a83	1763
bogdanm	0:9b334a45a8ff	1764	/* NOTE : - This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1765	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
bogdanm	0:9b334a45a8ff	1766	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
bogdanm	0:9b334a45a8ff	1767	and user can use HAL_SPI_GetError() API to check the latest error occurred.
bogdanm	0:9b334a45a8ff	1768	*/
bogdanm	0:9b334a45a8ff	1769	}
bogdanm	0:9b334a45a8ff	1770
bogdanm	0:9b334a45a8ff	1771	/**
bogdanm	0:9b334a45a8ff	1772	* @}
bogdanm	0:9b334a45a8ff	1773	*/
bogdanm	0:9b334a45a8ff	1774
mbed_official	113:b3775bf36a83	1775	/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	1776	* @brief SPI control functions
bogdanm	0:9b334a45a8ff	1777	*
bogdanm	0:9b334a45a8ff	1778	@verbatim
bogdanm	0:9b334a45a8ff	1779	===============================================================================
bogdanm	0:9b334a45a8ff	1780	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1781	===============================================================================
bogdanm	0:9b334a45a8ff	1782	[..]
bogdanm	0:9b334a45a8ff	1783	This subsection provides a set of functions allowing to control the SPI.
bogdanm	0:9b334a45a8ff	1784	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
bogdanm	0:9b334a45a8ff	1785	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
bogdanm	0:9b334a45a8ff	1786	@endverbatim
bogdanm	0:9b334a45a8ff	1787	* @{
bogdanm	0:9b334a45a8ff	1788	*/
bogdanm	0:9b334a45a8ff	1789
bogdanm	0:9b334a45a8ff	1790	/**
bogdanm	0:9b334a45a8ff	1791	* @brief Return the SPI state
bogdanm	0:9b334a45a8ff	1792	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1793	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1794	* @retval SPI state
bogdanm	0:9b334a45a8ff	1795	*/
bogdanm	0:9b334a45a8ff	1796	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1797	{
bogdanm	0:9b334a45a8ff	1798	return hspi->State;
bogdanm	0:9b334a45a8ff	1799	}
bogdanm	0:9b334a45a8ff	1800
bogdanm	0:9b334a45a8ff	1801	/**
bogdanm	0:9b334a45a8ff	1802	* @brief Return the SPI error code
bogdanm	0:9b334a45a8ff	1803	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1804	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1805	* @retval SPI Error Code
bogdanm	0:9b334a45a8ff	1806	*/
bogdanm	0:9b334a45a8ff	1807	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1808	{
bogdanm	0:9b334a45a8ff	1809	return hspi->ErrorCode;
bogdanm	0:9b334a45a8ff	1810	}
bogdanm	0:9b334a45a8ff	1811
bogdanm	0:9b334a45a8ff	1812	/**
bogdanm	0:9b334a45a8ff	1813	* @}
bogdanm	0:9b334a45a8ff	1814	*/
bogdanm	0:9b334a45a8ff	1815
bogdanm	0:9b334a45a8ff	1816	/**
bogdanm	0:9b334a45a8ff	1817	* @}
bogdanm	0:9b334a45a8ff	1818	*/
bogdanm	0:9b334a45a8ff	1819
bogdanm	0:9b334a45a8ff	1820
bogdanm	0:9b334a45a8ff	1821
mbed_official	113:b3775bf36a83	1822	/** @addtogroup SPI_Private
bogdanm	0:9b334a45a8ff	1823	* @{
bogdanm	0:9b334a45a8ff	1824	*/
bogdanm	0:9b334a45a8ff	1825
bogdanm	0:9b334a45a8ff	1826
bogdanm	0:9b334a45a8ff	1827	/**
bogdanm	0:9b334a45a8ff	1828	* @brief Interrupt Handler to close Tx transfer
bogdanm	0:9b334a45a8ff	1829	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1830	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1831	* @retval void
bogdanm	0:9b334a45a8ff	1832	*/
bogdanm	0:9b334a45a8ff	1833	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1834	{
bogdanm	0:9b334a45a8ff	1835	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	1836	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1837	{
bogdanm	0:9b334a45a8ff	1838	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1839	}
bogdanm	0:9b334a45a8ff	1840
bogdanm	0:9b334a45a8ff	1841	/* Disable TXE interrupt */
bogdanm	0:9b334a45a8ff	1842	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
bogdanm	0:9b334a45a8ff	1843
bogdanm	0:9b334a45a8ff	1844	/* Disable ERR interrupt if Receive process is finished */
bogdanm	0:9b334a45a8ff	1845	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
bogdanm	0:9b334a45a8ff	1846	{
bogdanm	0:9b334a45a8ff	1847	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1848
bogdanm	0:9b334a45a8ff	1849	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	1850	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1851	{
bogdanm	0:9b334a45a8ff	1852	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1853	}
bogdanm	0:9b334a45a8ff	1854
bogdanm	0:9b334a45a8ff	1855	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	1856	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1857	{
bogdanm	0:9b334a45a8ff	1858	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1859	}
bogdanm	0:9b334a45a8ff	1860
bogdanm	0:9b334a45a8ff	1861	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	1862	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1863	{
bogdanm	0:9b334a45a8ff	1864	/* Check if we are in Tx or in Rx/Tx Mode */
bogdanm	0:9b334a45a8ff	1865	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1866	{
bogdanm	0:9b334a45a8ff	1867	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1868	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1869	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1870	}
bogdanm	0:9b334a45a8ff	1871	else
bogdanm	0:9b334a45a8ff	1872	{
bogdanm	0:9b334a45a8ff	1873	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1874	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1875	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1876	}
bogdanm	0:9b334a45a8ff	1877	}
bogdanm	0:9b334a45a8ff	1878	else
bogdanm	0:9b334a45a8ff	1879	{
bogdanm	0:9b334a45a8ff	1880	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1881	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1882	/* Call Error call back in case of Error */
bogdanm	0:9b334a45a8ff	1883	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1884	}
bogdanm	0:9b334a45a8ff	1885	}
bogdanm	0:9b334a45a8ff	1886	}
bogdanm	0:9b334a45a8ff	1887
bogdanm	0:9b334a45a8ff	1888	/**
bogdanm	0:9b334a45a8ff	1889	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
bogdanm	0:9b334a45a8ff	1890	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1891	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1892	* @retval void
bogdanm	0:9b334a45a8ff	1893	*/
bogdanm	0:9b334a45a8ff	1894	static void SPI_TxISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1895	{
bogdanm	0:9b334a45a8ff	1896	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	1897	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1898	{
bogdanm	0:9b334a45a8ff	1899	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	1900	}
bogdanm	0:9b334a45a8ff	1901	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	1902	else
bogdanm	0:9b334a45a8ff	1903	{
bogdanm	0:9b334a45a8ff	1904	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	1905	hspi->pTxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	1906	}
bogdanm	0:9b334a45a8ff	1907	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	1908
bogdanm	0:9b334a45a8ff	1909	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1910	{
bogdanm	0:9b334a45a8ff	1911	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1912	{
bogdanm	0:9b334a45a8ff	1913	/* calculate and transfer CRC on Tx line */
bogdanm	0:9b334a45a8ff	1914	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	1915	}
bogdanm	0:9b334a45a8ff	1916	SPI_TxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	1917	}
bogdanm	0:9b334a45a8ff	1918	}
bogdanm	0:9b334a45a8ff	1919
bogdanm	0:9b334a45a8ff	1920	/**
bogdanm	0:9b334a45a8ff	1921	* @brief Interrupt Handler to close Rx transfer
bogdanm	0:9b334a45a8ff	1922	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1923	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1924	* @retval void
bogdanm	0:9b334a45a8ff	1925	*/
bogdanm	0:9b334a45a8ff	1926	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1927	{
bogdanm	0:9b334a45a8ff	1928	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1929
bogdanm	0:9b334a45a8ff	1930	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1931	{
bogdanm	0:9b334a45a8ff	1932	/* Wait until RXNE flag is set to read CRC data */
bogdanm	0:9b334a45a8ff	1933	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1934	{
bogdanm	0:9b334a45a8ff	1935	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1936	}
bogdanm	0:9b334a45a8ff	1937
bogdanm	0:9b334a45a8ff	1938	/* Read CRC to reset RXNE flag */
bogdanm	0:9b334a45a8ff	1939	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1940	UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
bogdanm	0:9b334a45a8ff	1941
bogdanm	0:9b334a45a8ff	1942	/* Wait until RXNE flag is reset */
bogdanm	0:9b334a45a8ff	1943	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1944	{
bogdanm	0:9b334a45a8ff	1945	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	1946	}
bogdanm	0:9b334a45a8ff	1947
bogdanm	0:9b334a45a8ff	1948	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	1949	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1950	{
bogdanm	0:9b334a45a8ff	1951	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	1952
bogdanm	0:9b334a45a8ff	1953	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1954	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1955	}
bogdanm	0:9b334a45a8ff	1956	}
bogdanm	0:9b334a45a8ff	1957
bogdanm	0:9b334a45a8ff	1958	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	1959	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
bogdanm	0:9b334a45a8ff	1960
bogdanm	0:9b334a45a8ff	1961	/* if Transmit process is finished */
bogdanm	0:9b334a45a8ff	1962	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
bogdanm	0:9b334a45a8ff	1963	{
bogdanm	0:9b334a45a8ff	1964	/* Disable ERR interrupt */
bogdanm	0:9b334a45a8ff	1965	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1966
bogdanm	0:9b334a45a8ff	1967	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	1968	{
bogdanm	0:9b334a45a8ff	1969	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	1970	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	1971	}
bogdanm	0:9b334a45a8ff	1972
bogdanm	0:9b334a45a8ff	1973	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	1974	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1975	{
bogdanm	0:9b334a45a8ff	1976	/* Check if we are in Rx or in Rx/Tx Mode */
bogdanm	0:9b334a45a8ff	1977	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1978	{
bogdanm	0:9b334a45a8ff	1979	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1980	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1981	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1982	}
bogdanm	0:9b334a45a8ff	1983	else
bogdanm	0:9b334a45a8ff	1984	{
bogdanm	0:9b334a45a8ff	1985	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1986	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1987	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1988	}
bogdanm	0:9b334a45a8ff	1989	}
bogdanm	0:9b334a45a8ff	1990	else
bogdanm	0:9b334a45a8ff	1991	{
bogdanm	0:9b334a45a8ff	1992	/* Set state to READY before run the Callback Complete */
bogdanm	0:9b334a45a8ff	1993	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1994	/* Call Error call back in case of Error */
bogdanm	0:9b334a45a8ff	1995	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1996	}
bogdanm	0:9b334a45a8ff	1997	}
bogdanm	0:9b334a45a8ff	1998	}
bogdanm	0:9b334a45a8ff	1999
bogdanm	0:9b334a45a8ff	2000	/**
bogdanm	0:9b334a45a8ff	2001	* @brief Interrupt Handler to receive amount of data in 2Lines mode
bogdanm	0:9b334a45a8ff	2002	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2003	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2004	* @retval void
bogdanm	0:9b334a45a8ff	2005	*/
bogdanm	0:9b334a45a8ff	2006	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2007	{
bogdanm	0:9b334a45a8ff	2008	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	2009	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	2010	{
bogdanm	0:9b334a45a8ff	2011	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2012	}
bogdanm	0:9b334a45a8ff	2013	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2014	else
bogdanm	0:9b334a45a8ff	2015	{
bogdanm	0:9b334a45a8ff	2016	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2017	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	2018	}
bogdanm	0:9b334a45a8ff	2019	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2020
bogdanm	0:9b334a45a8ff	2021	if(hspi->RxXferCount==0)
bogdanm	0:9b334a45a8ff	2022	{
bogdanm	0:9b334a45a8ff	2023	SPI_RxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	2024	}
bogdanm	0:9b334a45a8ff	2025	}
bogdanm	0:9b334a45a8ff	2026
bogdanm	0:9b334a45a8ff	2027	/**
bogdanm	0:9b334a45a8ff	2028	* @brief Interrupt Handler to receive amount of data in no-blocking mode
bogdanm	0:9b334a45a8ff	2029	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2030	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2031	* @retval void
bogdanm	0:9b334a45a8ff	2032	*/
bogdanm	0:9b334a45a8ff	2033	static void SPI_RxISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2034	{
bogdanm	0:9b334a45a8ff	2035	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	2036	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	2037	{
bogdanm	0:9b334a45a8ff	2038	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2039	}
bogdanm	0:9b334a45a8ff	2040	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2041	else
bogdanm	0:9b334a45a8ff	2042	{
bogdanm	0:9b334a45a8ff	2043	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2044	hspi->pRxBuffPtr+=2;
bogdanm	0:9b334a45a8ff	2045	}
bogdanm	0:9b334a45a8ff	2046	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2047
bogdanm	0:9b334a45a8ff	2048	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2049	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	2050	{
bogdanm	0:9b334a45a8ff	2051	/* Set CRC Next to calculate CRC on Rx side */
bogdanm	0:9b334a45a8ff	2052	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	2053	}
bogdanm	0:9b334a45a8ff	2054
bogdanm	0:9b334a45a8ff	2055	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2056	{
bogdanm	0:9b334a45a8ff	2057	SPI_RxCloseIRQHandler(hspi);
bogdanm	0:9b334a45a8ff	2058	}
bogdanm	0:9b334a45a8ff	2059	}
bogdanm	0:9b334a45a8ff	2060
bogdanm	0:9b334a45a8ff	2061	/**
bogdanm	0:9b334a45a8ff	2062	* @brief DMA SPI transmit process complete callback
bogdanm	0:9b334a45a8ff	2063	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2064	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2065	* @retval None
bogdanm	0:9b334a45a8ff	2066	*/
bogdanm	0:9b334a45a8ff	2067	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2068	{
bogdanm	0:9b334a45a8ff	2069	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2070
bogdanm	0:9b334a45a8ff	2071
bogdanm	0:9b334a45a8ff	2072	/* DMA Normal Mode */
bogdanm	0:9b334a45a8ff	2073	if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
bogdanm	0:9b334a45a8ff	2074	{
bogdanm	0:9b334a45a8ff	2075	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	2076	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2077	{
bogdanm	0:9b334a45a8ff	2078	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2079	}
bogdanm	0:9b334a45a8ff	2080
bogdanm	0:9b334a45a8ff	2081	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	2082	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2083
bogdanm	0:9b334a45a8ff	2084	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	2085	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2086	{
bogdanm	0:9b334a45a8ff	2087	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2088	}
bogdanm	0:9b334a45a8ff	2089
bogdanm	0:9b334a45a8ff	2090	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2091	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2092	}
bogdanm	0:9b334a45a8ff	2093
bogdanm	0:9b334a45a8ff	2094	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	2095	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	2096	{
bogdanm	0:9b334a45a8ff	2097	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2098	}
bogdanm	0:9b334a45a8ff	2099
bogdanm	0:9b334a45a8ff	2100	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2101	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2102	{
bogdanm	0:9b334a45a8ff	2103	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2104	}
bogdanm	0:9b334a45a8ff	2105	else
bogdanm	0:9b334a45a8ff	2106	{
bogdanm	0:9b334a45a8ff	2107	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2108	}
bogdanm	0:9b334a45a8ff	2109	}
bogdanm	0:9b334a45a8ff	2110
bogdanm	0:9b334a45a8ff	2111	/**
bogdanm	0:9b334a45a8ff	2112	* @brief DMA SPI receive process complete callback
bogdanm	0:9b334a45a8ff	2113	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2114	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2115	* @retval None
bogdanm	0:9b334a45a8ff	2116	*/
bogdanm	0:9b334a45a8ff	2117	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2118	{
bogdanm	0:9b334a45a8ff	2119	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	2120
bogdanm	0:9b334a45a8ff	2121	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2122
bogdanm	0:9b334a45a8ff	2123	/* DMA Normal mode */
bogdanm	0:9b334a45a8ff	2124	if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
bogdanm	0:9b334a45a8ff	2125	{
bogdanm	0:9b334a45a8ff	2126	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	2127	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2128
bogdanm	0:9b334a45a8ff	2129	/* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
bogdanm	0:9b334a45a8ff	2130	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2131
bogdanm	0:9b334a45a8ff	2132	/* CRC Calculation handling */
bogdanm	0:9b334a45a8ff	2133	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2134	{
bogdanm	0:9b334a45a8ff	2135	/* Wait until RXNE flag is set (CRC ready) */
bogdanm	0:9b334a45a8ff	2136	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2137	{
bogdanm	0:9b334a45a8ff	2138	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2139	}
bogdanm	0:9b334a45a8ff	2140
bogdanm	0:9b334a45a8ff	2141	/* Read CRC */
bogdanm	0:9b334a45a8ff	2142	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2143	UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
bogdanm	0:9b334a45a8ff	2144
bogdanm	0:9b334a45a8ff	2145	/* Wait until RXNE flag is reset */
bogdanm	0:9b334a45a8ff	2146	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2147	{
bogdanm	0:9b334a45a8ff	2148	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2149	}
bogdanm	0:9b334a45a8ff	2150
bogdanm	0:9b334a45a8ff	2151	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2152	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2153	{
bogdanm	0:9b334a45a8ff	2154	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	2155	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2156	}
bogdanm	0:9b334a45a8ff	2157	}
bogdanm	0:9b334a45a8ff	2158
bogdanm	0:9b334a45a8ff	2159	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2160	{
bogdanm	0:9b334a45a8ff	2161	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2162	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2163	}
bogdanm	0:9b334a45a8ff	2164
bogdanm	0:9b334a45a8ff	2165	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2166	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2167
bogdanm	0:9b334a45a8ff	2168	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2169	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2170	{
bogdanm	0:9b334a45a8ff	2171	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2172	}
bogdanm	0:9b334a45a8ff	2173	else
bogdanm	0:9b334a45a8ff	2174	{
bogdanm	0:9b334a45a8ff	2175	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2176	}
bogdanm	0:9b334a45a8ff	2177	}
bogdanm	0:9b334a45a8ff	2178	else
bogdanm	0:9b334a45a8ff	2179	{
bogdanm	0:9b334a45a8ff	2180	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2181	}
bogdanm	0:9b334a45a8ff	2182	}
bogdanm	0:9b334a45a8ff	2183
bogdanm	0:9b334a45a8ff	2184	/**
bogdanm	0:9b334a45a8ff	2185	* @brief DMA SPI transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2186	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2187	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2188	* @retval None
bogdanm	0:9b334a45a8ff	2189	*/
bogdanm	0:9b334a45a8ff	2190	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2191	{
bogdanm	0:9b334a45a8ff	2192	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	2193
bogdanm	0:9b334a45a8ff	2194	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2195	if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
bogdanm	0:9b334a45a8ff	2196	{
bogdanm	0:9b334a45a8ff	2197	/* CRC Calculation handling */
bogdanm	0:9b334a45a8ff	2198	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2199	{
bogdanm	0:9b334a45a8ff	2200	/* Check if CRC is done on going (RXNE flag set) */
bogdanm	0:9b334a45a8ff	2201	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
bogdanm	0:9b334a45a8ff	2202	{
bogdanm	0:9b334a45a8ff	2203	/* Wait until RXNE flag is set to send data */
bogdanm	0:9b334a45a8ff	2204	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2205	{
bogdanm	0:9b334a45a8ff	2206	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2207	}
bogdanm	0:9b334a45a8ff	2208	}
bogdanm	0:9b334a45a8ff	2209	/* Read CRC */
bogdanm	0:9b334a45a8ff	2210	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2211	UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
bogdanm	0:9b334a45a8ff	2212
bogdanm	0:9b334a45a8ff	2213	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2214	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2215	{
bogdanm	0:9b334a45a8ff	2216	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
bogdanm	0:9b334a45a8ff	2217	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2218	}
bogdanm	0:9b334a45a8ff	2219	}
bogdanm	0:9b334a45a8ff	2220
bogdanm	0:9b334a45a8ff	2221	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	2222	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2223	{
bogdanm	0:9b334a45a8ff	2224	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2225	}
bogdanm	0:9b334a45a8ff	2226
bogdanm	0:9b334a45a8ff	2227	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	2228	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2229
bogdanm	0:9b334a45a8ff	2230	/* Wait until Busy flag is reset before disabling SPI */
bogdanm	0:9b334a45a8ff	2231	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2232	{
bogdanm	0:9b334a45a8ff	2233	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
bogdanm	0:9b334a45a8ff	2234	}
bogdanm	0:9b334a45a8ff	2235
bogdanm	0:9b334a45a8ff	2236	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	2237	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2238
bogdanm	0:9b334a45a8ff	2239	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2240	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2241
bogdanm	0:9b334a45a8ff	2242	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2243
bogdanm	0:9b334a45a8ff	2244	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	2245	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2246	{
bogdanm	0:9b334a45a8ff	2247	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2248	}
bogdanm	0:9b334a45a8ff	2249	else
bogdanm	0:9b334a45a8ff	2250	{
bogdanm	0:9b334a45a8ff	2251	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2252	}
bogdanm	0:9b334a45a8ff	2253	}
bogdanm	0:9b334a45a8ff	2254	else
bogdanm	0:9b334a45a8ff	2255	{
bogdanm	0:9b334a45a8ff	2256	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2257	}
bogdanm	0:9b334a45a8ff	2258	}
bogdanm	0:9b334a45a8ff	2259
bogdanm	0:9b334a45a8ff	2260	/**
bogdanm	0:9b334a45a8ff	2261	* @brief DMA SPI half transmit process complete callback
bogdanm	0:9b334a45a8ff	2262	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2263	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2264	* @retval None
bogdanm	0:9b334a45a8ff	2265	*/
bogdanm	0:9b334a45a8ff	2266	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2267	{
bogdanm	0:9b334a45a8ff	2268	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2269
bogdanm	0:9b334a45a8ff	2270	HAL_SPI_TxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2271	}
bogdanm	0:9b334a45a8ff	2272
bogdanm	0:9b334a45a8ff	2273	/**
bogdanm	0:9b334a45a8ff	2274	* @brief DMA SPI half receive process complete callback
bogdanm	0:9b334a45a8ff	2275	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2276	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2277	* @retval None
bogdanm	0:9b334a45a8ff	2278	*/
bogdanm	0:9b334a45a8ff	2279	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2280	{
bogdanm	0:9b334a45a8ff	2281	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2282
bogdanm	0:9b334a45a8ff	2283	HAL_SPI_RxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2284	}
bogdanm	0:9b334a45a8ff	2285
bogdanm	0:9b334a45a8ff	2286	/**
bogdanm	0:9b334a45a8ff	2287	* @brief DMA SPI Half transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2288	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2289	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2290	* @retval None
bogdanm	0:9b334a45a8ff	2291	*/
bogdanm	0:9b334a45a8ff	2292	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2293	{
bogdanm	0:9b334a45a8ff	2294	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2295
bogdanm	0:9b334a45a8ff	2296	HAL_SPI_TxRxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2297	}
bogdanm	0:9b334a45a8ff	2298
bogdanm	0:9b334a45a8ff	2299	/**
bogdanm	0:9b334a45a8ff	2300	* @brief DMA SPI communication error callback
bogdanm	0:9b334a45a8ff	2301	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2302	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2303	* @retval None
bogdanm	0:9b334a45a8ff	2304	*/
bogdanm	0:9b334a45a8ff	2305	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2306	{
bogdanm	0:9b334a45a8ff	2307	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2308	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2309	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2310	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2311	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
bogdanm	0:9b334a45a8ff	2312	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2313	}
bogdanm	0:9b334a45a8ff	2314
bogdanm	0:9b334a45a8ff	2315	/**
bogdanm	0:9b334a45a8ff	2316	* @brief This function handles SPI Communication Timeout.
bogdanm	0:9b334a45a8ff	2317	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2318	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2319	* @param Flag: SPI flag to check
bogdanm	0:9b334a45a8ff	2320	* @param Status: Flag status to check: RESET or set
bogdanm	0:9b334a45a8ff	2321	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	2322	* @retval HAL status
bogdanm	0:9b334a45a8ff	2323	*/
bogdanm	0:9b334a45a8ff	2324	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2325	{
bogdanm	0:9b334a45a8ff	2326	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	2327
bogdanm	0:9b334a45a8ff	2328	/* Get tick */
bogdanm	0:9b334a45a8ff	2329	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2330
bogdanm	0:9b334a45a8ff	2331	/* Wait until flag is set */
bogdanm	0:9b334a45a8ff	2332	if(Status == RESET)
bogdanm	0:9b334a45a8ff	2333	{
bogdanm	0:9b334a45a8ff	2334	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
bogdanm	0:9b334a45a8ff	2335	{
bogdanm	0:9b334a45a8ff	2336	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2337	{
bogdanm	0:9b334a45a8ff	2338	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	2339	{
bogdanm	0:9b334a45a8ff	2340	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2341	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2342	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2343
bogdanm	0:9b334a45a8ff	2344	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2345	__HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2346
bogdanm	0:9b334a45a8ff	2347	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2348	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2349
bogdanm	0:9b334a45a8ff	2350	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2351	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2352	{
bogdanm	0:9b334a45a8ff	2353	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2354	}
bogdanm	0:9b334a45a8ff	2355
bogdanm	0:9b334a45a8ff	2356	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2357
bogdanm	0:9b334a45a8ff	2358	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2359	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2360
bogdanm	0:9b334a45a8ff	2361	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2362	}
bogdanm	0:9b334a45a8ff	2363	}
bogdanm	0:9b334a45a8ff	2364	}
bogdanm	0:9b334a45a8ff	2365	}
bogdanm	0:9b334a45a8ff	2366	else
bogdanm	0:9b334a45a8ff	2367	{
bogdanm	0:9b334a45a8ff	2368	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
bogdanm	0:9b334a45a8ff	2369	{
bogdanm	0:9b334a45a8ff	2370	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2371	{
bogdanm	0:9b334a45a8ff	2372	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	2373	{
bogdanm	0:9b334a45a8ff	2374	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2375	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2376	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2377
bogdanm	0:9b334a45a8ff	2378	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2379	__HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2380
bogdanm	0:9b334a45a8ff	2381	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2382	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2383
bogdanm	0:9b334a45a8ff	2384	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2385	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2386	{
bogdanm	0:9b334a45a8ff	2387	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2388	}
bogdanm	0:9b334a45a8ff	2389
bogdanm	0:9b334a45a8ff	2390	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2391
bogdanm	0:9b334a45a8ff	2392	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2393	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2394
bogdanm	0:9b334a45a8ff	2395	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2396	}
bogdanm	0:9b334a45a8ff	2397	}
bogdanm	0:9b334a45a8ff	2398	}
bogdanm	0:9b334a45a8ff	2399	}
bogdanm	0:9b334a45a8ff	2400	return HAL_OK;
bogdanm	0:9b334a45a8ff	2401	}
bogdanm	0:9b334a45a8ff	2402	/**
bogdanm	0:9b334a45a8ff	2403	* @}
bogdanm	0:9b334a45a8ff	2404	*/
bogdanm	0:9b334a45a8ff	2405
bogdanm	0:9b334a45a8ff	2406	/**
bogdanm	0:9b334a45a8ff	2407	* @}
bogdanm	0:9b334a45a8ff	2408	*/
bogdanm	0:9b334a45a8ff	2409
mbed_official	113:b3775bf36a83	2410	#endif /* HAL_SPI_MODULE_ENABLED */
mbed_official	113:b3775bf36a83	2411
bogdanm	0:9b334a45a8ff	2412	/**
bogdanm	0:9b334a45a8ff	2413	* @}
bogdanm	0:9b334a45a8ff	2414	*/
bogdanm	0:9b334a45a8ff	2415
bogdanm	0:9b334a45a8ff	2416	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	2417

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.c@113:b3775bf36a83, 2016-04-19 (annotated)

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