en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.c@113:b3775bf36a83, 2016-04-19 (annotated)

Committer:
mbed_official
Date:
Tue Apr 19 11:15:15 2016 +0100
Revision:
113:b3775bf36a83
Parent:
0:9b334a45a8ff 
Synchronized with git revision 896981126b34b6d9441e3eea77881c67a1ae3dbd



Full URL: https://github.com/mbedmicro/mbed/commit/896981126b34b6d9441e3eea77881c67a1ae3dbd/



Exporter tool addition for e2 studio

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l0xx_hal_pwr.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 113:b3775bf36a83 5 * @version V1.5.0
mbed_official 113:b3775bf36a83 6 * @date 8-January-2016
bogdanm 0:9b334a45a8ff 7 * @brief PWR HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the Power Controller (PWR) peripheral:
bogdanm 0:9b334a45a8ff 11 * + Initialization/de-initialization functions
bogdanm 0:9b334a45a8ff 12 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 ******************************************************************************
bogdanm 0:9b334a45a8ff 15 * @attention
bogdanm 0:9b334a45a8ff 16 *
mbed_official 113:b3775bf36a83 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 20 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 21 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 22 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 24 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 25 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 27 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 28 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 29 *
bogdanm 0:9b334a45a8ff 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 40 *
bogdanm 0:9b334a45a8ff 41 ******************************************************************************
bogdanm 0:9b334a45a8ff 42 */
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 45 #include "stm32l0xx_hal.h"
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 #ifdef HAL_PWR_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 48 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 0:9b334a45a8ff 49 * @{
bogdanm 0:9b334a45a8ff 50 */
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 /** @addtogroup PWR
bogdanm 0:9b334a45a8ff 53 * @{
bogdanm 0:9b334a45a8ff 54 */
bogdanm 0:9b334a45a8ff 55
mbed_official 113:b3775bf36a83 56 /** @addtogroup PWR_Private
bogdanm 0:9b334a45a8ff 57 * @{
bogdanm 0:9b334a45a8ff 58 */
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
bogdanm 0:9b334a45a8ff 61 * @{
bogdanm 0:9b334a45a8ff 62 */
bogdanm 0:9b334a45a8ff 63 #define PVD_MODE_IT ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 64 #define PVD_MODE_EVT ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 65 #define PVD_RISING_EDGE ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 66 #define PVD_FALLING_EDGE ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 67 /**
bogdanm 0:9b334a45a8ff 68 * @}
bogdanm 0:9b334a45a8ff 69 */
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 /**
bogdanm 0:9b334a45a8ff 72 * @}
bogdanm 0:9b334a45a8ff 73 */
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 /** @addtogroup PWR_Exported_Functions
bogdanm 0:9b334a45a8ff 77 * @{
bogdanm 0:9b334a45a8ff 78 */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 /** @addtogroup PWR_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 81 * @brief Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 82 *
bogdanm 0:9b334a45a8ff 83 @verbatim
bogdanm 0:9b334a45a8ff 84 ===============================================================================
bogdanm 0:9b334a45a8ff 85 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 86 ===============================================================================
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 @endverbatim
bogdanm 0:9b334a45a8ff 89 * @{
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 /**
bogdanm 0:9b334a45a8ff 93 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
bogdanm 0:9b334a45a8ff 94 * @retval None
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96 void HAL_PWR_DeInit(void)
bogdanm 0:9b334a45a8ff 97 {
bogdanm 0:9b334a45a8ff 98 __HAL_RCC_PWR_FORCE_RESET();
bogdanm 0:9b334a45a8ff 99 __HAL_RCC_PWR_RELEASE_RESET();
bogdanm 0:9b334a45a8ff 100 }
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /**
bogdanm 0:9b334a45a8ff 103 * @}
bogdanm 0:9b334a45a8ff 104 */
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /** @addtogroup PWR_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 107 * @brief Low Power modes configuration functions
bogdanm 0:9b334a45a8ff 108 *
bogdanm 0:9b334a45a8ff 109 @verbatim
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 ===============================================================================
bogdanm 0:9b334a45a8ff 112 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 113 ===============================================================================
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 *** Backup domain ***
bogdanm 0:9b334a45a8ff 116 =========================
bogdanm 0:9b334a45a8ff 117 [..]
bogdanm 0:9b334a45a8ff 118 After reset, the backup domain (RTC registers, RTC backup data
bogdanm 0:9b334a45a8ff 119 registers) is protected against possible unwanted
bogdanm 0:9b334a45a8ff 120 write accesses.
bogdanm 0:9b334a45a8ff 121 To enable access to the RTC Domain and RTC registers, proceed as follows:
bogdanm 0:9b334a45a8ff 122 (+) Enable the Power Controller (PWR) APB1 interface clock using the
bogdanm 0:9b334a45a8ff 123 __HAL_RCC_PWR_CLK_ENABLE() macro.
bogdanm 0:9b334a45a8ff 124 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 *** PVD configuration ***
bogdanm 0:9b334a45a8ff 127 =========================
bogdanm 0:9b334a45a8ff 128 [..]
bogdanm 0:9b334a45a8ff 129 (+) The PVD is used to monitor the VDD power supply by comparing it to a
bogdanm 0:9b334a45a8ff 130 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
bogdanm 0:9b334a45a8ff 131 (+) The PVD can use an external input analog voltage (PVD_IN) which is compared
bogdanm 0:9b334a45a8ff 132 internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
bogdanm 0:9b334a45a8ff 133 when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
bogdanm 0:9b334a45a8ff 136 than the PVD threshold. This event is internally connected to the EXTI
bogdanm 0:9b334a45a8ff 137 line16 and can generate an interrupt if enabled. This is done through
bogdanm 0:9b334a45a8ff 138 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
bogdanm 0:9b334a45a8ff 139 (+) The PVD is stopped in Standby mode.
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 *** WakeUp pin configuration ***
bogdanm 0:9b334a45a8ff 142 ================================
bogdanm 0:9b334a45a8ff 143 [..]
bogdanm 0:9b334a45a8ff 144 (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
bogdanm 0:9b334a45a8ff 145 forced in input pull-down configuration and is active on rising edges.
bogdanm 0:9b334a45a8ff 146 (+) There are two WakeUp pins:
bogdanm 0:9b334a45a8ff 147 WakeUp Pin 1 on PA.00.
bogdanm 0:9b334a45a8ff 148 WakeUp Pin 2 on PC.13.
bogdanm 0:9b334a45a8ff 149 WakeUp Pin 3 on PE.06 .
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 [..]
bogdanm 0:9b334a45a8ff 153 *** Main and Backup Regulators configuration ***
bogdanm 0:9b334a45a8ff 154 ================================================
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 (+) The main internal regulator can be configured to have a tradeoff between
bogdanm 0:9b334a45a8ff 157 performance and power consumption when the device does not operate at
bogdanm 0:9b334a45a8ff 158 the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG()
bogdanm 0:9b334a45a8ff 159 macro which configures the two VOS bits in PWR_CR register:
bogdanm 0:9b334a45a8ff 160 (++) PWR_REGULATOR_VOLTAGE_SCALE1 (VOS bits = 01), the regulator voltage output Scale 1 mode selected and
bogdanm 0:9b334a45a8ff 161 the System frequency can go up to 32 MHz.
bogdanm 0:9b334a45a8ff 162 (++) PWR_REGULATOR_VOLTAGE_SCALE2 (VOS bits = 10), the regulator voltage output Scale 2 mode selected and
bogdanm 0:9b334a45a8ff 163 the System frequency can go up to 16 MHz.
bogdanm 0:9b334a45a8ff 164 (++) PWR_REGULATOR_VOLTAGE_SCALE3 (VOS bits = 11), the regulator voltage output Scale 3 mode selected and
bogdanm 0:9b334a45a8ff 165 the System frequency can go up to 4.2 MHz.
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 Refer to the datasheets for more details.
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 *** Low Power modes configuration ***
bogdanm 0:9b334a45a8ff 170 =====================================
bogdanm 0:9b334a45a8ff 171 [..]
bogdanm 0:9b334a45a8ff 172 The device features 5 low-power modes:
bogdanm 0:9b334a45a8ff 173 (+) Low power run mode: regulator in low power mode, limited clock frequency,
bogdanm 0:9b334a45a8ff 174 limited number of peripherals running.
bogdanm 0:9b334a45a8ff 175 (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running.
bogdanm 0:9b334a45a8ff 176 (+) Low power sleep mode: Cortex-M0+ core stopped, limited clock frequency,
bogdanm 0:9b334a45a8ff 177 limited number of peripherals running, regulator in low power mode.
bogdanm 0:9b334a45a8ff 178 (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode.
bogdanm 0:9b334a45a8ff 179 (+) Standby mode: VCORE domain powered off
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 *** Low power run mode ***
bogdanm 0:9b334a45a8ff 182 =========================
bogdanm 0:9b334a45a8ff 183 [..]
bogdanm 0:9b334a45a8ff 184 To further reduce the consumption when the system is in Run mode, the regulator can be
bogdanm 0:9b334a45a8ff 185 configured in low power mode. In this mode, the system frequency should not exceed
bogdanm 0:9b334a45a8ff 186 MSI frequency range1.
bogdanm 0:9b334a45a8ff 187 In Low power run mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 (+) Entry:
bogdanm 0:9b334a45a8ff 190 (++) VCORE in range2
bogdanm 0:9b334a45a8ff 191 (++) Decrease the system frequency not to exceed the frequency of MSI frequency range1.
bogdanm 0:9b334a45a8ff 192 (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode()
bogdanm 0:9b334a45a8ff 193 function.
bogdanm 0:9b334a45a8ff 194 (+) Exit:
bogdanm 0:9b334a45a8ff 195 (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode()
bogdanm 0:9b334a45a8ff 196 function.
bogdanm 0:9b334a45a8ff 197 (++) Increase the system frequency if needed.
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 *** Sleep mode ***
bogdanm 0:9b334a45a8ff 200 ==================
bogdanm 0:9b334a45a8ff 201 [..]
bogdanm 0:9b334a45a8ff 202 (+) Entry:
bogdanm 0:9b334a45a8ff 203 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
bogdanm 0:9b334a45a8ff 204 functions with
bogdanm 0:9b334a45a8ff 205 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
bogdanm 0:9b334a45a8ff 206 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 (+) Exit:
bogdanm 0:9b334a45a8ff 209 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
bogdanm 0:9b334a45a8ff 210 controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction was used to enter sleep mode,
bogdanm 0:9b334a45a8ff 211 the MCU exits Sleep mode as soon as an event occurs.
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 *** Low power sleep mode ***
bogdanm 0:9b334a45a8ff 214 ============================
bogdanm 0:9b334a45a8ff 215 [..]
bogdanm 0:9b334a45a8ff 216 (+) Entry:
bogdanm 0:9b334a45a8ff 217 The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx)
bogdanm 0:9b334a45a8ff 218 functions with
bogdanm 0:9b334a45a8ff 219 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
bogdanm 0:9b334a45a8ff 220 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
bogdanm 0:9b334a45a8ff 221 (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register.
bogdanm 0:9b334a45a8ff 222 This reduces power consumption but increases the wake-up time.
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 (+) Exit:
bogdanm 0:9b334a45a8ff 225 (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt
bogdanm 0:9b334a45a8ff 226 acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device
bogdanm 0:9b334a45a8ff 227 from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode,
bogdanm 0:9b334a45a8ff 228 the MCU exits Sleep mode as soon as an event occurs.
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 *** Stop mode ***
bogdanm 0:9b334a45a8ff 231 =================
bogdanm 0:9b334a45a8ff 232 [..]
bogdanm 0:9b334a45a8ff 233 The Stop mode is based on the Cortex-M0+ deepsleep mode combined with peripheral
bogdanm 0:9b334a45a8ff 234 clock gating. The voltage regulator can be configured either in normal or low-power mode.
bogdanm 0:9b334a45a8ff 235 In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and
bogdanm 0:9b334a45a8ff 236 the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
bogdanm 0:9b334a45a8ff 237 To get the lowest consumption in Stop mode, the internal Flash memory also enters low
bogdanm 0:9b334a45a8ff 238 power mode. When the Flash memory is in power-down mode, an additional startup delay is
bogdanm 0:9b334a45a8ff 239 incurred when waking up from Stop mode.
bogdanm 0:9b334a45a8ff 240 To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
bogdanm 0:9b334a45a8ff 241 sensor can be switched off before entering Stop mode. They can be switched on again by
bogdanm 0:9b334a45a8ff 242 software after exiting Stop mode using the ULP bit in the PWR_CR register.
bogdanm 0:9b334a45a8ff 243 In Stop mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 (+) Entry:
bogdanm 0:9b334a45a8ff 246 The Stop mode is entered using the HAL_PWR_EnterSTOPMode
bogdanm 0:9b334a45a8ff 247 function with:
bogdanm 0:9b334a45a8ff 248 (++) Main regulator ON.
bogdanm 0:9b334a45a8ff 249 (++) Low Power regulator ON.
bogdanm 0:9b334a45a8ff 250 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
bogdanm 0:9b334a45a8ff 251 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
bogdanm 0:9b334a45a8ff 252 (+) Exit:
bogdanm 0:9b334a45a8ff 253 (++) By issuing an interrupt or a wakeup event, the MSI or HSI16 RC
bogdanm 0:9b334a45a8ff 254 oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR
bogdanm 0:9b334a45a8ff 255 register
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 *** Standby mode ***
bogdanm 0:9b334a45a8ff 258 ====================
bogdanm 0:9b334a45a8ff 259 [..]
bogdanm 0:9b334a45a8ff 260 The Standby mode allows to achieve the lowest power consumption. It is based on the
bogdanm 0:9b334a45a8ff 261 Cortex-M0+ deepsleep mode, with the voltage regulator disabled. The VCORE domain is
bogdanm 0:9b334a45a8ff 262 consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are
bogdanm 0:9b334a45a8ff 263 also switched off. SRAM and register contents are lost except for the RTC registers, RTC
bogdanm 0:9b334a45a8ff 264 backup registers and Standby circuitry.
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
bogdanm 0:9b334a45a8ff 267 sensor can be switched off before entering the Standby mode. They can be switched
bogdanm 0:9b334a45a8ff 268 on again by software after exiting the Standby mode.
bogdanm 0:9b334a45a8ff 269 function.
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 (+) Entry:
bogdanm 0:9b334a45a8ff 272 (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
bogdanm 0:9b334a45a8ff 273 (+) Exit:
bogdanm 0:9b334a45a8ff 274 (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
bogdanm 0:9b334a45a8ff 275 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 *** Auto-wakeup (AWU) from low-power mode ***
bogdanm 0:9b334a45a8ff 278 =============================================
bogdanm 0:9b334a45a8ff 279 [..]
bogdanm 0:9b334a45a8ff 280 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
bogdanm 0:9b334a45a8ff 281 Wakeup event, a tamper event, a time-stamp event, or a comparator event,
bogdanm 0:9b334a45a8ff 282 without depending on an external interrupt (Auto-wakeup mode).
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 (+) RTC auto-wakeup (AWU) from the Stop mode
bogdanm 0:9b334a45a8ff 285 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
bogdanm 0:9b334a45a8ff 286 (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
bogdanm 0:9b334a45a8ff 287 or Event modes) using the EXTI_Init() function.
bogdanm 0:9b334a45a8ff 288 (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
bogdanm 0:9b334a45a8ff 289 (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
bogdanm 0:9b334a45a8ff 290 and RTC_AlarmCmd() functions.
bogdanm 0:9b334a45a8ff 291 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
bogdanm 0:9b334a45a8ff 292 is necessary to:
bogdanm 0:9b334a45a8ff 293 (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
bogdanm 0:9b334a45a8ff 294 or Event modes) using the EXTI_Init() function.
bogdanm 0:9b334a45a8ff 295 (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
bogdanm 0:9b334a45a8ff 296 function.
bogdanm 0:9b334a45a8ff 297 (+++) Configure the RTC to detect the tamper or time stamp event using the
bogdanm 0:9b334a45a8ff 298 RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
bogdanm 0:9b334a45a8ff 299 functions.
bogdanm 0:9b334a45a8ff 300 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
bogdanm 0:9b334a45a8ff 301 (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt
bogdanm 0:9b334a45a8ff 302 or Event modes) using the EXTI_Init() function.
bogdanm 0:9b334a45a8ff 303 (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function.
bogdanm 0:9b334a45a8ff 304 (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
bogdanm 0:9b334a45a8ff 305 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 (+) RTC auto-wakeup (AWU) from the Standby mode
bogdanm 0:9b334a45a8ff 308 (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
bogdanm 0:9b334a45a8ff 309 (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
bogdanm 0:9b334a45a8ff 310 (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
bogdanm 0:9b334a45a8ff 311 and RTC_AlarmCmd() functions.
bogdanm 0:9b334a45a8ff 312 (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
bogdanm 0:9b334a45a8ff 313 is necessary to:
bogdanm 0:9b334a45a8ff 314 (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
bogdanm 0:9b334a45a8ff 315 function.
bogdanm 0:9b334a45a8ff 316 (+++) Configure the RTC to detect the tamper or time stamp event using the
bogdanm 0:9b334a45a8ff 317 RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
bogdanm 0:9b334a45a8ff 318 functions.
bogdanm 0:9b334a45a8ff 319 (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
bogdanm 0:9b334a45a8ff 320 (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
bogdanm 0:9b334a45a8ff 321 (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
bogdanm 0:9b334a45a8ff 322 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
bogdanm 0:9b334a45a8ff 323
bogdanm 0:9b334a45a8ff 324 (+) Comparator auto-wakeup (AWU) from the Stop mode
bogdanm 0:9b334a45a8ff 325 (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
bogdanm 0:9b334a45a8ff 326 event, it is necessary to:
bogdanm 0:9b334a45a8ff 327 (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
bogdanm 0:9b334a45a8ff 328 to be sensitive to to the selected edges (falling, rising or falling
bogdanm 0:9b334a45a8ff 329 and rising) (Interrupt or Event modes) using the EXTI_Init() function.
bogdanm 0:9b334a45a8ff 330 (+++) Configure the comparator to generate the event.
bogdanm 0:9b334a45a8ff 331 @endverbatim
bogdanm 0:9b334a45a8ff 332 * @{
bogdanm 0:9b334a45a8ff 333 */
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /**
bogdanm 0:9b334a45a8ff 336 * @brief Enables access to the backup domain (RTC registers, RTC
bogdanm 0:9b334a45a8ff 337 * backup data registers ).
bogdanm 0:9b334a45a8ff 338 * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
bogdanm 0:9b334a45a8ff 339 * Backup Domain Access should be kept enabled.
bogdanm 0:9b334a45a8ff 340 * @retval None
bogdanm 0:9b334a45a8ff 341 */
bogdanm 0:9b334a45a8ff 342 void HAL_PWR_EnableBkUpAccess(void)
bogdanm 0:9b334a45a8ff 343 {
bogdanm 0:9b334a45a8ff 344 /* Enable access to RTC and backup registers */
bogdanm 0:9b334a45a8ff 345 SET_BIT(PWR->CR, PWR_CR_DBP);
bogdanm 0:9b334a45a8ff 346 }
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 /**
bogdanm 0:9b334a45a8ff 349 * @brief Disables access to the backup domain
bogdanm 0:9b334a45a8ff 350 * @note Applies to RTC registers, RTC backup data registers.
bogdanm 0:9b334a45a8ff 351 * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
bogdanm 0:9b334a45a8ff 352 * Backup Domain Access should be kept enabled.
bogdanm 0:9b334a45a8ff 353 * @retval None
bogdanm 0:9b334a45a8ff 354 */
bogdanm 0:9b334a45a8ff 355 void HAL_PWR_DisableBkUpAccess(void)
bogdanm 0:9b334a45a8ff 356 {
bogdanm 0:9b334a45a8ff 357 /* Disable access to RTC and backup registers */
bogdanm 0:9b334a45a8ff 358 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
bogdanm 0:9b334a45a8ff 359 }
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /**
bogdanm 0:9b334a45a8ff 362 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
bogdanm 0:9b334a45a8ff 363 * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
bogdanm 0:9b334a45a8ff 364 * information for the PVD.
bogdanm 0:9b334a45a8ff 365 * @note Refer to the electrical characteristics of your device datasheet for
bogdanm 0:9b334a45a8ff 366 * more details about the voltage threshold corresponding to each
bogdanm 0:9b334a45a8ff 367 * detection level.
bogdanm 0:9b334a45a8ff 368 * @retval None
bogdanm 0:9b334a45a8ff 369 */
bogdanm 0:9b334a45a8ff 370 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
bogdanm 0:9b334a45a8ff 371 {
bogdanm 0:9b334a45a8ff 372 /* Check the parameters */
bogdanm 0:9b334a45a8ff 373 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
bogdanm 0:9b334a45a8ff 374 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /* Set PLS[7:5] bits according to PVDLevel value */
bogdanm 0:9b334a45a8ff 377 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
bogdanm 0:9b334a45a8ff 380 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
bogdanm 0:9b334a45a8ff 381 __HAL_PWR_PVD_EXTI_DISABLE_IT();
bogdanm 0:9b334a45a8ff 382 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 383 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 /* Configure interrupt mode */
bogdanm 0:9b334a45a8ff 386 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
bogdanm 0:9b334a45a8ff 387 {
bogdanm 0:9b334a45a8ff 388 __HAL_PWR_PVD_EXTI_ENABLE_IT();
bogdanm 0:9b334a45a8ff 389 }
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 /* Configure event mode */
bogdanm 0:9b334a45a8ff 392 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
bogdanm 0:9b334a45a8ff 393 {
bogdanm 0:9b334a45a8ff 394 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
bogdanm 0:9b334a45a8ff 395 }
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 /* Configure the edge */
bogdanm 0:9b334a45a8ff 398 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
bogdanm 0:9b334a45a8ff 399 {
bogdanm 0:9b334a45a8ff 400 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 401 }
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
bogdanm 0:9b334a45a8ff 404 {
bogdanm 0:9b334a45a8ff 405 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 406 }
bogdanm 0:9b334a45a8ff 407 }
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 /**
bogdanm 0:9b334a45a8ff 410 * @brief Enables the Power Voltage Detector(PVD).
bogdanm 0:9b334a45a8ff 411 * @retval None
bogdanm 0:9b334a45a8ff 412 */
bogdanm 0:9b334a45a8ff 413 void HAL_PWR_EnablePVD(void)
bogdanm 0:9b334a45a8ff 414 {
bogdanm 0:9b334a45a8ff 415 /* Enable the power voltage detector */
bogdanm 0:9b334a45a8ff 416 SET_BIT(PWR->CR, PWR_CR_PVDE);
bogdanm 0:9b334a45a8ff 417 }
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /**
bogdanm 0:9b334a45a8ff 420 * @brief Disables the Power Voltage Detector(PVD).
bogdanm 0:9b334a45a8ff 421 * @retval None
bogdanm 0:9b334a45a8ff 422 */
bogdanm 0:9b334a45a8ff 423 void HAL_PWR_DisablePVD(void)
bogdanm 0:9b334a45a8ff 424 {
bogdanm 0:9b334a45a8ff 425 /* Disable the power voltage detector */
bogdanm 0:9b334a45a8ff 426 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
bogdanm 0:9b334a45a8ff 427 }
bogdanm 0:9b334a45a8ff 428
bogdanm 0:9b334a45a8ff 429 /**
bogdanm 0:9b334a45a8ff 430 * @brief Enables the WakeUp PINx functionality.
bogdanm 0:9b334a45a8ff 431 * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
bogdanm 0:9b334a45a8ff 432 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 433 * @arg PWR_WAKEUP_PIN1
bogdanm 0:9b334a45a8ff 434 * @arg PWR_WAKEUP_PIN2
bogdanm 0:9b334a45a8ff 435 * @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only.
bogdanm 0:9b334a45a8ff 436 * @retval None
bogdanm 0:9b334a45a8ff 437 */
bogdanm 0:9b334a45a8ff 438 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
bogdanm 0:9b334a45a8ff 439 {
bogdanm 0:9b334a45a8ff 440 /* Check the parameter */
bogdanm 0:9b334a45a8ff 441 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
bogdanm 0:9b334a45a8ff 442 /* Enable the EWUPx pin */
bogdanm 0:9b334a45a8ff 443 SET_BIT(PWR->CSR, WakeUpPinx);
bogdanm 0:9b334a45a8ff 444 }
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /**
bogdanm 0:9b334a45a8ff 447 * @brief Disables the WakeUp PINx functionality.
bogdanm 0:9b334a45a8ff 448 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
bogdanm 0:9b334a45a8ff 449 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 450 * @arg PWR_WAKEUP_PIN1
bogdanm 0:9b334a45a8ff 451 * @arg PWR_WAKEUP_PIN2
bogdanm 0:9b334a45a8ff 452 * @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only.
bogdanm 0:9b334a45a8ff 453 * @retval None
bogdanm 0:9b334a45a8ff 454 */
bogdanm 0:9b334a45a8ff 455 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
bogdanm 0:9b334a45a8ff 456 {
bogdanm 0:9b334a45a8ff 457 /* Check the parameter */
bogdanm 0:9b334a45a8ff 458 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
bogdanm 0:9b334a45a8ff 459 /* Disable the EWUPx pin */
bogdanm 0:9b334a45a8ff 460 CLEAR_BIT(PWR->CSR, WakeUpPinx);
bogdanm 0:9b334a45a8ff 461 }
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 /**
bogdanm 0:9b334a45a8ff 464 * @brief Enters Sleep mode.
bogdanm 0:9b334a45a8ff 465 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 466 * @param Regulator: Specifies the regulator state in SLEEP mode.
bogdanm 0:9b334a45a8ff 467 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 468 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
bogdanm 0:9b334a45a8ff 469 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
bogdanm 0:9b334a45a8ff 470 * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 471 * When WFI entry is used, tick interrupt have to be disabled if not desired as
bogdanm 0:9b334a45a8ff 472 * the interrupt wake up source.
bogdanm 0:9b334a45a8ff 473 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 474 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
bogdanm 0:9b334a45a8ff 475 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
bogdanm 0:9b334a45a8ff 476 * @retval None
bogdanm 0:9b334a45a8ff 477 */
bogdanm 0:9b334a45a8ff 478 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
bogdanm 0:9b334a45a8ff 479 {
bogdanm 0:9b334a45a8ff 480 uint32_t tmpreg = 0;
bogdanm 0:9b334a45a8ff 481 /* Check the parameters */
bogdanm 0:9b334a45a8ff 482 assert_param(IS_PWR_REGULATOR(Regulator));
bogdanm 0:9b334a45a8ff 483 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 /* Select the regulator state in Sleep mode ---------------------------------*/
bogdanm 0:9b334a45a8ff 486 tmpreg = PWR->CR;
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 /* Clear PDDS and LPDS bits */
bogdanm 0:9b334a45a8ff 489 CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491 /* Set LPSDSR bit according to PWR_Regulator value */
bogdanm 0:9b334a45a8ff 492 SET_BIT(tmpreg, Regulator);
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 /* Store the new value */
bogdanm 0:9b334a45a8ff 495 PWR->CR = tmpreg;
bogdanm 0:9b334a45a8ff 496
bogdanm 0:9b334a45a8ff 497 /* Clear SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 498 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 /* Select SLEEP mode entry -------------------------------------------------*/
bogdanm 0:9b334a45a8ff 501 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
bogdanm 0:9b334a45a8ff 502 {
bogdanm 0:9b334a45a8ff 503 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 504 __WFI();
bogdanm 0:9b334a45a8ff 505 }
bogdanm 0:9b334a45a8ff 506 else
bogdanm 0:9b334a45a8ff 507 {
bogdanm 0:9b334a45a8ff 508 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 509 __SEV();
bogdanm 0:9b334a45a8ff 510 __WFE();
bogdanm 0:9b334a45a8ff 511 __WFE();
bogdanm 0:9b334a45a8ff 512 }
bogdanm 0:9b334a45a8ff 513 }
bogdanm 0:9b334a45a8ff 514
bogdanm 0:9b334a45a8ff 515 /**
bogdanm 0:9b334a45a8ff 516 * @brief Enters Stop mode.
bogdanm 0:9b334a45a8ff 517 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 518 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
bogdanm 0:9b334a45a8ff 519 * MSI or HSI16 RCoscillator is selected as system clock depending
bogdanm 0:9b334a45a8ff 520 * the bit STOPWUCK in the RCC_CFGR register.
bogdanm 0:9b334a45a8ff 521 * @note When the voltage regulator operates in low power mode, an additional
bogdanm 0:9b334a45a8ff 522 * startup delay is incurred when waking up from Stop mode.
bogdanm 0:9b334a45a8ff 523 * By keeping the internal regulator ON during Stop mode, the consumption
mbed_official 113:b3775bf36a83 524 * is higher although the startup time is reduced.
mbed_official 113:b3775bf36a83 525 * @note Before entering in this function, it is important to ensure that the WUF
mbed_official 113:b3775bf36a83 526 * wakeup flag is cleared. To perform this action, it is possible to call the
mbed_official 113:b3775bf36a83 527 * following macro : __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU)
mbed_official 113:b3775bf36a83 528 *
bogdanm 0:9b334a45a8ff 529 * @param Regulator: Specifies the regulator state in Stop mode.
bogdanm 0:9b334a45a8ff 530 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 531 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
bogdanm 0:9b334a45a8ff 532 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
bogdanm 0:9b334a45a8ff 533 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 534 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 535 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
bogdanm 0:9b334a45a8ff 536 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
bogdanm 0:9b334a45a8ff 537 * @retval None
bogdanm 0:9b334a45a8ff 538 */
bogdanm 0:9b334a45a8ff 539 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
bogdanm 0:9b334a45a8ff 540 {
bogdanm 0:9b334a45a8ff 541 uint32_t tmpreg = 0;
bogdanm 0:9b334a45a8ff 542
bogdanm 0:9b334a45a8ff 543 /* Check the parameters */
bogdanm 0:9b334a45a8ff 544 assert_param(IS_PWR_REGULATOR(Regulator));
bogdanm 0:9b334a45a8ff 545 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 /* Select the regulator state in Stop mode ---------------------------------*/
bogdanm 0:9b334a45a8ff 548 tmpreg = PWR->CR;
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 /* Clear PDDS and LPDS bits */
bogdanm 0:9b334a45a8ff 551 CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));
bogdanm 0:9b334a45a8ff 552
bogdanm 0:9b334a45a8ff 553 /* Set LPSDSR bit according to PWR_Regulator value */
bogdanm 0:9b334a45a8ff 554 SET_BIT(tmpreg, Regulator);
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556 /* Store the new value */
bogdanm 0:9b334a45a8ff 557 PWR->CR = tmpreg;
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 560 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
bogdanm 0:9b334a45a8ff 561
bogdanm 0:9b334a45a8ff 562 /* Select Stop mode entry --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 563 if(STOPEntry == PWR_STOPENTRY_WFI)
bogdanm 0:9b334a45a8ff 564 {
bogdanm 0:9b334a45a8ff 565 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 566 __WFI();
bogdanm 0:9b334a45a8ff 567 }
bogdanm 0:9b334a45a8ff 568 else
bogdanm 0:9b334a45a8ff 569 {
bogdanm 0:9b334a45a8ff 570 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 571 __SEV();
bogdanm 0:9b334a45a8ff 572 __WFE();
bogdanm 0:9b334a45a8ff 573 __WFE();
bogdanm 0:9b334a45a8ff 574 }
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 /* Reset SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 577 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 }
bogdanm 0:9b334a45a8ff 580
bogdanm 0:9b334a45a8ff 581 /**
bogdanm 0:9b334a45a8ff 582 * @brief Enters Standby mode.
bogdanm 0:9b334a45a8ff 583 * @note In Standby mode, all I/O pins are high impedance except for:
bogdanm 0:9b334a45a8ff 584 * - Reset pad (still available)
bogdanm 0:9b334a45a8ff 585 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
bogdanm 0:9b334a45a8ff 586 * Alarm out, or RTC clock calibration out.
bogdanm 0:9b334a45a8ff 587 * - RTC_AF2 pin (PC13) if configured for tamper.
bogdanm 0:9b334a45a8ff 588 * - WKUP pin 1 (PA00) if enabled.
bogdanm 0:9b334a45a8ff 589 * - WKUP pin 2 (PC13) if enabled.
bogdanm 0:9b334a45a8ff 590 * - WKUP pin 3 (PE06) if enabled, for stm32l07xxx and stm32l08xxx devices only.
bogdanm 0:9b334a45a8ff 591 * - WKUP pin 3 (PA02) if enabled, for stm32l031xx devices only.
bogdanm 0:9b334a45a8ff 592 * @retval None
bogdanm 0:9b334a45a8ff 593 */
bogdanm 0:9b334a45a8ff 594 void HAL_PWR_EnterSTANDBYMode(void)
bogdanm 0:9b334a45a8ff 595 {
bogdanm 0:9b334a45a8ff 596 /* Select Standby mode */
bogdanm 0:9b334a45a8ff 597 SET_BIT(PWR->CR, PWR_CR_PDDS);
bogdanm 0:9b334a45a8ff 598
bogdanm 0:9b334a45a8ff 599 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 600 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 /* This option is used to ensure that store operations are completed */
bogdanm 0:9b334a45a8ff 603 #if defined ( __CC_ARM)
bogdanm 0:9b334a45a8ff 604 __force_stores();
bogdanm 0:9b334a45a8ff 605 #endif
bogdanm 0:9b334a45a8ff 606 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 607 __WFI();
bogdanm 0:9b334a45a8ff 608 }
bogdanm 0:9b334a45a8ff 609
bogdanm 0:9b334a45a8ff 610 /**
bogdanm 0:9b334a45a8ff 611 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
bogdanm 0:9b334a45a8ff 612 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
bogdanm 0:9b334a45a8ff 613 * re-enters SLEEP mode when an interruption handling is over.
bogdanm 0:9b334a45a8ff 614 * Setting this bit is useful when the processor is expected to run only on
bogdanm 0:9b334a45a8ff 615 * interruptions handling.
bogdanm 0:9b334a45a8ff 616 * @retval None
bogdanm 0:9b334a45a8ff 617 */
bogdanm 0:9b334a45a8ff 618 void HAL_PWR_EnableSleepOnExit(void)
bogdanm 0:9b334a45a8ff 619 {
bogdanm 0:9b334a45a8ff 620 /* Set SLEEPONEXIT bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 621 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
bogdanm 0:9b334a45a8ff 622 }
bogdanm 0:9b334a45a8ff 623
bogdanm 0:9b334a45a8ff 624
bogdanm 0:9b334a45a8ff 625 /**
bogdanm 0:9b334a45a8ff 626 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
bogdanm 0:9b334a45a8ff 627 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
bogdanm 0:9b334a45a8ff 628 * re-enters SLEEP mode when an interruption handling is over.
bogdanm 0:9b334a45a8ff 629 * @retval None
bogdanm 0:9b334a45a8ff 630 */
bogdanm 0:9b334a45a8ff 631 void HAL_PWR_DisableSleepOnExit(void)
bogdanm 0:9b334a45a8ff 632 {
bogdanm 0:9b334a45a8ff 633 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 634 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
bogdanm 0:9b334a45a8ff 635 }
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638 /**
bogdanm 0:9b334a45a8ff 639 * @brief Enables CORTEX M0+ SEVONPEND bit.
bogdanm 0:9b334a45a8ff 640 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
bogdanm 0:9b334a45a8ff 641 * WFE to wake up when an interrupt moves from inactive to pended.
bogdanm 0:9b334a45a8ff 642 * @retval None
bogdanm 0:9b334a45a8ff 643 */
bogdanm 0:9b334a45a8ff 644 void HAL_PWR_EnableSEVOnPend(void)
bogdanm 0:9b334a45a8ff 645 {
bogdanm 0:9b334a45a8ff 646 /* Set SEVONPEND bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 647 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
bogdanm 0:9b334a45a8ff 648 }
bogdanm 0:9b334a45a8ff 649
bogdanm 0:9b334a45a8ff 650
bogdanm 0:9b334a45a8ff 651 /**
bogdanm 0:9b334a45a8ff 652 * @brief Disables CORTEX M0+ SEVONPEND bit.
bogdanm 0:9b334a45a8ff 653 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
bogdanm 0:9b334a45a8ff 654 * WFE to wake up when an interrupt moves from inactive to pended.
bogdanm 0:9b334a45a8ff 655 * @retval None
bogdanm 0:9b334a45a8ff 656 */
bogdanm 0:9b334a45a8ff 657 void HAL_PWR_DisableSEVOnPend(void)
bogdanm 0:9b334a45a8ff 658 {
bogdanm 0:9b334a45a8ff 659 /* Clear SEVONPEND bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 660 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
bogdanm 0:9b334a45a8ff 661 }
bogdanm 0:9b334a45a8ff 662
bogdanm 0:9b334a45a8ff 663 /**
bogdanm 0:9b334a45a8ff 664 * @brief This function handles the PWR PVD interrupt request.
bogdanm 0:9b334a45a8ff 665 * @note This API should be called under the PVD_IRQHandler().
bogdanm 0:9b334a45a8ff 666 * @retval None
bogdanm 0:9b334a45a8ff 667 */
bogdanm 0:9b334a45a8ff 668 void HAL_PWR_PVD_IRQHandler(void)
bogdanm 0:9b334a45a8ff 669 {
bogdanm 0:9b334a45a8ff 670 /* Check PWR exti flag */
bogdanm 0:9b334a45a8ff 671 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
bogdanm 0:9b334a45a8ff 672 {
bogdanm 0:9b334a45a8ff 673 /* PWR PVD interrupt user callback */
bogdanm 0:9b334a45a8ff 674 HAL_PWR_PVDCallback();
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676 /* Clear PWR Exti pending bit */
bogdanm 0:9b334a45a8ff 677 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
bogdanm 0:9b334a45a8ff 678 }
bogdanm 0:9b334a45a8ff 679 }
bogdanm 0:9b334a45a8ff 680
bogdanm 0:9b334a45a8ff 681 /**
bogdanm 0:9b334a45a8ff 682 * @brief PWR PVD interrupt callback
bogdanm 0:9b334a45a8ff 683 * @retval None
bogdanm 0:9b334a45a8ff 684 */
bogdanm 0:9b334a45a8ff 685 __weak void HAL_PWR_PVDCallback(void)
bogdanm 0:9b334a45a8ff 686 {
bogdanm 0:9b334a45a8ff 687 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 688 the HAL_PWR_PVDCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 689 */
bogdanm 0:9b334a45a8ff 690 }
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 /**
bogdanm 0:9b334a45a8ff 693 * @}
bogdanm 0:9b334a45a8ff 694 */
bogdanm 0:9b334a45a8ff 695
bogdanm 0:9b334a45a8ff 696 /**
bogdanm 0:9b334a45a8ff 697 * @}
bogdanm 0:9b334a45a8ff 698 */
bogdanm 0:9b334a45a8ff 699
bogdanm 0:9b334a45a8ff 700 #endif /* HAL_PWR_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 701 /**
bogdanm 0:9b334a45a8ff 702 * @}
bogdanm 0:9b334a45a8ff 703 */
bogdanm 0:9b334a45a8ff 704
bogdanm 0:9b334a45a8ff 705 /**
bogdanm 0:9b334a45a8ff 706 * @}
bogdanm 0:9b334a45a8ff 707 */
bogdanm 0:9b334a45a8ff 708
bogdanm 0:9b334a45a8ff 709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bogdanm 0:9b334a45a8ff 710