mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

Dependents: IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.c@113:b3775bf36a83, 2016-04-19 (annotated)

Committer:: mbed_official
Date:: Tue Apr 19 11:15:15 2016 +0100
Revision:: 113:b3775bf36a83
Parent:: 0:9b334a45a8ff

Synchronized with git revision 896981126b34b6d9441e3eea77881c67a1ae3dbd

Full URL: https://github.com/mbedmicro/mbed/commit/896981126b34b6d9441e3eea77881c67a1ae3dbd/

Exporter tool addition for e2 studio

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l0xx_hal_i2c.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	113:b3775bf36a83	5	* @version V1.5.0
mbed_official	113:b3775bf36a83	6	* @date 8-January-2016
bogdanm	0:9b334a45a8ff	7	* @brief I2C HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Inter Integrated Circuit (I2C) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + IO operation functions
bogdanm	0:9b334a45a8ff	12	* + Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	13	*
bogdanm	0:9b334a45a8ff	14	@verbatim
bogdanm	0:9b334a45a8ff	15	==============================================================================
bogdanm	0:9b334a45a8ff	16	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	17	==============================================================================
bogdanm	0:9b334a45a8ff	18	[..]
bogdanm	0:9b334a45a8ff	19	The I2C HAL driver can be used as follows:
bogdanm	0:9b334a45a8ff	20
bogdanm	0:9b334a45a8ff	21	(#) Declare a I2C_HandleTypeDef handle structure, for example:
bogdanm	0:9b334a45a8ff	22	I2C_HandleTypeDef hi2c;
bogdanm	0:9b334a45a8ff	23
bogdanm	0:9b334a45a8ff	24	(#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit ()API:
bogdanm	0:9b334a45a8ff	25	(##) Enable the I2Cx interface clock
bogdanm	0:9b334a45a8ff	26	(##) I2C pins configuration
bogdanm	0:9b334a45a8ff	27	(+++) Enable the clock for the I2C GPIOs
bogdanm	0:9b334a45a8ff	28	(+++) Configure I2C pins as alternate function open-drain
bogdanm	0:9b334a45a8ff	29	(##) NVIC configuration if you need to use interrupt process
bogdanm	0:9b334a45a8ff	30	(+++) Configure the I2Cx interrupt priority
bogdanm	0:9b334a45a8ff	31	(+++) Enable the NVIC I2C IRQ Channel
bogdanm	0:9b334a45a8ff	32	(##) DMA Configuration if you need to use DMA process
bogdanm	0:9b334a45a8ff	33	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
bogdanm	0:9b334a45a8ff	34	(+++) Enable the DMAx interface clock using
bogdanm	0:9b334a45a8ff	35	(+++) Configure the DMA handle parameters
bogdanm	0:9b334a45a8ff	36	(+++) Configure the DMA Tx or Rx channel
bogdanm	0:9b334a45a8ff	37	(+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle
bogdanm	0:9b334a45a8ff	38	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
bogdanm	0:9b334a45a8ff	39	the DMA Tx or Rx channel
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	(#) Configure the Communication Clock Timing, Own Address1, Master Adressing Mode, Dual Addressing mode,
bogdanm	0:9b334a45a8ff	42	Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	(#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
bogdanm	0:9b334a45a8ff	45	(GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API.
bogdanm	0:9b334a45a8ff	46
bogdanm	0:9b334a45a8ff	47	(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
bogdanm	0:9b334a45a8ff	50
bogdanm	0:9b334a45a8ff	51	* Polling mode IO operation *
bogdanm	0:9b334a45a8ff	52	=================================
bogdanm	0:9b334a45a8ff	53	[..]
bogdanm	0:9b334a45a8ff	54	(+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
bogdanm	0:9b334a45a8ff	55	(+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
bogdanm	0:9b334a45a8ff	56	(+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
bogdanm	0:9b334a45a8ff	57	(+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
bogdanm	0:9b334a45a8ff	58
bogdanm	0:9b334a45a8ff	59	* Polling mode IO MEM operation *
bogdanm	0:9b334a45a8ff	60	=====================================
bogdanm	0:9b334a45a8ff	61	[..]
bogdanm	0:9b334a45a8ff	62	(+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
bogdanm	0:9b334a45a8ff	63	(+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
bogdanm	0:9b334a45a8ff	64
bogdanm	0:9b334a45a8ff	65
bogdanm	0:9b334a45a8ff	66	* Interrupt mode IO operation *
bogdanm	0:9b334a45a8ff	67	===================================
bogdanm	0:9b334a45a8ff	68	[..]
bogdanm	0:9b334a45a8ff	69	(+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
bogdanm	0:9b334a45a8ff	70	(+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	71	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
bogdanm	0:9b334a45a8ff	72	(+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
bogdanm	0:9b334a45a8ff	73	(+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	74	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
bogdanm	0:9b334a45a8ff	75	(+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
bogdanm	0:9b334a45a8ff	76	(+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	77	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
bogdanm	0:9b334a45a8ff	78	(+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
bogdanm	0:9b334a45a8ff	79	(+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	80	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
bogdanm	0:9b334a45a8ff	81	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	82	add his own code by customization of function pointer HAL_I2C_ErrorCallback
bogdanm	0:9b334a45a8ff	83
bogdanm	0:9b334a45a8ff	84	* Interrupt mode IO MEM operation *
bogdanm	0:9b334a45a8ff	85	=======================================
bogdanm	0:9b334a45a8ff	86	[..]
bogdanm	0:9b334a45a8ff	87	(+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
bogdanm	0:9b334a45a8ff	88	HAL_I2C_Mem_Write_IT()
bogdanm	0:9b334a45a8ff	89	(+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	90	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
bogdanm	0:9b334a45a8ff	91	(+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
bogdanm	0:9b334a45a8ff	92	HAL_I2C_Mem_Read_IT()
bogdanm	0:9b334a45a8ff	93	(+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	94	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
bogdanm	0:9b334a45a8ff	95	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	96	add his own code by customization of function pointer HAL_I2C_ErrorCallback
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	* DMA mode IO operation *
bogdanm	0:9b334a45a8ff	99	==============================
bogdanm	0:9b334a45a8ff	100	[..]
bogdanm	0:9b334a45a8ff	101	(+) Transmit in master mode an amount of data in non blocking mode (DMA) using
bogdanm	0:9b334a45a8ff	102	HAL_I2C_Master_Transmit_DMA()
bogdanm	0:9b334a45a8ff	103	(+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	104	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
bogdanm	0:9b334a45a8ff	105	(+) Receive in master mode an amount of data in non blocking mode (DMA) using
bogdanm	0:9b334a45a8ff	106	HAL_I2C_Master_Receive_DMA()
bogdanm	0:9b334a45a8ff	107	(+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	108	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
bogdanm	0:9b334a45a8ff	109	(+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
bogdanm	0:9b334a45a8ff	110	HAL_I2C_Slave_Transmit_DMA()
bogdanm	0:9b334a45a8ff	111	(+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	112	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
bogdanm	0:9b334a45a8ff	113	(+) Receive in slave mode an amount of data in non blocking mode (DMA) using
bogdanm	0:9b334a45a8ff	114	HAL_I2C_Slave_Receive_DMA()
bogdanm	0:9b334a45a8ff	115	(+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	116	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
bogdanm	0:9b334a45a8ff	117	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	118	add his own code by customization of function pointer HAL_I2C_ErrorCallback
bogdanm	0:9b334a45a8ff	119
bogdanm	0:9b334a45a8ff	120	* DMA mode IO MEM operation *
bogdanm	0:9b334a45a8ff	121	=================================
bogdanm	0:9b334a45a8ff	122	[..]
bogdanm	0:9b334a45a8ff	123	(+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
bogdanm	0:9b334a45a8ff	124	HAL_I2C_Mem_Write_DMA()
bogdanm	0:9b334a45a8ff	125	(+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	126	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
bogdanm	0:9b334a45a8ff	127	(+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
bogdanm	0:9b334a45a8ff	128	HAL_I2C_Mem_Read_DMA()
bogdanm	0:9b334a45a8ff	129	(+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	130	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
bogdanm	0:9b334a45a8ff	131	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	132	add his own code by customization of function pointer HAL_I2C_ErrorCallback
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	* I2C HAL driver macros list *
bogdanm	0:9b334a45a8ff	136	==================================
bogdanm	0:9b334a45a8ff	137	[..]
bogdanm	0:9b334a45a8ff	138	Below the list of most used macros in I2C HAL driver.
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
bogdanm	0:9b334a45a8ff	141	(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
bogdanm	0:9b334a45a8ff	142	(+) __HAL_I2C_GET_FLAG : Check whether the specified I2C flag is set or not
bogdanm	0:9b334a45a8ff	143	(+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
bogdanm	0:9b334a45a8ff	144	(+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
bogdanm	0:9b334a45a8ff	145	(+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	[..]
bogdanm	0:9b334a45a8ff	148	(@) You can refer to the I2C HAL driver header file for more useful macros
bogdanm	0:9b334a45a8ff	149
bogdanm	0:9b334a45a8ff	150	@endverbatim
bogdanm	0:9b334a45a8ff	151	******************************************************************************
bogdanm	0:9b334a45a8ff	152	* @attention
bogdanm	0:9b334a45a8ff	153	*
mbed_official	113:b3775bf36a83	154	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	155	*
bogdanm	0:9b334a45a8ff	156	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	157	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	158	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	159	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	160	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	161	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	162	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	163	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	164	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	165	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	166	*
bogdanm	0:9b334a45a8ff	167	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	168	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	169	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	170	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	171	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	172	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	173	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	174	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	175	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	176	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	177	*
bogdanm	0:9b334a45a8ff	178	******************************************************************************
bogdanm	0:9b334a45a8ff	179	*/
bogdanm	0:9b334a45a8ff	180
bogdanm	0:9b334a45a8ff	181	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	182	#include "stm32l0xx_hal.h"
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	185	* @{
bogdanm	0:9b334a45a8ff	186	*/
bogdanm	0:9b334a45a8ff	187
mbed_official	113:b3775bf36a83	188	#ifdef HAL_I2C_MODULE_ENABLED
mbed_official	113:b3775bf36a83	189
mbed_official	113:b3775bf36a83	190	/** @addtogroup I2C I2C
bogdanm	0:9b334a45a8ff	191	* @brief I2C HAL module driver
bogdanm	0:9b334a45a8ff	192	* @{
bogdanm	0:9b334a45a8ff	193	*/
bogdanm	0:9b334a45a8ff	194
bogdanm	0:9b334a45a8ff	195	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	196	/* Private constants ---------------------------------------------------------*/
mbed_official	113:b3775bf36a83	197	/** @addtogroup I2C_Private
bogdanm	0:9b334a45a8ff	198	* @{
bogdanm	0:9b334a45a8ff	199	*/
bogdanm	0:9b334a45a8ff	200	#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /<! I2C TIMING clear register Mask /
bogdanm	0:9b334a45a8ff	201	#define I2C_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
bogdanm	0:9b334a45a8ff	202	#define I2C_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	203	#define I2C_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	204	#define I2C_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	205	#define I2C_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	206	#define I2C_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	207	#define I2C_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	208	#define I2C_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	209	#define I2C_TIMEOUT_FLAG ((uint32_t)25) /* 25 ms */
bogdanm	0:9b334a45a8ff	210	/**
bogdanm	0:9b334a45a8ff	211	* @}
bogdanm	0:9b334a45a8ff	212	*/
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	215	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	216	/* Private function prototypes -----------------------------------------------*/
mbed_official	113:b3775bf36a83	217	/** @addtogroup I2C_Private
bogdanm	0:9b334a45a8ff	218	* @{
bogdanm	0:9b334a45a8ff	219	*/
bogdanm	0:9b334a45a8ff	220	static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	221	static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	222	static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	223	static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	224	static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	225	static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	226	static void I2C_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	229	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	230	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	231	static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	232	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	233	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	234	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	235
bogdanm	0:9b334a45a8ff	236	static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c);
bogdanm	0:9b334a45a8ff	237	static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c);
bogdanm	0:9b334a45a8ff	238
bogdanm	0:9b334a45a8ff	239	static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c);
bogdanm	0:9b334a45a8ff	240	static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c);
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
bogdanm	0:9b334a45a8ff	243	/**
bogdanm	0:9b334a45a8ff	244	* @}
bogdanm	0:9b334a45a8ff	245	*/
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	248
mbed_official	113:b3775bf36a83	249	/** @addtogroup I2C_Exported_Functions
bogdanm	0:9b334a45a8ff	250	* @{
bogdanm	0:9b334a45a8ff	251	*/
bogdanm	0:9b334a45a8ff	252
mbed_official	113:b3775bf36a83	253	/** @addtogroup I2C_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	254	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	255	*
bogdanm	0:9b334a45a8ff	256	@verbatim
bogdanm	0:9b334a45a8ff	257	===============================================================================
bogdanm	0:9b334a45a8ff	258	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	259	===============================================================================
bogdanm	0:9b334a45a8ff	260	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	261	de-initialiaze the I2Cx peripheral:
bogdanm	0:9b334a45a8ff	262
bogdanm	0:9b334a45a8ff	263	(+) User must Implement HAL_I2C_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	264	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	265
bogdanm	0:9b334a45a8ff	266	(+) Call the function HAL_I2C_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	267	the selected configuration:
bogdanm	0:9b334a45a8ff	268	(++) Clock Timing
bogdanm	0:9b334a45a8ff	269	(++) Own Address 1
bogdanm	0:9b334a45a8ff	270	(++) Addressing mode (Master, Slave)
bogdanm	0:9b334a45a8ff	271	(++) Dual Addressing mode
bogdanm	0:9b334a45a8ff	272	(++) Own Address 2
bogdanm	0:9b334a45a8ff	273	(++) Own Address 2 Mask
bogdanm	0:9b334a45a8ff	274	(++) General call mode
bogdanm	0:9b334a45a8ff	275	(++) Nostretch mode
bogdanm	0:9b334a45a8ff	276
bogdanm	0:9b334a45a8ff	277	(+) Call the function HAL_I2C_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	278	of the selected I2Cx periperal.
bogdanm	0:9b334a45a8ff	279
bogdanm	0:9b334a45a8ff	280	@endverbatim
bogdanm	0:9b334a45a8ff	281	* @{
bogdanm	0:9b334a45a8ff	282	*/
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	/**
bogdanm	0:9b334a45a8ff	285	* @brief Initializes the I2C according to the specified parameters
bogdanm	0:9b334a45a8ff	286	* in the I2C_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	287	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	288	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	289	* @retval HAL status
bogdanm	0:9b334a45a8ff	290	*/
bogdanm	0:9b334a45a8ff	291	HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	292	{
bogdanm	0:9b334a45a8ff	293	/* Check the I2C handle allocation */
bogdanm	0:9b334a45a8ff	294	if(hi2c == NULL)
bogdanm	0:9b334a45a8ff	295	{
bogdanm	0:9b334a45a8ff	296	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	297	}
bogdanm	0:9b334a45a8ff	298
bogdanm	0:9b334a45a8ff	299	/* Check the parameters */
bogdanm	0:9b334a45a8ff	300	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
bogdanm	0:9b334a45a8ff	301	assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
bogdanm	0:9b334a45a8ff	302	assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
bogdanm	0:9b334a45a8ff	303	assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
bogdanm	0:9b334a45a8ff	304	assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
bogdanm	0:9b334a45a8ff	305	assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
bogdanm	0:9b334a45a8ff	306	assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
bogdanm	0:9b334a45a8ff	307	assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
bogdanm	0:9b334a45a8ff	308
bogdanm	0:9b334a45a8ff	309	if(hi2c->State == HAL_I2C_STATE_RESET)
bogdanm	0:9b334a45a8ff	310	{
mbed_official	113:b3775bf36a83	311	/* Allocate lock resource and initialize it */
mbed_official	113:b3775bf36a83	312	hi2c->Lock = HAL_UNLOCKED;
mbed_official	113:b3775bf36a83	313
bogdanm	0:9b334a45a8ff	314	/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
bogdanm	0:9b334a45a8ff	315	HAL_I2C_MspInit(hi2c);
bogdanm	0:9b334a45a8ff	316	}
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	hi2c->State = HAL_I2C_STATE_BUSY;
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320	/* Disable the selected I2C peripheral */
bogdanm	0:9b334a45a8ff	321	__HAL_I2C_DISABLE(hi2c);
bogdanm	0:9b334a45a8ff	322
bogdanm	0:9b334a45a8ff	323	/---------------------------- I2Cx TIMINGR Configuration ------------------/
bogdanm	0:9b334a45a8ff	324	/* Configure I2Cx: Frequency range */
bogdanm	0:9b334a45a8ff	325	hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	/---------------------------- I2Cx OAR1 Configuration ---------------------/
bogdanm	0:9b334a45a8ff	328	/* Configure I2Cx: Own Address1 and ack own address1 mode */
bogdanm	0:9b334a45a8ff	329	hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
bogdanm	0:9b334a45a8ff	330	if(hi2c->Init.OwnAddress1 != 0)
bogdanm	0:9b334a45a8ff	331	{
bogdanm	0:9b334a45a8ff	332	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
bogdanm	0:9b334a45a8ff	333	{
bogdanm	0:9b334a45a8ff	334	hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN \| hi2c->Init.OwnAddress1);
bogdanm	0:9b334a45a8ff	335	}
bogdanm	0:9b334a45a8ff	336	else /* I2C_ADDRESSINGMODE_10BIT */
bogdanm	0:9b334a45a8ff	337	{
bogdanm	0:9b334a45a8ff	338	hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN \| I2C_OAR1_OA1MODE \| hi2c->Init.OwnAddress1);
bogdanm	0:9b334a45a8ff	339	}
bogdanm	0:9b334a45a8ff	340	}
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	/---------------------------- I2Cx CR2 Configuration ----------------------/
bogdanm	0:9b334a45a8ff	343	/* Configure I2Cx: Addressing Master mode */
bogdanm	0:9b334a45a8ff	344	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
bogdanm	0:9b334a45a8ff	345	{
bogdanm	0:9b334a45a8ff	346	hi2c->Instance->CR2 = (I2C_CR2_ADD10);
bogdanm	0:9b334a45a8ff	347	}
bogdanm	0:9b334a45a8ff	348	/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
bogdanm	0:9b334a45a8ff	349	hi2c->Instance->CR2 \|= (I2C_CR2_AUTOEND \| I2C_CR2_NACK);
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	/---------------------------- I2Cx OAR2 Configuration ---------------------/
bogdanm	0:9b334a45a8ff	352	/* Configure I2Cx: Dual mode and Own Address2 */
bogdanm	0:9b334a45a8ff	353	hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode \| hi2c->Init.OwnAddress2 \| (hi2c->Init.OwnAddress2Masks << 8));
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/---------------------------- I2Cx CR1 Configuration ----------------------/
bogdanm	0:9b334a45a8ff	356	/* Configure I2Cx: Generalcall and NoStretch mode */
bogdanm	0:9b334a45a8ff	357	hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode \| hi2c->Init.NoStretchMode);
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	/* Enable the selected I2C peripheral */
bogdanm	0:9b334a45a8ff	360	__HAL_I2C_ENABLE(hi2c);
bogdanm	0:9b334a45a8ff	361
bogdanm	0:9b334a45a8ff	362	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	363	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	364
bogdanm	0:9b334a45a8ff	365	return HAL_OK;
bogdanm	0:9b334a45a8ff	366	}
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/**
bogdanm	0:9b334a45a8ff	369	* @brief DeInitializes the I2C peripheral.
bogdanm	0:9b334a45a8ff	370	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	371	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	372	* @retval HAL status
bogdanm	0:9b334a45a8ff	373	*/
bogdanm	0:9b334a45a8ff	374	HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	375	{
bogdanm	0:9b334a45a8ff	376	/* Check the I2C handle allocation */
bogdanm	0:9b334a45a8ff	377	if(hi2c == NULL)
bogdanm	0:9b334a45a8ff	378	{
bogdanm	0:9b334a45a8ff	379	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	380	}
bogdanm	0:9b334a45a8ff	381
bogdanm	0:9b334a45a8ff	382	/* Check the parameters */
bogdanm	0:9b334a45a8ff	383	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
bogdanm	0:9b334a45a8ff	384
bogdanm	0:9b334a45a8ff	385	hi2c->State = HAL_I2C_STATE_BUSY;
bogdanm	0:9b334a45a8ff	386
bogdanm	0:9b334a45a8ff	387	/* Disable the I2C Peripheral Clock */
bogdanm	0:9b334a45a8ff	388	__HAL_I2C_DISABLE(hi2c);
bogdanm	0:9b334a45a8ff	389
bogdanm	0:9b334a45a8ff	390	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	391	HAL_I2C_MspDeInit(hi2c);
bogdanm	0:9b334a45a8ff	392
bogdanm	0:9b334a45a8ff	393	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	394
bogdanm	0:9b334a45a8ff	395	hi2c->State = HAL_I2C_STATE_RESET;
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397	/* Release Lock */
bogdanm	0:9b334a45a8ff	398	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	399
bogdanm	0:9b334a45a8ff	400	return HAL_OK;
bogdanm	0:9b334a45a8ff	401	}
bogdanm	0:9b334a45a8ff	402
bogdanm	0:9b334a45a8ff	403	/**
bogdanm	0:9b334a45a8ff	404	* @brief I2C MSP Init.
bogdanm	0:9b334a45a8ff	405	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	406	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	407	* @retval None
bogdanm	0:9b334a45a8ff	408	*/
bogdanm	0:9b334a45a8ff	409	__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	410	{
mbed_official	113:b3775bf36a83	411	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	412	UNUSED(hi2c);
mbed_official	113:b3775bf36a83	413
bogdanm	0:9b334a45a8ff	414	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	415	the HAL_I2C_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	416	*/
bogdanm	0:9b334a45a8ff	417	}
bogdanm	0:9b334a45a8ff	418
bogdanm	0:9b334a45a8ff	419	/**
bogdanm	0:9b334a45a8ff	420	* @brief I2C MSP DeInit
bogdanm	0:9b334a45a8ff	421	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	422	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	423	* @retval None
bogdanm	0:9b334a45a8ff	424	*/
bogdanm	0:9b334a45a8ff	425	__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	426	{
mbed_official	113:b3775bf36a83	427	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	428	UNUSED(hi2c);
mbed_official	113:b3775bf36a83	429
bogdanm	0:9b334a45a8ff	430	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	431	the HAL_I2C_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	432	*/
bogdanm	0:9b334a45a8ff	433	}
bogdanm	0:9b334a45a8ff	434
bogdanm	0:9b334a45a8ff	435	/**
bogdanm	0:9b334a45a8ff	436	* @}
bogdanm	0:9b334a45a8ff	437	*/
bogdanm	0:9b334a45a8ff	438
mbed_official	113:b3775bf36a83	439	/** @addtogroup I2C_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	440	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	441	*
bogdanm	0:9b334a45a8ff	442	@verbatim
bogdanm	0:9b334a45a8ff	443	===============================================================================
bogdanm	0:9b334a45a8ff	444	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	445	===============================================================================
bogdanm	0:9b334a45a8ff	446	[..]
bogdanm	0:9b334a45a8ff	447	This subsection provides a set of functions allowing to manage the I2C data
bogdanm	0:9b334a45a8ff	448	transfers.
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	(#) There are two modes of transfer:
bogdanm	0:9b334a45a8ff	451	(++) Blocking mode : The communication is performed in the polling mode.
bogdanm	0:9b334a45a8ff	452	The status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	453	after finishing transfer.
bogdanm	0:9b334a45a8ff	454	(++) No-Blocking mode : The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	455	or DMA. These functions return the status of the transfer startup.
bogdanm	0:9b334a45a8ff	456	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	457	dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	458	using DMA mode.
bogdanm	0:9b334a45a8ff	459
bogdanm	0:9b334a45a8ff	460	(#) Blocking mode functions are :
bogdanm	0:9b334a45a8ff	461	(++) HAL_I2C_Master_Transmit()
bogdanm	0:9b334a45a8ff	462	(++) HAL_I2C_Master_Receive()
bogdanm	0:9b334a45a8ff	463	(++) HAL_I2C_Slave_Transmit()
bogdanm	0:9b334a45a8ff	464	(++) HAL_I2C_Slave_Receive()
bogdanm	0:9b334a45a8ff	465	(++) HAL_I2C_Mem_Write()
bogdanm	0:9b334a45a8ff	466	(++) HAL_I2C_Mem_Read()
bogdanm	0:9b334a45a8ff	467	(++) HAL_I2C_IsDeviceReady()
bogdanm	0:9b334a45a8ff	468
bogdanm	0:9b334a45a8ff	469	(#) No-Blocking mode functions with Interrupt are :
bogdanm	0:9b334a45a8ff	470	(++) HAL_I2C_Master_Transmit_IT()
bogdanm	0:9b334a45a8ff	471	(++) HAL_I2C_Master_Receive_IT()
bogdanm	0:9b334a45a8ff	472	(++) HAL_I2C_Slave_Transmit_IT()
bogdanm	0:9b334a45a8ff	473	(++) HAL_I2C_Slave_Receive_IT()
bogdanm	0:9b334a45a8ff	474	(++) HAL_I2C_Mem_Write_IT()
bogdanm	0:9b334a45a8ff	475	(++) HAL_I2C_Mem_Read_IT()
bogdanm	0:9b334a45a8ff	476
bogdanm	0:9b334a45a8ff	477	(#) No-Blocking mode functions with DMA are :
bogdanm	0:9b334a45a8ff	478	(++) HAL_I2C_Master_Transmit_DMA()
bogdanm	0:9b334a45a8ff	479	(++) HAL_I2C_Master_Receive_DMA()
bogdanm	0:9b334a45a8ff	480	(++) HAL_I2C_Slave_Transmit_DMA()
bogdanm	0:9b334a45a8ff	481	(++) HAL_I2C_Slave_Receive_DMA()
bogdanm	0:9b334a45a8ff	482	(++) HAL_I2C_Mem_Write_DMA()
bogdanm	0:9b334a45a8ff	483	(++) HAL_I2C_Mem_Read_DMA()
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
bogdanm	0:9b334a45a8ff	486	(++) HAL_I2C_MemTxCpltCallback()
bogdanm	0:9b334a45a8ff	487	(++) HAL_I2C_MemRxCpltCallback()
bogdanm	0:9b334a45a8ff	488	(++) HAL_I2C_MasterTxCpltCallback()
bogdanm	0:9b334a45a8ff	489	(++) HAL_I2C_MasterRxCpltCallback()
bogdanm	0:9b334a45a8ff	490	(++) HAL_I2C_SlaveTxCpltCallback()
bogdanm	0:9b334a45a8ff	491	(++) HAL_I2C_SlaveRxCpltCallback()
bogdanm	0:9b334a45a8ff	492	(++) HAL_I2C_ErrorCallback()
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	@endverbatim
bogdanm	0:9b334a45a8ff	495	* @{
bogdanm	0:9b334a45a8ff	496	*/
bogdanm	0:9b334a45a8ff	497
bogdanm	0:9b334a45a8ff	498	/**
bogdanm	0:9b334a45a8ff	499	* @brief Transmits in master mode an amount of data in blocking mode.
bogdanm	0:9b334a45a8ff	500	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	501	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	502	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	503	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	504	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	505	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	506	* @retval HAL status
bogdanm	0:9b334a45a8ff	507	*/
bogdanm	0:9b334a45a8ff	508	HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	509	{
bogdanm	0:9b334a45a8ff	510	uint32_t sizetmp = 0;
bogdanm	0:9b334a45a8ff	511
bogdanm	0:9b334a45a8ff	512	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	513	{
bogdanm	0:9b334a45a8ff	514	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	515	{
bogdanm	0:9b334a45a8ff	516	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	517	}
bogdanm	0:9b334a45a8ff	518
bogdanm	0:9b334a45a8ff	519	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	520	{
bogdanm	0:9b334a45a8ff	521	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	522	}
bogdanm	0:9b334a45a8ff	523
bogdanm	0:9b334a45a8ff	524	/* Process Locked */
bogdanm	0:9b334a45a8ff	525	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
bogdanm	0:9b334a45a8ff	528	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	531	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
bogdanm	0:9b334a45a8ff	532	/* Size > 255, need to set RELOAD bit */
bogdanm	0:9b334a45a8ff	533	if(Size > 255)
bogdanm	0:9b334a45a8ff	534	{
bogdanm	0:9b334a45a8ff	535	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
bogdanm	0:9b334a45a8ff	536	sizetmp = 255;
bogdanm	0:9b334a45a8ff	537	}
bogdanm	0:9b334a45a8ff	538	else
bogdanm	0:9b334a45a8ff	539	{
bogdanm	0:9b334a45a8ff	540	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
bogdanm	0:9b334a45a8ff	541	sizetmp = Size;
bogdanm	0:9b334a45a8ff	542	}
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	do
bogdanm	0:9b334a45a8ff	545	{
bogdanm	0:9b334a45a8ff	546	/* Wait until TXIS flag is set */
bogdanm	0:9b334a45a8ff	547	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	548	{
bogdanm	0:9b334a45a8ff	549	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	550	{
bogdanm	0:9b334a45a8ff	551	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	552	}
bogdanm	0:9b334a45a8ff	553	else
bogdanm	0:9b334a45a8ff	554	{
bogdanm	0:9b334a45a8ff	555	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	556	}
bogdanm	0:9b334a45a8ff	557	}
bogdanm	0:9b334a45a8ff	558	/* Write data to TXDR */
bogdanm	0:9b334a45a8ff	559	hi2c->Instance->TXDR = (*pData++);
bogdanm	0:9b334a45a8ff	560	sizetmp--;
bogdanm	0:9b334a45a8ff	561	Size--;
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	if((sizetmp == 0)&&(Size!=0))
bogdanm	0:9b334a45a8ff	564	{
mbed_official	113:b3775bf36a83	565	/* Wait until TCR flag is set */
bogdanm	0:9b334a45a8ff	566	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	567	{
bogdanm	0:9b334a45a8ff	568	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	569	}
bogdanm	0:9b334a45a8ff	570
bogdanm	0:9b334a45a8ff	571	if(Size > 255)
bogdanm	0:9b334a45a8ff	572	{
bogdanm	0:9b334a45a8ff	573	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	574	sizetmp = 255;
bogdanm	0:9b334a45a8ff	575	}
bogdanm	0:9b334a45a8ff	576	else
bogdanm	0:9b334a45a8ff	577	{
bogdanm	0:9b334a45a8ff	578	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	579	sizetmp = Size;
bogdanm	0:9b334a45a8ff	580	}
bogdanm	0:9b334a45a8ff	581	}
bogdanm	0:9b334a45a8ff	582
bogdanm	0:9b334a45a8ff	583	}while(Size > 0);
bogdanm	0:9b334a45a8ff	584
bogdanm	0:9b334a45a8ff	585	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	586	/* Wait until STOPF flag is set */
bogdanm	0:9b334a45a8ff	587	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	588	{
bogdanm	0:9b334a45a8ff	589	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	590	{
bogdanm	0:9b334a45a8ff	591	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	592	}
bogdanm	0:9b334a45a8ff	593	else
bogdanm	0:9b334a45a8ff	594	{
bogdanm	0:9b334a45a8ff	595	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	596	}
bogdanm	0:9b334a45a8ff	597	}
bogdanm	0:9b334a45a8ff	598
bogdanm	0:9b334a45a8ff	599	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	600	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	603	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	604
bogdanm	0:9b334a45a8ff	605	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	608	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	return HAL_OK;
bogdanm	0:9b334a45a8ff	611	}
bogdanm	0:9b334a45a8ff	612	else
bogdanm	0:9b334a45a8ff	613	{
bogdanm	0:9b334a45a8ff	614	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	615	}
bogdanm	0:9b334a45a8ff	616	}
bogdanm	0:9b334a45a8ff	617
bogdanm	0:9b334a45a8ff	618	/**
bogdanm	0:9b334a45a8ff	619	* @brief Receives in master mode an amount of data in blocking mode.
bogdanm	0:9b334a45a8ff	620	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	621	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	622	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	623	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	624	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	625	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	626	* @retval HAL status
bogdanm	0:9b334a45a8ff	627	*/
bogdanm	0:9b334a45a8ff	628	HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	629	{
bogdanm	0:9b334a45a8ff	630	uint32_t sizetmp = 0;
bogdanm	0:9b334a45a8ff	631
bogdanm	0:9b334a45a8ff	632	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	633	{
bogdanm	0:9b334a45a8ff	634	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	635	{
bogdanm	0:9b334a45a8ff	636	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	637	}
bogdanm	0:9b334a45a8ff	638
bogdanm	0:9b334a45a8ff	639	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	640	{
bogdanm	0:9b334a45a8ff	641	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	642	}
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	/* Process Locked */
bogdanm	0:9b334a45a8ff	645	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	646
bogdanm	0:9b334a45a8ff	647	hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
bogdanm	0:9b334a45a8ff	648	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	649
bogdanm	0:9b334a45a8ff	650	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	651	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
bogdanm	0:9b334a45a8ff	652	/* Size > 255, need to set RELOAD bit */
bogdanm	0:9b334a45a8ff	653	if(Size > 255)
bogdanm	0:9b334a45a8ff	654	{
bogdanm	0:9b334a45a8ff	655	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	656	sizetmp = 255;
bogdanm	0:9b334a45a8ff	657	}
bogdanm	0:9b334a45a8ff	658	else
bogdanm	0:9b334a45a8ff	659	{
bogdanm	0:9b334a45a8ff	660	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	661	sizetmp = Size;
bogdanm	0:9b334a45a8ff	662	}
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	do
bogdanm	0:9b334a45a8ff	665	{
bogdanm	0:9b334a45a8ff	666	/* Wait until RXNE flag is set */
mbed_official	113:b3775bf36a83	667	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK)
bogdanm	0:9b334a45a8ff	668	{
mbed_official	113:b3775bf36a83	669	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
mbed_official	113:b3775bf36a83	670	{
mbed_official	113:b3775bf36a83	671	return HAL_ERROR;
mbed_official	113:b3775bf36a83	672	}
mbed_official	113:b3775bf36a83	673	else
mbed_official	113:b3775bf36a83	674	{
mbed_official	113:b3775bf36a83	675	return HAL_TIMEOUT;
mbed_official	113:b3775bf36a83	676	}
bogdanm	0:9b334a45a8ff	677	}
bogdanm	0:9b334a45a8ff	678
bogdanm	0:9b334a45a8ff	679	/* Write data to RXDR */
bogdanm	0:9b334a45a8ff	680	(*pData++) =hi2c->Instance->RXDR;
bogdanm	0:9b334a45a8ff	681	sizetmp--;
bogdanm	0:9b334a45a8ff	682	Size--;
bogdanm	0:9b334a45a8ff	683
bogdanm	0:9b334a45a8ff	684	if((sizetmp == 0)&&(Size!=0))
bogdanm	0:9b334a45a8ff	685	{
bogdanm	0:9b334a45a8ff	686	/* Wait until TCR flag is set */
bogdanm	0:9b334a45a8ff	687	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	688	{
bogdanm	0:9b334a45a8ff	689	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	690	}
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692	if(Size > 255)
bogdanm	0:9b334a45a8ff	693	{
bogdanm	0:9b334a45a8ff	694	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	695	sizetmp = 255;
bogdanm	0:9b334a45a8ff	696	}
bogdanm	0:9b334a45a8ff	697	else
bogdanm	0:9b334a45a8ff	698	{
bogdanm	0:9b334a45a8ff	699	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	700	sizetmp = Size;
bogdanm	0:9b334a45a8ff	701	}
bogdanm	0:9b334a45a8ff	702	}
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	}while(Size > 0);
bogdanm	0:9b334a45a8ff	705
bogdanm	0:9b334a45a8ff	706	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	707	/* Wait until STOPF flag is set */
bogdanm	0:9b334a45a8ff	708	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	709	{
bogdanm	0:9b334a45a8ff	710	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	713	}
bogdanm	0:9b334a45a8ff	714	else
bogdanm	0:9b334a45a8ff	715	{
bogdanm	0:9b334a45a8ff	716	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	717	}
bogdanm	0:9b334a45a8ff	718	}
bogdanm	0:9b334a45a8ff	719
bogdanm	0:9b334a45a8ff	720	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	721	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	722
bogdanm	0:9b334a45a8ff	723	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	724	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	725
bogdanm	0:9b334a45a8ff	726	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	727
bogdanm	0:9b334a45a8ff	728	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	729	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731	return HAL_OK;
bogdanm	0:9b334a45a8ff	732	}
bogdanm	0:9b334a45a8ff	733	else
bogdanm	0:9b334a45a8ff	734	{
bogdanm	0:9b334a45a8ff	735	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	736	}
bogdanm	0:9b334a45a8ff	737	}
bogdanm	0:9b334a45a8ff	738
bogdanm	0:9b334a45a8ff	739	/**
bogdanm	0:9b334a45a8ff	740	* @brief Transmits in slave mode an amount of data in blocking mode.
bogdanm	0:9b334a45a8ff	741	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	742	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	743	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	744	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	745	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	746	* @retval HAL status
bogdanm	0:9b334a45a8ff	747	*/
bogdanm	0:9b334a45a8ff	748	HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	749	{
bogdanm	0:9b334a45a8ff	750	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	751	{
bogdanm	0:9b334a45a8ff	752	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	753	{
bogdanm	0:9b334a45a8ff	754	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	755	}
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	/* Process Locked */
bogdanm	0:9b334a45a8ff	758	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760	hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
bogdanm	0:9b334a45a8ff	761	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	762
bogdanm	0:9b334a45a8ff	763	/* Enable Address Acknowledge */
bogdanm	0:9b334a45a8ff	764	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	765
bogdanm	0:9b334a45a8ff	766	/* Wait until ADDR flag is set */
bogdanm	0:9b334a45a8ff	767	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	768	{
bogdanm	0:9b334a45a8ff	769	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	770	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	771	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	772	}
bogdanm	0:9b334a45a8ff	773
bogdanm	0:9b334a45a8ff	774	/* Clear ADDR flag */
bogdanm	0:9b334a45a8ff	775	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
bogdanm	0:9b334a45a8ff	776
bogdanm	0:9b334a45a8ff	777	/* If 10bit addressing mode is selected */
bogdanm	0:9b334a45a8ff	778	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
bogdanm	0:9b334a45a8ff	779	{
bogdanm	0:9b334a45a8ff	780	/* Wait until ADDR flag is set */
bogdanm	0:9b334a45a8ff	781	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	782	{
bogdanm	0:9b334a45a8ff	783	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	784	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	785	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	786	}
bogdanm	0:9b334a45a8ff	787
bogdanm	0:9b334a45a8ff	788	/* Clear ADDR flag */
bogdanm	0:9b334a45a8ff	789	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
bogdanm	0:9b334a45a8ff	790	}
bogdanm	0:9b334a45a8ff	791
bogdanm	0:9b334a45a8ff	792	/* Wait until DIR flag is set Transmitter mode */
bogdanm	0:9b334a45a8ff	793	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	794	{
bogdanm	0:9b334a45a8ff	795	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	796	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	797	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	798	}
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	do
bogdanm	0:9b334a45a8ff	801	{
bogdanm	0:9b334a45a8ff	802	/* Wait until TXIS flag is set */
bogdanm	0:9b334a45a8ff	803	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	804	{
bogdanm	0:9b334a45a8ff	805	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	806	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	807
bogdanm	0:9b334a45a8ff	808	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	809	{
bogdanm	0:9b334a45a8ff	810	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	811	}
bogdanm	0:9b334a45a8ff	812	else
bogdanm	0:9b334a45a8ff	813	{
bogdanm	0:9b334a45a8ff	814	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	815	}
bogdanm	0:9b334a45a8ff	816	}
bogdanm	0:9b334a45a8ff	817
bogdanm	0:9b334a45a8ff	818	/* Read data from TXDR */
bogdanm	0:9b334a45a8ff	819	hi2c->Instance->TXDR = (*pData++);
bogdanm	0:9b334a45a8ff	820	Size--;
bogdanm	0:9b334a45a8ff	821	}while(Size > 0);
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	/* Wait until STOP flag is set */
bogdanm	0:9b334a45a8ff	824	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	825	{
bogdanm	0:9b334a45a8ff	826	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	827	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	828
bogdanm	0:9b334a45a8ff	829	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	830	{
bogdanm	0:9b334a45a8ff	831	/* Normal use case for Transmitter mode */
bogdanm	0:9b334a45a8ff	832	/* A NACK is generated to confirm the end of transfer */
bogdanm	0:9b334a45a8ff	833	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	834	}
bogdanm	0:9b334a45a8ff	835	else
bogdanm	0:9b334a45a8ff	836	{
bogdanm	0:9b334a45a8ff	837	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	838	}
bogdanm	0:9b334a45a8ff	839	}
bogdanm	0:9b334a45a8ff	840
bogdanm	0:9b334a45a8ff	841	/* Clear STOP flag */
bogdanm	0:9b334a45a8ff	842	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/* Wait until BUSY flag is reset */
bogdanm	0:9b334a45a8ff	845	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	846	{
bogdanm	0:9b334a45a8ff	847	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	848	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	849	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	850	}
bogdanm	0:9b334a45a8ff	851
bogdanm	0:9b334a45a8ff	852	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	853	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	854
bogdanm	0:9b334a45a8ff	855	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	858	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	return HAL_OK;
bogdanm	0:9b334a45a8ff	861	}
bogdanm	0:9b334a45a8ff	862	else
bogdanm	0:9b334a45a8ff	863	{
bogdanm	0:9b334a45a8ff	864	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	865	}
bogdanm	0:9b334a45a8ff	866	}
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	/**
bogdanm	0:9b334a45a8ff	869	* @brief Receive in slave mode an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	870	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	871	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	872	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	873	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	874	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	875	* @retval HAL status
bogdanm	0:9b334a45a8ff	876	*/
bogdanm	0:9b334a45a8ff	877	HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	878	{
bogdanm	0:9b334a45a8ff	879	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	880	{
bogdanm	0:9b334a45a8ff	881	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	882	{
bogdanm	0:9b334a45a8ff	883	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	884	}
bogdanm	0:9b334a45a8ff	885
bogdanm	0:9b334a45a8ff	886	/* Process Locked */
bogdanm	0:9b334a45a8ff	887	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	888
bogdanm	0:9b334a45a8ff	889	hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
bogdanm	0:9b334a45a8ff	890	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892	/* Enable Address Acknowledge */
bogdanm	0:9b334a45a8ff	893	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	894
bogdanm	0:9b334a45a8ff	895	/* Wait until ADDR flag is set */
bogdanm	0:9b334a45a8ff	896	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	897	{
bogdanm	0:9b334a45a8ff	898	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	899	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	900	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	901	}
bogdanm	0:9b334a45a8ff	902
bogdanm	0:9b334a45a8ff	903	/* Clear ADDR flag */
bogdanm	0:9b334a45a8ff	904	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
bogdanm	0:9b334a45a8ff	905
bogdanm	0:9b334a45a8ff	906	/* Wait until DIR flag is reset Receiver mode */
bogdanm	0:9b334a45a8ff	907	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	908	{
bogdanm	0:9b334a45a8ff	909	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	910	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	911	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	912	}
bogdanm	0:9b334a45a8ff	913
bogdanm	0:9b334a45a8ff	914	while(Size > 0)
bogdanm	0:9b334a45a8ff	915	{
bogdanm	0:9b334a45a8ff	916	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	917	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	918	{
bogdanm	0:9b334a45a8ff	919	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	920	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
mbed_official	113:b3775bf36a83	921
mbed_official	113:b3775bf36a83	922	/* Store Last receive data if any */
mbed_official	113:b3775bf36a83	923	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
mbed_official	113:b3775bf36a83	924	{
mbed_official	113:b3775bf36a83	925	/* Read data from RXDR */
mbed_official	113:b3775bf36a83	926	(*pData++) = hi2c->Instance->RXDR;
mbed_official	113:b3775bf36a83	927	}
mbed_official	113:b3775bf36a83	928
bogdanm	0:9b334a45a8ff	929	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
bogdanm	0:9b334a45a8ff	930	{
bogdanm	0:9b334a45a8ff	931	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	932	}
bogdanm	0:9b334a45a8ff	933	else
bogdanm	0:9b334a45a8ff	934	{
bogdanm	0:9b334a45a8ff	935	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	936	}
bogdanm	0:9b334a45a8ff	937	}
bogdanm	0:9b334a45a8ff	938
bogdanm	0:9b334a45a8ff	939	/* Read data from RXDR */
bogdanm	0:9b334a45a8ff	940	(*pData++) = hi2c->Instance->RXDR;
bogdanm	0:9b334a45a8ff	941	Size--;
bogdanm	0:9b334a45a8ff	942	}
bogdanm	0:9b334a45a8ff	943
bogdanm	0:9b334a45a8ff	944	/* Wait until STOP flag is set */
bogdanm	0:9b334a45a8ff	945	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	946	{
bogdanm	0:9b334a45a8ff	947	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	948	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	951	{
bogdanm	0:9b334a45a8ff	952	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	953	}
bogdanm	0:9b334a45a8ff	954	else
bogdanm	0:9b334a45a8ff	955	{
bogdanm	0:9b334a45a8ff	956	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	957	}
bogdanm	0:9b334a45a8ff	958	}
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960	/* Clear STOP flag */
bogdanm	0:9b334a45a8ff	961	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	/* Wait until BUSY flag is reset */
bogdanm	0:9b334a45a8ff	964	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	965	{
bogdanm	0:9b334a45a8ff	966	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	967	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	968	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	969	}
bogdanm	0:9b334a45a8ff	970
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	973	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	974
bogdanm	0:9b334a45a8ff	975	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	976
bogdanm	0:9b334a45a8ff	977	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	978	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	979
bogdanm	0:9b334a45a8ff	980	return HAL_OK;
bogdanm	0:9b334a45a8ff	981	}
bogdanm	0:9b334a45a8ff	982	else
bogdanm	0:9b334a45a8ff	983	{
bogdanm	0:9b334a45a8ff	984	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	985	}
bogdanm	0:9b334a45a8ff	986	}
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988	/**
bogdanm	0:9b334a45a8ff	989	* @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	990	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	991	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	992	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	993	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	994	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	995	* @retval HAL status
bogdanm	0:9b334a45a8ff	996	*/
bogdanm	0:9b334a45a8ff	997	HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	998	{
bogdanm	0:9b334a45a8ff	999	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	1000	{
bogdanm	0:9b334a45a8ff	1001	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1002	{
bogdanm	0:9b334a45a8ff	1003	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1004	}
bogdanm	0:9b334a45a8ff	1005
bogdanm	0:9b334a45a8ff	1006	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	1007	{
bogdanm	0:9b334a45a8ff	1008	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1009	}
bogdanm	0:9b334a45a8ff	1010
bogdanm	0:9b334a45a8ff	1011	/* Process Locked */
bogdanm	0:9b334a45a8ff	1012	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
bogdanm	0:9b334a45a8ff	1015	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1016
bogdanm	0:9b334a45a8ff	1017	hi2c->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1018	hi2c->XferCount = Size;
bogdanm	0:9b334a45a8ff	1019	if(Size > 255)
bogdanm	0:9b334a45a8ff	1020	{
bogdanm	0:9b334a45a8ff	1021	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	1022	}
bogdanm	0:9b334a45a8ff	1023	else
bogdanm	0:9b334a45a8ff	1024	{
bogdanm	0:9b334a45a8ff	1025	hi2c->XferSize = Size;
bogdanm	0:9b334a45a8ff	1026	}
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	1029	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
bogdanm	0:9b334a45a8ff	1030	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	1031	{
bogdanm	0:9b334a45a8ff	1032	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
bogdanm	0:9b334a45a8ff	1033	}
bogdanm	0:9b334a45a8ff	1034	else
bogdanm	0:9b334a45a8ff	1035	{
bogdanm	0:9b334a45a8ff	1036	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
bogdanm	0:9b334a45a8ff	1037	}
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1040	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1041
bogdanm	0:9b334a45a8ff	1042	/* Note : The I2C interrupts must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1043	to avoid the risk of I2C interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1044	process unlock */
bogdanm	0:9b334a45a8ff	1045
bogdanm	0:9b334a45a8ff	1046
bogdanm	0:9b334a45a8ff	1047	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
bogdanm	0:9b334a45a8ff	1048	/* possible to enable all of these */
bogdanm	0:9b334a45a8ff	1049	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
bogdanm	0:9b334a45a8ff	1050	__HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_TXI );
bogdanm	0:9b334a45a8ff	1051
bogdanm	0:9b334a45a8ff	1052	return HAL_OK;
bogdanm	0:9b334a45a8ff	1053	}
bogdanm	0:9b334a45a8ff	1054	else
bogdanm	0:9b334a45a8ff	1055	{
bogdanm	0:9b334a45a8ff	1056	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1057	}
bogdanm	0:9b334a45a8ff	1058	}
bogdanm	0:9b334a45a8ff	1059
bogdanm	0:9b334a45a8ff	1060	/**
bogdanm	0:9b334a45a8ff	1061	* @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1062	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1063	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	1064	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	1065	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	1066	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	1067	* @retval HAL status
bogdanm	0:9b334a45a8ff	1068	*/
bogdanm	0:9b334a45a8ff	1069	HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1070	{
bogdanm	0:9b334a45a8ff	1071	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	1072	{
bogdanm	0:9b334a45a8ff	1073	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1074	{
bogdanm	0:9b334a45a8ff	1075	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1076	}
bogdanm	0:9b334a45a8ff	1077
bogdanm	0:9b334a45a8ff	1078	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	1079	{
bogdanm	0:9b334a45a8ff	1080	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1081	}
bogdanm	0:9b334a45a8ff	1082
bogdanm	0:9b334a45a8ff	1083	/* Process Locked */
bogdanm	0:9b334a45a8ff	1084	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	1085
bogdanm	0:9b334a45a8ff	1086	hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
bogdanm	0:9b334a45a8ff	1087	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1088
bogdanm	0:9b334a45a8ff	1089	hi2c->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1090	hi2c->XferCount = Size;
bogdanm	0:9b334a45a8ff	1091	if(Size > 255)
bogdanm	0:9b334a45a8ff	1092	{
bogdanm	0:9b334a45a8ff	1093	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	1094	}
bogdanm	0:9b334a45a8ff	1095	else
bogdanm	0:9b334a45a8ff	1096	{
bogdanm	0:9b334a45a8ff	1097	hi2c->XferSize = Size;
bogdanm	0:9b334a45a8ff	1098	}
bogdanm	0:9b334a45a8ff	1099
bogdanm	0:9b334a45a8ff	1100	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	1101	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
bogdanm	0:9b334a45a8ff	1102	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	1103	{
bogdanm	0:9b334a45a8ff	1104	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	1105	}
bogdanm	0:9b334a45a8ff	1106	else
bogdanm	0:9b334a45a8ff	1107	{
bogdanm	0:9b334a45a8ff	1108	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	1109	}
bogdanm	0:9b334a45a8ff	1110
bogdanm	0:9b334a45a8ff	1111	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1112	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1113
bogdanm	0:9b334a45a8ff	1114	/* Note : The I2C interrupts must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1115	to avoid the risk of I2C interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1116	process unlock */
bogdanm	0:9b334a45a8ff	1117
bogdanm	0:9b334a45a8ff	1118	/* Enable ERR, TC, STOP, NACK, RXI interrupt */
bogdanm	0:9b334a45a8ff	1119	/* possible to enable all of these */
bogdanm	0:9b334a45a8ff	1120	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
bogdanm	0:9b334a45a8ff	1121	__HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_RXI );
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	return HAL_OK;
bogdanm	0:9b334a45a8ff	1124	}
bogdanm	0:9b334a45a8ff	1125	else
bogdanm	0:9b334a45a8ff	1126	{
bogdanm	0:9b334a45a8ff	1127	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1128	}
bogdanm	0:9b334a45a8ff	1129	}
bogdanm	0:9b334a45a8ff	1130
bogdanm	0:9b334a45a8ff	1131	/**
bogdanm	0:9b334a45a8ff	1132	* @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1133	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1134	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	1135	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	1136	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	1137	* @retval HAL status
bogdanm	0:9b334a45a8ff	1138	*/
bogdanm	0:9b334a45a8ff	1139	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1140	{
bogdanm	0:9b334a45a8ff	1141	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	1142	{
bogdanm	0:9b334a45a8ff	1143	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1144	{
bogdanm	0:9b334a45a8ff	1145	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1146	}
bogdanm	0:9b334a45a8ff	1147
bogdanm	0:9b334a45a8ff	1148	/* Process Locked */
bogdanm	0:9b334a45a8ff	1149	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;
bogdanm	0:9b334a45a8ff	1152	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	/* Enable Address Acknowledge */
bogdanm	0:9b334a45a8ff	1155	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	hi2c->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1158	hi2c->XferSize = Size;
bogdanm	0:9b334a45a8ff	1159	hi2c->XferCount = Size;
bogdanm	0:9b334a45a8ff	1160
bogdanm	0:9b334a45a8ff	1161	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1162	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1163
bogdanm	0:9b334a45a8ff	1164	/* Note : The I2C interrupts must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1165	to avoid the risk of I2C interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1166	process unlock */
bogdanm	0:9b334a45a8ff	1167
bogdanm	0:9b334a45a8ff	1168	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
bogdanm	0:9b334a45a8ff	1169	/* possible to enable all of these */
bogdanm	0:9b334a45a8ff	1170	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
bogdanm	0:9b334a45a8ff	1171	__HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_TXI );
bogdanm	0:9b334a45a8ff	1172
bogdanm	0:9b334a45a8ff	1173	return HAL_OK;
bogdanm	0:9b334a45a8ff	1174	}
bogdanm	0:9b334a45a8ff	1175	else
bogdanm	0:9b334a45a8ff	1176	{
bogdanm	0:9b334a45a8ff	1177	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1178	}
bogdanm	0:9b334a45a8ff	1179	}
bogdanm	0:9b334a45a8ff	1180
bogdanm	0:9b334a45a8ff	1181	/**
bogdanm	0:9b334a45a8ff	1182	* @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1183	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1184	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	1185	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	1186	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	1187	* @retval HAL status
bogdanm	0:9b334a45a8ff	1188	*/
bogdanm	0:9b334a45a8ff	1189	HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1190	{
bogdanm	0:9b334a45a8ff	1191	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	1192	{
bogdanm	0:9b334a45a8ff	1193	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1194	{
bogdanm	0:9b334a45a8ff	1195	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1196	}
bogdanm	0:9b334a45a8ff	1197
bogdanm	0:9b334a45a8ff	1198	/* Process Locked */
bogdanm	0:9b334a45a8ff	1199	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	1200
bogdanm	0:9b334a45a8ff	1201	hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1202	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1203
bogdanm	0:9b334a45a8ff	1204	/* Enable Address Acknowledge */
bogdanm	0:9b334a45a8ff	1205	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	hi2c->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1208	hi2c->XferSize = Size;
bogdanm	0:9b334a45a8ff	1209	hi2c->XferCount = Size;
bogdanm	0:9b334a45a8ff	1210
bogdanm	0:9b334a45a8ff	1211	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1212	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1213
bogdanm	0:9b334a45a8ff	1214	/* Note : The I2C interrupts must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1215	to avoid the risk of I2C interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1216	process unlock */
bogdanm	0:9b334a45a8ff	1217
bogdanm	0:9b334a45a8ff	1218	/* Enable ERR, TC, STOP, NACK, RXI interrupt */
bogdanm	0:9b334a45a8ff	1219	/* possible to enable all of these */
bogdanm	0:9b334a45a8ff	1220	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
bogdanm	0:9b334a45a8ff	1221	__HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI);
bogdanm	0:9b334a45a8ff	1222
bogdanm	0:9b334a45a8ff	1223	return HAL_OK;
bogdanm	0:9b334a45a8ff	1224	}
bogdanm	0:9b334a45a8ff	1225	else
bogdanm	0:9b334a45a8ff	1226	{
bogdanm	0:9b334a45a8ff	1227	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1228	}
bogdanm	0:9b334a45a8ff	1229	}
bogdanm	0:9b334a45a8ff	1230
bogdanm	0:9b334a45a8ff	1231	/**
bogdanm	0:9b334a45a8ff	1232	* @brief Transmit in master mode an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1233	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1234	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	1235	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	1236	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	1237	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	1238	* @retval HAL status
bogdanm	0:9b334a45a8ff	1239	*/
bogdanm	0:9b334a45a8ff	1240	HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1241	{
bogdanm	0:9b334a45a8ff	1242	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	1243	{
bogdanm	0:9b334a45a8ff	1244	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1245	{
bogdanm	0:9b334a45a8ff	1246	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1247	}
bogdanm	0:9b334a45a8ff	1248
bogdanm	0:9b334a45a8ff	1249	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	1250	{
bogdanm	0:9b334a45a8ff	1251	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1252	}
bogdanm	0:9b334a45a8ff	1253
bogdanm	0:9b334a45a8ff	1254	/* Process Locked */
bogdanm	0:9b334a45a8ff	1255	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	1256
bogdanm	0:9b334a45a8ff	1257	hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
bogdanm	0:9b334a45a8ff	1258	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1259
bogdanm	0:9b334a45a8ff	1260	hi2c->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1261	hi2c->XferCount = Size;
bogdanm	0:9b334a45a8ff	1262	if(Size > 255)
bogdanm	0:9b334a45a8ff	1263	{
bogdanm	0:9b334a45a8ff	1264	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	1265	}
bogdanm	0:9b334a45a8ff	1266	else
bogdanm	0:9b334a45a8ff	1267	{
bogdanm	0:9b334a45a8ff	1268	hi2c->XferSize = Size;
bogdanm	0:9b334a45a8ff	1269	}
bogdanm	0:9b334a45a8ff	1270
bogdanm	0:9b334a45a8ff	1271	/* Set the I2C DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1272	hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1275	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
bogdanm	0:9b334a45a8ff	1276
bogdanm	0:9b334a45a8ff	1277	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1278	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	1281	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
bogdanm	0:9b334a45a8ff	1282	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	1283	{
bogdanm	0:9b334a45a8ff	1284	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
bogdanm	0:9b334a45a8ff	1285	}
bogdanm	0:9b334a45a8ff	1286	else
bogdanm	0:9b334a45a8ff	1287	{
bogdanm	0:9b334a45a8ff	1288	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
bogdanm	0:9b334a45a8ff	1289	}
bogdanm	0:9b334a45a8ff	1290
bogdanm	0:9b334a45a8ff	1291	/* Wait until TXIS flag is set */
bogdanm	0:9b334a45a8ff	1292	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
bogdanm	0:9b334a45a8ff	1293	{
bogdanm	0:9b334a45a8ff	1294	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	1295	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	1296
mbed_official	113:b3775bf36a83	1297	/* Abort DMA */
mbed_official	113:b3775bf36a83	1298	HAL_DMA_Abort(hi2c->hdmatx);
mbed_official	113:b3775bf36a83	1299
bogdanm	0:9b334a45a8ff	1300	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	1301	{
bogdanm	0:9b334a45a8ff	1302	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1303	}
bogdanm	0:9b334a45a8ff	1304	else
bogdanm	0:9b334a45a8ff	1305	{
bogdanm	0:9b334a45a8ff	1306	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1307	}
bogdanm	0:9b334a45a8ff	1308	}
bogdanm	0:9b334a45a8ff	1309
bogdanm	0:9b334a45a8ff	1310
bogdanm	0:9b334a45a8ff	1311	/* Enable DMA Request */
bogdanm	0:9b334a45a8ff	1312	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
bogdanm	0:9b334a45a8ff	1313
bogdanm	0:9b334a45a8ff	1314	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1315	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1316
bogdanm	0:9b334a45a8ff	1317	return HAL_OK;
bogdanm	0:9b334a45a8ff	1318	}
bogdanm	0:9b334a45a8ff	1319	else
bogdanm	0:9b334a45a8ff	1320	{
bogdanm	0:9b334a45a8ff	1321	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1322	}
bogdanm	0:9b334a45a8ff	1323	}
bogdanm	0:9b334a45a8ff	1324
bogdanm	0:9b334a45a8ff	1325	/**
bogdanm	0:9b334a45a8ff	1326	* @brief Receive in master mode an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1327	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1328	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	1329	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	1330	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	1331	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	1332	* @retval HAL status
bogdanm	0:9b334a45a8ff	1333	*/
bogdanm	0:9b334a45a8ff	1334	HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1335	{
bogdanm	0:9b334a45a8ff	1336	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	1337	{
bogdanm	0:9b334a45a8ff	1338	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1339	{
bogdanm	0:9b334a45a8ff	1340	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1341	}
bogdanm	0:9b334a45a8ff	1342
bogdanm	0:9b334a45a8ff	1343	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	1344	{
bogdanm	0:9b334a45a8ff	1345	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1346	}
bogdanm	0:9b334a45a8ff	1347
bogdanm	0:9b334a45a8ff	1348	/* Process Locked */
bogdanm	0:9b334a45a8ff	1349	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	1350
bogdanm	0:9b334a45a8ff	1351	hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
bogdanm	0:9b334a45a8ff	1352	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1353
bogdanm	0:9b334a45a8ff	1354	hi2c->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1355	hi2c->XferCount = Size;
bogdanm	0:9b334a45a8ff	1356	if(Size > 255)
bogdanm	0:9b334a45a8ff	1357	{
bogdanm	0:9b334a45a8ff	1358	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	1359	}
bogdanm	0:9b334a45a8ff	1360	else
bogdanm	0:9b334a45a8ff	1361	{
bogdanm	0:9b334a45a8ff	1362	hi2c->XferSize = Size;
bogdanm	0:9b334a45a8ff	1363	}
bogdanm	0:9b334a45a8ff	1364
bogdanm	0:9b334a45a8ff	1365	/* Set the I2C DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1366	hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
bogdanm	0:9b334a45a8ff	1367
bogdanm	0:9b334a45a8ff	1368	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1369	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
bogdanm	0:9b334a45a8ff	1370
bogdanm	0:9b334a45a8ff	1371	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1372	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
bogdanm	0:9b334a45a8ff	1373
bogdanm	0:9b334a45a8ff	1374	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	1375	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
bogdanm	0:9b334a45a8ff	1376	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	1377	{
bogdanm	0:9b334a45a8ff	1378	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	1379	}
bogdanm	0:9b334a45a8ff	1380	else
bogdanm	0:9b334a45a8ff	1381	{
bogdanm	0:9b334a45a8ff	1382	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	1383	}
bogdanm	0:9b334a45a8ff	1384
bogdanm	0:9b334a45a8ff	1385	/* Wait until RXNE flag is set */
mbed_official	113:b3775bf36a83	1386	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK)
bogdanm	0:9b334a45a8ff	1387	{
mbed_official	113:b3775bf36a83	1388	/* Abort DMA */
mbed_official	113:b3775bf36a83	1389	HAL_DMA_Abort(hi2c->hdmarx);
mbed_official	113:b3775bf36a83	1390
mbed_official	113:b3775bf36a83	1391	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
mbed_official	113:b3775bf36a83	1392	{
mbed_official	113:b3775bf36a83	1393	return HAL_ERROR;
mbed_official	113:b3775bf36a83	1394	}
mbed_official	113:b3775bf36a83	1395	else
mbed_official	113:b3775bf36a83	1396	{
mbed_official	113:b3775bf36a83	1397	return HAL_TIMEOUT;
mbed_official	113:b3775bf36a83	1398	}
bogdanm	0:9b334a45a8ff	1399	}
bogdanm	0:9b334a45a8ff	1400
bogdanm	0:9b334a45a8ff	1401	/* Enable DMA Request */
bogdanm	0:9b334a45a8ff	1402	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
bogdanm	0:9b334a45a8ff	1403
bogdanm	0:9b334a45a8ff	1404	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1405	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1406
bogdanm	0:9b334a45a8ff	1407	return HAL_OK;
bogdanm	0:9b334a45a8ff	1408	}
bogdanm	0:9b334a45a8ff	1409	else
bogdanm	0:9b334a45a8ff	1410	{
bogdanm	0:9b334a45a8ff	1411	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1412	}
bogdanm	0:9b334a45a8ff	1413	}
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	/**
bogdanm	0:9b334a45a8ff	1416	* @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1417	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1418	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	1419	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	1420	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	1421	* @retval HAL status
bogdanm	0:9b334a45a8ff	1422	*/
bogdanm	0:9b334a45a8ff	1423	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1424	{
bogdanm	0:9b334a45a8ff	1425	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	1426	{
bogdanm	0:9b334a45a8ff	1427	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1428	{
bogdanm	0:9b334a45a8ff	1429	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1430	}
bogdanm	0:9b334a45a8ff	1431	/* Process Locked */
bogdanm	0:9b334a45a8ff	1432	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;
bogdanm	0:9b334a45a8ff	1435	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1436
bogdanm	0:9b334a45a8ff	1437	hi2c->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1438	hi2c->XferCount = Size;
bogdanm	0:9b334a45a8ff	1439	hi2c->XferSize = Size;
bogdanm	0:9b334a45a8ff	1440
bogdanm	0:9b334a45a8ff	1441	/* Set the I2C DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1442	hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
bogdanm	0:9b334a45a8ff	1443
bogdanm	0:9b334a45a8ff	1444	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1445	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
bogdanm	0:9b334a45a8ff	1446
bogdanm	0:9b334a45a8ff	1447	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1448	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
bogdanm	0:9b334a45a8ff	1449
bogdanm	0:9b334a45a8ff	1450	/* Enable Address Acknowledge */
bogdanm	0:9b334a45a8ff	1451	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	1452
bogdanm	0:9b334a45a8ff	1453	/* Wait until ADDR flag is set */
bogdanm	0:9b334a45a8ff	1454	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
bogdanm	0:9b334a45a8ff	1455	{
bogdanm	0:9b334a45a8ff	1456	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	1457	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	1458	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1459	}
bogdanm	0:9b334a45a8ff	1460
bogdanm	0:9b334a45a8ff	1461	/* Clear ADDR flag */
bogdanm	0:9b334a45a8ff	1462	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
bogdanm	0:9b334a45a8ff	1463
bogdanm	0:9b334a45a8ff	1464	/* If 10bits addressing mode is selected */
bogdanm	0:9b334a45a8ff	1465	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
bogdanm	0:9b334a45a8ff	1466	{
bogdanm	0:9b334a45a8ff	1467	/* Wait until ADDR flag is set */
bogdanm	0:9b334a45a8ff	1468	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
bogdanm	0:9b334a45a8ff	1469	{
bogdanm	0:9b334a45a8ff	1470	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	1471	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	1472	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1473	}
bogdanm	0:9b334a45a8ff	1474
bogdanm	0:9b334a45a8ff	1475	/* Clear ADDR flag */
bogdanm	0:9b334a45a8ff	1476	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
bogdanm	0:9b334a45a8ff	1477	}
bogdanm	0:9b334a45a8ff	1478
bogdanm	0:9b334a45a8ff	1479	/* Wait until DIR flag is set Transmitter mode */
bogdanm	0:9b334a45a8ff	1480	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, I2C_TIMEOUT_BUSY) != HAL_OK)
bogdanm	0:9b334a45a8ff	1481	{
bogdanm	0:9b334a45a8ff	1482	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	1483	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	1484	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1485	}
bogdanm	0:9b334a45a8ff	1486
bogdanm	0:9b334a45a8ff	1487	/* Enable DMA Request */
bogdanm	0:9b334a45a8ff	1488	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
bogdanm	0:9b334a45a8ff	1489
bogdanm	0:9b334a45a8ff	1490	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1491	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1492
bogdanm	0:9b334a45a8ff	1493	return HAL_OK;
bogdanm	0:9b334a45a8ff	1494	}
bogdanm	0:9b334a45a8ff	1495	else
bogdanm	0:9b334a45a8ff	1496	{
bogdanm	0:9b334a45a8ff	1497	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1498	}
bogdanm	0:9b334a45a8ff	1499	}
bogdanm	0:9b334a45a8ff	1500
bogdanm	0:9b334a45a8ff	1501	/**
bogdanm	0:9b334a45a8ff	1502	* @brief Receive in slave mode an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1503	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1504	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	1505	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	1506	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	1507	* @retval HAL status
bogdanm	0:9b334a45a8ff	1508	*/
bogdanm	0:9b334a45a8ff	1509	HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1510	{
bogdanm	0:9b334a45a8ff	1511	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	1512	{
bogdanm	0:9b334a45a8ff	1513	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1514	{
bogdanm	0:9b334a45a8ff	1515	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1516	}
bogdanm	0:9b334a45a8ff	1517	/* Process Locked */
bogdanm	0:9b334a45a8ff	1518	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	1519
bogdanm	0:9b334a45a8ff	1520	hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1521	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1522
bogdanm	0:9b334a45a8ff	1523	hi2c->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1524	hi2c->XferSize = Size;
bogdanm	0:9b334a45a8ff	1525	hi2c->XferCount = Size;
bogdanm	0:9b334a45a8ff	1526
bogdanm	0:9b334a45a8ff	1527	/* Set the I2C DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1528	hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
bogdanm	0:9b334a45a8ff	1529
bogdanm	0:9b334a45a8ff	1530	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1531	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
bogdanm	0:9b334a45a8ff	1532
bogdanm	0:9b334a45a8ff	1533	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1534	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, Size);
bogdanm	0:9b334a45a8ff	1535
bogdanm	0:9b334a45a8ff	1536	/* Enable Address Acknowledge */
bogdanm	0:9b334a45a8ff	1537	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	1538
bogdanm	0:9b334a45a8ff	1539	/* Wait until ADDR flag is set */
bogdanm	0:9b334a45a8ff	1540	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
bogdanm	0:9b334a45a8ff	1541	{
bogdanm	0:9b334a45a8ff	1542	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	1543	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	1544	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1545	}
bogdanm	0:9b334a45a8ff	1546
bogdanm	0:9b334a45a8ff	1547	/* Clear ADDR flag */
bogdanm	0:9b334a45a8ff	1548	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
bogdanm	0:9b334a45a8ff	1549
bogdanm	0:9b334a45a8ff	1550	/* Wait until DIR flag is set Receiver mode */
bogdanm	0:9b334a45a8ff	1551	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, I2C_TIMEOUT_DIR) != HAL_OK)
bogdanm	0:9b334a45a8ff	1552	{
bogdanm	0:9b334a45a8ff	1553	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	1554	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	1555	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1556	}
bogdanm	0:9b334a45a8ff	1557
bogdanm	0:9b334a45a8ff	1558	/* Enable DMA Request */
bogdanm	0:9b334a45a8ff	1559	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
bogdanm	0:9b334a45a8ff	1560
bogdanm	0:9b334a45a8ff	1561	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1562	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1563
bogdanm	0:9b334a45a8ff	1564	return HAL_OK;
bogdanm	0:9b334a45a8ff	1565	}
bogdanm	0:9b334a45a8ff	1566	else
bogdanm	0:9b334a45a8ff	1567	{
bogdanm	0:9b334a45a8ff	1568	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1569	}
bogdanm	0:9b334a45a8ff	1570	}
bogdanm	0:9b334a45a8ff	1571
bogdanm	0:9b334a45a8ff	1572	/**
bogdanm	0:9b334a45a8ff	1573	* @brief Write an amount of data in blocking mode to a specific memory address
bogdanm	0:9b334a45a8ff	1574	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1575	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	1576	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	1577	* @param MemAddress: Internal memory address
bogdanm	0:9b334a45a8ff	1578	* @param MemAddSize: Size of internal memory address
bogdanm	0:9b334a45a8ff	1579	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	1580	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	1581	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	1582	* @retval HAL status
bogdanm	0:9b334a45a8ff	1583	*/
bogdanm	0:9b334a45a8ff	1584	HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1585	{
bogdanm	0:9b334a45a8ff	1586	uint32_t Sizetmp = 0;
bogdanm	0:9b334a45a8ff	1587
bogdanm	0:9b334a45a8ff	1588	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1589	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
bogdanm	0:9b334a45a8ff	1590
bogdanm	0:9b334a45a8ff	1591	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	1592	{
bogdanm	0:9b334a45a8ff	1593	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1594	{
bogdanm	0:9b334a45a8ff	1595	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1596	}
bogdanm	0:9b334a45a8ff	1597
bogdanm	0:9b334a45a8ff	1598	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	1599	{
bogdanm	0:9b334a45a8ff	1600	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1601	}
bogdanm	0:9b334a45a8ff	1602
bogdanm	0:9b334a45a8ff	1603	/* Process Locked */
bogdanm	0:9b334a45a8ff	1604	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	1605
bogdanm	0:9b334a45a8ff	1606	hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
bogdanm	0:9b334a45a8ff	1607	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	/* Send Slave Address and Memory Address */
bogdanm	0:9b334a45a8ff	1610	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1611	{
bogdanm	0:9b334a45a8ff	1612	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	1613	{
bogdanm	0:9b334a45a8ff	1614	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1615	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1616	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1617	}
bogdanm	0:9b334a45a8ff	1618	else
bogdanm	0:9b334a45a8ff	1619	{
bogdanm	0:9b334a45a8ff	1620	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1621	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1622	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1623	}
bogdanm	0:9b334a45a8ff	1624	}
bogdanm	0:9b334a45a8ff	1625
bogdanm	0:9b334a45a8ff	1626	/* Set NBYTES to write and reload if size > 255 */
bogdanm	0:9b334a45a8ff	1627	/* Size > 255, need to set RELOAD bit */
bogdanm	0:9b334a45a8ff	1628	if(Size > 255)
bogdanm	0:9b334a45a8ff	1629	{
bogdanm	0:9b334a45a8ff	1630	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	1631	Sizetmp = 255;
bogdanm	0:9b334a45a8ff	1632	}
bogdanm	0:9b334a45a8ff	1633	else
bogdanm	0:9b334a45a8ff	1634	{
bogdanm	0:9b334a45a8ff	1635	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	1636	Sizetmp = Size;
bogdanm	0:9b334a45a8ff	1637	}
bogdanm	0:9b334a45a8ff	1638
bogdanm	0:9b334a45a8ff	1639	do
bogdanm	0:9b334a45a8ff	1640	{
bogdanm	0:9b334a45a8ff	1641	/* Wait until TXIS flag is set */
bogdanm	0:9b334a45a8ff	1642	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1643	{
bogdanm	0:9b334a45a8ff	1644	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	1645	{
bogdanm	0:9b334a45a8ff	1646	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1647	}
bogdanm	0:9b334a45a8ff	1648	else
bogdanm	0:9b334a45a8ff	1649	{
bogdanm	0:9b334a45a8ff	1650	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1651	}
bogdanm	0:9b334a45a8ff	1652	}
bogdanm	0:9b334a45a8ff	1653
bogdanm	0:9b334a45a8ff	1654	/* Write data to DR */
bogdanm	0:9b334a45a8ff	1655	hi2c->Instance->TXDR = (*pData++);
bogdanm	0:9b334a45a8ff	1656	Sizetmp--;
bogdanm	0:9b334a45a8ff	1657	Size--;
bogdanm	0:9b334a45a8ff	1658
bogdanm	0:9b334a45a8ff	1659	if((Sizetmp == 0)&&(Size!=0))
bogdanm	0:9b334a45a8ff	1660	{
bogdanm	0:9b334a45a8ff	1661	/* Wait until TCR flag is set */
bogdanm	0:9b334a45a8ff	1662	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1663	{
bogdanm	0:9b334a45a8ff	1664	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1665	}
bogdanm	0:9b334a45a8ff	1666
bogdanm	0:9b334a45a8ff	1667
bogdanm	0:9b334a45a8ff	1668	if(Size > 255)
bogdanm	0:9b334a45a8ff	1669	{
bogdanm	0:9b334a45a8ff	1670	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	1671	Sizetmp = 255;
bogdanm	0:9b334a45a8ff	1672	}
bogdanm	0:9b334a45a8ff	1673	else
bogdanm	0:9b334a45a8ff	1674	{
bogdanm	0:9b334a45a8ff	1675	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	1676	Sizetmp = Size;
bogdanm	0:9b334a45a8ff	1677	}
bogdanm	0:9b334a45a8ff	1678	}
bogdanm	0:9b334a45a8ff	1679
bogdanm	0:9b334a45a8ff	1680	}while(Size > 0);
bogdanm	0:9b334a45a8ff	1681
bogdanm	0:9b334a45a8ff	1682	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	1683	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	1684	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	1685	{
bogdanm	0:9b334a45a8ff	1686	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	1687	{
bogdanm	0:9b334a45a8ff	1688	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1689	}
bogdanm	0:9b334a45a8ff	1690	else
bogdanm	0:9b334a45a8ff	1691	{
bogdanm	0:9b334a45a8ff	1692	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1693	}
bogdanm	0:9b334a45a8ff	1694	}
bogdanm	0:9b334a45a8ff	1695
bogdanm	0:9b334a45a8ff	1696	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	1697	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	1698
bogdanm	0:9b334a45a8ff	1699	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	1700	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	1701
bogdanm	0:9b334a45a8ff	1702	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	1703
bogdanm	0:9b334a45a8ff	1704	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1705	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1706
bogdanm	0:9b334a45a8ff	1707	return HAL_OK;
bogdanm	0:9b334a45a8ff	1708	}
bogdanm	0:9b334a45a8ff	1709	else
bogdanm	0:9b334a45a8ff	1710	{
bogdanm	0:9b334a45a8ff	1711	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1712	}
bogdanm	0:9b334a45a8ff	1713	}
bogdanm	0:9b334a45a8ff	1714
bogdanm	0:9b334a45a8ff	1715	/**
bogdanm	0:9b334a45a8ff	1716	* @brief Read an amount of data in blocking mode from a specific memory address
bogdanm	0:9b334a45a8ff	1717	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1718	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	1719	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	1720	* @param MemAddress: Internal memory address
bogdanm	0:9b334a45a8ff	1721	* @param MemAddSize: Size of internal memory address
bogdanm	0:9b334a45a8ff	1722	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	1723	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	1724	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	1725	* @retval HAL status
bogdanm	0:9b334a45a8ff	1726	*/
bogdanm	0:9b334a45a8ff	1727	HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1728	{
bogdanm	0:9b334a45a8ff	1729	uint32_t Sizetmp = 0;
bogdanm	0:9b334a45a8ff	1730
bogdanm	0:9b334a45a8ff	1731	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1732	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
bogdanm	0:9b334a45a8ff	1733
bogdanm	0:9b334a45a8ff	1734	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	1735	{
bogdanm	0:9b334a45a8ff	1736	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1737	{
bogdanm	0:9b334a45a8ff	1738	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1739	}
bogdanm	0:9b334a45a8ff	1740
bogdanm	0:9b334a45a8ff	1741	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	1742	{
bogdanm	0:9b334a45a8ff	1743	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1744	}
bogdanm	0:9b334a45a8ff	1745
bogdanm	0:9b334a45a8ff	1746	/* Process Locked */
bogdanm	0:9b334a45a8ff	1747	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	1748
bogdanm	0:9b334a45a8ff	1749	hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
bogdanm	0:9b334a45a8ff	1750	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1751
bogdanm	0:9b334a45a8ff	1752	/* Send Slave Address and Memory Address */
bogdanm	0:9b334a45a8ff	1753	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1754	{
bogdanm	0:9b334a45a8ff	1755	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	1756	{
bogdanm	0:9b334a45a8ff	1757	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1758	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1759	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1760	}
bogdanm	0:9b334a45a8ff	1761	else
bogdanm	0:9b334a45a8ff	1762	{
bogdanm	0:9b334a45a8ff	1763	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1764	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1765	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1766	}
bogdanm	0:9b334a45a8ff	1767	}
bogdanm	0:9b334a45a8ff	1768
bogdanm	0:9b334a45a8ff	1769	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	1770	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
bogdanm	0:9b334a45a8ff	1771	/* Size > 255, need to set RELOAD bit */
bogdanm	0:9b334a45a8ff	1772	if(Size > 255)
bogdanm	0:9b334a45a8ff	1773	{
bogdanm	0:9b334a45a8ff	1774	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	1775	Sizetmp = 255;
bogdanm	0:9b334a45a8ff	1776	}
bogdanm	0:9b334a45a8ff	1777	else
bogdanm	0:9b334a45a8ff	1778	{
bogdanm	0:9b334a45a8ff	1779	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	1780	Sizetmp = Size;
bogdanm	0:9b334a45a8ff	1781	}
bogdanm	0:9b334a45a8ff	1782
bogdanm	0:9b334a45a8ff	1783	do
bogdanm	0:9b334a45a8ff	1784	{
bogdanm	0:9b334a45a8ff	1785	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	1786	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1787	{
bogdanm	0:9b334a45a8ff	1788	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1789	}
bogdanm	0:9b334a45a8ff	1790
bogdanm	0:9b334a45a8ff	1791	/* Read data from RXDR */
bogdanm	0:9b334a45a8ff	1792	(*pData++) = hi2c->Instance->RXDR;
bogdanm	0:9b334a45a8ff	1793
bogdanm	0:9b334a45a8ff	1794	/* Decrement the Size counter */
bogdanm	0:9b334a45a8ff	1795	Sizetmp--;
bogdanm	0:9b334a45a8ff	1796	Size--;
bogdanm	0:9b334a45a8ff	1797
bogdanm	0:9b334a45a8ff	1798	if((Sizetmp == 0)&&(Size!=0))
bogdanm	0:9b334a45a8ff	1799	{
bogdanm	0:9b334a45a8ff	1800	/* Wait until TCR flag is set */
bogdanm	0:9b334a45a8ff	1801	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	1802	{
bogdanm	0:9b334a45a8ff	1803	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1804	}
bogdanm	0:9b334a45a8ff	1805
bogdanm	0:9b334a45a8ff	1806	if(Size > 255)
bogdanm	0:9b334a45a8ff	1807	{
bogdanm	0:9b334a45a8ff	1808	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	1809	Sizetmp = 255;
bogdanm	0:9b334a45a8ff	1810	}
bogdanm	0:9b334a45a8ff	1811	else
bogdanm	0:9b334a45a8ff	1812	{
bogdanm	0:9b334a45a8ff	1813	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	1814	Sizetmp = Size;
bogdanm	0:9b334a45a8ff	1815	}
bogdanm	0:9b334a45a8ff	1816	}
bogdanm	0:9b334a45a8ff	1817
bogdanm	0:9b334a45a8ff	1818	}while(Size > 0);
bogdanm	0:9b334a45a8ff	1819
bogdanm	0:9b334a45a8ff	1820	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	1821	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	1822	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	1823	{
bogdanm	0:9b334a45a8ff	1824	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	1825	{
bogdanm	0:9b334a45a8ff	1826	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1827	}
bogdanm	0:9b334a45a8ff	1828	else
bogdanm	0:9b334a45a8ff	1829	{
bogdanm	0:9b334a45a8ff	1830	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1831	}
bogdanm	0:9b334a45a8ff	1832	}
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	1835	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	1836
bogdanm	0:9b334a45a8ff	1837	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	1838	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	1839
bogdanm	0:9b334a45a8ff	1840	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	1841
bogdanm	0:9b334a45a8ff	1842	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1843	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1844
bogdanm	0:9b334a45a8ff	1845	return HAL_OK;
bogdanm	0:9b334a45a8ff	1846	}
bogdanm	0:9b334a45a8ff	1847	else
bogdanm	0:9b334a45a8ff	1848	{
bogdanm	0:9b334a45a8ff	1849	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1850	}
bogdanm	0:9b334a45a8ff	1851	}
bogdanm	0:9b334a45a8ff	1852
bogdanm	0:9b334a45a8ff	1853	/**
bogdanm	0:9b334a45a8ff	1854	* @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
bogdanm	0:9b334a45a8ff	1855	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1856	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	1857	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	1858	* @param MemAddress: Internal memory address
bogdanm	0:9b334a45a8ff	1859	* @param MemAddSize: Size of internal memory address
bogdanm	0:9b334a45a8ff	1860	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	1861	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	1862	* @retval HAL status
bogdanm	0:9b334a45a8ff	1863	*/
bogdanm	0:9b334a45a8ff	1864	HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1865	{
bogdanm	0:9b334a45a8ff	1866	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1867	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
bogdanm	0:9b334a45a8ff	1868
bogdanm	0:9b334a45a8ff	1869	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	1870	{
bogdanm	0:9b334a45a8ff	1871	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1872	{
bogdanm	0:9b334a45a8ff	1873	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1874	}
bogdanm	0:9b334a45a8ff	1875
bogdanm	0:9b334a45a8ff	1876	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	1877	{
bogdanm	0:9b334a45a8ff	1878	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1879	}
bogdanm	0:9b334a45a8ff	1880
bogdanm	0:9b334a45a8ff	1881	/* Process Locked */
bogdanm	0:9b334a45a8ff	1882	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	1883
bogdanm	0:9b334a45a8ff	1884	hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
bogdanm	0:9b334a45a8ff	1885	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1886
bogdanm	0:9b334a45a8ff	1887	hi2c->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1888	hi2c->XferCount = Size;
bogdanm	0:9b334a45a8ff	1889	if(Size > 255)
bogdanm	0:9b334a45a8ff	1890	{
bogdanm	0:9b334a45a8ff	1891	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	1892	}
bogdanm	0:9b334a45a8ff	1893	else
bogdanm	0:9b334a45a8ff	1894	{
bogdanm	0:9b334a45a8ff	1895	hi2c->XferSize = Size;
bogdanm	0:9b334a45a8ff	1896	}
bogdanm	0:9b334a45a8ff	1897
bogdanm	0:9b334a45a8ff	1898	/* Send Slave Address and Memory Address */
bogdanm	0:9b334a45a8ff	1899	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
bogdanm	0:9b334a45a8ff	1900	{
bogdanm	0:9b334a45a8ff	1901	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	1902	{
bogdanm	0:9b334a45a8ff	1903	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1904	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1905	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1906	}
bogdanm	0:9b334a45a8ff	1907	else
bogdanm	0:9b334a45a8ff	1908	{
bogdanm	0:9b334a45a8ff	1909	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1910	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1911	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1912	}
bogdanm	0:9b334a45a8ff	1913	}
bogdanm	0:9b334a45a8ff	1914
bogdanm	0:9b334a45a8ff	1915	/* Set NBYTES to write and reload if size > 255 */
bogdanm	0:9b334a45a8ff	1916	/* Size > 255, need to set RELOAD bit */
bogdanm	0:9b334a45a8ff	1917	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	1918	{
bogdanm	0:9b334a45a8ff	1919	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	1920	}
bogdanm	0:9b334a45a8ff	1921	else
bogdanm	0:9b334a45a8ff	1922	{
bogdanm	0:9b334a45a8ff	1923	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	1924	}
bogdanm	0:9b334a45a8ff	1925
bogdanm	0:9b334a45a8ff	1926	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1927	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1928
bogdanm	0:9b334a45a8ff	1929	/* Note : The I2C interrupts must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1930	to avoid the risk of I2C interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1931	process unlock */
bogdanm	0:9b334a45a8ff	1932
bogdanm	0:9b334a45a8ff	1933	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
bogdanm	0:9b334a45a8ff	1934	/* possible to enable all of these */
bogdanm	0:9b334a45a8ff	1935	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
bogdanm	0:9b334a45a8ff	1936	__HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_TXI );
bogdanm	0:9b334a45a8ff	1937
bogdanm	0:9b334a45a8ff	1938	return HAL_OK;
bogdanm	0:9b334a45a8ff	1939	}
bogdanm	0:9b334a45a8ff	1940	else
bogdanm	0:9b334a45a8ff	1941	{
bogdanm	0:9b334a45a8ff	1942	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1943	}
bogdanm	0:9b334a45a8ff	1944	}
bogdanm	0:9b334a45a8ff	1945
bogdanm	0:9b334a45a8ff	1946	/**
bogdanm	0:9b334a45a8ff	1947	* @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
bogdanm	0:9b334a45a8ff	1948	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1949	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	1950	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	1951	* @param MemAddress: Internal memory address
bogdanm	0:9b334a45a8ff	1952	* @param MemAddSize: Size of internal memory address
bogdanm	0:9b334a45a8ff	1953	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	1954	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	1955	* @retval HAL status
bogdanm	0:9b334a45a8ff	1956	*/
bogdanm	0:9b334a45a8ff	1957	HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1958	{
bogdanm	0:9b334a45a8ff	1959	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1960	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
bogdanm	0:9b334a45a8ff	1961
bogdanm	0:9b334a45a8ff	1962	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	1963	{
bogdanm	0:9b334a45a8ff	1964	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1965	{
bogdanm	0:9b334a45a8ff	1966	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1967	}
bogdanm	0:9b334a45a8ff	1968
bogdanm	0:9b334a45a8ff	1969	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	1970	{
bogdanm	0:9b334a45a8ff	1971	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1972	}
bogdanm	0:9b334a45a8ff	1973
bogdanm	0:9b334a45a8ff	1974	/* Process Locked */
bogdanm	0:9b334a45a8ff	1975	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	1976
bogdanm	0:9b334a45a8ff	1977	hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
bogdanm	0:9b334a45a8ff	1978
bogdanm	0:9b334a45a8ff	1979	hi2c->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1980	hi2c->XferCount = Size;
bogdanm	0:9b334a45a8ff	1981	if(Size > 255)
bogdanm	0:9b334a45a8ff	1982	{
bogdanm	0:9b334a45a8ff	1983	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	1984	}
bogdanm	0:9b334a45a8ff	1985	else
bogdanm	0:9b334a45a8ff	1986	{
bogdanm	0:9b334a45a8ff	1987	hi2c->XferSize = Size;
bogdanm	0:9b334a45a8ff	1988	}
bogdanm	0:9b334a45a8ff	1989
bogdanm	0:9b334a45a8ff	1990	/* Send Slave Address and Memory Address */
bogdanm	0:9b334a45a8ff	1991	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
bogdanm	0:9b334a45a8ff	1992	{
bogdanm	0:9b334a45a8ff	1993	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	1994	{
bogdanm	0:9b334a45a8ff	1995	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1996	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	1997	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1998	}
bogdanm	0:9b334a45a8ff	1999	else
bogdanm	0:9b334a45a8ff	2000	{
bogdanm	0:9b334a45a8ff	2001	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2002	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2003	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2004	}
bogdanm	0:9b334a45a8ff	2005	}
bogdanm	0:9b334a45a8ff	2006
bogdanm	0:9b334a45a8ff	2007	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
bogdanm	0:9b334a45a8ff	2008	/* Size > 255, need to set RELOAD bit */
bogdanm	0:9b334a45a8ff	2009	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	2010	{
bogdanm	0:9b334a45a8ff	2011	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	2012	}
bogdanm	0:9b334a45a8ff	2013	else
bogdanm	0:9b334a45a8ff	2014	{
bogdanm	0:9b334a45a8ff	2015	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	2016	}
bogdanm	0:9b334a45a8ff	2017
bogdanm	0:9b334a45a8ff	2018	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2019	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2020
bogdanm	0:9b334a45a8ff	2021	/* Note : The I2C interrupts must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	2022	to avoid the risk of I2C interrupt handle execution before current
bogdanm	0:9b334a45a8ff	2023	process unlock */
bogdanm	0:9b334a45a8ff	2024
bogdanm	0:9b334a45a8ff	2025	/* Enable ERR, TC, STOP, NACK, RXI interrupt */
bogdanm	0:9b334a45a8ff	2026	/* possible to enable all of these */
bogdanm	0:9b334a45a8ff	2027	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
bogdanm	0:9b334a45a8ff	2028	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_RXI );
bogdanm	0:9b334a45a8ff	2029
bogdanm	0:9b334a45a8ff	2030	return HAL_OK;
bogdanm	0:9b334a45a8ff	2031	}
bogdanm	0:9b334a45a8ff	2032	else
bogdanm	0:9b334a45a8ff	2033	{
bogdanm	0:9b334a45a8ff	2034	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2035	}
bogdanm	0:9b334a45a8ff	2036	}
bogdanm	0:9b334a45a8ff	2037
bogdanm	0:9b334a45a8ff	2038	/**
bogdanm	0:9b334a45a8ff	2039	* @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
bogdanm	0:9b334a45a8ff	2040	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2041	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2042	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	2043	* @param MemAddress: Internal memory address
bogdanm	0:9b334a45a8ff	2044	* @param MemAddSize: Size of internal memory address
bogdanm	0:9b334a45a8ff	2045	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	2046	* @param Size: Amount of data to be sent
bogdanm	0:9b334a45a8ff	2047	* @retval HAL status
bogdanm	0:9b334a45a8ff	2048	*/
bogdanm	0:9b334a45a8ff	2049	HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	2050	{
bogdanm	0:9b334a45a8ff	2051	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2052	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
bogdanm	0:9b334a45a8ff	2053
bogdanm	0:9b334a45a8ff	2054	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	2055	{
bogdanm	0:9b334a45a8ff	2056	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	2057	{
bogdanm	0:9b334a45a8ff	2058	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2059	}
bogdanm	0:9b334a45a8ff	2060
bogdanm	0:9b334a45a8ff	2061	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	2062	{
bogdanm	0:9b334a45a8ff	2063	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2064	}
bogdanm	0:9b334a45a8ff	2065
bogdanm	0:9b334a45a8ff	2066	/* Process Locked */
bogdanm	0:9b334a45a8ff	2067	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	2068
bogdanm	0:9b334a45a8ff	2069	hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
bogdanm	0:9b334a45a8ff	2070	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	2071
bogdanm	0:9b334a45a8ff	2072	hi2c->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	2073	hi2c->XferCount = Size;
bogdanm	0:9b334a45a8ff	2074	if(Size > 255)
bogdanm	0:9b334a45a8ff	2075	{
bogdanm	0:9b334a45a8ff	2076	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	2077	}
bogdanm	0:9b334a45a8ff	2078	else
bogdanm	0:9b334a45a8ff	2079	{
bogdanm	0:9b334a45a8ff	2080	hi2c->XferSize = Size;
bogdanm	0:9b334a45a8ff	2081	}
bogdanm	0:9b334a45a8ff	2082
bogdanm	0:9b334a45a8ff	2083	/* Set the I2C DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	2084	hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
bogdanm	0:9b334a45a8ff	2085
bogdanm	0:9b334a45a8ff	2086	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2087	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
bogdanm	0:9b334a45a8ff	2088
bogdanm	0:9b334a45a8ff	2089	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2090	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
bogdanm	0:9b334a45a8ff	2091
bogdanm	0:9b334a45a8ff	2092	/* Send Slave Address and Memory Address */
bogdanm	0:9b334a45a8ff	2093	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
bogdanm	0:9b334a45a8ff	2094	{
bogdanm	0:9b334a45a8ff	2095	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	2096	{
bogdanm	0:9b334a45a8ff	2097	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2098	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2099	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2100	}
bogdanm	0:9b334a45a8ff	2101	else
bogdanm	0:9b334a45a8ff	2102	{
bogdanm	0:9b334a45a8ff	2103	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2104	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2105	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2106	}
bogdanm	0:9b334a45a8ff	2107	}
bogdanm	0:9b334a45a8ff	2108
bogdanm	0:9b334a45a8ff	2109	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	2110	/* Set NBYTES to write and reload if size > 255 */
bogdanm	0:9b334a45a8ff	2111	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	2112	{
bogdanm	0:9b334a45a8ff	2113	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	2114	}
bogdanm	0:9b334a45a8ff	2115	else
bogdanm	0:9b334a45a8ff	2116	{
bogdanm	0:9b334a45a8ff	2117	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	2118	}
bogdanm	0:9b334a45a8ff	2119
bogdanm	0:9b334a45a8ff	2120	/* Wait until TXIS flag is set */
bogdanm	0:9b334a45a8ff	2121	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
bogdanm	0:9b334a45a8ff	2122	{
bogdanm	0:9b334a45a8ff	2123	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	2124	{
bogdanm	0:9b334a45a8ff	2125	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2126	}
bogdanm	0:9b334a45a8ff	2127	else
bogdanm	0:9b334a45a8ff	2128	{
bogdanm	0:9b334a45a8ff	2129	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2130	}
bogdanm	0:9b334a45a8ff	2131	}
bogdanm	0:9b334a45a8ff	2132
bogdanm	0:9b334a45a8ff	2133	/* Enable DMA Request */
bogdanm	0:9b334a45a8ff	2134	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
bogdanm	0:9b334a45a8ff	2135
bogdanm	0:9b334a45a8ff	2136	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2137	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2138
bogdanm	0:9b334a45a8ff	2139	return HAL_OK;
bogdanm	0:9b334a45a8ff	2140	}
bogdanm	0:9b334a45a8ff	2141	else
bogdanm	0:9b334a45a8ff	2142	{
bogdanm	0:9b334a45a8ff	2143	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2144	}
bogdanm	0:9b334a45a8ff	2145	}
bogdanm	0:9b334a45a8ff	2146
bogdanm	0:9b334a45a8ff	2147	/**
bogdanm	0:9b334a45a8ff	2148	* @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
bogdanm	0:9b334a45a8ff	2149	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2150	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2151	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	2152	* @param MemAddress: Internal memory address
bogdanm	0:9b334a45a8ff	2153	* @param MemAddSize: Size of internal memory address
bogdanm	0:9b334a45a8ff	2154	* @param pData: Pointer to data buffer
bogdanm	0:9b334a45a8ff	2155	* @param Size: Amount of data to be read
bogdanm	0:9b334a45a8ff	2156	* @retval HAL status
bogdanm	0:9b334a45a8ff	2157	*/
bogdanm	0:9b334a45a8ff	2158	HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	2159	{
bogdanm	0:9b334a45a8ff	2160	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2161	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
bogdanm	0:9b334a45a8ff	2162
bogdanm	0:9b334a45a8ff	2163	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	2164	{
bogdanm	0:9b334a45a8ff	2165	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	2166	{
bogdanm	0:9b334a45a8ff	2167	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2168	}
bogdanm	0:9b334a45a8ff	2169
bogdanm	0:9b334a45a8ff	2170	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	2171	{
bogdanm	0:9b334a45a8ff	2172	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2173	}
bogdanm	0:9b334a45a8ff	2174
bogdanm	0:9b334a45a8ff	2175	/* Process Locked */
bogdanm	0:9b334a45a8ff	2176	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	2177
bogdanm	0:9b334a45a8ff	2178	hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
bogdanm	0:9b334a45a8ff	2179
bogdanm	0:9b334a45a8ff	2180	hi2c->pBuffPtr = pData;
bogdanm	0:9b334a45a8ff	2181	hi2c->XferCount = Size;
bogdanm	0:9b334a45a8ff	2182	if(Size > 255)
bogdanm	0:9b334a45a8ff	2183	{
bogdanm	0:9b334a45a8ff	2184	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	2185	}
bogdanm	0:9b334a45a8ff	2186	else
bogdanm	0:9b334a45a8ff	2187	{
bogdanm	0:9b334a45a8ff	2188	hi2c->XferSize = Size;
bogdanm	0:9b334a45a8ff	2189	}
bogdanm	0:9b334a45a8ff	2190
bogdanm	0:9b334a45a8ff	2191	/* Set the I2C DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	2192	hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
bogdanm	0:9b334a45a8ff	2193
bogdanm	0:9b334a45a8ff	2194	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	2195	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
bogdanm	0:9b334a45a8ff	2196
bogdanm	0:9b334a45a8ff	2197	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	2198	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
bogdanm	0:9b334a45a8ff	2199
bogdanm	0:9b334a45a8ff	2200	/* Send Slave Address and Memory Address */
bogdanm	0:9b334a45a8ff	2201	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
bogdanm	0:9b334a45a8ff	2202	{
bogdanm	0:9b334a45a8ff	2203	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	2204	{
bogdanm	0:9b334a45a8ff	2205	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2206	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2207	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2208	}
bogdanm	0:9b334a45a8ff	2209	else
bogdanm	0:9b334a45a8ff	2210	{
bogdanm	0:9b334a45a8ff	2211	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2212	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2213	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2214	}
bogdanm	0:9b334a45a8ff	2215	}
bogdanm	0:9b334a45a8ff	2216
bogdanm	0:9b334a45a8ff	2217	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
bogdanm	0:9b334a45a8ff	2218	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	2219	{
bogdanm	0:9b334a45a8ff	2220	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	2221	}
bogdanm	0:9b334a45a8ff	2222	else
bogdanm	0:9b334a45a8ff	2223	{
bogdanm	0:9b334a45a8ff	2224	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
bogdanm	0:9b334a45a8ff	2225	}
bogdanm	0:9b334a45a8ff	2226
bogdanm	0:9b334a45a8ff	2227	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	2228	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
bogdanm	0:9b334a45a8ff	2229	{
bogdanm	0:9b334a45a8ff	2230	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2231	}
bogdanm	0:9b334a45a8ff	2232
bogdanm	0:9b334a45a8ff	2233	/* Enable DMA Request */
bogdanm	0:9b334a45a8ff	2234	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
bogdanm	0:9b334a45a8ff	2235
bogdanm	0:9b334a45a8ff	2236	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2237	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2238
bogdanm	0:9b334a45a8ff	2239	return HAL_OK;
bogdanm	0:9b334a45a8ff	2240	}
bogdanm	0:9b334a45a8ff	2241	else
bogdanm	0:9b334a45a8ff	2242	{
bogdanm	0:9b334a45a8ff	2243	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2244	}
bogdanm	0:9b334a45a8ff	2245	}
bogdanm	0:9b334a45a8ff	2246
bogdanm	0:9b334a45a8ff	2247	/**
bogdanm	0:9b334a45a8ff	2248	* @brief Checks if target device is ready for communication.
bogdanm	0:9b334a45a8ff	2249	* @note This function is used with Memory devices
bogdanm	0:9b334a45a8ff	2250	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2251	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2252	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	2253	* @param Trials: Number of trials
bogdanm	0:9b334a45a8ff	2254	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	2255	* @retval HAL status
bogdanm	0:9b334a45a8ff	2256	*/
bogdanm	0:9b334a45a8ff	2257	HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2258	{
bogdanm	0:9b334a45a8ff	2259	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	2260
bogdanm	0:9b334a45a8ff	2261	__IO uint32_t I2C_Trials = 0;
bogdanm	0:9b334a45a8ff	2262
bogdanm	0:9b334a45a8ff	2263	if(hi2c->State == HAL_I2C_STATE_READY)
bogdanm	0:9b334a45a8ff	2264	{
bogdanm	0:9b334a45a8ff	2265	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
bogdanm	0:9b334a45a8ff	2266	{
bogdanm	0:9b334a45a8ff	2267	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2268	}
bogdanm	0:9b334a45a8ff	2269
bogdanm	0:9b334a45a8ff	2270	/* Process Locked */
bogdanm	0:9b334a45a8ff	2271	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	2272
bogdanm	0:9b334a45a8ff	2273	hi2c->State = HAL_I2C_STATE_BUSY;
bogdanm	0:9b334a45a8ff	2274	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	2275
bogdanm	0:9b334a45a8ff	2276	do
bogdanm	0:9b334a45a8ff	2277	{
bogdanm	0:9b334a45a8ff	2278	/* Generate Start */
bogdanm	0:9b334a45a8ff	2279	hi2c->Instance->CR2 = __I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
bogdanm	0:9b334a45a8ff	2280
bogdanm	0:9b334a45a8ff	2281	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	2282	/* Wait until STOPF flag is set or a NACK flag is set*/
bogdanm	0:9b334a45a8ff	2283	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2284	while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
bogdanm	0:9b334a45a8ff	2285	{
bogdanm	0:9b334a45a8ff	2286	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2287	{
bogdanm	0:9b334a45a8ff	2288	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	2289	{
bogdanm	0:9b334a45a8ff	2290	/* Device is ready */
bogdanm	0:9b334a45a8ff	2291	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	2292	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2293	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2294	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2295	}
bogdanm	0:9b334a45a8ff	2296	}
bogdanm	0:9b334a45a8ff	2297	}
bogdanm	0:9b334a45a8ff	2298
bogdanm	0:9b334a45a8ff	2299	/* Check if the NACKF flag has not been set */
bogdanm	0:9b334a45a8ff	2300	if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
bogdanm	0:9b334a45a8ff	2301	{
bogdanm	0:9b334a45a8ff	2302	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	2303	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2304	{
bogdanm	0:9b334a45a8ff	2305	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2306	}
bogdanm	0:9b334a45a8ff	2307
bogdanm	0:9b334a45a8ff	2308	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	2309	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	2310
bogdanm	0:9b334a45a8ff	2311	/* Device is ready */
bogdanm	0:9b334a45a8ff	2312	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	2313
bogdanm	0:9b334a45a8ff	2314	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2315	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2316
bogdanm	0:9b334a45a8ff	2317	return HAL_OK;
bogdanm	0:9b334a45a8ff	2318	}
bogdanm	0:9b334a45a8ff	2319	else
bogdanm	0:9b334a45a8ff	2320	{
bogdanm	0:9b334a45a8ff	2321	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	2322	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2323	{
bogdanm	0:9b334a45a8ff	2324	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2325	}
bogdanm	0:9b334a45a8ff	2326
bogdanm	0:9b334a45a8ff	2327	/* Clear NACK Flag */
bogdanm	0:9b334a45a8ff	2328	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
bogdanm	0:9b334a45a8ff	2329
bogdanm	0:9b334a45a8ff	2330	/* Clear STOP Flag, auto generated with autoend*/
bogdanm	0:9b334a45a8ff	2331	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	2332	}
bogdanm	0:9b334a45a8ff	2333
bogdanm	0:9b334a45a8ff	2334	/* Check if the maximum allowed number of trials has been reached */
bogdanm	0:9b334a45a8ff	2335	if (I2C_Trials++ == Trials)
bogdanm	0:9b334a45a8ff	2336	{
bogdanm	0:9b334a45a8ff	2337	/* Generate Stop */
bogdanm	0:9b334a45a8ff	2338	hi2c->Instance->CR2 \|= I2C_CR2_STOP;
bogdanm	0:9b334a45a8ff	2339
bogdanm	0:9b334a45a8ff	2340	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	2341	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2342	{
bogdanm	0:9b334a45a8ff	2343	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2344	}
bogdanm	0:9b334a45a8ff	2345
bogdanm	0:9b334a45a8ff	2346	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	2347	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	2348	}
bogdanm	0:9b334a45a8ff	2349	}while(I2C_Trials < Trials);
bogdanm	0:9b334a45a8ff	2350
bogdanm	0:9b334a45a8ff	2351	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	2352
bogdanm	0:9b334a45a8ff	2353	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2354	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2355
bogdanm	0:9b334a45a8ff	2356	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2357	}
bogdanm	0:9b334a45a8ff	2358	else
bogdanm	0:9b334a45a8ff	2359	{
bogdanm	0:9b334a45a8ff	2360	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	2361	}
bogdanm	0:9b334a45a8ff	2362	}
bogdanm	0:9b334a45a8ff	2363	/**
bogdanm	0:9b334a45a8ff	2364	* @}
bogdanm	0:9b334a45a8ff	2365	*/
bogdanm	0:9b334a45a8ff	2366
mbed_official	113:b3775bf36a83	2367	/** @addtogroup IRQ_Handler_and_Callbacks
bogdanm	0:9b334a45a8ff	2368	* @{
bogdanm	0:9b334a45a8ff	2369	*/
bogdanm	0:9b334a45a8ff	2370
bogdanm	0:9b334a45a8ff	2371	/**
bogdanm	0:9b334a45a8ff	2372	* @brief This function handles I2C event interrupt request.
bogdanm	0:9b334a45a8ff	2373	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2374	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2375	* @retval None
bogdanm	0:9b334a45a8ff	2376	*/
bogdanm	0:9b334a45a8ff	2377	void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2378	{
bogdanm	0:9b334a45a8ff	2379	/* I2C in mode Transmitter ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2380	if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_TXI \| I2C_IT_ADDRI)) == SET))
bogdanm	0:9b334a45a8ff	2381	{
bogdanm	0:9b334a45a8ff	2382	/* Slave mode selected */
bogdanm	0:9b334a45a8ff	2383	if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX)
bogdanm	0:9b334a45a8ff	2384	{
bogdanm	0:9b334a45a8ff	2385	I2C_SlaveTransmit_ISR(hi2c);
bogdanm	0:9b334a45a8ff	2386	}
bogdanm	0:9b334a45a8ff	2387	}
bogdanm	0:9b334a45a8ff	2388
bogdanm	0:9b334a45a8ff	2389	if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_TXI)) == SET))
bogdanm	0:9b334a45a8ff	2390	{
bogdanm	0:9b334a45a8ff	2391	/* Master mode selected */
bogdanm	0:9b334a45a8ff	2392	if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) \|\| (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX))
bogdanm	0:9b334a45a8ff	2393	{
bogdanm	0:9b334a45a8ff	2394	I2C_MasterTransmit_ISR(hi2c);
bogdanm	0:9b334a45a8ff	2395	}
bogdanm	0:9b334a45a8ff	2396	}
bogdanm	0:9b334a45a8ff	2397
bogdanm	0:9b334a45a8ff	2398	/* I2C in mode Receiver ----------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2399	if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_RXI \| I2C_IT_ADDRI)) == SET))
bogdanm	0:9b334a45a8ff	2400	{
bogdanm	0:9b334a45a8ff	2401	/* Slave mode selected */
bogdanm	0:9b334a45a8ff	2402	if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)
bogdanm	0:9b334a45a8ff	2403	{
bogdanm	0:9b334a45a8ff	2404	I2C_SlaveReceive_ISR(hi2c);
bogdanm	0:9b334a45a8ff	2405	}
bogdanm	0:9b334a45a8ff	2406	}
bogdanm	0:9b334a45a8ff	2407	if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_RXI)) == SET))
bogdanm	0:9b334a45a8ff	2408	{
bogdanm	0:9b334a45a8ff	2409	/* Master mode selected */
bogdanm	0:9b334a45a8ff	2410	if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) \|\| (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))
bogdanm	0:9b334a45a8ff	2411	{
bogdanm	0:9b334a45a8ff	2412	I2C_MasterReceive_ISR(hi2c);
bogdanm	0:9b334a45a8ff	2413	}
bogdanm	0:9b334a45a8ff	2414	}
bogdanm	0:9b334a45a8ff	2415	}
bogdanm	0:9b334a45a8ff	2416
bogdanm	0:9b334a45a8ff	2417	/**
bogdanm	0:9b334a45a8ff	2418	* @brief This function handles I2C error interrupt request.
bogdanm	0:9b334a45a8ff	2419	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2420	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2421	* @retval None
bogdanm	0:9b334a45a8ff	2422	*/
bogdanm	0:9b334a45a8ff	2423	void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2424	{
bogdanm	0:9b334a45a8ff	2425	/* I2C Bus error interrupt occurred ------------------------------------*/
bogdanm	0:9b334a45a8ff	2426	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
bogdanm	0:9b334a45a8ff	2427	{
bogdanm	0:9b334a45a8ff	2428	hi2c->ErrorCode \|= HAL_I2C_ERROR_BERR;
bogdanm	0:9b334a45a8ff	2429
bogdanm	0:9b334a45a8ff	2430	/* Clear BERR flag */
bogdanm	0:9b334a45a8ff	2431	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
bogdanm	0:9b334a45a8ff	2432	}
bogdanm	0:9b334a45a8ff	2433
bogdanm	0:9b334a45a8ff	2434	/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
bogdanm	0:9b334a45a8ff	2435	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
bogdanm	0:9b334a45a8ff	2436	{
bogdanm	0:9b334a45a8ff	2437	hi2c->ErrorCode \|= HAL_I2C_ERROR_OVR;
bogdanm	0:9b334a45a8ff	2438
bogdanm	0:9b334a45a8ff	2439	/* Clear OVR flag */
bogdanm	0:9b334a45a8ff	2440	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
bogdanm	0:9b334a45a8ff	2441	}
bogdanm	0:9b334a45a8ff	2442
bogdanm	0:9b334a45a8ff	2443	/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
bogdanm	0:9b334a45a8ff	2444	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
bogdanm	0:9b334a45a8ff	2445	{
bogdanm	0:9b334a45a8ff	2446	hi2c->ErrorCode \|= HAL_I2C_ERROR_ARLO;
bogdanm	0:9b334a45a8ff	2447
bogdanm	0:9b334a45a8ff	2448	/* Clear ARLO flag */
bogdanm	0:9b334a45a8ff	2449	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
bogdanm	0:9b334a45a8ff	2450	}
bogdanm	0:9b334a45a8ff	2451
bogdanm	0:9b334a45a8ff	2452	/* Call the Error Callback in case of Error detected */
bogdanm	0:9b334a45a8ff	2453	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2454	{
bogdanm	0:9b334a45a8ff	2455	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	2456
bogdanm	0:9b334a45a8ff	2457	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	2458	}
bogdanm	0:9b334a45a8ff	2459	}
bogdanm	0:9b334a45a8ff	2460
bogdanm	0:9b334a45a8ff	2461	/**
bogdanm	0:9b334a45a8ff	2462	* @brief Master Tx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	2463	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2464	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2465	* @retval None
bogdanm	0:9b334a45a8ff	2466	*/
bogdanm	0:9b334a45a8ff	2467	__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2468	{
mbed_official	113:b3775bf36a83	2469	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	2470	UNUSED(hi2c);
mbed_official	113:b3775bf36a83	2471
bogdanm	0:9b334a45a8ff	2472	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2473	the HAL_I2C_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	2474	*/
bogdanm	0:9b334a45a8ff	2475	}
bogdanm	0:9b334a45a8ff	2476
bogdanm	0:9b334a45a8ff	2477	/**
bogdanm	0:9b334a45a8ff	2478	* @brief Master Rx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	2479	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2480	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2481	* @retval None
bogdanm	0:9b334a45a8ff	2482	*/
bogdanm	0:9b334a45a8ff	2483	__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2484	{
mbed_official	113:b3775bf36a83	2485	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	2486	UNUSED(hi2c);
mbed_official	113:b3775bf36a83	2487
bogdanm	0:9b334a45a8ff	2488	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2489	the HAL_I2C_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	2490	*/
bogdanm	0:9b334a45a8ff	2491	}
bogdanm	0:9b334a45a8ff	2492
bogdanm	0:9b334a45a8ff	2493	/** @brief Slave Tx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	2494	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2495	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2496	* @retval None
bogdanm	0:9b334a45a8ff	2497	*/
bogdanm	0:9b334a45a8ff	2498	__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2499	{
mbed_official	113:b3775bf36a83	2500	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	2501	UNUSED(hi2c);
mbed_official	113:b3775bf36a83	2502
bogdanm	0:9b334a45a8ff	2503	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2504	the HAL_I2C_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	2505	*/
bogdanm	0:9b334a45a8ff	2506	}
bogdanm	0:9b334a45a8ff	2507
bogdanm	0:9b334a45a8ff	2508	/**
bogdanm	0:9b334a45a8ff	2509	* @brief Slave Rx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	2510	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2511	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2512	* @retval None
bogdanm	0:9b334a45a8ff	2513	*/
bogdanm	0:9b334a45a8ff	2514	__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2515	{
mbed_official	113:b3775bf36a83	2516	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	2517	UNUSED(hi2c);
mbed_official	113:b3775bf36a83	2518
bogdanm	0:9b334a45a8ff	2519	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2520	the HAL_I2C_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	2521	*/
bogdanm	0:9b334a45a8ff	2522	}
bogdanm	0:9b334a45a8ff	2523
bogdanm	0:9b334a45a8ff	2524	/**
bogdanm	0:9b334a45a8ff	2525	* @brief Memory Tx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	2526	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2527	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2528	* @retval None
bogdanm	0:9b334a45a8ff	2529	*/
bogdanm	0:9b334a45a8ff	2530	__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2531	{
mbed_official	113:b3775bf36a83	2532	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	2533	UNUSED(hi2c);
mbed_official	113:b3775bf36a83	2534
bogdanm	0:9b334a45a8ff	2535	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2536	the HAL_I2C_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	2537	*/
bogdanm	0:9b334a45a8ff	2538	}
bogdanm	0:9b334a45a8ff	2539
bogdanm	0:9b334a45a8ff	2540	/**
bogdanm	0:9b334a45a8ff	2541	* @brief Memory Rx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	2542	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2543	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2544	* @retval None
bogdanm	0:9b334a45a8ff	2545	*/
bogdanm	0:9b334a45a8ff	2546	__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2547	{
mbed_official	113:b3775bf36a83	2548	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	2549	UNUSED(hi2c);
mbed_official	113:b3775bf36a83	2550
bogdanm	0:9b334a45a8ff	2551	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2552	the HAL_I2C_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	2553	*/
bogdanm	0:9b334a45a8ff	2554	}
bogdanm	0:9b334a45a8ff	2555
bogdanm	0:9b334a45a8ff	2556	/**
bogdanm	0:9b334a45a8ff	2557	* @brief I2C error callbacks.
bogdanm	0:9b334a45a8ff	2558	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2559	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2560	* @retval None
bogdanm	0:9b334a45a8ff	2561	*/
bogdanm	0:9b334a45a8ff	2562	__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2563	{
mbed_official	113:b3775bf36a83	2564	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	2565	UNUSED(hi2c);
mbed_official	113:b3775bf36a83	2566
bogdanm	0:9b334a45a8ff	2567	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	2568	the HAL_I2C_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	2569	*/
bogdanm	0:9b334a45a8ff	2570	}
bogdanm	0:9b334a45a8ff	2571
bogdanm	0:9b334a45a8ff	2572	/**
bogdanm	0:9b334a45a8ff	2573	* @}
bogdanm	0:9b334a45a8ff	2574	*/
bogdanm	0:9b334a45a8ff	2575
bogdanm	0:9b334a45a8ff	2576
mbed_official	113:b3775bf36a83	2577	/** @addtogroup I2C_Exported_Functions_Group3
bogdanm	0:9b334a45a8ff	2578	* @brief Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	2579	*
bogdanm	0:9b334a45a8ff	2580	@verbatim
bogdanm	0:9b334a45a8ff	2581	===============================================================================
bogdanm	0:9b334a45a8ff	2582	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	2583	===============================================================================
bogdanm	0:9b334a45a8ff	2584	[..]
bogdanm	0:9b334a45a8ff	2585	This subsection permit to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	2586	and the data flow.
bogdanm	0:9b334a45a8ff	2587
bogdanm	0:9b334a45a8ff	2588	@endverbatim
bogdanm	0:9b334a45a8ff	2589	* @{
bogdanm	0:9b334a45a8ff	2590	*/
bogdanm	0:9b334a45a8ff	2591
bogdanm	0:9b334a45a8ff	2592	/**
bogdanm	0:9b334a45a8ff	2593	* @brief Returns the I2C state.
bogdanm	0:9b334a45a8ff	2594	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2595	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2596	* @retval HAL state
bogdanm	0:9b334a45a8ff	2597	*/
bogdanm	0:9b334a45a8ff	2598	HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2599	{
bogdanm	0:9b334a45a8ff	2600	return hi2c->State;
bogdanm	0:9b334a45a8ff	2601	}
bogdanm	0:9b334a45a8ff	2602
bogdanm	0:9b334a45a8ff	2603	/**
bogdanm	0:9b334a45a8ff	2604	* @brief Return the I2C error code
bogdanm	0:9b334a45a8ff	2605	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2606	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2607	* @retval I2C Error Code
bogdanm	0:9b334a45a8ff	2608	*/
bogdanm	0:9b334a45a8ff	2609	uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2610	{
bogdanm	0:9b334a45a8ff	2611	return hi2c->ErrorCode;
bogdanm	0:9b334a45a8ff	2612	}
bogdanm	0:9b334a45a8ff	2613
bogdanm	0:9b334a45a8ff	2614	/**
bogdanm	0:9b334a45a8ff	2615	* @}
bogdanm	0:9b334a45a8ff	2616	*/
bogdanm	0:9b334a45a8ff	2617
bogdanm	0:9b334a45a8ff	2618	/**
bogdanm	0:9b334a45a8ff	2619	* @}
bogdanm	0:9b334a45a8ff	2620	*/
bogdanm	0:9b334a45a8ff	2621
mbed_official	113:b3775bf36a83	2622	/** @addtogroup I2C_Private
bogdanm	0:9b334a45a8ff	2623	* @{
bogdanm	0:9b334a45a8ff	2624	*/
bogdanm	0:9b334a45a8ff	2625
bogdanm	0:9b334a45a8ff	2626	/**
bogdanm	0:9b334a45a8ff	2627	* @brief Handle Interrupt Flags Master Transmit Mode
bogdanm	0:9b334a45a8ff	2628	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2629	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2630	* @retval HAL status
bogdanm	0:9b334a45a8ff	2631	*/
bogdanm	0:9b334a45a8ff	2632	static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2633	{
bogdanm	0:9b334a45a8ff	2634	uint16_t DevAddress;
bogdanm	0:9b334a45a8ff	2635
bogdanm	0:9b334a45a8ff	2636	/* Process Locked */
bogdanm	0:9b334a45a8ff	2637	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	2638
bogdanm	0:9b334a45a8ff	2639	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
bogdanm	0:9b334a45a8ff	2640	{
bogdanm	0:9b334a45a8ff	2641	/* Write data to TXDR */
bogdanm	0:9b334a45a8ff	2642	hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
bogdanm	0:9b334a45a8ff	2643	hi2c->XferSize--;
bogdanm	0:9b334a45a8ff	2644	hi2c->XferCount--;
bogdanm	0:9b334a45a8ff	2645	}
bogdanm	0:9b334a45a8ff	2646	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
bogdanm	0:9b334a45a8ff	2647	{
bogdanm	0:9b334a45a8ff	2648	if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
bogdanm	0:9b334a45a8ff	2649	{
bogdanm	0:9b334a45a8ff	2650	DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
bogdanm	0:9b334a45a8ff	2651
bogdanm	0:9b334a45a8ff	2652	if(hi2c->XferCount > 255)
bogdanm	0:9b334a45a8ff	2653	{
bogdanm	0:9b334a45a8ff	2654	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	2655	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	2656	}
bogdanm	0:9b334a45a8ff	2657	else
bogdanm	0:9b334a45a8ff	2658	{
bogdanm	0:9b334a45a8ff	2659	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	2660	hi2c->XferSize = hi2c->XferCount;
bogdanm	0:9b334a45a8ff	2661	}
bogdanm	0:9b334a45a8ff	2662	}
bogdanm	0:9b334a45a8ff	2663	else
bogdanm	0:9b334a45a8ff	2664	{
bogdanm	0:9b334a45a8ff	2665	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2666	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2667
bogdanm	0:9b334a45a8ff	2668	/* Wrong size Status regarding TCR flag event */
bogdanm	0:9b334a45a8ff	2669	hi2c->ErrorCode \|= HAL_I2C_ERROR_SIZE;
bogdanm	0:9b334a45a8ff	2670	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	2671	}
bogdanm	0:9b334a45a8ff	2672	}
bogdanm	0:9b334a45a8ff	2673	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
bogdanm	0:9b334a45a8ff	2674	{
bogdanm	0:9b334a45a8ff	2675	if(hi2c->XferCount == 0)
bogdanm	0:9b334a45a8ff	2676	{
bogdanm	0:9b334a45a8ff	2677	/* Generate Stop */
bogdanm	0:9b334a45a8ff	2678	hi2c->Instance->CR2 \|= I2C_CR2_STOP;
bogdanm	0:9b334a45a8ff	2679	}
bogdanm	0:9b334a45a8ff	2680	else
bogdanm	0:9b334a45a8ff	2681	{
bogdanm	0:9b334a45a8ff	2682	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2683	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2684
bogdanm	0:9b334a45a8ff	2685	/* Wrong size Status regarding TCR flag event */
bogdanm	0:9b334a45a8ff	2686	hi2c->ErrorCode \|= HAL_I2C_ERROR_SIZE;
bogdanm	0:9b334a45a8ff	2687	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	2688	}
bogdanm	0:9b334a45a8ff	2689	}
bogdanm	0:9b334a45a8ff	2690	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
bogdanm	0:9b334a45a8ff	2691	{
mbed_official	113:b3775bf36a83	2692	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
mbed_official	113:b3775bf36a83	2693	{
mbed_official	113:b3775bf36a83	2694	/* Clear NACK Flag */
mbed_official	113:b3775bf36a83	2695	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
mbed_official	113:b3775bf36a83	2696
mbed_official	113:b3775bf36a83	2697	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
mbed_official	113:b3775bf36a83	2698	}
mbed_official	113:b3775bf36a83	2699	/* Disable ERR, TC, STOP, NACK, TXI interrupts */
bogdanm	0:9b334a45a8ff	2700	__HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_TXI );
bogdanm	0:9b334a45a8ff	2701
bogdanm	0:9b334a45a8ff	2702	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	2703	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	2704
bogdanm	0:9b334a45a8ff	2705	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	2706	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	2707
mbed_official	113:b3775bf36a83	2708	/* Flush TX register if not empty */
mbed_official	113:b3775bf36a83	2709	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
bogdanm	0:9b334a45a8ff	2710	{
mbed_official	113:b3775bf36a83	2711	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
mbed_official	113:b3775bf36a83	2712	}
mbed_official	113:b3775bf36a83	2713
mbed_official	113:b3775bf36a83	2714	/* Call the correct callback to inform upper layer */
mbed_official	113:b3775bf36a83	2715	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
mbed_official	113:b3775bf36a83	2716	{
mbed_official	113:b3775bf36a83	2717	hi2c->State = HAL_I2C_STATE_READY;
mbed_official	113:b3775bf36a83	2718
mbed_official	113:b3775bf36a83	2719	/* Process Unlocked */
mbed_official	113:b3775bf36a83	2720	__HAL_UNLOCK(hi2c);
mbed_official	113:b3775bf36a83	2721
mbed_official	113:b3775bf36a83	2722	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	2723	}
bogdanm	0:9b334a45a8ff	2724	else
bogdanm	0:9b334a45a8ff	2725	{
mbed_official	113:b3775bf36a83	2726	if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
mbed_official	113:b3775bf36a83	2727	{
mbed_official	113:b3775bf36a83	2728	hi2c->State = HAL_I2C_STATE_READY;
mbed_official	113:b3775bf36a83	2729
mbed_official	113:b3775bf36a83	2730	/* Process Unlocked */
mbed_official	113:b3775bf36a83	2731	__HAL_UNLOCK(hi2c);
mbed_official	113:b3775bf36a83	2732
mbed_official	113:b3775bf36a83	2733	HAL_I2C_MemTxCpltCallback(hi2c);
mbed_official	113:b3775bf36a83	2734	}
mbed_official	113:b3775bf36a83	2735	else
mbed_official	113:b3775bf36a83	2736	{
mbed_official	113:b3775bf36a83	2737	hi2c->State = HAL_I2C_STATE_READY;
mbed_official	113:b3775bf36a83	2738
mbed_official	113:b3775bf36a83	2739	/* Process Unlocked */
mbed_official	113:b3775bf36a83	2740	__HAL_UNLOCK(hi2c);
mbed_official	113:b3775bf36a83	2741
mbed_official	113:b3775bf36a83	2742	HAL_I2C_MasterTxCpltCallback(hi2c);
mbed_official	113:b3775bf36a83	2743	}
bogdanm	0:9b334a45a8ff	2744	}
bogdanm	0:9b334a45a8ff	2745	}
bogdanm	0:9b334a45a8ff	2746	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
bogdanm	0:9b334a45a8ff	2747	{
bogdanm	0:9b334a45a8ff	2748	/* Clear NACK Flag */
bogdanm	0:9b334a45a8ff	2749	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
bogdanm	0:9b334a45a8ff	2750
bogdanm	0:9b334a45a8ff	2751	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2752	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2753
bogdanm	0:9b334a45a8ff	2754	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	2755	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	2756	}
bogdanm	0:9b334a45a8ff	2757
bogdanm	0:9b334a45a8ff	2758	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2759	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2760
bogdanm	0:9b334a45a8ff	2761	return HAL_OK;
bogdanm	0:9b334a45a8ff	2762	}
bogdanm	0:9b334a45a8ff	2763
bogdanm	0:9b334a45a8ff	2764	/**
bogdanm	0:9b334a45a8ff	2765	* @brief Handle Interrupt Flags Master Receive Mode
bogdanm	0:9b334a45a8ff	2766	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2767	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2768	* @retval HAL status
bogdanm	0:9b334a45a8ff	2769	*/
bogdanm	0:9b334a45a8ff	2770	static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2771	{
bogdanm	0:9b334a45a8ff	2772	uint16_t DevAddress;
bogdanm	0:9b334a45a8ff	2773
bogdanm	0:9b334a45a8ff	2774	/* Process Locked */
bogdanm	0:9b334a45a8ff	2775	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	2776
bogdanm	0:9b334a45a8ff	2777	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
bogdanm	0:9b334a45a8ff	2778	{
bogdanm	0:9b334a45a8ff	2779	/* Read data from RXDR */
bogdanm	0:9b334a45a8ff	2780	(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
bogdanm	0:9b334a45a8ff	2781	hi2c->XferSize--;
bogdanm	0:9b334a45a8ff	2782	hi2c->XferCount--;
bogdanm	0:9b334a45a8ff	2783	}
bogdanm	0:9b334a45a8ff	2784	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
bogdanm	0:9b334a45a8ff	2785	{
bogdanm	0:9b334a45a8ff	2786	if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
bogdanm	0:9b334a45a8ff	2787	{
bogdanm	0:9b334a45a8ff	2788	DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
bogdanm	0:9b334a45a8ff	2789
bogdanm	0:9b334a45a8ff	2790	if(hi2c->XferCount > 255)
bogdanm	0:9b334a45a8ff	2791	{
bogdanm	0:9b334a45a8ff	2792	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	2793	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	2794	}
bogdanm	0:9b334a45a8ff	2795	else
bogdanm	0:9b334a45a8ff	2796	{
bogdanm	0:9b334a45a8ff	2797	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	2798	hi2c->XferSize = hi2c->XferCount;
bogdanm	0:9b334a45a8ff	2799	}
bogdanm	0:9b334a45a8ff	2800	}
bogdanm	0:9b334a45a8ff	2801	else
bogdanm	0:9b334a45a8ff	2802	{
bogdanm	0:9b334a45a8ff	2803	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2804	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2805
bogdanm	0:9b334a45a8ff	2806	/* Wrong size Status regarding TCR flag event */
bogdanm	0:9b334a45a8ff	2807	hi2c->ErrorCode \|= HAL_I2C_ERROR_SIZE;
bogdanm	0:9b334a45a8ff	2808	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	2809	}
bogdanm	0:9b334a45a8ff	2810	}
bogdanm	0:9b334a45a8ff	2811	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
bogdanm	0:9b334a45a8ff	2812	{
bogdanm	0:9b334a45a8ff	2813	if(hi2c->XferCount == 0)
bogdanm	0:9b334a45a8ff	2814	{
bogdanm	0:9b334a45a8ff	2815	/* Generate Stop */
bogdanm	0:9b334a45a8ff	2816	hi2c->Instance->CR2 \|= I2C_CR2_STOP;
bogdanm	0:9b334a45a8ff	2817	}
bogdanm	0:9b334a45a8ff	2818	else
bogdanm	0:9b334a45a8ff	2819	{
bogdanm	0:9b334a45a8ff	2820	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2821	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2822
bogdanm	0:9b334a45a8ff	2823	/* Wrong size Status regarding TCR flag event */
bogdanm	0:9b334a45a8ff	2824	hi2c->ErrorCode \|= HAL_I2C_ERROR_SIZE;
bogdanm	0:9b334a45a8ff	2825	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	2826	}
bogdanm	0:9b334a45a8ff	2827	}
bogdanm	0:9b334a45a8ff	2828	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
bogdanm	0:9b334a45a8ff	2829	{
mbed_official	113:b3775bf36a83	2830	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
mbed_official	113:b3775bf36a83	2831	{
mbed_official	113:b3775bf36a83	2832	/* Clear NACK Flag */
mbed_official	113:b3775bf36a83	2833	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
mbed_official	113:b3775bf36a83	2834
mbed_official	113:b3775bf36a83	2835	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
mbed_official	113:b3775bf36a83	2836	}
mbed_official	113:b3775bf36a83	2837	/* Disable ERR, TC, STOP, NACK, RXI interrupts */
bogdanm	0:9b334a45a8ff	2838	__HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_RXI );
bogdanm	0:9b334a45a8ff	2839
bogdanm	0:9b334a45a8ff	2840	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	2841	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	2842
bogdanm	0:9b334a45a8ff	2843	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	2844	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	2845
mbed_official	113:b3775bf36a83	2846	/* Call the correct callback to inform upper layer */
mbed_official	113:b3775bf36a83	2847	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
mbed_official	113:b3775bf36a83	2848	{
mbed_official	113:b3775bf36a83	2849	hi2c->State = HAL_I2C_STATE_READY;
mbed_official	113:b3775bf36a83	2850
mbed_official	113:b3775bf36a83	2851	/* Process Unlocked */
mbed_official	113:b3775bf36a83	2852	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2853
mbed_official	113:b3775bf36a83	2854	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	2855	}
bogdanm	0:9b334a45a8ff	2856	else
bogdanm	0:9b334a45a8ff	2857	{
mbed_official	113:b3775bf36a83	2858	if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
mbed_official	113:b3775bf36a83	2859	{
mbed_official	113:b3775bf36a83	2860	hi2c->State = HAL_I2C_STATE_READY;
mbed_official	113:b3775bf36a83	2861
mbed_official	113:b3775bf36a83	2862	/* Process Unlocked */
mbed_official	113:b3775bf36a83	2863	__HAL_UNLOCK(hi2c);
mbed_official	113:b3775bf36a83	2864
mbed_official	113:b3775bf36a83	2865	HAL_I2C_MemRxCpltCallback(hi2c);
mbed_official	113:b3775bf36a83	2866	}
mbed_official	113:b3775bf36a83	2867	else
mbed_official	113:b3775bf36a83	2868	{
mbed_official	113:b3775bf36a83	2869	hi2c->State = HAL_I2C_STATE_READY;
mbed_official	113:b3775bf36a83	2870
mbed_official	113:b3775bf36a83	2871	/* Process Unlocked */
mbed_official	113:b3775bf36a83	2872	__HAL_UNLOCK(hi2c);
mbed_official	113:b3775bf36a83	2873
mbed_official	113:b3775bf36a83	2874	HAL_I2C_MasterRxCpltCallback(hi2c);
mbed_official	113:b3775bf36a83	2875	}
bogdanm	0:9b334a45a8ff	2876	}
bogdanm	0:9b334a45a8ff	2877	}
bogdanm	0:9b334a45a8ff	2878	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
bogdanm	0:9b334a45a8ff	2879	{
bogdanm	0:9b334a45a8ff	2880	/* Clear NACK Flag */
bogdanm	0:9b334a45a8ff	2881	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
bogdanm	0:9b334a45a8ff	2882
bogdanm	0:9b334a45a8ff	2883	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2884	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2885
bogdanm	0:9b334a45a8ff	2886	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	2887	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	2888	}
bogdanm	0:9b334a45a8ff	2889
bogdanm	0:9b334a45a8ff	2890	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2891	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2892
bogdanm	0:9b334a45a8ff	2893	return HAL_OK;
bogdanm	0:9b334a45a8ff	2894
bogdanm	0:9b334a45a8ff	2895	}
bogdanm	0:9b334a45a8ff	2896
bogdanm	0:9b334a45a8ff	2897	/**
bogdanm	0:9b334a45a8ff	2898	* @brief Handle Interrupt Flags Slave Transmit Mode
bogdanm	0:9b334a45a8ff	2899	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2900	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2901	* @retval HAL status
bogdanm	0:9b334a45a8ff	2902	*/
bogdanm	0:9b334a45a8ff	2903	static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2904	{
bogdanm	0:9b334a45a8ff	2905	/* Process locked */
bogdanm	0:9b334a45a8ff	2906	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	2907
bogdanm	0:9b334a45a8ff	2908	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
bogdanm	0:9b334a45a8ff	2909	{
bogdanm	0:9b334a45a8ff	2910	/* Check that I2C transfer finished */
bogdanm	0:9b334a45a8ff	2911	/* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */
bogdanm	0:9b334a45a8ff	2912	/* Mean XferCount == 0*/
bogdanm	0:9b334a45a8ff	2913	/* So clear Flag NACKF only */
bogdanm	0:9b334a45a8ff	2914	if(hi2c->XferCount == 0)
bogdanm	0:9b334a45a8ff	2915	{
bogdanm	0:9b334a45a8ff	2916	/* Clear NACK Flag */
bogdanm	0:9b334a45a8ff	2917	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
bogdanm	0:9b334a45a8ff	2918
bogdanm	0:9b334a45a8ff	2919	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2920	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2921	}
bogdanm	0:9b334a45a8ff	2922	else
bogdanm	0:9b334a45a8ff	2923	{
bogdanm	0:9b334a45a8ff	2924	/* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/
bogdanm	0:9b334a45a8ff	2925	/* Clear NACK Flag */
bogdanm	0:9b334a45a8ff	2926	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
bogdanm	0:9b334a45a8ff	2927
bogdanm	0:9b334a45a8ff	2928	/* Set ErrorCode corresponding to a Non-Acknowledge */
bogdanm	0:9b334a45a8ff	2929	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	2930
bogdanm	0:9b334a45a8ff	2931	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2932	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2933
bogdanm	0:9b334a45a8ff	2934	/* Call the Error callback to prevent upper layer */
bogdanm	0:9b334a45a8ff	2935	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	2936	}
bogdanm	0:9b334a45a8ff	2937	}
bogdanm	0:9b334a45a8ff	2938	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
bogdanm	0:9b334a45a8ff	2939	{
bogdanm	0:9b334a45a8ff	2940	/* Clear ADDR flag */
bogdanm	0:9b334a45a8ff	2941	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
bogdanm	0:9b334a45a8ff	2942	}
bogdanm	0:9b334a45a8ff	2943	/* Check first if STOPF is set */
bogdanm	0:9b334a45a8ff	2944	/* to prevent a Write Data in TX buffer */
bogdanm	0:9b334a45a8ff	2945	/* which is stuck in TXDR until next */
bogdanm	0:9b334a45a8ff	2946	/* communication with Master */
bogdanm	0:9b334a45a8ff	2947	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
bogdanm	0:9b334a45a8ff	2948	{
mbed_official	113:b3775bf36a83	2949	/* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupts */
bogdanm	0:9b334a45a8ff	2950	__HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI );
bogdanm	0:9b334a45a8ff	2951
bogdanm	0:9b334a45a8ff	2952	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	2953	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	2954
bogdanm	0:9b334a45a8ff	2955	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	2956	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	2957
bogdanm	0:9b334a45a8ff	2958	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	2959
bogdanm	0:9b334a45a8ff	2960	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2961	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2962
bogdanm	0:9b334a45a8ff	2963	HAL_I2C_SlaveTxCpltCallback(hi2c);
bogdanm	0:9b334a45a8ff	2964	}
bogdanm	0:9b334a45a8ff	2965	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
bogdanm	0:9b334a45a8ff	2966	{
bogdanm	0:9b334a45a8ff	2967	/* Write data to TXDR only if XferCount not reach "0" */
bogdanm	0:9b334a45a8ff	2968	/* A TXIS flag can be set, during STOP treatment */
bogdanm	0:9b334a45a8ff	2969	if(hi2c->XferCount > 0)
bogdanm	0:9b334a45a8ff	2970	{
bogdanm	0:9b334a45a8ff	2971	/* Write data to TXDR */
bogdanm	0:9b334a45a8ff	2972	hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
bogdanm	0:9b334a45a8ff	2973	hi2c->XferCount--;
bogdanm	0:9b334a45a8ff	2974	}
bogdanm	0:9b334a45a8ff	2975	}
bogdanm	0:9b334a45a8ff	2976
bogdanm	0:9b334a45a8ff	2977	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2978	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	2979
bogdanm	0:9b334a45a8ff	2980	return HAL_OK;
bogdanm	0:9b334a45a8ff	2981	}
bogdanm	0:9b334a45a8ff	2982
bogdanm	0:9b334a45a8ff	2983	/**
bogdanm	0:9b334a45a8ff	2984	* @brief Handle Interrupt Flags Slave Receive Mode
bogdanm	0:9b334a45a8ff	2985	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2986	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	2987	* @retval HAL status
bogdanm	0:9b334a45a8ff	2988	*/
bogdanm	0:9b334a45a8ff	2989	static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c)
bogdanm	0:9b334a45a8ff	2990	{
bogdanm	0:9b334a45a8ff	2991	/* Process Locked */
bogdanm	0:9b334a45a8ff	2992	__HAL_LOCK(hi2c);
bogdanm	0:9b334a45a8ff	2993
bogdanm	0:9b334a45a8ff	2994	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
bogdanm	0:9b334a45a8ff	2995	{
bogdanm	0:9b334a45a8ff	2996	/* Clear NACK Flag */
bogdanm	0:9b334a45a8ff	2997	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
bogdanm	0:9b334a45a8ff	2998
bogdanm	0:9b334a45a8ff	2999	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	3000	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	3001
bogdanm	0:9b334a45a8ff	3002	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3003	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3004	}
bogdanm	0:9b334a45a8ff	3005	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
bogdanm	0:9b334a45a8ff	3006	{
bogdanm	0:9b334a45a8ff	3007	/* Clear ADDR flag */
bogdanm	0:9b334a45a8ff	3008	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
bogdanm	0:9b334a45a8ff	3009	}
bogdanm	0:9b334a45a8ff	3010	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
bogdanm	0:9b334a45a8ff	3011	{
bogdanm	0:9b334a45a8ff	3012	/* Read data from RXDR */
bogdanm	0:9b334a45a8ff	3013	(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
bogdanm	0:9b334a45a8ff	3014	hi2c->XferSize--;
bogdanm	0:9b334a45a8ff	3015	hi2c->XferCount--;
bogdanm	0:9b334a45a8ff	3016	}
bogdanm	0:9b334a45a8ff	3017	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
bogdanm	0:9b334a45a8ff	3018	{
mbed_official	113:b3775bf36a83	3019	/* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupts */
mbed_official	113:b3775bf36a83	3020	__HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI );
bogdanm	0:9b334a45a8ff	3021
bogdanm	0:9b334a45a8ff	3022	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	3023	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	3024
bogdanm	0:9b334a45a8ff	3025	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3026	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3027
bogdanm	0:9b334a45a8ff	3028	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3029
bogdanm	0:9b334a45a8ff	3030	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	3031	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	3032
bogdanm	0:9b334a45a8ff	3033	HAL_I2C_SlaveRxCpltCallback(hi2c);
bogdanm	0:9b334a45a8ff	3034	}
bogdanm	0:9b334a45a8ff	3035
bogdanm	0:9b334a45a8ff	3036	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	3037	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	3038
bogdanm	0:9b334a45a8ff	3039	return HAL_OK;
bogdanm	0:9b334a45a8ff	3040	}
bogdanm	0:9b334a45a8ff	3041
bogdanm	0:9b334a45a8ff	3042	/**
bogdanm	0:9b334a45a8ff	3043	* @brief Master sends target device address followed by internal memory address for write request.
bogdanm	0:9b334a45a8ff	3044	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3045	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	3046	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	3047	* @param MemAddress: Internal memory address
bogdanm	0:9b334a45a8ff	3048	* @param MemAddSize: Size of internal memory address
bogdanm	0:9b334a45a8ff	3049	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	3050	* @retval HAL status
bogdanm	0:9b334a45a8ff	3051	*/
bogdanm	0:9b334a45a8ff	3052	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	3053	{
bogdanm	0:9b334a45a8ff	3054	I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
bogdanm	0:9b334a45a8ff	3055
bogdanm	0:9b334a45a8ff	3056	/* Wait until TXIS flag is set */
bogdanm	0:9b334a45a8ff	3057	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	3058	{
bogdanm	0:9b334a45a8ff	3059	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3060	{
bogdanm	0:9b334a45a8ff	3061	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3062	}
bogdanm	0:9b334a45a8ff	3063	else
bogdanm	0:9b334a45a8ff	3064	{
bogdanm	0:9b334a45a8ff	3065	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	3066	}
bogdanm	0:9b334a45a8ff	3067	}
bogdanm	0:9b334a45a8ff	3068
bogdanm	0:9b334a45a8ff	3069	/* If Memory address size is 8Bit */
bogdanm	0:9b334a45a8ff	3070	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
bogdanm	0:9b334a45a8ff	3071	{
bogdanm	0:9b334a45a8ff	3072	/* Send Memory Address */
bogdanm	0:9b334a45a8ff	3073	hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress);
bogdanm	0:9b334a45a8ff	3074	}
bogdanm	0:9b334a45a8ff	3075	/* If Memory address size is 16Bit */
bogdanm	0:9b334a45a8ff	3076	else
bogdanm	0:9b334a45a8ff	3077	{
bogdanm	0:9b334a45a8ff	3078	/* Send MSB of Memory Address */
bogdanm	0:9b334a45a8ff	3079	hi2c->Instance->TXDR = __I2C_MEM_ADD_MSB(MemAddress);
bogdanm	0:9b334a45a8ff	3080
bogdanm	0:9b334a45a8ff	3081	/* Wait until TXIS flag is set */
bogdanm	0:9b334a45a8ff	3082	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	3083	{
bogdanm	0:9b334a45a8ff	3084	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3085	{
bogdanm	0:9b334a45a8ff	3086	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3087	}
bogdanm	0:9b334a45a8ff	3088	else
bogdanm	0:9b334a45a8ff	3089	{
bogdanm	0:9b334a45a8ff	3090	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	3091	}
bogdanm	0:9b334a45a8ff	3092	}
bogdanm	0:9b334a45a8ff	3093
bogdanm	0:9b334a45a8ff	3094	/* Send LSB of Memory Address */
bogdanm	0:9b334a45a8ff	3095	hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress);
bogdanm	0:9b334a45a8ff	3096	}
bogdanm	0:9b334a45a8ff	3097
bogdanm	0:9b334a45a8ff	3098	/* Wait until TCR flag is set */
bogdanm	0:9b334a45a8ff	3099	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	3100	{
bogdanm	0:9b334a45a8ff	3101	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	3102	}
bogdanm	0:9b334a45a8ff	3103
bogdanm	0:9b334a45a8ff	3104	return HAL_OK;
bogdanm	0:9b334a45a8ff	3105	}
bogdanm	0:9b334a45a8ff	3106
bogdanm	0:9b334a45a8ff	3107	/**
bogdanm	0:9b334a45a8ff	3108	* @brief Master sends target device address followed by internal memory address for read request.
bogdanm	0:9b334a45a8ff	3109	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3110	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	3111	* @param DevAddress: Target device address
bogdanm	0:9b334a45a8ff	3112	* @param MemAddress: Internal memory address
bogdanm	0:9b334a45a8ff	3113	* @param MemAddSize: Size of internal memory address
bogdanm	0:9b334a45a8ff	3114	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	3115	* @retval HAL status
bogdanm	0:9b334a45a8ff	3116	*/
bogdanm	0:9b334a45a8ff	3117	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	3118	{
bogdanm	0:9b334a45a8ff	3119	I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
bogdanm	0:9b334a45a8ff	3120
bogdanm	0:9b334a45a8ff	3121	/* Wait until TXIS flag is set */
bogdanm	0:9b334a45a8ff	3122	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	3123	{
bogdanm	0:9b334a45a8ff	3124	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3125	{
bogdanm	0:9b334a45a8ff	3126	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3127	}
bogdanm	0:9b334a45a8ff	3128	else
bogdanm	0:9b334a45a8ff	3129	{
bogdanm	0:9b334a45a8ff	3130	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	3131	}
bogdanm	0:9b334a45a8ff	3132	}
bogdanm	0:9b334a45a8ff	3133
bogdanm	0:9b334a45a8ff	3134	/* If Memory address size is 8Bit */
bogdanm	0:9b334a45a8ff	3135	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
bogdanm	0:9b334a45a8ff	3136	{
bogdanm	0:9b334a45a8ff	3137	/* Send Memory Address */
bogdanm	0:9b334a45a8ff	3138	hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress);
bogdanm	0:9b334a45a8ff	3139	}
mbed_official	113:b3775bf36a83	3140	/* If Memory address size is 16Bit */
bogdanm	0:9b334a45a8ff	3141	else
bogdanm	0:9b334a45a8ff	3142	{
bogdanm	0:9b334a45a8ff	3143	/* Send MSB of Memory Address */
bogdanm	0:9b334a45a8ff	3144	hi2c->Instance->TXDR = __I2C_MEM_ADD_MSB(MemAddress);
bogdanm	0:9b334a45a8ff	3145
bogdanm	0:9b334a45a8ff	3146	/* Wait until TXIS flag is set */
bogdanm	0:9b334a45a8ff	3147	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	3148	{
bogdanm	0:9b334a45a8ff	3149	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3150	{
bogdanm	0:9b334a45a8ff	3151	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	3152	}
bogdanm	0:9b334a45a8ff	3153	else
bogdanm	0:9b334a45a8ff	3154	{
bogdanm	0:9b334a45a8ff	3155	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	3156	}
bogdanm	0:9b334a45a8ff	3157	}
bogdanm	0:9b334a45a8ff	3158
bogdanm	0:9b334a45a8ff	3159	/* Send LSB of Memory Address */
bogdanm	0:9b334a45a8ff	3160	hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress);
bogdanm	0:9b334a45a8ff	3161	}
bogdanm	0:9b334a45a8ff	3162
bogdanm	0:9b334a45a8ff	3163	/* Wait until TC flag is set */
bogdanm	0:9b334a45a8ff	3164	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	3165	{
bogdanm	0:9b334a45a8ff	3166	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	3167	}
bogdanm	0:9b334a45a8ff	3168
bogdanm	0:9b334a45a8ff	3169	return HAL_OK;
bogdanm	0:9b334a45a8ff	3170	}
bogdanm	0:9b334a45a8ff	3171
bogdanm	0:9b334a45a8ff	3172	/**
bogdanm	0:9b334a45a8ff	3173	* @brief DMA I2C master transmit process complete callback.
bogdanm	0:9b334a45a8ff	3174	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	3175	* @retval None
bogdanm	0:9b334a45a8ff	3176	*/
bogdanm	0:9b334a45a8ff	3177	static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	3178	{
bogdanm	0:9b334a45a8ff	3179	uint16_t DevAddress;
bogdanm	0:9b334a45a8ff	3180	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	3181
bogdanm	0:9b334a45a8ff	3182	/* Check if last DMA request was done with RELOAD */
bogdanm	0:9b334a45a8ff	3183	/* Set NBYTES to write and reload if size > 255 */
bogdanm	0:9b334a45a8ff	3184	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	3185	{
bogdanm	0:9b334a45a8ff	3186	/* Wait until TCR flag is set */
bogdanm	0:9b334a45a8ff	3187	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
bogdanm	0:9b334a45a8ff	3188	{
bogdanm	0:9b334a45a8ff	3189	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3190	}
bogdanm	0:9b334a45a8ff	3191
bogdanm	0:9b334a45a8ff	3192	/* Disable DMA Request */
bogdanm	0:9b334a45a8ff	3193	hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
bogdanm	0:9b334a45a8ff	3194
bogdanm	0:9b334a45a8ff	3195	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	3196	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	3197	{
bogdanm	0:9b334a45a8ff	3198	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	3199	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3200	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3201	{
bogdanm	0:9b334a45a8ff	3202	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3203	{
bogdanm	0:9b334a45a8ff	3204	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3205	}
bogdanm	0:9b334a45a8ff	3206	else
bogdanm	0:9b334a45a8ff	3207	{
bogdanm	0:9b334a45a8ff	3208	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3209	}
bogdanm	0:9b334a45a8ff	3210	}
bogdanm	0:9b334a45a8ff	3211
bogdanm	0:9b334a45a8ff	3212	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3213	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3214
bogdanm	0:9b334a45a8ff	3215	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	3216	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	3217
bogdanm	0:9b334a45a8ff	3218	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3219
bogdanm	0:9b334a45a8ff	3220	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3221	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3222	}
bogdanm	0:9b334a45a8ff	3223	else
bogdanm	0:9b334a45a8ff	3224	{
bogdanm	0:9b334a45a8ff	3225	hi2c->pBuffPtr += hi2c->XferSize;
bogdanm	0:9b334a45a8ff	3226	hi2c->XferCount -= hi2c->XferSize;
bogdanm	0:9b334a45a8ff	3227	if(hi2c->XferCount > 255)
bogdanm	0:9b334a45a8ff	3228	{
bogdanm	0:9b334a45a8ff	3229	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	3230	}
bogdanm	0:9b334a45a8ff	3231	else
bogdanm	0:9b334a45a8ff	3232	{
bogdanm	0:9b334a45a8ff	3233	hi2c->XferSize = hi2c->XferCount;
bogdanm	0:9b334a45a8ff	3234	}
bogdanm	0:9b334a45a8ff	3235
bogdanm	0:9b334a45a8ff	3236	DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
bogdanm	0:9b334a45a8ff	3237
bogdanm	0:9b334a45a8ff	3238	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3239	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
bogdanm	0:9b334a45a8ff	3240
bogdanm	0:9b334a45a8ff	3241	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	3242	/* Set NBYTES to write and reload if size > 255 */
bogdanm	0:9b334a45a8ff	3243	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	3244	{
bogdanm	0:9b334a45a8ff	3245	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	3246	}
bogdanm	0:9b334a45a8ff	3247	else
bogdanm	0:9b334a45a8ff	3248	{
bogdanm	0:9b334a45a8ff	3249	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	3250	}
bogdanm	0:9b334a45a8ff	3251
bogdanm	0:9b334a45a8ff	3252	/* Wait until TXIS flag is set */
bogdanm	0:9b334a45a8ff	3253	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
bogdanm	0:9b334a45a8ff	3254	{
bogdanm	0:9b334a45a8ff	3255	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	3256	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3257	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3258	{
bogdanm	0:9b334a45a8ff	3259	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3260	{
bogdanm	0:9b334a45a8ff	3261	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3262	}
bogdanm	0:9b334a45a8ff	3263	else
bogdanm	0:9b334a45a8ff	3264	{
bogdanm	0:9b334a45a8ff	3265	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3266	}
bogdanm	0:9b334a45a8ff	3267	}
bogdanm	0:9b334a45a8ff	3268
bogdanm	0:9b334a45a8ff	3269	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3270	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3271
bogdanm	0:9b334a45a8ff	3272	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	3273	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	3274
bogdanm	0:9b334a45a8ff	3275	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3276
bogdanm	0:9b334a45a8ff	3277	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3278	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3279	}
bogdanm	0:9b334a45a8ff	3280	else
bogdanm	0:9b334a45a8ff	3281	{
bogdanm	0:9b334a45a8ff	3282	/* Enable DMA Request */
bogdanm	0:9b334a45a8ff	3283	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
bogdanm	0:9b334a45a8ff	3284	}
bogdanm	0:9b334a45a8ff	3285	}
bogdanm	0:9b334a45a8ff	3286	}
bogdanm	0:9b334a45a8ff	3287	else
bogdanm	0:9b334a45a8ff	3288	{
bogdanm	0:9b334a45a8ff	3289	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	3290	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3291	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3292	{
bogdanm	0:9b334a45a8ff	3293	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3294	{
bogdanm	0:9b334a45a8ff	3295	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3296	}
bogdanm	0:9b334a45a8ff	3297	else
bogdanm	0:9b334a45a8ff	3298	{
bogdanm	0:9b334a45a8ff	3299	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3300	}
bogdanm	0:9b334a45a8ff	3301	}
bogdanm	0:9b334a45a8ff	3302
bogdanm	0:9b334a45a8ff	3303	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3304	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3305
bogdanm	0:9b334a45a8ff	3306	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	3307	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	3308
bogdanm	0:9b334a45a8ff	3309	/* Disable DMA Request */
bogdanm	0:9b334a45a8ff	3310	hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
bogdanm	0:9b334a45a8ff	3311
bogdanm	0:9b334a45a8ff	3312	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3313
bogdanm	0:9b334a45a8ff	3314	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3315
bogdanm	0:9b334a45a8ff	3316	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	3317	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	3318	{
bogdanm	0:9b334a45a8ff	3319	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3320	}
bogdanm	0:9b334a45a8ff	3321	else
bogdanm	0:9b334a45a8ff	3322	{
bogdanm	0:9b334a45a8ff	3323	HAL_I2C_MasterTxCpltCallback(hi2c);
bogdanm	0:9b334a45a8ff	3324	}
bogdanm	0:9b334a45a8ff	3325	}
bogdanm	0:9b334a45a8ff	3326	}
bogdanm	0:9b334a45a8ff	3327
bogdanm	0:9b334a45a8ff	3328	/**
bogdanm	0:9b334a45a8ff	3329	* @brief DMA I2C slave transmit process complete callback.
bogdanm	0:9b334a45a8ff	3330	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	3331	* @retval None
bogdanm	0:9b334a45a8ff	3332	*/
bogdanm	0:9b334a45a8ff	3333	static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	3334	{
bogdanm	0:9b334a45a8ff	3335	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	3336
bogdanm	0:9b334a45a8ff	3337	/* Wait until STOP flag is set */
bogdanm	0:9b334a45a8ff	3338	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3339	{
bogdanm	0:9b334a45a8ff	3340	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3341	{
bogdanm	0:9b334a45a8ff	3342	/* Normal Use case, a AF is generated by master */
bogdanm	0:9b334a45a8ff	3343	/* to inform slave the end of transfer */
bogdanm	0:9b334a45a8ff	3344	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	3345	}
bogdanm	0:9b334a45a8ff	3346	else
bogdanm	0:9b334a45a8ff	3347	{
bogdanm	0:9b334a45a8ff	3348	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3349	}
bogdanm	0:9b334a45a8ff	3350	}
bogdanm	0:9b334a45a8ff	3351
bogdanm	0:9b334a45a8ff	3352	/* Clear STOP flag */
bogdanm	0:9b334a45a8ff	3353	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3354
bogdanm	0:9b334a45a8ff	3355	/* Wait until BUSY flag is reset */
bogdanm	0:9b334a45a8ff	3356	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK)
bogdanm	0:9b334a45a8ff	3357	{
bogdanm	0:9b334a45a8ff	3358	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3359	}
bogdanm	0:9b334a45a8ff	3360
bogdanm	0:9b334a45a8ff	3361	/* Disable DMA Request */
bogdanm	0:9b334a45a8ff	3362	hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
bogdanm	0:9b334a45a8ff	3363
bogdanm	0:9b334a45a8ff	3364	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3365
bogdanm	0:9b334a45a8ff	3366	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3367
bogdanm	0:9b334a45a8ff	3368	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	3369	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	3370	{
bogdanm	0:9b334a45a8ff	3371	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3372	}
bogdanm	0:9b334a45a8ff	3373	else
bogdanm	0:9b334a45a8ff	3374	{
bogdanm	0:9b334a45a8ff	3375	HAL_I2C_SlaveTxCpltCallback(hi2c);
bogdanm	0:9b334a45a8ff	3376	}
bogdanm	0:9b334a45a8ff	3377	}
bogdanm	0:9b334a45a8ff	3378
bogdanm	0:9b334a45a8ff	3379	/**
bogdanm	0:9b334a45a8ff	3380	* @brief DMA I2C master receive process complete callback
bogdanm	0:9b334a45a8ff	3381	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	3382	* @retval None
bogdanm	0:9b334a45a8ff	3383	*/
bogdanm	0:9b334a45a8ff	3384	static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	3385	{
bogdanm	0:9b334a45a8ff	3386	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	3387	uint16_t DevAddress;
bogdanm	0:9b334a45a8ff	3388
bogdanm	0:9b334a45a8ff	3389	/* Check if last DMA request was done with RELOAD */
bogdanm	0:9b334a45a8ff	3390	/* Set NBYTES to write and reload if size > 255 */
bogdanm	0:9b334a45a8ff	3391	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	3392	{
bogdanm	0:9b334a45a8ff	3393	/* Wait until TCR flag is set */
bogdanm	0:9b334a45a8ff	3394	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
bogdanm	0:9b334a45a8ff	3395	{
bogdanm	0:9b334a45a8ff	3396	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3397	}
bogdanm	0:9b334a45a8ff	3398
bogdanm	0:9b334a45a8ff	3399	/* Disable DMA Request */
bogdanm	0:9b334a45a8ff	3400	hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
bogdanm	0:9b334a45a8ff	3401
bogdanm	0:9b334a45a8ff	3402	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	3403	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	3404	{
bogdanm	0:9b334a45a8ff	3405	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	3406	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3407	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3408	{
bogdanm	0:9b334a45a8ff	3409	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3410	{
bogdanm	0:9b334a45a8ff	3411	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3412	}
bogdanm	0:9b334a45a8ff	3413	else
bogdanm	0:9b334a45a8ff	3414	{
bogdanm	0:9b334a45a8ff	3415	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3416	}
bogdanm	0:9b334a45a8ff	3417	}
bogdanm	0:9b334a45a8ff	3418
bogdanm	0:9b334a45a8ff	3419	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3420	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3421
bogdanm	0:9b334a45a8ff	3422	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	3423	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	3424
bogdanm	0:9b334a45a8ff	3425	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3426
bogdanm	0:9b334a45a8ff	3427	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3428	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3429	}
bogdanm	0:9b334a45a8ff	3430	else
bogdanm	0:9b334a45a8ff	3431	{
bogdanm	0:9b334a45a8ff	3432	hi2c->pBuffPtr += hi2c->XferSize;
bogdanm	0:9b334a45a8ff	3433	hi2c->XferCount -= hi2c->XferSize;
bogdanm	0:9b334a45a8ff	3434	if(hi2c->XferCount > 255)
bogdanm	0:9b334a45a8ff	3435	{
bogdanm	0:9b334a45a8ff	3436	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	3437	}
bogdanm	0:9b334a45a8ff	3438	else
bogdanm	0:9b334a45a8ff	3439	{
bogdanm	0:9b334a45a8ff	3440	hi2c->XferSize = hi2c->XferCount;
bogdanm	0:9b334a45a8ff	3441	}
bogdanm	0:9b334a45a8ff	3442
bogdanm	0:9b334a45a8ff	3443	DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
bogdanm	0:9b334a45a8ff	3444
bogdanm	0:9b334a45a8ff	3445	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3446	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
bogdanm	0:9b334a45a8ff	3447
bogdanm	0:9b334a45a8ff	3448	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	3449	/* Set NBYTES to write and reload if size > 255 */
bogdanm	0:9b334a45a8ff	3450	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	3451	{
bogdanm	0:9b334a45a8ff	3452	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	3453	}
bogdanm	0:9b334a45a8ff	3454	else
bogdanm	0:9b334a45a8ff	3455	{
bogdanm	0:9b334a45a8ff	3456	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	3457	}
bogdanm	0:9b334a45a8ff	3458
bogdanm	0:9b334a45a8ff	3459	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	3460	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
bogdanm	0:9b334a45a8ff	3461	{
bogdanm	0:9b334a45a8ff	3462	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3463	}
bogdanm	0:9b334a45a8ff	3464
bogdanm	0:9b334a45a8ff	3465	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	3466	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	3467	{
bogdanm	0:9b334a45a8ff	3468	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	3469	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3470	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3471	{
bogdanm	0:9b334a45a8ff	3472	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3473	{
bogdanm	0:9b334a45a8ff	3474	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3475	}
bogdanm	0:9b334a45a8ff	3476	else
bogdanm	0:9b334a45a8ff	3477	{
bogdanm	0:9b334a45a8ff	3478	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3479	}
bogdanm	0:9b334a45a8ff	3480	}
bogdanm	0:9b334a45a8ff	3481
bogdanm	0:9b334a45a8ff	3482	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3483	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3484
bogdanm	0:9b334a45a8ff	3485	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	3486	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	3487
bogdanm	0:9b334a45a8ff	3488	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3489
bogdanm	0:9b334a45a8ff	3490	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3491
bogdanm	0:9b334a45a8ff	3492	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3493	}
bogdanm	0:9b334a45a8ff	3494	else
bogdanm	0:9b334a45a8ff	3495	{
bogdanm	0:9b334a45a8ff	3496	/* Enable DMA Request */
bogdanm	0:9b334a45a8ff	3497	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
bogdanm	0:9b334a45a8ff	3498	}
bogdanm	0:9b334a45a8ff	3499	}
bogdanm	0:9b334a45a8ff	3500	}
bogdanm	0:9b334a45a8ff	3501	else
bogdanm	0:9b334a45a8ff	3502	{
bogdanm	0:9b334a45a8ff	3503	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	3504	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3505	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3506	{
bogdanm	0:9b334a45a8ff	3507	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3508	{
bogdanm	0:9b334a45a8ff	3509	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3510	}
bogdanm	0:9b334a45a8ff	3511	else
bogdanm	0:9b334a45a8ff	3512	{
bogdanm	0:9b334a45a8ff	3513	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3514	}
bogdanm	0:9b334a45a8ff	3515	}
bogdanm	0:9b334a45a8ff	3516
bogdanm	0:9b334a45a8ff	3517	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3518	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3519
bogdanm	0:9b334a45a8ff	3520	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	3521	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	3522
bogdanm	0:9b334a45a8ff	3523	/* Disable DMA Request */
bogdanm	0:9b334a45a8ff	3524	hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
bogdanm	0:9b334a45a8ff	3525
bogdanm	0:9b334a45a8ff	3526	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3527
bogdanm	0:9b334a45a8ff	3528	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3529
bogdanm	0:9b334a45a8ff	3530	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	3531	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	3532	{
bogdanm	0:9b334a45a8ff	3533	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3534	}
bogdanm	0:9b334a45a8ff	3535	else
bogdanm	0:9b334a45a8ff	3536	{
bogdanm	0:9b334a45a8ff	3537	HAL_I2C_MasterRxCpltCallback(hi2c);
bogdanm	0:9b334a45a8ff	3538	}
bogdanm	0:9b334a45a8ff	3539	}
bogdanm	0:9b334a45a8ff	3540	}
bogdanm	0:9b334a45a8ff	3541
bogdanm	0:9b334a45a8ff	3542	/**
bogdanm	0:9b334a45a8ff	3543	* @brief DMA I2C slave receive process complete callback.
bogdanm	0:9b334a45a8ff	3544	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	3545	* @retval None
bogdanm	0:9b334a45a8ff	3546	*/
bogdanm	0:9b334a45a8ff	3547	static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	3548	{
bogdanm	0:9b334a45a8ff	3549	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	3550
bogdanm	0:9b334a45a8ff	3551	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3552	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3553	{
bogdanm	0:9b334a45a8ff	3554	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3555	{
bogdanm	0:9b334a45a8ff	3556	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3557	}
bogdanm	0:9b334a45a8ff	3558	else
bogdanm	0:9b334a45a8ff	3559	{
bogdanm	0:9b334a45a8ff	3560	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3561	}
bogdanm	0:9b334a45a8ff	3562	}
bogdanm	0:9b334a45a8ff	3563
bogdanm	0:9b334a45a8ff	3564	/* Clear STOPF flag */
bogdanm	0:9b334a45a8ff	3565	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3566
bogdanm	0:9b334a45a8ff	3567	/* Wait until BUSY flag is reset */
bogdanm	0:9b334a45a8ff	3568	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK)
bogdanm	0:9b334a45a8ff	3569	{
bogdanm	0:9b334a45a8ff	3570	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3571	}
bogdanm	0:9b334a45a8ff	3572
bogdanm	0:9b334a45a8ff	3573	/* Disable DMA Request */
bogdanm	0:9b334a45a8ff	3574	hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
bogdanm	0:9b334a45a8ff	3575
bogdanm	0:9b334a45a8ff	3576	/* Disable Address Acknowledge */
bogdanm	0:9b334a45a8ff	3577	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	3578
bogdanm	0:9b334a45a8ff	3579	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3580
bogdanm	0:9b334a45a8ff	3581	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3582
bogdanm	0:9b334a45a8ff	3583	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	3584	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	3585	{
bogdanm	0:9b334a45a8ff	3586	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3587	}
bogdanm	0:9b334a45a8ff	3588	else
bogdanm	0:9b334a45a8ff	3589	{
bogdanm	0:9b334a45a8ff	3590	HAL_I2C_SlaveRxCpltCallback(hi2c);
bogdanm	0:9b334a45a8ff	3591	}
bogdanm	0:9b334a45a8ff	3592	}
bogdanm	0:9b334a45a8ff	3593
bogdanm	0:9b334a45a8ff	3594	/**
bogdanm	0:9b334a45a8ff	3595	* @brief DMA I2C Memory Write process complete callback
bogdanm	0:9b334a45a8ff	3596	* @param hdma : DMA handle
bogdanm	0:9b334a45a8ff	3597	* @retval None
bogdanm	0:9b334a45a8ff	3598	*/
bogdanm	0:9b334a45a8ff	3599	static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	3600	{
bogdanm	0:9b334a45a8ff	3601	uint16_t DevAddress;
bogdanm	0:9b334a45a8ff	3602	I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	3603
bogdanm	0:9b334a45a8ff	3604	/* Check if last DMA request was done with RELOAD */
bogdanm	0:9b334a45a8ff	3605	/* Set NBYTES to write and reload if size > 255 */
bogdanm	0:9b334a45a8ff	3606	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	3607	{
bogdanm	0:9b334a45a8ff	3608	/* Wait until TCR flag is set */
bogdanm	0:9b334a45a8ff	3609	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
bogdanm	0:9b334a45a8ff	3610	{
bogdanm	0:9b334a45a8ff	3611	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3612	}
bogdanm	0:9b334a45a8ff	3613
bogdanm	0:9b334a45a8ff	3614	/* Disable DMA Request */
bogdanm	0:9b334a45a8ff	3615	hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
bogdanm	0:9b334a45a8ff	3616
bogdanm	0:9b334a45a8ff	3617	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	3618	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	3619	{
bogdanm	0:9b334a45a8ff	3620	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	3621	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3622	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3623	{
bogdanm	0:9b334a45a8ff	3624	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3625	{
bogdanm	0:9b334a45a8ff	3626	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3627	}
bogdanm	0:9b334a45a8ff	3628	else
bogdanm	0:9b334a45a8ff	3629	{
bogdanm	0:9b334a45a8ff	3630	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3631	}
bogdanm	0:9b334a45a8ff	3632	}
bogdanm	0:9b334a45a8ff	3633
bogdanm	0:9b334a45a8ff	3634	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3635	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3636
bogdanm	0:9b334a45a8ff	3637	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	3638	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	3639
bogdanm	0:9b334a45a8ff	3640	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3641
bogdanm	0:9b334a45a8ff	3642	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3643	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3644	}
bogdanm	0:9b334a45a8ff	3645	else
bogdanm	0:9b334a45a8ff	3646	{
bogdanm	0:9b334a45a8ff	3647	hi2c->pBuffPtr += hi2c->XferSize;
bogdanm	0:9b334a45a8ff	3648	hi2c->XferCount -= hi2c->XferSize;
bogdanm	0:9b334a45a8ff	3649	if(hi2c->XferCount > 255)
bogdanm	0:9b334a45a8ff	3650	{
bogdanm	0:9b334a45a8ff	3651	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	3652	}
bogdanm	0:9b334a45a8ff	3653	else
bogdanm	0:9b334a45a8ff	3654	{
bogdanm	0:9b334a45a8ff	3655	hi2c->XferSize = hi2c->XferCount;
bogdanm	0:9b334a45a8ff	3656	}
bogdanm	0:9b334a45a8ff	3657
bogdanm	0:9b334a45a8ff	3658	DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
bogdanm	0:9b334a45a8ff	3659
bogdanm	0:9b334a45a8ff	3660	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3661	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
bogdanm	0:9b334a45a8ff	3662
bogdanm	0:9b334a45a8ff	3663	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	3664	/* Set NBYTES to write and reload if size > 255 */
bogdanm	0:9b334a45a8ff	3665	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	3666	{
bogdanm	0:9b334a45a8ff	3667	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	3668	}
bogdanm	0:9b334a45a8ff	3669	else
bogdanm	0:9b334a45a8ff	3670	{
bogdanm	0:9b334a45a8ff	3671	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	3672	}
bogdanm	0:9b334a45a8ff	3673
bogdanm	0:9b334a45a8ff	3674	/* Wait until TXIS flag is set */
bogdanm	0:9b334a45a8ff	3675	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
bogdanm	0:9b334a45a8ff	3676	{
bogdanm	0:9b334a45a8ff	3677	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	3678	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3679	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3680	{
bogdanm	0:9b334a45a8ff	3681	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3682	{
bogdanm	0:9b334a45a8ff	3683	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3684	}
bogdanm	0:9b334a45a8ff	3685	else
bogdanm	0:9b334a45a8ff	3686	{
bogdanm	0:9b334a45a8ff	3687	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3688	}
bogdanm	0:9b334a45a8ff	3689	}
bogdanm	0:9b334a45a8ff	3690
bogdanm	0:9b334a45a8ff	3691	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3692	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3693
bogdanm	0:9b334a45a8ff	3694	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	3695	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	3696
bogdanm	0:9b334a45a8ff	3697	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3698
bogdanm	0:9b334a45a8ff	3699	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3700	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3701	}
bogdanm	0:9b334a45a8ff	3702	else
bogdanm	0:9b334a45a8ff	3703	{
bogdanm	0:9b334a45a8ff	3704	/* Enable DMA Request */
bogdanm	0:9b334a45a8ff	3705	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
bogdanm	0:9b334a45a8ff	3706	}
bogdanm	0:9b334a45a8ff	3707	}
bogdanm	0:9b334a45a8ff	3708	}
bogdanm	0:9b334a45a8ff	3709	else
bogdanm	0:9b334a45a8ff	3710	{
bogdanm	0:9b334a45a8ff	3711	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	3712	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3713	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3714	{
bogdanm	0:9b334a45a8ff	3715	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3716	{
bogdanm	0:9b334a45a8ff	3717	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3718	}
bogdanm	0:9b334a45a8ff	3719	else
bogdanm	0:9b334a45a8ff	3720	{
bogdanm	0:9b334a45a8ff	3721	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3722	}
bogdanm	0:9b334a45a8ff	3723	}
bogdanm	0:9b334a45a8ff	3724
bogdanm	0:9b334a45a8ff	3725	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3726	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3727
bogdanm	0:9b334a45a8ff	3728	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	3729	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	3730
bogdanm	0:9b334a45a8ff	3731	/* Disable DMA Request */
bogdanm	0:9b334a45a8ff	3732	hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
bogdanm	0:9b334a45a8ff	3733
bogdanm	0:9b334a45a8ff	3734	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3735
bogdanm	0:9b334a45a8ff	3736	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3737
bogdanm	0:9b334a45a8ff	3738	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	3739	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	3740	{
bogdanm	0:9b334a45a8ff	3741	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3742	}
bogdanm	0:9b334a45a8ff	3743	else
bogdanm	0:9b334a45a8ff	3744	{
bogdanm	0:9b334a45a8ff	3745	HAL_I2C_MemTxCpltCallback(hi2c);
bogdanm	0:9b334a45a8ff	3746	}
bogdanm	0:9b334a45a8ff	3747	}
bogdanm	0:9b334a45a8ff	3748	}
bogdanm	0:9b334a45a8ff	3749
bogdanm	0:9b334a45a8ff	3750	/**
bogdanm	0:9b334a45a8ff	3751	* @brief DMA I2C Memory Read process complete callback
bogdanm	0:9b334a45a8ff	3752	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	3753	* @retval None
bogdanm	0:9b334a45a8ff	3754	*/
bogdanm	0:9b334a45a8ff	3755	static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	3756	{
bogdanm	0:9b334a45a8ff	3757	I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	3758	uint16_t DevAddress;
bogdanm	0:9b334a45a8ff	3759
bogdanm	0:9b334a45a8ff	3760	/* Check if last DMA request was done with RELOAD */
bogdanm	0:9b334a45a8ff	3761	/* Set NBYTES to write and reload if size > 255 */
bogdanm	0:9b334a45a8ff	3762	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	3763	{
bogdanm	0:9b334a45a8ff	3764	/* Wait until TCR flag is set */
bogdanm	0:9b334a45a8ff	3765	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
bogdanm	0:9b334a45a8ff	3766	{
bogdanm	0:9b334a45a8ff	3767	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3768	}
bogdanm	0:9b334a45a8ff	3769
bogdanm	0:9b334a45a8ff	3770	/* Disable DMA Request */
bogdanm	0:9b334a45a8ff	3771	hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
bogdanm	0:9b334a45a8ff	3772
bogdanm	0:9b334a45a8ff	3773	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	3774	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	3775	{
bogdanm	0:9b334a45a8ff	3776	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	3777	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3778	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3779	{
bogdanm	0:9b334a45a8ff	3780	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3781	{
bogdanm	0:9b334a45a8ff	3782	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3783	}
bogdanm	0:9b334a45a8ff	3784	else
bogdanm	0:9b334a45a8ff	3785	{
bogdanm	0:9b334a45a8ff	3786	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3787	}
bogdanm	0:9b334a45a8ff	3788	}
bogdanm	0:9b334a45a8ff	3789
bogdanm	0:9b334a45a8ff	3790	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3791	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3792
bogdanm	0:9b334a45a8ff	3793	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	3794	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	3795
bogdanm	0:9b334a45a8ff	3796	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3797
bogdanm	0:9b334a45a8ff	3798	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3799	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3800	}
bogdanm	0:9b334a45a8ff	3801	else
bogdanm	0:9b334a45a8ff	3802	{
bogdanm	0:9b334a45a8ff	3803	hi2c->pBuffPtr += hi2c->XferSize;
bogdanm	0:9b334a45a8ff	3804	hi2c->XferCount -= hi2c->XferSize;
bogdanm	0:9b334a45a8ff	3805	if(hi2c->XferCount > 255)
bogdanm	0:9b334a45a8ff	3806	{
bogdanm	0:9b334a45a8ff	3807	hi2c->XferSize = 255;
bogdanm	0:9b334a45a8ff	3808	}
bogdanm	0:9b334a45a8ff	3809	else
bogdanm	0:9b334a45a8ff	3810	{
bogdanm	0:9b334a45a8ff	3811	hi2c->XferSize = hi2c->XferCount;
bogdanm	0:9b334a45a8ff	3812	}
bogdanm	0:9b334a45a8ff	3813
bogdanm	0:9b334a45a8ff	3814	DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
bogdanm	0:9b334a45a8ff	3815
bogdanm	0:9b334a45a8ff	3816	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	3817	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
bogdanm	0:9b334a45a8ff	3818
bogdanm	0:9b334a45a8ff	3819	/* Send Slave Address */
bogdanm	0:9b334a45a8ff	3820	/* Set NBYTES to write and reload if size > 255 */
bogdanm	0:9b334a45a8ff	3821	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
bogdanm	0:9b334a45a8ff	3822	{
bogdanm	0:9b334a45a8ff	3823	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	3824	}
bogdanm	0:9b334a45a8ff	3825	else
bogdanm	0:9b334a45a8ff	3826	{
bogdanm	0:9b334a45a8ff	3827	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
bogdanm	0:9b334a45a8ff	3828	}
bogdanm	0:9b334a45a8ff	3829
bogdanm	0:9b334a45a8ff	3830	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	3831	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
bogdanm	0:9b334a45a8ff	3832	{
bogdanm	0:9b334a45a8ff	3833	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3834	}
bogdanm	0:9b334a45a8ff	3835
bogdanm	0:9b334a45a8ff	3836	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	3837	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	3838	{
bogdanm	0:9b334a45a8ff	3839	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	3840	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3841	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3842	{
bogdanm	0:9b334a45a8ff	3843	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3844	{
bogdanm	0:9b334a45a8ff	3845	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3846	}
bogdanm	0:9b334a45a8ff	3847	else
bogdanm	0:9b334a45a8ff	3848	{
bogdanm	0:9b334a45a8ff	3849	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3850	}
bogdanm	0:9b334a45a8ff	3851	}
bogdanm	0:9b334a45a8ff	3852
bogdanm	0:9b334a45a8ff	3853	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3854	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3855
bogdanm	0:9b334a45a8ff	3856	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	3857	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	3858
bogdanm	0:9b334a45a8ff	3859	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3860
bogdanm	0:9b334a45a8ff	3861	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3862	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3863	}
bogdanm	0:9b334a45a8ff	3864	else
bogdanm	0:9b334a45a8ff	3865	{
bogdanm	0:9b334a45a8ff	3866	/* Enable DMA Request */
bogdanm	0:9b334a45a8ff	3867	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
bogdanm	0:9b334a45a8ff	3868	}
bogdanm	0:9b334a45a8ff	3869	}
bogdanm	0:9b334a45a8ff	3870	}
bogdanm	0:9b334a45a8ff	3871	else
bogdanm	0:9b334a45a8ff	3872	{
bogdanm	0:9b334a45a8ff	3873	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
bogdanm	0:9b334a45a8ff	3874	/* Wait until STOPF flag is reset */
bogdanm	0:9b334a45a8ff	3875	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
bogdanm	0:9b334a45a8ff	3876	{
bogdanm	0:9b334a45a8ff	3877	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
bogdanm	0:9b334a45a8ff	3878	{
bogdanm	0:9b334a45a8ff	3879	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	3880	}
bogdanm	0:9b334a45a8ff	3881	else
bogdanm	0:9b334a45a8ff	3882	{
bogdanm	0:9b334a45a8ff	3883	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	3884	}
bogdanm	0:9b334a45a8ff	3885	}
bogdanm	0:9b334a45a8ff	3886
bogdanm	0:9b334a45a8ff	3887	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	3888	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	3889
bogdanm	0:9b334a45a8ff	3890	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	3891	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	3892
bogdanm	0:9b334a45a8ff	3893	/* Disable DMA Request */
bogdanm	0:9b334a45a8ff	3894	hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
bogdanm	0:9b334a45a8ff	3895
bogdanm	0:9b334a45a8ff	3896	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3897
bogdanm	0:9b334a45a8ff	3898	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3899
bogdanm	0:9b334a45a8ff	3900	/* Check if Errors has been detected during transfer */
bogdanm	0:9b334a45a8ff	3901	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
bogdanm	0:9b334a45a8ff	3902	{
bogdanm	0:9b334a45a8ff	3903	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3904	}
bogdanm	0:9b334a45a8ff	3905	else
bogdanm	0:9b334a45a8ff	3906	{
bogdanm	0:9b334a45a8ff	3907	HAL_I2C_MemRxCpltCallback(hi2c);
bogdanm	0:9b334a45a8ff	3908	}
bogdanm	0:9b334a45a8ff	3909	}
bogdanm	0:9b334a45a8ff	3910	}
bogdanm	0:9b334a45a8ff	3911
bogdanm	0:9b334a45a8ff	3912	/**
bogdanm	0:9b334a45a8ff	3913	* @brief DMA I2C communication error callback.
bogdanm	0:9b334a45a8ff	3914	* @param hdma : DMA handle
bogdanm	0:9b334a45a8ff	3915	* @retval None
bogdanm	0:9b334a45a8ff	3916	*/
bogdanm	0:9b334a45a8ff	3917	static void I2C_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	3918	{
bogdanm	0:9b334a45a8ff	3919	I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	3920
bogdanm	0:9b334a45a8ff	3921	/* Disable Acknowledge */
bogdanm	0:9b334a45a8ff	3922	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
bogdanm	0:9b334a45a8ff	3923
bogdanm	0:9b334a45a8ff	3924	hi2c->XferCount = 0;
bogdanm	0:9b334a45a8ff	3925
bogdanm	0:9b334a45a8ff	3926	hi2c->State = HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3927
bogdanm	0:9b334a45a8ff	3928	hi2c->ErrorCode \|= HAL_I2C_ERROR_DMA;
bogdanm	0:9b334a45a8ff	3929
bogdanm	0:9b334a45a8ff	3930	HAL_I2C_ErrorCallback(hi2c);
bogdanm	0:9b334a45a8ff	3931	}
bogdanm	0:9b334a45a8ff	3932
bogdanm	0:9b334a45a8ff	3933	/**
bogdanm	0:9b334a45a8ff	3934	* @brief This function handles I2C Communication Timeout.
bogdanm	0:9b334a45a8ff	3935	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3936	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	3937	* @param Flag: specifies the I2C flag to check.
bogdanm	0:9b334a45a8ff	3938	* @param Status: The new Flag status (SET or RESET).
bogdanm	0:9b334a45a8ff	3939	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	3940	* @retval HAL status
bogdanm	0:9b334a45a8ff	3941	*/
bogdanm	0:9b334a45a8ff	3942	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	3943	{
bogdanm	0:9b334a45a8ff	3944	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	3945
bogdanm	0:9b334a45a8ff	3946	/* Wait until flag is set */
bogdanm	0:9b334a45a8ff	3947	if(Status == RESET)
bogdanm	0:9b334a45a8ff	3948	{
bogdanm	0:9b334a45a8ff	3949	while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
bogdanm	0:9b334a45a8ff	3950	{
bogdanm	0:9b334a45a8ff	3951	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	3952	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	3953	{
bogdanm	0:9b334a45a8ff	3954	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	3955	{
bogdanm	0:9b334a45a8ff	3956	hi2c->State= HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3957	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	3958	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	3959	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	3960	}
bogdanm	0:9b334a45a8ff	3961	}
bogdanm	0:9b334a45a8ff	3962	}
bogdanm	0:9b334a45a8ff	3963	}
bogdanm	0:9b334a45a8ff	3964	else
bogdanm	0:9b334a45a8ff	3965	{
bogdanm	0:9b334a45a8ff	3966	while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
bogdanm	0:9b334a45a8ff	3967	{
bogdanm	0:9b334a45a8ff	3968	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	3969	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	3970	{
bogdanm	0:9b334a45a8ff	3971	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	3972	{
bogdanm	0:9b334a45a8ff	3973	hi2c->State= HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	3974	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	3975	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	3976	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	3977	}
bogdanm	0:9b334a45a8ff	3978	}
bogdanm	0:9b334a45a8ff	3979	}
bogdanm	0:9b334a45a8ff	3980	}
bogdanm	0:9b334a45a8ff	3981	return HAL_OK;
bogdanm	0:9b334a45a8ff	3982	}
bogdanm	0:9b334a45a8ff	3983
bogdanm	0:9b334a45a8ff	3984	/**
bogdanm	0:9b334a45a8ff	3985	* @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
bogdanm	0:9b334a45a8ff	3986	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	3987	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	3988	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	3989	* @retval HAL status
bogdanm	0:9b334a45a8ff	3990	*/
bogdanm	0:9b334a45a8ff	3991	static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	3992	{
bogdanm	0:9b334a45a8ff	3993	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	3994
bogdanm	0:9b334a45a8ff	3995	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
bogdanm	0:9b334a45a8ff	3996	{
bogdanm	0:9b334a45a8ff	3997	/* Check if a NACK is detected */
bogdanm	0:9b334a45a8ff	3998	if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	3999	{
bogdanm	0:9b334a45a8ff	4000	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	4001	}
bogdanm	0:9b334a45a8ff	4002
bogdanm	0:9b334a45a8ff	4003	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	4004	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	4005	{
bogdanm	0:9b334a45a8ff	4006	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	4007	{
bogdanm	0:9b334a45a8ff	4008	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	4009	hi2c->State= HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	4010
bogdanm	0:9b334a45a8ff	4011	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	4012	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	4013
bogdanm	0:9b334a45a8ff	4014	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	4015	}
bogdanm	0:9b334a45a8ff	4016	}
bogdanm	0:9b334a45a8ff	4017	}
bogdanm	0:9b334a45a8ff	4018	return HAL_OK;
bogdanm	0:9b334a45a8ff	4019	}
bogdanm	0:9b334a45a8ff	4020
bogdanm	0:9b334a45a8ff	4021	/**
bogdanm	0:9b334a45a8ff	4022	* @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
bogdanm	0:9b334a45a8ff	4023	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4024	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	4025	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	4026	* @retval HAL status
bogdanm	0:9b334a45a8ff	4027	*/
bogdanm	0:9b334a45a8ff	4028	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	4029	{
bogdanm	0:9b334a45a8ff	4030	uint32_t tickstart = 0x00;
bogdanm	0:9b334a45a8ff	4031	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	4032
bogdanm	0:9b334a45a8ff	4033	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
bogdanm	0:9b334a45a8ff	4034	{
bogdanm	0:9b334a45a8ff	4035	/* Check if a NACK is detected */
bogdanm	0:9b334a45a8ff	4036	if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	4037	{
bogdanm	0:9b334a45a8ff	4038	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	4039	}
bogdanm	0:9b334a45a8ff	4040
bogdanm	0:9b334a45a8ff	4041	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	4042	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	4043	{
bogdanm	0:9b334a45a8ff	4044	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	4045	hi2c->State= HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	4046
bogdanm	0:9b334a45a8ff	4047	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	4048	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	4049
bogdanm	0:9b334a45a8ff	4050	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	4051	}
bogdanm	0:9b334a45a8ff	4052	}
bogdanm	0:9b334a45a8ff	4053	return HAL_OK;
bogdanm	0:9b334a45a8ff	4054	}
bogdanm	0:9b334a45a8ff	4055
bogdanm	0:9b334a45a8ff	4056	/**
bogdanm	0:9b334a45a8ff	4057	* @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
bogdanm	0:9b334a45a8ff	4058	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4059	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	4060	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	4061	* @retval HAL status
bogdanm	0:9b334a45a8ff	4062	*/
bogdanm	0:9b334a45a8ff	4063	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	4064	{
bogdanm	0:9b334a45a8ff	4065	uint32_t tickstart = 0x00;
bogdanm	0:9b334a45a8ff	4066	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	4067
bogdanm	0:9b334a45a8ff	4068	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
bogdanm	0:9b334a45a8ff	4069	{
mbed_official	113:b3775bf36a83	4070	/* Check if a NACK is detected */
mbed_official	113:b3775bf36a83	4071	if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
mbed_official	113:b3775bf36a83	4072	{
mbed_official	113:b3775bf36a83	4073	return HAL_ERROR;
mbed_official	113:b3775bf36a83	4074	}
bogdanm	0:9b334a45a8ff	4075	/* Check if a STOPF is detected */
bogdanm	0:9b334a45a8ff	4076	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
bogdanm	0:9b334a45a8ff	4077	{
bogdanm	0:9b334a45a8ff	4078	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	4079	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	4080
bogdanm	0:9b334a45a8ff	4081	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	4082	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	4083
bogdanm	0:9b334a45a8ff	4084	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
bogdanm	0:9b334a45a8ff	4085	hi2c->State= HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	4086
bogdanm	0:9b334a45a8ff	4087	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	4088	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	4089
bogdanm	0:9b334a45a8ff	4090	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	4091	}
bogdanm	0:9b334a45a8ff	4092
bogdanm	0:9b334a45a8ff	4093	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	4094	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	4095	{
bogdanm	0:9b334a45a8ff	4096	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	4097	hi2c->State= HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	4098
bogdanm	0:9b334a45a8ff	4099	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	4100	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	4101
bogdanm	0:9b334a45a8ff	4102	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	4103	}
bogdanm	0:9b334a45a8ff	4104	}
bogdanm	0:9b334a45a8ff	4105	return HAL_OK;
bogdanm	0:9b334a45a8ff	4106	}
bogdanm	0:9b334a45a8ff	4107
bogdanm	0:9b334a45a8ff	4108	/**
bogdanm	0:9b334a45a8ff	4109	* @brief This function handles Acknowledge failed detection during an I2C Communication.
bogdanm	0:9b334a45a8ff	4110	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	4111	* the configuration information for the specified I2C.
bogdanm	0:9b334a45a8ff	4112	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	4113	* @retval HAL status
bogdanm	0:9b334a45a8ff	4114	*/
bogdanm	0:9b334a45a8ff	4115	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	4116	{
bogdanm	0:9b334a45a8ff	4117	uint32_t tickstart = 0x00;
bogdanm	0:9b334a45a8ff	4118	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	4119
bogdanm	0:9b334a45a8ff	4120	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
bogdanm	0:9b334a45a8ff	4121	{
bogdanm	0:9b334a45a8ff	4122	/* Generate stop if necessary only in case of I2C peripheral in MASTER mode */
bogdanm	0:9b334a45a8ff	4123	if((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) \|\| (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
bogdanm	0:9b334a45a8ff	4124	\|\| (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))
bogdanm	0:9b334a45a8ff	4125	{
bogdanm	0:9b334a45a8ff	4126	/* No need to generate the STOP condition if AUTOEND mode is enabled */
bogdanm	0:9b334a45a8ff	4127	/* Generate the STOP condition only in case of SOFTEND mode is enabled */
bogdanm	0:9b334a45a8ff	4128	if((hi2c->Instance->CR2 & I2C_AUTOEND_MODE) != I2C_AUTOEND_MODE)
bogdanm	0:9b334a45a8ff	4129	{
bogdanm	0:9b334a45a8ff	4130	/* Generate Stop */
bogdanm	0:9b334a45a8ff	4131	hi2c->Instance->CR2 \|= I2C_CR2_STOP;
bogdanm	0:9b334a45a8ff	4132	}
bogdanm	0:9b334a45a8ff	4133	}
bogdanm	0:9b334a45a8ff	4134
bogdanm	0:9b334a45a8ff	4135	/* Wait until STOP Flag is reset */
bogdanm	0:9b334a45a8ff	4136	/* AutoEnd should be initiate after AF */
bogdanm	0:9b334a45a8ff	4137	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
bogdanm	0:9b334a45a8ff	4138	{
bogdanm	0:9b334a45a8ff	4139	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	4140	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	4141	{
bogdanm	0:9b334a45a8ff	4142	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	4143	{
bogdanm	0:9b334a45a8ff	4144	hi2c->State= HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	4145	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	4146	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	4147	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	4148	}
bogdanm	0:9b334a45a8ff	4149	}
bogdanm	0:9b334a45a8ff	4150	}
bogdanm	0:9b334a45a8ff	4151
bogdanm	0:9b334a45a8ff	4152	/* Clear NACKF Flag */
bogdanm	0:9b334a45a8ff	4153	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
bogdanm	0:9b334a45a8ff	4154
bogdanm	0:9b334a45a8ff	4155	/* Clear STOP Flag */
bogdanm	0:9b334a45a8ff	4156	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
bogdanm	0:9b334a45a8ff	4157
mbed_official	113:b3775bf36a83	4158	/* Flush TX register if not empty */
mbed_official	113:b3775bf36a83	4159	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
mbed_official	113:b3775bf36a83	4160	{
mbed_official	113:b3775bf36a83	4161	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
mbed_official	113:b3775bf36a83	4162	}
bogdanm	0:9b334a45a8ff	4163	/* Clear Configuration Register 2 */
bogdanm	0:9b334a45a8ff	4164	__I2C_RESET_CR2(hi2c);
bogdanm	0:9b334a45a8ff	4165
bogdanm	0:9b334a45a8ff	4166	hi2c->ErrorCode = HAL_I2C_ERROR_AF;
bogdanm	0:9b334a45a8ff	4167	hi2c->State= HAL_I2C_STATE_READY;
bogdanm	0:9b334a45a8ff	4168
bogdanm	0:9b334a45a8ff	4169	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	4170	__HAL_UNLOCK(hi2c);
bogdanm	0:9b334a45a8ff	4171
bogdanm	0:9b334a45a8ff	4172	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	4173	}
bogdanm	0:9b334a45a8ff	4174	return HAL_OK;
bogdanm	0:9b334a45a8ff	4175	}
bogdanm	0:9b334a45a8ff	4176
bogdanm	0:9b334a45a8ff	4177	/**
bogdanm	0:9b334a45a8ff	4178	* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
bogdanm	0:9b334a45a8ff	4179	* @param hi2c: I2C handle.
bogdanm	0:9b334a45a8ff	4180	* @param DevAddress: specifies the slave address to be programmed.
bogdanm	0:9b334a45a8ff	4181	* @param Size: specifies the number of bytes to be programmed.
bogdanm	0:9b334a45a8ff	4182	* This parameter must be a value between 0 and 255.
bogdanm	0:9b334a45a8ff	4183	* @param Mode: new state of the I2C START condition generation.
bogdanm	0:9b334a45a8ff	4184	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	4185	* @arg I2C_RELOAD_MODE: Enable Reload mode .
bogdanm	0:9b334a45a8ff	4186	* @arg I2C_AUTOEND_MODE: Enable Automatic end mode.
bogdanm	0:9b334a45a8ff	4187	* @arg I2C_SOFTEND_MODE: Enable Software end mode.
bogdanm	0:9b334a45a8ff	4188	* @param Request: new state of the I2C START condition generation.
bogdanm	0:9b334a45a8ff	4189	* This parameter can be one of the following values:
mbed_official	113:b3775bf36a83	4190	* @arg I2C_NO_STARTSTOP: Do not Generate stop and start condition.
bogdanm	0:9b334a45a8ff	4191	* @arg I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).
bogdanm	0:9b334a45a8ff	4192	* @arg I2C_GENERATE_START_READ: Generate Restart for read request.
bogdanm	0:9b334a45a8ff	4193	* @arg I2C_GENERATE_START_WRITE: Generate Restart for write request.
bogdanm	0:9b334a45a8ff	4194	* @retval None
bogdanm	0:9b334a45a8ff	4195	*/
bogdanm	0:9b334a45a8ff	4196	static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
bogdanm	0:9b334a45a8ff	4197	{
bogdanm	0:9b334a45a8ff	4198	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	4199
bogdanm	0:9b334a45a8ff	4200	/* Check the parameters */
bogdanm	0:9b334a45a8ff	4201	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
bogdanm	0:9b334a45a8ff	4202	assert_param(IS_TRANSFER_MODE(Mode));
bogdanm	0:9b334a45a8ff	4203	assert_param(IS_TRANSFER_REQUEST(Request));
bogdanm	0:9b334a45a8ff	4204
bogdanm	0:9b334a45a8ff	4205	/* Get the CR2 register value */
bogdanm	0:9b334a45a8ff	4206	tmpreg = hi2c->Instance->CR2;
bogdanm	0:9b334a45a8ff	4207
bogdanm	0:9b334a45a8ff	4208	/* clear tmpreg specific bits */
bogdanm	0:9b334a45a8ff	4209	tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD \| I2C_CR2_NBYTES \| I2C_CR2_RELOAD \| I2C_CR2_AUTOEND \| I2C_CR2_RD_WRN \| I2C_CR2_START \| I2C_CR2_STOP));
bogdanm	0:9b334a45a8ff	4210
bogdanm	0:9b334a45a8ff	4211	/* update tmpreg */
bogdanm	0:9b334a45a8ff	4212	tmpreg \|= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) \| (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) \| \
bogdanm	0:9b334a45a8ff	4213	(uint32_t)Mode \| (uint32_t)Request);
bogdanm	0:9b334a45a8ff	4214
bogdanm	0:9b334a45a8ff	4215	/* update CR2 register */
bogdanm	0:9b334a45a8ff	4216	hi2c->Instance->CR2 = tmpreg;
bogdanm	0:9b334a45a8ff	4217	}
bogdanm	0:9b334a45a8ff	4218
bogdanm	0:9b334a45a8ff	4219	/**
bogdanm	0:9b334a45a8ff	4220	* @}
bogdanm	0:9b334a45a8ff	4221	*/
bogdanm	0:9b334a45a8ff	4222
bogdanm	0:9b334a45a8ff	4223	/**
bogdanm	0:9b334a45a8ff	4224	* @}
bogdanm	0:9b334a45a8ff	4225	*/
bogdanm	0:9b334a45a8ff	4226
mbed_official	113:b3775bf36a83	4227	#endif /* HAL_I2C_MODULE_ENABLED */
mbed_official	113:b3775bf36a83	4228
bogdanm	0:9b334a45a8ff	4229	/**
bogdanm	0:9b334a45a8ff	4230	* @}
bogdanm	0:9b334a45a8ff	4231	*/
bogdanm	0:9b334a45a8ff	4232
bogdanm	0:9b334a45a8ff	4233	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	4234

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.c@113:b3775bf36a83, 2016-04-19 (annotated)

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