en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/stm32f410rx.h@25:ac5b0a371348, 2015-11-20 (annotated)

Committer:
mbed_official
Date:
Fri Nov 20 10:00:12 2015 +0000
Revision:
25:ac5b0a371348
Synchronized with git revision a4b777d8b25f9146e77396273dc9631c38583eb9



Full URL: https://github.com/mbedmicro/mbed/commit/a4b777d8b25f9146e77396273dc9631c38583eb9/



Added new Nucleo target - F410RB

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 25:ac5b0a371348 1 /**
mbed_official 25:ac5b0a371348 2 ******************************************************************************
mbed_official 25:ac5b0a371348 3 * @file stm32f410rx.h
mbed_official 25:ac5b0a371348 4 * @author MCD Application Team
mbed_official 25:ac5b0a371348 5 * @version V2.4.1
mbed_official 25:ac5b0a371348 6 * @date 09-October-2015
mbed_official 25:ac5b0a371348 7 * @brief CMSIS STM32F410Rx Device Peripheral Access Layer Header File.
mbed_official 25:ac5b0a371348 8 *
mbed_official 25:ac5b0a371348 9 * This file contains:
mbed_official 25:ac5b0a371348 10 * - Data structures and the address mapping for all peripherals
mbed_official 25:ac5b0a371348 11 * - Peripheral's registers declarations and bits definition
mbed_official 25:ac5b0a371348 12 * - Macros to access peripheral’s registers hardware
mbed_official 25:ac5b0a371348 13 *
mbed_official 25:ac5b0a371348 14 ******************************************************************************
mbed_official 25:ac5b0a371348 15 * @attention
mbed_official 25:ac5b0a371348 16 *
mbed_official 25:ac5b0a371348 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 25:ac5b0a371348 18 *
mbed_official 25:ac5b0a371348 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 25:ac5b0a371348 20 * are permitted provided that the following conditions are met:
mbed_official 25:ac5b0a371348 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 25:ac5b0a371348 22 * this list of conditions and the following disclaimer.
mbed_official 25:ac5b0a371348 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 25:ac5b0a371348 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 25:ac5b0a371348 25 * and/or other materials provided with the distribution.
mbed_official 25:ac5b0a371348 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 25:ac5b0a371348 27 * may be used to endorse or promote products derived from this software
mbed_official 25:ac5b0a371348 28 * without specific prior written permission.
mbed_official 25:ac5b0a371348 29 *
mbed_official 25:ac5b0a371348 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 25:ac5b0a371348 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 25:ac5b0a371348 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 25:ac5b0a371348 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 25:ac5b0a371348 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 25:ac5b0a371348 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 25:ac5b0a371348 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 25:ac5b0a371348 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 25:ac5b0a371348 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 25:ac5b0a371348 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 25:ac5b0a371348 40 *
mbed_official 25:ac5b0a371348 41 ******************************************************************************
mbed_official 25:ac5b0a371348 42 */
mbed_official 25:ac5b0a371348 43
mbed_official 25:ac5b0a371348 44 /** @addtogroup CMSIS
mbed_official 25:ac5b0a371348 45 * @{
mbed_official 25:ac5b0a371348 46 */
mbed_official 25:ac5b0a371348 47
mbed_official 25:ac5b0a371348 48 /** @addtogroup stm32f410xx
mbed_official 25:ac5b0a371348 49 * @{
mbed_official 25:ac5b0a371348 50 */
mbed_official 25:ac5b0a371348 51
mbed_official 25:ac5b0a371348 52 #ifndef __STM32F410xx_H
mbed_official 25:ac5b0a371348 53 #define __STM32F410xx_H
mbed_official 25:ac5b0a371348 54
mbed_official 25:ac5b0a371348 55 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 56 extern "C" {
mbed_official 25:ac5b0a371348 57 #endif /* __cplusplus */
mbed_official 25:ac5b0a371348 58
mbed_official 25:ac5b0a371348 59
mbed_official 25:ac5b0a371348 60 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 25:ac5b0a371348 61 * @{
mbed_official 25:ac5b0a371348 62 */
mbed_official 25:ac5b0a371348 63
mbed_official 25:ac5b0a371348 64 /**
mbed_official 25:ac5b0a371348 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
mbed_official 25:ac5b0a371348 66 */
mbed_official 25:ac5b0a371348 67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
mbed_official 25:ac5b0a371348 68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
mbed_official 25:ac5b0a371348 69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
mbed_official 25:ac5b0a371348 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 25:ac5b0a371348 71 #define __FPU_PRESENT 1 /*!< FPU present */
mbed_official 25:ac5b0a371348 72
mbed_official 25:ac5b0a371348 73 /**
mbed_official 25:ac5b0a371348 74 * @}
mbed_official 25:ac5b0a371348 75 */
mbed_official 25:ac5b0a371348 76
mbed_official 25:ac5b0a371348 77 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 25:ac5b0a371348 78 * @{
mbed_official 25:ac5b0a371348 79 */
mbed_official 25:ac5b0a371348 80
mbed_official 25:ac5b0a371348 81 /**
mbed_official 25:ac5b0a371348 82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
mbed_official 25:ac5b0a371348 83 * in @ref Library_configuration_section
mbed_official 25:ac5b0a371348 84 */
mbed_official 25:ac5b0a371348 85 typedef enum
mbed_official 25:ac5b0a371348 86 {
mbed_official 25:ac5b0a371348 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
mbed_official 25:ac5b0a371348 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 25:ac5b0a371348 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 25:ac5b0a371348 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 25:ac5b0a371348 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 25:ac5b0a371348 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 25:ac5b0a371348 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 25:ac5b0a371348 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 25:ac5b0a371348 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 25:ac5b0a371348 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 25:ac5b0a371348 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 25:ac5b0a371348 98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 25:ac5b0a371348 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
mbed_official 25:ac5b0a371348 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
mbed_official 25:ac5b0a371348 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 25:ac5b0a371348 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 25:ac5b0a371348 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 25:ac5b0a371348 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 25:ac5b0a371348 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 25:ac5b0a371348 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 25:ac5b0a371348 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 25:ac5b0a371348 108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
mbed_official 25:ac5b0a371348 109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
mbed_official 25:ac5b0a371348 110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
mbed_official 25:ac5b0a371348 111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
mbed_official 25:ac5b0a371348 112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
mbed_official 25:ac5b0a371348 113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
mbed_official 25:ac5b0a371348 114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
mbed_official 25:ac5b0a371348 115 ADC_IRQn = 18, /*!< ADC1 global Interrupts */
mbed_official 25:ac5b0a371348 116 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 25:ac5b0a371348 117 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
mbed_official 25:ac5b0a371348 118 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
mbed_official 25:ac5b0a371348 119 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
mbed_official 25:ac5b0a371348 120 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 25:ac5b0a371348 121 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 25:ac5b0a371348 122 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 25:ac5b0a371348 123 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 25:ac5b0a371348 124 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 25:ac5b0a371348 125 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 25:ac5b0a371348 126 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 25:ac5b0a371348 127 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 25:ac5b0a371348 128 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 25:ac5b0a371348 129 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 25:ac5b0a371348 130 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
mbed_official 25:ac5b0a371348 131 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
mbed_official 25:ac5b0a371348 132 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
mbed_official 25:ac5b0a371348 133 TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
mbed_official 25:ac5b0a371348 134 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
mbed_official 25:ac5b0a371348 135 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
mbed_official 25:ac5b0a371348 136 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
mbed_official 25:ac5b0a371348 137 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
mbed_official 25:ac5b0a371348 138 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
mbed_official 25:ac5b0a371348 139 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
mbed_official 25:ac5b0a371348 140 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
mbed_official 25:ac5b0a371348 141 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
mbed_official 25:ac5b0a371348 142 USART6_IRQn = 71, /*!< USART6 global interrupt */
mbed_official 25:ac5b0a371348 143 RNG_IRQn = 80, /*!< RNG global Interrupt */
mbed_official 25:ac5b0a371348 144 FPU_IRQn = 81, /*!< FPU global interrupt */
mbed_official 25:ac5b0a371348 145 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
mbed_official 25:ac5b0a371348 146 FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
mbed_official 25:ac5b0a371348 147 FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
mbed_official 25:ac5b0a371348 148 LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
mbed_official 25:ac5b0a371348 149 } IRQn_Type;
mbed_official 25:ac5b0a371348 150
mbed_official 25:ac5b0a371348 151 /**
mbed_official 25:ac5b0a371348 152 * @}
mbed_official 25:ac5b0a371348 153 */
mbed_official 25:ac5b0a371348 154
mbed_official 25:ac5b0a371348 155 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 25:ac5b0a371348 156 #include "system_stm32f4xx.h"
mbed_official 25:ac5b0a371348 157 #include <stdint.h>
mbed_official 25:ac5b0a371348 158
mbed_official 25:ac5b0a371348 159 /** @addtogroup Peripheral_registers_structures
mbed_official 25:ac5b0a371348 160 * @{
mbed_official 25:ac5b0a371348 161 */
mbed_official 25:ac5b0a371348 162
mbed_official 25:ac5b0a371348 163 /**
mbed_official 25:ac5b0a371348 164 * @brief Analog to Digital Converter
mbed_official 25:ac5b0a371348 165 */
mbed_official 25:ac5b0a371348 166
mbed_official 25:ac5b0a371348 167 typedef struct
mbed_official 25:ac5b0a371348 168 {
mbed_official 25:ac5b0a371348 169 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 170 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 171 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 172 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 173 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 174 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 175 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 176 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 177 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 178 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 179 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
mbed_official 25:ac5b0a371348 180 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
mbed_official 25:ac5b0a371348 181 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
mbed_official 25:ac5b0a371348 182 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
mbed_official 25:ac5b0a371348 183 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
mbed_official 25:ac5b0a371348 184 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
mbed_official 25:ac5b0a371348 185 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
mbed_official 25:ac5b0a371348 186 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
mbed_official 25:ac5b0a371348 187 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
mbed_official 25:ac5b0a371348 188 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
mbed_official 25:ac5b0a371348 189 } ADC_TypeDef;
mbed_official 25:ac5b0a371348 190
mbed_official 25:ac5b0a371348 191 typedef struct
mbed_official 25:ac5b0a371348 192 {
mbed_official 25:ac5b0a371348 193 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
mbed_official 25:ac5b0a371348 194 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
mbed_official 25:ac5b0a371348 195 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 25:ac5b0a371348 196 AND triple modes, Address offset: ADC1 base address + 0x308 */
mbed_official 25:ac5b0a371348 197 } ADC_Common_TypeDef;
mbed_official 25:ac5b0a371348 198
mbed_official 25:ac5b0a371348 199 /**
mbed_official 25:ac5b0a371348 200 * @brief CRC calculation unit
mbed_official 25:ac5b0a371348 201 */
mbed_official 25:ac5b0a371348 202
mbed_official 25:ac5b0a371348 203 typedef struct
mbed_official 25:ac5b0a371348 204 {
mbed_official 25:ac5b0a371348 205 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 206 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 207 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 25:ac5b0a371348 208 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 25:ac5b0a371348 209 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 210 } CRC_TypeDef;
mbed_official 25:ac5b0a371348 211
mbed_official 25:ac5b0a371348 212 /**
mbed_official 25:ac5b0a371348 213 * @brief Digital to Analog Converter
mbed_official 25:ac5b0a371348 214 */
mbed_official 25:ac5b0a371348 215
mbed_official 25:ac5b0a371348 216 typedef struct
mbed_official 25:ac5b0a371348 217 {
mbed_official 25:ac5b0a371348 218 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 219 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 220 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 221 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 222 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 223 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 224 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 225 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 226 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 227 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 228 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 25:ac5b0a371348 229 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 25:ac5b0a371348 230 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 25:ac5b0a371348 231 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 25:ac5b0a371348 232 } DAC_TypeDef;
mbed_official 25:ac5b0a371348 233
mbed_official 25:ac5b0a371348 234 /**
mbed_official 25:ac5b0a371348 235 * @brief Debug MCU
mbed_official 25:ac5b0a371348 236 */
mbed_official 25:ac5b0a371348 237
mbed_official 25:ac5b0a371348 238 typedef struct
mbed_official 25:ac5b0a371348 239 {
mbed_official 25:ac5b0a371348 240 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 241 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 242 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 243 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 244 }DBGMCU_TypeDef;
mbed_official 25:ac5b0a371348 245
mbed_official 25:ac5b0a371348 246
mbed_official 25:ac5b0a371348 247 /**
mbed_official 25:ac5b0a371348 248 * @brief DMA Controller
mbed_official 25:ac5b0a371348 249 */
mbed_official 25:ac5b0a371348 250
mbed_official 25:ac5b0a371348 251 typedef struct
mbed_official 25:ac5b0a371348 252 {
mbed_official 25:ac5b0a371348 253 __IO uint32_t CR; /*!< DMA stream x configuration register */
mbed_official 25:ac5b0a371348 254 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
mbed_official 25:ac5b0a371348 255 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
mbed_official 25:ac5b0a371348 256 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
mbed_official 25:ac5b0a371348 257 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
mbed_official 25:ac5b0a371348 258 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
mbed_official 25:ac5b0a371348 259 } DMA_Stream_TypeDef;
mbed_official 25:ac5b0a371348 260
mbed_official 25:ac5b0a371348 261 typedef struct
mbed_official 25:ac5b0a371348 262 {
mbed_official 25:ac5b0a371348 263 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 264 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 265 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 266 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 267 } DMA_TypeDef;
mbed_official 25:ac5b0a371348 268
mbed_official 25:ac5b0a371348 269
mbed_official 25:ac5b0a371348 270 /**
mbed_official 25:ac5b0a371348 271 * @brief External Interrupt/Event Controller
mbed_official 25:ac5b0a371348 272 */
mbed_official 25:ac5b0a371348 273
mbed_official 25:ac5b0a371348 274 typedef struct
mbed_official 25:ac5b0a371348 275 {
mbed_official 25:ac5b0a371348 276 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 277 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 278 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 279 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 280 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 281 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 282 } EXTI_TypeDef;
mbed_official 25:ac5b0a371348 283
mbed_official 25:ac5b0a371348 284 /**
mbed_official 25:ac5b0a371348 285 * @brief FLASH Registers
mbed_official 25:ac5b0a371348 286 */
mbed_official 25:ac5b0a371348 287
mbed_official 25:ac5b0a371348 288 typedef struct
mbed_official 25:ac5b0a371348 289 {
mbed_official 25:ac5b0a371348 290 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 291 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 292 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 293 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 294 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 295 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
mbed_official 25:ac5b0a371348 296 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 297 } FLASH_TypeDef;
mbed_official 25:ac5b0a371348 298
mbed_official 25:ac5b0a371348 299 /**
mbed_official 25:ac5b0a371348 300 * @brief General Purpose I/O
mbed_official 25:ac5b0a371348 301 */
mbed_official 25:ac5b0a371348 302
mbed_official 25:ac5b0a371348 303 typedef struct
mbed_official 25:ac5b0a371348 304 {
mbed_official 25:ac5b0a371348 305 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 306 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 307 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 308 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 309 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 310 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 311 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 312 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 313 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
mbed_official 25:ac5b0a371348 314 } GPIO_TypeDef;
mbed_official 25:ac5b0a371348 315
mbed_official 25:ac5b0a371348 316 /**
mbed_official 25:ac5b0a371348 317 * @brief System configuration controller
mbed_official 25:ac5b0a371348 318 */
mbed_official 25:ac5b0a371348 319
mbed_official 25:ac5b0a371348 320 typedef struct
mbed_official 25:ac5b0a371348 321 {
mbed_official 25:ac5b0a371348 322 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 323 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 324 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
mbed_official 25:ac5b0a371348 325 uint32_t RESERVED; /*!< Reserved, 0x18 */
mbed_official 25:ac5b0a371348 326 uint32_t CFGR2; /*!< Reserved, 0x1C */
mbed_official 25:ac5b0a371348 327 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 328 uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
mbed_official 25:ac5b0a371348 329 __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
mbed_official 25:ac5b0a371348 330 } SYSCFG_TypeDef;
mbed_official 25:ac5b0a371348 331
mbed_official 25:ac5b0a371348 332 /**
mbed_official 25:ac5b0a371348 333 * @brief Inter-integrated Circuit Interface
mbed_official 25:ac5b0a371348 334 */
mbed_official 25:ac5b0a371348 335
mbed_official 25:ac5b0a371348 336 typedef struct
mbed_official 25:ac5b0a371348 337 {
mbed_official 25:ac5b0a371348 338 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 339 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 340 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 341 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 342 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 343 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 344 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 345 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 346 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 347 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 348 } I2C_TypeDef;
mbed_official 25:ac5b0a371348 349
mbed_official 25:ac5b0a371348 350 /**
mbed_official 25:ac5b0a371348 351 * @brief Inter-integrated Circuit Interface
mbed_official 25:ac5b0a371348 352 */
mbed_official 25:ac5b0a371348 353
mbed_official 25:ac5b0a371348 354 typedef struct
mbed_official 25:ac5b0a371348 355 {
mbed_official 25:ac5b0a371348 356 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 357 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 358 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 359 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 360 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 361 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 362 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 363 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 364 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 365 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 366 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
mbed_official 25:ac5b0a371348 367 } FMPI2C_TypeDef;
mbed_official 25:ac5b0a371348 368
mbed_official 25:ac5b0a371348 369 /**
mbed_official 25:ac5b0a371348 370 * @brief Independent WATCHDOG
mbed_official 25:ac5b0a371348 371 */
mbed_official 25:ac5b0a371348 372
mbed_official 25:ac5b0a371348 373 typedef struct
mbed_official 25:ac5b0a371348 374 {
mbed_official 25:ac5b0a371348 375 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 376 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 377 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 378 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 379 } IWDG_TypeDef;
mbed_official 25:ac5b0a371348 380
mbed_official 25:ac5b0a371348 381 /**
mbed_official 25:ac5b0a371348 382 * @brief Power Control
mbed_official 25:ac5b0a371348 383 */
mbed_official 25:ac5b0a371348 384
mbed_official 25:ac5b0a371348 385 typedef struct
mbed_official 25:ac5b0a371348 386 {
mbed_official 25:ac5b0a371348 387 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 388 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 389 } PWR_TypeDef;
mbed_official 25:ac5b0a371348 390
mbed_official 25:ac5b0a371348 391 /**
mbed_official 25:ac5b0a371348 392 * @brief Reset and Clock Control
mbed_official 25:ac5b0a371348 393 */
mbed_official 25:ac5b0a371348 394
mbed_official 25:ac5b0a371348 395 typedef struct
mbed_official 25:ac5b0a371348 396 {
mbed_official 25:ac5b0a371348 397 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 398 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 399 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 400 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 401 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 402 uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */
mbed_official 25:ac5b0a371348 403 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 404 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 405 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
mbed_official 25:ac5b0a371348 406 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
mbed_official 25:ac5b0a371348 407 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
mbed_official 25:ac5b0a371348 408 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
mbed_official 25:ac5b0a371348 409 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
mbed_official 25:ac5b0a371348 410 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
mbed_official 25:ac5b0a371348 411 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
mbed_official 25:ac5b0a371348 412 uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */
mbed_official 25:ac5b0a371348 413 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
mbed_official 25:ac5b0a371348 414 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
mbed_official 25:ac5b0a371348 415 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
mbed_official 25:ac5b0a371348 416 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
mbed_official 25:ac5b0a371348 417 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
mbed_official 25:ac5b0a371348 418 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
mbed_official 25:ac5b0a371348 419 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
mbed_official 25:ac5b0a371348 420 uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */
mbed_official 25:ac5b0a371348 421 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
mbed_official 25:ac5b0a371348 422 __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
mbed_official 25:ac5b0a371348 423 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
mbed_official 25:ac5b0a371348 424
mbed_official 25:ac5b0a371348 425 } RCC_TypeDef;
mbed_official 25:ac5b0a371348 426
mbed_official 25:ac5b0a371348 427 /**
mbed_official 25:ac5b0a371348 428 * @brief Real-Time Clock
mbed_official 25:ac5b0a371348 429 */
mbed_official 25:ac5b0a371348 430
mbed_official 25:ac5b0a371348 431 typedef struct
mbed_official 25:ac5b0a371348 432 {
mbed_official 25:ac5b0a371348 433 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 434 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 435 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 436 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 437 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 438 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 439 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 440 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 441 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 442 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 443 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 25:ac5b0a371348 444 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 25:ac5b0a371348 445 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 25:ac5b0a371348 446 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 25:ac5b0a371348 447 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 25:ac5b0a371348 448 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 25:ac5b0a371348 449 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 25:ac5b0a371348 450 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 25:ac5b0a371348 451 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 25:ac5b0a371348 452 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 25:ac5b0a371348 453 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
mbed_official 25:ac5b0a371348 454 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 25:ac5b0a371348 455 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 25:ac5b0a371348 456 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 25:ac5b0a371348 457 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 25:ac5b0a371348 458 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 25:ac5b0a371348 459 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 25:ac5b0a371348 460 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 25:ac5b0a371348 461 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 25:ac5b0a371348 462 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 25:ac5b0a371348 463 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 25:ac5b0a371348 464 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 25:ac5b0a371348 465 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 25:ac5b0a371348 466 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 25:ac5b0a371348 467 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 25:ac5b0a371348 468 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 25:ac5b0a371348 469 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
mbed_official 25:ac5b0a371348 470 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
mbed_official 25:ac5b0a371348 471 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
mbed_official 25:ac5b0a371348 472 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
mbed_official 25:ac5b0a371348 473 } RTC_TypeDef;
mbed_official 25:ac5b0a371348 474
mbed_official 25:ac5b0a371348 475 /**
mbed_official 25:ac5b0a371348 476 * @brief Serial Peripheral Interface
mbed_official 25:ac5b0a371348 477 */
mbed_official 25:ac5b0a371348 478
mbed_official 25:ac5b0a371348 479 typedef struct
mbed_official 25:ac5b0a371348 480 {
mbed_official 25:ac5b0a371348 481 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 25:ac5b0a371348 482 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 483 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 484 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 485 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 25:ac5b0a371348 486 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 25:ac5b0a371348 487 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 25:ac5b0a371348 488 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 489 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 490 } SPI_TypeDef;
mbed_official 25:ac5b0a371348 491
mbed_official 25:ac5b0a371348 492 /**
mbed_official 25:ac5b0a371348 493 * @brief TIM
mbed_official 25:ac5b0a371348 494 */
mbed_official 25:ac5b0a371348 495
mbed_official 25:ac5b0a371348 496 typedef struct
mbed_official 25:ac5b0a371348 497 {
mbed_official 25:ac5b0a371348 498 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 499 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 500 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 501 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 502 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 503 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 504 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 505 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 506 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 507 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 508 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 25:ac5b0a371348 509 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 25:ac5b0a371348 510 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 25:ac5b0a371348 511 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 25:ac5b0a371348 512 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 25:ac5b0a371348 513 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 25:ac5b0a371348 514 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 25:ac5b0a371348 515 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 25:ac5b0a371348 516 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 25:ac5b0a371348 517 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 25:ac5b0a371348 518 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 25:ac5b0a371348 519 } TIM_TypeDef;
mbed_official 25:ac5b0a371348 520
mbed_official 25:ac5b0a371348 521 /**
mbed_official 25:ac5b0a371348 522 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 25:ac5b0a371348 523 */
mbed_official 25:ac5b0a371348 524
mbed_official 25:ac5b0a371348 525 typedef struct
mbed_official 25:ac5b0a371348 526 {
mbed_official 25:ac5b0a371348 527 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 528 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 529 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 530 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 531 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 532 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 533 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 534 } USART_TypeDef;
mbed_official 25:ac5b0a371348 535
mbed_official 25:ac5b0a371348 536 /**
mbed_official 25:ac5b0a371348 537 * @brief Window WATCHDOG
mbed_official 25:ac5b0a371348 538 */
mbed_official 25:ac5b0a371348 539
mbed_official 25:ac5b0a371348 540 typedef struct
mbed_official 25:ac5b0a371348 541 {
mbed_official 25:ac5b0a371348 542 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 543 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 544 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 545 } WWDG_TypeDef;
mbed_official 25:ac5b0a371348 546
mbed_official 25:ac5b0a371348 547
mbed_official 25:ac5b0a371348 548 /**
mbed_official 25:ac5b0a371348 549 * @brief RNG
mbed_official 25:ac5b0a371348 550 */
mbed_official 25:ac5b0a371348 551
mbed_official 25:ac5b0a371348 552 typedef struct
mbed_official 25:ac5b0a371348 553 {
mbed_official 25:ac5b0a371348 554 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 555 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 556 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 557 } RNG_TypeDef;
mbed_official 25:ac5b0a371348 558
mbed_official 25:ac5b0a371348 559
mbed_official 25:ac5b0a371348 560 /**
mbed_official 25:ac5b0a371348 561 * @brief LPTIMER
mbed_official 25:ac5b0a371348 562 */
mbed_official 25:ac5b0a371348 563 typedef struct
mbed_official 25:ac5b0a371348 564 {
mbed_official 25:ac5b0a371348 565 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 566 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 567 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 568 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 569 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 570 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 571 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 572 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 573 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 574 } LPTIM_TypeDef;
mbed_official 25:ac5b0a371348 575
mbed_official 25:ac5b0a371348 576 /**
mbed_official 25:ac5b0a371348 577 * @brief Peripheral_memory_map
mbed_official 25:ac5b0a371348 578 */
mbed_official 25:ac5b0a371348 579 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
mbed_official 25:ac5b0a371348 580 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(32 KB) base address in the alias region */
mbed_official 25:ac5b0a371348 581 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 25:ac5b0a371348 582 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(32 KB) base address in the bit-band region */
mbed_official 25:ac5b0a371348 583 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 25:ac5b0a371348 584 #define FLASH_END ((uint32_t)0x0801FFFF) /*!< FLASH end address */
mbed_official 25:ac5b0a371348 585
mbed_official 25:ac5b0a371348 586 /* Legacy defines */
mbed_official 25:ac5b0a371348 587 #define SRAM_BASE SRAM1_BASE
mbed_official 25:ac5b0a371348 588 #define SRAM_BB_BASE SRAM1_BB_BASE
mbed_official 25:ac5b0a371348 589
mbed_official 25:ac5b0a371348 590 /*!< Peripheral memory map */
mbed_official 25:ac5b0a371348 591 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 25:ac5b0a371348 592 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 25:ac5b0a371348 593 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 25:ac5b0a371348 594
mbed_official 25:ac5b0a371348 595 /*!< APB1 peripherals */
mbed_official 25:ac5b0a371348 596 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
mbed_official 25:ac5b0a371348 597 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
mbed_official 25:ac5b0a371348 598 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
mbed_official 25:ac5b0a371348 599 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
mbed_official 25:ac5b0a371348 600 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
mbed_official 25:ac5b0a371348 601 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
mbed_official 25:ac5b0a371348 602 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
mbed_official 25:ac5b0a371348 603 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
mbed_official 25:ac5b0a371348 604 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
mbed_official 25:ac5b0a371348 605 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
mbed_official 25:ac5b0a371348 606 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
mbed_official 25:ac5b0a371348 607 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000)
mbed_official 25:ac5b0a371348 608 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
mbed_official 25:ac5b0a371348 609 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
mbed_official 25:ac5b0a371348 610 /*!< APB2 peripherals */
mbed_official 25:ac5b0a371348 611 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
mbed_official 25:ac5b0a371348 612 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
mbed_official 25:ac5b0a371348 613 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
mbed_official 25:ac5b0a371348 614 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
mbed_official 25:ac5b0a371348 615 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
mbed_official 25:ac5b0a371348 616 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
mbed_official 25:ac5b0a371348 617 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
mbed_official 25:ac5b0a371348 618 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
mbed_official 25:ac5b0a371348 619 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
mbed_official 25:ac5b0a371348 620 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
mbed_official 25:ac5b0a371348 621 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
mbed_official 25:ac5b0a371348 622
mbed_official 25:ac5b0a371348 623 /*!< AHB1 peripherals */
mbed_official 25:ac5b0a371348 624 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
mbed_official 25:ac5b0a371348 625 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
mbed_official 25:ac5b0a371348 626 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
mbed_official 25:ac5b0a371348 627 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
mbed_official 25:ac5b0a371348 628 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
mbed_official 25:ac5b0a371348 629 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
mbed_official 25:ac5b0a371348 630 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
mbed_official 25:ac5b0a371348 631 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
mbed_official 25:ac5b0a371348 632 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
mbed_official 25:ac5b0a371348 633 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
mbed_official 25:ac5b0a371348 634 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
mbed_official 25:ac5b0a371348 635 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
mbed_official 25:ac5b0a371348 636 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
mbed_official 25:ac5b0a371348 637 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
mbed_official 25:ac5b0a371348 638 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
mbed_official 25:ac5b0a371348 639 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
mbed_official 25:ac5b0a371348 640 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
mbed_official 25:ac5b0a371348 641 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
mbed_official 25:ac5b0a371348 642 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
mbed_official 25:ac5b0a371348 643 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
mbed_official 25:ac5b0a371348 644 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
mbed_official 25:ac5b0a371348 645 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
mbed_official 25:ac5b0a371348 646 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
mbed_official 25:ac5b0a371348 647 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
mbed_official 25:ac5b0a371348 648 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
mbed_official 25:ac5b0a371348 649 #define RNG_BASE (PERIPH_BASE + 0x80000)
mbed_official 25:ac5b0a371348 650
mbed_official 25:ac5b0a371348 651 /* Debug MCU registers base address */
mbed_official 25:ac5b0a371348 652 #define DBGMCU_BASE ((uint32_t )0xE0042000)
mbed_official 25:ac5b0a371348 653
mbed_official 25:ac5b0a371348 654 /**
mbed_official 25:ac5b0a371348 655 * @}
mbed_official 25:ac5b0a371348 656 */
mbed_official 25:ac5b0a371348 657
mbed_official 25:ac5b0a371348 658 /** @addtogroup Peripheral_declaration
mbed_official 25:ac5b0a371348 659 * @{
mbed_official 25:ac5b0a371348 660 */
mbed_official 25:ac5b0a371348 661 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official 25:ac5b0a371348 662 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 25:ac5b0a371348 663 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 25:ac5b0a371348 664 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 25:ac5b0a371348 665 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 25:ac5b0a371348 666 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 25:ac5b0a371348 667 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 25:ac5b0a371348 668 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 25:ac5b0a371348 669 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 25:ac5b0a371348 670 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
mbed_official 25:ac5b0a371348 671 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
mbed_official 25:ac5b0a371348 672 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 25:ac5b0a371348 673 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 25:ac5b0a371348 674 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 25:ac5b0a371348 675 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 25:ac5b0a371348 676 #define USART6 ((USART_TypeDef *) USART6_BASE)
mbed_official 25:ac5b0a371348 677 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 25:ac5b0a371348 678 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 25:ac5b0a371348 679 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 25:ac5b0a371348 680 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 25:ac5b0a371348 681 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 25:ac5b0a371348 682 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official 25:ac5b0a371348 683 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
mbed_official 25:ac5b0a371348 684 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
mbed_official 25:ac5b0a371348 685 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 25:ac5b0a371348 686 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 25:ac5b0a371348 687 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 25:ac5b0a371348 688 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 25:ac5b0a371348 689 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 25:ac5b0a371348 690 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 25:ac5b0a371348 691 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 25:ac5b0a371348 692 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 25:ac5b0a371348 693 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
mbed_official 25:ac5b0a371348 694 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
mbed_official 25:ac5b0a371348 695 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
mbed_official 25:ac5b0a371348 696 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
mbed_official 25:ac5b0a371348 697 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
mbed_official 25:ac5b0a371348 698 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
mbed_official 25:ac5b0a371348 699 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
mbed_official 25:ac5b0a371348 700 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
mbed_official 25:ac5b0a371348 701 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 25:ac5b0a371348 702 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
mbed_official 25:ac5b0a371348 703 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
mbed_official 25:ac5b0a371348 704 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
mbed_official 25:ac5b0a371348 705 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
mbed_official 25:ac5b0a371348 706 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
mbed_official 25:ac5b0a371348 707 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
mbed_official 25:ac5b0a371348 708 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
mbed_official 25:ac5b0a371348 709 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
mbed_official 25:ac5b0a371348 710 #define RNG ((RNG_TypeDef *) RNG_BASE)
mbed_official 25:ac5b0a371348 711
mbed_official 25:ac5b0a371348 712 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 25:ac5b0a371348 713
mbed_official 25:ac5b0a371348 714 /**
mbed_official 25:ac5b0a371348 715 * @}
mbed_official 25:ac5b0a371348 716 */
mbed_official 25:ac5b0a371348 717
mbed_official 25:ac5b0a371348 718 /** @addtogroup Exported_constants
mbed_official 25:ac5b0a371348 719 * @{
mbed_official 25:ac5b0a371348 720 */
mbed_official 25:ac5b0a371348 721
mbed_official 25:ac5b0a371348 722 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 25:ac5b0a371348 723 * @{
mbed_official 25:ac5b0a371348 724 */
mbed_official 25:ac5b0a371348 725
mbed_official 25:ac5b0a371348 726 /******************************************************************************/
mbed_official 25:ac5b0a371348 727 /* Peripheral Registers_Bits_Definition */
mbed_official 25:ac5b0a371348 728 /******************************************************************************/
mbed_official 25:ac5b0a371348 729
mbed_official 25:ac5b0a371348 730 /******************************************************************************/
mbed_official 25:ac5b0a371348 731 /* */
mbed_official 25:ac5b0a371348 732 /* Analog to Digital Converter */
mbed_official 25:ac5b0a371348 733 /* */
mbed_official 25:ac5b0a371348 734 /******************************************************************************/
mbed_official 25:ac5b0a371348 735 /******************** Bit definition for ADC_SR register ********************/
mbed_official 25:ac5b0a371348 736 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
mbed_official 25:ac5b0a371348 737 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
mbed_official 25:ac5b0a371348 738 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
mbed_official 25:ac5b0a371348 739 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
mbed_official 25:ac5b0a371348 740 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
mbed_official 25:ac5b0a371348 741 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
mbed_official 25:ac5b0a371348 742
mbed_official 25:ac5b0a371348 743 /******************* Bit definition for ADC_CR1 register ********************/
mbed_official 25:ac5b0a371348 744 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 25:ac5b0a371348 745 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 746 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 747 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 748 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 749 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 750 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
mbed_official 25:ac5b0a371348 751 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
mbed_official 25:ac5b0a371348 752 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
mbed_official 25:ac5b0a371348 753 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
mbed_official 25:ac5b0a371348 754 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
mbed_official 25:ac5b0a371348 755 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
mbed_official 25:ac5b0a371348 756 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
mbed_official 25:ac5b0a371348 757 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
mbed_official 25:ac5b0a371348 758 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
mbed_official 25:ac5b0a371348 759 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 760 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 761 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 762 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
mbed_official 25:ac5b0a371348 763 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
mbed_official 25:ac5b0a371348 764 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
mbed_official 25:ac5b0a371348 765 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 766 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 767 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
mbed_official 25:ac5b0a371348 768
mbed_official 25:ac5b0a371348 769 /******************* Bit definition for ADC_CR2 register ********************/
mbed_official 25:ac5b0a371348 770 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
mbed_official 25:ac5b0a371348 771 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
mbed_official 25:ac5b0a371348 772 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
mbed_official 25:ac5b0a371348 773 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
mbed_official 25:ac5b0a371348 774 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
mbed_official 25:ac5b0a371348 775 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
mbed_official 25:ac5b0a371348 776 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
mbed_official 25:ac5b0a371348 777 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 778 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 779 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 780 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 781 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
mbed_official 25:ac5b0a371348 782 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 783 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 784 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
mbed_official 25:ac5b0a371348 785 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
mbed_official 25:ac5b0a371348 786 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 787 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 788 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 789 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 790 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
mbed_official 25:ac5b0a371348 791 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 792 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 793 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
mbed_official 25:ac5b0a371348 794
mbed_official 25:ac5b0a371348 795 /****************** Bit definition for ADC_SMPR1 register *******************/
mbed_official 25:ac5b0a371348 796 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
mbed_official 25:ac5b0a371348 797 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 798 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 799 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 800 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
mbed_official 25:ac5b0a371348 801 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 802 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 803 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 804 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
mbed_official 25:ac5b0a371348 805 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 806 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 807 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 808 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
mbed_official 25:ac5b0a371348 809 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 810 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 811 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 812 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
mbed_official 25:ac5b0a371348 813 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 814 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 815 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 816 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
mbed_official 25:ac5b0a371348 817 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 818 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 819 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 820 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
mbed_official 25:ac5b0a371348 821 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 822 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 823 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 824 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
mbed_official 25:ac5b0a371348 825 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 826 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 827 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 828 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
mbed_official 25:ac5b0a371348 829 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 830 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 831 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 832
mbed_official 25:ac5b0a371348 833 /****************** Bit definition for ADC_SMPR2 register *******************/
mbed_official 25:ac5b0a371348 834 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
mbed_official 25:ac5b0a371348 835 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 836 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 837 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 838 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
mbed_official 25:ac5b0a371348 839 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 840 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 841 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 842 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
mbed_official 25:ac5b0a371348 843 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 844 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 845 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 846 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
mbed_official 25:ac5b0a371348 847 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 848 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 849 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 850 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
mbed_official 25:ac5b0a371348 851 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 852 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 853 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 854 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
mbed_official 25:ac5b0a371348 855 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 856 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 857 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 858 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
mbed_official 25:ac5b0a371348 859 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 860 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 861 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 862 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
mbed_official 25:ac5b0a371348 863 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 864 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 865 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 866 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
mbed_official 25:ac5b0a371348 867 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 868 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 869 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 870 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
mbed_official 25:ac5b0a371348 871 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 872 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 873 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 874
mbed_official 25:ac5b0a371348 875 /****************** Bit definition for ADC_JOFR1 register *******************/
mbed_official 25:ac5b0a371348 876 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
mbed_official 25:ac5b0a371348 877
mbed_official 25:ac5b0a371348 878 /****************** Bit definition for ADC_JOFR2 register *******************/
mbed_official 25:ac5b0a371348 879 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
mbed_official 25:ac5b0a371348 880
mbed_official 25:ac5b0a371348 881 /****************** Bit definition for ADC_JOFR3 register *******************/
mbed_official 25:ac5b0a371348 882 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
mbed_official 25:ac5b0a371348 883
mbed_official 25:ac5b0a371348 884 /****************** Bit definition for ADC_JOFR4 register *******************/
mbed_official 25:ac5b0a371348 885 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
mbed_official 25:ac5b0a371348 886
mbed_official 25:ac5b0a371348 887 /******************* Bit definition for ADC_HTR register ********************/
mbed_official 25:ac5b0a371348 888 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
mbed_official 25:ac5b0a371348 889
mbed_official 25:ac5b0a371348 890 /******************* Bit definition for ADC_LTR register ********************/
mbed_official 25:ac5b0a371348 891 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
mbed_official 25:ac5b0a371348 892
mbed_official 25:ac5b0a371348 893 /******************* Bit definition for ADC_SQR1 register *******************/
mbed_official 25:ac5b0a371348 894 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 895 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 896 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 897 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 898 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 899 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 900 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 901 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 902 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 903 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 904 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 905 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 906 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 907 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 908 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 909 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 910 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 911 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 912 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 913 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 914 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 915 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 916 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 917 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 918 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
mbed_official 25:ac5b0a371348 919 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 920 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 921 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 922 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 923
mbed_official 25:ac5b0a371348 924 /******************* Bit definition for ADC_SQR2 register *******************/
mbed_official 25:ac5b0a371348 925 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 926 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 927 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 928 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 929 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 930 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 931 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 932 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 933 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 934 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 935 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 936 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 937 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 938 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 939 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 940 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 941 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 942 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 943 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 944 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 945 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 946 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 947 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 948 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 949 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 950 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 951 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 952 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 953 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 954 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 955 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 956 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 957 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 958 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 959 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 960 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 961
mbed_official 25:ac5b0a371348 962 /******************* Bit definition for ADC_SQR3 register *******************/
mbed_official 25:ac5b0a371348 963 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
mbed_official 25:ac5b0a371348 964 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 965 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 966 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 967 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 968 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 969 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
mbed_official 25:ac5b0a371348 970 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 971 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 972 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 973 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 974 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 975 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
mbed_official 25:ac5b0a371348 976 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 977 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 978 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 979 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 980 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 981 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 982 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 983 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 984 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 985 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 986 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 987 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 988 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 989 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 990 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 991 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 992 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 993 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
mbed_official 25:ac5b0a371348 994 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 995 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 996 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 997 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 998 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 999
mbed_official 25:ac5b0a371348 1000 /******************* Bit definition for ADC_JSQR register *******************/
mbed_official 25:ac5b0a371348 1001 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
mbed_official 25:ac5b0a371348 1002 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 1003 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 1004 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 1005 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 1006 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 1007 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
mbed_official 25:ac5b0a371348 1008 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 1009 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 1010 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 1011 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 1012 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 1013 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
mbed_official 25:ac5b0a371348 1014 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 1015 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 1016 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 1017 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 1018 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 1019 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
mbed_official 25:ac5b0a371348 1020 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 1021 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 1022 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 1023 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 1024 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 1025 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
mbed_official 25:ac5b0a371348 1026 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 1027 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 1028
mbed_official 25:ac5b0a371348 1029 /******************* Bit definition for ADC_JDR1 register *******************/
mbed_official 25:ac5b0a371348 1030 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 25:ac5b0a371348 1031
mbed_official 25:ac5b0a371348 1032 /******************* Bit definition for ADC_JDR2 register *******************/
mbed_official 25:ac5b0a371348 1033 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 25:ac5b0a371348 1034
mbed_official 25:ac5b0a371348 1035 /******************* Bit definition for ADC_JDR3 register *******************/
mbed_official 25:ac5b0a371348 1036 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 25:ac5b0a371348 1037
mbed_official 25:ac5b0a371348 1038 /******************* Bit definition for ADC_JDR4 register *******************/
mbed_official 25:ac5b0a371348 1039 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 25:ac5b0a371348 1040
mbed_official 25:ac5b0a371348 1041 /******************** Bit definition for ADC_DR register ********************/
mbed_official 25:ac5b0a371348 1042 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
mbed_official 25:ac5b0a371348 1043 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
mbed_official 25:ac5b0a371348 1044
mbed_official 25:ac5b0a371348 1045 /******************* Bit definition for ADC_CSR register ********************/
mbed_official 25:ac5b0a371348 1046 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
mbed_official 25:ac5b0a371348 1047 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
mbed_official 25:ac5b0a371348 1048 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
mbed_official 25:ac5b0a371348 1049 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
mbed_official 25:ac5b0a371348 1050 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
mbed_official 25:ac5b0a371348 1051 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
mbed_official 25:ac5b0a371348 1052 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
mbed_official 25:ac5b0a371348 1053 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
mbed_official 25:ac5b0a371348 1054 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
mbed_official 25:ac5b0a371348 1055 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
mbed_official 25:ac5b0a371348 1056 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
mbed_official 25:ac5b0a371348 1057 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
mbed_official 25:ac5b0a371348 1058 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
mbed_official 25:ac5b0a371348 1059 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
mbed_official 25:ac5b0a371348 1060 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
mbed_official 25:ac5b0a371348 1061 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
mbed_official 25:ac5b0a371348 1062 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
mbed_official 25:ac5b0a371348 1063 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
mbed_official 25:ac5b0a371348 1064
mbed_official 25:ac5b0a371348 1065 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 25:ac5b0a371348 1066 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
mbed_official 25:ac5b0a371348 1067 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 1068 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 1069 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 1070 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 1071 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 1072 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
mbed_official 25:ac5b0a371348 1073 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 1074 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 1075 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 1076 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 1077 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
mbed_official 25:ac5b0a371348 1078 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
mbed_official 25:ac5b0a371348 1079 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 1080 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 1081 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
mbed_official 25:ac5b0a371348 1082 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 1083 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 1084 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
mbed_official 25:ac5b0a371348 1085 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
mbed_official 25:ac5b0a371348 1086
mbed_official 25:ac5b0a371348 1087 /******************* Bit definition for ADC_CDR register ********************/
mbed_official 25:ac5b0a371348 1088 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
mbed_official 25:ac5b0a371348 1089 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
mbed_official 25:ac5b0a371348 1090
mbed_official 25:ac5b0a371348 1091 /******************************************************************************/
mbed_official 25:ac5b0a371348 1092 /* */
mbed_official 25:ac5b0a371348 1093 /* CRC calculation unit */
mbed_official 25:ac5b0a371348 1094 /* */
mbed_official 25:ac5b0a371348 1095 /******************************************************************************/
mbed_official 25:ac5b0a371348 1096 /******************* Bit definition for CRC_DR register *********************/
mbed_official 25:ac5b0a371348 1097 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 25:ac5b0a371348 1098
mbed_official 25:ac5b0a371348 1099
mbed_official 25:ac5b0a371348 1100 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 25:ac5b0a371348 1101 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 25:ac5b0a371348 1102
mbed_official 25:ac5b0a371348 1103
mbed_official 25:ac5b0a371348 1104 /******************** Bit definition for CRC_CR register ********************/
mbed_official 25:ac5b0a371348 1105 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
mbed_official 25:ac5b0a371348 1106
mbed_official 25:ac5b0a371348 1107 /******************************************************************************/
mbed_official 25:ac5b0a371348 1108 /* */
mbed_official 25:ac5b0a371348 1109 /* Debug MCU */
mbed_official 25:ac5b0a371348 1110 /* */
mbed_official 25:ac5b0a371348 1111 /******************************************************************************/
mbed_official 25:ac5b0a371348 1112
mbed_official 25:ac5b0a371348 1113 /******************************************************************************/
mbed_official 25:ac5b0a371348 1114 /* */
mbed_official 25:ac5b0a371348 1115 /* DMA Controller */
mbed_official 25:ac5b0a371348 1116 /* */
mbed_official 25:ac5b0a371348 1117 /******************************************************************************/
mbed_official 25:ac5b0a371348 1118 /******************** Bits definition for DMA_SxCR register *****************/
mbed_official 25:ac5b0a371348 1119 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
mbed_official 25:ac5b0a371348 1120 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 1121 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 1122 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 1123 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
mbed_official 25:ac5b0a371348 1124 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 1125 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 1126 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
mbed_official 25:ac5b0a371348 1127 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 1128 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 1129 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 1130 #define DMA_SxCR_CT ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 1131 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 1132 #define DMA_SxCR_PL ((uint32_t)0x00030000)
mbed_official 25:ac5b0a371348 1133 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1134 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 1135 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 1136 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
mbed_official 25:ac5b0a371348 1137 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 1138 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 1139 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
mbed_official 25:ac5b0a371348 1140 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1141 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 1142 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1143 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1144 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1145 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
mbed_official 25:ac5b0a371348 1146 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1147 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1148 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1149 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1150 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1151 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1152 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1153 #define DMA_SxCR_EN ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1154
mbed_official 25:ac5b0a371348 1155 /******************** Bits definition for DMA_SxCNDTR register **************/
mbed_official 25:ac5b0a371348 1156 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
mbed_official 25:ac5b0a371348 1157 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1158 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1159 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1160 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1161 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1162 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1163 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1164 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1165 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1166 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1167 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1168 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1169 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 1170 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 1171 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 1172 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 1173
mbed_official 25:ac5b0a371348 1174 /******************** Bits definition for DMA_SxFCR register ****************/
mbed_official 25:ac5b0a371348 1175 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1176 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
mbed_official 25:ac5b0a371348 1177 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1178 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1179 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1180 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1181 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
mbed_official 25:ac5b0a371348 1182 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1183 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1184
mbed_official 25:ac5b0a371348 1185 /******************** Bits definition for DMA_LISR register *****************/
mbed_official 25:ac5b0a371348 1186 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 1187 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 1188 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 1189 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 1190 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 1191 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 1192 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 1193 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 1194 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 1195 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1196 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1197 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1198 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1199 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1200 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1201 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1202 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1203 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1204 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1205 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1206
mbed_official 25:ac5b0a371348 1207 /******************** Bits definition for DMA_HISR register *****************/
mbed_official 25:ac5b0a371348 1208 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 1209 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 1210 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 1211 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 1212 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 1213 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 1214 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 1215 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 1216 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 1217 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1218 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1219 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1220 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1221 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1222 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1223 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1224 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1225 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1226 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1227 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1228
mbed_official 25:ac5b0a371348 1229 /******************** Bits definition for DMA_LIFCR register ****************/
mbed_official 25:ac5b0a371348 1230 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 1231 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 1232 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 1233 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 1234 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 1235 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 1236 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 1237 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 1238 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 1239 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1240 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1241 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1242 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1243 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1244 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1245 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1246 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1247 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1248 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1249 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1250
mbed_official 25:ac5b0a371348 1251 /******************** Bits definition for DMA_HIFCR register ****************/
mbed_official 25:ac5b0a371348 1252 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 1253 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 1254 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 1255 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 1256 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 1257 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 1258 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 1259 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 1260 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 1261 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1262 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1263 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1264 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1265 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1266 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1267 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1268 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1269 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1270 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1271 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1272
mbed_official 25:ac5b0a371348 1273
mbed_official 25:ac5b0a371348 1274 /******************************************************************************/
mbed_official 25:ac5b0a371348 1275 /* */
mbed_official 25:ac5b0a371348 1276 /* External Interrupt/Event Controller */
mbed_official 25:ac5b0a371348 1277 /* */
mbed_official 25:ac5b0a371348 1278 /******************************************************************************/
mbed_official 25:ac5b0a371348 1279 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 25:ac5b0a371348 1280 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 25:ac5b0a371348 1281 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 25:ac5b0a371348 1282 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 25:ac5b0a371348 1283 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 25:ac5b0a371348 1284 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 25:ac5b0a371348 1285 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 25:ac5b0a371348 1286 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 25:ac5b0a371348 1287 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 25:ac5b0a371348 1288 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 25:ac5b0a371348 1289 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 25:ac5b0a371348 1290 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 25:ac5b0a371348 1291 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 25:ac5b0a371348 1292 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 25:ac5b0a371348 1293 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 25:ac5b0a371348 1294 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 25:ac5b0a371348 1295 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 25:ac5b0a371348 1296 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 25:ac5b0a371348 1297 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 25:ac5b0a371348 1298 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 25:ac5b0a371348 1299 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 25:ac5b0a371348 1300 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 25:ac5b0a371348 1301 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 25:ac5b0a371348 1302 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 25:ac5b0a371348 1303 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 25:ac5b0a371348 1304
mbed_official 25:ac5b0a371348 1305 /******************* Bit definition for EXTI_EMR register *******************/
mbed_official 25:ac5b0a371348 1306 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 25:ac5b0a371348 1307 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 25:ac5b0a371348 1308 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 25:ac5b0a371348 1309 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 25:ac5b0a371348 1310 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 25:ac5b0a371348 1311 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 25:ac5b0a371348 1312 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 25:ac5b0a371348 1313 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 25:ac5b0a371348 1314 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 25:ac5b0a371348 1315 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 25:ac5b0a371348 1316 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 25:ac5b0a371348 1317 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 25:ac5b0a371348 1318 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 25:ac5b0a371348 1319 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 25:ac5b0a371348 1320 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 25:ac5b0a371348 1321 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 25:ac5b0a371348 1322 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 25:ac5b0a371348 1323 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 25:ac5b0a371348 1324 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 25:ac5b0a371348 1325 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 25:ac5b0a371348 1326 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 25:ac5b0a371348 1327 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 25:ac5b0a371348 1328 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 25:ac5b0a371348 1329 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 25:ac5b0a371348 1330
mbed_official 25:ac5b0a371348 1331 /****************** Bit definition for EXTI_RTSR register *******************/
mbed_official 25:ac5b0a371348 1332 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 25:ac5b0a371348 1333 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 25:ac5b0a371348 1334 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 25:ac5b0a371348 1335 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 25:ac5b0a371348 1336 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 25:ac5b0a371348 1337 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 25:ac5b0a371348 1338 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 25:ac5b0a371348 1339 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 25:ac5b0a371348 1340 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 25:ac5b0a371348 1341 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 25:ac5b0a371348 1342 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 25:ac5b0a371348 1343 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 25:ac5b0a371348 1344 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 25:ac5b0a371348 1345 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 25:ac5b0a371348 1346 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 25:ac5b0a371348 1347 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 25:ac5b0a371348 1348 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 25:ac5b0a371348 1349 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 25:ac5b0a371348 1350 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 25:ac5b0a371348 1351 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 25:ac5b0a371348 1352 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 25:ac5b0a371348 1353 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 25:ac5b0a371348 1354 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 25:ac5b0a371348 1355 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
mbed_official 25:ac5b0a371348 1356
mbed_official 25:ac5b0a371348 1357 /****************** Bit definition for EXTI_FTSR register *******************/
mbed_official 25:ac5b0a371348 1358 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 25:ac5b0a371348 1359 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 25:ac5b0a371348 1360 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 25:ac5b0a371348 1361 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 25:ac5b0a371348 1362 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 25:ac5b0a371348 1363 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 25:ac5b0a371348 1364 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 25:ac5b0a371348 1365 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 25:ac5b0a371348 1366 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 25:ac5b0a371348 1367 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 25:ac5b0a371348 1368 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 25:ac5b0a371348 1369 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 25:ac5b0a371348 1370 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 25:ac5b0a371348 1371 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 25:ac5b0a371348 1372 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 25:ac5b0a371348 1373 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 25:ac5b0a371348 1374 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 25:ac5b0a371348 1375 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 25:ac5b0a371348 1376 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 25:ac5b0a371348 1377 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 25:ac5b0a371348 1378 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 25:ac5b0a371348 1379 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 25:ac5b0a371348 1380 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 25:ac5b0a371348 1381 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
mbed_official 25:ac5b0a371348 1382
mbed_official 25:ac5b0a371348 1383 /****************** Bit definition for EXTI_SWIER register ******************/
mbed_official 25:ac5b0a371348 1384 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 25:ac5b0a371348 1385 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 25:ac5b0a371348 1386 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 25:ac5b0a371348 1387 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 25:ac5b0a371348 1388 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 25:ac5b0a371348 1389 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 25:ac5b0a371348 1390 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 25:ac5b0a371348 1391 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 25:ac5b0a371348 1392 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 25:ac5b0a371348 1393 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 25:ac5b0a371348 1394 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 25:ac5b0a371348 1395 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 25:ac5b0a371348 1396 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 25:ac5b0a371348 1397 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 25:ac5b0a371348 1398 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 25:ac5b0a371348 1399 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 25:ac5b0a371348 1400 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 25:ac5b0a371348 1401 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 25:ac5b0a371348 1402 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 25:ac5b0a371348 1403 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 25:ac5b0a371348 1404 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 25:ac5b0a371348 1405 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 25:ac5b0a371348 1406 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 25:ac5b0a371348 1407 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
mbed_official 25:ac5b0a371348 1408
mbed_official 25:ac5b0a371348 1409 /******************* Bit definition for EXTI_PR register ********************/
mbed_official 25:ac5b0a371348 1410 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
mbed_official 25:ac5b0a371348 1411 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
mbed_official 25:ac5b0a371348 1412 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
mbed_official 25:ac5b0a371348 1413 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
mbed_official 25:ac5b0a371348 1414 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
mbed_official 25:ac5b0a371348 1415 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
mbed_official 25:ac5b0a371348 1416 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
mbed_official 25:ac5b0a371348 1417 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
mbed_official 25:ac5b0a371348 1418 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
mbed_official 25:ac5b0a371348 1419 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
mbed_official 25:ac5b0a371348 1420 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
mbed_official 25:ac5b0a371348 1421 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
mbed_official 25:ac5b0a371348 1422 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
mbed_official 25:ac5b0a371348 1423 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
mbed_official 25:ac5b0a371348 1424 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
mbed_official 25:ac5b0a371348 1425 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
mbed_official 25:ac5b0a371348 1426 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
mbed_official 25:ac5b0a371348 1427 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
mbed_official 25:ac5b0a371348 1428 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
mbed_official 25:ac5b0a371348 1429 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
mbed_official 25:ac5b0a371348 1430 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
mbed_official 25:ac5b0a371348 1431 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
mbed_official 25:ac5b0a371348 1432 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
mbed_official 25:ac5b0a371348 1433 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
mbed_official 25:ac5b0a371348 1434
mbed_official 25:ac5b0a371348 1435 /******************************************************************************/
mbed_official 25:ac5b0a371348 1436 /* */
mbed_official 25:ac5b0a371348 1437 /* FLASH */
mbed_official 25:ac5b0a371348 1438 /* */
mbed_official 25:ac5b0a371348 1439 /******************************************************************************/
mbed_official 25:ac5b0a371348 1440 /******************* Bits definition for FLASH_ACR register *****************/
mbed_official 25:ac5b0a371348 1441 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
mbed_official 25:ac5b0a371348 1442 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
mbed_official 25:ac5b0a371348 1443 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1444 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1445 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
mbed_official 25:ac5b0a371348 1446 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1447 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
mbed_official 25:ac5b0a371348 1448 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
mbed_official 25:ac5b0a371348 1449 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
mbed_official 25:ac5b0a371348 1450
mbed_official 25:ac5b0a371348 1451 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1452 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1453 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1454 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1455 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 1456 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
mbed_official 25:ac5b0a371348 1457 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
mbed_official 25:ac5b0a371348 1458
mbed_official 25:ac5b0a371348 1459 /******************* Bits definition for FLASH_SR register ******************/
mbed_official 25:ac5b0a371348 1460 #define FLASH_SR_EOP ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1461 #define FLASH_SR_SOP ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1462 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1463 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1464 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1465 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1466 #define FLASH_SR_BSY ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1467
mbed_official 25:ac5b0a371348 1468 /******************* Bits definition for FLASH_CR register ******************/
mbed_official 25:ac5b0a371348 1469 #define FLASH_CR_PG ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1470 #define FLASH_CR_SER ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1471 #define FLASH_CR_MER ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1472 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
mbed_official 25:ac5b0a371348 1473 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1474 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1475 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1476 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1477 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1478 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
mbed_official 25:ac5b0a371348 1479 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1480 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1481 #define FLASH_CR_STRT ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1482 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 1483 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 1484
mbed_official 25:ac5b0a371348 1485 /******************* Bits definition for FLASH_OPTCR register ***************/
mbed_official 25:ac5b0a371348 1486 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1487 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1488 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1489 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1490 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
mbed_official 25:ac5b0a371348 1491
mbed_official 25:ac5b0a371348 1492 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1493 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1494 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1495 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
mbed_official 25:ac5b0a371348 1496 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1497 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1498 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1499 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1500 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 1501 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 1502 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 1503 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 1504 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
mbed_official 25:ac5b0a371348 1505 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1506 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 1507 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 1508 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 1509 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 1510 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 1511 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 1512 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 1513 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 1514 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 1515 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 1516 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 1517
mbed_official 25:ac5b0a371348 1518 /****************** Bits definition for FLASH_OPTCR1 register ***************/
mbed_official 25:ac5b0a371348 1519 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
mbed_official 25:ac5b0a371348 1520 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1521 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 1522 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 1523 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 1524 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 1525 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 1526 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 1527 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 1528 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 1529 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 1530 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 1531 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 1532
mbed_official 25:ac5b0a371348 1533 /******************************************************************************/
mbed_official 25:ac5b0a371348 1534 /* */
mbed_official 25:ac5b0a371348 1535 /* General Purpose I/O */
mbed_official 25:ac5b0a371348 1536 /* */
mbed_official 25:ac5b0a371348 1537 /******************************************************************************/
mbed_official 25:ac5b0a371348 1538 /****************** Bits definition for GPIO_MODER register *****************/
mbed_official 25:ac5b0a371348 1539 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 25:ac5b0a371348 1540 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1541 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1542
mbed_official 25:ac5b0a371348 1543 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 25:ac5b0a371348 1544 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1545 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1546
mbed_official 25:ac5b0a371348 1547 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 25:ac5b0a371348 1548 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1549 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1550
mbed_official 25:ac5b0a371348 1551 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 25:ac5b0a371348 1552 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1553 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1554
mbed_official 25:ac5b0a371348 1555 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 25:ac5b0a371348 1556 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1557 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1558
mbed_official 25:ac5b0a371348 1559 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 25:ac5b0a371348 1560 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1561 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1562
mbed_official 25:ac5b0a371348 1563 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 25:ac5b0a371348 1564 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 1565 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 1566
mbed_official 25:ac5b0a371348 1567 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 25:ac5b0a371348 1568 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 1569 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 1570
mbed_official 25:ac5b0a371348 1571 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 25:ac5b0a371348 1572 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1573 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 1574
mbed_official 25:ac5b0a371348 1575 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 25:ac5b0a371348 1576 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 1577 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 1578
mbed_official 25:ac5b0a371348 1579 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 25:ac5b0a371348 1580 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 1581 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 1582
mbed_official 25:ac5b0a371348 1583 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 25:ac5b0a371348 1584 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 1585 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 1586
mbed_official 25:ac5b0a371348 1587 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 25:ac5b0a371348 1588 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 1589 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 1590
mbed_official 25:ac5b0a371348 1591 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 25:ac5b0a371348 1592 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 1593 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 1594
mbed_official 25:ac5b0a371348 1595 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 25:ac5b0a371348 1596 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 25:ac5b0a371348 1597 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 25:ac5b0a371348 1598
mbed_official 25:ac5b0a371348 1599 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 25:ac5b0a371348 1600 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 25:ac5b0a371348 1601 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 1602
mbed_official 25:ac5b0a371348 1603 /****************** Bits definition for GPIO_OTYPER register ****************/
mbed_official 25:ac5b0a371348 1604 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1605 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1606 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1607 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1608 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1609 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1610 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1611 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1612 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1613 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1614 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1615 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1616 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 1617 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 1618 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 1619 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 1620
mbed_official 25:ac5b0a371348 1621 /****************** Bits definition for GPIO_OSPEEDR register ***************/
mbed_official 25:ac5b0a371348 1622 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 25:ac5b0a371348 1623 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1624 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1625
mbed_official 25:ac5b0a371348 1626 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 25:ac5b0a371348 1627 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1628 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1629
mbed_official 25:ac5b0a371348 1630 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 25:ac5b0a371348 1631 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1632 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1633
mbed_official 25:ac5b0a371348 1634 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 25:ac5b0a371348 1635 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1636 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1637
mbed_official 25:ac5b0a371348 1638 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 25:ac5b0a371348 1639 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1640 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1641
mbed_official 25:ac5b0a371348 1642 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 25:ac5b0a371348 1643 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1644 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1645
mbed_official 25:ac5b0a371348 1646 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 25:ac5b0a371348 1647 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 1648 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 1649
mbed_official 25:ac5b0a371348 1650 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 25:ac5b0a371348 1651 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 1652 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 1653
mbed_official 25:ac5b0a371348 1654 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 25:ac5b0a371348 1655 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1656 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 1657
mbed_official 25:ac5b0a371348 1658 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 25:ac5b0a371348 1659 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 1660 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 1661
mbed_official 25:ac5b0a371348 1662 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 25:ac5b0a371348 1663 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 1664 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 1665
mbed_official 25:ac5b0a371348 1666 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 25:ac5b0a371348 1667 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 1668 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 1669
mbed_official 25:ac5b0a371348 1670 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 25:ac5b0a371348 1671 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 1672 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 1673
mbed_official 25:ac5b0a371348 1674 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 25:ac5b0a371348 1675 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 1676 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 1677
mbed_official 25:ac5b0a371348 1678 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 25:ac5b0a371348 1679 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 25:ac5b0a371348 1680 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 25:ac5b0a371348 1681
mbed_official 25:ac5b0a371348 1682 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 25:ac5b0a371348 1683 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 25:ac5b0a371348 1684 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 1685
mbed_official 25:ac5b0a371348 1686 /****************** Bits definition for GPIO_PUPDR register *****************/
mbed_official 25:ac5b0a371348 1687 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 25:ac5b0a371348 1688 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1689 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1690
mbed_official 25:ac5b0a371348 1691 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 25:ac5b0a371348 1692 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1693 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1694
mbed_official 25:ac5b0a371348 1695 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 25:ac5b0a371348 1696 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1697 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1698
mbed_official 25:ac5b0a371348 1699 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 25:ac5b0a371348 1700 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1701 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1702
mbed_official 25:ac5b0a371348 1703 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 25:ac5b0a371348 1704 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1705 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1706
mbed_official 25:ac5b0a371348 1707 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 25:ac5b0a371348 1708 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1709 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1710
mbed_official 25:ac5b0a371348 1711 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 25:ac5b0a371348 1712 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 1713 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 1714
mbed_official 25:ac5b0a371348 1715 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 25:ac5b0a371348 1716 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 1717 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 1718
mbed_official 25:ac5b0a371348 1719 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 25:ac5b0a371348 1720 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1721 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 1722
mbed_official 25:ac5b0a371348 1723 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 25:ac5b0a371348 1724 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 1725 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 1726
mbed_official 25:ac5b0a371348 1727 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 25:ac5b0a371348 1728 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 1729 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 1730
mbed_official 25:ac5b0a371348 1731 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 25:ac5b0a371348 1732 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 1733 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 1734
mbed_official 25:ac5b0a371348 1735 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 25:ac5b0a371348 1736 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 1737 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 1738
mbed_official 25:ac5b0a371348 1739 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 25:ac5b0a371348 1740 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 1741 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 1742
mbed_official 25:ac5b0a371348 1743 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 25:ac5b0a371348 1744 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 25:ac5b0a371348 1745 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 25:ac5b0a371348 1746
mbed_official 25:ac5b0a371348 1747 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 25:ac5b0a371348 1748 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 25:ac5b0a371348 1749 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 1750
mbed_official 25:ac5b0a371348 1751 /****************** Bits definition for GPIO_IDR register *******************/
mbed_official 25:ac5b0a371348 1752 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1753 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1754 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1755 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1756 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1757 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1758 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1759 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1760 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1761 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1762 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1763 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1764 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 1765 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 1766 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 1767 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 1768
mbed_official 25:ac5b0a371348 1769 /****************** Bits definition for GPIO_ODR register *******************/
mbed_official 25:ac5b0a371348 1770 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1771 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1772 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1773 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1774 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1775 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1776 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1777 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1778 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1779 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1780 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1781 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1782 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 1783 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 1784 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 1785 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 1786
mbed_official 25:ac5b0a371348 1787 /****************** Bits definition for GPIO_BSRR register ******************/
mbed_official 25:ac5b0a371348 1788 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1789 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1790 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1791 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1792 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1793 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1794 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1795 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1796 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1797 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1798 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1799 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1800 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 1801 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 1802 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 1803 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 1804 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1805 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 1806 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 1807 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 1808 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 1809 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 1810 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 1811 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 1812 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 1813 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 1814 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 1815 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 1816 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 25:ac5b0a371348 1817 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 25:ac5b0a371348 1818 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 25:ac5b0a371348 1819 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 1820
mbed_official 25:ac5b0a371348 1821 /****************** Bit definition for GPIO_LCKR register *********************/
mbed_official 25:ac5b0a371348 1822 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 1823 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 1824 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 1825 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 1826 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 1827 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 1828 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 1829 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 1830 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 1831 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 1832 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 1833 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 1834 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 1835 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 1836 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 1837 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 1838 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 1839
mbed_official 25:ac5b0a371348 1840 /******************************************************************************/
mbed_official 25:ac5b0a371348 1841 /* */
mbed_official 25:ac5b0a371348 1842 /* Inter-integrated Circuit Interface */
mbed_official 25:ac5b0a371348 1843 /* */
mbed_official 25:ac5b0a371348 1844 /******************************************************************************/
mbed_official 25:ac5b0a371348 1845 /******************* Bit definition for I2C_CR1 register ********************/
mbed_official 25:ac5b0a371348 1846 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
mbed_official 25:ac5b0a371348 1847 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
mbed_official 25:ac5b0a371348 1848 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
mbed_official 25:ac5b0a371348 1849 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
mbed_official 25:ac5b0a371348 1850 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
mbed_official 25:ac5b0a371348 1851 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
mbed_official 25:ac5b0a371348 1852 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
mbed_official 25:ac5b0a371348 1853 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
mbed_official 25:ac5b0a371348 1854 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
mbed_official 25:ac5b0a371348 1855 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
mbed_official 25:ac5b0a371348 1856 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
mbed_official 25:ac5b0a371348 1857 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
mbed_official 25:ac5b0a371348 1858 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
mbed_official 25:ac5b0a371348 1859 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
mbed_official 25:ac5b0a371348 1860
mbed_official 25:ac5b0a371348 1861 /******************* Bit definition for I2C_CR2 register ********************/
mbed_official 25:ac5b0a371348 1862 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
mbed_official 25:ac5b0a371348 1863 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 1864 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 1865 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 1866 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 1867 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 1868 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 25:ac5b0a371348 1869
mbed_official 25:ac5b0a371348 1870 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
mbed_official 25:ac5b0a371348 1871 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
mbed_official 25:ac5b0a371348 1872 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
mbed_official 25:ac5b0a371348 1873 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
mbed_official 25:ac5b0a371348 1874 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
mbed_official 25:ac5b0a371348 1875
mbed_official 25:ac5b0a371348 1876 /******************* Bit definition for I2C_OAR1 register *******************/
mbed_official 25:ac5b0a371348 1877 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
mbed_official 25:ac5b0a371348 1878 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
mbed_official 25:ac5b0a371348 1879
mbed_official 25:ac5b0a371348 1880 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 1881 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 1882 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 1883 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 1884 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 1885 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 25:ac5b0a371348 1886 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 25:ac5b0a371348 1887 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 25:ac5b0a371348 1888 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
mbed_official 25:ac5b0a371348 1889 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
mbed_official 25:ac5b0a371348 1890
mbed_official 25:ac5b0a371348 1891 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
mbed_official 25:ac5b0a371348 1892
mbed_official 25:ac5b0a371348 1893 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 25:ac5b0a371348 1894 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
mbed_official 25:ac5b0a371348 1895 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
mbed_official 25:ac5b0a371348 1896
mbed_official 25:ac5b0a371348 1897 /******************** Bit definition for I2C_DR register ********************/
mbed_official 25:ac5b0a371348 1898 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
mbed_official 25:ac5b0a371348 1899
mbed_official 25:ac5b0a371348 1900 /******************* Bit definition for I2C_SR1 register ********************/
mbed_official 25:ac5b0a371348 1901 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
mbed_official 25:ac5b0a371348 1902 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
mbed_official 25:ac5b0a371348 1903 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
mbed_official 25:ac5b0a371348 1904 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
mbed_official 25:ac5b0a371348 1905 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
mbed_official 25:ac5b0a371348 1906 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
mbed_official 25:ac5b0a371348 1907 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
mbed_official 25:ac5b0a371348 1908 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
mbed_official 25:ac5b0a371348 1909 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
mbed_official 25:ac5b0a371348 1910 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
mbed_official 25:ac5b0a371348 1911 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
mbed_official 25:ac5b0a371348 1912 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
mbed_official 25:ac5b0a371348 1913 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
mbed_official 25:ac5b0a371348 1914 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
mbed_official 25:ac5b0a371348 1915
mbed_official 25:ac5b0a371348 1916 /******************* Bit definition for I2C_SR2 register ********************/
mbed_official 25:ac5b0a371348 1917 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
mbed_official 25:ac5b0a371348 1918 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
mbed_official 25:ac5b0a371348 1919 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
mbed_official 25:ac5b0a371348 1920 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
mbed_official 25:ac5b0a371348 1921 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
mbed_official 25:ac5b0a371348 1922 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
mbed_official 25:ac5b0a371348 1923 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
mbed_official 25:ac5b0a371348 1924 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
mbed_official 25:ac5b0a371348 1925
mbed_official 25:ac5b0a371348 1926 /******************* Bit definition for I2C_CCR register ********************/
mbed_official 25:ac5b0a371348 1927 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
mbed_official 25:ac5b0a371348 1928 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
mbed_official 25:ac5b0a371348 1929 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
mbed_official 25:ac5b0a371348 1930
mbed_official 25:ac5b0a371348 1931 /****************** Bit definition for I2C_TRISE register *******************/
mbed_official 25:ac5b0a371348 1932 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
mbed_official 25:ac5b0a371348 1933
mbed_official 25:ac5b0a371348 1934 /****************** Bit definition for I2C_FLTR register *******************/
mbed_official 25:ac5b0a371348 1935 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
mbed_official 25:ac5b0a371348 1936 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
mbed_official 25:ac5b0a371348 1937
mbed_official 25:ac5b0a371348 1938 /******************************************************************************/
mbed_official 25:ac5b0a371348 1939 /* */
mbed_official 25:ac5b0a371348 1940 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
mbed_official 25:ac5b0a371348 1941 /* */
mbed_official 25:ac5b0a371348 1942 /******************************************************************************/
mbed_official 25:ac5b0a371348 1943 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 25:ac5b0a371348 1944 #define FMPI2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
mbed_official 25:ac5b0a371348 1945 #define FMPI2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
mbed_official 25:ac5b0a371348 1946 #define FMPI2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
mbed_official 25:ac5b0a371348 1947 #define FMPI2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
mbed_official 25:ac5b0a371348 1948 #define FMPI2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
mbed_official 25:ac5b0a371348 1949 #define FMPI2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
mbed_official 25:ac5b0a371348 1950 #define FMPI2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
mbed_official 25:ac5b0a371348 1951 #define FMPI2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
mbed_official 25:ac5b0a371348 1952 #define FMPI2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
mbed_official 25:ac5b0a371348 1953 #define FMPI2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
mbed_official 25:ac5b0a371348 1954 #define FMPI2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
mbed_official 25:ac5b0a371348 1955 #define FMPI2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
mbed_official 25:ac5b0a371348 1956 #define FMPI2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
mbed_official 25:ac5b0a371348 1957 #define FMPI2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
mbed_official 25:ac5b0a371348 1958 #define FMPI2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
mbed_official 25:ac5b0a371348 1959 #define FMPI2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
mbed_official 25:ac5b0a371348 1960 #define FMPI2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
mbed_official 25:ac5b0a371348 1961 #define FMPI2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
mbed_official 25:ac5b0a371348 1962 #define FMPI2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
mbed_official 25:ac5b0a371348 1963 #define FMPI2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
mbed_official 25:ac5b0a371348 1964 #define FMPI2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
mbed_official 25:ac5b0a371348 1965
mbed_official 25:ac5b0a371348 1966 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 25:ac5b0a371348 1967 #define FMPI2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
mbed_official 25:ac5b0a371348 1968 #define FMPI2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
mbed_official 25:ac5b0a371348 1969 #define FMPI2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
mbed_official 25:ac5b0a371348 1970 #define FMPI2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
mbed_official 25:ac5b0a371348 1971 #define FMPI2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
mbed_official 25:ac5b0a371348 1972 #define FMPI2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
mbed_official 25:ac5b0a371348 1973 #define FMPI2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
mbed_official 25:ac5b0a371348 1974 #define FMPI2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
mbed_official 25:ac5b0a371348 1975 #define FMPI2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
mbed_official 25:ac5b0a371348 1976 #define FMPI2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
mbed_official 25:ac5b0a371348 1977 #define FMPI2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
mbed_official 25:ac5b0a371348 1978
mbed_official 25:ac5b0a371348 1979 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 25:ac5b0a371348 1980 #define FMPI2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
mbed_official 25:ac5b0a371348 1981 #define FMPI2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
mbed_official 25:ac5b0a371348 1982 #define FMPI2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
mbed_official 25:ac5b0a371348 1983
mbed_official 25:ac5b0a371348 1984 /******************* Bit definition for I2C_OAR2 register ******************/
mbed_official 25:ac5b0a371348 1985 #define FMPI2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
mbed_official 25:ac5b0a371348 1986 #define FMPI2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
mbed_official 25:ac5b0a371348 1987 #define FMPI2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
mbed_official 25:ac5b0a371348 1988
mbed_official 25:ac5b0a371348 1989 /******************* Bit definition for I2C_TIMINGR register *******************/
mbed_official 25:ac5b0a371348 1990 #define FMPI2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
mbed_official 25:ac5b0a371348 1991 #define FMPI2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
mbed_official 25:ac5b0a371348 1992 #define FMPI2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
mbed_official 25:ac5b0a371348 1993 #define FMPI2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
mbed_official 25:ac5b0a371348 1994 #define FMPI2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
mbed_official 25:ac5b0a371348 1995
mbed_official 25:ac5b0a371348 1996 /******************* Bit definition for I2C_TIMEOUTR register *******************/
mbed_official 25:ac5b0a371348 1997 #define FMPI2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
mbed_official 25:ac5b0a371348 1998 #define FMPI2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
mbed_official 25:ac5b0a371348 1999 #define FMPI2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
mbed_official 25:ac5b0a371348 2000 #define FMPI2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */
mbed_official 25:ac5b0a371348 2001 #define FMPI2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
mbed_official 25:ac5b0a371348 2002
mbed_official 25:ac5b0a371348 2003 /****************** Bit definition for I2C_ISR register *********************/
mbed_official 25:ac5b0a371348 2004 #define FMPI2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
mbed_official 25:ac5b0a371348 2005 #define FMPI2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
mbed_official 25:ac5b0a371348 2006 #define FMPI2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
mbed_official 25:ac5b0a371348 2007 #define FMPI2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */
mbed_official 25:ac5b0a371348 2008 #define FMPI2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
mbed_official 25:ac5b0a371348 2009 #define FMPI2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
mbed_official 25:ac5b0a371348 2010 #define FMPI2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
mbed_official 25:ac5b0a371348 2011 #define FMPI2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
mbed_official 25:ac5b0a371348 2012 #define FMPI2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
mbed_official 25:ac5b0a371348 2013 #define FMPI2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
mbed_official 25:ac5b0a371348 2014 #define FMPI2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
mbed_official 25:ac5b0a371348 2015 #define FMPI2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
mbed_official 25:ac5b0a371348 2016 #define FMPI2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
mbed_official 25:ac5b0a371348 2017 #define FMPI2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
mbed_official 25:ac5b0a371348 2018 #define FMPI2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
mbed_official 25:ac5b0a371348 2019 #define FMPI2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
mbed_official 25:ac5b0a371348 2020 #define FMPI2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
mbed_official 25:ac5b0a371348 2021
mbed_official 25:ac5b0a371348 2022 /****************** Bit definition for I2C_ICR register *********************/
mbed_official 25:ac5b0a371348 2023 #define FMPI2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
mbed_official 25:ac5b0a371348 2024 #define FMPI2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
mbed_official 25:ac5b0a371348 2025 #define FMPI2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
mbed_official 25:ac5b0a371348 2026 #define FMPI2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
mbed_official 25:ac5b0a371348 2027 #define FMPI2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
mbed_official 25:ac5b0a371348 2028 #define FMPI2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
mbed_official 25:ac5b0a371348 2029 #define FMPI2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
mbed_official 25:ac5b0a371348 2030 #define FMPI2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
mbed_official 25:ac5b0a371348 2031 #define FMPI2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
mbed_official 25:ac5b0a371348 2032
mbed_official 25:ac5b0a371348 2033 /****************** Bit definition for I2C_PECR register *********************/
mbed_official 25:ac5b0a371348 2034 #define FMPI2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
mbed_official 25:ac5b0a371348 2035
mbed_official 25:ac5b0a371348 2036 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 25:ac5b0a371348 2037 #define FMPI2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
mbed_official 25:ac5b0a371348 2038
mbed_official 25:ac5b0a371348 2039 /****************** Bit definition for I2C_TXDR register *********************/
mbed_official 25:ac5b0a371348 2040 #define FMPI2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
mbed_official 25:ac5b0a371348 2041
mbed_official 25:ac5b0a371348 2042 /******************************************************************************/
mbed_official 25:ac5b0a371348 2043 /* */
mbed_official 25:ac5b0a371348 2044 /* Independent WATCHDOG */
mbed_official 25:ac5b0a371348 2045 /* */
mbed_official 25:ac5b0a371348 2046 /******************************************************************************/
mbed_official 25:ac5b0a371348 2047 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 25:ac5b0a371348 2048 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
mbed_official 25:ac5b0a371348 2049
mbed_official 25:ac5b0a371348 2050 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 25:ac5b0a371348 2051 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
mbed_official 25:ac5b0a371348 2052 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 2053 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 2054 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 2055
mbed_official 25:ac5b0a371348 2056 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 25:ac5b0a371348 2057 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
mbed_official 25:ac5b0a371348 2058
mbed_official 25:ac5b0a371348 2059 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 25:ac5b0a371348 2060 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
mbed_official 25:ac5b0a371348 2061 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
mbed_official 25:ac5b0a371348 2062
mbed_official 25:ac5b0a371348 2063
mbed_official 25:ac5b0a371348 2064 /******************************************************************************/
mbed_official 25:ac5b0a371348 2065 /* */
mbed_official 25:ac5b0a371348 2066 /* Power Control */
mbed_official 25:ac5b0a371348 2067 /* */
mbed_official 25:ac5b0a371348 2068 /******************************************************************************/
mbed_official 25:ac5b0a371348 2069 /******************** Bit definition for PWR_CR register ********************/
mbed_official 25:ac5b0a371348 2070 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
mbed_official 25:ac5b0a371348 2071 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 25:ac5b0a371348 2072 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 25:ac5b0a371348 2073 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 25:ac5b0a371348 2074 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 25:ac5b0a371348 2075
mbed_official 25:ac5b0a371348 2076 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 25:ac5b0a371348 2077 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 2078 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 2079 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 25:ac5b0a371348 2080
mbed_official 25:ac5b0a371348 2081 /*!< PVD level configuration */
mbed_official 25:ac5b0a371348 2082 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 25:ac5b0a371348 2083 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 25:ac5b0a371348 2084 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 25:ac5b0a371348 2085 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 25:ac5b0a371348 2086 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 25:ac5b0a371348 2087 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 25:ac5b0a371348 2088 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 25:ac5b0a371348 2089 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 25:ac5b0a371348 2090
mbed_official 25:ac5b0a371348 2091 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 25:ac5b0a371348 2092 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
mbed_official 25:ac5b0a371348 2093 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
mbed_official 25:ac5b0a371348 2094 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
mbed_official 25:ac5b0a371348 2095 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 25:ac5b0a371348 2096
mbed_official 25:ac5b0a371348 2097 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
mbed_official 25:ac5b0a371348 2098 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 2099 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 2100
mbed_official 25:ac5b0a371348 2101 #define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
mbed_official 25:ac5b0a371348 2102 #define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
mbed_official 25:ac5b0a371348 2103 /* Legacy define */
mbed_official 25:ac5b0a371348 2104 #define PWR_CR_PMODE PWR_CR_VOS
mbed_official 25:ac5b0a371348 2105
mbed_official 25:ac5b0a371348 2106 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 25:ac5b0a371348 2107 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 25:ac5b0a371348 2108 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 25:ac5b0a371348 2109 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 25:ac5b0a371348 2110 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
mbed_official 25:ac5b0a371348 2111 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
mbed_official 25:ac5b0a371348 2112 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
mbed_official 25:ac5b0a371348 2113 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
mbed_official 25:ac5b0a371348 2114
mbed_official 25:ac5b0a371348 2115 /* Legacy define */
mbed_official 25:ac5b0a371348 2116 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
mbed_official 25:ac5b0a371348 2117
mbed_official 25:ac5b0a371348 2118 /******************************************************************************/
mbed_official 25:ac5b0a371348 2119 /* */
mbed_official 25:ac5b0a371348 2120 /* Reset and Clock Control */
mbed_official 25:ac5b0a371348 2121 /* */
mbed_official 25:ac5b0a371348 2122 /******************************************************************************/
mbed_official 25:ac5b0a371348 2123 /******************** Bit definition for RCC_CR register ********************/
mbed_official 25:ac5b0a371348 2124 #define RCC_CR_HSION ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2125 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2126
mbed_official 25:ac5b0a371348 2127 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
mbed_official 25:ac5b0a371348 2128 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
mbed_official 25:ac5b0a371348 2129 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
mbed_official 25:ac5b0a371348 2130 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
mbed_official 25:ac5b0a371348 2131 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
mbed_official 25:ac5b0a371348 2132 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
mbed_official 25:ac5b0a371348 2133
mbed_official 25:ac5b0a371348 2134 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
mbed_official 25:ac5b0a371348 2135 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
mbed_official 25:ac5b0a371348 2136 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
mbed_official 25:ac5b0a371348 2137 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
mbed_official 25:ac5b0a371348 2138 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
mbed_official 25:ac5b0a371348 2139 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
mbed_official 25:ac5b0a371348 2140 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
mbed_official 25:ac5b0a371348 2141 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
mbed_official 25:ac5b0a371348 2142 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
mbed_official 25:ac5b0a371348 2143
mbed_official 25:ac5b0a371348 2144 #define RCC_CR_HSEON ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2145 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2146 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2147 #define RCC_CR_CSSON ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 2148 #define RCC_CR_PLLON ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 2149 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 2150
mbed_official 25:ac5b0a371348 2151 /******************** Bit definition for RCC_PLLCFGR register ***************/
mbed_official 25:ac5b0a371348 2152 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
mbed_official 25:ac5b0a371348 2153 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2154 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2155 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2156 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2157 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2158 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2159
mbed_official 25:ac5b0a371348 2160 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
mbed_official 25:ac5b0a371348 2161 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 2162 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 2163 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2164 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2165 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2166 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2167 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2168 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 2169 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2170
mbed_official 25:ac5b0a371348 2171 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
mbed_official 25:ac5b0a371348 2172 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2173 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2174
mbed_official 25:ac5b0a371348 2175 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2176 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2177 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
mbed_official 25:ac5b0a371348 2178
mbed_official 25:ac5b0a371348 2179 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
mbed_official 25:ac5b0a371348 2180 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 2181 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 2182 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 2183 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 2184
mbed_official 25:ac5b0a371348 2185 #define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)
mbed_official 25:ac5b0a371348 2186 #define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
mbed_official 25:ac5b0a371348 2187 #define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)
mbed_official 25:ac5b0a371348 2188 #define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)
mbed_official 25:ac5b0a371348 2189 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 25:ac5b0a371348 2190 /*!< SW configuration */
mbed_official 25:ac5b0a371348 2191 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 25:ac5b0a371348 2192 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 2193 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 2194
mbed_official 25:ac5b0a371348 2195 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 25:ac5b0a371348 2196 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 25:ac5b0a371348 2197 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 25:ac5b0a371348 2198
mbed_official 25:ac5b0a371348 2199 /*!< SWS configuration */
mbed_official 25:ac5b0a371348 2200 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 25:ac5b0a371348 2201 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 2202 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 2203
mbed_official 25:ac5b0a371348 2204 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 25:ac5b0a371348 2205 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 25:ac5b0a371348 2206 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 25:ac5b0a371348 2207
mbed_official 25:ac5b0a371348 2208 /*!< HPRE configuration */
mbed_official 25:ac5b0a371348 2209 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 25:ac5b0a371348 2210 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 2211 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 2212 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 25:ac5b0a371348 2213 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 25:ac5b0a371348 2214
mbed_official 25:ac5b0a371348 2215 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 25:ac5b0a371348 2216 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 25:ac5b0a371348 2217 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 25:ac5b0a371348 2218 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 25:ac5b0a371348 2219 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 25:ac5b0a371348 2220 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 25:ac5b0a371348 2221 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 25:ac5b0a371348 2222 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 25:ac5b0a371348 2223 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 25:ac5b0a371348 2224
mbed_official 25:ac5b0a371348 2225 /*!< MCO1EN configuration */
mbed_official 25:ac5b0a371348 2226 #define RCC_CFGR_MCO1EN ((uint32_t)0x00000100) /*!< MCO1EN bit */
mbed_official 25:ac5b0a371348 2227
mbed_official 25:ac5b0a371348 2228 /*!< MCO2EN configuration */
mbed_official 25:ac5b0a371348 2229 #define RCC_CFGR_MCO2EN ((uint32_t)0x00000200) /*!< MCO2EN bit */
mbed_official 25:ac5b0a371348 2230
mbed_official 25:ac5b0a371348 2231 /*!< PPRE1 configuration */
mbed_official 25:ac5b0a371348 2232 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 25:ac5b0a371348 2233 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 2234 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 2235 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 25:ac5b0a371348 2236
mbed_official 25:ac5b0a371348 2237 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 25:ac5b0a371348 2238 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
mbed_official 25:ac5b0a371348 2239 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
mbed_official 25:ac5b0a371348 2240 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
mbed_official 25:ac5b0a371348 2241 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
mbed_official 25:ac5b0a371348 2242
mbed_official 25:ac5b0a371348 2243 /*!< PPRE2 configuration */
mbed_official 25:ac5b0a371348 2244 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 25:ac5b0a371348 2245 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 2246 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 2247 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 25:ac5b0a371348 2248
mbed_official 25:ac5b0a371348 2249 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 25:ac5b0a371348 2250 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
mbed_official 25:ac5b0a371348 2251 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
mbed_official 25:ac5b0a371348 2252 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
mbed_official 25:ac5b0a371348 2253 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
mbed_official 25:ac5b0a371348 2254
mbed_official 25:ac5b0a371348 2255 /*!< RTCPRE configuration */
mbed_official 25:ac5b0a371348 2256 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
mbed_official 25:ac5b0a371348 2257 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2258 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2259 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2260 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 2261 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 2262
mbed_official 25:ac5b0a371348 2263 /*!< MCO1 configuration */
mbed_official 25:ac5b0a371348 2264 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
mbed_official 25:ac5b0a371348 2265 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2266 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2267
mbed_official 25:ac5b0a371348 2268 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
mbed_official 25:ac5b0a371348 2269 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 2270 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 2271 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 2272
mbed_official 25:ac5b0a371348 2273 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
mbed_official 25:ac5b0a371348 2274 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 2275 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
mbed_official 25:ac5b0a371348 2276 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
mbed_official 25:ac5b0a371348 2277
mbed_official 25:ac5b0a371348 2278 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
mbed_official 25:ac5b0a371348 2279 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
mbed_official 25:ac5b0a371348 2280 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 2281
mbed_official 25:ac5b0a371348 2282 /******************** Bit definition for RCC_CIR register *******************/
mbed_official 25:ac5b0a371348 2283 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2284 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2285 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2286 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2287 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2288
mbed_official 25:ac5b0a371348 2289 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 2290 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2291 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2292 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2293 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2294 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2295
mbed_official 25:ac5b0a371348 2296 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2297 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2298 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2299 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 2300 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 2301
mbed_official 25:ac5b0a371348 2302 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 2303
mbed_official 25:ac5b0a371348 2304 /******************** Bit definition for RCC_AHB1RSTR register **************/
mbed_official 25:ac5b0a371348 2305 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2306 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2307 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2308 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 2309 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2310 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2311 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2312 #define RCC_AHB1RSTR_RNGRST ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 2313
mbed_official 25:ac5b0a371348 2314 /******************** Bit definition for RCC_APB1RSTR register **************/
mbed_official 25:ac5b0a371348 2315 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2316 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2317 #define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2318 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2319 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2320 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2321 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2322 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2323 #define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 2324 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
mbed_official 25:ac5b0a371348 2325 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
mbed_official 25:ac5b0a371348 2326
mbed_official 25:ac5b0a371348 2327 /******************** Bit definition for RCC_APB2RSTR register **************/
mbed_official 25:ac5b0a371348 2328 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2329 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2330 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2331 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2332 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2333 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2334 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2335 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2336 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 2337
mbed_official 25:ac5b0a371348 2338 /******************** Bit definition for RCC_AHB1ENR register ***************/
mbed_official 25:ac5b0a371348 2339 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2340 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2341 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2342 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 2343 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2344 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2345 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2346 #define RCC_AHB1ENR_RNGEN ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 2347
mbed_official 25:ac5b0a371348 2348 /******************** Bit definition for RCC_APB1ENR register ***************/
mbed_official 25:ac5b0a371348 2349 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2350 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2351 #define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2352 #define RCC_APB1ENR_RTCAPBEN ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2353 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2354 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2355 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2356 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2357 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2358 #define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 2359 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
mbed_official 25:ac5b0a371348 2360 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
mbed_official 25:ac5b0a371348 2361
mbed_official 25:ac5b0a371348 2362 /******************** Bit definition for RCC_APB2ENR register ***************/
mbed_official 25:ac5b0a371348 2363 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2364 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2365 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2366 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2367 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2368 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2369 #define RCC_APB2ENR_EXTITEN ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 2370 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2371 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2372 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 2373
mbed_official 25:ac5b0a371348 2374 /******************** Bit definition for RCC_AHB1LPENR register *************/
mbed_official 25:ac5b0a371348 2375 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2376 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2377 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2378 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 2379 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2380 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 2381 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2382 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2383 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2384 #define RCC_AHB1LPENR_RNGLPEN ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 2385
mbed_official 25:ac5b0a371348 2386 /******************** Bit definition for RCC_APB1LPENR register *************/
mbed_official 25:ac5b0a371348 2387 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2388 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2389 #define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2390 #define RCC_APB1LPENR_RTCAPBLPEN ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2391 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2392 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2393 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2394 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2395 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2396 #define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 2397 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
mbed_official 25:ac5b0a371348 2398 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
mbed_official 25:ac5b0a371348 2399
mbed_official 25:ac5b0a371348 2400 /******************** Bit definition for RCC_APB2LPENR register *************/
mbed_official 25:ac5b0a371348 2401 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2402 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2403 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2404 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2405 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2406 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2407 #define RCC_APB2LPENR_EXTITLPEN ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 2408 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2409 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2410 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 2411
mbed_official 25:ac5b0a371348 2412 /******************** Bit definition for RCC_BDCR register ******************/
mbed_official 25:ac5b0a371348 2413 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2414 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2415 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2416 #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2417
mbed_official 25:ac5b0a371348 2418 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
mbed_official 25:ac5b0a371348 2419 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2420 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2421
mbed_official 25:ac5b0a371348 2422 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 2423 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2424
mbed_official 25:ac5b0a371348 2425 /******************** Bit definition for RCC_CSR register *******************/
mbed_official 25:ac5b0a371348 2426 #define RCC_CSR_LSION ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2427 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2428 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 2429 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 2430 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 2431 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 2432 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
mbed_official 25:ac5b0a371348 2433 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
mbed_official 25:ac5b0a371348 2434 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
mbed_official 25:ac5b0a371348 2435 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 2436
mbed_official 25:ac5b0a371348 2437 /******************** Bit definition for RCC_SSCGR register *****************/
mbed_official 25:ac5b0a371348 2438 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
mbed_official 25:ac5b0a371348 2439 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
mbed_official 25:ac5b0a371348 2440 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
mbed_official 25:ac5b0a371348 2441 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 2442
mbed_official 25:ac5b0a371348 2443 /******************** Bit definition for RCC_DCKCFGR register ***************/
mbed_official 25:ac5b0a371348 2444 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 2445 #define RCC_DCKCFGR_I2SSRC ((uint32_t)0x06000000)
mbed_official 25:ac5b0a371348 2446 #define RCC_DCKCFGR_I2SSRC_0 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 2447 #define RCC_DCKCFGR_I2SSRC_1 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 2448
mbed_official 25:ac5b0a371348 2449 /******************** Bit definition for RCC_CKGATENR register **************/
mbed_official 25:ac5b0a371348 2450 #define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2451 #define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2452 #define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2453 #define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2454 #define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2455 #define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2456 #define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 2457
mbed_official 25:ac5b0a371348 2458 /******************** Bit definition for RCC_DCKCFGR2 register **************/
mbed_official 25:ac5b0a371348 2459 #define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)
mbed_official 25:ac5b0a371348 2460 #define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2461 #define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 2462 #define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0xC0000000)
mbed_official 25:ac5b0a371348 2463 #define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x40000000)
mbed_official 25:ac5b0a371348 2464 #define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 2465
mbed_official 25:ac5b0a371348 2466 /******************************************************************************/
mbed_official 25:ac5b0a371348 2467 /* */
mbed_official 25:ac5b0a371348 2468 /* RNG */
mbed_official 25:ac5b0a371348 2469 /* */
mbed_official 25:ac5b0a371348 2470 /******************************************************************************/
mbed_official 25:ac5b0a371348 2471 /******************** Bits definition for RNG_CR register *******************/
mbed_official 25:ac5b0a371348 2472 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2473 #define RNG_CR_IE ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2474
mbed_official 25:ac5b0a371348 2475 /******************** Bits definition for RNG_SR register *******************/
mbed_official 25:ac5b0a371348 2476 #define RNG_SR_DRDY ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2477 #define RNG_SR_CECS ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2478 #define RNG_SR_SECS ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2479 #define RNG_SR_CEIS ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2480 #define RNG_SR_SEIS ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 2481
mbed_official 25:ac5b0a371348 2482 /******************************************************************************/
mbed_official 25:ac5b0a371348 2483 /* */
mbed_official 25:ac5b0a371348 2484 /* Real-Time Clock (RTC) */
mbed_official 25:ac5b0a371348 2485 /* */
mbed_official 25:ac5b0a371348 2486 /******************************************************************************/
mbed_official 25:ac5b0a371348 2487 /******************** Bits definition for RTC_TR register *******************/
mbed_official 25:ac5b0a371348 2488 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2489 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 25:ac5b0a371348 2490 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 2491 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2492 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 25:ac5b0a371348 2493 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2494 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2495 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2496 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 2497 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 25:ac5b0a371348 2498 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2499 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 2500 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2501 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 25:ac5b0a371348 2502 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2503 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2504 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2505 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2506 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 25:ac5b0a371348 2507 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2508 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2509 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 2510 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 25:ac5b0a371348 2511 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2512 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2513 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2514 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2515
mbed_official 25:ac5b0a371348 2516 /******************** Bits definition for RTC_DR register *******************/
mbed_official 25:ac5b0a371348 2517 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 25:ac5b0a371348 2518 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 2519 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2520 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2521 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 2522 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 25:ac5b0a371348 2523 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2524 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2525 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2526 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 2527 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 25:ac5b0a371348 2528 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 2529 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2530 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 2531 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2532 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 25:ac5b0a371348 2533 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2534 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2535 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2536 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2537 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 25:ac5b0a371348 2538 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2539 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2540 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 25:ac5b0a371348 2541 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2542 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2543 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2544 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2545
mbed_official 25:ac5b0a371348 2546 /******************** Bits definition for RTC_CR register *******************/
mbed_official 25:ac5b0a371348 2547 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 2548 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 25:ac5b0a371348 2549 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2550 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2551 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 2552 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 2553 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2554 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2555 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2556 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 2557 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2558 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 2559 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2560 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2561 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2562 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2563 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2564 #define RTC_CR_DCE ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 2565 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 2566 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2567 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2568 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2569 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 25:ac5b0a371348 2570 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2571 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2572 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2573
mbed_official 25:ac5b0a371348 2574 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 25:ac5b0a371348 2575 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2576 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 2577 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2578 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2579 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2580 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2581 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2582 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2583 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 2584 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 2585 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2586 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2587 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2588 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2589 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2590 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2591
mbed_official 25:ac5b0a371348 2592 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 25:ac5b0a371348 2593 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 25:ac5b0a371348 2594 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 25:ac5b0a371348 2595
mbed_official 25:ac5b0a371348 2596 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 25:ac5b0a371348 2597 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 25:ac5b0a371348 2598
mbed_official 25:ac5b0a371348 2599 /******************** Bits definition for RTC_CALIBR register ***************/
mbed_official 25:ac5b0a371348 2600 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 2601 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
mbed_official 25:ac5b0a371348 2602
mbed_official 25:ac5b0a371348 2603 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 25:ac5b0a371348 2604 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 2605 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 25:ac5b0a371348 2606 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 25:ac5b0a371348 2607 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 25:ac5b0a371348 2608 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 25:ac5b0a371348 2609 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 25:ac5b0a371348 2610 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 2611 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 2612 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 2613 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 2614 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 2615 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2616 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 25:ac5b0a371348 2617 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 2618 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2619 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 25:ac5b0a371348 2620 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2621 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2622 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2623 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 2624 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 2625 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 25:ac5b0a371348 2626 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2627 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 2628 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2629 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 25:ac5b0a371348 2630 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2631 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2632 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2633 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2634 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 2635 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 25:ac5b0a371348 2636 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2637 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2638 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 2639 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 25:ac5b0a371348 2640 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2641 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2642 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2643 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2644
mbed_official 25:ac5b0a371348 2645 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 25:ac5b0a371348 2646 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 2647 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 25:ac5b0a371348 2648 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 25:ac5b0a371348 2649 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 25:ac5b0a371348 2650 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 25:ac5b0a371348 2651 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 25:ac5b0a371348 2652 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 2653 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 2654 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 2655 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 2656 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 25:ac5b0a371348 2657 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2658 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 25:ac5b0a371348 2659 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 2660 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2661 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 25:ac5b0a371348 2662 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2663 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2664 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2665 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 2666 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 2667 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 25:ac5b0a371348 2668 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2669 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 2670 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2671 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 25:ac5b0a371348 2672 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2673 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2674 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2675 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2676 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 2677 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 25:ac5b0a371348 2678 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2679 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2680 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 2681 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 25:ac5b0a371348 2682 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2683 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2684 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2685 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2686
mbed_official 25:ac5b0a371348 2687 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 25:ac5b0a371348 2688 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 25:ac5b0a371348 2689
mbed_official 25:ac5b0a371348 2690 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 25:ac5b0a371348 2691 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 25:ac5b0a371348 2692
mbed_official 25:ac5b0a371348 2693 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 25:ac5b0a371348 2694 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 25:ac5b0a371348 2695 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 25:ac5b0a371348 2696
mbed_official 25:ac5b0a371348 2697 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 25:ac5b0a371348 2698 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 2699 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 25:ac5b0a371348 2700 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 25:ac5b0a371348 2701 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 2702 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 25:ac5b0a371348 2703 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2704 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2705 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2706 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 25:ac5b0a371348 2707 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 25:ac5b0a371348 2708 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2709 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 2710 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2711 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 25:ac5b0a371348 2712 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2713 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2714 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2715 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2716 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 25:ac5b0a371348 2717 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2718 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2719 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 2720 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 25:ac5b0a371348 2721 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2722 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2723 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2724 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2725
mbed_official 25:ac5b0a371348 2726 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 25:ac5b0a371348 2727 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 25:ac5b0a371348 2728 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 2729 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2730 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 2731 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2732 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 25:ac5b0a371348 2733 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2734 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2735 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2736 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2737 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 25:ac5b0a371348 2738 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2739 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2740 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 25:ac5b0a371348 2741 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2742 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2743 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2744 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2745
mbed_official 25:ac5b0a371348 2746 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 25:ac5b0a371348 2747 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 25:ac5b0a371348 2748
mbed_official 25:ac5b0a371348 2749 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 25:ac5b0a371348 2750 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 2751 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2752 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 2753 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 25:ac5b0a371348 2754 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2755 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2756 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2757 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2758 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2759 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 2760 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 25:ac5b0a371348 2761 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 2762 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2763
mbed_official 25:ac5b0a371348 2764 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 25:ac5b0a371348 2765 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 2766 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
mbed_official 25:ac5b0a371348 2767 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 2768 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 25:ac5b0a371348 2769 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 25:ac5b0a371348 2770 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 25:ac5b0a371348 2771 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 25:ac5b0a371348 2772 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 25:ac5b0a371348 2773 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 2774 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 2775 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 25:ac5b0a371348 2776 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 25:ac5b0a371348 2777 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 25:ac5b0a371348 2778 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 2779 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 25:ac5b0a371348 2780 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 2781 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 2782 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2783 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2784 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2785
mbed_official 25:ac5b0a371348 2786 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 25:ac5b0a371348 2787 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 25:ac5b0a371348 2788 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 2789 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 2790 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 2791 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 2792 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 25:ac5b0a371348 2793
mbed_official 25:ac5b0a371348 2794 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 25:ac5b0a371348 2795 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 25:ac5b0a371348 2796 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 25:ac5b0a371348 2797 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 2798 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 2799 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 25:ac5b0a371348 2800 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 25:ac5b0a371348 2801
mbed_official 25:ac5b0a371348 2802 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 25:ac5b0a371348 2803 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2804
mbed_official 25:ac5b0a371348 2805 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 25:ac5b0a371348 2806 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2807
mbed_official 25:ac5b0a371348 2808 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 25:ac5b0a371348 2809 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2810
mbed_official 25:ac5b0a371348 2811 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 25:ac5b0a371348 2812 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2813
mbed_official 25:ac5b0a371348 2814 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 25:ac5b0a371348 2815 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2816
mbed_official 25:ac5b0a371348 2817 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 25:ac5b0a371348 2818 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2819
mbed_official 25:ac5b0a371348 2820 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 25:ac5b0a371348 2821 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2822
mbed_official 25:ac5b0a371348 2823 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 25:ac5b0a371348 2824 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2825
mbed_official 25:ac5b0a371348 2826 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 25:ac5b0a371348 2827 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2828
mbed_official 25:ac5b0a371348 2829 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 25:ac5b0a371348 2830 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2831
mbed_official 25:ac5b0a371348 2832 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 25:ac5b0a371348 2833 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2834
mbed_official 25:ac5b0a371348 2835 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 25:ac5b0a371348 2836 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2837
mbed_official 25:ac5b0a371348 2838 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 25:ac5b0a371348 2839 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2840
mbed_official 25:ac5b0a371348 2841 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 25:ac5b0a371348 2842 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2843
mbed_official 25:ac5b0a371348 2844 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 25:ac5b0a371348 2845 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2846
mbed_official 25:ac5b0a371348 2847 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 25:ac5b0a371348 2848 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2849
mbed_official 25:ac5b0a371348 2850 /******************** Bits definition for RTC_BKP16R register ***************/
mbed_official 25:ac5b0a371348 2851 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2852
mbed_official 25:ac5b0a371348 2853 /******************** Bits definition for RTC_BKP17R register ***************/
mbed_official 25:ac5b0a371348 2854 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2855
mbed_official 25:ac5b0a371348 2856 /******************** Bits definition for RTC_BKP18R register ***************/
mbed_official 25:ac5b0a371348 2857 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2858
mbed_official 25:ac5b0a371348 2859 /******************** Bits definition for RTC_BKP19R register ***************/
mbed_official 25:ac5b0a371348 2860 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
mbed_official 25:ac5b0a371348 2861
mbed_official 25:ac5b0a371348 2862 /******************************************************************************/
mbed_official 25:ac5b0a371348 2863 /* */
mbed_official 25:ac5b0a371348 2864 /* Serial Peripheral Interface */
mbed_official 25:ac5b0a371348 2865 /* */
mbed_official 25:ac5b0a371348 2866 /******************************************************************************/
mbed_official 25:ac5b0a371348 2867 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 25:ac5b0a371348 2868 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
mbed_official 25:ac5b0a371348 2869 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
mbed_official 25:ac5b0a371348 2870 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
mbed_official 25:ac5b0a371348 2871
mbed_official 25:ac5b0a371348 2872 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
mbed_official 25:ac5b0a371348 2873 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 2874 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 2875 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 2876
mbed_official 25:ac5b0a371348 2877 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
mbed_official 25:ac5b0a371348 2878 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
mbed_official 25:ac5b0a371348 2879 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
mbed_official 25:ac5b0a371348 2880 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
mbed_official 25:ac5b0a371348 2881 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
mbed_official 25:ac5b0a371348 2882 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
mbed_official 25:ac5b0a371348 2883 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
mbed_official 25:ac5b0a371348 2884 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
mbed_official 25:ac5b0a371348 2885 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
mbed_official 25:ac5b0a371348 2886 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
mbed_official 25:ac5b0a371348 2887
mbed_official 25:ac5b0a371348 2888 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 25:ac5b0a371348 2889 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
mbed_official 25:ac5b0a371348 2890 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
mbed_official 25:ac5b0a371348 2891 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
mbed_official 25:ac5b0a371348 2892 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
mbed_official 25:ac5b0a371348 2893 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
mbed_official 25:ac5b0a371348 2894 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
mbed_official 25:ac5b0a371348 2895 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
mbed_official 25:ac5b0a371348 2896
mbed_official 25:ac5b0a371348 2897 /******************** Bit definition for SPI_SR register ********************/
mbed_official 25:ac5b0a371348 2898 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
mbed_official 25:ac5b0a371348 2899 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
mbed_official 25:ac5b0a371348 2900 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
mbed_official 25:ac5b0a371348 2901 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
mbed_official 25:ac5b0a371348 2902 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
mbed_official 25:ac5b0a371348 2903 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
mbed_official 25:ac5b0a371348 2904 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
mbed_official 25:ac5b0a371348 2905 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
mbed_official 25:ac5b0a371348 2906 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
mbed_official 25:ac5b0a371348 2907
mbed_official 25:ac5b0a371348 2908 /******************** Bit definition for SPI_DR register ********************/
mbed_official 25:ac5b0a371348 2909 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
mbed_official 25:ac5b0a371348 2910
mbed_official 25:ac5b0a371348 2911 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 25:ac5b0a371348 2912 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
mbed_official 25:ac5b0a371348 2913
mbed_official 25:ac5b0a371348 2914 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 25:ac5b0a371348 2915 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
mbed_official 25:ac5b0a371348 2916
mbed_official 25:ac5b0a371348 2917 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 25:ac5b0a371348 2918 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
mbed_official 25:ac5b0a371348 2919
mbed_official 25:ac5b0a371348 2920 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 25:ac5b0a371348 2921 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 25:ac5b0a371348 2922
mbed_official 25:ac5b0a371348 2923 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 25:ac5b0a371348 2924 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 2925 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 2926
mbed_official 25:ac5b0a371348 2927 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 25:ac5b0a371348 2928
mbed_official 25:ac5b0a371348 2929 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 25:ac5b0a371348 2930 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 2931 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 2932
mbed_official 25:ac5b0a371348 2933 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 25:ac5b0a371348 2934
mbed_official 25:ac5b0a371348 2935 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 25:ac5b0a371348 2936 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 2937 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 2938
mbed_official 25:ac5b0a371348 2939 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 25:ac5b0a371348 2940 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 25:ac5b0a371348 2941
mbed_official 25:ac5b0a371348 2942 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 25:ac5b0a371348 2943 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 25:ac5b0a371348 2944 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 25:ac5b0a371348 2945 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 25:ac5b0a371348 2946
mbed_official 25:ac5b0a371348 2947 /******************************************************************************/
mbed_official 25:ac5b0a371348 2948 /* */
mbed_official 25:ac5b0a371348 2949 /* SYSCFG */
mbed_official 25:ac5b0a371348 2950 /* */
mbed_official 25:ac5b0a371348 2951 /******************************************************************************/
mbed_official 25:ac5b0a371348 2952 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
mbed_official 25:ac5b0a371348 2953 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
mbed_official 25:ac5b0a371348 2954 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 2955 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 2956 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 2957
mbed_official 25:ac5b0a371348 2958 /****************** Bit definition for SYSCFG_PMC register ******************/
mbed_official 25:ac5b0a371348 2959 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 25:ac5b0a371348 2960
mbed_official 25:ac5b0a371348 2961 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 25:ac5b0a371348 2962 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
mbed_official 25:ac5b0a371348 2963 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
mbed_official 25:ac5b0a371348 2964 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
mbed_official 25:ac5b0a371348 2965 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
mbed_official 25:ac5b0a371348 2966 /**
mbed_official 25:ac5b0a371348 2967 * @brief EXTI0 configuration
mbed_official 25:ac5b0a371348 2968 */
mbed_official 25:ac5b0a371348 2969 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
mbed_official 25:ac5b0a371348 2970 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
mbed_official 25:ac5b0a371348 2971 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
mbed_official 25:ac5b0a371348 2972 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
mbed_official 25:ac5b0a371348 2973
mbed_official 25:ac5b0a371348 2974 /**
mbed_official 25:ac5b0a371348 2975 * @brief EXTI1 configuration
mbed_official 25:ac5b0a371348 2976 */
mbed_official 25:ac5b0a371348 2977 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
mbed_official 25:ac5b0a371348 2978 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
mbed_official 25:ac5b0a371348 2979 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
mbed_official 25:ac5b0a371348 2980 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
mbed_official 25:ac5b0a371348 2981
mbed_official 25:ac5b0a371348 2982 /**
mbed_official 25:ac5b0a371348 2983 * @brief EXTI2 configuration
mbed_official 25:ac5b0a371348 2984 */
mbed_official 25:ac5b0a371348 2985 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
mbed_official 25:ac5b0a371348 2986 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
mbed_official 25:ac5b0a371348 2987 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
mbed_official 25:ac5b0a371348 2988 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
mbed_official 25:ac5b0a371348 2989
mbed_official 25:ac5b0a371348 2990 /**
mbed_official 25:ac5b0a371348 2991 * @brief EXTI3 configuration
mbed_official 25:ac5b0a371348 2992 */
mbed_official 25:ac5b0a371348 2993 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
mbed_official 25:ac5b0a371348 2994 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
mbed_official 25:ac5b0a371348 2995 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
mbed_official 25:ac5b0a371348 2996 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
mbed_official 25:ac5b0a371348 2997
mbed_official 25:ac5b0a371348 2998 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official 25:ac5b0a371348 2999 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
mbed_official 25:ac5b0a371348 3000 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
mbed_official 25:ac5b0a371348 3001 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
mbed_official 25:ac5b0a371348 3002 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
mbed_official 25:ac5b0a371348 3003 /**
mbed_official 25:ac5b0a371348 3004 * @brief EXTI4 configuration
mbed_official 25:ac5b0a371348 3005 */
mbed_official 25:ac5b0a371348 3006 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
mbed_official 25:ac5b0a371348 3007 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
mbed_official 25:ac5b0a371348 3008 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
mbed_official 25:ac5b0a371348 3009 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
mbed_official 25:ac5b0a371348 3010
mbed_official 25:ac5b0a371348 3011 /**
mbed_official 25:ac5b0a371348 3012 * @brief EXTI5 configuration
mbed_official 25:ac5b0a371348 3013 */
mbed_official 25:ac5b0a371348 3014 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
mbed_official 25:ac5b0a371348 3015 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
mbed_official 25:ac5b0a371348 3016 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
mbed_official 25:ac5b0a371348 3017 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
mbed_official 25:ac5b0a371348 3018
mbed_official 25:ac5b0a371348 3019 /**
mbed_official 25:ac5b0a371348 3020 * @brief EXTI6 configuration
mbed_official 25:ac5b0a371348 3021 */
mbed_official 25:ac5b0a371348 3022 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
mbed_official 25:ac5b0a371348 3023 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
mbed_official 25:ac5b0a371348 3024 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
mbed_official 25:ac5b0a371348 3025 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
mbed_official 25:ac5b0a371348 3026
mbed_official 25:ac5b0a371348 3027 /**
mbed_official 25:ac5b0a371348 3028 * @brief EXTI7 configuration
mbed_official 25:ac5b0a371348 3029 */
mbed_official 25:ac5b0a371348 3030 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
mbed_official 25:ac5b0a371348 3031 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
mbed_official 25:ac5b0a371348 3032 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
mbed_official 25:ac5b0a371348 3033 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
mbed_official 25:ac5b0a371348 3034
mbed_official 25:ac5b0a371348 3035
mbed_official 25:ac5b0a371348 3036 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official 25:ac5b0a371348 3037 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
mbed_official 25:ac5b0a371348 3038 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
mbed_official 25:ac5b0a371348 3039 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
mbed_official 25:ac5b0a371348 3040 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
mbed_official 25:ac5b0a371348 3041
mbed_official 25:ac5b0a371348 3042 /**
mbed_official 25:ac5b0a371348 3043 * @brief EXTI8 configuration
mbed_official 25:ac5b0a371348 3044 */
mbed_official 25:ac5b0a371348 3045 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
mbed_official 25:ac5b0a371348 3046 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
mbed_official 25:ac5b0a371348 3047 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
mbed_official 25:ac5b0a371348 3048 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
mbed_official 25:ac5b0a371348 3049
mbed_official 25:ac5b0a371348 3050 /**
mbed_official 25:ac5b0a371348 3051 * @brief EXTI9 configuration
mbed_official 25:ac5b0a371348 3052 */
mbed_official 25:ac5b0a371348 3053 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
mbed_official 25:ac5b0a371348 3054 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
mbed_official 25:ac5b0a371348 3055 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
mbed_official 25:ac5b0a371348 3056 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
mbed_official 25:ac5b0a371348 3057
mbed_official 25:ac5b0a371348 3058 /**
mbed_official 25:ac5b0a371348 3059 * @brief EXTI10 configuration
mbed_official 25:ac5b0a371348 3060 */
mbed_official 25:ac5b0a371348 3061 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
mbed_official 25:ac5b0a371348 3062 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
mbed_official 25:ac5b0a371348 3063 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
mbed_official 25:ac5b0a371348 3064 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
mbed_official 25:ac5b0a371348 3065
mbed_official 25:ac5b0a371348 3066 /**
mbed_official 25:ac5b0a371348 3067 * @brief EXTI11 configuration
mbed_official 25:ac5b0a371348 3068 */
mbed_official 25:ac5b0a371348 3069 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
mbed_official 25:ac5b0a371348 3070 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
mbed_official 25:ac5b0a371348 3071 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
mbed_official 25:ac5b0a371348 3072 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
mbed_official 25:ac5b0a371348 3073
mbed_official 25:ac5b0a371348 3074 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
mbed_official 25:ac5b0a371348 3075 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
mbed_official 25:ac5b0a371348 3076 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
mbed_official 25:ac5b0a371348 3077 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
mbed_official 25:ac5b0a371348 3078 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
mbed_official 25:ac5b0a371348 3079 /**
mbed_official 25:ac5b0a371348 3080 * @brief EXTI12 configuration
mbed_official 25:ac5b0a371348 3081 */
mbed_official 25:ac5b0a371348 3082 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
mbed_official 25:ac5b0a371348 3083 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
mbed_official 25:ac5b0a371348 3084 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
mbed_official 25:ac5b0a371348 3085 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
mbed_official 25:ac5b0a371348 3086
mbed_official 25:ac5b0a371348 3087 /**
mbed_official 25:ac5b0a371348 3088 * @brief EXTI13 configuration
mbed_official 25:ac5b0a371348 3089 */
mbed_official 25:ac5b0a371348 3090 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
mbed_official 25:ac5b0a371348 3091 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
mbed_official 25:ac5b0a371348 3092 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
mbed_official 25:ac5b0a371348 3093 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
mbed_official 25:ac5b0a371348 3094
mbed_official 25:ac5b0a371348 3095 /**
mbed_official 25:ac5b0a371348 3096 * @brief EXTI14 configuration
mbed_official 25:ac5b0a371348 3097 */
mbed_official 25:ac5b0a371348 3098 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
mbed_official 25:ac5b0a371348 3099 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
mbed_official 25:ac5b0a371348 3100 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
mbed_official 25:ac5b0a371348 3101 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
mbed_official 25:ac5b0a371348 3102
mbed_official 25:ac5b0a371348 3103 /**
mbed_official 25:ac5b0a371348 3104 * @brief EXTI15 configuration
mbed_official 25:ac5b0a371348 3105 */
mbed_official 25:ac5b0a371348 3106 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
mbed_official 25:ac5b0a371348 3107 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
mbed_official 25:ac5b0a371348 3108 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
mbed_official 25:ac5b0a371348 3109 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
mbed_official 25:ac5b0a371348 3110
mbed_official 25:ac5b0a371348 3111 /****************** Bit definition for SYSCFG_CMPCR register ****************/
mbed_official 25:ac5b0a371348 3112 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
mbed_official 25:ac5b0a371348 3113 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
mbed_official 25:ac5b0a371348 3114
mbed_official 25:ac5b0a371348 3115 /****************** Bit definition for SYSCFG_CFGR register *****************/
mbed_official 25:ac5b0a371348 3116 #define SYSCFG_CFGR_FMPI2C1_SCL ((uint32_t)0x00000001) /*!<FM+ drive capability for FMPI2C1_SCL pin */
mbed_official 25:ac5b0a371348 3117 #define SYSCFG_CFGR_FMPI2C1_SDA ((uint32_t)0x00000002) /*!<FM+ drive capability for FMPI2C1_SDA pin */
mbed_official 25:ac5b0a371348 3118
mbed_official 25:ac5b0a371348 3119 /****************** Bit definition for SYSCFG_CFGR2 register *****************/
mbed_official 25:ac5b0a371348 3120 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!<Core Lockup lock */
mbed_official 25:ac5b0a371348 3121 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!<PVD Lock */
mbed_official 25:ac5b0a371348 3122
mbed_official 25:ac5b0a371348 3123 /******************************************************************************/
mbed_official 25:ac5b0a371348 3124 /* */
mbed_official 25:ac5b0a371348 3125 /* TIM */
mbed_official 25:ac5b0a371348 3126 /* */
mbed_official 25:ac5b0a371348 3127 /******************************************************************************/
mbed_official 25:ac5b0a371348 3128 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 25:ac5b0a371348 3129 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
mbed_official 25:ac5b0a371348 3130 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
mbed_official 25:ac5b0a371348 3131 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
mbed_official 25:ac5b0a371348 3132 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
mbed_official 25:ac5b0a371348 3133 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
mbed_official 25:ac5b0a371348 3134
mbed_official 25:ac5b0a371348 3135 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 25:ac5b0a371348 3136 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3137 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3138
mbed_official 25:ac5b0a371348 3139 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
mbed_official 25:ac5b0a371348 3140
mbed_official 25:ac5b0a371348 3141 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
mbed_official 25:ac5b0a371348 3142 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3143 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3144
mbed_official 25:ac5b0a371348 3145 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 25:ac5b0a371348 3146 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
mbed_official 25:ac5b0a371348 3147 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
mbed_official 25:ac5b0a371348 3148 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
mbed_official 25:ac5b0a371348 3149
mbed_official 25:ac5b0a371348 3150 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 25:ac5b0a371348 3151 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3152 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3153 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3154
mbed_official 25:ac5b0a371348 3155 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
mbed_official 25:ac5b0a371348 3156 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 25:ac5b0a371348 3157 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 25:ac5b0a371348 3158 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 25:ac5b0a371348 3159 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 25:ac5b0a371348 3160 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 25:ac5b0a371348 3161 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 25:ac5b0a371348 3162 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 25:ac5b0a371348 3163
mbed_official 25:ac5b0a371348 3164 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 25:ac5b0a371348 3165 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 25:ac5b0a371348 3166 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3167 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3168 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3169
mbed_official 25:ac5b0a371348 3170 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 25:ac5b0a371348 3171 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3172 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3173 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3174
mbed_official 25:ac5b0a371348 3175 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
mbed_official 25:ac5b0a371348 3176
mbed_official 25:ac5b0a371348 3177 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 25:ac5b0a371348 3178 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3179 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3180 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3181 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3182
mbed_official 25:ac5b0a371348 3183 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 25:ac5b0a371348 3184 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3185 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3186
mbed_official 25:ac5b0a371348 3187 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
mbed_official 25:ac5b0a371348 3188 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
mbed_official 25:ac5b0a371348 3189
mbed_official 25:ac5b0a371348 3190 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 25:ac5b0a371348 3191 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
mbed_official 25:ac5b0a371348 3192 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 25:ac5b0a371348 3193 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 25:ac5b0a371348 3194 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 25:ac5b0a371348 3195 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 25:ac5b0a371348 3196 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
mbed_official 25:ac5b0a371348 3197 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
mbed_official 25:ac5b0a371348 3198 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
mbed_official 25:ac5b0a371348 3199 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
mbed_official 25:ac5b0a371348 3200 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 25:ac5b0a371348 3201 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 25:ac5b0a371348 3202 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 25:ac5b0a371348 3203 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 25:ac5b0a371348 3204 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
mbed_official 25:ac5b0a371348 3205 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
mbed_official 25:ac5b0a371348 3206
mbed_official 25:ac5b0a371348 3207 /******************** Bit definition for TIM_SR register ********************/
mbed_official 25:ac5b0a371348 3208 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
mbed_official 25:ac5b0a371348 3209 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 25:ac5b0a371348 3210 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 25:ac5b0a371348 3211 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 25:ac5b0a371348 3212 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 25:ac5b0a371348 3213 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
mbed_official 25:ac5b0a371348 3214 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
mbed_official 25:ac5b0a371348 3215 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
mbed_official 25:ac5b0a371348 3216 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 25:ac5b0a371348 3217 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 25:ac5b0a371348 3218 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 25:ac5b0a371348 3219 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 25:ac5b0a371348 3220
mbed_official 25:ac5b0a371348 3221 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 25:ac5b0a371348 3222 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
mbed_official 25:ac5b0a371348 3223 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
mbed_official 25:ac5b0a371348 3224 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
mbed_official 25:ac5b0a371348 3225 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
mbed_official 25:ac5b0a371348 3226 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
mbed_official 25:ac5b0a371348 3227 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
mbed_official 25:ac5b0a371348 3228 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
mbed_official 25:ac5b0a371348 3229 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
mbed_official 25:ac5b0a371348 3230
mbed_official 25:ac5b0a371348 3231 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 25:ac5b0a371348 3232 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 25:ac5b0a371348 3233 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3234 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3235
mbed_official 25:ac5b0a371348 3236 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
mbed_official 25:ac5b0a371348 3237 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
mbed_official 25:ac5b0a371348 3238
mbed_official 25:ac5b0a371348 3239 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 25:ac5b0a371348 3240 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3241 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3242 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3243
mbed_official 25:ac5b0a371348 3244 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
mbed_official 25:ac5b0a371348 3245
mbed_official 25:ac5b0a371348 3246 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 25:ac5b0a371348 3247 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3248 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3249
mbed_official 25:ac5b0a371348 3250 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
mbed_official 25:ac5b0a371348 3251 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
mbed_official 25:ac5b0a371348 3252
mbed_official 25:ac5b0a371348 3253 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 25:ac5b0a371348 3254 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3255 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3256 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3257
mbed_official 25:ac5b0a371348 3258 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
mbed_official 25:ac5b0a371348 3259
mbed_official 25:ac5b0a371348 3260 /*----------------------------------------------------------------------------*/
mbed_official 25:ac5b0a371348 3261
mbed_official 25:ac5b0a371348 3262 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 25:ac5b0a371348 3263 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3264 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3265
mbed_official 25:ac5b0a371348 3266 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 25:ac5b0a371348 3267 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3268 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3269 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3270 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3271
mbed_official 25:ac5b0a371348 3272 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 25:ac5b0a371348 3273 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3274 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3275
mbed_official 25:ac5b0a371348 3276 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 25:ac5b0a371348 3277 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3278 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3279 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3280 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3281
mbed_official 25:ac5b0a371348 3282 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 25:ac5b0a371348 3283 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 25:ac5b0a371348 3284 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3285 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3286
mbed_official 25:ac5b0a371348 3287 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
mbed_official 25:ac5b0a371348 3288 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
mbed_official 25:ac5b0a371348 3289
mbed_official 25:ac5b0a371348 3290 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 25:ac5b0a371348 3291 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3292 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3293 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3294
mbed_official 25:ac5b0a371348 3295 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
mbed_official 25:ac5b0a371348 3296
mbed_official 25:ac5b0a371348 3297 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 25:ac5b0a371348 3298 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3299 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3300
mbed_official 25:ac5b0a371348 3301 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
mbed_official 25:ac5b0a371348 3302 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
mbed_official 25:ac5b0a371348 3303
mbed_official 25:ac5b0a371348 3304 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 25:ac5b0a371348 3305 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3306 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3307 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3308
mbed_official 25:ac5b0a371348 3309 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
mbed_official 25:ac5b0a371348 3310
mbed_official 25:ac5b0a371348 3311 /*----------------------------------------------------------------------------*/
mbed_official 25:ac5b0a371348 3312
mbed_official 25:ac5b0a371348 3313 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 25:ac5b0a371348 3314 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3315 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3316
mbed_official 25:ac5b0a371348 3317 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 25:ac5b0a371348 3318 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3319 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3320 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3321 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3322
mbed_official 25:ac5b0a371348 3323 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 25:ac5b0a371348 3324 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3325 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3326
mbed_official 25:ac5b0a371348 3327 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 25:ac5b0a371348 3328 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3329 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3330 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3331 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3332
mbed_official 25:ac5b0a371348 3333 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 25:ac5b0a371348 3334 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
mbed_official 25:ac5b0a371348 3335 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
mbed_official 25:ac5b0a371348 3336 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 25:ac5b0a371348 3337 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 25:ac5b0a371348 3338 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
mbed_official 25:ac5b0a371348 3339 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
mbed_official 25:ac5b0a371348 3340 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 25:ac5b0a371348 3341 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 25:ac5b0a371348 3342 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
mbed_official 25:ac5b0a371348 3343 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
mbed_official 25:ac5b0a371348 3344 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 25:ac5b0a371348 3345 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 25:ac5b0a371348 3346 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
mbed_official 25:ac5b0a371348 3347 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
mbed_official 25:ac5b0a371348 3348 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 25:ac5b0a371348 3349
mbed_official 25:ac5b0a371348 3350 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 25:ac5b0a371348 3351 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
mbed_official 25:ac5b0a371348 3352
mbed_official 25:ac5b0a371348 3353 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 25:ac5b0a371348 3354 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
mbed_official 25:ac5b0a371348 3355
mbed_official 25:ac5b0a371348 3356 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 25:ac5b0a371348 3357 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
mbed_official 25:ac5b0a371348 3358
mbed_official 25:ac5b0a371348 3359 /******************* Bit definition for TIM_RCR register ********************/
mbed_official 25:ac5b0a371348 3360 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
mbed_official 25:ac5b0a371348 3361
mbed_official 25:ac5b0a371348 3362 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 25:ac5b0a371348 3363 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
mbed_official 25:ac5b0a371348 3364
mbed_official 25:ac5b0a371348 3365 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 25:ac5b0a371348 3366 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
mbed_official 25:ac5b0a371348 3367
mbed_official 25:ac5b0a371348 3368 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 25:ac5b0a371348 3369 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
mbed_official 25:ac5b0a371348 3370
mbed_official 25:ac5b0a371348 3371 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 25:ac5b0a371348 3372 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
mbed_official 25:ac5b0a371348 3373
mbed_official 25:ac5b0a371348 3374 /******************* Bit definition for TIM_BDTR register *******************/
mbed_official 25:ac5b0a371348 3375 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 25:ac5b0a371348 3376 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3377 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3378 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3379 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3380 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 3381 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 25:ac5b0a371348 3382 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 25:ac5b0a371348 3383 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
mbed_official 25:ac5b0a371348 3384
mbed_official 25:ac5b0a371348 3385 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 25:ac5b0a371348 3386 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3387 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3388
mbed_official 25:ac5b0a371348 3389 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
mbed_official 25:ac5b0a371348 3390 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
mbed_official 25:ac5b0a371348 3391 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
mbed_official 25:ac5b0a371348 3392 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
mbed_official 25:ac5b0a371348 3393 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
mbed_official 25:ac5b0a371348 3394 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
mbed_official 25:ac5b0a371348 3395
mbed_official 25:ac5b0a371348 3396 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 25:ac5b0a371348 3397 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 25:ac5b0a371348 3398 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3399 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3400 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3401 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3402 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 3403
mbed_official 25:ac5b0a371348 3404 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 25:ac5b0a371348 3405 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3406 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3407 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3408 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3409 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 3410
mbed_official 25:ac5b0a371348 3411 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 25:ac5b0a371348 3412 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
mbed_official 25:ac5b0a371348 3413
mbed_official 25:ac5b0a371348 3414 /******************* Bit definition for TIM_OR register *********************/
mbed_official 25:ac5b0a371348 3415 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
mbed_official 25:ac5b0a371348 3416 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3417 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3418
mbed_official 25:ac5b0a371348 3419 /******************************************************************************/
mbed_official 25:ac5b0a371348 3420 /* */
mbed_official 25:ac5b0a371348 3421 /* Low Power Timer (LPTIM) */
mbed_official 25:ac5b0a371348 3422 /* */
mbed_official 25:ac5b0a371348 3423 /******************************************************************************/
mbed_official 25:ac5b0a371348 3424 /****************** Bit definition for LPTIM_ISR register *******************/
mbed_official 25:ac5b0a371348 3425 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
mbed_official 25:ac5b0a371348 3426 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
mbed_official 25:ac5b0a371348 3427 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
mbed_official 25:ac5b0a371348 3428 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
mbed_official 25:ac5b0a371348 3429 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
mbed_official 25:ac5b0a371348 3430 #define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
mbed_official 25:ac5b0a371348 3431 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
mbed_official 25:ac5b0a371348 3432
mbed_official 25:ac5b0a371348 3433 /****************** Bit definition for LPTIM_ICR register *******************/
mbed_official 25:ac5b0a371348 3434 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
mbed_official 25:ac5b0a371348 3435 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
mbed_official 25:ac5b0a371348 3436 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
mbed_official 25:ac5b0a371348 3437 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
mbed_official 25:ac5b0a371348 3438 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
mbed_official 25:ac5b0a371348 3439 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
mbed_official 25:ac5b0a371348 3440 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
mbed_official 25:ac5b0a371348 3441
mbed_official 25:ac5b0a371348 3442 /****************** Bit definition for LPTIM_IER register ********************/
mbed_official 25:ac5b0a371348 3443 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
mbed_official 25:ac5b0a371348 3444 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
mbed_official 25:ac5b0a371348 3445 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
mbed_official 25:ac5b0a371348 3446 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
mbed_official 25:ac5b0a371348 3447 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
mbed_official 25:ac5b0a371348 3448 #define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
mbed_official 25:ac5b0a371348 3449 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
mbed_official 25:ac5b0a371348 3450
mbed_official 25:ac5b0a371348 3451 /****************** Bit definition for LPTIM_CFGR register *******************/
mbed_official 25:ac5b0a371348 3452 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
mbed_official 25:ac5b0a371348 3453
mbed_official 25:ac5b0a371348 3454 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
mbed_official 25:ac5b0a371348 3455 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 3456 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 3457
mbed_official 25:ac5b0a371348 3458 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
mbed_official 25:ac5b0a371348 3459 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 3460 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 3461
mbed_official 25:ac5b0a371348 3462 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
mbed_official 25:ac5b0a371348 3463 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 3464 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 3465
mbed_official 25:ac5b0a371348 3466 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
mbed_official 25:ac5b0a371348 3467 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 3468 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 3469 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 25:ac5b0a371348 3470
mbed_official 25:ac5b0a371348 3471 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
mbed_official 25:ac5b0a371348 3472 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 3473 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 3474 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 25:ac5b0a371348 3475
mbed_official 25:ac5b0a371348 3476 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
mbed_official 25:ac5b0a371348 3477 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 3478 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 3479
mbed_official 25:ac5b0a371348 3480 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
mbed_official 25:ac5b0a371348 3481 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
mbed_official 25:ac5b0a371348 3482 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
mbed_official 25:ac5b0a371348 3483 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
mbed_official 25:ac5b0a371348 3484 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
mbed_official 25:ac5b0a371348 3485 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
mbed_official 25:ac5b0a371348 3486
mbed_official 25:ac5b0a371348 3487 /****************** Bit definition for LPTIM_CR register ********************/
mbed_official 25:ac5b0a371348 3488 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
mbed_official 25:ac5b0a371348 3489 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /*!< Timer start in single mode */
mbed_official 25:ac5b0a371348 3490 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
mbed_official 25:ac5b0a371348 3491
mbed_official 25:ac5b0a371348 3492 /****************** Bit definition for LPTIM_CMP register *******************/
mbed_official 25:ac5b0a371348 3493 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
mbed_official 25:ac5b0a371348 3494
mbed_official 25:ac5b0a371348 3495 /****************** Bit definition for LPTIM_ARR register *******************/
mbed_official 25:ac5b0a371348 3496 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
mbed_official 25:ac5b0a371348 3497
mbed_official 25:ac5b0a371348 3498 /****************** Bit definition for LPTIM_CNT register *******************/
mbed_official 25:ac5b0a371348 3499 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
mbed_official 25:ac5b0a371348 3500
mbed_official 25:ac5b0a371348 3501 /****************** Bit definition for LPTIM_OR register *******************/
mbed_official 25:ac5b0a371348 3502 #define LPTIM_OR_OR ((uint32_t)0x00000003) /*!< LPTIMER[1:0] bits (Remap selection) */
mbed_official 25:ac5b0a371348 3503 #define LPTIM_OR_OR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 25:ac5b0a371348 3504 #define LPTIM_OR_OR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 25:ac5b0a371348 3505
mbed_official 25:ac5b0a371348 3506 /******************************************************************************/
mbed_official 25:ac5b0a371348 3507 /* */
mbed_official 25:ac5b0a371348 3508 /* Universal Synchronous Asynchronous Receiver Transmitter */
mbed_official 25:ac5b0a371348 3509 /* */
mbed_official 25:ac5b0a371348 3510 /******************************************************************************/
mbed_official 25:ac5b0a371348 3511 /******************* Bit definition for USART_SR register *******************/
mbed_official 25:ac5b0a371348 3512 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
mbed_official 25:ac5b0a371348 3513 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
mbed_official 25:ac5b0a371348 3514 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
mbed_official 25:ac5b0a371348 3515 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
mbed_official 25:ac5b0a371348 3516 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
mbed_official 25:ac5b0a371348 3517 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
mbed_official 25:ac5b0a371348 3518 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
mbed_official 25:ac5b0a371348 3519 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
mbed_official 25:ac5b0a371348 3520 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
mbed_official 25:ac5b0a371348 3521 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
mbed_official 25:ac5b0a371348 3522
mbed_official 25:ac5b0a371348 3523 /******************* Bit definition for USART_DR register *******************/
mbed_official 25:ac5b0a371348 3524 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
mbed_official 25:ac5b0a371348 3525
mbed_official 25:ac5b0a371348 3526 /****************** Bit definition for USART_BRR register *******************/
mbed_official 25:ac5b0a371348 3527 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
mbed_official 25:ac5b0a371348 3528 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
mbed_official 25:ac5b0a371348 3529
mbed_official 25:ac5b0a371348 3530 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 25:ac5b0a371348 3531 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
mbed_official 25:ac5b0a371348 3532 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
mbed_official 25:ac5b0a371348 3533 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
mbed_official 25:ac5b0a371348 3534 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
mbed_official 25:ac5b0a371348 3535 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
mbed_official 25:ac5b0a371348 3536 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
mbed_official 25:ac5b0a371348 3537 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
mbed_official 25:ac5b0a371348 3538 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
mbed_official 25:ac5b0a371348 3539 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
mbed_official 25:ac5b0a371348 3540 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
mbed_official 25:ac5b0a371348 3541 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
mbed_official 25:ac5b0a371348 3542 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
mbed_official 25:ac5b0a371348 3543 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
mbed_official 25:ac5b0a371348 3544 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
mbed_official 25:ac5b0a371348 3545 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
mbed_official 25:ac5b0a371348 3546
mbed_official 25:ac5b0a371348 3547 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 25:ac5b0a371348 3548 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
mbed_official 25:ac5b0a371348 3549 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
mbed_official 25:ac5b0a371348 3550 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
mbed_official 25:ac5b0a371348 3551 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
mbed_official 25:ac5b0a371348 3552 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
mbed_official 25:ac5b0a371348 3553 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
mbed_official 25:ac5b0a371348 3554 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
mbed_official 25:ac5b0a371348 3555
mbed_official 25:ac5b0a371348 3556 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
mbed_official 25:ac5b0a371348 3557 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3558 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3559
mbed_official 25:ac5b0a371348 3560 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
mbed_official 25:ac5b0a371348 3561
mbed_official 25:ac5b0a371348 3562 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 25:ac5b0a371348 3563 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
mbed_official 25:ac5b0a371348 3564 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
mbed_official 25:ac5b0a371348 3565 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
mbed_official 25:ac5b0a371348 3566 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
mbed_official 25:ac5b0a371348 3567 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
mbed_official 25:ac5b0a371348 3568 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
mbed_official 25:ac5b0a371348 3569 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
mbed_official 25:ac5b0a371348 3570 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
mbed_official 25:ac5b0a371348 3571 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
mbed_official 25:ac5b0a371348 3572 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
mbed_official 25:ac5b0a371348 3573 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
mbed_official 25:ac5b0a371348 3574 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
mbed_official 25:ac5b0a371348 3575
mbed_official 25:ac5b0a371348 3576 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 25:ac5b0a371348 3577 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
mbed_official 25:ac5b0a371348 3578 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3579 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3580 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3581 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3582 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 3583 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 25:ac5b0a371348 3584 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 25:ac5b0a371348 3585 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
mbed_official 25:ac5b0a371348 3586
mbed_official 25:ac5b0a371348 3587 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
mbed_official 25:ac5b0a371348 3588
mbed_official 25:ac5b0a371348 3589 /******************************************************************************/
mbed_official 25:ac5b0a371348 3590 /* */
mbed_official 25:ac5b0a371348 3591 /* Window WATCHDOG */
mbed_official 25:ac5b0a371348 3592 /* */
mbed_official 25:ac5b0a371348 3593 /******************************************************************************/
mbed_official 25:ac5b0a371348 3594 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 25:ac5b0a371348 3595 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 25:ac5b0a371348 3596 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3597 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3598 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3599 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3600 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 3601 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
mbed_official 25:ac5b0a371348 3602 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
mbed_official 25:ac5b0a371348 3603
mbed_official 25:ac5b0a371348 3604 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
mbed_official 25:ac5b0a371348 3605
mbed_official 25:ac5b0a371348 3606 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 25:ac5b0a371348 3607 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 25:ac5b0a371348 3608 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3609 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3610 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3611 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3612 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 25:ac5b0a371348 3613 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 25:ac5b0a371348 3614 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 25:ac5b0a371348 3615
mbed_official 25:ac5b0a371348 3616 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 25:ac5b0a371348 3617 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3618 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3619
mbed_official 25:ac5b0a371348 3620 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
mbed_official 25:ac5b0a371348 3621
mbed_official 25:ac5b0a371348 3622 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 25:ac5b0a371348 3623 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
mbed_official 25:ac5b0a371348 3624
mbed_official 25:ac5b0a371348 3625 /******************************************************************************/
mbed_official 25:ac5b0a371348 3626 /* */
mbed_official 25:ac5b0a371348 3627 /* Digital to Analog Converter */
mbed_official 25:ac5b0a371348 3628 /* */
mbed_official 25:ac5b0a371348 3629 /******************************************************************************/
mbed_official 25:ac5b0a371348 3630 /******************** Bit definition for DAC_CR register ********************/
mbed_official 25:ac5b0a371348 3631 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
mbed_official 25:ac5b0a371348 3632 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
mbed_official 25:ac5b0a371348 3633 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
mbed_official 25:ac5b0a371348 3634
mbed_official 25:ac5b0a371348 3635 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 25:ac5b0a371348 3636 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3637 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3638 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3639
mbed_official 25:ac5b0a371348 3640 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 25:ac5b0a371348 3641 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3642 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3643
mbed_official 25:ac5b0a371348 3644 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 25:ac5b0a371348 3645 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3646 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3647 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3648 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3649
mbed_official 25:ac5b0a371348 3650 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
mbed_official 25:ac5b0a371348 3651 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
mbed_official 25:ac5b0a371348 3652 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
mbed_official 25:ac5b0a371348 3653 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
mbed_official 25:ac5b0a371348 3654
mbed_official 25:ac5b0a371348 3655 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 25:ac5b0a371348 3656 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3657 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3658 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3659
mbed_official 25:ac5b0a371348 3660 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 25:ac5b0a371348 3661 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3662 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3663
mbed_official 25:ac5b0a371348 3664 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 25:ac5b0a371348 3665 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 25:ac5b0a371348 3666 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3667 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 25:ac5b0a371348 3668 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3669
mbed_official 25:ac5b0a371348 3670 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
mbed_official 25:ac5b0a371348 3671
mbed_official 25:ac5b0a371348 3672 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 25:ac5b0a371348 3673 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
mbed_official 25:ac5b0a371348 3674 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
mbed_official 25:ac5b0a371348 3675
mbed_official 25:ac5b0a371348 3676 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 25:ac5b0a371348 3677 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 25:ac5b0a371348 3678
mbed_official 25:ac5b0a371348 3679 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 25:ac5b0a371348 3680 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 25:ac5b0a371348 3681
mbed_official 25:ac5b0a371348 3682 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 25:ac5b0a371348 3683 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 25:ac5b0a371348 3684
mbed_official 25:ac5b0a371348 3685 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 25:ac5b0a371348 3686 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 25:ac5b0a371348 3687
mbed_official 25:ac5b0a371348 3688 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 25:ac5b0a371348 3689 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 25:ac5b0a371348 3690
mbed_official 25:ac5b0a371348 3691 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 25:ac5b0a371348 3692 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 25:ac5b0a371348 3693
mbed_official 25:ac5b0a371348 3694 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 25:ac5b0a371348 3695 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 25:ac5b0a371348 3696 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 25:ac5b0a371348 3697
mbed_official 25:ac5b0a371348 3698 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 25:ac5b0a371348 3699 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 25:ac5b0a371348 3700 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 25:ac5b0a371348 3701
mbed_official 25:ac5b0a371348 3702 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 25:ac5b0a371348 3703 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 25:ac5b0a371348 3704 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 25:ac5b0a371348 3705
mbed_official 25:ac5b0a371348 3706 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 25:ac5b0a371348 3707 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
mbed_official 25:ac5b0a371348 3708
mbed_official 25:ac5b0a371348 3709 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 25:ac5b0a371348 3710 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
mbed_official 25:ac5b0a371348 3711
mbed_official 25:ac5b0a371348 3712 /******************** Bit definition for DAC_SR register ********************/
mbed_official 25:ac5b0a371348 3713 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
mbed_official 25:ac5b0a371348 3714 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
mbed_official 25:ac5b0a371348 3715 /******************************************************************************/
mbed_official 25:ac5b0a371348 3716 /* */
mbed_official 25:ac5b0a371348 3717 /* DBG */
mbed_official 25:ac5b0a371348 3718 /* */
mbed_official 25:ac5b0a371348 3719 /******************************************************************************/
mbed_official 25:ac5b0a371348 3720 /******************** Bit definition for DBGMCU_IDCODE register *************/
mbed_official 25:ac5b0a371348 3721 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
mbed_official 25:ac5b0a371348 3722 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
mbed_official 25:ac5b0a371348 3723
mbed_official 25:ac5b0a371348 3724 /******************** Bit definition for DBGMCU_CR register *****************/
mbed_official 25:ac5b0a371348 3725 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 3726 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
mbed_official 25:ac5b0a371348 3727 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
mbed_official 25:ac5b0a371348 3728 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
mbed_official 25:ac5b0a371348 3729
mbed_official 25:ac5b0a371348 3730 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
mbed_official 25:ac5b0a371348 3731 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
mbed_official 25:ac5b0a371348 3732 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
mbed_official 25:ac5b0a371348 3733
mbed_official 25:ac5b0a371348 3734 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official 25:ac5b0a371348 3735 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
mbed_official 25:ac5b0a371348 3736 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
mbed_official 25:ac5b0a371348 3737 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
mbed_official 25:ac5b0a371348 3738 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
mbed_official 25:ac5b0a371348 3739 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
mbed_official 25:ac5b0a371348 3740 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
mbed_official 25:ac5b0a371348 3741 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
mbed_official 25:ac5b0a371348 3742 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
mbed_official 25:ac5b0a371348 3743 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
mbed_official 25:ac5b0a371348 3744
mbed_official 25:ac5b0a371348 3745 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official 25:ac5b0a371348 3746 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
mbed_official 25:ac5b0a371348 3747 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
mbed_official 25:ac5b0a371348 3748 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
mbed_official 25:ac5b0a371348 3749
mbed_official 25:ac5b0a371348 3750 /**
mbed_official 25:ac5b0a371348 3751 * @}
mbed_official 25:ac5b0a371348 3752 */
mbed_official 25:ac5b0a371348 3753
mbed_official 25:ac5b0a371348 3754 /**
mbed_official 25:ac5b0a371348 3755 * @}
mbed_official 25:ac5b0a371348 3756 */
mbed_official 25:ac5b0a371348 3757
mbed_official 25:ac5b0a371348 3758 /** @addtogroup Exported_macros
mbed_official 25:ac5b0a371348 3759 * @{
mbed_official 25:ac5b0a371348 3760 */
mbed_official 25:ac5b0a371348 3761
mbed_official 25:ac5b0a371348 3762 /******************************* ADC Instances ********************************/
mbed_official 25:ac5b0a371348 3763 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official 25:ac5b0a371348 3764
mbed_official 25:ac5b0a371348 3765 /******************************* CRC Instances ********************************/
mbed_official 25:ac5b0a371348 3766 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 25:ac5b0a371348 3767
mbed_official 25:ac5b0a371348 3768 /******************************* DAC Instances ********************************/
mbed_official 25:ac5b0a371348 3769 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 25:ac5b0a371348 3770
mbed_official 25:ac5b0a371348 3771 /******************************** DMA Instances *******************************/
mbed_official 25:ac5b0a371348 3772 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
mbed_official 25:ac5b0a371348 3773 ((INSTANCE) == DMA1_Stream1) || \
mbed_official 25:ac5b0a371348 3774 ((INSTANCE) == DMA1_Stream2) || \
mbed_official 25:ac5b0a371348 3775 ((INSTANCE) == DMA1_Stream3) || \
mbed_official 25:ac5b0a371348 3776 ((INSTANCE) == DMA1_Stream4) || \
mbed_official 25:ac5b0a371348 3777 ((INSTANCE) == DMA1_Stream5) || \
mbed_official 25:ac5b0a371348 3778 ((INSTANCE) == DMA1_Stream6) || \
mbed_official 25:ac5b0a371348 3779 ((INSTANCE) == DMA1_Stream7) || \
mbed_official 25:ac5b0a371348 3780 ((INSTANCE) == DMA2_Stream0) || \
mbed_official 25:ac5b0a371348 3781 ((INSTANCE) == DMA2_Stream1) || \
mbed_official 25:ac5b0a371348 3782 ((INSTANCE) == DMA2_Stream2) || \
mbed_official 25:ac5b0a371348 3783 ((INSTANCE) == DMA2_Stream3) || \
mbed_official 25:ac5b0a371348 3784 ((INSTANCE) == DMA2_Stream4) || \
mbed_official 25:ac5b0a371348 3785 ((INSTANCE) == DMA2_Stream5) || \
mbed_official 25:ac5b0a371348 3786 ((INSTANCE) == DMA2_Stream6) || \
mbed_official 25:ac5b0a371348 3787 ((INSTANCE) == DMA2_Stream7))
mbed_official 25:ac5b0a371348 3788
mbed_official 25:ac5b0a371348 3789 /******************************* GPIO Instances *******************************/
mbed_official 25:ac5b0a371348 3790 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 25:ac5b0a371348 3791 ((INSTANCE) == GPIOB) || \
mbed_official 25:ac5b0a371348 3792 ((INSTANCE) == GPIOC) || \
mbed_official 25:ac5b0a371348 3793 ((INSTANCE) == GPIOH))
mbed_official 25:ac5b0a371348 3794
mbed_official 25:ac5b0a371348 3795 /******************************** I2C Instances *******************************/
mbed_official 25:ac5b0a371348 3796 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 25:ac5b0a371348 3797 ((INSTANCE) == I2C2))
mbed_official 25:ac5b0a371348 3798 /******************************** I2S Instances *******************************/
mbed_official 25:ac5b0a371348 3799 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 25:ac5b0a371348 3800 ((INSTANCE) == SPI2) || \
mbed_official 25:ac5b0a371348 3801 ((INSTANCE) == SPI5))
mbed_official 25:ac5b0a371348 3802
mbed_official 25:ac5b0a371348 3803 /******************************* LPTIM Instances ******************************/
mbed_official 25:ac5b0a371348 3804 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
mbed_official 25:ac5b0a371348 3805
mbed_official 25:ac5b0a371348 3806 /******************************* RNG Instances ********************************/
mbed_official 25:ac5b0a371348 3807 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
mbed_official 25:ac5b0a371348 3808
mbed_official 25:ac5b0a371348 3809 /****************************** RTC Instances *********************************/
mbed_official 25:ac5b0a371348 3810 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 25:ac5b0a371348 3811
mbed_official 25:ac5b0a371348 3812 /******************************** SPI Instances *******************************/
mbed_official 25:ac5b0a371348 3813 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 25:ac5b0a371348 3814 ((INSTANCE) == SPI2) || \
mbed_official 25:ac5b0a371348 3815 ((INSTANCE) == SPI5))
mbed_official 25:ac5b0a371348 3816 /*************************** SPI Extended Instances ***************************/
mbed_official 25:ac5b0a371348 3817 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 25:ac5b0a371348 3818 ((INSTANCE) == SPI2) || \
mbed_official 25:ac5b0a371348 3819 ((INSTANCE) == SPI5))
mbed_official 25:ac5b0a371348 3820
mbed_official 25:ac5b0a371348 3821 /****************** TIM Instances : All supported instances *******************/
mbed_official 25:ac5b0a371348 3822 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3823 ((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3824 ((INSTANCE) == TIM6) || \
mbed_official 25:ac5b0a371348 3825 ((INSTANCE) == TIM9) || \
mbed_official 25:ac5b0a371348 3826 ((INSTANCE) == TIM11))
mbed_official 25:ac5b0a371348 3827
mbed_official 25:ac5b0a371348 3828 /************* TIM Instances : at least 1 capture/compare channel *************/
mbed_official 25:ac5b0a371348 3829 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3830 ((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3831 ((INSTANCE) == TIM9) || \
mbed_official 25:ac5b0a371348 3832 ((INSTANCE) == TIM11))
mbed_official 25:ac5b0a371348 3833
mbed_official 25:ac5b0a371348 3834 /************ TIM Instances : at least 2 capture/compare channels *************/
mbed_official 25:ac5b0a371348 3835 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3836 ((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3837 ((INSTANCE) == TIM9))
mbed_official 25:ac5b0a371348 3838
mbed_official 25:ac5b0a371348 3839 /************ TIM Instances : at least 3 capture/compare channels *************/
mbed_official 25:ac5b0a371348 3840 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3841 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3842
mbed_official 25:ac5b0a371348 3843 /************ TIM Instances : at least 4 capture/compare channels *************/
mbed_official 25:ac5b0a371348 3844 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3845 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3846
mbed_official 25:ac5b0a371348 3847 /******************** TIM Instances : Advanced-control timers *****************/
mbed_official 25:ac5b0a371348 3848 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
mbed_official 25:ac5b0a371348 3849
mbed_official 25:ac5b0a371348 3850 /******************* TIM Instances : Timer input XOR function *****************/
mbed_official 25:ac5b0a371348 3851 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3852 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3853
mbed_official 25:ac5b0a371348 3854 /****************** TIM Instances : DMA requests generation (UDE) *************/
mbed_official 25:ac5b0a371348 3855 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3856 ((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3857 ((INSTANCE) == TIM6))
mbed_official 25:ac5b0a371348 3858
mbed_official 25:ac5b0a371348 3859 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
mbed_official 25:ac5b0a371348 3860 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3861 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3862
mbed_official 25:ac5b0a371348 3863 /************ TIM Instances : DMA requests generation (COMDE) *****************/
mbed_official 25:ac5b0a371348 3864 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3865 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3866
mbed_official 25:ac5b0a371348 3867 /******************** TIM Instances : DMA burst feature ***********************/
mbed_official 25:ac5b0a371348 3868 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3869 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3870
mbed_official 25:ac5b0a371348 3871 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
mbed_official 25:ac5b0a371348 3872 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3873 ((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3874 ((INSTANCE) == TIM6) || \
mbed_official 25:ac5b0a371348 3875 ((INSTANCE) == TIM9))
mbed_official 25:ac5b0a371348 3876
mbed_official 25:ac5b0a371348 3877 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
mbed_official 25:ac5b0a371348 3878 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3879 ((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3880 ((INSTANCE) == TIM9))
mbed_official 25:ac5b0a371348 3881
mbed_official 25:ac5b0a371348 3882 /********************** TIM Instances : 32 bit Counter ************************/
mbed_official 25:ac5b0a371348 3883 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3884
mbed_official 25:ac5b0a371348 3885 /***************** TIM Instances : external trigger input availabe ************/
mbed_official 25:ac5b0a371348 3886 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3887 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3888
mbed_official 25:ac5b0a371348 3889 /****************** TIM Instances : remapping capability **********************/
mbed_official 25:ac5b0a371348 3890 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3891 ((INSTANCE) == TIM11))
mbed_official 25:ac5b0a371348 3892
mbed_official 25:ac5b0a371348 3893 /******************* TIM Instances : output(s) available **********************/
mbed_official 25:ac5b0a371348 3894 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 25:ac5b0a371348 3895 ((((INSTANCE) == TIM1) && \
mbed_official 25:ac5b0a371348 3896 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 25:ac5b0a371348 3897 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 25:ac5b0a371348 3898 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 25:ac5b0a371348 3899 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 25:ac5b0a371348 3900 || \
mbed_official 25:ac5b0a371348 3901 (((INSTANCE) == TIM5) && \
mbed_official 25:ac5b0a371348 3902 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 25:ac5b0a371348 3903 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 25:ac5b0a371348 3904 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 25:ac5b0a371348 3905 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 25:ac5b0a371348 3906 || \
mbed_official 25:ac5b0a371348 3907 (((INSTANCE) == TIM9) && \
mbed_official 25:ac5b0a371348 3908 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 25:ac5b0a371348 3909 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 25:ac5b0a371348 3910 || \
mbed_official 25:ac5b0a371348 3911 (((INSTANCE) == TIM11) && \
mbed_official 25:ac5b0a371348 3912 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 25:ac5b0a371348 3913
mbed_official 25:ac5b0a371348 3914 /************ TIM Instances : complementary output(s) available ***************/
mbed_official 25:ac5b0a371348 3915 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 25:ac5b0a371348 3916 ((((INSTANCE) == TIM1) && \
mbed_official 25:ac5b0a371348 3917 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 25:ac5b0a371348 3918 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 25:ac5b0a371348 3919 ((CHANNEL) == TIM_CHANNEL_3))))
mbed_official 25:ac5b0a371348 3920
mbed_official 25:ac5b0a371348 3921 /******************** USART Instances : Synchronous mode **********************/
mbed_official 25:ac5b0a371348 3922 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 25:ac5b0a371348 3923 ((INSTANCE) == USART2) || \
mbed_official 25:ac5b0a371348 3924 ((INSTANCE) == USART6))
mbed_official 25:ac5b0a371348 3925
mbed_official 25:ac5b0a371348 3926 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 25:ac5b0a371348 3927 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 25:ac5b0a371348 3928 ((INSTANCE) == USART2) || \
mbed_official 25:ac5b0a371348 3929 ((INSTANCE) == USART6))
mbed_official 25:ac5b0a371348 3930
mbed_official 25:ac5b0a371348 3931 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 25:ac5b0a371348 3932 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 25:ac5b0a371348 3933 ((INSTANCE) == USART2) || \
mbed_official 25:ac5b0a371348 3934 ((INSTANCE) == USART6))
mbed_official 25:ac5b0a371348 3935
mbed_official 25:ac5b0a371348 3936 /********************* UART Instances : Smard card mode ***********************/
mbed_official 25:ac5b0a371348 3937 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 25:ac5b0a371348 3938 ((INSTANCE) == USART2) || \
mbed_official 25:ac5b0a371348 3939 ((INSTANCE) == USART6))
mbed_official 25:ac5b0a371348 3940
mbed_official 25:ac5b0a371348 3941 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 25:ac5b0a371348 3942 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 25:ac5b0a371348 3943 ((INSTANCE) == USART2) || \
mbed_official 25:ac5b0a371348 3944 ((INSTANCE) == USART6))
mbed_official 25:ac5b0a371348 3945
mbed_official 25:ac5b0a371348 3946 /****************************** IWDG Instances ********************************/
mbed_official 25:ac5b0a371348 3947 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 25:ac5b0a371348 3948
mbed_official 25:ac5b0a371348 3949 /****************************** WWDG Instances ********************************/
mbed_official 25:ac5b0a371348 3950 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 25:ac5b0a371348 3951
mbed_official 25:ac5b0a371348 3952 /***************************** FMPI2C Instances *******************************/
mbed_official 25:ac5b0a371348 3953 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
mbed_official 25:ac5b0a371348 3954
mbed_official 25:ac5b0a371348 3955 /**
mbed_official 25:ac5b0a371348 3956 * @}
mbed_official 25:ac5b0a371348 3957 */
mbed_official 25:ac5b0a371348 3958
mbed_official 25:ac5b0a371348 3959 /**
mbed_official 25:ac5b0a371348 3960 * @}
mbed_official 25:ac5b0a371348 3961 */
mbed_official 25:ac5b0a371348 3962
mbed_official 25:ac5b0a371348 3963 /**
mbed_official 25:ac5b0a371348 3964 * @}
mbed_official 25:ac5b0a371348 3965 */
mbed_official 25:ac5b0a371348 3966
mbed_official 25:ac5b0a371348 3967 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 3968 }
mbed_official 25:ac5b0a371348 3969 #endif /* __cplusplus */
mbed_official 25:ac5b0a371348 3970
mbed_official 25:ac5b0a371348 3971 #endif /* __STM32F410xx_H */
mbed_official 25:ac5b0a371348 3972
mbed_official 25:ac5b0a371348 3973
mbed_official 25:ac5b0a371348 3974
mbed_official 25:ac5b0a371348 3975 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/