en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c@83:a036322b8637, 2016-03-07 (annotated)

Committer:
mbed_official
Date:
Mon Mar 07 10:00:14 2016 +0000
Revision:
83:a036322b8637
Parent:
0:9b334a45a8ff 
Synchronized with git revision ee20d03969aa5c570152f88e8f3d8a4739eed40b



Full URL: https://github.com/mbedmicro/mbed/commit/ee20d03969aa5c570152f88e8f3d8a4739eed40b/



[STM32F7] Update STM32F7Cube_FW version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f7xx_hal_pwr_ex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 83:a036322b8637 5 * @version V1.0.4
mbed_official 83:a036322b8637 6 * @date 09-December-2015
bogdanm 0:9b334a45a8ff 7 * @brief Extended PWR HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of PWR extension peripheral:
bogdanm 0:9b334a45a8ff 10 * + Peripheral Extended features functions
bogdanm 0:9b334a45a8ff 11 *
bogdanm 0:9b334a45a8ff 12 ******************************************************************************
bogdanm 0:9b334a45a8ff 13 * @attention
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 16 *
bogdanm 0:9b334a45a8ff 17 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 18 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 19 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 20 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 22 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 23 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 25 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 26 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 27 *
bogdanm 0:9b334a45a8ff 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 38 *
bogdanm 0:9b334a45a8ff 39 ******************************************************************************
bogdanm 0:9b334a45a8ff 40 */
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 43 #include "stm32f7xx_hal.h"
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45 /** @addtogroup STM32F7xx_HAL_Driver
bogdanm 0:9b334a45a8ff 46 * @{
bogdanm 0:9b334a45a8ff 47 */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @defgroup PWREx PWREx
bogdanm 0:9b334a45a8ff 50 * @brief PWR HAL module driver
bogdanm 0:9b334a45a8ff 51 * @{
bogdanm 0:9b334a45a8ff 52 */
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 #ifdef HAL_PWR_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 57 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58 /** @addtogroup PWREx_Private_Constants
bogdanm 0:9b334a45a8ff 59 * @{
bogdanm 0:9b334a45a8ff 60 */
bogdanm 0:9b334a45a8ff 61 #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
bogdanm 0:9b334a45a8ff 62 #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
bogdanm 0:9b334a45a8ff 63 #define PWR_BKPREG_TIMEOUT_VALUE 1000
bogdanm 0:9b334a45a8ff 64 #define PWR_VOSRDY_TIMEOUT_VALUE 1000
bogdanm 0:9b334a45a8ff 65 /**
bogdanm 0:9b334a45a8ff 66 * @}
bogdanm 0:9b334a45a8ff 67 */
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 70 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 71 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 72 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 73 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
bogdanm 0:9b334a45a8ff 74 * @{
bogdanm 0:9b334a45a8ff 75 */
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
bogdanm 0:9b334a45a8ff 78 * @brief Peripheral Extended features functions
bogdanm 0:9b334a45a8ff 79 *
bogdanm 0:9b334a45a8ff 80 @verbatim
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 ===============================================================================
bogdanm 0:9b334a45a8ff 83 ##### Peripheral extended features functions #####
bogdanm 0:9b334a45a8ff 84 ===============================================================================
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 *** Main and Backup Regulators configuration ***
bogdanm 0:9b334a45a8ff 87 ================================================
bogdanm 0:9b334a45a8ff 88 [..]
bogdanm 0:9b334a45a8ff 89 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
bogdanm 0:9b334a45a8ff 90 the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
bogdanm 0:9b334a45a8ff 91 retained even in Standby or VBAT mode when the low power backup regulator
bogdanm 0:9b334a45a8ff 92 is enabled. It can be considered as an internal EEPROM when VBAT is
bogdanm 0:9b334a45a8ff 93 always present. You can use the HAL_PWREx_EnableBkUpReg() function to
bogdanm 0:9b334a45a8ff 94 enable the low power backup regulator.
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
bogdanm 0:9b334a45a8ff 97 the backup SRAM is powered from VDD which replaces the VBAT power supply to
bogdanm 0:9b334a45a8ff 98 save battery life.
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 (+) The backup SRAM is not mass erased by a tamper event. It is read
bogdanm 0:9b334a45a8ff 101 protected to prevent confidential data, such as cryptographic private
bogdanm 0:9b334a45a8ff 102 key, from being accessed. The backup SRAM can be erased only through
bogdanm 0:9b334a45a8ff 103 the Flash interface when a protection level change from level 1 to
bogdanm 0:9b334a45a8ff 104 level 0 is requested.
bogdanm 0:9b334a45a8ff 105 -@- Refer to the description of Read protection (RDP) in the Flash
bogdanm 0:9b334a45a8ff 106 programming manual.
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 (+) The main internal regulator can be configured to have a tradeoff between
bogdanm 0:9b334a45a8ff 109 performance and power consumption when the device does not operate at
bogdanm 0:9b334a45a8ff 110 the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
bogdanm 0:9b334a45a8ff 111 macro which configure VOS bit in PWR_CR register
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 Refer to the product datasheets for more details.
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 *** FLASH Power Down configuration ****
bogdanm 0:9b334a45a8ff 116 =======================================
bogdanm 0:9b334a45a8ff 117 [..]
bogdanm 0:9b334a45a8ff 118 (+) By setting the FPDS bit in the PWR_CR register by using the
bogdanm 0:9b334a45a8ff 119 HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
bogdanm 0:9b334a45a8ff 120 down mode when the device enters Stop mode. When the Flash memory
bogdanm 0:9b334a45a8ff 121 is in power down mode, an additional startup delay is incurred when
bogdanm 0:9b334a45a8ff 122 waking up from Stop mode.
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 *** Over-Drive and Under-Drive configuration ****
bogdanm 0:9b334a45a8ff 125 =================================================
bogdanm 0:9b334a45a8ff 126 [..]
bogdanm 0:9b334a45a8ff 127 (+) In Run mode: the main regulator has 2 operating modes available:
bogdanm 0:9b334a45a8ff 128 (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
bogdanm 0:9b334a45a8ff 129 voltage scaling (scale 1, scale 2 or scale 3)
bogdanm 0:9b334a45a8ff 130 (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
bogdanm 0:9b334a45a8ff 131 higher frequency than the normal mode for a given voltage scaling (scale 1,
bogdanm 0:9b334a45a8ff 132 scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
bogdanm 0:9b334a45a8ff 133 disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
bogdanm 0:9b334a45a8ff 134 the sequence described in Reference manual.
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 (+) In Stop mode: the main regulator or low power regulator supplies a low power
bogdanm 0:9b334a45a8ff 137 voltage to the 1.2V domain, thus preserving the content of registers
bogdanm 0:9b334a45a8ff 138 and internal SRAM. 2 operating modes are available:
bogdanm 0:9b334a45a8ff 139 (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
bogdanm 0:9b334a45a8ff 140 available when the main regulator or the low power regulator is used in Scale 3 or
bogdanm 0:9b334a45a8ff 141 low voltage mode.
bogdanm 0:9b334a45a8ff 142 (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
bogdanm 0:9b334a45a8ff 143 available when the main regulator or the low power regulator is in low voltage mode.
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 @endverbatim
bogdanm 0:9b334a45a8ff 146 * @{
bogdanm 0:9b334a45a8ff 147 */
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 /**
bogdanm 0:9b334a45a8ff 150 * @brief Enables the Backup Regulator.
bogdanm 0:9b334a45a8ff 151 * @retval HAL status
bogdanm 0:9b334a45a8ff 152 */
bogdanm 0:9b334a45a8ff 153 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
bogdanm 0:9b334a45a8ff 154 {
bogdanm 0:9b334a45a8ff 155 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 /* Enable Backup regulator */
bogdanm 0:9b334a45a8ff 158 PWR->CSR1 |= PWR_CSR1_BRE;
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 /* Get tick */
bogdanm 0:9b334a45a8ff 161 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 /* Wait till Backup regulator ready flag is set */
bogdanm 0:9b334a45a8ff 164 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
bogdanm 0:9b334a45a8ff 165 {
bogdanm 0:9b334a45a8ff 166 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 167 {
bogdanm 0:9b334a45a8ff 168 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 169 }
bogdanm 0:9b334a45a8ff 170 }
bogdanm 0:9b334a45a8ff 171 return HAL_OK;
bogdanm 0:9b334a45a8ff 172 }
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /**
bogdanm 0:9b334a45a8ff 175 * @brief Disables the Backup Regulator.
bogdanm 0:9b334a45a8ff 176 * @retval HAL status
bogdanm 0:9b334a45a8ff 177 */
bogdanm 0:9b334a45a8ff 178 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
bogdanm 0:9b334a45a8ff 179 {
bogdanm 0:9b334a45a8ff 180 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 /* Disable Backup regulator */
bogdanm 0:9b334a45a8ff 183 PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /* Get tick */
bogdanm 0:9b334a45a8ff 186 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 /* Wait till Backup regulator ready flag is set */
bogdanm 0:9b334a45a8ff 189 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
bogdanm 0:9b334a45a8ff 190 {
bogdanm 0:9b334a45a8ff 191 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 192 {
bogdanm 0:9b334a45a8ff 193 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 194 }
bogdanm 0:9b334a45a8ff 195 }
bogdanm 0:9b334a45a8ff 196 return HAL_OK;
bogdanm 0:9b334a45a8ff 197 }
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 /**
bogdanm 0:9b334a45a8ff 200 * @brief Enables the Flash Power Down in Stop mode.
bogdanm 0:9b334a45a8ff 201 * @retval None
bogdanm 0:9b334a45a8ff 202 */
bogdanm 0:9b334a45a8ff 203 void HAL_PWREx_EnableFlashPowerDown(void)
bogdanm 0:9b334a45a8ff 204 {
bogdanm 0:9b334a45a8ff 205 /* Enable the Flash Power Down */
bogdanm 0:9b334a45a8ff 206 PWR->CR1 |= PWR_CR1_FPDS;
bogdanm 0:9b334a45a8ff 207 }
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /**
bogdanm 0:9b334a45a8ff 210 * @brief Disables the Flash Power Down in Stop mode.
bogdanm 0:9b334a45a8ff 211 * @retval None
bogdanm 0:9b334a45a8ff 212 */
bogdanm 0:9b334a45a8ff 213 void HAL_PWREx_DisableFlashPowerDown(void)
bogdanm 0:9b334a45a8ff 214 {
bogdanm 0:9b334a45a8ff 215 /* Disable the Flash Power Down */
bogdanm 0:9b334a45a8ff 216 PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);
bogdanm 0:9b334a45a8ff 217 }
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 /**
bogdanm 0:9b334a45a8ff 220 * @brief Enables Main Regulator low voltage mode.
bogdanm 0:9b334a45a8ff 221 * @retval None
bogdanm 0:9b334a45a8ff 222 */
bogdanm 0:9b334a45a8ff 223 void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
bogdanm 0:9b334a45a8ff 224 {
bogdanm 0:9b334a45a8ff 225 /* Enable Main regulator low voltage */
bogdanm 0:9b334a45a8ff 226 PWR->CR1 |= PWR_CR1_MRUDS;
bogdanm 0:9b334a45a8ff 227 }
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 /**
bogdanm 0:9b334a45a8ff 230 * @brief Disables Main Regulator low voltage mode.
bogdanm 0:9b334a45a8ff 231 * @retval None
bogdanm 0:9b334a45a8ff 232 */
bogdanm 0:9b334a45a8ff 233 void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
bogdanm 0:9b334a45a8ff 234 {
bogdanm 0:9b334a45a8ff 235 /* Disable Main regulator low voltage */
bogdanm 0:9b334a45a8ff 236 PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);
bogdanm 0:9b334a45a8ff 237 }
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 /**
bogdanm 0:9b334a45a8ff 240 * @brief Enables Low Power Regulator low voltage mode.
bogdanm 0:9b334a45a8ff 241 * @retval None
bogdanm 0:9b334a45a8ff 242 */
bogdanm 0:9b334a45a8ff 243 void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
bogdanm 0:9b334a45a8ff 244 {
bogdanm 0:9b334a45a8ff 245 /* Enable low power regulator */
bogdanm 0:9b334a45a8ff 246 PWR->CR1 |= PWR_CR1_LPUDS;
bogdanm 0:9b334a45a8ff 247 }
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /**
bogdanm 0:9b334a45a8ff 250 * @brief Disables Low Power Regulator low voltage mode.
bogdanm 0:9b334a45a8ff 251 * @retval None
bogdanm 0:9b334a45a8ff 252 */
bogdanm 0:9b334a45a8ff 253 void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
bogdanm 0:9b334a45a8ff 254 {
bogdanm 0:9b334a45a8ff 255 /* Disable low power regulator */
bogdanm 0:9b334a45a8ff 256 PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);
bogdanm 0:9b334a45a8ff 257 }
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 /**
bogdanm 0:9b334a45a8ff 260 * @brief Activates the Over-Drive mode.
bogdanm 0:9b334a45a8ff 261 * @note This mode allows the CPU and the core logic to operate at a higher frequency
bogdanm 0:9b334a45a8ff 262 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
bogdanm 0:9b334a45a8ff 263 * @note It is recommended to enter or exit Over-drive mode when the application is not running
bogdanm 0:9b334a45a8ff 264 * critical tasks and when the system clock source is either HSI or HSE.
bogdanm 0:9b334a45a8ff 265 * During the Over-drive switch activation, no peripheral clocks should be enabled.
bogdanm 0:9b334a45a8ff 266 * The peripheral clocks must be enabled once the Over-drive mode is activated.
bogdanm 0:9b334a45a8ff 267 * @retval HAL status
bogdanm 0:9b334a45a8ff 268 */
bogdanm 0:9b334a45a8ff 269 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
bogdanm 0:9b334a45a8ff 270 {
bogdanm 0:9b334a45a8ff 271 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 __HAL_RCC_PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 /* Enable the Over-drive to extend the clock frequency to 216 MHz */
bogdanm 0:9b334a45a8ff 276 __HAL_PWR_OVERDRIVE_ENABLE();
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 /* Get tick */
bogdanm 0:9b334a45a8ff 279 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 280
bogdanm 0:9b334a45a8ff 281 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
bogdanm 0:9b334a45a8ff 282 {
bogdanm 0:9b334a45a8ff 283 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 284 {
bogdanm 0:9b334a45a8ff 285 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 286 }
bogdanm 0:9b334a45a8ff 287 }
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 /* Enable the Over-drive switch */
bogdanm 0:9b334a45a8ff 290 __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 /* Get tick */
bogdanm 0:9b334a45a8ff 293 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
bogdanm 0:9b334a45a8ff 296 {
bogdanm 0:9b334a45a8ff 297 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 298 {
bogdanm 0:9b334a45a8ff 299 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 300 }
bogdanm 0:9b334a45a8ff 301 }
bogdanm 0:9b334a45a8ff 302 return HAL_OK;
bogdanm 0:9b334a45a8ff 303 }
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 /**
bogdanm 0:9b334a45a8ff 306 * @brief Deactivates the Over-Drive mode.
bogdanm 0:9b334a45a8ff 307 * @note This mode allows the CPU and the core logic to operate at a higher frequency
bogdanm 0:9b334a45a8ff 308 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
bogdanm 0:9b334a45a8ff 309 * @note It is recommended to enter or exit Over-drive mode when the application is not running
bogdanm 0:9b334a45a8ff 310 * critical tasks and when the system clock source is either HSI or HSE.
bogdanm 0:9b334a45a8ff 311 * During the Over-drive switch activation, no peripheral clocks should be enabled.
bogdanm 0:9b334a45a8ff 312 * The peripheral clocks must be enabled once the Over-drive mode is activated.
bogdanm 0:9b334a45a8ff 313 * @retval HAL status
bogdanm 0:9b334a45a8ff 314 */
bogdanm 0:9b334a45a8ff 315 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
bogdanm 0:9b334a45a8ff 316 {
bogdanm 0:9b334a45a8ff 317 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 318
bogdanm 0:9b334a45a8ff 319 __HAL_RCC_PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321 /* Disable the Over-drive switch */
bogdanm 0:9b334a45a8ff 322 __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
bogdanm 0:9b334a45a8ff 323
bogdanm 0:9b334a45a8ff 324 /* Get tick */
bogdanm 0:9b334a45a8ff 325 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
bogdanm 0:9b334a45a8ff 328 {
bogdanm 0:9b334a45a8ff 329 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 330 {
bogdanm 0:9b334a45a8ff 331 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 332 }
bogdanm 0:9b334a45a8ff 333 }
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /* Disable the Over-drive */
bogdanm 0:9b334a45a8ff 336 __HAL_PWR_OVERDRIVE_DISABLE();
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 /* Get tick */
bogdanm 0:9b334a45a8ff 339 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 340
bogdanm 0:9b334a45a8ff 341 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
bogdanm 0:9b334a45a8ff 342 {
bogdanm 0:9b334a45a8ff 343 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 344 {
bogdanm 0:9b334a45a8ff 345 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 346 }
bogdanm 0:9b334a45a8ff 347 }
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 return HAL_OK;
bogdanm 0:9b334a45a8ff 350 }
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 /**
bogdanm 0:9b334a45a8ff 353 * @brief Enters in Under-Drive STOP mode.
bogdanm 0:9b334a45a8ff 354 *
bogdanm 0:9b334a45a8ff 355 * @note This mode can be selected only when the Under-Drive is already active
bogdanm 0:9b334a45a8ff 356 *
bogdanm 0:9b334a45a8ff 357 * @note This mode is enabled only with STOP low power mode.
bogdanm 0:9b334a45a8ff 358 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
bogdanm 0:9b334a45a8ff 359 * mode is only available when the main regulator or the low power regulator
bogdanm 0:9b334a45a8ff 360 * is in low voltage mode
bogdanm 0:9b334a45a8ff 361 *
bogdanm 0:9b334a45a8ff 362 * @note If the Under-drive mode was enabled, it is automatically disabled after
bogdanm 0:9b334a45a8ff 363 * exiting Stop mode.
bogdanm 0:9b334a45a8ff 364 * When the voltage regulator operates in Under-drive mode, an additional
bogdanm 0:9b334a45a8ff 365 * startup delay is induced when waking up from Stop mode.
bogdanm 0:9b334a45a8ff 366 *
bogdanm 0:9b334a45a8ff 367 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 368 *
bogdanm 0:9b334a45a8ff 369 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
bogdanm 0:9b334a45a8ff 370 * the HSI RC oscillator is selected as system clock.
bogdanm 0:9b334a45a8ff 371 *
bogdanm 0:9b334a45a8ff 372 * @note When the voltage regulator operates in low power mode, an additional
bogdanm 0:9b334a45a8ff 373 * startup delay is incurred when waking up from Stop mode.
bogdanm 0:9b334a45a8ff 374 * By keeping the internal regulator ON during Stop mode, the consumption
bogdanm 0:9b334a45a8ff 375 * is higher although the startup time is reduced.
bogdanm 0:9b334a45a8ff 376 *
bogdanm 0:9b334a45a8ff 377 * @param Regulator: specifies the regulator state in STOP mode.
bogdanm 0:9b334a45a8ff 378 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 379 * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
bogdanm 0:9b334a45a8ff 380 * and Flash memory in power-down when the device is in Stop under-drive mode
bogdanm 0:9b334a45a8ff 381 * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
bogdanm 0:9b334a45a8ff 382 * and Flash memory in power-down when the device is in Stop under-drive mode
bogdanm 0:9b334a45a8ff 383 * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 384 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 385 * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
bogdanm 0:9b334a45a8ff 386 * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
bogdanm 0:9b334a45a8ff 387 * @retval None
bogdanm 0:9b334a45a8ff 388 */
bogdanm 0:9b334a45a8ff 389 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
bogdanm 0:9b334a45a8ff 390 {
bogdanm 0:9b334a45a8ff 391 uint32_t tempreg = 0;
bogdanm 0:9b334a45a8ff 392 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 /* Check the parameters */
bogdanm 0:9b334a45a8ff 395 assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
bogdanm 0:9b334a45a8ff 396 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 /* Enable Power ctrl clock */
bogdanm 0:9b334a45a8ff 399 __HAL_RCC_PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 400 /* Enable the Under-drive Mode ---------------------------------------------*/
bogdanm 0:9b334a45a8ff 401 /* Clear Under-drive flag */
bogdanm 0:9b334a45a8ff 402 __HAL_PWR_CLEAR_ODRUDR_FLAG();
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 /* Enable the Under-drive */
bogdanm 0:9b334a45a8ff 405 __HAL_PWR_UNDERDRIVE_ENABLE();
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /* Get tick */
bogdanm 0:9b334a45a8ff 408 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /* Wait for UnderDrive mode is ready */
bogdanm 0:9b334a45a8ff 411 while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
bogdanm 0:9b334a45a8ff 412 {
bogdanm 0:9b334a45a8ff 413 if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 414 {
bogdanm 0:9b334a45a8ff 415 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 416 }
bogdanm 0:9b334a45a8ff 417 }
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /* Select the regulator state in STOP mode ---------------------------------*/
bogdanm 0:9b334a45a8ff 420 tempreg = PWR->CR1;
bogdanm 0:9b334a45a8ff 421 /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
bogdanm 0:9b334a45a8ff 422 tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
bogdanm 0:9b334a45a8ff 425 tempreg |= Regulator;
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 /* Store the new value */
bogdanm 0:9b334a45a8ff 428 PWR->CR1 = tempreg;
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 431 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
bogdanm 0:9b334a45a8ff 432
bogdanm 0:9b334a45a8ff 433 /* Select STOP mode entry --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 434 if(STOPEntry == PWR_SLEEPENTRY_WFI)
bogdanm 0:9b334a45a8ff 435 {
bogdanm 0:9b334a45a8ff 436 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 437 __WFI();
bogdanm 0:9b334a45a8ff 438 }
bogdanm 0:9b334a45a8ff 439 else
bogdanm 0:9b334a45a8ff 440 {
bogdanm 0:9b334a45a8ff 441 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 442 __WFE();
bogdanm 0:9b334a45a8ff 443 }
bogdanm 0:9b334a45a8ff 444 /* Reset SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 445 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 return HAL_OK;
bogdanm 0:9b334a45a8ff 448 }
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 /**
bogdanm 0:9b334a45a8ff 451 * @brief Returns Voltage Scaling Range.
bogdanm 0:9b334a45a8ff 452 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or
bogdanm 0:9b334a45a8ff 453 * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1
bogdanm 0:9b334a45a8ff 454 */
bogdanm 0:9b334a45a8ff 455 uint32_t HAL_PWREx_GetVoltageRange(void)
bogdanm 0:9b334a45a8ff 456 {
bogdanm 0:9b334a45a8ff 457 return (PWR->CR1 & PWR_CR1_VOS);
bogdanm 0:9b334a45a8ff 458 }
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /**
bogdanm 0:9b334a45a8ff 461 * @brief Configures the main internal regulator output voltage.
bogdanm 0:9b334a45a8ff 462 * @param VoltageScaling: specifies the regulator output voltage to achieve
bogdanm 0:9b334a45a8ff 463 * a tradeoff between performance and power consumption.
bogdanm 0:9b334a45a8ff 464 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 465 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
bogdanm 0:9b334a45a8ff 466 * typical output voltage at 1.4 V,
bogdanm 0:9b334a45a8ff 467 * system frequency up to 216 MHz.
bogdanm 0:9b334a45a8ff 468 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
bogdanm 0:9b334a45a8ff 469 * typical output voltage at 1.2 V,
bogdanm 0:9b334a45a8ff 470 * system frequency up to 180 MHz.
bogdanm 0:9b334a45a8ff 471 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,
bogdanm 0:9b334a45a8ff 472 * typical output voltage at 1.00 V,
bogdanm 0:9b334a45a8ff 473 * system frequency up to 151 MHz.
bogdanm 0:9b334a45a8ff 474 * @note To update the system clock frequency(SYSCLK):
bogdanm 0:9b334a45a8ff 475 * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
bogdanm 0:9b334a45a8ff 476 * - Call the HAL_RCC_OscConfig() to configure the PLL.
bogdanm 0:9b334a45a8ff 477 * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
bogdanm 0:9b334a45a8ff 478 * - Set the new system clock frequency using the HAL_RCC_ClockConfig().
bogdanm 0:9b334a45a8ff 479 * @note The scale can be modified only when the HSI or HSE clock source is selected
bogdanm 0:9b334a45a8ff 480 * as system clock source, otherwise the API returns HAL_ERROR.
bogdanm 0:9b334a45a8ff 481 * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
bogdanm 0:9b334a45a8ff 482 * value in the PWR_CR1 register are not taken in account.
bogdanm 0:9b334a45a8ff 483 * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
bogdanm 0:9b334a45a8ff 484 * @note The new voltage scale is active only when the PLL is ON.
bogdanm 0:9b334a45a8ff 485 * @retval HAL Status
bogdanm 0:9b334a45a8ff 486 */
bogdanm 0:9b334a45a8ff 487 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
bogdanm 0:9b334a45a8ff 488 {
bogdanm 0:9b334a45a8ff 489 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491 assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 /* Enable Power ctrl clock */
bogdanm 0:9b334a45a8ff 494 __HAL_RCC_PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 /* Check if the PLL is used as system clock or not */
bogdanm 0:9b334a45a8ff 497 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
bogdanm 0:9b334a45a8ff 498 {
bogdanm 0:9b334a45a8ff 499 /* Disable the main PLL */
bogdanm 0:9b334a45a8ff 500 __HAL_RCC_PLL_DISABLE();
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /* Get Start Tick */
bogdanm 0:9b334a45a8ff 503 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 504 /* Wait till PLL is disabled */
bogdanm 0:9b334a45a8ff 505 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm 0:9b334a45a8ff 506 {
bogdanm 0:9b334a45a8ff 507 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 508 {
bogdanm 0:9b334a45a8ff 509 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 510 }
bogdanm 0:9b334a45a8ff 511 }
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 /* Set Range */
bogdanm 0:9b334a45a8ff 514 __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 /* Enable the main PLL */
bogdanm 0:9b334a45a8ff 517 __HAL_RCC_PLL_ENABLE();
bogdanm 0:9b334a45a8ff 518
bogdanm 0:9b334a45a8ff 519 /* Get Start Tick */
bogdanm 0:9b334a45a8ff 520 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 521 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 522 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 523 {
bogdanm 0:9b334a45a8ff 524 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 525 {
bogdanm 0:9b334a45a8ff 526 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 527 }
bogdanm 0:9b334a45a8ff 528 }
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /* Get Start Tick */
bogdanm 0:9b334a45a8ff 531 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 532 while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
bogdanm 0:9b334a45a8ff 533 {
bogdanm 0:9b334a45a8ff 534 if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 535 {
bogdanm 0:9b334a45a8ff 536 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 537 }
bogdanm 0:9b334a45a8ff 538 }
bogdanm 0:9b334a45a8ff 539 }
bogdanm 0:9b334a45a8ff 540 else
bogdanm 0:9b334a45a8ff 541 {
bogdanm 0:9b334a45a8ff 542 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 543 }
bogdanm 0:9b334a45a8ff 544 return HAL_OK;
bogdanm 0:9b334a45a8ff 545 }
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 /**
bogdanm 0:9b334a45a8ff 548 * @}
bogdanm 0:9b334a45a8ff 549 */
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /**
bogdanm 0:9b334a45a8ff 552 * @}
bogdanm 0:9b334a45a8ff 553 */
bogdanm 0:9b334a45a8ff 554
bogdanm 0:9b334a45a8ff 555 #endif /* HAL_PWR_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 556 /**
bogdanm 0:9b334a45a8ff 557 * @}
bogdanm 0:9b334a45a8ff 558 */
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 /**
bogdanm 0:9b334a45a8ff 561 * @}
bogdanm 0:9b334a45a8ff 562 */
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/