en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c@83:a036322b8637, 2016-03-07 (annotated)

Committer:
mbed_official
Date:
Mon Mar 07 10:00:14 2016 +0000
Revision:
83:a036322b8637
Parent:
0:9b334a45a8ff 
Synchronized with git revision ee20d03969aa5c570152f88e8f3d8a4739eed40b



Full URL: https://github.com/mbedmicro/mbed/commit/ee20d03969aa5c570152f88e8f3d8a4739eed40b/



[STM32F7] Update STM32F7Cube_FW version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f7xx_hal_dma.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 83:a036322b8637 5 * @version V1.0.4
mbed_official 83:a036322b8637 6 * @date 09-December-2015
bogdanm 0:9b334a45a8ff 7 * @brief DMA HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the Direct Memory Access (DMA) peripheral:
bogdanm 0:9b334a45a8ff 11 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 12 * + IO operation functions
bogdanm 0:9b334a45a8ff 13 * + Peripheral State and errors functions
bogdanm 0:9b334a45a8ff 14 @verbatim
bogdanm 0:9b334a45a8ff 15 ==============================================================================
bogdanm 0:9b334a45a8ff 16 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 17 ==============================================================================
bogdanm 0:9b334a45a8ff 18 [..]
bogdanm 0:9b334a45a8ff 19 (#) Enable and configure the peripheral to be connected to the DMA Stream
bogdanm 0:9b334a45a8ff 20 (except for internal SRAM/FLASH memories: no initialization is
bogdanm 0:9b334a45a8ff 21 necessary) please refer to Reference manual for connection between peripherals
bogdanm 0:9b334a45a8ff 22 and DMA requests .
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 (#) For a given Stream, program the required configuration through the following parameters:
bogdanm 0:9b334a45a8ff 25 Transfer Direction, Source and Destination data formats,
bogdanm 0:9b334a45a8ff 26 Circular, Normal or peripheral flow control mode, Stream Priority level,
bogdanm 0:9b334a45a8ff 27 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
bogdanm 0:9b334a45a8ff 28 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 *** Polling mode IO operation ***
bogdanm 0:9b334a45a8ff 31 =================================
bogdanm 0:9b334a45a8ff 32 [..]
bogdanm 0:9b334a45a8ff 33 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
bogdanm 0:9b334a45a8ff 34 address and destination address and the Length of data to be transferred
bogdanm 0:9b334a45a8ff 35 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
bogdanm 0:9b334a45a8ff 36 case a fixed Timeout can be configured by User depending from his application.
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 *** Interrupt mode IO operation ***
bogdanm 0:9b334a45a8ff 39 ===================================
bogdanm 0:9b334a45a8ff 40 [..]
bogdanm 0:9b334a45a8ff 41 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
bogdanm 0:9b334a45a8ff 42 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
bogdanm 0:9b334a45a8ff 43 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
bogdanm 0:9b334a45a8ff 44 Source address and destination address and the Length of data to be transferred. In this
bogdanm 0:9b334a45a8ff 45 case the DMA interrupt is configured
bogdanm 0:9b334a45a8ff 46 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
bogdanm 0:9b334a45a8ff 47 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
bogdanm 0:9b334a45a8ff 48 add his own function by customization of function pointer XferCpltCallback and
bogdanm 0:9b334a45a8ff 49 XferErrorCallback (i.e a member of DMA handle structure).
bogdanm 0:9b334a45a8ff 50 [..]
bogdanm 0:9b334a45a8ff 51 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
bogdanm 0:9b334a45a8ff 52 detection.
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 (#) Use HAL_DMA_Abort() function to abort the current transfer
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
bogdanm 0:9b334a45a8ff 59 possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
bogdanm 0:9b334a45a8ff 60 Half-Word data size for the peripheral to access its data register and set Word data size
bogdanm 0:9b334a45a8ff 61 for the Memory to gain in access time. Each two half words will be packed and written in
bogdanm 0:9b334a45a8ff 62 a single access to a Word in the Memory).
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
bogdanm 0:9b334a45a8ff 65 and Destination. In this case the Peripheral Data Size will be applied to both Source
bogdanm 0:9b334a45a8ff 66 and Destination.
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 *** DMA HAL driver macros list ***
bogdanm 0:9b334a45a8ff 69 =============================================
bogdanm 0:9b334a45a8ff 70 [..]
bogdanm 0:9b334a45a8ff 71 Below the list of most used macros in DMA HAL driver.
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
bogdanm 0:9b334a45a8ff 74 (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
bogdanm 0:9b334a45a8ff 75 (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
bogdanm 0:9b334a45a8ff 76 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
bogdanm 0:9b334a45a8ff 77 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
bogdanm 0:9b334a45a8ff 78 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 [..]
bogdanm 0:9b334a45a8ff 81 (@) You can refer to the DMA HAL driver header file for more useful macros
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 @endverbatim
bogdanm 0:9b334a45a8ff 84 ******************************************************************************
bogdanm 0:9b334a45a8ff 85 * @attention
bogdanm 0:9b334a45a8ff 86 *
bogdanm 0:9b334a45a8ff 87 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 88 *
bogdanm 0:9b334a45a8ff 89 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 90 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 91 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 92 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 93 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 94 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 95 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 96 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 97 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 98 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 99 *
bogdanm 0:9b334a45a8ff 100 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 101 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 102 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 103 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 104 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 105 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 106 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 107 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 108 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 109 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 110 *
bogdanm 0:9b334a45a8ff 111 ******************************************************************************
bogdanm 0:9b334a45a8ff 112 */
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 115 #include "stm32f7xx_hal.h"
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /** @addtogroup STM32F7xx_HAL_Driver
bogdanm 0:9b334a45a8ff 118 * @{
bogdanm 0:9b334a45a8ff 119 */
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 /** @defgroup DMA DMA
bogdanm 0:9b334a45a8ff 122 * @brief DMA HAL module driver
bogdanm 0:9b334a45a8ff 123 * @{
bogdanm 0:9b334a45a8ff 124 */
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 #ifdef HAL_DMA_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /* Private types -------------------------------------------------------------*/
mbed_official 83:a036322b8637 129 typedef struct
mbed_official 83:a036322b8637 130 {
mbed_official 83:a036322b8637 131 __IO uint32_t ISR; /*!< DMA interrupt status register */
mbed_official 83:a036322b8637 132 __IO uint32_t Reserved0;
mbed_official 83:a036322b8637 133 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
mbed_official 83:a036322b8637 134 } DMA_Base_Registers;
mbed_official 83:a036322b8637 135
bogdanm 0:9b334a45a8ff 136 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 137 /* Private constants ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 138 /** @addtogroup DMA_Private_Constants
bogdanm 0:9b334a45a8ff 139 * @{
bogdanm 0:9b334a45a8ff 140 */
bogdanm 0:9b334a45a8ff 141 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
bogdanm 0:9b334a45a8ff 142 /**
bogdanm 0:9b334a45a8ff 143 * @}
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145 /* Private macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 146 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 147 /** @addtogroup DMA_Private_Functions
bogdanm 0:9b334a45a8ff 148 * @{
bogdanm 0:9b334a45a8ff 149 */
bogdanm 0:9b334a45a8ff 150 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
mbed_official 83:a036322b8637 151 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
mbed_official 83:a036322b8637 152
bogdanm 0:9b334a45a8ff 153 /**
bogdanm 0:9b334a45a8ff 154 * @brief Sets the DMA Transfer parameter.
bogdanm 0:9b334a45a8ff 155 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 156 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 157 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 158 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 159 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 160 * @retval HAL status
bogdanm 0:9b334a45a8ff 161 */
bogdanm 0:9b334a45a8ff 162 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 163 {
bogdanm 0:9b334a45a8ff 164 /* Clear DBM bit */
bogdanm 0:9b334a45a8ff 165 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 /* Configure DMA Stream data length */
bogdanm 0:9b334a45a8ff 168 hdma->Instance->NDTR = DataLength;
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /* Peripheral to Memory */
bogdanm 0:9b334a45a8ff 171 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
bogdanm 0:9b334a45a8ff 172 {
bogdanm 0:9b334a45a8ff 173 /* Configure DMA Stream destination address */
bogdanm 0:9b334a45a8ff 174 hdma->Instance->PAR = DstAddress;
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 /* Configure DMA Stream source address */
bogdanm 0:9b334a45a8ff 177 hdma->Instance->M0AR = SrcAddress;
bogdanm 0:9b334a45a8ff 178 }
bogdanm 0:9b334a45a8ff 179 /* Memory to Peripheral */
bogdanm 0:9b334a45a8ff 180 else
bogdanm 0:9b334a45a8ff 181 {
bogdanm 0:9b334a45a8ff 182 /* Configure DMA Stream source address */
bogdanm 0:9b334a45a8ff 183 hdma->Instance->PAR = SrcAddress;
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /* Configure DMA Stream destination address */
bogdanm 0:9b334a45a8ff 186 hdma->Instance->M0AR = DstAddress;
bogdanm 0:9b334a45a8ff 187 }
bogdanm 0:9b334a45a8ff 188 }
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /**
bogdanm 0:9b334a45a8ff 191 * @}
bogdanm 0:9b334a45a8ff 192 */
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 195 /** @addtogroup DMA_Exported_Functions
bogdanm 0:9b334a45a8ff 196 * @{
bogdanm 0:9b334a45a8ff 197 */
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 /** @addtogroup DMA_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 200 *
bogdanm 0:9b334a45a8ff 201 @verbatim
bogdanm 0:9b334a45a8ff 202 ===============================================================================
bogdanm 0:9b334a45a8ff 203 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 204 ===============================================================================
bogdanm 0:9b334a45a8ff 205 [..]
bogdanm 0:9b334a45a8ff 206 This section provides functions allowing to initialize the DMA Stream source
bogdanm 0:9b334a45a8ff 207 and destination addresses, incrementation and data sizes, transfer direction,
bogdanm 0:9b334a45a8ff 208 circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
bogdanm 0:9b334a45a8ff 209 [..]
bogdanm 0:9b334a45a8ff 210 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
bogdanm 0:9b334a45a8ff 211 reference manual.
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 @endverbatim
bogdanm 0:9b334a45a8ff 214 * @{
bogdanm 0:9b334a45a8ff 215 */
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /**
bogdanm 0:9b334a45a8ff 218 * @brief Initializes the DMA according to the specified
bogdanm 0:9b334a45a8ff 219 * parameters in the DMA_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 220 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 221 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 222 * @retval HAL status
bogdanm 0:9b334a45a8ff 223 */
bogdanm 0:9b334a45a8ff 224 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 225 {
bogdanm 0:9b334a45a8ff 226 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /* Check the DMA peripheral state */
bogdanm 0:9b334a45a8ff 229 if(hdma == NULL)
bogdanm 0:9b334a45a8ff 230 {
bogdanm 0:9b334a45a8ff 231 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 232 }
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 /* Check the parameters */
bogdanm 0:9b334a45a8ff 235 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
bogdanm 0:9b334a45a8ff 236 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
bogdanm 0:9b334a45a8ff 237 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
bogdanm 0:9b334a45a8ff 238 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
bogdanm 0:9b334a45a8ff 239 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
bogdanm 0:9b334a45a8ff 240 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
bogdanm 0:9b334a45a8ff 241 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
bogdanm 0:9b334a45a8ff 242 assert_param(IS_DMA_MODE(hdma->Init.Mode));
bogdanm 0:9b334a45a8ff 243 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
bogdanm 0:9b334a45a8ff 244 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
bogdanm 0:9b334a45a8ff 245 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
bogdanm 0:9b334a45a8ff 246 when FIFO mode is enabled */
bogdanm 0:9b334a45a8ff 247 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
bogdanm 0:9b334a45a8ff 248 {
bogdanm 0:9b334a45a8ff 249 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
bogdanm 0:9b334a45a8ff 250 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
bogdanm 0:9b334a45a8ff 251 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
bogdanm 0:9b334a45a8ff 252 }
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 255 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /* Get the CR register value */
bogdanm 0:9b334a45a8ff 258 tmp = hdma->Instance->CR;
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
bogdanm 0:9b334a45a8ff 261 tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
bogdanm 0:9b334a45a8ff 262 DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
bogdanm 0:9b334a45a8ff 263 DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
bogdanm 0:9b334a45a8ff 264 DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 /* Prepare the DMA Stream configuration */
bogdanm 0:9b334a45a8ff 267 tmp |= hdma->Init.Channel | hdma->Init.Direction |
bogdanm 0:9b334a45a8ff 268 hdma->Init.PeriphInc | hdma->Init.MemInc |
bogdanm 0:9b334a45a8ff 269 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
bogdanm 0:9b334a45a8ff 270 hdma->Init.Mode | hdma->Init.Priority;
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272 /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
bogdanm 0:9b334a45a8ff 273 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
bogdanm 0:9b334a45a8ff 274 {
bogdanm 0:9b334a45a8ff 275 /* Get memory burst and peripheral burst */
bogdanm 0:9b334a45a8ff 276 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
bogdanm 0:9b334a45a8ff 277 }
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 /* Write to DMA Stream CR register */
bogdanm 0:9b334a45a8ff 280 hdma->Instance->CR = tmp;
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282 /* Get the FCR register value */
bogdanm 0:9b334a45a8ff 283 tmp = hdma->Instance->FCR;
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 /* Clear Direct mode and FIFO threshold bits */
bogdanm 0:9b334a45a8ff 286 tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 /* Prepare the DMA Stream FIFO configuration */
bogdanm 0:9b334a45a8ff 289 tmp |= hdma->Init.FIFOMode;
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /* the FIFO threshold is not used when the FIFO mode is disabled */
bogdanm 0:9b334a45a8ff 292 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
bogdanm 0:9b334a45a8ff 293 {
bogdanm 0:9b334a45a8ff 294 /* Get the FIFO threshold */
bogdanm 0:9b334a45a8ff 295 tmp |= hdma->Init.FIFOThreshold;
bogdanm 0:9b334a45a8ff 296 }
bogdanm 0:9b334a45a8ff 297
bogdanm 0:9b334a45a8ff 298 /* Write to DMA Stream FCR */
bogdanm 0:9b334a45a8ff 299 hdma->Instance->FCR = tmp;
bogdanm 0:9b334a45a8ff 300
mbed_official 83:a036322b8637 301 /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
mbed_official 83:a036322b8637 302 DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
mbed_official 83:a036322b8637 303 DMA_CalcBaseAndBitshift(hdma);
mbed_official 83:a036322b8637 304
bogdanm 0:9b334a45a8ff 305 /* Initialize the error code */
bogdanm 0:9b334a45a8ff 306 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /* Initialize the DMA state */
bogdanm 0:9b334a45a8ff 309 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 return HAL_OK;
bogdanm 0:9b334a45a8ff 312 }
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 /**
bogdanm 0:9b334a45a8ff 315 * @brief DeInitializes the DMA peripheral
bogdanm 0:9b334a45a8ff 316 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 317 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 318 * @retval HAL status
bogdanm 0:9b334a45a8ff 319 */
bogdanm 0:9b334a45a8ff 320 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 321 {
mbed_official 83:a036322b8637 322 DMA_Base_Registers *regs;
mbed_official 83:a036322b8637 323
bogdanm 0:9b334a45a8ff 324 /* Check the DMA peripheral state */
bogdanm 0:9b334a45a8ff 325 if(hdma == NULL)
bogdanm 0:9b334a45a8ff 326 {
bogdanm 0:9b334a45a8ff 327 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 328 }
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 /* Check the DMA peripheral state */
bogdanm 0:9b334a45a8ff 331 if(hdma->State == HAL_DMA_STATE_BUSY)
bogdanm 0:9b334a45a8ff 332 {
bogdanm 0:9b334a45a8ff 333 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 334 }
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336 /* Disable the selected DMA Streamx */
bogdanm 0:9b334a45a8ff 337 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 /* Reset DMA Streamx control register */
bogdanm 0:9b334a45a8ff 340 hdma->Instance->CR = 0;
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 /* Reset DMA Streamx number of data to transfer register */
bogdanm 0:9b334a45a8ff 343 hdma->Instance->NDTR = 0;
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 /* Reset DMA Streamx peripheral address register */
bogdanm 0:9b334a45a8ff 346 hdma->Instance->PAR = 0;
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 /* Reset DMA Streamx memory 0 address register */
bogdanm 0:9b334a45a8ff 349 hdma->Instance->M0AR = 0;
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 /* Reset DMA Streamx memory 1 address register */
bogdanm 0:9b334a45a8ff 352 hdma->Instance->M1AR = 0;
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 /* Reset DMA Streamx FIFO control register */
bogdanm 0:9b334a45a8ff 355 hdma->Instance->FCR = (uint32_t)0x00000021;
bogdanm 0:9b334a45a8ff 356
mbed_official 83:a036322b8637 357 /* Get DMA steam Base Address */
mbed_official 83:a036322b8637 358 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
mbed_official 83:a036322b8637 359
mbed_official 83:a036322b8637 360 /* Clear all interrupt flags at correct offset within the register */
mbed_official 83:a036322b8637 361 regs->IFCR = 0x3F << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 /* Initialize the error code */
bogdanm 0:9b334a45a8ff 364 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 /* Initialize the DMA state */
bogdanm 0:9b334a45a8ff 367 hdma->State = HAL_DMA_STATE_RESET;
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 /* Release Lock */
bogdanm 0:9b334a45a8ff 370 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 371
bogdanm 0:9b334a45a8ff 372 return HAL_OK;
bogdanm 0:9b334a45a8ff 373 }
bogdanm 0:9b334a45a8ff 374
bogdanm 0:9b334a45a8ff 375 /**
bogdanm 0:9b334a45a8ff 376 * @}
bogdanm 0:9b334a45a8ff 377 */
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 /** @addtogroup DMA_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 380 *
bogdanm 0:9b334a45a8ff 381 @verbatim
bogdanm 0:9b334a45a8ff 382 ===============================================================================
bogdanm 0:9b334a45a8ff 383 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 384 ===============================================================================
bogdanm 0:9b334a45a8ff 385 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 386 (+) Configure the source, destination address and data length and Start DMA transfer
bogdanm 0:9b334a45a8ff 387 (+) Configure the source, destination address and data length and
bogdanm 0:9b334a45a8ff 388 Start DMA transfer with interrupt
bogdanm 0:9b334a45a8ff 389 (+) Abort DMA transfer
bogdanm 0:9b334a45a8ff 390 (+) Poll for transfer complete
bogdanm 0:9b334a45a8ff 391 (+) Handle DMA interrupt request
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 @endverbatim
bogdanm 0:9b334a45a8ff 394 * @{
bogdanm 0:9b334a45a8ff 395 */
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 /**
bogdanm 0:9b334a45a8ff 398 * @brief Starts the DMA Transfer.
bogdanm 0:9b334a45a8ff 399 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 400 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 401 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 402 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 403 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 404 * @retval HAL status
bogdanm 0:9b334a45a8ff 405 */
bogdanm 0:9b334a45a8ff 406 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 407 {
bogdanm 0:9b334a45a8ff 408 /* Process locked */
bogdanm 0:9b334a45a8ff 409 __HAL_LOCK(hdma);
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 412 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /* Check the parameters */
bogdanm 0:9b334a45a8ff 415 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /* Disable the peripheral */
bogdanm 0:9b334a45a8ff 418 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 /* Configure the source, destination address and the data length */
bogdanm 0:9b334a45a8ff 421 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
bogdanm 0:9b334a45a8ff 422
bogdanm 0:9b334a45a8ff 423 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 424 __HAL_DMA_ENABLE(hdma);
bogdanm 0:9b334a45a8ff 425
bogdanm 0:9b334a45a8ff 426 return HAL_OK;
bogdanm 0:9b334a45a8ff 427 }
bogdanm 0:9b334a45a8ff 428
bogdanm 0:9b334a45a8ff 429 /**
bogdanm 0:9b334a45a8ff 430 * @brief Start the DMA Transfer with interrupt enabled.
bogdanm 0:9b334a45a8ff 431 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 432 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 433 * @param SrcAddress: The source memory Buffer address
bogdanm 0:9b334a45a8ff 434 * @param DstAddress: The destination memory Buffer address
bogdanm 0:9b334a45a8ff 435 * @param DataLength: The length of data to be transferred from source to destination
bogdanm 0:9b334a45a8ff 436 * @retval HAL status
bogdanm 0:9b334a45a8ff 437 */
bogdanm 0:9b334a45a8ff 438 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
bogdanm 0:9b334a45a8ff 439 {
bogdanm 0:9b334a45a8ff 440 /* Process locked */
bogdanm 0:9b334a45a8ff 441 __HAL_LOCK(hdma);
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 444 hdma->State = HAL_DMA_STATE_BUSY;
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /* Check the parameters */
bogdanm 0:9b334a45a8ff 447 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 /* Disable the peripheral */
bogdanm 0:9b334a45a8ff 450 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 /* Configure the source, destination address and the data length */
bogdanm 0:9b334a45a8ff 453 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
bogdanm 0:9b334a45a8ff 454
mbed_official 83:a036322b8637 455 /* Enable all interrupts */
mbed_official 83:a036322b8637 456 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME;
mbed_official 83:a036322b8637 457 hdma->Instance->FCR |= DMA_IT_FE;
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 460 __HAL_DMA_ENABLE(hdma);
bogdanm 0:9b334a45a8ff 461
bogdanm 0:9b334a45a8ff 462 return HAL_OK;
bogdanm 0:9b334a45a8ff 463 }
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 /**
bogdanm 0:9b334a45a8ff 466 * @brief Aborts the DMA Transfer.
bogdanm 0:9b334a45a8ff 467 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 468 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 469 *
bogdanm 0:9b334a45a8ff 470 * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
bogdanm 0:9b334a45a8ff 471 * effectively disabled is added. If a Stream is disabled
bogdanm 0:9b334a45a8ff 472 * while a data transfer is ongoing, the current data will be transferred
bogdanm 0:9b334a45a8ff 473 * and the Stream will be effectively disabled only after the transfer of
bogdanm 0:9b334a45a8ff 474 * this single data is finished.
bogdanm 0:9b334a45a8ff 475 * @retval HAL status
bogdanm 0:9b334a45a8ff 476 */
bogdanm 0:9b334a45a8ff 477 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 478 {
bogdanm 0:9b334a45a8ff 479 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 480
bogdanm 0:9b334a45a8ff 481 /* Disable the stream */
bogdanm 0:9b334a45a8ff 482 __HAL_DMA_DISABLE(hdma);
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /* Get tick */
bogdanm 0:9b334a45a8ff 485 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 /* Check if the DMA Stream is effectively disabled */
bogdanm 0:9b334a45a8ff 488 while((hdma->Instance->CR & DMA_SxCR_EN) != 0)
bogdanm 0:9b334a45a8ff 489 {
bogdanm 0:9b334a45a8ff 490 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 491 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
bogdanm 0:9b334a45a8ff 492 {
bogdanm 0:9b334a45a8ff 493 /* Update error code */
bogdanm 0:9b334a45a8ff 494 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 497 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 498
bogdanm 0:9b334a45a8ff 499 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 500 hdma->State = HAL_DMA_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 503 }
bogdanm 0:9b334a45a8ff 504 }
bogdanm 0:9b334a45a8ff 505 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 506 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 /* Change the DMA state*/
bogdanm 0:9b334a45a8ff 509 hdma->State = HAL_DMA_STATE_READY;
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 return HAL_OK;
bogdanm 0:9b334a45a8ff 512 }
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514 /**
bogdanm 0:9b334a45a8ff 515 * @brief Polling for transfer complete.
bogdanm 0:9b334a45a8ff 516 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 517 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 518 * @param CompleteLevel: Specifies the DMA level complete.
bogdanm 0:9b334a45a8ff 519 * @param Timeout: Timeout duration.
bogdanm 0:9b334a45a8ff 520 * @retval HAL status
bogdanm 0:9b334a45a8ff 521 */
bogdanm 0:9b334a45a8ff 522 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 523 {
bogdanm 0:9b334a45a8ff 524 uint32_t temp, tmp, tmp1, tmp2;
bogdanm 0:9b334a45a8ff 525 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 526
mbed_official 83:a036322b8637 527 /* calculate DMA base and stream number */
mbed_official 83:a036322b8637 528 DMA_Base_Registers *regs;
mbed_official 83:a036322b8637 529
mbed_official 83:a036322b8637 530 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
mbed_official 83:a036322b8637 531
bogdanm 0:9b334a45a8ff 532 /* Get the level transfer complete flag */
bogdanm 0:9b334a45a8ff 533 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
bogdanm 0:9b334a45a8ff 534 {
bogdanm 0:9b334a45a8ff 535 /* Transfer Complete flag */
mbed_official 83:a036322b8637 536 temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 537 }
bogdanm 0:9b334a45a8ff 538 else
bogdanm 0:9b334a45a8ff 539 {
bogdanm 0:9b334a45a8ff 540 /* Half Transfer Complete flag */
mbed_official 83:a036322b8637 541 temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 542 }
bogdanm 0:9b334a45a8ff 543
bogdanm 0:9b334a45a8ff 544 /* Get tick */
bogdanm 0:9b334a45a8ff 545 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 546
mbed_official 83:a036322b8637 547 while((regs->ISR & temp) == RESET)
bogdanm 0:9b334a45a8ff 548 {
mbed_official 83:a036322b8637 549 tmp = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex);
mbed_official 83:a036322b8637 550 tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex);
mbed_official 83:a036322b8637 551 tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex);
bogdanm 0:9b334a45a8ff 552 if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
bogdanm 0:9b334a45a8ff 553 {
bogdanm 0:9b334a45a8ff 554 if(tmp != RESET)
bogdanm 0:9b334a45a8ff 555 {
bogdanm 0:9b334a45a8ff 556 /* Update error code */
bogdanm 0:9b334a45a8ff 557 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /* Clear the transfer error flag */
mbed_official 83:a036322b8637 560 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 561 }
bogdanm 0:9b334a45a8ff 562 if(tmp1 != RESET)
bogdanm 0:9b334a45a8ff 563 {
bogdanm 0:9b334a45a8ff 564 /* Update error code */
bogdanm 0:9b334a45a8ff 565 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 /* Clear the FIFO error flag */
mbed_official 83:a036322b8637 568 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570 if(tmp2 != RESET)
bogdanm 0:9b334a45a8ff 571 {
bogdanm 0:9b334a45a8ff 572 /* Update error code */
bogdanm 0:9b334a45a8ff 573 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575 /* Clear the Direct Mode error flag */
mbed_official 83:a036322b8637 576 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 577 }
bogdanm 0:9b334a45a8ff 578 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 579 hdma->State= HAL_DMA_STATE_ERROR;
bogdanm 0:9b334a45a8ff 580
bogdanm 0:9b334a45a8ff 581 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 582 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 583
bogdanm 0:9b334a45a8ff 584 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 585 }
bogdanm 0:9b334a45a8ff 586 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 587 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 588 {
bogdanm 0:9b334a45a8ff 589 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 590 {
bogdanm 0:9b334a45a8ff 591 /* Update error code */
bogdanm 0:9b334a45a8ff 592 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
bogdanm 0:9b334a45a8ff 593
bogdanm 0:9b334a45a8ff 594 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 595 hdma->State = HAL_DMA_STATE_TIMEOUT;
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 598 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 601 }
bogdanm 0:9b334a45a8ff 602 }
bogdanm 0:9b334a45a8ff 603 }
bogdanm 0:9b334a45a8ff 604
bogdanm 0:9b334a45a8ff 605 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
bogdanm 0:9b334a45a8ff 606 {
mbed_official 83:a036322b8637 607 /* Clear the half transfer and transfer complete flags */
mbed_official 83:a036322b8637 608 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
mbed_official 83:a036322b8637 609
bogdanm 0:9b334a45a8ff 610 /* Multi_Buffering mode enabled */
bogdanm 0:9b334a45a8ff 611 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
bogdanm 0:9b334a45a8ff 612 {
bogdanm 0:9b334a45a8ff 613 /* Current memory buffer used is Memory 0 */
bogdanm 0:9b334a45a8ff 614 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
bogdanm 0:9b334a45a8ff 615 {
bogdanm 0:9b334a45a8ff 616 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 617 hdma->State = HAL_DMA_STATE_READY_MEM0;
bogdanm 0:9b334a45a8ff 618 }
bogdanm 0:9b334a45a8ff 619 /* Current memory buffer used is Memory 1 */
bogdanm 0:9b334a45a8ff 620 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
bogdanm 0:9b334a45a8ff 621 {
bogdanm 0:9b334a45a8ff 622 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 623 hdma->State = HAL_DMA_STATE_READY_MEM1;
bogdanm 0:9b334a45a8ff 624 }
bogdanm 0:9b334a45a8ff 625 }
bogdanm 0:9b334a45a8ff 626 else
bogdanm 0:9b334a45a8ff 627 {
bogdanm 0:9b334a45a8ff 628 /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
bogdanm 0:9b334a45a8ff 629 are complete) */
bogdanm 0:9b334a45a8ff 630 hdma->State = HAL_DMA_STATE_READY_MEM0;
bogdanm 0:9b334a45a8ff 631 }
bogdanm 0:9b334a45a8ff 632 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 633 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 634 }
bogdanm 0:9b334a45a8ff 635 else
mbed_official 83:a036322b8637 636 {
mbed_official 83:a036322b8637 637 /* Clear the half transfer complete flag */
mbed_official 83:a036322b8637 638 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
mbed_official 83:a036322b8637 639
bogdanm 0:9b334a45a8ff 640 /* Multi_Buffering mode enabled */
bogdanm 0:9b334a45a8ff 641 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
bogdanm 0:9b334a45a8ff 642 {
bogdanm 0:9b334a45a8ff 643 /* Current memory buffer used is Memory 0 */
bogdanm 0:9b334a45a8ff 644 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
bogdanm 0:9b334a45a8ff 645 {
bogdanm 0:9b334a45a8ff 646 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 647 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
bogdanm 0:9b334a45a8ff 648 }
bogdanm 0:9b334a45a8ff 649 /* Current memory buffer used is Memory 1 */
bogdanm 0:9b334a45a8ff 650 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
bogdanm 0:9b334a45a8ff 651 {
bogdanm 0:9b334a45a8ff 652 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 653 hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
bogdanm 0:9b334a45a8ff 654 }
bogdanm 0:9b334a45a8ff 655 }
bogdanm 0:9b334a45a8ff 656 else
bogdanm 0:9b334a45a8ff 657 {
bogdanm 0:9b334a45a8ff 658 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 659 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
bogdanm 0:9b334a45a8ff 660 }
bogdanm 0:9b334a45a8ff 661 }
bogdanm 0:9b334a45a8ff 662 return HAL_OK;
bogdanm 0:9b334a45a8ff 663 }
bogdanm 0:9b334a45a8ff 664
bogdanm 0:9b334a45a8ff 665 /**
bogdanm 0:9b334a45a8ff 666 * @brief Handles DMA interrupt request.
bogdanm 0:9b334a45a8ff 667 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 668 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 669 * @retval None
bogdanm 0:9b334a45a8ff 670 */
bogdanm 0:9b334a45a8ff 671 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 672 {
mbed_official 83:a036322b8637 673 /* calculate DMA base and stream number */
mbed_official 83:a036322b8637 674 DMA_Base_Registers *regs;
mbed_official 83:a036322b8637 675
mbed_official 83:a036322b8637 676 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
mbed_official 83:a036322b8637 677
bogdanm 0:9b334a45a8ff 678 /* Transfer Error Interrupt management ***************************************/
mbed_official 83:a036322b8637 679 if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
bogdanm 0:9b334a45a8ff 680 {
bogdanm 0:9b334a45a8ff 681 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
bogdanm 0:9b334a45a8ff 682 {
bogdanm 0:9b334a45a8ff 683 /* Disable the transfer error interrupt */
bogdanm 0:9b334a45a8ff 684 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
bogdanm 0:9b334a45a8ff 685
bogdanm 0:9b334a45a8ff 686 /* Clear the transfer error flag */
mbed_official 83:a036322b8637 687 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 688
bogdanm 0:9b334a45a8ff 689 /* Update error code */
bogdanm 0:9b334a45a8ff 690 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 693 hdma->State = HAL_DMA_STATE_ERROR;
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 696 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 697
bogdanm 0:9b334a45a8ff 698 if(hdma->XferErrorCallback != NULL)
bogdanm 0:9b334a45a8ff 699 {
bogdanm 0:9b334a45a8ff 700 /* Transfer error callback */
bogdanm 0:9b334a45a8ff 701 hdma->XferErrorCallback(hdma);
bogdanm 0:9b334a45a8ff 702 }
bogdanm 0:9b334a45a8ff 703 }
bogdanm 0:9b334a45a8ff 704 }
bogdanm 0:9b334a45a8ff 705 /* FIFO Error Interrupt management ******************************************/
mbed_official 83:a036322b8637 706 if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
bogdanm 0:9b334a45a8ff 707 {
bogdanm 0:9b334a45a8ff 708 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
bogdanm 0:9b334a45a8ff 709 {
bogdanm 0:9b334a45a8ff 710 /* Disable the FIFO Error interrupt */
bogdanm 0:9b334a45a8ff 711 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 /* Clear the FIFO error flag */
mbed_official 83:a036322b8637 714 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 /* Update error code */
bogdanm 0:9b334a45a8ff 717 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
bogdanm 0:9b334a45a8ff 718
bogdanm 0:9b334a45a8ff 719 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 720 hdma->State = HAL_DMA_STATE_ERROR;
bogdanm 0:9b334a45a8ff 721
bogdanm 0:9b334a45a8ff 722 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 723 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 724
bogdanm 0:9b334a45a8ff 725 if(hdma->XferErrorCallback != NULL)
bogdanm 0:9b334a45a8ff 726 {
bogdanm 0:9b334a45a8ff 727 /* Transfer error callback */
bogdanm 0:9b334a45a8ff 728 hdma->XferErrorCallback(hdma);
bogdanm 0:9b334a45a8ff 729 }
bogdanm 0:9b334a45a8ff 730 }
bogdanm 0:9b334a45a8ff 731 }
bogdanm 0:9b334a45a8ff 732 /* Direct Mode Error Interrupt management ***********************************/
mbed_official 83:a036322b8637 733 if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
bogdanm 0:9b334a45a8ff 734 {
bogdanm 0:9b334a45a8ff 735 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
bogdanm 0:9b334a45a8ff 736 {
bogdanm 0:9b334a45a8ff 737 /* Disable the direct mode Error interrupt */
bogdanm 0:9b334a45a8ff 738 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
bogdanm 0:9b334a45a8ff 739
bogdanm 0:9b334a45a8ff 740 /* Clear the direct mode error flag */
mbed_official 83:a036322b8637 741 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743 /* Update error code */
bogdanm 0:9b334a45a8ff 744 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
bogdanm 0:9b334a45a8ff 745
bogdanm 0:9b334a45a8ff 746 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 747 hdma->State = HAL_DMA_STATE_ERROR;
bogdanm 0:9b334a45a8ff 748
bogdanm 0:9b334a45a8ff 749 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 750 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 if(hdma->XferErrorCallback != NULL)
bogdanm 0:9b334a45a8ff 753 {
bogdanm 0:9b334a45a8ff 754 /* Transfer error callback */
bogdanm 0:9b334a45a8ff 755 hdma->XferErrorCallback(hdma);
bogdanm 0:9b334a45a8ff 756 }
bogdanm 0:9b334a45a8ff 757 }
bogdanm 0:9b334a45a8ff 758 }
bogdanm 0:9b334a45a8ff 759 /* Half Transfer Complete Interrupt management ******************************/
mbed_official 83:a036322b8637 760 if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
bogdanm 0:9b334a45a8ff 761 {
bogdanm 0:9b334a45a8ff 762 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
bogdanm 0:9b334a45a8ff 763 {
bogdanm 0:9b334a45a8ff 764 /* Multi_Buffering mode enabled */
bogdanm 0:9b334a45a8ff 765 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
bogdanm 0:9b334a45a8ff 766 {
bogdanm 0:9b334a45a8ff 767 /* Clear the half transfer complete flag */
mbed_official 83:a036322b8637 768 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 769
bogdanm 0:9b334a45a8ff 770 /* Current memory buffer used is Memory 0 */
bogdanm 0:9b334a45a8ff 771 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
bogdanm 0:9b334a45a8ff 772 {
bogdanm 0:9b334a45a8ff 773 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 774 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
bogdanm 0:9b334a45a8ff 775 }
bogdanm 0:9b334a45a8ff 776 /* Current memory buffer used is Memory 1 */
bogdanm 0:9b334a45a8ff 777 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
bogdanm 0:9b334a45a8ff 778 {
bogdanm 0:9b334a45a8ff 779 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 780 hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
bogdanm 0:9b334a45a8ff 781 }
bogdanm 0:9b334a45a8ff 782 }
bogdanm 0:9b334a45a8ff 783 else
bogdanm 0:9b334a45a8ff 784 {
bogdanm 0:9b334a45a8ff 785 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
bogdanm 0:9b334a45a8ff 786 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 787 {
bogdanm 0:9b334a45a8ff 788 /* Disable the half transfer interrupt */
bogdanm 0:9b334a45a8ff 789 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
bogdanm 0:9b334a45a8ff 790 }
bogdanm 0:9b334a45a8ff 791 /* Clear the half transfer complete flag */
mbed_official 83:a036322b8637 792 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 793
bogdanm 0:9b334a45a8ff 794 /* Change DMA peripheral state */
bogdanm 0:9b334a45a8ff 795 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
bogdanm 0:9b334a45a8ff 796 }
bogdanm 0:9b334a45a8ff 797
bogdanm 0:9b334a45a8ff 798 if(hdma->XferHalfCpltCallback != NULL)
bogdanm 0:9b334a45a8ff 799 {
bogdanm 0:9b334a45a8ff 800 /* Half transfer callback */
bogdanm 0:9b334a45a8ff 801 hdma->XferHalfCpltCallback(hdma);
bogdanm 0:9b334a45a8ff 802 }
bogdanm 0:9b334a45a8ff 803 }
bogdanm 0:9b334a45a8ff 804 }
bogdanm 0:9b334a45a8ff 805 /* Transfer Complete Interrupt management ***********************************/
mbed_official 83:a036322b8637 806 if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
bogdanm 0:9b334a45a8ff 807 {
bogdanm 0:9b334a45a8ff 808 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
bogdanm 0:9b334a45a8ff 809 {
bogdanm 0:9b334a45a8ff 810 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
bogdanm 0:9b334a45a8ff 811 {
bogdanm 0:9b334a45a8ff 812 /* Clear the transfer complete flag */
mbed_official 83:a036322b8637 813 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 814
bogdanm 0:9b334a45a8ff 815 /* Current memory buffer used is Memory 1 */
bogdanm 0:9b334a45a8ff 816 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
bogdanm 0:9b334a45a8ff 817 {
bogdanm 0:9b334a45a8ff 818 if(hdma->XferM1CpltCallback != NULL)
bogdanm 0:9b334a45a8ff 819 {
bogdanm 0:9b334a45a8ff 820 /* Transfer complete Callback for memory1 */
bogdanm 0:9b334a45a8ff 821 hdma->XferM1CpltCallback(hdma);
bogdanm 0:9b334a45a8ff 822 }
bogdanm 0:9b334a45a8ff 823 }
bogdanm 0:9b334a45a8ff 824 /* Current memory buffer used is Memory 0 */
bogdanm 0:9b334a45a8ff 825 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
bogdanm 0:9b334a45a8ff 826 {
bogdanm 0:9b334a45a8ff 827 if(hdma->XferCpltCallback != NULL)
bogdanm 0:9b334a45a8ff 828 {
bogdanm 0:9b334a45a8ff 829 /* Transfer complete Callback for memory0 */
bogdanm 0:9b334a45a8ff 830 hdma->XferCpltCallback(hdma);
bogdanm 0:9b334a45a8ff 831 }
bogdanm 0:9b334a45a8ff 832 }
bogdanm 0:9b334a45a8ff 833 }
bogdanm 0:9b334a45a8ff 834 /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
bogdanm 0:9b334a45a8ff 835 else
bogdanm 0:9b334a45a8ff 836 {
bogdanm 0:9b334a45a8ff 837 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 838 {
bogdanm 0:9b334a45a8ff 839 /* Disable the transfer complete interrupt */
bogdanm 0:9b334a45a8ff 840 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
bogdanm 0:9b334a45a8ff 841 }
bogdanm 0:9b334a45a8ff 842 /* Clear the transfer complete flag */
mbed_official 83:a036322b8637 843 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
bogdanm 0:9b334a45a8ff 844
bogdanm 0:9b334a45a8ff 845 /* Update error code */
bogdanm 0:9b334a45a8ff 846 hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
bogdanm 0:9b334a45a8ff 847
bogdanm 0:9b334a45a8ff 848 /* Change the DMA state */
bogdanm 0:9b334a45a8ff 849 hdma->State = HAL_DMA_STATE_READY_MEM0;
bogdanm 0:9b334a45a8ff 850
bogdanm 0:9b334a45a8ff 851 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 852 __HAL_UNLOCK(hdma);
bogdanm 0:9b334a45a8ff 853
bogdanm 0:9b334a45a8ff 854 if(hdma->XferCpltCallback != NULL)
bogdanm 0:9b334a45a8ff 855 {
bogdanm 0:9b334a45a8ff 856 /* Transfer complete callback */
bogdanm 0:9b334a45a8ff 857 hdma->XferCpltCallback(hdma);
bogdanm 0:9b334a45a8ff 858 }
bogdanm 0:9b334a45a8ff 859 }
bogdanm 0:9b334a45a8ff 860 }
bogdanm 0:9b334a45a8ff 861 }
bogdanm 0:9b334a45a8ff 862 }
bogdanm 0:9b334a45a8ff 863
mbed_official 83:a036322b8637 864
bogdanm 0:9b334a45a8ff 865 /**
bogdanm 0:9b334a45a8ff 866 * @}
bogdanm 0:9b334a45a8ff 867 */
bogdanm 0:9b334a45a8ff 868
bogdanm 0:9b334a45a8ff 869 /** @addtogroup DMA_Exported_Functions_Group3
bogdanm 0:9b334a45a8ff 870 *
bogdanm 0:9b334a45a8ff 871 @verbatim
bogdanm 0:9b334a45a8ff 872 ===============================================================================
bogdanm 0:9b334a45a8ff 873 ##### State and Errors functions #####
bogdanm 0:9b334a45a8ff 874 ===============================================================================
bogdanm 0:9b334a45a8ff 875 [..]
bogdanm 0:9b334a45a8ff 876 This subsection provides functions allowing to
bogdanm 0:9b334a45a8ff 877 (+) Check the DMA state
bogdanm 0:9b334a45a8ff 878 (+) Get error code
bogdanm 0:9b334a45a8ff 879
bogdanm 0:9b334a45a8ff 880 @endverbatim
bogdanm 0:9b334a45a8ff 881 * @{
bogdanm 0:9b334a45a8ff 882 */
bogdanm 0:9b334a45a8ff 883
bogdanm 0:9b334a45a8ff 884 /**
bogdanm 0:9b334a45a8ff 885 * @brief Returns the DMA state.
bogdanm 0:9b334a45a8ff 886 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 887 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 888 * @retval HAL state
bogdanm 0:9b334a45a8ff 889 */
bogdanm 0:9b334a45a8ff 890 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 891 {
bogdanm 0:9b334a45a8ff 892 return hdma->State;
bogdanm 0:9b334a45a8ff 893 }
bogdanm 0:9b334a45a8ff 894
bogdanm 0:9b334a45a8ff 895 /**
bogdanm 0:9b334a45a8ff 896 * @brief Return the DMA error code
bogdanm 0:9b334a45a8ff 897 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 898 * the configuration information for the specified DMA Stream.
bogdanm 0:9b334a45a8ff 899 * @retval DMA Error Code
bogdanm 0:9b334a45a8ff 900 */
bogdanm 0:9b334a45a8ff 901 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 902 {
bogdanm 0:9b334a45a8ff 903 return hdma->ErrorCode;
bogdanm 0:9b334a45a8ff 904 }
bogdanm 0:9b334a45a8ff 905
bogdanm 0:9b334a45a8ff 906 /**
bogdanm 0:9b334a45a8ff 907 * @}
bogdanm 0:9b334a45a8ff 908 */
bogdanm 0:9b334a45a8ff 909
bogdanm 0:9b334a45a8ff 910 /**
mbed_official 83:a036322b8637 911 * @brief Returns the DMA Stream base address depending on stream number
mbed_official 83:a036322b8637 912 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 83:a036322b8637 913 * the configuration information for the specified DMA Stream.
mbed_official 83:a036322b8637 914 * @retval Stream base address
mbed_official 83:a036322b8637 915 */
mbed_official 83:a036322b8637 916 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
mbed_official 83:a036322b8637 917 {
mbed_official 83:a036322b8637 918 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24;
mbed_official 83:a036322b8637 919
mbed_official 83:a036322b8637 920 /* lookup table for necessary bitshift of flags within status registers */
mbed_official 83:a036322b8637 921 static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22};
mbed_official 83:a036322b8637 922 hdma->StreamIndex = flagBitshiftOffset[stream_number];
mbed_official 83:a036322b8637 923
mbed_official 83:a036322b8637 924 if (stream_number > 3)
mbed_official 83:a036322b8637 925 {
mbed_official 83:a036322b8637 926 /* return pointer to HISR and HIFCR */
mbed_official 83:a036322b8637 927 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4);
mbed_official 83:a036322b8637 928 }
mbed_official 83:a036322b8637 929 else
mbed_official 83:a036322b8637 930 {
mbed_official 83:a036322b8637 931 /* return pointer to LISR and LIFCR */
mbed_official 83:a036322b8637 932 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF));
mbed_official 83:a036322b8637 933 }
mbed_official 83:a036322b8637 934
mbed_official 83:a036322b8637 935 return hdma->StreamBaseAddress;
mbed_official 83:a036322b8637 936 }
mbed_official 83:a036322b8637 937 /**
bogdanm 0:9b334a45a8ff 938 * @}
bogdanm 0:9b334a45a8ff 939 */
bogdanm 0:9b334a45a8ff 940
bogdanm 0:9b334a45a8ff 941 #endif /* HAL_DMA_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 942 /**
bogdanm 0:9b334a45a8ff 943 * @}
bogdanm 0:9b334a45a8ff 944 */
bogdanm 0:9b334a45a8ff 945
bogdanm 0:9b334a45a8ff 946 /**
bogdanm 0:9b334a45a8ff 947 * @}
bogdanm 0:9b334a45a8ff 948 */
bogdanm 0:9b334a45a8ff 949
bogdanm 0:9b334a45a8ff 950 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/