en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c@83:a036322b8637, 2016-03-07 (annotated)

Committer:
mbed_official
Date:
Mon Mar 07 10:00:14 2016 +0000
Revision:
83:a036322b8637
Parent:
74:9322579e4309 
Synchronized with git revision ee20d03969aa5c570152f88e8f3d8a4739eed40b



Full URL: https://github.com/mbedmicro/mbed/commit/ee20d03969aa5c570152f88e8f3d8a4739eed40b/



[STM32F7] Update STM32F7Cube_FW version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 74:9322579e4309 1 /**
mbed_official 74:9322579e4309 2 ******************************************************************************
mbed_official 74:9322579e4309 3 * @file system_stm32f7xx.c
mbed_official 74:9322579e4309 4 * @author MCD Application Team
mbed_official 83:a036322b8637 5 * @version V1.0.2
mbed_official 83:a036322b8637 6 * @date 21-September-2015
mbed_official 74:9322579e4309 7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
mbed_official 74:9322579e4309 8 *
mbed_official 74:9322579e4309 9 * This file provides two functions and one global variable to be called from
mbed_official 74:9322579e4309 10 * user application:
mbed_official 74:9322579e4309 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 74:9322579e4309 12 * before branch to main program. This call is made inside
mbed_official 74:9322579e4309 13 * the "startup_stm32f7xx.s" file.
mbed_official 74:9322579e4309 14 *
mbed_official 74:9322579e4309 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 74:9322579e4309 16 * by the user application to setup the SysTick
mbed_official 74:9322579e4309 17 * timer or configure other parameters.
mbed_official 74:9322579e4309 18 *
mbed_official 74:9322579e4309 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 74:9322579e4309 20 * be called whenever the core clock is changed
mbed_official 74:9322579e4309 21 * during program execution.
mbed_official 74:9322579e4309 22 *
mbed_official 74:9322579e4309 23 * This file configures the system clock as follows:
mbed_official 74:9322579e4309 24 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 25 * System clock source | [1] PLL_HSE_XTAL | [2] PLL_HSI if [1] fails
mbed_official 74:9322579e4309 26 * | (external 25MHz xtal) | (internal 16MHz clock)
mbed_official 74:9322579e4309 27 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 28 * SYSCLK(MHz) | 216 | 216
mbed_official 74:9322579e4309 29 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 30 * AHBCLK (MHz) | 216 | 216
mbed_official 74:9322579e4309 31 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 32 * APB1CLK (MHz) | 54 | 54
mbed_official 74:9322579e4309 33 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 34 * APB2CLK (MHz) | 108 | 108
mbed_official 74:9322579e4309 35 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 36 * USB capable | YES | NO
mbed_official 74:9322579e4309 37 * with 48 MHz precise clock | |
mbed_official 74:9322579e4309 38 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 39 ******************************************************************************
mbed_official 74:9322579e4309 40 * @attention
mbed_official 74:9322579e4309 41 *
mbed_official 83:a036322b8637 42 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
mbed_official 74:9322579e4309 43 *
mbed_official 74:9322579e4309 44 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 74:9322579e4309 45 * are permitted provided that the following conditions are met:
mbed_official 74:9322579e4309 46 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 74:9322579e4309 47 * this list of conditions and the following disclaimer.
mbed_official 74:9322579e4309 48 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 74:9322579e4309 49 * this list of conditions and the following disclaimer in the documentation
mbed_official 74:9322579e4309 50 * and/or other materials provided with the distribution.
mbed_official 74:9322579e4309 51 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 74:9322579e4309 52 * may be used to endorse or promote products derived from this software
mbed_official 74:9322579e4309 53 * without specific prior written permission.
mbed_official 74:9322579e4309 54 *
mbed_official 74:9322579e4309 55 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 74:9322579e4309 56 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 74:9322579e4309 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 74:9322579e4309 58 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 74:9322579e4309 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 74:9322579e4309 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 74:9322579e4309 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 74:9322579e4309 62 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 74:9322579e4309 63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 74:9322579e4309 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 74:9322579e4309 65 *
mbed_official 74:9322579e4309 66 ******************************************************************************
mbed_official 74:9322579e4309 67 */
mbed_official 74:9322579e4309 68
mbed_official 74:9322579e4309 69 /** @addtogroup CMSIS
mbed_official 74:9322579e4309 70 * @{
mbed_official 74:9322579e4309 71 */
mbed_official 74:9322579e4309 72
mbed_official 74:9322579e4309 73 /** @addtogroup stm32f7xx_system
mbed_official 74:9322579e4309 74 * @{
mbed_official 74:9322579e4309 75 */
mbed_official 74:9322579e4309 76
mbed_official 74:9322579e4309 77 /** @addtogroup STM32F7xx_System_Private_Includes
mbed_official 74:9322579e4309 78 * @{
mbed_official 74:9322579e4309 79 */
mbed_official 74:9322579e4309 80
mbed_official 74:9322579e4309 81 #include "stm32f7xx.h"
mbed_official 74:9322579e4309 82 #include "hal_tick.h"
mbed_official 74:9322579e4309 83
mbed_official 74:9322579e4309 84 HAL_StatusTypeDef HAL_Init(void);
mbed_official 74:9322579e4309 85
mbed_official 74:9322579e4309 86 #if !defined (HSE_VALUE)
mbed_official 74:9322579e4309 87 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
mbed_official 74:9322579e4309 88 #endif /* HSE_VALUE */
mbed_official 74:9322579e4309 89
mbed_official 74:9322579e4309 90 #if !defined (HSI_VALUE)
mbed_official 74:9322579e4309 91 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 74:9322579e4309 92 #endif /* HSI_VALUE */
mbed_official 74:9322579e4309 93
mbed_official 74:9322579e4309 94 /**
mbed_official 74:9322579e4309 95 * @}
mbed_official 74:9322579e4309 96 */
mbed_official 74:9322579e4309 97
mbed_official 74:9322579e4309 98 /** @addtogroup STM32F7xx_System_Private_TypesDefinitions
mbed_official 74:9322579e4309 99 * @{
mbed_official 74:9322579e4309 100 */
mbed_official 74:9322579e4309 101
mbed_official 74:9322579e4309 102 /**
mbed_official 74:9322579e4309 103 * @}
mbed_official 74:9322579e4309 104 */
mbed_official 74:9322579e4309 105
mbed_official 74:9322579e4309 106 /** @addtogroup STM32F7xx_System_Private_Defines
mbed_official 74:9322579e4309 107 * @{
mbed_official 74:9322579e4309 108 */
mbed_official 74:9322579e4309 109
mbed_official 74:9322579e4309 110 /************************* Miscellaneous Configuration ************************/
mbed_official 83:a036322b8637 111 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
mbed_official 83:a036322b8637 112 on STMicroelectronics EVAL/Discovery boards as data memory */
mbed_official 83:a036322b8637 113 /*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
mbed_official 83:a036322b8637 114 need to be added in the project preprocessor to avoid SDRAM multiple configuration
mbed_official 83:a036322b8637 115 (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
mbed_official 83:a036322b8637 116 /* #define DATA_IN_ExtSRAM */
mbed_official 83:a036322b8637 117 /* #define DATA_IN_ExtSDRAM */
mbed_official 83:a036322b8637 118
mbed_official 74:9322579e4309 119 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 74:9322579e4309 120 Internal SRAM. */
mbed_official 74:9322579e4309 121 /* #define VECT_TAB_SRAM */
mbed_official 74:9322579e4309 122 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 74:9322579e4309 123 This value must be a multiple of 0x200. */
mbed_official 74:9322579e4309 124 /******************************************************************************/
mbed_official 74:9322579e4309 125
mbed_official 74:9322579e4309 126 /**
mbed_official 74:9322579e4309 127 * @}
mbed_official 74:9322579e4309 128 */
mbed_official 74:9322579e4309 129
mbed_official 74:9322579e4309 130 /** @addtogroup STM32F7xx_System_Private_Macros
mbed_official 74:9322579e4309 131 * @{
mbed_official 74:9322579e4309 132 */
mbed_official 74:9322579e4309 133
mbed_official 74:9322579e4309 134 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 74:9322579e4309 135 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 74:9322579e4309 136 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 74:9322579e4309 137
mbed_official 74:9322579e4309 138 /**
mbed_official 74:9322579e4309 139 * @}
mbed_official 74:9322579e4309 140 */
mbed_official 74:9322579e4309 141
mbed_official 74:9322579e4309 142 /** @addtogroup STM32F7xx_System_Private_Variables
mbed_official 74:9322579e4309 143 * @{
mbed_official 74:9322579e4309 144 */
mbed_official 74:9322579e4309 145
mbed_official 74:9322579e4309 146 /* This variable is updated in three ways:
mbed_official 74:9322579e4309 147 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 74:9322579e4309 148 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 74:9322579e4309 149 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 74:9322579e4309 150 Note: If you use this function to configure the system clock; then there
mbed_official 74:9322579e4309 151 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 74:9322579e4309 152 variable is updated automatically.
mbed_official 74:9322579e4309 153 */
mbed_official 74:9322579e4309 154 uint32_t SystemCoreClock = HSI_VALUE;
mbed_official 74:9322579e4309 155 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 74:9322579e4309 156
mbed_official 74:9322579e4309 157 /**
mbed_official 74:9322579e4309 158 * @}
mbed_official 74:9322579e4309 159 */
mbed_official 74:9322579e4309 160
mbed_official 74:9322579e4309 161 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
mbed_official 74:9322579e4309 162 * @{
mbed_official 74:9322579e4309 163 */
mbed_official 83:a036322b8637 164 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 83:a036322b8637 165 static void SystemInit_ExtMemCtl(void);
mbed_official 83:a036322b8637 166 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 83:a036322b8637 167
mbed_official 74:9322579e4309 168 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 74:9322579e4309 169 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 74:9322579e4309 170 #endif
mbed_official 74:9322579e4309 171
mbed_official 74:9322579e4309 172 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 74:9322579e4309 173
mbed_official 74:9322579e4309 174 /**
mbed_official 74:9322579e4309 175 * @}
mbed_official 74:9322579e4309 176 */
mbed_official 74:9322579e4309 177
mbed_official 74:9322579e4309 178 /** @addtogroup STM32F7xx_System_Private_Functions
mbed_official 74:9322579e4309 179 * @{
mbed_official 74:9322579e4309 180 */
mbed_official 74:9322579e4309 181
mbed_official 74:9322579e4309 182 /**
mbed_official 74:9322579e4309 183 * @brief Setup the microcontroller system
mbed_official 74:9322579e4309 184 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 74:9322579e4309 185 * SystemFrequency variable.
mbed_official 74:9322579e4309 186 * @param None
mbed_official 74:9322579e4309 187 * @retval None
mbed_official 74:9322579e4309 188 */
mbed_official 74:9322579e4309 189 void SystemInit(void)
mbed_official 74:9322579e4309 190 {
mbed_official 74:9322579e4309 191 /* FPU settings ------------------------------------------------------------*/
mbed_official 74:9322579e4309 192 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 74:9322579e4309 193 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 74:9322579e4309 194 #endif
mbed_official 74:9322579e4309 195 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 74:9322579e4309 196 /* Set HSION bit */
mbed_official 74:9322579e4309 197 RCC->CR |= (uint32_t)0x00000001;
mbed_official 74:9322579e4309 198
mbed_official 74:9322579e4309 199 /* Reset CFGR register */
mbed_official 74:9322579e4309 200 RCC->CFGR = 0x00000000;
mbed_official 74:9322579e4309 201
mbed_official 74:9322579e4309 202 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 74:9322579e4309 203 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 74:9322579e4309 204
mbed_official 74:9322579e4309 205 /* Reset PLLCFGR register */
mbed_official 74:9322579e4309 206 RCC->PLLCFGR = 0x24003010;
mbed_official 74:9322579e4309 207
mbed_official 74:9322579e4309 208 /* Reset HSEBYP bit */
mbed_official 74:9322579e4309 209 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 74:9322579e4309 210
mbed_official 74:9322579e4309 211 /* Disable all interrupts */
mbed_official 74:9322579e4309 212 RCC->CIR = 0x00000000;
mbed_official 74:9322579e4309 213
mbed_official 83:a036322b8637 214 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 83:a036322b8637 215 SystemInit_ExtMemCtl();
mbed_official 83:a036322b8637 216 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 83:a036322b8637 217
mbed_official 74:9322579e4309 218 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 74:9322579e4309 219 #ifdef VECT_TAB_SRAM
mbed_official 83:a036322b8637 220 SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 74:9322579e4309 221 #else
mbed_official 74:9322579e4309 222 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 74:9322579e4309 223 #endif
mbed_official 74:9322579e4309 224
mbed_official 74:9322579e4309 225 /* Configure the Cube driver */
mbed_official 74:9322579e4309 226 SystemCoreClock = HSI_VALUE; // At this stage the HSI is used as system clock
mbed_official 74:9322579e4309 227 HAL_Init();
mbed_official 74:9322579e4309 228
mbed_official 74:9322579e4309 229 // Enable CPU L1-Cache
mbed_official 74:9322579e4309 230 SCB_EnableICache();
mbed_official 74:9322579e4309 231 SCB_EnableDCache();
mbed_official 74:9322579e4309 232
mbed_official 74:9322579e4309 233 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 74:9322579e4309 234 AHB/APBx prescalers and Flash settings */
mbed_official 74:9322579e4309 235 SetSysClock();
mbed_official 74:9322579e4309 236
mbed_official 74:9322579e4309 237 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 74:9322579e4309 238 TIM_MST_RESET_ON;
mbed_official 74:9322579e4309 239 TIM_MST_RESET_OFF;
mbed_official 74:9322579e4309 240 }
mbed_official 74:9322579e4309 241
mbed_official 74:9322579e4309 242 /**
mbed_official 74:9322579e4309 243 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 74:9322579e4309 244 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 74:9322579e4309 245 * be used by the user application to setup the SysTick timer or configure
mbed_official 74:9322579e4309 246 * other parameters.
mbed_official 74:9322579e4309 247 *
mbed_official 74:9322579e4309 248 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 74:9322579e4309 249 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 74:9322579e4309 250 * based on this variable will be incorrect.
mbed_official 74:9322579e4309 251 *
mbed_official 74:9322579e4309 252 * @note - The system frequency computed by this function is not the real
mbed_official 74:9322579e4309 253 * frequency in the chip. It is calculated based on the predefined
mbed_official 74:9322579e4309 254 * constant and the selected clock source:
mbed_official 74:9322579e4309 255 *
mbed_official 74:9322579e4309 256 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 74:9322579e4309 257 *
mbed_official 74:9322579e4309 258 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 74:9322579e4309 259 *
mbed_official 74:9322579e4309 260 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 74:9322579e4309 261 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 74:9322579e4309 262 *
mbed_official 74:9322579e4309 263 * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
mbed_official 74:9322579e4309 264 * 16 MHz) but the real value may vary depending on the variations
mbed_official 74:9322579e4309 265 * in voltage and temperature.
mbed_official 74:9322579e4309 266 *
mbed_official 74:9322579e4309 267 * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
mbed_official 74:9322579e4309 268 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 74:9322579e4309 269 * frequency of the crystal used. Otherwise, this function may
mbed_official 74:9322579e4309 270 * have wrong result.
mbed_official 74:9322579e4309 271 *
mbed_official 74:9322579e4309 272 * - The result of this function could be not correct when using fractional
mbed_official 74:9322579e4309 273 * value for HSE crystal.
mbed_official 74:9322579e4309 274 *
mbed_official 74:9322579e4309 275 * @param None
mbed_official 74:9322579e4309 276 * @retval None
mbed_official 74:9322579e4309 277 */
mbed_official 74:9322579e4309 278 void SystemCoreClockUpdate(void)
mbed_official 74:9322579e4309 279 {
mbed_official 74:9322579e4309 280 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
mbed_official 74:9322579e4309 281
mbed_official 74:9322579e4309 282 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 74:9322579e4309 283 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 74:9322579e4309 284
mbed_official 74:9322579e4309 285 switch (tmp)
mbed_official 74:9322579e4309 286 {
mbed_official 74:9322579e4309 287 case 0x00: /* HSI used as system clock source */
mbed_official 74:9322579e4309 288 SystemCoreClock = HSI_VALUE;
mbed_official 74:9322579e4309 289 break;
mbed_official 74:9322579e4309 290 case 0x04: /* HSE used as system clock source */
mbed_official 74:9322579e4309 291 SystemCoreClock = HSE_VALUE;
mbed_official 74:9322579e4309 292 break;
mbed_official 74:9322579e4309 293 case 0x08: /* PLL used as system clock source */
mbed_official 74:9322579e4309 294
mbed_official 74:9322579e4309 295 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
mbed_official 74:9322579e4309 296 SYSCLK = PLL_VCO / PLL_P
mbed_official 74:9322579e4309 297 */
mbed_official 74:9322579e4309 298 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
mbed_official 74:9322579e4309 299 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official 74:9322579e4309 300
mbed_official 74:9322579e4309 301 if (pllsource != 0)
mbed_official 74:9322579e4309 302 {
mbed_official 74:9322579e4309 303 /* HSE used as PLL clock source */
mbed_official 74:9322579e4309 304 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 74:9322579e4309 305 }
mbed_official 74:9322579e4309 306 else
mbed_official 74:9322579e4309 307 {
mbed_official 74:9322579e4309 308 /* HSI used as PLL clock source */
mbed_official 74:9322579e4309 309 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 74:9322579e4309 310 }
mbed_official 74:9322579e4309 311
mbed_official 74:9322579e4309 312 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
mbed_official 74:9322579e4309 313 SystemCoreClock = pllvco/pllp;
mbed_official 74:9322579e4309 314 break;
mbed_official 74:9322579e4309 315 default:
mbed_official 74:9322579e4309 316 SystemCoreClock = HSI_VALUE;
mbed_official 74:9322579e4309 317 break;
mbed_official 74:9322579e4309 318 }
mbed_official 74:9322579e4309 319 /* Compute HCLK frequency --------------------------------------------------*/
mbed_official 74:9322579e4309 320 /* Get HCLK prescaler */
mbed_official 74:9322579e4309 321 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 74:9322579e4309 322 /* HCLK frequency */
mbed_official 74:9322579e4309 323 SystemCoreClock >>= tmp;
mbed_official 74:9322579e4309 324 }
mbed_official 74:9322579e4309 325
mbed_official 83:a036322b8637 326 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 83:a036322b8637 327 /**
mbed_official 83:a036322b8637 328 * @brief Setup the external memory controller.
mbed_official 83:a036322b8637 329 * Called in startup_stm32f7xx.s before jump to main.
mbed_official 83:a036322b8637 330 * This function configures the external memories (SRAM/SDRAM)
mbed_official 83:a036322b8637 331 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
mbed_official 83:a036322b8637 332 * @param None
mbed_official 83:a036322b8637 333 * @retval None
mbed_official 83:a036322b8637 334 */
mbed_official 83:a036322b8637 335 void SystemInit_ExtMemCtl(void)
mbed_official 83:a036322b8637 336 {
mbed_official 83:a036322b8637 337 __IO uint32_t tmp = 0;
mbed_official 83:a036322b8637 338 #if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
mbed_official 83:a036322b8637 339 register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official 83:a036322b8637 340 register uint32_t index;
mbed_official 83:a036322b8637 341
mbed_official 83:a036322b8637 342 /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official 83:a036322b8637 343 clock */
mbed_official 83:a036322b8637 344 RCC->AHB1ENR |= 0x000001F8;
mbed_official 83:a036322b8637 345
mbed_official 83:a036322b8637 346 /* Delay after an RCC peripheral clock enabling */
mbed_official 83:a036322b8637 347 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
mbed_official 83:a036322b8637 348
mbed_official 83:a036322b8637 349 /* Connect PDx pins to FMC Alternate function */
mbed_official 83:a036322b8637 350 GPIOD->AFR[0] = 0x00CCC0CC;
mbed_official 83:a036322b8637 351 GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 352 /* Configure PDx pins in Alternate function mode */
mbed_official 83:a036322b8637 353 GPIOD->MODER = 0xAAAA0A8A;
mbed_official 83:a036322b8637 354
mbed_official 83:a036322b8637 355 /* Configure PDx pins speed to 100 MHz */
mbed_official 83:a036322b8637 356 GPIOD->OSPEEDR = 0xFFFF0FCF;
mbed_official 83:a036322b8637 357 /* Configure PDx pins Output type to push-pull */
mbed_official 83:a036322b8637 358 GPIOD->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 359 /* No pull-up, pull-down for PDx pins */
mbed_official 83:a036322b8637 360 GPIOD->PUPDR = 0x55550545;
mbed_official 83:a036322b8637 361
mbed_official 83:a036322b8637 362 /* Connect PEx pins to FMC Alternate function */
mbed_official 83:a036322b8637 363 GPIOE->AFR[0] = 0xC00CC0CC;
mbed_official 83:a036322b8637 364 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 365 /* Configure PEx pins in Alternate function mode */
mbed_official 83:a036322b8637 366 GPIOE->MODER = 0xAAAA828A;
mbed_official 83:a036322b8637 367 /* Configure PEx pins speed to 50 MHz */
mbed_official 83:a036322b8637 368 GPIOE->OSPEEDR = 0xFFFFC3CF;
mbed_official 83:a036322b8637 369 /* Configure PEx pins Output type to push-pull */
mbed_official 83:a036322b8637 370 GPIOE->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 371 /* No pull-up, pull-down for PEx pins */
mbed_official 83:a036322b8637 372 GPIOE->PUPDR = 0x55554145;
mbed_official 83:a036322b8637 373
mbed_official 83:a036322b8637 374 /* Connect PFx pins to FMC Alternate function */
mbed_official 83:a036322b8637 375 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 83:a036322b8637 376 GPIOF->AFR[1] = 0xCCCCC000;
mbed_official 83:a036322b8637 377 /* Configure PFx pins in Alternate function mode */
mbed_official 83:a036322b8637 378 GPIOF->MODER = 0xAA800AAA;
mbed_official 83:a036322b8637 379 /* Configure PFx pins speed to 50 MHz */
mbed_official 83:a036322b8637 380 GPIOF->OSPEEDR = 0xFF800FFF;
mbed_official 83:a036322b8637 381 /* Configure PFx pins Output type to push-pull */
mbed_official 83:a036322b8637 382 GPIOF->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 383 /* No pull-up, pull-down for PFx pins */
mbed_official 83:a036322b8637 384 GPIOF->PUPDR = 0x55400555;
mbed_official 83:a036322b8637 385
mbed_official 83:a036322b8637 386 /* Connect PGx pins to FMC Alternate function */
mbed_official 83:a036322b8637 387 GPIOG->AFR[0] = 0x00CC00CC;
mbed_official 83:a036322b8637 388 GPIOG->AFR[1] = 0xC00000CC;
mbed_official 83:a036322b8637 389 /* Configure PGx pins in Alternate function mode */
mbed_official 83:a036322b8637 390 GPIOG->MODER = 0x80220AAA;
mbed_official 83:a036322b8637 391 /* Configure PGx pins speed to 50 MHz */
mbed_official 83:a036322b8637 392 GPIOG->OSPEEDR = 0x80320FFF;
mbed_official 83:a036322b8637 393 /* Configure PGx pins Output type to push-pull */
mbed_official 83:a036322b8637 394 GPIOG->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 395 /* No pull-up, pull-down for PGx pins */
mbed_official 83:a036322b8637 396 GPIOG->PUPDR = 0x40110555;
mbed_official 83:a036322b8637 397
mbed_official 83:a036322b8637 398 /* Connect PHx pins to FMC Alternate function */
mbed_official 83:a036322b8637 399 GPIOH->AFR[0] = 0x00C0CC00;
mbed_official 83:a036322b8637 400 GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 401 /* Configure PHx pins in Alternate function mode */
mbed_official 83:a036322b8637 402 GPIOH->MODER = 0xAAAA08A0;
mbed_official 83:a036322b8637 403 /* Configure PHx pins speed to 50 MHz */
mbed_official 83:a036322b8637 404 GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official 83:a036322b8637 405 /* Configure PHx pins Output type to push-pull */
mbed_official 83:a036322b8637 406 GPIOH->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 407 /* No pull-up, pull-down for PHx pins */
mbed_official 83:a036322b8637 408 GPIOH->PUPDR = 0x55550450;
mbed_official 83:a036322b8637 409
mbed_official 83:a036322b8637 410 /* Connect PIx pins to FMC Alternate function */
mbed_official 83:a036322b8637 411 GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 412 GPIOI->AFR[1] = 0x00000CC0;
mbed_official 83:a036322b8637 413 /* Configure PIx pins in Alternate function mode */
mbed_official 83:a036322b8637 414 GPIOI->MODER = 0x0028AAAA;
mbed_official 83:a036322b8637 415 /* Configure PIx pins speed to 50 MHz */
mbed_official 83:a036322b8637 416 GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official 83:a036322b8637 417 /* Configure PIx pins Output type to push-pull */
mbed_official 83:a036322b8637 418 GPIOI->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 419 /* No pull-up, pull-down for PIx pins */
mbed_official 83:a036322b8637 420 GPIOI->PUPDR = 0x00145555;
mbed_official 83:a036322b8637 421
mbed_official 83:a036322b8637 422 /*-- FMC Configuration ------------------------------------------------------*/
mbed_official 83:a036322b8637 423 /* Enable the FMC interface clock */
mbed_official 83:a036322b8637 424 RCC->AHB3ENR |= 0x00000001;
mbed_official 83:a036322b8637 425
mbed_official 83:a036322b8637 426 /* Delay after an RCC peripheral clock enabling */
mbed_official 83:a036322b8637 427 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
mbed_official 83:a036322b8637 428
mbed_official 83:a036322b8637 429 /* Configure and enable Bank1_SRAM2 */
mbed_official 83:a036322b8637 430 FMC_Bank1->BTCR[4] = 0x00001091;
mbed_official 83:a036322b8637 431 FMC_Bank1->BTCR[5] = 0x00110212;
mbed_official 83:a036322b8637 432 FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
mbed_official 83:a036322b8637 433
mbed_official 83:a036322b8637 434 /* Configure and enable SDRAM bank1 */
mbed_official 83:a036322b8637 435 FMC_Bank5_6->SDCR[0] = 0x000019E5;
mbed_official 83:a036322b8637 436 FMC_Bank5_6->SDTR[0] = 0x01116361;
mbed_official 83:a036322b8637 437
mbed_official 83:a036322b8637 438 /* SDRAM initialization sequence */
mbed_official 83:a036322b8637 439 /* Clock enable command */
mbed_official 83:a036322b8637 440 FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official 83:a036322b8637 441 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 442 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 443 {
mbed_official 83:a036322b8637 444 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 445 }
mbed_official 83:a036322b8637 446
mbed_official 83:a036322b8637 447 /* Delay */
mbed_official 83:a036322b8637 448 for (index = 0; index<1000; index++);
mbed_official 83:a036322b8637 449
mbed_official 83:a036322b8637 450 /* PALL command */
mbed_official 83:a036322b8637 451 FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official 83:a036322b8637 452 timeout = 0xFFFF;
mbed_official 83:a036322b8637 453 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 454 {
mbed_official 83:a036322b8637 455 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 456 }
mbed_official 83:a036322b8637 457
mbed_official 83:a036322b8637 458 /* Auto refresh command */
mbed_official 83:a036322b8637 459 FMC_Bank5_6->SDCMR = 0x000000F3;
mbed_official 83:a036322b8637 460 timeout = 0xFFFF;
mbed_official 83:a036322b8637 461 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 462 {
mbed_official 83:a036322b8637 463 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 464 }
mbed_official 83:a036322b8637 465
mbed_official 83:a036322b8637 466 /* MRD register program */
mbed_official 83:a036322b8637 467 FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official 83:a036322b8637 468 timeout = 0xFFFF;
mbed_official 83:a036322b8637 469 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 470 {
mbed_official 83:a036322b8637 471 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 472 }
mbed_official 83:a036322b8637 473
mbed_official 83:a036322b8637 474 /* Set refresh count */
mbed_official 83:a036322b8637 475 tmpreg = FMC_Bank5_6->SDRTR;
mbed_official 83:a036322b8637 476 FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
mbed_official 83:a036322b8637 477
mbed_official 83:a036322b8637 478 /* Disable write protection */
mbed_official 83:a036322b8637 479 tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official 83:a036322b8637 480 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official 83:a036322b8637 481
mbed_official 83:a036322b8637 482 #elif defined (DATA_IN_ExtSDRAM)
mbed_official 83:a036322b8637 483 register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official 83:a036322b8637 484 register uint32_t index;
mbed_official 83:a036322b8637 485
mbed_official 83:a036322b8637 486 /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official 83:a036322b8637 487 clock */
mbed_official 83:a036322b8637 488 RCC->AHB1ENR |= 0x000001F8;
mbed_official 83:a036322b8637 489
mbed_official 83:a036322b8637 490 /* Delay after an RCC peripheral clock enabling */
mbed_official 83:a036322b8637 491 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
mbed_official 83:a036322b8637 492
mbed_official 83:a036322b8637 493 /* Connect PDx pins to FMC Alternate function */
mbed_official 83:a036322b8637 494 GPIOD->AFR[0] = 0x000000CC;
mbed_official 83:a036322b8637 495 GPIOD->AFR[1] = 0xCC000CCC;
mbed_official 83:a036322b8637 496 /* Configure PDx pins in Alternate function mode */
mbed_official 83:a036322b8637 497 GPIOD->MODER = 0xA02A000A;
mbed_official 83:a036322b8637 498 /* Configure PDx pins speed to 50 MHz */
mbed_official 83:a036322b8637 499 GPIOD->OSPEEDR = 0xA02A000A;
mbed_official 83:a036322b8637 500 /* Configure PDx pins Output type to push-pull */
mbed_official 83:a036322b8637 501 GPIOD->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 502 /* No pull-up, pull-down for PDx pins */
mbed_official 83:a036322b8637 503 GPIOD->PUPDR = 0x50150005;
mbed_official 83:a036322b8637 504
mbed_official 83:a036322b8637 505 /* Connect PEx pins to FMC Alternate function */
mbed_official 83:a036322b8637 506 GPIOE->AFR[0] = 0xC00000CC;
mbed_official 83:a036322b8637 507 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 508 /* Configure PEx pins in Alternate function mode */
mbed_official 83:a036322b8637 509 GPIOE->MODER = 0xAAAA800A;
mbed_official 83:a036322b8637 510 /* Configure PEx pins speed to 50 MHz */
mbed_official 83:a036322b8637 511 GPIOE->OSPEEDR = 0xAAAA800A;
mbed_official 83:a036322b8637 512 /* Configure PEx pins Output type to push-pull */
mbed_official 83:a036322b8637 513 GPIOE->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 514 /* No pull-up, pull-down for PEx pins */
mbed_official 83:a036322b8637 515 GPIOE->PUPDR = 0x55554005;
mbed_official 83:a036322b8637 516
mbed_official 83:a036322b8637 517 /* Connect PFx pins to FMC Alternate function */
mbed_official 83:a036322b8637 518 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 83:a036322b8637 519 GPIOF->AFR[1] = 0xCCCCC000;
mbed_official 83:a036322b8637 520 /* Configure PFx pins in Alternate function mode */
mbed_official 83:a036322b8637 521 GPIOF->MODER = 0xAA800AAA;
mbed_official 83:a036322b8637 522 /* Configure PFx pins speed to 50 MHz */
mbed_official 83:a036322b8637 523 GPIOF->OSPEEDR = 0xAA800AAA;
mbed_official 83:a036322b8637 524 /* Configure PFx pins Output type to push-pull */
mbed_official 83:a036322b8637 525 GPIOF->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 526 /* No pull-up, pull-down for PFx pins */
mbed_official 83:a036322b8637 527 GPIOF->PUPDR = 0x55400555;
mbed_official 83:a036322b8637 528
mbed_official 83:a036322b8637 529 /* Connect PGx pins to FMC Alternate function */
mbed_official 83:a036322b8637 530 GPIOG->AFR[0] = 0x00CC00CC;
mbed_official 83:a036322b8637 531 GPIOG->AFR[1] = 0xC000000C;
mbed_official 83:a036322b8637 532 /* Configure PGx pins in Alternate function mode */
mbed_official 83:a036322b8637 533 GPIOG->MODER = 0x80020A0A;
mbed_official 83:a036322b8637 534 /* Configure PGx pins speed to 50 MHz */
mbed_official 83:a036322b8637 535 GPIOG->OSPEEDR = 0x80020A0A;
mbed_official 83:a036322b8637 536 /* Configure PGx pins Output type to push-pull */
mbed_official 83:a036322b8637 537 GPIOG->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 538 /* No pull-up, pull-down for PGx pins */
mbed_official 83:a036322b8637 539 GPIOG->PUPDR = 0x40010505;
mbed_official 83:a036322b8637 540
mbed_official 83:a036322b8637 541 /* Connect PHx pins to FMC Alternate function */
mbed_official 83:a036322b8637 542 GPIOH->AFR[0] = 0x00C0CC00;
mbed_official 83:a036322b8637 543 GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 544 /* Configure PHx pins in Alternate function mode */
mbed_official 83:a036322b8637 545 GPIOH->MODER = 0xAAAA08A0;
mbed_official 83:a036322b8637 546 /* Configure PHx pins speed to 50 MHz */
mbed_official 83:a036322b8637 547 GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official 83:a036322b8637 548 /* Configure PHx pins Output type to push-pull */
mbed_official 83:a036322b8637 549 GPIOH->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 550 /* No pull-up, pull-down for PHx pins */
mbed_official 83:a036322b8637 551 GPIOH->PUPDR = 0x55550450;
mbed_official 83:a036322b8637 552
mbed_official 83:a036322b8637 553 /* Connect PIx pins to FMC Alternate function */
mbed_official 83:a036322b8637 554 GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 555 GPIOI->AFR[1] = 0x00000CC0;
mbed_official 83:a036322b8637 556 /* Configure PIx pins in Alternate function mode */
mbed_official 83:a036322b8637 557 GPIOI->MODER = 0x0028AAAA;
mbed_official 83:a036322b8637 558 /* Configure PIx pins speed to 50 MHz */
mbed_official 83:a036322b8637 559 GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official 83:a036322b8637 560 /* Configure PIx pins Output type to push-pull */
mbed_official 83:a036322b8637 561 GPIOI->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 562 /* No pull-up, pull-down for PIx pins */
mbed_official 83:a036322b8637 563 GPIOI->PUPDR = 0x00145555;
mbed_official 83:a036322b8637 564
mbed_official 83:a036322b8637 565 /*-- FMC Configuration ------------------------------------------------------*/
mbed_official 83:a036322b8637 566 /* Enable the FMC interface clock */
mbed_official 83:a036322b8637 567 RCC->AHB3ENR |= 0x00000001;
mbed_official 83:a036322b8637 568
mbed_official 83:a036322b8637 569 /* Delay after an RCC peripheral clock enabling */
mbed_official 83:a036322b8637 570 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
mbed_official 83:a036322b8637 571
mbed_official 83:a036322b8637 572 /* Configure and enable SDRAM bank1 */
mbed_official 83:a036322b8637 573 FMC_Bank5_6->SDCR[0] = 0x000019E5;
mbed_official 83:a036322b8637 574 FMC_Bank5_6->SDTR[0] = 0x01116361;
mbed_official 83:a036322b8637 575
mbed_official 83:a036322b8637 576 /* SDRAM initialization sequence */
mbed_official 83:a036322b8637 577 /* Clock enable command */
mbed_official 83:a036322b8637 578 FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official 83:a036322b8637 579 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 580 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 581 {
mbed_official 83:a036322b8637 582 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 583 }
mbed_official 83:a036322b8637 584
mbed_official 83:a036322b8637 585 /* Delay */
mbed_official 83:a036322b8637 586 for (index = 0; index<1000; index++);
mbed_official 83:a036322b8637 587
mbed_official 83:a036322b8637 588 /* PALL command */
mbed_official 83:a036322b8637 589 FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official 83:a036322b8637 590 timeout = 0xFFFF;
mbed_official 83:a036322b8637 591 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 592 {
mbed_official 83:a036322b8637 593 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 594 }
mbed_official 83:a036322b8637 595
mbed_official 83:a036322b8637 596 /* Auto refresh command */
mbed_official 83:a036322b8637 597 FMC_Bank5_6->SDCMR = 0x000000F3;
mbed_official 83:a036322b8637 598 timeout = 0xFFFF;
mbed_official 83:a036322b8637 599 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 600 {
mbed_official 83:a036322b8637 601 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 602 }
mbed_official 83:a036322b8637 603
mbed_official 83:a036322b8637 604 /* MRD register program */
mbed_official 83:a036322b8637 605 FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official 83:a036322b8637 606 timeout = 0xFFFF;
mbed_official 83:a036322b8637 607 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 608 {
mbed_official 83:a036322b8637 609 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 610 }
mbed_official 83:a036322b8637 611
mbed_official 83:a036322b8637 612 /* Set refresh count */
mbed_official 83:a036322b8637 613 tmpreg = FMC_Bank5_6->SDRTR;
mbed_official 83:a036322b8637 614 FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
mbed_official 83:a036322b8637 615
mbed_official 83:a036322b8637 616 /* Disable write protection */
mbed_official 83:a036322b8637 617 tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official 83:a036322b8637 618 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official 83:a036322b8637 619
mbed_official 83:a036322b8637 620 #elif defined(DATA_IN_ExtSRAM)
mbed_official 83:a036322b8637 621 /*-- GPIOs Configuration -----------------------------------------------------*/
mbed_official 83:a036322b8637 622 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official 83:a036322b8637 623 RCC->AHB1ENR |= 0x00000078;
mbed_official 83:a036322b8637 624
mbed_official 83:a036322b8637 625 /* Delay after an RCC peripheral clock enabling */
mbed_official 83:a036322b8637 626 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
mbed_official 83:a036322b8637 627
mbed_official 83:a036322b8637 628 /* Connect PDx pins to FMC Alternate function */
mbed_official 83:a036322b8637 629 GPIOD->AFR[0] = 0x00CCC0CC;
mbed_official 83:a036322b8637 630 GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 631 /* Configure PDx pins in Alternate function mode */
mbed_official 83:a036322b8637 632 GPIOD->MODER = 0xAAAA0A8A;
mbed_official 83:a036322b8637 633 /* Configure PDx pins speed to 100 MHz */
mbed_official 83:a036322b8637 634 GPIOD->OSPEEDR = 0xFFFF0FCF;
mbed_official 83:a036322b8637 635 /* Configure PDx pins Output type to push-pull */
mbed_official 83:a036322b8637 636 GPIOD->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 637 /* No pull-up, pull-down for PDx pins */
mbed_official 83:a036322b8637 638 GPIOD->PUPDR = 0x55550545;
mbed_official 83:a036322b8637 639
mbed_official 83:a036322b8637 640 /* Connect PEx pins to FMC Alternate function */
mbed_official 83:a036322b8637 641 GPIOE->AFR[0] = 0xC00CC0CC;
mbed_official 83:a036322b8637 642 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 643 /* Configure PEx pins in Alternate function mode */
mbed_official 83:a036322b8637 644 GPIOE->MODER = 0xAAAA828A;
mbed_official 83:a036322b8637 645 /* Configure PEx pins speed to 100 MHz */
mbed_official 83:a036322b8637 646 GPIOE->OSPEEDR = 0xFFFFC3CF;
mbed_official 83:a036322b8637 647 /* Configure PEx pins Output type to push-pull */
mbed_official 83:a036322b8637 648 GPIOE->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 649 /* No pull-up, pull-down for PEx pins */
mbed_official 83:a036322b8637 650 GPIOE->PUPDR = 0x55554145;
mbed_official 83:a036322b8637 651
mbed_official 83:a036322b8637 652 /* Connect PFx pins to FMC Alternate function */
mbed_official 83:a036322b8637 653 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 83:a036322b8637 654 GPIOF->AFR[1] = 0xCCCC0000;
mbed_official 83:a036322b8637 655 /* Configure PFx pins in Alternate function mode */
mbed_official 83:a036322b8637 656 GPIOF->MODER = 0xAA000AAA;
mbed_official 83:a036322b8637 657 /* Configure PFx pins speed to 100 MHz */
mbed_official 83:a036322b8637 658 GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official 83:a036322b8637 659 /* Configure PFx pins Output type to push-pull */
mbed_official 83:a036322b8637 660 GPIOF->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 661 /* No pull-up, pull-down for PFx pins */
mbed_official 83:a036322b8637 662 GPIOF->PUPDR = 0x55000555;
mbed_official 83:a036322b8637 663
mbed_official 83:a036322b8637 664 /* Connect PGx pins to FMC Alternate function */
mbed_official 83:a036322b8637 665 GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official 83:a036322b8637 666 GPIOG->AFR[1] = 0x000000C0;
mbed_official 83:a036322b8637 667 /* Configure PGx pins in Alternate function mode */
mbed_official 83:a036322b8637 668 GPIOG->MODER = 0x00200AAA;
mbed_official 83:a036322b8637 669 /* Configure PGx pins speed to 100 MHz */
mbed_official 83:a036322b8637 670 GPIOG->OSPEEDR = 0x00300FFF;
mbed_official 83:a036322b8637 671 /* Configure PGx pins Output type to push-pull */
mbed_official 83:a036322b8637 672 GPIOG->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 673 /* No pull-up, pull-down for PGx pins */
mbed_official 83:a036322b8637 674 GPIOG->PUPDR = 0x00100555;
mbed_official 83:a036322b8637 675
mbed_official 83:a036322b8637 676 /*-- FMC/FSMC Configuration --------------------------------------------------*/
mbed_official 83:a036322b8637 677 /* Enable the FMC/FSMC interface clock */
mbed_official 83:a036322b8637 678 RCC->AHB3ENR |= 0x00000001;
mbed_official 83:a036322b8637 679
mbed_official 83:a036322b8637 680 /* Delay after an RCC peripheral clock enabling */
mbed_official 83:a036322b8637 681 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
mbed_official 83:a036322b8637 682
mbed_official 83:a036322b8637 683 /* Configure and enable Bank1_SRAM2 */
mbed_official 83:a036322b8637 684 FMC_Bank1->BTCR[4] = 0x00001091;
mbed_official 83:a036322b8637 685 FMC_Bank1->BTCR[5] = 0x00110212;
mbed_official 83:a036322b8637 686 FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
mbed_official 83:a036322b8637 687
mbed_official 83:a036322b8637 688 #endif /* DATA_IN_ExtSRAM */
mbed_official 83:a036322b8637 689
mbed_official 83:a036322b8637 690 (void)(tmp);
mbed_official 83:a036322b8637 691 }
mbed_official 83:a036322b8637 692 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 83:a036322b8637 693
mbed_official 74:9322579e4309 694 /**
mbed_official 74:9322579e4309 695 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 74:9322579e4309 696 * AHB/APBx prescalers and Flash settings
mbed_official 74:9322579e4309 697 * @note This function should be called only once the RCC clock configuration
mbed_official 74:9322579e4309 698 * is reset to the default reset state (done in SystemInit() function).
mbed_official 74:9322579e4309 699 * @param None
mbed_official 74:9322579e4309 700 * @retval None
mbed_official 74:9322579e4309 701 */
mbed_official 74:9322579e4309 702 void SetSysClock(void)
mbed_official 74:9322579e4309 703 {
mbed_official 74:9322579e4309 704 /* 1- Try to start with HSE and external clock */
mbed_official 74:9322579e4309 705 #if USE_PLL_HSE_EXTC != 0
mbed_official 74:9322579e4309 706 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 74:9322579e4309 707 #endif
mbed_official 74:9322579e4309 708 {
mbed_official 74:9322579e4309 709 /* 2- If fail try to start with HSE and external xtal */
mbed_official 74:9322579e4309 710 #if USE_PLL_HSE_XTAL != 0
mbed_official 74:9322579e4309 711 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 74:9322579e4309 712 #endif
mbed_official 74:9322579e4309 713 {
mbed_official 74:9322579e4309 714 /* 3- If fail start with HSI clock */
mbed_official 74:9322579e4309 715 if (SetSysClock_PLL_HSI() == 0)
mbed_official 74:9322579e4309 716 {
mbed_official 74:9322579e4309 717 while(1)
mbed_official 74:9322579e4309 718 {
mbed_official 74:9322579e4309 719 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 74:9322579e4309 720 }
mbed_official 74:9322579e4309 721 }
mbed_official 74:9322579e4309 722 }
mbed_official 74:9322579e4309 723 }
mbed_official 74:9322579e4309 724
mbed_official 74:9322579e4309 725 // Output clock on MCO2 pin(PC9) for debugging purpose
mbed_official 74:9322579e4309 726 // Can be visualized on CN8 connector pin 4
mbed_official 74:9322579e4309 727 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
mbed_official 74:9322579e4309 728 }
mbed_official 74:9322579e4309 729
mbed_official 74:9322579e4309 730 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 74:9322579e4309 731 /******************************************************************************/
mbed_official 74:9322579e4309 732 /* PLL (clocked by HSE) used as System clock source */
mbed_official 74:9322579e4309 733 /******************************************************************************/
mbed_official 74:9322579e4309 734 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 74:9322579e4309 735 {
mbed_official 74:9322579e4309 736 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 74:9322579e4309 737 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 74:9322579e4309 738
mbed_official 74:9322579e4309 739 // Enable power clock
mbed_official 74:9322579e4309 740 __PWR_CLK_ENABLE();
mbed_official 74:9322579e4309 741
mbed_official 74:9322579e4309 742 // Enable HSE oscillator and activate PLL with HSE as source
mbed_official 74:9322579e4309 743 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 74:9322579e4309 744 if (bypass == 0)
mbed_official 74:9322579e4309 745 {
mbed_official 74:9322579e4309 746 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
mbed_official 74:9322579e4309 747 }
mbed_official 74:9322579e4309 748 else
mbed_official 74:9322579e4309 749 {
mbed_official 74:9322579e4309 750 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */
mbed_official 74:9322579e4309 751 }
mbed_official 74:9322579e4309 752 // Warning: this configuration is for a 8 MHz xtal clock only
mbed_official 74:9322579e4309 753 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 74:9322579e4309 754 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 74:9322579e4309 755 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
mbed_official 74:9322579e4309 756 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
mbed_official 74:9322579e4309 757 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
mbed_official 74:9322579e4309 758 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
mbed_official 74:9322579e4309 759
mbed_official 74:9322579e4309 760 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 74:9322579e4309 761 {
mbed_official 74:9322579e4309 762 return 0; // FAIL
mbed_official 74:9322579e4309 763 }
mbed_official 74:9322579e4309 764
mbed_official 74:9322579e4309 765 // Activate the OverDrive to reach the 216 MHz Frequency
mbed_official 74:9322579e4309 766 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
mbed_official 74:9322579e4309 767 {
mbed_official 74:9322579e4309 768 return 0; // FAIL
mbed_official 74:9322579e4309 769 }
mbed_official 74:9322579e4309 770
mbed_official 74:9322579e4309 771 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
mbed_official 74:9322579e4309 772 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 74:9322579e4309 773 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
mbed_official 74:9322579e4309 774 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
mbed_official 74:9322579e4309 775 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
mbed_official 74:9322579e4309 776 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
mbed_official 74:9322579e4309 777
mbed_official 74:9322579e4309 778 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
mbed_official 74:9322579e4309 779 {
mbed_official 74:9322579e4309 780 return 0; // FAIL
mbed_official 74:9322579e4309 781 }
mbed_official 74:9322579e4309 782
mbed_official 74:9322579e4309 783 return 1; // OK
mbed_official 74:9322579e4309 784 }
mbed_official 74:9322579e4309 785 #endif
mbed_official 74:9322579e4309 786
mbed_official 74:9322579e4309 787 /******************************************************************************/
mbed_official 74:9322579e4309 788 /* PLL (clocked by HSI) used as System clock source */
mbed_official 74:9322579e4309 789 /******************************************************************************/
mbed_official 74:9322579e4309 790 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 74:9322579e4309 791 {
mbed_official 74:9322579e4309 792 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 74:9322579e4309 793 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 74:9322579e4309 794
mbed_official 74:9322579e4309 795 // Enable CPU L1-Cache
mbed_official 74:9322579e4309 796 SCB_EnableICache();
mbed_official 74:9322579e4309 797 SCB_EnableDCache();
mbed_official 74:9322579e4309 798
mbed_official 74:9322579e4309 799 // Enable power clock
mbed_official 74:9322579e4309 800 __PWR_CLK_ENABLE();
mbed_official 74:9322579e4309 801
mbed_official 74:9322579e4309 802 // Enable HSI oscillator and activate PLL with HSI as source
mbed_official 74:9322579e4309 803 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 74:9322579e4309 804 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 74:9322579e4309 805 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 74:9322579e4309 806 RCC_OscInitStruct.HSICalibrationValue = 16;
mbed_official 74:9322579e4309 807 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 74:9322579e4309 808 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 74:9322579e4309 809 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
mbed_official 74:9322579e4309 810 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
mbed_official 74:9322579e4309 811 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
mbed_official 74:9322579e4309 812 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
mbed_official 74:9322579e4309 813
mbed_official 74:9322579e4309 814 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 74:9322579e4309 815 {
mbed_official 74:9322579e4309 816 return 0; // FAIL
mbed_official 74:9322579e4309 817 }
mbed_official 74:9322579e4309 818
mbed_official 74:9322579e4309 819 // Activate the OverDrive to reach the 216 MHz Frequency
mbed_official 74:9322579e4309 820 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
mbed_official 74:9322579e4309 821 {
mbed_official 74:9322579e4309 822 return 0; // FAIL
mbed_official 74:9322579e4309 823 }
mbed_official 74:9322579e4309 824
mbed_official 74:9322579e4309 825 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
mbed_official 74:9322579e4309 826 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 74:9322579e4309 827 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
mbed_official 74:9322579e4309 828 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
mbed_official 74:9322579e4309 829 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
mbed_official 74:9322579e4309 830 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
mbed_official 74:9322579e4309 831
mbed_official 74:9322579e4309 832 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
mbed_official 74:9322579e4309 833 {
mbed_official 74:9322579e4309 834 return 0; // FAIL
mbed_official 74:9322579e4309 835 }
mbed_official 74:9322579e4309 836
mbed_official 74:9322579e4309 837 return 1; // OK
mbed_official 74:9322579e4309 838 }
mbed_official 74:9322579e4309 839
mbed_official 74:9322579e4309 840 /**
mbed_official 74:9322579e4309 841 * @}
mbed_official 74:9322579e4309 842 */
mbed_official 74:9322579e4309 843
mbed_official 74:9322579e4309 844 /**
mbed_official 74:9322579e4309 845 * @}
mbed_official 74:9322579e4309 846 */
mbed_official 74:9322579e4309 847
mbed_official 74:9322579e4309 848 /**
mbed_official 74:9322579e4309 849 * @}
mbed_official 74:9322579e4309 850 */
mbed_official 74:9322579e4309 851 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/