en 129
fix LPC812 PWM
Fork of
mbed-dev
by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_fmc.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32l4xx_ll_fmc.h |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.0.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 26-June-2015 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file of FMC HAL module. |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * @attention |
| bogdanm | 0:9b334a45a8ff | 10 | * |
| bogdanm | 0:9b334a45a8ff | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 12 | * |
| bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 23 | * |
| bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 34 | * |
| bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 36 | */ |
| bogdanm | 0:9b334a45a8ff | 37 | |
| bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32L4xx_LL_FMC_H |
| bogdanm | 0:9b334a45a8ff | 40 | #define __STM32L4xx_LL_FMC_H |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 44 | #endif |
| bogdanm | 0:9b334a45a8ff | 45 | |
| bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 47 | #include "stm32l4xx_hal_def.h" |
| bogdanm | 0:9b334a45a8ff | 48 | |
| bogdanm | 0:9b334a45a8ff | 49 | /** @addtogroup STM32L4xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 50 | * @{ |
| bogdanm | 0:9b334a45a8ff | 51 | */ |
| bogdanm | 0:9b334a45a8ff | 52 | |
| bogdanm | 0:9b334a45a8ff | 53 | /** @addtogroup FMC_LL FMC Low Layer |
| bogdanm | 0:9b334a45a8ff | 54 | * @{ |
| bogdanm | 0:9b334a45a8ff | 55 | */ |
| bogdanm | 0:9b334a45a8ff | 56 | |
| bogdanm | 0:9b334a45a8ff | 57 | /** @addtogroup FMC_LL_Private_Macros FMC Low Layer Private Macros |
| bogdanm | 0:9b334a45a8ff | 58 | * @{ |
| bogdanm | 0:9b334a45a8ff | 59 | */ |
| bogdanm | 0:9b334a45a8ff | 60 | #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ |
| bogdanm | 0:9b334a45a8ff | 61 | ((__BANK__) == FMC_NORSRAM_BANK2) || \ |
| bogdanm | 0:9b334a45a8ff | 62 | ((__BANK__) == FMC_NORSRAM_BANK3) || \ |
| bogdanm | 0:9b334a45a8ff | 63 | ((__BANK__) == FMC_NORSRAM_BANK4)) |
| bogdanm | 0:9b334a45a8ff | 64 | |
| bogdanm | 0:9b334a45a8ff | 65 | |
| bogdanm | 0:9b334a45a8ff | 66 | #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 67 | ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 68 | |
| bogdanm | 0:9b334a45a8ff | 69 | |
| bogdanm | 0:9b334a45a8ff | 70 | #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ |
| bogdanm | 0:9b334a45a8ff | 71 | ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ |
| bogdanm | 0:9b334a45a8ff | 72 | ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) |
| bogdanm | 0:9b334a45a8ff | 73 | |
| bogdanm | 0:9b334a45a8ff | 74 | #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| bogdanm | 0:9b334a45a8ff | 75 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| bogdanm | 0:9b334a45a8ff | 76 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| bogdanm | 0:9b334a45a8ff | 77 | |
| bogdanm | 0:9b334a45a8ff | 78 | #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ |
| bogdanm | 0:9b334a45a8ff | 79 | ((__SIZE__) == FMC_PAGE_SIZE_128) || \ |
| bogdanm | 0:9b334a45a8ff | 80 | ((__SIZE__) == FMC_PAGE_SIZE_256) || \ |
| bogdanm | 0:9b334a45a8ff | 81 | ((__SIZE__) == FMC_PAGE_SIZE_1024)) |
| bogdanm | 0:9b334a45a8ff | 82 | |
| bogdanm | 0:9b334a45a8ff | 83 | #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 84 | ((__BURST__) == FMC_WRITE_BURST_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 85 | |
| bogdanm | 0:9b334a45a8ff | 86 | #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
| bogdanm | 0:9b334a45a8ff | 87 | ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
| bogdanm | 0:9b334a45a8ff | 88 | |
| bogdanm | 0:9b334a45a8ff | 89 | #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 90 | ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 91 | |
| bogdanm | 0:9b334a45a8ff | 92 | |
| bogdanm | 0:9b334a45a8ff | 93 | #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ |
| bogdanm | 0:9b334a45a8ff | 94 | ((__MODE__) == FMC_ACCESS_MODE_B) || \ |
| bogdanm | 0:9b334a45a8ff | 95 | ((__MODE__) == FMC_ACCESS_MODE_C) || \ |
| bogdanm | 0:9b334a45a8ff | 96 | ((__MODE__) == FMC_ACCESS_MODE_D)) |
| bogdanm | 0:9b334a45a8ff | 97 | |
| bogdanm | 0:9b334a45a8ff | 98 | |
| bogdanm | 0:9b334a45a8ff | 99 | #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) |
| bogdanm | 0:9b334a45a8ff | 100 | |
| bogdanm | 0:9b334a45a8ff | 101 | #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 102 | ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 103 | |
| bogdanm | 0:9b334a45a8ff | 104 | #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ |
| bogdanm | 0:9b334a45a8ff | 105 | ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) |
| bogdanm | 0:9b334a45a8ff | 106 | |
| bogdanm | 0:9b334a45a8ff | 107 | #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 108 | ((__STATE__) == FMC_NAND_ECC_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 109 | |
| bogdanm | 0:9b334a45a8ff | 110 | |
| bogdanm | 0:9b334a45a8ff | 111 | #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
| bogdanm | 0:9b334a45a8ff | 112 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
| bogdanm | 0:9b334a45a8ff | 113 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
| bogdanm | 0:9b334a45a8ff | 114 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
| bogdanm | 0:9b334a45a8ff | 115 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
| bogdanm | 0:9b334a45a8ff | 116 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
| bogdanm | 0:9b334a45a8ff | 117 | |
| bogdanm | 0:9b334a45a8ff | 118 | |
| bogdanm | 0:9b334a45a8ff | 119 | /** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance |
| bogdanm | 0:9b334a45a8ff | 120 | * @{ |
| bogdanm | 0:9b334a45a8ff | 121 | */ |
| bogdanm | 0:9b334a45a8ff | 122 | #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) |
| bogdanm | 0:9b334a45a8ff | 123 | /** |
| bogdanm | 0:9b334a45a8ff | 124 | * @} |
| bogdanm | 0:9b334a45a8ff | 125 | */ |
| bogdanm | 0:9b334a45a8ff | 126 | |
| bogdanm | 0:9b334a45a8ff | 127 | /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance |
| bogdanm | 0:9b334a45a8ff | 128 | * @{ |
| bogdanm | 0:9b334a45a8ff | 129 | */ |
| bogdanm | 0:9b334a45a8ff | 130 | #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) |
| bogdanm | 0:9b334a45a8ff | 131 | /** |
| bogdanm | 0:9b334a45a8ff | 132 | * @} |
| bogdanm | 0:9b334a45a8ff | 133 | */ |
| bogdanm | 0:9b334a45a8ff | 134 | |
| bogdanm | 0:9b334a45a8ff | 135 | /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance |
| bogdanm | 0:9b334a45a8ff | 136 | * @{ |
| bogdanm | 0:9b334a45a8ff | 137 | */ |
| bogdanm | 0:9b334a45a8ff | 138 | #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) |
| bogdanm | 0:9b334a45a8ff | 139 | /** |
| bogdanm | 0:9b334a45a8ff | 140 | * @} |
| bogdanm | 0:9b334a45a8ff | 141 | */ |
| bogdanm | 0:9b334a45a8ff | 142 | |
| bogdanm | 0:9b334a45a8ff | 143 | #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 144 | ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 145 | |
| bogdanm | 0:9b334a45a8ff | 146 | #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| bogdanm | 0:9b334a45a8ff | 147 | ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| bogdanm | 0:9b334a45a8ff | 148 | |
| bogdanm | 0:9b334a45a8ff | 149 | #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ |
| bogdanm | 0:9b334a45a8ff | 150 | ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) |
| bogdanm | 0:9b334a45a8ff | 151 | |
| bogdanm | 0:9b334a45a8ff | 152 | |
| bogdanm | 0:9b334a45a8ff | 153 | #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 154 | ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 155 | |
| bogdanm | 0:9b334a45a8ff | 156 | #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 157 | ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 158 | |
| bogdanm | 0:9b334a45a8ff | 159 | #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 160 | ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 161 | |
| bogdanm | 0:9b334a45a8ff | 162 | #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 163 | ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 164 | |
| bogdanm | 0:9b334a45a8ff | 165 | /** @defgroup FMC_Address_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 166 | * @{ |
| bogdanm | 0:9b334a45a8ff | 167 | */ |
| bogdanm | 0:9b334a45a8ff | 168 | #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) |
| bogdanm | 0:9b334a45a8ff | 169 | /** |
| bogdanm | 0:9b334a45a8ff | 170 | * @} |
| bogdanm | 0:9b334a45a8ff | 171 | */ |
| bogdanm | 0:9b334a45a8ff | 172 | |
| bogdanm | 0:9b334a45a8ff | 173 | /** @defgroup FMC_Address_Hold_Time |
| bogdanm | 0:9b334a45a8ff | 174 | * @{ |
| bogdanm | 0:9b334a45a8ff | 175 | */ |
| bogdanm | 0:9b334a45a8ff | 176 | #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) |
| bogdanm | 0:9b334a45a8ff | 177 | /** |
| bogdanm | 0:9b334a45a8ff | 178 | * @} |
| bogdanm | 0:9b334a45a8ff | 179 | */ |
| bogdanm | 0:9b334a45a8ff | 180 | |
| bogdanm | 0:9b334a45a8ff | 181 | /** @defgroup FMC_Data_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 182 | * @{ |
| bogdanm | 0:9b334a45a8ff | 183 | */ |
| bogdanm | 0:9b334a45a8ff | 184 | #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) |
| bogdanm | 0:9b334a45a8ff | 185 | /** |
| bogdanm | 0:9b334a45a8ff | 186 | * @} |
| bogdanm | 0:9b334a45a8ff | 187 | */ |
| bogdanm | 0:9b334a45a8ff | 188 | |
| bogdanm | 0:9b334a45a8ff | 189 | /** @defgroup FMC_Bus_Turn_around_Duration |
| bogdanm | 0:9b334a45a8ff | 190 | * @{ |
| bogdanm | 0:9b334a45a8ff | 191 | */ |
| bogdanm | 0:9b334a45a8ff | 192 | #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) |
| bogdanm | 0:9b334a45a8ff | 193 | /** |
| bogdanm | 0:9b334a45a8ff | 194 | * @} |
| bogdanm | 0:9b334a45a8ff | 195 | */ |
| bogdanm | 0:9b334a45a8ff | 196 | |
| bogdanm | 0:9b334a45a8ff | 197 | /** @defgroup FMC_CLK_Division |
| bogdanm | 0:9b334a45a8ff | 198 | * @{ |
| bogdanm | 0:9b334a45a8ff | 199 | */ |
| bogdanm | 0:9b334a45a8ff | 200 | #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) |
| bogdanm | 0:9b334a45a8ff | 201 | /** |
| bogdanm | 0:9b334a45a8ff | 202 | * @} |
| bogdanm | 0:9b334a45a8ff | 203 | */ |
| bogdanm | 0:9b334a45a8ff | 204 | |
| bogdanm | 0:9b334a45a8ff | 205 | /** @defgroup FMC_Data_Latency |
| bogdanm | 0:9b334a45a8ff | 206 | * @{ |
| bogdanm | 0:9b334a45a8ff | 207 | */ |
| bogdanm | 0:9b334a45a8ff | 208 | #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) |
| bogdanm | 0:9b334a45a8ff | 209 | /** |
| bogdanm | 0:9b334a45a8ff | 210 | * @} |
| bogdanm | 0:9b334a45a8ff | 211 | */ |
| bogdanm | 0:9b334a45a8ff | 212 | |
| bogdanm | 0:9b334a45a8ff | 213 | /** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time |
| bogdanm | 0:9b334a45a8ff | 214 | * @{ |
| bogdanm | 0:9b334a45a8ff | 215 | */ |
| bogdanm | 0:9b334a45a8ff | 216 | #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) |
| bogdanm | 0:9b334a45a8ff | 217 | /** |
| bogdanm | 0:9b334a45a8ff | 218 | * @} |
| bogdanm | 0:9b334a45a8ff | 219 | */ |
| bogdanm | 0:9b334a45a8ff | 220 | |
| bogdanm | 0:9b334a45a8ff | 221 | /** @defgroup FMC_TAR_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 222 | * @{ |
| bogdanm | 0:9b334a45a8ff | 223 | */ |
| bogdanm | 0:9b334a45a8ff | 224 | #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) |
| bogdanm | 0:9b334a45a8ff | 225 | /** |
| bogdanm | 0:9b334a45a8ff | 226 | * @} |
| bogdanm | 0:9b334a45a8ff | 227 | */ |
| bogdanm | 0:9b334a45a8ff | 228 | |
| bogdanm | 0:9b334a45a8ff | 229 | /** @defgroup FMC_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 230 | * @{ |
| bogdanm | 0:9b334a45a8ff | 231 | */ |
| bogdanm | 0:9b334a45a8ff | 232 | #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255) |
| bogdanm | 0:9b334a45a8ff | 233 | /** |
| bogdanm | 0:9b334a45a8ff | 234 | * @} |
| bogdanm | 0:9b334a45a8ff | 235 | */ |
| bogdanm | 0:9b334a45a8ff | 236 | |
| bogdanm | 0:9b334a45a8ff | 237 | /** @defgroup FMC_Wait_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 238 | * @{ |
| bogdanm | 0:9b334a45a8ff | 239 | */ |
| bogdanm | 0:9b334a45a8ff | 240 | #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255) |
| bogdanm | 0:9b334a45a8ff | 241 | /** |
| bogdanm | 0:9b334a45a8ff | 242 | * @} |
| bogdanm | 0:9b334a45a8ff | 243 | */ |
| bogdanm | 0:9b334a45a8ff | 244 | |
| bogdanm | 0:9b334a45a8ff | 245 | /** @defgroup FMC_Hold_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 246 | * @{ |
| bogdanm | 0:9b334a45a8ff | 247 | */ |
| bogdanm | 0:9b334a45a8ff | 248 | #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255) |
| bogdanm | 0:9b334a45a8ff | 249 | /** |
| bogdanm | 0:9b334a45a8ff | 250 | * @} |
| bogdanm | 0:9b334a45a8ff | 251 | */ |
| bogdanm | 0:9b334a45a8ff | 252 | |
| bogdanm | 0:9b334a45a8ff | 253 | /** @defgroup FMC_HiZ_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 254 | * @{ |
| bogdanm | 0:9b334a45a8ff | 255 | */ |
| bogdanm | 0:9b334a45a8ff | 256 | #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255) |
| bogdanm | 0:9b334a45a8ff | 257 | /** |
| bogdanm | 0:9b334a45a8ff | 258 | * @} |
| bogdanm | 0:9b334a45a8ff | 259 | */ |
| bogdanm | 0:9b334a45a8ff | 260 | |
| bogdanm | 0:9b334a45a8ff | 261 | /** |
| bogdanm | 0:9b334a45a8ff | 262 | * @} |
| bogdanm | 0:9b334a45a8ff | 263 | */ |
| bogdanm | 0:9b334a45a8ff | 264 | |
| bogdanm | 0:9b334a45a8ff | 265 | /* Exported typedef ----------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 266 | /** @addtogroup FMC_LL_Exported_Typedef FMC Low Layer Exported Typedef |
| bogdanm | 0:9b334a45a8ff | 267 | * @{ |
| bogdanm | 0:9b334a45a8ff | 268 | */ |
| bogdanm | 0:9b334a45a8ff | 269 | #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef |
| bogdanm | 0:9b334a45a8ff | 270 | #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef |
| bogdanm | 0:9b334a45a8ff | 271 | #define FMC_NAND_TypeDef FMC_Bank3_TypeDef |
| bogdanm | 0:9b334a45a8ff | 272 | |
| bogdanm | 0:9b334a45a8ff | 273 | #define FMC_NORSRAM_DEVICE FMC_Bank1_R |
| bogdanm | 0:9b334a45a8ff | 274 | #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R |
| bogdanm | 0:9b334a45a8ff | 275 | #define FMC_NAND_DEVICE FMC_Bank3_R |
| bogdanm | 0:9b334a45a8ff | 276 | |
| bogdanm | 0:9b334a45a8ff | 277 | /** |
| bogdanm | 0:9b334a45a8ff | 278 | * @brief FMC_NORSRAM Configuration Structure definition |
| bogdanm | 0:9b334a45a8ff | 279 | */ |
| bogdanm | 0:9b334a45a8ff | 280 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 281 | { |
| bogdanm | 0:9b334a45a8ff | 282 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| bogdanm | 0:9b334a45a8ff | 283 | This parameter can be a value of @ref FMC_NORSRAM_Bank */ |
| bogdanm | 0:9b334a45a8ff | 284 | |
| bogdanm | 0:9b334a45a8ff | 285 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
| bogdanm | 0:9b334a45a8ff | 286 | multiplexed on the data bus or not. |
| bogdanm | 0:9b334a45a8ff | 287 | This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ |
| bogdanm | 0:9b334a45a8ff | 288 | |
| bogdanm | 0:9b334a45a8ff | 289 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
| bogdanm | 0:9b334a45a8ff | 290 | the corresponding memory device. |
| bogdanm | 0:9b334a45a8ff | 291 | This parameter can be a value of @ref FMC_Memory_Type */ |
| bogdanm | 0:9b334a45a8ff | 292 | |
| bogdanm | 0:9b334a45a8ff | 293 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| bogdanm | 0:9b334a45a8ff | 294 | This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ |
| bogdanm | 0:9b334a45a8ff | 295 | |
| bogdanm | 0:9b334a45a8ff | 296 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
| bogdanm | 0:9b334a45a8ff | 297 | valid only with synchronous burst Flash memories. |
| bogdanm | 0:9b334a45a8ff | 298 | This parameter can be a value of @ref FMC_Burst_Access_Mode */ |
| bogdanm | 0:9b334a45a8ff | 299 | |
| bogdanm | 0:9b334a45a8ff | 300 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
| bogdanm | 0:9b334a45a8ff | 301 | the Flash memory in burst mode. |
| bogdanm | 0:9b334a45a8ff | 302 | This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ |
| bogdanm | 0:9b334a45a8ff | 303 | |
| bogdanm | 0:9b334a45a8ff | 304 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
| bogdanm | 0:9b334a45a8ff | 305 | clock cycle before the wait state or during the wait state, |
| bogdanm | 0:9b334a45a8ff | 306 | valid only when accessing memories in burst mode. |
| bogdanm | 0:9b334a45a8ff | 307 | This parameter can be a value of @ref FMC_Wait_Timing */ |
| bogdanm | 0:9b334a45a8ff | 308 | |
| bogdanm | 0:9b334a45a8ff | 309 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. |
| bogdanm | 0:9b334a45a8ff | 310 | This parameter can be a value of @ref FMC_Write_Operation */ |
| bogdanm | 0:9b334a45a8ff | 311 | |
| bogdanm | 0:9b334a45a8ff | 312 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
| bogdanm | 0:9b334a45a8ff | 313 | signal, valid for Flash memory access in burst mode. |
| bogdanm | 0:9b334a45a8ff | 314 | This parameter can be a value of @ref FMC_Wait_Signal */ |
| bogdanm | 0:9b334a45a8ff | 315 | |
| bogdanm | 0:9b334a45a8ff | 316 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
| bogdanm | 0:9b334a45a8ff | 317 | This parameter can be a value of @ref FMC_Extended_Mode */ |
| bogdanm | 0:9b334a45a8ff | 318 | |
| bogdanm | 0:9b334a45a8ff | 319 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
| bogdanm | 0:9b334a45a8ff | 320 | valid only with asynchronous Flash memories. |
| bogdanm | 0:9b334a45a8ff | 321 | This parameter can be a value of @ref FMC_AsynchronousWait */ |
| bogdanm | 0:9b334a45a8ff | 322 | |
| bogdanm | 0:9b334a45a8ff | 323 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
| bogdanm | 0:9b334a45a8ff | 324 | This parameter can be a value of @ref FMC_Write_Burst */ |
| bogdanm | 0:9b334a45a8ff | 325 | |
| bogdanm | 0:9b334a45a8ff | 326 | uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. |
| bogdanm | 0:9b334a45a8ff | 327 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
| bogdanm | 0:9b334a45a8ff | 328 | through FMC_BCR2..4 registers. |
| bogdanm | 0:9b334a45a8ff | 329 | This parameter can be a value of @ref FMC_Continous_Clock */ |
| bogdanm | 0:9b334a45a8ff | 330 | |
| bogdanm | 0:9b334a45a8ff | 331 | uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. |
| bogdanm | 0:9b334a45a8ff | 332 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
| bogdanm | 0:9b334a45a8ff | 333 | through FMC_BCR2..4 registers. |
| bogdanm | 0:9b334a45a8ff | 334 | This parameter can be a value of @ref FMC_Write_FIFO */ |
| bogdanm | 0:9b334a45a8ff | 335 | |
| bogdanm | 0:9b334a45a8ff | 336 | uint32_t PageSize; /*!< Specifies the memory page size. |
| bogdanm | 0:9b334a45a8ff | 337 | This parameter can be a value of @ref FMC_Page_Size */ |
| bogdanm | 0:9b334a45a8ff | 338 | |
| bogdanm | 0:9b334a45a8ff | 339 | }FMC_NORSRAM_InitTypeDef; |
| bogdanm | 0:9b334a45a8ff | 340 | |
| bogdanm | 0:9b334a45a8ff | 341 | /** |
| bogdanm | 0:9b334a45a8ff | 342 | * @brief FMC_NORSRAM Timing parameters structure definition |
| bogdanm | 0:9b334a45a8ff | 343 | */ |
| bogdanm | 0:9b334a45a8ff | 344 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 345 | { |
| bogdanm | 0:9b334a45a8ff | 346 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| bogdanm | 0:9b334a45a8ff | 347 | the duration of the address setup time. |
| bogdanm | 0:9b334a45a8ff | 348 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| bogdanm | 0:9b334a45a8ff | 349 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| bogdanm | 0:9b334a45a8ff | 350 | |
| bogdanm | 0:9b334a45a8ff | 351 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
| bogdanm | 0:9b334a45a8ff | 352 | the duration of the address hold time. |
| bogdanm | 0:9b334a45a8ff | 353 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| bogdanm | 0:9b334a45a8ff | 354 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| bogdanm | 0:9b334a45a8ff | 355 | |
| bogdanm | 0:9b334a45a8ff | 356 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
| bogdanm | 0:9b334a45a8ff | 357 | the duration of the data setup time. |
| bogdanm | 0:9b334a45a8ff | 358 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| bogdanm | 0:9b334a45a8ff | 359 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| bogdanm | 0:9b334a45a8ff | 360 | NOR Flash memories. */ |
| bogdanm | 0:9b334a45a8ff | 361 | |
| bogdanm | 0:9b334a45a8ff | 362 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
| bogdanm | 0:9b334a45a8ff | 363 | the duration of the bus turnaround. |
| bogdanm | 0:9b334a45a8ff | 364 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| bogdanm | 0:9b334a45a8ff | 365 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| bogdanm | 0:9b334a45a8ff | 366 | |
| bogdanm | 0:9b334a45a8ff | 367 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
| bogdanm | 0:9b334a45a8ff | 368 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
| bogdanm | 0:9b334a45a8ff | 369 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| bogdanm | 0:9b334a45a8ff | 370 | accesses. */ |
| bogdanm | 0:9b334a45a8ff | 371 | |
| bogdanm | 0:9b334a45a8ff | 372 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
| bogdanm | 0:9b334a45a8ff | 373 | to the memory before getting the first data. |
| bogdanm | 0:9b334a45a8ff | 374 | The parameter value depends on the memory type as shown below: |
| bogdanm | 0:9b334a45a8ff | 375 | - It must be set to 0 in case of a CRAM |
| bogdanm | 0:9b334a45a8ff | 376 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| bogdanm | 0:9b334a45a8ff | 377 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
| bogdanm | 0:9b334a45a8ff | 378 | with synchronous burst mode enable */ |
| bogdanm | 0:9b334a45a8ff | 379 | |
| bogdanm | 0:9b334a45a8ff | 380 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
| bogdanm | 0:9b334a45a8ff | 381 | This parameter can be a value of @ref FMC_Access_Mode */ |
| bogdanm | 0:9b334a45a8ff | 382 | }FMC_NORSRAM_TimingTypeDef; |
| bogdanm | 0:9b334a45a8ff | 383 | |
| bogdanm | 0:9b334a45a8ff | 384 | /** |
| bogdanm | 0:9b334a45a8ff | 385 | * @brief FMC_NAND Configuration Structure definition |
| bogdanm | 0:9b334a45a8ff | 386 | */ |
| bogdanm | 0:9b334a45a8ff | 387 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 388 | { |
| bogdanm | 0:9b334a45a8ff | 389 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
| bogdanm | 0:9b334a45a8ff | 390 | This parameter can be a value of @ref FMC_NAND_Bank */ |
| bogdanm | 0:9b334a45a8ff | 391 | |
| bogdanm | 0:9b334a45a8ff | 392 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
| bogdanm | 0:9b334a45a8ff | 393 | This parameter can be any value of @ref FMC_Wait_feature */ |
| bogdanm | 0:9b334a45a8ff | 394 | |
| bogdanm | 0:9b334a45a8ff | 395 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| bogdanm | 0:9b334a45a8ff | 396 | This parameter can be any value of @ref FMC_NAND_Data_Width */ |
| bogdanm | 0:9b334a45a8ff | 397 | |
| bogdanm | 0:9b334a45a8ff | 398 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
| bogdanm | 0:9b334a45a8ff | 399 | This parameter can be any value of @ref FMC_ECC */ |
| bogdanm | 0:9b334a45a8ff | 400 | |
| bogdanm | 0:9b334a45a8ff | 401 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
| bogdanm | 0:9b334a45a8ff | 402 | This parameter can be any value of @ref FMC_ECC_Page_Size */ |
| bogdanm | 0:9b334a45a8ff | 403 | |
| bogdanm | 0:9b334a45a8ff | 404 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| bogdanm | 0:9b334a45a8ff | 405 | delay between CLE low and RE low. |
| bogdanm | 0:9b334a45a8ff | 406 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 407 | |
| bogdanm | 0:9b334a45a8ff | 408 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| bogdanm | 0:9b334a45a8ff | 409 | delay between ALE low and RE low. |
| bogdanm | 0:9b334a45a8ff | 410 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 411 | }FMC_NAND_InitTypeDef; |
| bogdanm | 0:9b334a45a8ff | 412 | |
| bogdanm | 0:9b334a45a8ff | 413 | /** |
| bogdanm | 0:9b334a45a8ff | 414 | * @brief FMC_NAND Timing parameters structure definition |
| bogdanm | 0:9b334a45a8ff | 415 | */ |
| bogdanm | 0:9b334a45a8ff | 416 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 417 | { |
| bogdanm | 0:9b334a45a8ff | 418 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
| bogdanm | 0:9b334a45a8ff | 419 | the command assertion for NAND-Flash read or write access |
| bogdanm | 0:9b334a45a8ff | 420 | to common/Attribute or I/O memory space (depending on |
| bogdanm | 0:9b334a45a8ff | 421 | the memory space timing to be configured). |
| bogdanm | 0:9b334a45a8ff | 422 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 423 | |
| bogdanm | 0:9b334a45a8ff | 424 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
| bogdanm | 0:9b334a45a8ff | 425 | command for NAND-Flash read or write access to |
| bogdanm | 0:9b334a45a8ff | 426 | common/Attribute or I/O memory space (depending on the |
| bogdanm | 0:9b334a45a8ff | 427 | memory space timing to be configured). |
| bogdanm | 0:9b334a45a8ff | 428 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 429 | |
| bogdanm | 0:9b334a45a8ff | 430 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
| bogdanm | 0:9b334a45a8ff | 431 | (and data for write access) after the command de-assertion |
| bogdanm | 0:9b334a45a8ff | 432 | for NAND-Flash read or write access to common/Attribute |
| bogdanm | 0:9b334a45a8ff | 433 | or I/O memory space (depending on the memory space timing |
| bogdanm | 0:9b334a45a8ff | 434 | to be configured). |
| bogdanm | 0:9b334a45a8ff | 435 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 436 | |
| bogdanm | 0:9b334a45a8ff | 437 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
| bogdanm | 0:9b334a45a8ff | 438 | data bus is kept in HiZ after the start of a NAND-Flash |
| bogdanm | 0:9b334a45a8ff | 439 | write access to common/Attribute or I/O memory space (depending |
| bogdanm | 0:9b334a45a8ff | 440 | on the memory space timing to be configured). |
| bogdanm | 0:9b334a45a8ff | 441 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 442 | }FMC_NAND_PCC_TimingTypeDef; |
| bogdanm | 0:9b334a45a8ff | 443 | |
| bogdanm | 0:9b334a45a8ff | 444 | /** |
| bogdanm | 0:9b334a45a8ff | 445 | * @} |
| bogdanm | 0:9b334a45a8ff | 446 | */ |
| bogdanm | 0:9b334a45a8ff | 447 | |
| bogdanm | 0:9b334a45a8ff | 448 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 449 | /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants |
| bogdanm | 0:9b334a45a8ff | 450 | * @{ |
| bogdanm | 0:9b334a45a8ff | 451 | */ |
| bogdanm | 0:9b334a45a8ff | 452 | |
| bogdanm | 0:9b334a45a8ff | 453 | /** @defgroup FMC_NOR_SRAM_Exported_constants FMC NOR/SRAM Exported constants |
| bogdanm | 0:9b334a45a8ff | 454 | * @{ |
| bogdanm | 0:9b334a45a8ff | 455 | */ |
| bogdanm | 0:9b334a45a8ff | 456 | |
| bogdanm | 0:9b334a45a8ff | 457 | /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank |
| bogdanm | 0:9b334a45a8ff | 458 | * @{ |
| bogdanm | 0:9b334a45a8ff | 459 | */ |
| bogdanm | 0:9b334a45a8ff | 460 | #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 461 | #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) |
| bogdanm | 0:9b334a45a8ff | 462 | #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) |
| bogdanm | 0:9b334a45a8ff | 463 | #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) |
| bogdanm | 0:9b334a45a8ff | 464 | /** |
| bogdanm | 0:9b334a45a8ff | 465 | * @} |
| bogdanm | 0:9b334a45a8ff | 466 | */ |
| bogdanm | 0:9b334a45a8ff | 467 | |
| bogdanm | 0:9b334a45a8ff | 468 | /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing |
| bogdanm | 0:9b334a45a8ff | 469 | * @{ |
| bogdanm | 0:9b334a45a8ff | 470 | */ |
| bogdanm | 0:9b334a45a8ff | 471 | #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 472 | #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN) |
| bogdanm | 0:9b334a45a8ff | 473 | /** |
| bogdanm | 0:9b334a45a8ff | 474 | * @} |
| bogdanm | 0:9b334a45a8ff | 475 | */ |
| bogdanm | 0:9b334a45a8ff | 476 | |
| bogdanm | 0:9b334a45a8ff | 477 | /** @defgroup FMC_Memory_Type FMC Memory Type |
| bogdanm | 0:9b334a45a8ff | 478 | * @{ |
| bogdanm | 0:9b334a45a8ff | 479 | */ |
| bogdanm | 0:9b334a45a8ff | 480 | #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 481 | #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0) |
| bogdanm | 0:9b334a45a8ff | 482 | #define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1) |
| bogdanm | 0:9b334a45a8ff | 483 | /** |
| bogdanm | 0:9b334a45a8ff | 484 | * @} |
| bogdanm | 0:9b334a45a8ff | 485 | */ |
| bogdanm | 0:9b334a45a8ff | 486 | |
| bogdanm | 0:9b334a45a8ff | 487 | /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width |
| bogdanm | 0:9b334a45a8ff | 488 | * @{ |
| bogdanm | 0:9b334a45a8ff | 489 | */ |
| bogdanm | 0:9b334a45a8ff | 490 | #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 491 | #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0) |
| bogdanm | 0:9b334a45a8ff | 492 | #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1) |
| bogdanm | 0:9b334a45a8ff | 493 | /** |
| bogdanm | 0:9b334a45a8ff | 494 | * @} |
| bogdanm | 0:9b334a45a8ff | 495 | */ |
| bogdanm | 0:9b334a45a8ff | 496 | |
| bogdanm | 0:9b334a45a8ff | 497 | /** @defgroup FMC_NORSRAM_Flash_Access FMC NORSRAM Flash Access |
| bogdanm | 0:9b334a45a8ff | 498 | * @{ |
| bogdanm | 0:9b334a45a8ff | 499 | */ |
| bogdanm | 0:9b334a45a8ff | 500 | #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN) |
| bogdanm | 0:9b334a45a8ff | 501 | #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 502 | /** |
| bogdanm | 0:9b334a45a8ff | 503 | * @} |
| bogdanm | 0:9b334a45a8ff | 504 | */ |
| bogdanm | 0:9b334a45a8ff | 505 | |
| bogdanm | 0:9b334a45a8ff | 506 | /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode |
| bogdanm | 0:9b334a45a8ff | 507 | * @{ |
| bogdanm | 0:9b334a45a8ff | 508 | */ |
| bogdanm | 0:9b334a45a8ff | 509 | #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 510 | #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN) |
| bogdanm | 0:9b334a45a8ff | 511 | /** |
| bogdanm | 0:9b334a45a8ff | 512 | * @} |
| bogdanm | 0:9b334a45a8ff | 513 | */ |
| bogdanm | 0:9b334a45a8ff | 514 | |
| bogdanm | 0:9b334a45a8ff | 515 | |
| bogdanm | 0:9b334a45a8ff | 516 | /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity |
| bogdanm | 0:9b334a45a8ff | 517 | * @{ |
| bogdanm | 0:9b334a45a8ff | 518 | */ |
| bogdanm | 0:9b334a45a8ff | 519 | #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 520 | #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL) |
| bogdanm | 0:9b334a45a8ff | 521 | /** |
| bogdanm | 0:9b334a45a8ff | 522 | * @} |
| bogdanm | 0:9b334a45a8ff | 523 | */ |
| bogdanm | 0:9b334a45a8ff | 524 | |
| bogdanm | 0:9b334a45a8ff | 525 | /** @defgroup FMC_Wait_Timing FMC Wait Timing |
| bogdanm | 0:9b334a45a8ff | 526 | * @{ |
| bogdanm | 0:9b334a45a8ff | 527 | */ |
| bogdanm | 0:9b334a45a8ff | 528 | #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 529 | #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG) |
| bogdanm | 0:9b334a45a8ff | 530 | |
| bogdanm | 0:9b334a45a8ff | 531 | /** |
| bogdanm | 0:9b334a45a8ff | 532 | * @} |
| bogdanm | 0:9b334a45a8ff | 533 | */ |
| bogdanm | 0:9b334a45a8ff | 534 | |
| bogdanm | 0:9b334a45a8ff | 535 | /** @defgroup FMC_Write_Operation FMC Write Operation |
| bogdanm | 0:9b334a45a8ff | 536 | * @{ |
| bogdanm | 0:9b334a45a8ff | 537 | */ |
| bogdanm | 0:9b334a45a8ff | 538 | #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 539 | #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN) |
| bogdanm | 0:9b334a45a8ff | 540 | /** |
| bogdanm | 0:9b334a45a8ff | 541 | * @} |
| bogdanm | 0:9b334a45a8ff | 542 | */ |
| bogdanm | 0:9b334a45a8ff | 543 | |
| bogdanm | 0:9b334a45a8ff | 544 | /** @defgroup FMC_Wait_Signal FMC Wait Signal |
| bogdanm | 0:9b334a45a8ff | 545 | * @{ |
| bogdanm | 0:9b334a45a8ff | 546 | */ |
| bogdanm | 0:9b334a45a8ff | 547 | #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 548 | #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN) |
| bogdanm | 0:9b334a45a8ff | 549 | /** |
| bogdanm | 0:9b334a45a8ff | 550 | * @} |
| bogdanm | 0:9b334a45a8ff | 551 | */ |
| bogdanm | 0:9b334a45a8ff | 552 | |
| bogdanm | 0:9b334a45a8ff | 553 | /** @defgroup FMC_Extended_Mode FMC Extended Mode |
| bogdanm | 0:9b334a45a8ff | 554 | * @{ |
| bogdanm | 0:9b334a45a8ff | 555 | */ |
| bogdanm | 0:9b334a45a8ff | 556 | #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 557 | #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD) |
| bogdanm | 0:9b334a45a8ff | 558 | /** |
| bogdanm | 0:9b334a45a8ff | 559 | * @} |
| bogdanm | 0:9b334a45a8ff | 560 | */ |
| bogdanm | 0:9b334a45a8ff | 561 | |
| bogdanm | 0:9b334a45a8ff | 562 | /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait |
| bogdanm | 0:9b334a45a8ff | 563 | * @{ |
| bogdanm | 0:9b334a45a8ff | 564 | */ |
| bogdanm | 0:9b334a45a8ff | 565 | #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 566 | #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT) |
| bogdanm | 0:9b334a45a8ff | 567 | /** |
| bogdanm | 0:9b334a45a8ff | 568 | * @} |
| bogdanm | 0:9b334a45a8ff | 569 | */ |
| bogdanm | 0:9b334a45a8ff | 570 | |
| bogdanm | 0:9b334a45a8ff | 571 | /** @defgroup FMC_Page_Size FMC Page Size |
| bogdanm | 0:9b334a45a8ff | 572 | * @{ |
| bogdanm | 0:9b334a45a8ff | 573 | */ |
| bogdanm | 0:9b334a45a8ff | 574 | #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 575 | #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) |
| bogdanm | 0:9b334a45a8ff | 576 | #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) |
| bogdanm | 0:9b334a45a8ff | 577 | #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2) |
| bogdanm | 0:9b334a45a8ff | 578 | /** |
| bogdanm | 0:9b334a45a8ff | 579 | * @} |
| bogdanm | 0:9b334a45a8ff | 580 | */ |
| bogdanm | 0:9b334a45a8ff | 581 | |
| bogdanm | 0:9b334a45a8ff | 582 | /** @defgroup FMC_Write_Burst FMC Write Burst |
| bogdanm | 0:9b334a45a8ff | 583 | * @{ |
| bogdanm | 0:9b334a45a8ff | 584 | */ |
| bogdanm | 0:9b334a45a8ff | 585 | #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 586 | #define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW) |
| bogdanm | 0:9b334a45a8ff | 587 | /** |
| bogdanm | 0:9b334a45a8ff | 588 | * @} |
| bogdanm | 0:9b334a45a8ff | 589 | */ |
| bogdanm | 0:9b334a45a8ff | 590 | |
| bogdanm | 0:9b334a45a8ff | 591 | /** @defgroup FMC_Continous_Clock FMC Continous Clock |
| bogdanm | 0:9b334a45a8ff | 592 | * @{ |
| bogdanm | 0:9b334a45a8ff | 593 | */ |
| bogdanm | 0:9b334a45a8ff | 594 | #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 595 | #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN) |
| bogdanm | 0:9b334a45a8ff | 596 | /** |
| bogdanm | 0:9b334a45a8ff | 597 | * @} |
| bogdanm | 0:9b334a45a8ff | 598 | */ |
| bogdanm | 0:9b334a45a8ff | 599 | |
| bogdanm | 0:9b334a45a8ff | 600 | /** @defgroup FMC_Write_FIFO FMC Write FIFO |
| bogdanm | 0:9b334a45a8ff | 601 | * @{ |
| bogdanm | 0:9b334a45a8ff | 602 | */ |
| bogdanm | 0:9b334a45a8ff | 603 | #define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 604 | #define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS) |
| bogdanm | 0:9b334a45a8ff | 605 | /** |
| bogdanm | 0:9b334a45a8ff | 606 | * @} |
| bogdanm | 0:9b334a45a8ff | 607 | */ |
| bogdanm | 0:9b334a45a8ff | 608 | |
| bogdanm | 0:9b334a45a8ff | 609 | /** @defgroup FMC_Access_Mode FMC Access Mode |
| bogdanm | 0:9b334a45a8ff | 610 | * @{ |
| bogdanm | 0:9b334a45a8ff | 611 | */ |
| bogdanm | 0:9b334a45a8ff | 612 | #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 613 | #define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0) |
| bogdanm | 0:9b334a45a8ff | 614 | #define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1) |
| bogdanm | 0:9b334a45a8ff | 615 | #define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0|FMC_BTRx_ACCMOD_1)) |
| bogdanm | 0:9b334a45a8ff | 616 | /** |
| bogdanm | 0:9b334a45a8ff | 617 | * @} |
| bogdanm | 0:9b334a45a8ff | 618 | */ |
| bogdanm | 0:9b334a45a8ff | 619 | |
| bogdanm | 0:9b334a45a8ff | 620 | /** |
| bogdanm | 0:9b334a45a8ff | 621 | * @} |
| bogdanm | 0:9b334a45a8ff | 622 | */ |
| bogdanm | 0:9b334a45a8ff | 623 | |
| bogdanm | 0:9b334a45a8ff | 624 | /** |
| bogdanm | 0:9b334a45a8ff | 625 | * @} |
| bogdanm | 0:9b334a45a8ff | 626 | */ |
| bogdanm | 0:9b334a45a8ff | 627 | |
| bogdanm | 0:9b334a45a8ff | 628 | /** @defgroup FMC_NAND_Controller FMC NAND Exported constants |
| bogdanm | 0:9b334a45a8ff | 629 | * @{ |
| bogdanm | 0:9b334a45a8ff | 630 | */ |
| bogdanm | 0:9b334a45a8ff | 631 | |
| bogdanm | 0:9b334a45a8ff | 632 | /** @defgroup FMC_NAND_Bank FMC NAND Bank |
| bogdanm | 0:9b334a45a8ff | 633 | * @{ |
| bogdanm | 0:9b334a45a8ff | 634 | */ |
| bogdanm | 0:9b334a45a8ff | 635 | #define FMC_NAND_BANK3 ((uint32_t)0x00000100) |
| bogdanm | 0:9b334a45a8ff | 636 | /** |
| bogdanm | 0:9b334a45a8ff | 637 | * @} |
| bogdanm | 0:9b334a45a8ff | 638 | */ |
| bogdanm | 0:9b334a45a8ff | 639 | |
| bogdanm | 0:9b334a45a8ff | 640 | /** @defgroup FMC_Wait_feature FMC Wait feature |
| bogdanm | 0:9b334a45a8ff | 641 | * @{ |
| bogdanm | 0:9b334a45a8ff | 642 | */ |
| bogdanm | 0:9b334a45a8ff | 643 | #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 644 | #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCR_PWAITEN) |
| bogdanm | 0:9b334a45a8ff | 645 | /** |
| bogdanm | 0:9b334a45a8ff | 646 | * @} |
| bogdanm | 0:9b334a45a8ff | 647 | */ |
| bogdanm | 0:9b334a45a8ff | 648 | |
| bogdanm | 0:9b334a45a8ff | 649 | /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type |
| bogdanm | 0:9b334a45a8ff | 650 | * @{ |
| bogdanm | 0:9b334a45a8ff | 651 | */ |
| bogdanm | 0:9b334a45a8ff | 652 | #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCR_PTYP) |
| bogdanm | 0:9b334a45a8ff | 653 | /** |
| bogdanm | 0:9b334a45a8ff | 654 | * @} |
| bogdanm | 0:9b334a45a8ff | 655 | */ |
| bogdanm | 0:9b334a45a8ff | 656 | |
| bogdanm | 0:9b334a45a8ff | 657 | /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width |
| bogdanm | 0:9b334a45a8ff | 658 | * @{ |
| bogdanm | 0:9b334a45a8ff | 659 | */ |
| bogdanm | 0:9b334a45a8ff | 660 | #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 661 | #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCR_PWID_0) |
| bogdanm | 0:9b334a45a8ff | 662 | /** |
| bogdanm | 0:9b334a45a8ff | 663 | * @} |
| bogdanm | 0:9b334a45a8ff | 664 | */ |
| bogdanm | 0:9b334a45a8ff | 665 | |
| bogdanm | 0:9b334a45a8ff | 666 | /** @defgroup FMC_ECC FMC NAND ECC |
| bogdanm | 0:9b334a45a8ff | 667 | * @{ |
| bogdanm | 0:9b334a45a8ff | 668 | */ |
| bogdanm | 0:9b334a45a8ff | 669 | #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 670 | #define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCR_ECCEN) |
| bogdanm | 0:9b334a45a8ff | 671 | /** |
| bogdanm | 0:9b334a45a8ff | 672 | * @} |
| bogdanm | 0:9b334a45a8ff | 673 | */ |
| bogdanm | 0:9b334a45a8ff | 674 | |
| bogdanm | 0:9b334a45a8ff | 675 | /** @defgroup FMC_ECC_Page_Size FMC NAND ECC Page Size |
| bogdanm | 0:9b334a45a8ff | 676 | * @{ |
| bogdanm | 0:9b334a45a8ff | 677 | */ |
| bogdanm | 0:9b334a45a8ff | 678 | #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 679 | #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCR_ECCPS_0) |
| bogdanm | 0:9b334a45a8ff | 680 | #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCR_ECCPS_1) |
| bogdanm | 0:9b334a45a8ff | 681 | #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1) |
| bogdanm | 0:9b334a45a8ff | 682 | #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCR_ECCPS_2) |
| bogdanm | 0:9b334a45a8ff | 683 | #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2) |
| bogdanm | 0:9b334a45a8ff | 684 | /** |
| bogdanm | 0:9b334a45a8ff | 685 | * @} |
| bogdanm | 0:9b334a45a8ff | 686 | */ |
| bogdanm | 0:9b334a45a8ff | 687 | |
| bogdanm | 0:9b334a45a8ff | 688 | /** |
| bogdanm | 0:9b334a45a8ff | 689 | * @} |
| bogdanm | 0:9b334a45a8ff | 690 | */ |
| bogdanm | 0:9b334a45a8ff | 691 | |
| bogdanm | 0:9b334a45a8ff | 692 | /** |
| bogdanm | 0:9b334a45a8ff | 693 | * @} |
| bogdanm | 0:9b334a45a8ff | 694 | */ |
| bogdanm | 0:9b334a45a8ff | 695 | |
| bogdanm | 0:9b334a45a8ff | 696 | /** @defgroup FMC_Interrupt_definition FMC Interrupt definition |
| bogdanm | 0:9b334a45a8ff | 697 | * @brief FMC Interrupt definition |
| bogdanm | 0:9b334a45a8ff | 698 | * @{ |
| bogdanm | 0:9b334a45a8ff | 699 | */ |
| bogdanm | 0:9b334a45a8ff | 700 | #define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) |
| bogdanm | 0:9b334a45a8ff | 701 | #define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) |
| bogdanm | 0:9b334a45a8ff | 702 | #define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) |
| bogdanm | 0:9b334a45a8ff | 703 | /** |
| bogdanm | 0:9b334a45a8ff | 704 | * @} |
| bogdanm | 0:9b334a45a8ff | 705 | */ |
| bogdanm | 0:9b334a45a8ff | 706 | |
| bogdanm | 0:9b334a45a8ff | 707 | /** @defgroup FMC_Flag_definition FMC Flag definition |
| bogdanm | 0:9b334a45a8ff | 708 | * @brief FMC Flag definition |
| bogdanm | 0:9b334a45a8ff | 709 | * @{ |
| bogdanm | 0:9b334a45a8ff | 710 | */ |
| bogdanm | 0:9b334a45a8ff | 711 | #define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SR_IRS) |
| bogdanm | 0:9b334a45a8ff | 712 | #define FMC_FLAG_LEVEL ((uint32_t)FMC_SR_ILS) |
| bogdanm | 0:9b334a45a8ff | 713 | #define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SR_IFS) |
| bogdanm | 0:9b334a45a8ff | 714 | #define FMC_FLAG_FEMPT ((uint32_t)FMC_SR_FEMPT) |
| bogdanm | 0:9b334a45a8ff | 715 | /** |
| bogdanm | 0:9b334a45a8ff | 716 | * @} |
| bogdanm | 0:9b334a45a8ff | 717 | */ |
| bogdanm | 0:9b334a45a8ff | 718 | |
| bogdanm | 0:9b334a45a8ff | 719 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 720 | |
| bogdanm | 0:9b334a45a8ff | 721 | /** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros |
| bogdanm | 0:9b334a45a8ff | 722 | * @{ |
| bogdanm | 0:9b334a45a8ff | 723 | */ |
| bogdanm | 0:9b334a45a8ff | 724 | |
| bogdanm | 0:9b334a45a8ff | 725 | /** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros |
| bogdanm | 0:9b334a45a8ff | 726 | * @brief macros to handle NOR device enable/disable and read/write operations |
| bogdanm | 0:9b334a45a8ff | 727 | * @{ |
| bogdanm | 0:9b334a45a8ff | 728 | */ |
| bogdanm | 0:9b334a45a8ff | 729 | |
| bogdanm | 0:9b334a45a8ff | 730 | /** |
| bogdanm | 0:9b334a45a8ff | 731 | * @brief Enable the NORSRAM device access. |
| bogdanm | 0:9b334a45a8ff | 732 | * @param __INSTANCE__: FMC_NORSRAM Instance |
| bogdanm | 0:9b334a45a8ff | 733 | * @param __BANK__: FMC_NORSRAM Bank |
| bogdanm | 0:9b334a45a8ff | 734 | * @retval none |
| bogdanm | 0:9b334a45a8ff | 735 | */ |
| bogdanm | 0:9b334a45a8ff | 736 | #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) |
| bogdanm | 0:9b334a45a8ff | 737 | |
| bogdanm | 0:9b334a45a8ff | 738 | /** |
| bogdanm | 0:9b334a45a8ff | 739 | * @brief Disable the NORSRAM device access. |
| bogdanm | 0:9b334a45a8ff | 740 | * @param __INSTANCE__: FMC_NORSRAM Instance |
| bogdanm | 0:9b334a45a8ff | 741 | * @param __BANK__: FMC_NORSRAM Bank |
| bogdanm | 0:9b334a45a8ff | 742 | * @retval none |
| bogdanm | 0:9b334a45a8ff | 743 | */ |
| bogdanm | 0:9b334a45a8ff | 744 | #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) |
| bogdanm | 0:9b334a45a8ff | 745 | |
| bogdanm | 0:9b334a45a8ff | 746 | /** |
| bogdanm | 0:9b334a45a8ff | 747 | * @} |
| bogdanm | 0:9b334a45a8ff | 748 | */ |
| bogdanm | 0:9b334a45a8ff | 749 | |
| bogdanm | 0:9b334a45a8ff | 750 | /** @defgroup FMC_NAND_Macros FMC NAND Macros |
| bogdanm | 0:9b334a45a8ff | 751 | * @brief macros to handle NAND device enable/disable |
| bogdanm | 0:9b334a45a8ff | 752 | * @{ |
| bogdanm | 0:9b334a45a8ff | 753 | */ |
| bogdanm | 0:9b334a45a8ff | 754 | |
| bogdanm | 0:9b334a45a8ff | 755 | /** |
| bogdanm | 0:9b334a45a8ff | 756 | * @brief Enable the NAND device access. |
| bogdanm | 0:9b334a45a8ff | 757 | * @param __INSTANCE__: FMC_NAND Instance |
| bogdanm | 0:9b334a45a8ff | 758 | * @param __BANK__: FMC_NAND Bank |
| bogdanm | 0:9b334a45a8ff | 759 | * @retval none |
| bogdanm | 0:9b334a45a8ff | 760 | */ |
| bogdanm | 0:9b334a45a8ff | 761 | #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) |
| bogdanm | 0:9b334a45a8ff | 762 | |
| bogdanm | 0:9b334a45a8ff | 763 | /** |
| bogdanm | 0:9b334a45a8ff | 764 | * @brief Disable the NAND device access. |
| bogdanm | 0:9b334a45a8ff | 765 | * @param __INSTANCE__: FMC_NAND Instance |
| bogdanm | 0:9b334a45a8ff | 766 | * @param __BANK__: FMC_NAND Bank |
| bogdanm | 0:9b334a45a8ff | 767 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 768 | */ |
| bogdanm | 0:9b334a45a8ff | 769 | #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) |
| bogdanm | 0:9b334a45a8ff | 770 | |
| bogdanm | 0:9b334a45a8ff | 771 | /** |
| bogdanm | 0:9b334a45a8ff | 772 | * @} |
| bogdanm | 0:9b334a45a8ff | 773 | */ |
| bogdanm | 0:9b334a45a8ff | 774 | |
| bogdanm | 0:9b334a45a8ff | 775 | /** @defgroup FMC_Interrupt FMC Interrupt |
| bogdanm | 0:9b334a45a8ff | 776 | * @brief macros to handle FMC interrupts |
| bogdanm | 0:9b334a45a8ff | 777 | * @{ |
| bogdanm | 0:9b334a45a8ff | 778 | */ |
| bogdanm | 0:9b334a45a8ff | 779 | |
| bogdanm | 0:9b334a45a8ff | 780 | /** |
| bogdanm | 0:9b334a45a8ff | 781 | * @brief Enable the NAND device interrupt. |
| bogdanm | 0:9b334a45a8ff | 782 | * @param __INSTANCE__: FMC_NAND Instance |
| bogdanm | 0:9b334a45a8ff | 783 | * @param __BANK__: FMC_NAND Bank |
| bogdanm | 0:9b334a45a8ff | 784 | * @param __INTERRUPT__: FMC_NAND interrupt |
| bogdanm | 0:9b334a45a8ff | 785 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 786 | * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. |
| bogdanm | 0:9b334a45a8ff | 787 | * @arg FMC_IT_LEVEL: Interrupt level. |
| bogdanm | 0:9b334a45a8ff | 788 | * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. |
| bogdanm | 0:9b334a45a8ff | 789 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 790 | */ |
| bogdanm | 0:9b334a45a8ff | 791 | #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 792 | |
| bogdanm | 0:9b334a45a8ff | 793 | /** |
| bogdanm | 0:9b334a45a8ff | 794 | * @brief Disable the NAND device interrupt. |
| bogdanm | 0:9b334a45a8ff | 795 | * @param __INSTANCE__: FMC_NAND Instance |
| bogdanm | 0:9b334a45a8ff | 796 | * @param __BANK__: FMC_NAND Bank |
| bogdanm | 0:9b334a45a8ff | 797 | * @param __INTERRUPT__: FMC_NAND interrupt |
| bogdanm | 0:9b334a45a8ff | 798 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 799 | * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. |
| bogdanm | 0:9b334a45a8ff | 800 | * @arg FMC_IT_LEVEL: Interrupt level. |
| bogdanm | 0:9b334a45a8ff | 801 | * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. |
| bogdanm | 0:9b334a45a8ff | 802 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 803 | */ |
| bogdanm | 0:9b334a45a8ff | 804 | #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 805 | |
| bogdanm | 0:9b334a45a8ff | 806 | /** |
| bogdanm | 0:9b334a45a8ff | 807 | * @brief Get flag status of the NAND device. |
| bogdanm | 0:9b334a45a8ff | 808 | * @param __INSTANCE__: FMC_NAND Instance |
| bogdanm | 0:9b334a45a8ff | 809 | * @param __BANK__: FMC_NAND Bank |
| bogdanm | 0:9b334a45a8ff | 810 | * @param __FLAG__: FMC_NAND flag |
| bogdanm | 0:9b334a45a8ff | 811 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 812 | * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| bogdanm | 0:9b334a45a8ff | 813 | * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. |
| bogdanm | 0:9b334a45a8ff | 814 | * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| bogdanm | 0:9b334a45a8ff | 815 | * @arg FMC_FLAG_FEMPT: FIFO empty flag. |
| bogdanm | 0:9b334a45a8ff | 816 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 0:9b334a45a8ff | 817 | */ |
| bogdanm | 0:9b334a45a8ff | 818 | #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 819 | |
| bogdanm | 0:9b334a45a8ff | 820 | /** |
| bogdanm | 0:9b334a45a8ff | 821 | * @brief Clear flag status of the NAND device. |
| bogdanm | 0:9b334a45a8ff | 822 | * @param __INSTANCE__: FMC_NAND Instance |
| bogdanm | 0:9b334a45a8ff | 823 | * @param __BANK__: FMC_NAND Bank |
| bogdanm | 0:9b334a45a8ff | 824 | * @param __FLAG__: FMC_NAND flag |
| bogdanm | 0:9b334a45a8ff | 825 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 826 | * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| bogdanm | 0:9b334a45a8ff | 827 | * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. |
| bogdanm | 0:9b334a45a8ff | 828 | * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| bogdanm | 0:9b334a45a8ff | 829 | * @arg FMC_FLAG_FEMPT: FIFO empty flag. |
| bogdanm | 0:9b334a45a8ff | 830 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 831 | */ |
| bogdanm | 0:9b334a45a8ff | 832 | #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR, (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 833 | |
| bogdanm | 0:9b334a45a8ff | 834 | |
| bogdanm | 0:9b334a45a8ff | 835 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 836 | /** @addgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions |
| bogdanm | 0:9b334a45a8ff | 837 | * @{ |
| bogdanm | 0:9b334a45a8ff | 838 | */ |
| bogdanm | 0:9b334a45a8ff | 839 | |
| bogdanm | 0:9b334a45a8ff | 840 | /* FMC_LL_NORSRAM Controller functions *******************************************/ |
| bogdanm | 0:9b334a45a8ff | 841 | /** @addgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions |
| bogdanm | 0:9b334a45a8ff | 842 | * @{ |
| bogdanm | 0:9b334a45a8ff | 843 | */ |
| bogdanm | 0:9b334a45a8ff | 844 | /* Initialization/de-initialization functions */ |
| bogdanm | 0:9b334a45a8ff | 845 | HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); |
| bogdanm | 0:9b334a45a8ff | 846 | HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 847 | HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
| bogdanm | 0:9b334a45a8ff | 848 | HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 849 | /** |
| bogdanm | 0:9b334a45a8ff | 850 | * @} |
| bogdanm | 0:9b334a45a8ff | 851 | */ |
| bogdanm | 0:9b334a45a8ff | 852 | |
| bogdanm | 0:9b334a45a8ff | 853 | /** @addtogroup FMC_LL_NORSRAM_Exported_Functions_Group2 Peripheral Control functions |
| bogdanm | 0:9b334a45a8ff | 854 | * @{ |
| bogdanm | 0:9b334a45a8ff | 855 | */ |
| bogdanm | 0:9b334a45a8ff | 856 | /* FMC_NORSRAM Control functions */ |
| bogdanm | 0:9b334a45a8ff | 857 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 858 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 859 | /** |
| bogdanm | 0:9b334a45a8ff | 860 | * @} |
| bogdanm | 0:9b334a45a8ff | 861 | */ |
| bogdanm | 0:9b334a45a8ff | 862 | |
| bogdanm | 0:9b334a45a8ff | 863 | /* FMC_NAND Controller functions **********************************************/ |
| bogdanm | 0:9b334a45a8ff | 864 | /** @addtogroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
| bogdanm | 0:9b334a45a8ff | 865 | * @{ |
| bogdanm | 0:9b334a45a8ff | 866 | */ |
| bogdanm | 0:9b334a45a8ff | 867 | /* Initialization/de-initialization functions */ |
| bogdanm | 0:9b334a45a8ff | 868 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); |
| bogdanm | 0:9b334a45a8ff | 869 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 870 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 871 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 872 | /** |
| bogdanm | 0:9b334a45a8ff | 873 | * @} |
| bogdanm | 0:9b334a45a8ff | 874 | */ |
| bogdanm | 0:9b334a45a8ff | 875 | |
| bogdanm | 0:9b334a45a8ff | 876 | /** @defgroup FMC_LL_NAND_Exported_Functions_Group2 FMC Low Layer Peripheral Control functions |
| bogdanm | 0:9b334a45a8ff | 877 | * @{ |
| bogdanm | 0:9b334a45a8ff | 878 | */ |
| bogdanm | 0:9b334a45a8ff | 879 | /* FMC_NAND Control functions */ |
| bogdanm | 0:9b334a45a8ff | 880 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 881 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 882 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 883 | /** |
| bogdanm | 0:9b334a45a8ff | 884 | * @} |
| bogdanm | 0:9b334a45a8ff | 885 | */ |
| bogdanm | 0:9b334a45a8ff | 886 | |
| bogdanm | 0:9b334a45a8ff | 887 | /** |
| bogdanm | 0:9b334a45a8ff | 888 | * @} |
| bogdanm | 0:9b334a45a8ff | 889 | */ |
| bogdanm | 0:9b334a45a8ff | 890 | |
| bogdanm | 0:9b334a45a8ff | 891 | /** |
| bogdanm | 0:9b334a45a8ff | 892 | * @} |
| bogdanm | 0:9b334a45a8ff | 893 | */ |
| bogdanm | 0:9b334a45a8ff | 894 | |
| bogdanm | 0:9b334a45a8ff | 895 | /** |
| bogdanm | 0:9b334a45a8ff | 896 | * @} |
| bogdanm | 0:9b334a45a8ff | 897 | */ |
| bogdanm | 0:9b334a45a8ff | 898 | |
| bogdanm | 0:9b334a45a8ff | 899 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 900 | } |
| bogdanm | 0:9b334a45a8ff | 901 | #endif |
| bogdanm | 0:9b334a45a8ff | 902 | |
| bogdanm | 0:9b334a45a8ff | 903 | #endif /* __STM32L4xx_LL_FMC_H */ |
| bogdanm | 0:9b334a45a8ff | 904 | |
| bogdanm | 0:9b334a45a8ff | 905 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |