en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_tim_ex.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l4xx_hal_tim_ex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief TIM HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Timer Extended peripheral:
bogdanm 0:9b334a45a8ff 10 * + Time Hall Sensor Interface Initialization
bogdanm 0:9b334a45a8ff 11 * + Time Hall Sensor Interface Start
bogdanm 0:9b334a45a8ff 12 * + Time Complementary signal break and dead time configuration
bogdanm 0:9b334a45a8ff 13 * + Time Master and Slave synchronization configuration
bogdanm 0:9b334a45a8ff 14 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
bogdanm 0:9b334a45a8ff 15 * + Time OCRef clear configuration
bogdanm 0:9b334a45a8ff 16 * + Timer remapping capabilities configuration
bogdanm 0:9b334a45a8ff 17 @verbatim
bogdanm 0:9b334a45a8ff 18 ==============================================================================
bogdanm 0:9b334a45a8ff 19 ##### TIMER Extended features #####
bogdanm 0:9b334a45a8ff 20 ==============================================================================
bogdanm 0:9b334a45a8ff 21 [..]
bogdanm 0:9b334a45a8ff 22 The Timer Extended features include:
bogdanm 0:9b334a45a8ff 23 (#) Complementary outputs with programmable dead-time for :
bogdanm 0:9b334a45a8ff 24 (++) Output Compare
bogdanm 0:9b334a45a8ff 25 (++) PWM generation (Edge and Center-aligned Mode)
bogdanm 0:9b334a45a8ff 26 (++) One-pulse mode output
bogdanm 0:9b334a45a8ff 27 (#) Synchronization circuit to control the timer with external signals and to
bogdanm 0:9b334a45a8ff 28 interconnect several timers together.
bogdanm 0:9b334a45a8ff 29 (#) Break input to put the timer output signals in reset state or in a known state.
bogdanm 0:9b334a45a8ff 30 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
bogdanm 0:9b334a45a8ff 31 positioning purposes
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 34 ==============================================================================
bogdanm 0:9b334a45a8ff 35 [..]
bogdanm 0:9b334a45a8ff 36 (#) Initialize the TIM low level resources by implementing the following functions
bogdanm 0:9b334a45a8ff 37 depending on the selected feature:
bogdanm 0:9b334a45a8ff 38 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 (#) Initialize the TIM low level resources :
bogdanm 0:9b334a45a8ff 41 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 42 (##) TIM pins configuration
bogdanm 0:9b334a45a8ff 43 (+++) Enable the clock for the TIM GPIOs using the following function:
bogdanm 0:9b334a45a8ff 44 __HAL_RCC_GPIOx_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 45 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 (#) The external Clock can be configured, if needed (the default clock is the
bogdanm 0:9b334a45a8ff 48 internal clock from the APBx), using the following function:
bogdanm 0:9b334a45a8ff 49 HAL_TIM_ConfigClockSource, the clock configuration should be done before
bogdanm 0:9b334a45a8ff 50 any start function.
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 (#) Configure the TIM in the desired functioning mode using one of the
bogdanm 0:9b334a45a8ff 53 initialization function of this driver:
bogdanm 0:9b334a45a8ff 54 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the
bogdanm 0:9b334a45a8ff 55 Timer Hall Sensor Interface and the commutation event with the corresponding
bogdanm 0:9b334a45a8ff 56 Interrupt and DMA request if needed (Note that One Timer is used to interface
bogdanm 0:9b334a45a8ff 57 with the Hall sensor Interface and another Timer should be used to use
bogdanm 0:9b334a45a8ff 58 the commutation event).
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 (#) Activate the TIM peripheral using one of the start functions:
bogdanm 0:9b334a45a8ff 61 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
bogdanm 0:9b334a45a8ff 62 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
bogdanm 0:9b334a45a8ff 63 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
bogdanm 0:9b334a45a8ff 64 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
bogdanm 0:9b334a45a8ff 65
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 @endverbatim
bogdanm 0:9b334a45a8ff 68 ******************************************************************************
bogdanm 0:9b334a45a8ff 69 * @attention
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 72 *
bogdanm 0:9b334a45a8ff 73 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 74 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 75 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 76 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 78 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 79 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 81 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 82 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 83 *
bogdanm 0:9b334a45a8ff 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 94 *
bogdanm 0:9b334a45a8ff 95 ******************************************************************************
bogdanm 0:9b334a45a8ff 96 */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 99 #include "stm32l4xx_hal.h"
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /** @addtogroup STM32L4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 102 * @{
bogdanm 0:9b334a45a8ff 103 */
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 /** @defgroup TIMEx TIMEx
bogdanm 0:9b334a45a8ff 106 * @brief TIM Extended HAL module driver
bogdanm 0:9b334a45a8ff 107 * @{
bogdanm 0:9b334a45a8ff 108 */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 #ifdef HAL_TIM_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 111
bogdanm 0:9b334a45a8ff 112 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 113 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 114 #define BDTR_BKF_SHIFT (16)
bogdanm 0:9b334a45a8ff 115 #define BDTR_BK2F_SHIFT (20)
bogdanm 0:9b334a45a8ff 116 #define TIMx_ETRSEL_MASK ((uint32_t)0x0001C000)
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 119 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 120 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 121 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
bogdanm 0:9b334a45a8ff 122 TIM_OC_InitTypeDef *OC_Config);
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
bogdanm 0:9b334a45a8ff 125 TIM_OC_InitTypeDef *OC_Config);
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 130 /**
bogdanm 0:9b334a45a8ff 131 * @brief Timer Ouput Compare 5 configuration
bogdanm 0:9b334a45a8ff 132 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 133 * @param OC_Config: The ouput configuration structure
bogdanm 0:9b334a45a8ff 134 * @retval None
bogdanm 0:9b334a45a8ff 135 */
bogdanm 0:9b334a45a8ff 136 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
bogdanm 0:9b334a45a8ff 137 TIM_OC_InitTypeDef *OC_Config)
bogdanm 0:9b334a45a8ff 138 {
bogdanm 0:9b334a45a8ff 139 uint32_t tmpccmrx = 0;
bogdanm 0:9b334a45a8ff 140 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 141 uint32_t tmpcr2 = 0;
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /* Disable the output: Reset the CCxE Bit */
bogdanm 0:9b334a45a8ff 144 TIMx->CCER &= ~TIM_CCER_CC5E;
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /* Get the TIMx CCER register value */
bogdanm 0:9b334a45a8ff 147 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 148 /* Get the TIMx CR2 register value */
bogdanm 0:9b334a45a8ff 149 tmpcr2 = TIMx->CR2;
bogdanm 0:9b334a45a8ff 150 /* Get the TIMx CCMR1 register value */
bogdanm 0:9b334a45a8ff 151 tmpccmrx = TIMx->CCMR3;
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 /* Reset the Output Compare Mode Bits */
bogdanm 0:9b334a45a8ff 154 tmpccmrx &= ~(TIM_CCMR3_OC5M);
bogdanm 0:9b334a45a8ff 155 /* Select the Output Compare Mode */
bogdanm 0:9b334a45a8ff 156 tmpccmrx |= OC_Config->OCMode;
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 /* Reset the Output Polarity level */
bogdanm 0:9b334a45a8ff 159 tmpccer &= ~TIM_CCER_CC5P;
bogdanm 0:9b334a45a8ff 160 /* Set the Output Compare Polarity */
bogdanm 0:9b334a45a8ff 161 tmpccer |= (OC_Config->OCPolarity << 16);
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm 0:9b334a45a8ff 164 {
bogdanm 0:9b334a45a8ff 165 /* Reset the Output Compare IDLE State */
bogdanm 0:9b334a45a8ff 166 tmpcr2 &= ~TIM_CR2_OIS5;
bogdanm 0:9b334a45a8ff 167 /* Set the Output Idle state */
bogdanm 0:9b334a45a8ff 168 tmpcr2 |= (OC_Config->OCIdleState << 8);
bogdanm 0:9b334a45a8ff 169 }
bogdanm 0:9b334a45a8ff 170 /* Write to TIMx CR2 */
bogdanm 0:9b334a45a8ff 171 TIMx->CR2 = tmpcr2;
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 /* Write to TIMx CCMR3 */
bogdanm 0:9b334a45a8ff 174 TIMx->CCMR3 = tmpccmrx;
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 /* Set the Capture Compare Register value */
bogdanm 0:9b334a45a8ff 177 TIMx->CCR5 = OC_Config->Pulse;
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 /* Write to TIMx CCER */
bogdanm 0:9b334a45a8ff 180 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 181 }
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /**
bogdanm 0:9b334a45a8ff 184 * @brief Timer Ouput Compare 6 configuration
bogdanm 0:9b334a45a8ff 185 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 186 * @param OC_Config: The ouput configuration structure
bogdanm 0:9b334a45a8ff 187 * @retval None
bogdanm 0:9b334a45a8ff 188 */
bogdanm 0:9b334a45a8ff 189 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
bogdanm 0:9b334a45a8ff 190 TIM_OC_InitTypeDef *OC_Config)
bogdanm 0:9b334a45a8ff 191 {
bogdanm 0:9b334a45a8ff 192 uint32_t tmpccmrx = 0;
bogdanm 0:9b334a45a8ff 193 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 194 uint32_t tmpcr2 = 0;
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 /* Disable the output: Reset the CCxE Bit */
bogdanm 0:9b334a45a8ff 197 TIMx->CCER &= ~TIM_CCER_CC6E;
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 /* Get the TIMx CCER register value */
bogdanm 0:9b334a45a8ff 200 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 201 /* Get the TIMx CR2 register value */
bogdanm 0:9b334a45a8ff 202 tmpcr2 = TIMx->CR2;
bogdanm 0:9b334a45a8ff 203 /* Get the TIMx CCMR1 register value */
bogdanm 0:9b334a45a8ff 204 tmpccmrx = TIMx->CCMR3;
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /* Reset the Output Compare Mode Bits */
bogdanm 0:9b334a45a8ff 207 tmpccmrx &= ~(TIM_CCMR3_OC6M);
bogdanm 0:9b334a45a8ff 208 /* Select the Output Compare Mode */
bogdanm 0:9b334a45a8ff 209 tmpccmrx |= (OC_Config->OCMode << 8);
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 /* Reset the Output Polarity level */
bogdanm 0:9b334a45a8ff 212 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
bogdanm 0:9b334a45a8ff 213 /* Set the Output Compare Polarity */
bogdanm 0:9b334a45a8ff 214 tmpccer |= (OC_Config->OCPolarity << 20);
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm 0:9b334a45a8ff 217 {
bogdanm 0:9b334a45a8ff 218 /* Reset the Output Compare IDLE State */
bogdanm 0:9b334a45a8ff 219 tmpcr2 &= ~TIM_CR2_OIS6;
bogdanm 0:9b334a45a8ff 220 /* Set the Output Idle state */
bogdanm 0:9b334a45a8ff 221 tmpcr2 |= (OC_Config->OCIdleState << 10);
bogdanm 0:9b334a45a8ff 222 }
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 /* Write to TIMx CR2 */
bogdanm 0:9b334a45a8ff 225 TIMx->CR2 = tmpcr2;
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /* Write to TIMx CCMR3 */
bogdanm 0:9b334a45a8ff 228 TIMx->CCMR3 = tmpccmrx;
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /* Set the Capture Compare Register value */
bogdanm 0:9b334a45a8ff 231 TIMx->CCR6 = OC_Config->Pulse;
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /* Write to TIMx CCER */
bogdanm 0:9b334a45a8ff 234 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 235 }
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 238 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
bogdanm 0:9b334a45a8ff 239 * @{
bogdanm 0:9b334a45a8ff 240 */
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
bogdanm 0:9b334a45a8ff 243 * @brief Timer Hall Sensor functions
bogdanm 0:9b334a45a8ff 244 *
bogdanm 0:9b334a45a8ff 245 @verbatim
bogdanm 0:9b334a45a8ff 246 ==============================================================================
bogdanm 0:9b334a45a8ff 247 ##### Timer Hall Sensor functions #####
bogdanm 0:9b334a45a8ff 248 ==============================================================================
bogdanm 0:9b334a45a8ff 249 [..]
bogdanm 0:9b334a45a8ff 250 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 251 (+) Initialize and configure TIM HAL Sensor.
bogdanm 0:9b334a45a8ff 252 (+) De-initialize TIM HAL Sensor.
bogdanm 0:9b334a45a8ff 253 (+) Start the Hall Sensor Interface.
bogdanm 0:9b334a45a8ff 254 (+) Stop the Hall Sensor Interface.
bogdanm 0:9b334a45a8ff 255 (+) Start the Hall Sensor Interface and enable interrupts.
bogdanm 0:9b334a45a8ff 256 (+) Stop the Hall Sensor Interface and disable interrupts.
bogdanm 0:9b334a45a8ff 257 (+) Start the Hall Sensor Interface and enable DMA transfers.
bogdanm 0:9b334a45a8ff 258 (+) Stop the Hall Sensor Interface and disable DMA transfers.
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 @endverbatim
bogdanm 0:9b334a45a8ff 261 * @{
bogdanm 0:9b334a45a8ff 262 */
bogdanm 0:9b334a45a8ff 263 /**
bogdanm 0:9b334a45a8ff 264 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
bogdanm 0:9b334a45a8ff 265 * @param htim: TIM Encoder Interface handle
bogdanm 0:9b334a45a8ff 266 * @param sConfig: TIM Hall Sensor configuration structure
bogdanm 0:9b334a45a8ff 267 * @retval HAL status
bogdanm 0:9b334a45a8ff 268 */
bogdanm 0:9b334a45a8ff 269 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
bogdanm 0:9b334a45a8ff 270 {
bogdanm 0:9b334a45a8ff 271 TIM_OC_InitTypeDef OC_Config;
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 /* Check the TIM handle allocation */
bogdanm 0:9b334a45a8ff 274 if(htim == NULL)
bogdanm 0:9b334a45a8ff 275 {
bogdanm 0:9b334a45a8ff 276 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 277 }
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 280 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm 0:9b334a45a8ff 281 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm 0:9b334a45a8ff 282 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
bogdanm 0:9b334a45a8ff 283 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
bogdanm 0:9b334a45a8ff 284 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 if(htim->State == HAL_TIM_STATE_RESET)
bogdanm 0:9b334a45a8ff 287 {
bogdanm 0:9b334a45a8ff 288 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 289 htim->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm 0:9b334a45a8ff 292 HAL_TIMEx_HallSensor_MspInit(htim);
bogdanm 0:9b334a45a8ff 293 }
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 /* Set the TIM state */
bogdanm 0:9b334a45a8ff 296 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 297
bogdanm 0:9b334a45a8ff 298 /* Configure the Time base in the Encoder Mode */
bogdanm 0:9b334a45a8ff 299 TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
bogdanm 0:9b334a45a8ff 302 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 /* Reset the IC1PSC Bits */
bogdanm 0:9b334a45a8ff 305 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm 0:9b334a45a8ff 306 /* Set the IC1PSC value */
bogdanm 0:9b334a45a8ff 307 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /* Enable the Hall sensor interface (XOR function of the three inputs) */
bogdanm 0:9b334a45a8ff 310 htim->Instance->CR2 |= TIM_CR2_TI1S;
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
bogdanm 0:9b334a45a8ff 313 htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm 0:9b334a45a8ff 314 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
bogdanm 0:9b334a45a8ff 317 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm 0:9b334a45a8ff 318 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
bogdanm 0:9b334a45a8ff 321 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
bogdanm 0:9b334a45a8ff 322 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
bogdanm 0:9b334a45a8ff 323 OC_Config.OCMode = TIM_OCMODE_PWM2;
bogdanm 0:9b334a45a8ff 324 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
bogdanm 0:9b334a45a8ff 325 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
bogdanm 0:9b334a45a8ff 326 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
bogdanm 0:9b334a45a8ff 327 OC_Config.Pulse = sConfig->Commutation_Delay;
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
bogdanm 0:9b334a45a8ff 332 register to 101 */
bogdanm 0:9b334a45a8ff 333 htim->Instance->CR2 &= ~TIM_CR2_MMS;
bogdanm 0:9b334a45a8ff 334 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336 /* Initialize the TIM state*/
bogdanm 0:9b334a45a8ff 337 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 return HAL_OK;
bogdanm 0:9b334a45a8ff 340 }
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 /**
bogdanm 0:9b334a45a8ff 343 * @brief DeInitialize the TIM Hall Sensor interface
bogdanm 0:9b334a45a8ff 344 * @param htim: TIM Hall Sensor handle
bogdanm 0:9b334a45a8ff 345 * @retval HAL status
bogdanm 0:9b334a45a8ff 346 */
bogdanm 0:9b334a45a8ff 347 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 348 {
bogdanm 0:9b334a45a8ff 349 /* Check the parameters */
bogdanm 0:9b334a45a8ff 350 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 /* Disable the TIM Peripheral Clock */
bogdanm 0:9b334a45a8ff 355 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm 0:9b334a45a8ff 358 HAL_TIMEx_HallSensor_MspDeInit(htim);
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360 /* Change TIM state */
bogdanm 0:9b334a45a8ff 361 htim->State = HAL_TIM_STATE_RESET;
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 /* Release Lock */
bogdanm 0:9b334a45a8ff 364 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 return HAL_OK;
bogdanm 0:9b334a45a8ff 367 }
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 /**
bogdanm 0:9b334a45a8ff 370 * @brief Initializes the TIM Hall Sensor MSP.
bogdanm 0:9b334a45a8ff 371 * @param htim: TIM handle
bogdanm 0:9b334a45a8ff 372 * @retval None
bogdanm 0:9b334a45a8ff 373 */
bogdanm 0:9b334a45a8ff 374 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 375 {
bogdanm 0:9b334a45a8ff 376 /* NOTE : This function should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 377 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 378 */
bogdanm 0:9b334a45a8ff 379 }
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 /**
bogdanm 0:9b334a45a8ff 382 * @brief DeInitialize TIM Hall Sensor MSP.
bogdanm 0:9b334a45a8ff 383 * @param htim: TIM handle
bogdanm 0:9b334a45a8ff 384 * @retval None
bogdanm 0:9b334a45a8ff 385 */
bogdanm 0:9b334a45a8ff 386 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 387 {
bogdanm 0:9b334a45a8ff 388 /* NOTE : This function should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 389 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 390 */
bogdanm 0:9b334a45a8ff 391 }
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 /**
bogdanm 0:9b334a45a8ff 394 * @brief Starts the TIM Hall Sensor Interface.
bogdanm 0:9b334a45a8ff 395 * @param htim : TIM Hall Sensor handle
bogdanm 0:9b334a45a8ff 396 * @retval HAL status
bogdanm 0:9b334a45a8ff 397 */
bogdanm 0:9b334a45a8ff 398 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 399 {
bogdanm 0:9b334a45a8ff 400 /* Check the parameters */
bogdanm 0:9b334a45a8ff 401 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 /* Enable the Input Capture channels 1
bogdanm 0:9b334a45a8ff 404 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm 0:9b334a45a8ff 405 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 408 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /* Return function status */
bogdanm 0:9b334a45a8ff 411 return HAL_OK;
bogdanm 0:9b334a45a8ff 412 }
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /**
bogdanm 0:9b334a45a8ff 415 * @brief Stops the TIM Hall sensor Interface.
bogdanm 0:9b334a45a8ff 416 * @param htim : TIM Hall Sensor handle
bogdanm 0:9b334a45a8ff 417 * @retval HAL status
bogdanm 0:9b334a45a8ff 418 */
bogdanm 0:9b334a45a8ff 419 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 420 {
bogdanm 0:9b334a45a8ff 421 /* Check the parameters */
bogdanm 0:9b334a45a8ff 422 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /* Disable the Input Capture channels 1, 2 and 3
bogdanm 0:9b334a45a8ff 425 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm 0:9b334a45a8ff 426 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 429 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 430
bogdanm 0:9b334a45a8ff 431 /* Return function status */
bogdanm 0:9b334a45a8ff 432 return HAL_OK;
bogdanm 0:9b334a45a8ff 433 }
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 /**
bogdanm 0:9b334a45a8ff 436 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
bogdanm 0:9b334a45a8ff 437 * @param htim : TIM Hall Sensor handle
bogdanm 0:9b334a45a8ff 438 * @retval HAL status
bogdanm 0:9b334a45a8ff 439 */
bogdanm 0:9b334a45a8ff 440 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 441 {
bogdanm 0:9b334a45a8ff 442 /* Check the parameters */
bogdanm 0:9b334a45a8ff 443 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 444
bogdanm 0:9b334a45a8ff 445 /* Enable the capture compare Interrupts 1 event */
bogdanm 0:9b334a45a8ff 446 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 447
bogdanm 0:9b334a45a8ff 448 /* Enable the Input Capture channels 1
bogdanm 0:9b334a45a8ff 449 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm 0:9b334a45a8ff 450 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 453 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 /* Return function status */
bogdanm 0:9b334a45a8ff 456 return HAL_OK;
bogdanm 0:9b334a45a8ff 457 }
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459 /**
bogdanm 0:9b334a45a8ff 460 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
bogdanm 0:9b334a45a8ff 461 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 462 * @retval HAL status
bogdanm 0:9b334a45a8ff 463 */
bogdanm 0:9b334a45a8ff 464 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 465 {
bogdanm 0:9b334a45a8ff 466 /* Check the parameters */
bogdanm 0:9b334a45a8ff 467 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /* Disable the Input Capture channels 1
bogdanm 0:9b334a45a8ff 470 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm 0:9b334a45a8ff 471 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /* Disable the capture compare Interrupts event */
bogdanm 0:9b334a45a8ff 474 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 477 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479 /* Return function status */
bogdanm 0:9b334a45a8ff 480 return HAL_OK;
bogdanm 0:9b334a45a8ff 481 }
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /**
bogdanm 0:9b334a45a8ff 484 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
bogdanm 0:9b334a45a8ff 485 * @param htim : TIM Hall Sensor handle
bogdanm 0:9b334a45a8ff 486 * @param pData: The destination Buffer address.
bogdanm 0:9b334a45a8ff 487 * @param Length: The length of data to be transferred from TIM peripheral to memory.
bogdanm 0:9b334a45a8ff 488 * @retval HAL status
bogdanm 0:9b334a45a8ff 489 */
bogdanm 0:9b334a45a8ff 490 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
bogdanm 0:9b334a45a8ff 491 {
bogdanm 0:9b334a45a8ff 492 /* Check the parameters */
bogdanm 0:9b334a45a8ff 493 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 496 {
bogdanm 0:9b334a45a8ff 497 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 498 }
bogdanm 0:9b334a45a8ff 499 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 500 {
bogdanm 0:9b334a45a8ff 501 if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm 0:9b334a45a8ff 502 {
bogdanm 0:9b334a45a8ff 503 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 504 }
bogdanm 0:9b334a45a8ff 505 else
bogdanm 0:9b334a45a8ff 506 {
bogdanm 0:9b334a45a8ff 507 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 508 }
bogdanm 0:9b334a45a8ff 509 }
bogdanm 0:9b334a45a8ff 510 /* Enable the Input Capture channels 1
bogdanm 0:9b334a45a8ff 511 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm 0:9b334a45a8ff 512 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514 /* Set the DMA Input Capture 1 Callback */
bogdanm 0:9b334a45a8ff 515 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 516 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 517 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 518
bogdanm 0:9b334a45a8ff 519 /* Enable the DMA channel for Capture 1*/
bogdanm 0:9b334a45a8ff 520 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 /* Enable the capture compare 1 Interrupt */
bogdanm 0:9b334a45a8ff 523 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 526 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 527
bogdanm 0:9b334a45a8ff 528 /* Return function status */
bogdanm 0:9b334a45a8ff 529 return HAL_OK;
bogdanm 0:9b334a45a8ff 530 }
bogdanm 0:9b334a45a8ff 531
bogdanm 0:9b334a45a8ff 532 /**
bogdanm 0:9b334a45a8ff 533 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
bogdanm 0:9b334a45a8ff 534 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 535 * @retval HAL status
bogdanm 0:9b334a45a8ff 536 */
bogdanm 0:9b334a45a8ff 537 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 538 {
bogdanm 0:9b334a45a8ff 539 /* Check the parameters */
bogdanm 0:9b334a45a8ff 540 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /* Disable the Input Capture channels 1
bogdanm 0:9b334a45a8ff 543 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm 0:9b334a45a8ff 544 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 545
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 /* Disable the capture compare Interrupts 1 event */
bogdanm 0:9b334a45a8ff 548 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 551 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 552
bogdanm 0:9b334a45a8ff 553 /* Return function status */
bogdanm 0:9b334a45a8ff 554 return HAL_OK;
bogdanm 0:9b334a45a8ff 555 }
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 /**
bogdanm 0:9b334a45a8ff 558 * @}
bogdanm 0:9b334a45a8ff 559 */
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
bogdanm 0:9b334a45a8ff 562 * @brief Timer Complementary Output Compare functions
bogdanm 0:9b334a45a8ff 563 *
bogdanm 0:9b334a45a8ff 564 @verbatim
bogdanm 0:9b334a45a8ff 565 ==============================================================================
bogdanm 0:9b334a45a8ff 566 ##### Timer Complementary Output Compare functions #####
bogdanm 0:9b334a45a8ff 567 ==============================================================================
bogdanm 0:9b334a45a8ff 568 [..]
bogdanm 0:9b334a45a8ff 569 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 570 (+) Start the Complementary Output Compare/PWM.
bogdanm 0:9b334a45a8ff 571 (+) Stop the Complementary Output Compare/PWM.
bogdanm 0:9b334a45a8ff 572 (+) Start the Complementary Output Compare/PWM and enable interrupts.
bogdanm 0:9b334a45a8ff 573 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
bogdanm 0:9b334a45a8ff 574 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
bogdanm 0:9b334a45a8ff 575 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 @endverbatim
bogdanm 0:9b334a45a8ff 578 * @{
bogdanm 0:9b334a45a8ff 579 */
bogdanm 0:9b334a45a8ff 580
bogdanm 0:9b334a45a8ff 581 /**
bogdanm 0:9b334a45a8ff 582 * @brief Starts the TIM Output Compare signal generation on the complementary
bogdanm 0:9b334a45a8ff 583 * output.
bogdanm 0:9b334a45a8ff 584 * @param htim : TIM Output Compare handle
bogdanm 0:9b334a45a8ff 585 * @param Channel : TIM Channel to be enabled
bogdanm 0:9b334a45a8ff 586 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 587 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 588 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 589 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 590 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 591 * @retval HAL status
bogdanm 0:9b334a45a8ff 592 */
bogdanm 0:9b334a45a8ff 593 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 594 {
bogdanm 0:9b334a45a8ff 595 /* Check the parameters */
bogdanm 0:9b334a45a8ff 596 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 597
bogdanm 0:9b334a45a8ff 598 /* Enable the Capture compare channel N */
bogdanm 0:9b334a45a8ff 599 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 600
bogdanm 0:9b334a45a8ff 601 /* Enable the Main Ouput */
bogdanm 0:9b334a45a8ff 602 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 603
bogdanm 0:9b334a45a8ff 604 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 605 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 606
bogdanm 0:9b334a45a8ff 607 /* Return function status */
bogdanm 0:9b334a45a8ff 608 return HAL_OK;
bogdanm 0:9b334a45a8ff 609 }
bogdanm 0:9b334a45a8ff 610
bogdanm 0:9b334a45a8ff 611 /**
bogdanm 0:9b334a45a8ff 612 * @brief Stops the TIM Output Compare signal generation on the complementary
bogdanm 0:9b334a45a8ff 613 * output.
bogdanm 0:9b334a45a8ff 614 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 615 * @param Channel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 616 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 617 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 618 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 619 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 620 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 621 * @retval HAL status
bogdanm 0:9b334a45a8ff 622 */
bogdanm 0:9b334a45a8ff 623 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 624 {
bogdanm 0:9b334a45a8ff 625 /* Check the parameters */
bogdanm 0:9b334a45a8ff 626 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 627
bogdanm 0:9b334a45a8ff 628 /* Disable the Capture compare channel N */
bogdanm 0:9b334a45a8ff 629 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 630
bogdanm 0:9b334a45a8ff 631 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 632 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 633
bogdanm 0:9b334a45a8ff 634 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 635 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 /* Return function status */
bogdanm 0:9b334a45a8ff 638 return HAL_OK;
bogdanm 0:9b334a45a8ff 639 }
bogdanm 0:9b334a45a8ff 640
bogdanm 0:9b334a45a8ff 641 /**
bogdanm 0:9b334a45a8ff 642 * @brief Starts the TIM Output Compare signal generation in interrupt mode
bogdanm 0:9b334a45a8ff 643 * on the complementary output.
bogdanm 0:9b334a45a8ff 644 * @param htim : TIM OC handle
bogdanm 0:9b334a45a8ff 645 * @param Channel : TIM Channel to be enabled
bogdanm 0:9b334a45a8ff 646 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 647 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 648 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 649 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 650 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 651 * @retval HAL status
bogdanm 0:9b334a45a8ff 652 */
bogdanm 0:9b334a45a8ff 653 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 654 {
bogdanm 0:9b334a45a8ff 655 /* Check the parameters */
bogdanm 0:9b334a45a8ff 656 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 657
bogdanm 0:9b334a45a8ff 658 switch (Channel)
bogdanm 0:9b334a45a8ff 659 {
bogdanm 0:9b334a45a8ff 660 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 661 {
bogdanm 0:9b334a45a8ff 662 /* Enable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 663 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 664 }
bogdanm 0:9b334a45a8ff 665 break;
bogdanm 0:9b334a45a8ff 666
bogdanm 0:9b334a45a8ff 667 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 668 {
bogdanm 0:9b334a45a8ff 669 /* Enable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 670 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 671 }
bogdanm 0:9b334a45a8ff 672 break;
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 675 {
bogdanm 0:9b334a45a8ff 676 /* Enable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 677 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 678 }
bogdanm 0:9b334a45a8ff 679 break;
bogdanm 0:9b334a45a8ff 680
bogdanm 0:9b334a45a8ff 681 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 682 {
bogdanm 0:9b334a45a8ff 683 /* Enable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 684 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 685 }
bogdanm 0:9b334a45a8ff 686 break;
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 default:
bogdanm 0:9b334a45a8ff 689 break;
bogdanm 0:9b334a45a8ff 690 }
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 /* Enable the TIM Break interrupt */
bogdanm 0:9b334a45a8ff 693 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 /* Enable the Capture compare channel N */
bogdanm 0:9b334a45a8ff 696 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 697
bogdanm 0:9b334a45a8ff 698 /* Enable the Main Ouput */
bogdanm 0:9b334a45a8ff 699 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 702 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 /* Return function status */
bogdanm 0:9b334a45a8ff 705 return HAL_OK;
bogdanm 0:9b334a45a8ff 706 }
bogdanm 0:9b334a45a8ff 707
bogdanm 0:9b334a45a8ff 708 /**
bogdanm 0:9b334a45a8ff 709 * @brief Stops the TIM Output Compare signal generation in interrupt mode
bogdanm 0:9b334a45a8ff 710 * on the complementary output.
bogdanm 0:9b334a45a8ff 711 * @param htim : TIM Output Compare handle
bogdanm 0:9b334a45a8ff 712 * @param Channel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 713 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 714 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 715 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 716 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 717 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 718 * @retval HAL status
bogdanm 0:9b334a45a8ff 719 */
bogdanm 0:9b334a45a8ff 720 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 721 {
bogdanm 0:9b334a45a8ff 722 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 723
bogdanm 0:9b334a45a8ff 724 /* Check the parameters */
bogdanm 0:9b334a45a8ff 725 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 726
bogdanm 0:9b334a45a8ff 727 switch (Channel)
bogdanm 0:9b334a45a8ff 728 {
bogdanm 0:9b334a45a8ff 729 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 730 {
bogdanm 0:9b334a45a8ff 731 /* Disable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 732 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 733 }
bogdanm 0:9b334a45a8ff 734 break;
bogdanm 0:9b334a45a8ff 735
bogdanm 0:9b334a45a8ff 736 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 737 {
bogdanm 0:9b334a45a8ff 738 /* Disable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 739 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 740 }
bogdanm 0:9b334a45a8ff 741 break;
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 744 {
bogdanm 0:9b334a45a8ff 745 /* Disable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 746 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 747 }
bogdanm 0:9b334a45a8ff 748 break;
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 751 {
bogdanm 0:9b334a45a8ff 752 /* Disable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 753 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 754 }
bogdanm 0:9b334a45a8ff 755 break;
bogdanm 0:9b334a45a8ff 756
bogdanm 0:9b334a45a8ff 757 default:
bogdanm 0:9b334a45a8ff 758 break;
bogdanm 0:9b334a45a8ff 759 }
bogdanm 0:9b334a45a8ff 760
bogdanm 0:9b334a45a8ff 761 /* Disable the Capture compare channel N */
bogdanm 0:9b334a45a8ff 762 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 763
bogdanm 0:9b334a45a8ff 764 /* Disable the TIM Break interrupt (only if no more channel is active) */
bogdanm 0:9b334a45a8ff 765 tmpccer = htim->Instance->CCER;
bogdanm 0:9b334a45a8ff 766 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
bogdanm 0:9b334a45a8ff 767 {
bogdanm 0:9b334a45a8ff 768 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
bogdanm 0:9b334a45a8ff 769 }
bogdanm 0:9b334a45a8ff 770
bogdanm 0:9b334a45a8ff 771 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 772 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 773
bogdanm 0:9b334a45a8ff 774 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 775 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 776
bogdanm 0:9b334a45a8ff 777 /* Return function status */
bogdanm 0:9b334a45a8ff 778 return HAL_OK;
bogdanm 0:9b334a45a8ff 779 }
bogdanm 0:9b334a45a8ff 780
bogdanm 0:9b334a45a8ff 781 /**
bogdanm 0:9b334a45a8ff 782 * @brief Starts the TIM Output Compare signal generation in DMA mode
bogdanm 0:9b334a45a8ff 783 * on the complementary output.
bogdanm 0:9b334a45a8ff 784 * @param htim : TIM Output Compare handle
bogdanm 0:9b334a45a8ff 785 * @param Channel : TIM Channel to be enabled
bogdanm 0:9b334a45a8ff 786 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 787 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 788 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 789 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 790 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 791 * @param pData: The source Buffer address.
bogdanm 0:9b334a45a8ff 792 * @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm 0:9b334a45a8ff 793 * @retval HAL status
bogdanm 0:9b334a45a8ff 794 */
bogdanm 0:9b334a45a8ff 795 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
bogdanm 0:9b334a45a8ff 796 {
bogdanm 0:9b334a45a8ff 797 /* Check the parameters */
bogdanm 0:9b334a45a8ff 798 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 799
bogdanm 0:9b334a45a8ff 800 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 801 {
bogdanm 0:9b334a45a8ff 802 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 803 }
bogdanm 0:9b334a45a8ff 804 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 805 {
bogdanm 0:9b334a45a8ff 806 if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm 0:9b334a45a8ff 807 {
bogdanm 0:9b334a45a8ff 808 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 809 }
bogdanm 0:9b334a45a8ff 810 else
bogdanm 0:9b334a45a8ff 811 {
bogdanm 0:9b334a45a8ff 812 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 813 }
bogdanm 0:9b334a45a8ff 814 }
bogdanm 0:9b334a45a8ff 815 switch (Channel)
bogdanm 0:9b334a45a8ff 816 {
bogdanm 0:9b334a45a8ff 817 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 818 {
bogdanm 0:9b334a45a8ff 819 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 820 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 821
bogdanm 0:9b334a45a8ff 822 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 823 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 824
bogdanm 0:9b334a45a8ff 825 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 826 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm 0:9b334a45a8ff 827
bogdanm 0:9b334a45a8ff 828 /* Enable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 829 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 830 }
bogdanm 0:9b334a45a8ff 831 break;
bogdanm 0:9b334a45a8ff 832
bogdanm 0:9b334a45a8ff 833 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 834 {
bogdanm 0:9b334a45a8ff 835 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 836 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 837
bogdanm 0:9b334a45a8ff 838 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 839 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 840
bogdanm 0:9b334a45a8ff 841 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 842 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 /* Enable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 845 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 846 }
bogdanm 0:9b334a45a8ff 847 break;
bogdanm 0:9b334a45a8ff 848
bogdanm 0:9b334a45a8ff 849 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 850 {
bogdanm 0:9b334a45a8ff 851 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 852 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 853
bogdanm 0:9b334a45a8ff 854 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 855 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 856
bogdanm 0:9b334a45a8ff 857 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 858 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm 0:9b334a45a8ff 859
bogdanm 0:9b334a45a8ff 860 /* Enable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 861 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 862 }
bogdanm 0:9b334a45a8ff 863 break;
bogdanm 0:9b334a45a8ff 864
bogdanm 0:9b334a45a8ff 865 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 866 {
bogdanm 0:9b334a45a8ff 867 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 868 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 869
bogdanm 0:9b334a45a8ff 870 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 871 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 872
bogdanm 0:9b334a45a8ff 873 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 874 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm 0:9b334a45a8ff 875
bogdanm 0:9b334a45a8ff 876 /* Enable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 877 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 878 }
bogdanm 0:9b334a45a8ff 879 break;
bogdanm 0:9b334a45a8ff 880
bogdanm 0:9b334a45a8ff 881 default:
bogdanm 0:9b334a45a8ff 882 break;
bogdanm 0:9b334a45a8ff 883 }
bogdanm 0:9b334a45a8ff 884
bogdanm 0:9b334a45a8ff 885 /* Enable the Capture compare channel N */
bogdanm 0:9b334a45a8ff 886 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 887
bogdanm 0:9b334a45a8ff 888 /* Enable the Main Ouput */
bogdanm 0:9b334a45a8ff 889 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 890
bogdanm 0:9b334a45a8ff 891 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 892 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 /* Return function status */
bogdanm 0:9b334a45a8ff 895 return HAL_OK;
bogdanm 0:9b334a45a8ff 896 }
bogdanm 0:9b334a45a8ff 897
bogdanm 0:9b334a45a8ff 898 /**
bogdanm 0:9b334a45a8ff 899 * @brief Stops the TIM Output Compare signal generation in DMA mode
bogdanm 0:9b334a45a8ff 900 * on the complementary output.
bogdanm 0:9b334a45a8ff 901 * @param htim : TIM Output Compare handle
bogdanm 0:9b334a45a8ff 902 * @param Channel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 903 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 904 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 905 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 906 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 907 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 908 * @retval HAL status
bogdanm 0:9b334a45a8ff 909 */
bogdanm 0:9b334a45a8ff 910 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 911 {
bogdanm 0:9b334a45a8ff 912 /* Check the parameters */
bogdanm 0:9b334a45a8ff 913 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 914
bogdanm 0:9b334a45a8ff 915 switch (Channel)
bogdanm 0:9b334a45a8ff 916 {
bogdanm 0:9b334a45a8ff 917 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 918 {
bogdanm 0:9b334a45a8ff 919 /* Disable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 920 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 921 }
bogdanm 0:9b334a45a8ff 922 break;
bogdanm 0:9b334a45a8ff 923
bogdanm 0:9b334a45a8ff 924 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 925 {
bogdanm 0:9b334a45a8ff 926 /* Disable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 927 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 928 }
bogdanm 0:9b334a45a8ff 929 break;
bogdanm 0:9b334a45a8ff 930
bogdanm 0:9b334a45a8ff 931 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 932 {
bogdanm 0:9b334a45a8ff 933 /* Disable the TIM Output Compare DMA request */
bogdanm 0:9b334a45a8ff 934 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 935 }
bogdanm 0:9b334a45a8ff 936 break;
bogdanm 0:9b334a45a8ff 937
bogdanm 0:9b334a45a8ff 938 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 939 {
bogdanm 0:9b334a45a8ff 940 /* Disable the TIM Output Compare interrupt */
bogdanm 0:9b334a45a8ff 941 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 942 }
bogdanm 0:9b334a45a8ff 943 break;
bogdanm 0:9b334a45a8ff 944
bogdanm 0:9b334a45a8ff 945 default:
bogdanm 0:9b334a45a8ff 946 break;
bogdanm 0:9b334a45a8ff 947 }
bogdanm 0:9b334a45a8ff 948
bogdanm 0:9b334a45a8ff 949 /* Disable the Capture compare channel N */
bogdanm 0:9b334a45a8ff 950 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 951
bogdanm 0:9b334a45a8ff 952 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 953 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 954
bogdanm 0:9b334a45a8ff 955 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 956 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 957
bogdanm 0:9b334a45a8ff 958 /* Change the htim state */
bogdanm 0:9b334a45a8ff 959 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 960
bogdanm 0:9b334a45a8ff 961 /* Return function status */
bogdanm 0:9b334a45a8ff 962 return HAL_OK;
bogdanm 0:9b334a45a8ff 963 }
bogdanm 0:9b334a45a8ff 964
bogdanm 0:9b334a45a8ff 965 /**
bogdanm 0:9b334a45a8ff 966 * @}
bogdanm 0:9b334a45a8ff 967 */
bogdanm 0:9b334a45a8ff 968
bogdanm 0:9b334a45a8ff 969 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
bogdanm 0:9b334a45a8ff 970 * @brief Timer Complementary PWM functions
bogdanm 0:9b334a45a8ff 971 *
bogdanm 0:9b334a45a8ff 972 @verbatim
bogdanm 0:9b334a45a8ff 973 ==============================================================================
bogdanm 0:9b334a45a8ff 974 ##### Timer Complementary PWM functions #####
bogdanm 0:9b334a45a8ff 975 ==============================================================================
bogdanm 0:9b334a45a8ff 976 [..]
bogdanm 0:9b334a45a8ff 977 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 978 (+) Start the Complementary PWM.
bogdanm 0:9b334a45a8ff 979 (+) Stop the Complementary PWM.
bogdanm 0:9b334a45a8ff 980 (+) Start the Complementary PWM and enable interrupts.
bogdanm 0:9b334a45a8ff 981 (+) Stop the Complementary PWM and disable interrupts.
bogdanm 0:9b334a45a8ff 982 (+) Start the Complementary PWM and enable DMA transfers.
bogdanm 0:9b334a45a8ff 983 (+) Stop the Complementary PWM and disable DMA transfers.
bogdanm 0:9b334a45a8ff 984 (+) Start the Complementary Input Capture measurement.
bogdanm 0:9b334a45a8ff 985 (+) Stop the Complementary Input Capture.
bogdanm 0:9b334a45a8ff 986 (+) Start the Complementary Input Capture and enable interrupts.
bogdanm 0:9b334a45a8ff 987 (+) Stop the Complementary Input Capture and disable interrupts.
bogdanm 0:9b334a45a8ff 988 (+) Start the Complementary Input Capture and enable DMA transfers.
bogdanm 0:9b334a45a8ff 989 (+) Stop the Complementary Input Capture and disable DMA transfers.
bogdanm 0:9b334a45a8ff 990 (+) Start the Complementary One Pulse generation.
bogdanm 0:9b334a45a8ff 991 (+) Stop the Complementary One Pulse.
bogdanm 0:9b334a45a8ff 992 (+) Start the Complementary One Pulse and enable interrupts.
bogdanm 0:9b334a45a8ff 993 (+) Stop the Complementary One Pulse and disable interrupts.
bogdanm 0:9b334a45a8ff 994
bogdanm 0:9b334a45a8ff 995 @endverbatim
bogdanm 0:9b334a45a8ff 996 * @{
bogdanm 0:9b334a45a8ff 997 */
bogdanm 0:9b334a45a8ff 998
bogdanm 0:9b334a45a8ff 999 /**
bogdanm 0:9b334a45a8ff 1000 * @brief Starts the PWM signal generation on the complementary output.
bogdanm 0:9b334a45a8ff 1001 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1002 * @param Channel : TIM Channel to be enabled
bogdanm 0:9b334a45a8ff 1003 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1004 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1005 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1006 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1007 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1008 * @retval HAL status
bogdanm 0:9b334a45a8ff 1009 */
bogdanm 0:9b334a45a8ff 1010 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1011 {
bogdanm 0:9b334a45a8ff 1012 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1013 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1014
bogdanm 0:9b334a45a8ff 1015 /* Enable the complementary PWM output */
bogdanm 0:9b334a45a8ff 1016 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 1017
bogdanm 0:9b334a45a8ff 1018 /* Enable the Main Ouput */
bogdanm 0:9b334a45a8ff 1019 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1020
bogdanm 0:9b334a45a8ff 1021 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 1022 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1023
bogdanm 0:9b334a45a8ff 1024 /* Return function status */
bogdanm 0:9b334a45a8ff 1025 return HAL_OK;
bogdanm 0:9b334a45a8ff 1026 }
bogdanm 0:9b334a45a8ff 1027
bogdanm 0:9b334a45a8ff 1028 /**
bogdanm 0:9b334a45a8ff 1029 * @brief Stops the PWM signal generation on the complementary output.
bogdanm 0:9b334a45a8ff 1030 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1031 * @param Channel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 1032 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1033 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1034 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1035 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1036 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1037 * @retval HAL status
bogdanm 0:9b334a45a8ff 1038 */
bogdanm 0:9b334a45a8ff 1039 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1040 {
bogdanm 0:9b334a45a8ff 1041 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1042 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1043
bogdanm 0:9b334a45a8ff 1044 /* Disable the complementary PWM output */
bogdanm 0:9b334a45a8ff 1045 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 1046
bogdanm 0:9b334a45a8ff 1047 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 1048 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1049
bogdanm 0:9b334a45a8ff 1050 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1051 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1052
bogdanm 0:9b334a45a8ff 1053 /* Return function status */
bogdanm 0:9b334a45a8ff 1054 return HAL_OK;
bogdanm 0:9b334a45a8ff 1055 }
bogdanm 0:9b334a45a8ff 1056
bogdanm 0:9b334a45a8ff 1057 /**
bogdanm 0:9b334a45a8ff 1058 * @brief Starts the PWM signal generation in interrupt mode on the
bogdanm 0:9b334a45a8ff 1059 * complementary output.
bogdanm 0:9b334a45a8ff 1060 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1061 * @param Channel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 1062 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1063 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1064 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1065 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1066 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1067 * @retval HAL status
bogdanm 0:9b334a45a8ff 1068 */
bogdanm 0:9b334a45a8ff 1069 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1070 {
bogdanm 0:9b334a45a8ff 1071 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1072 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1073
bogdanm 0:9b334a45a8ff 1074 switch (Channel)
bogdanm 0:9b334a45a8ff 1075 {
bogdanm 0:9b334a45a8ff 1076 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1077 {
bogdanm 0:9b334a45a8ff 1078 /* Enable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 1079 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 1080 }
bogdanm 0:9b334a45a8ff 1081 break;
bogdanm 0:9b334a45a8ff 1082
bogdanm 0:9b334a45a8ff 1083 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1084 {
bogdanm 0:9b334a45a8ff 1085 /* Enable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 1086 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 1087 }
bogdanm 0:9b334a45a8ff 1088 break;
bogdanm 0:9b334a45a8ff 1089
bogdanm 0:9b334a45a8ff 1090 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1091 {
bogdanm 0:9b334a45a8ff 1092 /* Enable the TIM Capture/Compare 3 interrupt */
bogdanm 0:9b334a45a8ff 1093 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 1094 }
bogdanm 0:9b334a45a8ff 1095 break;
bogdanm 0:9b334a45a8ff 1096
bogdanm 0:9b334a45a8ff 1097 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1098 {
bogdanm 0:9b334a45a8ff 1099 /* Enable the TIM Capture/Compare 4 interrupt */
bogdanm 0:9b334a45a8ff 1100 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 1101 }
bogdanm 0:9b334a45a8ff 1102 break;
bogdanm 0:9b334a45a8ff 1103
bogdanm 0:9b334a45a8ff 1104 default:
bogdanm 0:9b334a45a8ff 1105 break;
bogdanm 0:9b334a45a8ff 1106 }
bogdanm 0:9b334a45a8ff 1107
bogdanm 0:9b334a45a8ff 1108 /* Enable the TIM Break interrupt */
bogdanm 0:9b334a45a8ff 1109 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
bogdanm 0:9b334a45a8ff 1110
bogdanm 0:9b334a45a8ff 1111 /* Enable the complementary PWM output */
bogdanm 0:9b334a45a8ff 1112 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 1113
bogdanm 0:9b334a45a8ff 1114 /* Enable the Main Ouput */
bogdanm 0:9b334a45a8ff 1115 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1116
bogdanm 0:9b334a45a8ff 1117 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 1118 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1119
bogdanm 0:9b334a45a8ff 1120 /* Return function status */
bogdanm 0:9b334a45a8ff 1121 return HAL_OK;
bogdanm 0:9b334a45a8ff 1122 }
bogdanm 0:9b334a45a8ff 1123
bogdanm 0:9b334a45a8ff 1124 /**
bogdanm 0:9b334a45a8ff 1125 * @brief Stops the PWM signal generation in interrupt mode on the
bogdanm 0:9b334a45a8ff 1126 * complementary output.
bogdanm 0:9b334a45a8ff 1127 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1128 * @param Channel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 1129 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1130 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1131 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1132 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1133 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1134 * @retval HAL status
bogdanm 0:9b334a45a8ff 1135 */
bogdanm 0:9b334a45a8ff 1136 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1137 {
bogdanm 0:9b334a45a8ff 1138 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 1139
bogdanm 0:9b334a45a8ff 1140 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1141 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1142
bogdanm 0:9b334a45a8ff 1143 switch (Channel)
bogdanm 0:9b334a45a8ff 1144 {
bogdanm 0:9b334a45a8ff 1145 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1146 {
bogdanm 0:9b334a45a8ff 1147 /* Disable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 1148 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 1149 }
bogdanm 0:9b334a45a8ff 1150 break;
bogdanm 0:9b334a45a8ff 1151
bogdanm 0:9b334a45a8ff 1152 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1153 {
bogdanm 0:9b334a45a8ff 1154 /* Disable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 1155 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 1156 }
bogdanm 0:9b334a45a8ff 1157 break;
bogdanm 0:9b334a45a8ff 1158
bogdanm 0:9b334a45a8ff 1159 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1160 {
bogdanm 0:9b334a45a8ff 1161 /* Disable the TIM Capture/Compare 3 interrupt */
bogdanm 0:9b334a45a8ff 1162 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 1163 }
bogdanm 0:9b334a45a8ff 1164 break;
bogdanm 0:9b334a45a8ff 1165
bogdanm 0:9b334a45a8ff 1166 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1167 {
bogdanm 0:9b334a45a8ff 1168 /* Disable the TIM Capture/Compare 3 interrupt */
bogdanm 0:9b334a45a8ff 1169 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 1170 }
bogdanm 0:9b334a45a8ff 1171 break;
bogdanm 0:9b334a45a8ff 1172
bogdanm 0:9b334a45a8ff 1173 default:
bogdanm 0:9b334a45a8ff 1174 break;
bogdanm 0:9b334a45a8ff 1175 }
bogdanm 0:9b334a45a8ff 1176
bogdanm 0:9b334a45a8ff 1177 /* Disable the complementary PWM output */
bogdanm 0:9b334a45a8ff 1178 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 1179
bogdanm 0:9b334a45a8ff 1180
bogdanm 0:9b334a45a8ff 1181 /* Disable the TIM Break interrupt (only if no more channel is active) */
bogdanm 0:9b334a45a8ff 1182 tmpccer = htim->Instance->CCER;
bogdanm 0:9b334a45a8ff 1183 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
bogdanm 0:9b334a45a8ff 1184 {
bogdanm 0:9b334a45a8ff 1185 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
bogdanm 0:9b334a45a8ff 1186 }
bogdanm 0:9b334a45a8ff 1187
bogdanm 0:9b334a45a8ff 1188 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 1189 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1190
bogdanm 0:9b334a45a8ff 1191 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1192 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1193
bogdanm 0:9b334a45a8ff 1194 /* Return function status */
bogdanm 0:9b334a45a8ff 1195 return HAL_OK;
bogdanm 0:9b334a45a8ff 1196 }
bogdanm 0:9b334a45a8ff 1197
bogdanm 0:9b334a45a8ff 1198 /**
bogdanm 0:9b334a45a8ff 1199 * @brief Starts the TIM PWM signal generation in DMA mode on the
bogdanm 0:9b334a45a8ff 1200 * complementary output
bogdanm 0:9b334a45a8ff 1201 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1202 * @param Channel : TIM Channel to be enabled
bogdanm 0:9b334a45a8ff 1203 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1204 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1205 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1206 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1207 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1208 * @param pData: The source Buffer address.
bogdanm 0:9b334a45a8ff 1209 * @param Length: The length of data to be transferred from memory to TIM peripheral
bogdanm 0:9b334a45a8ff 1210 * @retval HAL status
bogdanm 0:9b334a45a8ff 1211 */
bogdanm 0:9b334a45a8ff 1212 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
bogdanm 0:9b334a45a8ff 1213 {
bogdanm 0:9b334a45a8ff 1214 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1215 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1216
bogdanm 0:9b334a45a8ff 1217 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 1218 {
bogdanm 0:9b334a45a8ff 1219 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1220 }
bogdanm 0:9b334a45a8ff 1221 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 1222 {
bogdanm 0:9b334a45a8ff 1223 if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm 0:9b334a45a8ff 1224 {
bogdanm 0:9b334a45a8ff 1225 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1226 }
bogdanm 0:9b334a45a8ff 1227 else
bogdanm 0:9b334a45a8ff 1228 {
bogdanm 0:9b334a45a8ff 1229 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1230 }
bogdanm 0:9b334a45a8ff 1231 }
bogdanm 0:9b334a45a8ff 1232 switch (Channel)
bogdanm 0:9b334a45a8ff 1233 {
bogdanm 0:9b334a45a8ff 1234 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1235 {
bogdanm 0:9b334a45a8ff 1236 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1237 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 1238
bogdanm 0:9b334a45a8ff 1239 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1240 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1241
bogdanm 0:9b334a45a8ff 1242 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 1243 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm 0:9b334a45a8ff 1244
bogdanm 0:9b334a45a8ff 1245 /* Enable the TIM Capture/Compare 1 DMA request */
bogdanm 0:9b334a45a8ff 1246 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 1247 }
bogdanm 0:9b334a45a8ff 1248 break;
bogdanm 0:9b334a45a8ff 1249
bogdanm 0:9b334a45a8ff 1250 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1251 {
bogdanm 0:9b334a45a8ff 1252 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1253 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 1254
bogdanm 0:9b334a45a8ff 1255 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1256 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1257
bogdanm 0:9b334a45a8ff 1258 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 1259 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm 0:9b334a45a8ff 1260
bogdanm 0:9b334a45a8ff 1261 /* Enable the TIM Capture/Compare 2 DMA request */
bogdanm 0:9b334a45a8ff 1262 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 1263 }
bogdanm 0:9b334a45a8ff 1264 break;
bogdanm 0:9b334a45a8ff 1265
bogdanm 0:9b334a45a8ff 1266 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1267 {
bogdanm 0:9b334a45a8ff 1268 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1269 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 1270
bogdanm 0:9b334a45a8ff 1271 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1272 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1273
bogdanm 0:9b334a45a8ff 1274 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 1275 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm 0:9b334a45a8ff 1276
bogdanm 0:9b334a45a8ff 1277 /* Enable the TIM Capture/Compare 3 DMA request */
bogdanm 0:9b334a45a8ff 1278 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 1279 }
bogdanm 0:9b334a45a8ff 1280 break;
bogdanm 0:9b334a45a8ff 1281
bogdanm 0:9b334a45a8ff 1282 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1283 {
bogdanm 0:9b334a45a8ff 1284 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1285 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 1286
bogdanm 0:9b334a45a8ff 1287 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1288 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1289
bogdanm 0:9b334a45a8ff 1290 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 1291 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm 0:9b334a45a8ff 1292
bogdanm 0:9b334a45a8ff 1293 /* Enable the TIM Capture/Compare 4 DMA request */
bogdanm 0:9b334a45a8ff 1294 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 1295 }
bogdanm 0:9b334a45a8ff 1296 break;
bogdanm 0:9b334a45a8ff 1297
bogdanm 0:9b334a45a8ff 1298 default:
bogdanm 0:9b334a45a8ff 1299 break;
bogdanm 0:9b334a45a8ff 1300 }
bogdanm 0:9b334a45a8ff 1301
bogdanm 0:9b334a45a8ff 1302 /* Enable the complementary PWM output */
bogdanm 0:9b334a45a8ff 1303 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 1304
bogdanm 0:9b334a45a8ff 1305 /* Enable the Main Ouput */
bogdanm 0:9b334a45a8ff 1306 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1307
bogdanm 0:9b334a45a8ff 1308 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 1309 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1310
bogdanm 0:9b334a45a8ff 1311 /* Return function status */
bogdanm 0:9b334a45a8ff 1312 return HAL_OK;
bogdanm 0:9b334a45a8ff 1313 }
bogdanm 0:9b334a45a8ff 1314
bogdanm 0:9b334a45a8ff 1315 /**
bogdanm 0:9b334a45a8ff 1316 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
bogdanm 0:9b334a45a8ff 1317 * output
bogdanm 0:9b334a45a8ff 1318 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1319 * @param Channel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 1320 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1321 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1322 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1323 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1324 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1325 * @retval HAL status
bogdanm 0:9b334a45a8ff 1326 */
bogdanm 0:9b334a45a8ff 1327 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1328 {
bogdanm 0:9b334a45a8ff 1329 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1330 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1331
bogdanm 0:9b334a45a8ff 1332 switch (Channel)
bogdanm 0:9b334a45a8ff 1333 {
bogdanm 0:9b334a45a8ff 1334 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1335 {
bogdanm 0:9b334a45a8ff 1336 /* Disable the TIM Capture/Compare 1 DMA request */
bogdanm 0:9b334a45a8ff 1337 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 1338 }
bogdanm 0:9b334a45a8ff 1339 break;
bogdanm 0:9b334a45a8ff 1340
bogdanm 0:9b334a45a8ff 1341 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1342 {
bogdanm 0:9b334a45a8ff 1343 /* Disable the TIM Capture/Compare 2 DMA request */
bogdanm 0:9b334a45a8ff 1344 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 1345 }
bogdanm 0:9b334a45a8ff 1346 break;
bogdanm 0:9b334a45a8ff 1347
bogdanm 0:9b334a45a8ff 1348 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1349 {
bogdanm 0:9b334a45a8ff 1350 /* Disable the TIM Capture/Compare 3 DMA request */
bogdanm 0:9b334a45a8ff 1351 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 1352 }
bogdanm 0:9b334a45a8ff 1353 break;
bogdanm 0:9b334a45a8ff 1354
bogdanm 0:9b334a45a8ff 1355 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1356 {
bogdanm 0:9b334a45a8ff 1357 /* Disable the TIM Capture/Compare 4 DMA request */
bogdanm 0:9b334a45a8ff 1358 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 1359 }
bogdanm 0:9b334a45a8ff 1360 break;
bogdanm 0:9b334a45a8ff 1361
bogdanm 0:9b334a45a8ff 1362 default:
bogdanm 0:9b334a45a8ff 1363 break;
bogdanm 0:9b334a45a8ff 1364 }
bogdanm 0:9b334a45a8ff 1365
bogdanm 0:9b334a45a8ff 1366 /* Disable the complementary PWM output */
bogdanm 0:9b334a45a8ff 1367 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 1368
bogdanm 0:9b334a45a8ff 1369 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 1370 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1371
bogdanm 0:9b334a45a8ff 1372 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1373 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1374
bogdanm 0:9b334a45a8ff 1375 /* Change the htim state */
bogdanm 0:9b334a45a8ff 1376 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 1377
bogdanm 0:9b334a45a8ff 1378 /* Return function status */
bogdanm 0:9b334a45a8ff 1379 return HAL_OK;
bogdanm 0:9b334a45a8ff 1380 }
bogdanm 0:9b334a45a8ff 1381
bogdanm 0:9b334a45a8ff 1382 /**
bogdanm 0:9b334a45a8ff 1383 * @}
bogdanm 0:9b334a45a8ff 1384 */
bogdanm 0:9b334a45a8ff 1385
bogdanm 0:9b334a45a8ff 1386 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
bogdanm 0:9b334a45a8ff 1387 * @brief Timer Complementary One Pulse functions
bogdanm 0:9b334a45a8ff 1388 *
bogdanm 0:9b334a45a8ff 1389 @verbatim
bogdanm 0:9b334a45a8ff 1390 ==============================================================================
bogdanm 0:9b334a45a8ff 1391 ##### Timer Complementary One Pulse functions #####
bogdanm 0:9b334a45a8ff 1392 ==============================================================================
bogdanm 0:9b334a45a8ff 1393 [..]
bogdanm 0:9b334a45a8ff 1394 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 1395 (+) Start the Complementary One Pulse generation.
bogdanm 0:9b334a45a8ff 1396 (+) Stop the Complementary One Pulse.
bogdanm 0:9b334a45a8ff 1397 (+) Start the Complementary One Pulse and enable interrupts.
bogdanm 0:9b334a45a8ff 1398 (+) Stop the Complementary One Pulse and disable interrupts.
bogdanm 0:9b334a45a8ff 1399
bogdanm 0:9b334a45a8ff 1400 @endverbatim
bogdanm 0:9b334a45a8ff 1401 * @{
bogdanm 0:9b334a45a8ff 1402 */
bogdanm 0:9b334a45a8ff 1403
bogdanm 0:9b334a45a8ff 1404 /**
bogdanm 0:9b334a45a8ff 1405 * @brief Starts the TIM One Pulse signal generation on the complementary
bogdanm 0:9b334a45a8ff 1406 * output.
bogdanm 0:9b334a45a8ff 1407 * @param htim : TIM One Pulse handle
bogdanm 0:9b334a45a8ff 1408 * @param OutputChannel : TIM Channel to be enabled
bogdanm 0:9b334a45a8ff 1409 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1410 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1411 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1412 * @retval HAL status
bogdanm 0:9b334a45a8ff 1413 */
bogdanm 0:9b334a45a8ff 1414 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm 0:9b334a45a8ff 1415 {
bogdanm 0:9b334a45a8ff 1416 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1417 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm 0:9b334a45a8ff 1418
bogdanm 0:9b334a45a8ff 1419 /* Enable the complementary One Pulse output */
bogdanm 0:9b334a45a8ff 1420 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 1421
bogdanm 0:9b334a45a8ff 1422 /* Enable the Main Ouput */
bogdanm 0:9b334a45a8ff 1423 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1424
bogdanm 0:9b334a45a8ff 1425 /* Return function status */
bogdanm 0:9b334a45a8ff 1426 return HAL_OK;
bogdanm 0:9b334a45a8ff 1427 }
bogdanm 0:9b334a45a8ff 1428
bogdanm 0:9b334a45a8ff 1429 /**
bogdanm 0:9b334a45a8ff 1430 * @brief Stops the TIM One Pulse signal generation on the complementary
bogdanm 0:9b334a45a8ff 1431 * output.
bogdanm 0:9b334a45a8ff 1432 * @param htim : TIM One Pulse handle
bogdanm 0:9b334a45a8ff 1433 * @param OutputChannel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 1434 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1435 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1436 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1437 * @retval HAL status
bogdanm 0:9b334a45a8ff 1438 */
bogdanm 0:9b334a45a8ff 1439 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm 0:9b334a45a8ff 1440 {
bogdanm 0:9b334a45a8ff 1441
bogdanm 0:9b334a45a8ff 1442 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1443 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm 0:9b334a45a8ff 1444
bogdanm 0:9b334a45a8ff 1445 /* Disable the complementary One Pulse output */
bogdanm 0:9b334a45a8ff 1446 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 1447
bogdanm 0:9b334a45a8ff 1448 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 1449 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1450
bogdanm 0:9b334a45a8ff 1451 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1452 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1453
bogdanm 0:9b334a45a8ff 1454 /* Return function status */
bogdanm 0:9b334a45a8ff 1455 return HAL_OK;
bogdanm 0:9b334a45a8ff 1456 }
bogdanm 0:9b334a45a8ff 1457
bogdanm 0:9b334a45a8ff 1458 /**
bogdanm 0:9b334a45a8ff 1459 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
bogdanm 0:9b334a45a8ff 1460 * complementary channel.
bogdanm 0:9b334a45a8ff 1461 * @param htim : TIM One Pulse handle
bogdanm 0:9b334a45a8ff 1462 * @param OutputChannel : TIM Channel to be enabled
bogdanm 0:9b334a45a8ff 1463 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1464 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1465 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1466 * @retval HAL status
bogdanm 0:9b334a45a8ff 1467 */
bogdanm 0:9b334a45a8ff 1468 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm 0:9b334a45a8ff 1469 {
bogdanm 0:9b334a45a8ff 1470 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1471 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm 0:9b334a45a8ff 1472
bogdanm 0:9b334a45a8ff 1473 /* Enable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 1474 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 1475
bogdanm 0:9b334a45a8ff 1476 /* Enable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 1477 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 1478
bogdanm 0:9b334a45a8ff 1479 /* Enable the complementary One Pulse output */
bogdanm 0:9b334a45a8ff 1480 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
bogdanm 0:9b334a45a8ff 1481
bogdanm 0:9b334a45a8ff 1482 /* Enable the Main Ouput */
bogdanm 0:9b334a45a8ff 1483 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1484
bogdanm 0:9b334a45a8ff 1485 /* Return function status */
bogdanm 0:9b334a45a8ff 1486 return HAL_OK;
bogdanm 0:9b334a45a8ff 1487 }
bogdanm 0:9b334a45a8ff 1488
bogdanm 0:9b334a45a8ff 1489 /**
bogdanm 0:9b334a45a8ff 1490 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
bogdanm 0:9b334a45a8ff 1491 * complementary channel.
bogdanm 0:9b334a45a8ff 1492 * @param htim : TIM One Pulse handle
bogdanm 0:9b334a45a8ff 1493 * @param OutputChannel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 1494 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1495 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1496 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1497 * @retval HAL status
bogdanm 0:9b334a45a8ff 1498 */
bogdanm 0:9b334a45a8ff 1499 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm 0:9b334a45a8ff 1500 {
bogdanm 0:9b334a45a8ff 1501 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1502 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm 0:9b334a45a8ff 1503
bogdanm 0:9b334a45a8ff 1504 /* Disable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 1505 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 1506
bogdanm 0:9b334a45a8ff 1507 /* Disable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 1508 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 1509
bogdanm 0:9b334a45a8ff 1510 /* Disable the complementary One Pulse output */
bogdanm 0:9b334a45a8ff 1511 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
bogdanm 0:9b334a45a8ff 1512
bogdanm 0:9b334a45a8ff 1513 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 1514 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1515
bogdanm 0:9b334a45a8ff 1516 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1517 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1518
bogdanm 0:9b334a45a8ff 1519 /* Return function status */
bogdanm 0:9b334a45a8ff 1520 return HAL_OK;
bogdanm 0:9b334a45a8ff 1521 }
bogdanm 0:9b334a45a8ff 1522
bogdanm 0:9b334a45a8ff 1523 /**
bogdanm 0:9b334a45a8ff 1524 * @}
bogdanm 0:9b334a45a8ff 1525 */
bogdanm 0:9b334a45a8ff 1526
bogdanm 0:9b334a45a8ff 1527 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 1528 * @brief Peripheral Control functions
bogdanm 0:9b334a45a8ff 1529 *
bogdanm 0:9b334a45a8ff 1530 @verbatim
bogdanm 0:9b334a45a8ff 1531 ==============================================================================
bogdanm 0:9b334a45a8ff 1532 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 1533 ==============================================================================
bogdanm 0:9b334a45a8ff 1534 [..]
bogdanm 0:9b334a45a8ff 1535 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 1536 (+) Configure the commutation event in case of use of the Hall sensor interface.
bogdanm 0:9b334a45a8ff 1537 (+) Configure Output channels for OC and PWM mode.
bogdanm 0:9b334a45a8ff 1538
bogdanm 0:9b334a45a8ff 1539 (+) Configure Complementary channels, break features and dead time.
bogdanm 0:9b334a45a8ff 1540 (+) Configure Master synchronization.
bogdanm 0:9b334a45a8ff 1541 (+) Configure timer remapping capabilities.
bogdanm 0:9b334a45a8ff 1542 (+) Enable or disable channel grouping
bogdanm 0:9b334a45a8ff 1543
bogdanm 0:9b334a45a8ff 1544 @endverbatim
bogdanm 0:9b334a45a8ff 1545 * @{
bogdanm 0:9b334a45a8ff 1546 */
bogdanm 0:9b334a45a8ff 1547
bogdanm 0:9b334a45a8ff 1548 /**
bogdanm 0:9b334a45a8ff 1549 * @brief Configure the TIM commutation event sequence.
bogdanm 0:9b334a45a8ff 1550 * @note This function is mandatory to use the commutation event in order to
bogdanm 0:9b334a45a8ff 1551 * update the configuration at each commutation detection on the TRGI input of the Timer,
bogdanm 0:9b334a45a8ff 1552 * the typical use of this feature is with the use of another Timer(interface Timer)
bogdanm 0:9b334a45a8ff 1553 * configured in Hall sensor interface, this interface Timer will generate the
bogdanm 0:9b334a45a8ff 1554 * commutation at its TRGO output (connected to Timer used in this function) each time
bogdanm 0:9b334a45a8ff 1555 * the TI1 of the Interface Timer detect a commutation at its input TI1.
bogdanm 0:9b334a45a8ff 1556 * @param htim: TIM handle
bogdanm 0:9b334a45a8ff 1557 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
bogdanm 0:9b334a45a8ff 1558 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1559 * @arg TIM_TS_ITR0: Internal trigger 0 selected
bogdanm 0:9b334a45a8ff 1560 * @arg TIM_TS_ITR1: Internal trigger 1 selected
bogdanm 0:9b334a45a8ff 1561 * @arg TIM_TS_ITR2: Internal trigger 2 selected
bogdanm 0:9b334a45a8ff 1562 * @arg TIM_TS_ITR3: Internal trigger 3 selected
bogdanm 0:9b334a45a8ff 1563 * @arg TIM_TS_NONE: No trigger is needed
bogdanm 0:9b334a45a8ff 1564 * @param CommutationSource : the Commutation Event source
bogdanm 0:9b334a45a8ff 1565 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1566 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
bogdanm 0:9b334a45a8ff 1567 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
bogdanm 0:9b334a45a8ff 1568 * @retval HAL status
bogdanm 0:9b334a45a8ff 1569 */
bogdanm 0:9b334a45a8ff 1570 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
bogdanm 0:9b334a45a8ff 1571 {
bogdanm 0:9b334a45a8ff 1572 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1573 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1574 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
bogdanm 0:9b334a45a8ff 1575
bogdanm 0:9b334a45a8ff 1576 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 1577
bogdanm 0:9b334a45a8ff 1578 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
bogdanm 0:9b334a45a8ff 1579 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
bogdanm 0:9b334a45a8ff 1580 {
bogdanm 0:9b334a45a8ff 1581 /* Select the Input trigger */
bogdanm 0:9b334a45a8ff 1582 htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm 0:9b334a45a8ff 1583 htim->Instance->SMCR |= InputTrigger;
bogdanm 0:9b334a45a8ff 1584 }
bogdanm 0:9b334a45a8ff 1585
bogdanm 0:9b334a45a8ff 1586 /* Select the Capture Compare preload feature */
bogdanm 0:9b334a45a8ff 1587 htim->Instance->CR2 |= TIM_CR2_CCPC;
bogdanm 0:9b334a45a8ff 1588 /* Select the Commutation event source */
bogdanm 0:9b334a45a8ff 1589 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
bogdanm 0:9b334a45a8ff 1590 htim->Instance->CR2 |= CommutationSource;
bogdanm 0:9b334a45a8ff 1591
bogdanm 0:9b334a45a8ff 1592 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 1593
bogdanm 0:9b334a45a8ff 1594 return HAL_OK;
bogdanm 0:9b334a45a8ff 1595 }
bogdanm 0:9b334a45a8ff 1596
bogdanm 0:9b334a45a8ff 1597 /**
bogdanm 0:9b334a45a8ff 1598 * @brief Configure the TIM commutation event sequence with interrupt.
bogdanm 0:9b334a45a8ff 1599 * @note This function is mandatory to use the commutation event in order to
bogdanm 0:9b334a45a8ff 1600 * update the configuration at each commutation detection on the TRGI input of the Timer,
bogdanm 0:9b334a45a8ff 1601 * the typical use of this feature is with the use of another Timer(interface Timer)
bogdanm 0:9b334a45a8ff 1602 * configured in Hall sensor interface, this interface Timer will generate the
bogdanm 0:9b334a45a8ff 1603 * commutation at its TRGO output (connected to Timer used in this function) each time
bogdanm 0:9b334a45a8ff 1604 * the TI1 of the Interface Timer detect a commutation at its input TI1.
bogdanm 0:9b334a45a8ff 1605 * @param htim: TIM handle
bogdanm 0:9b334a45a8ff 1606 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
bogdanm 0:9b334a45a8ff 1607 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1608 * @arg TIM_TS_ITR0: Internal trigger 0 selected
bogdanm 0:9b334a45a8ff 1609 * @arg TIM_TS_ITR1: Internal trigger 1 selected
bogdanm 0:9b334a45a8ff 1610 * @arg TIM_TS_ITR2: Internal trigger 2 selected
bogdanm 0:9b334a45a8ff 1611 * @arg TIM_TS_ITR3: Internal trigger 3 selected
bogdanm 0:9b334a45a8ff 1612 * @arg TIM_TS_NONE: No trigger is needed
bogdanm 0:9b334a45a8ff 1613 * @param CommutationSource : the Commutation Event source
bogdanm 0:9b334a45a8ff 1614 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1615 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
bogdanm 0:9b334a45a8ff 1616 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
bogdanm 0:9b334a45a8ff 1617 * @retval HAL status
bogdanm 0:9b334a45a8ff 1618 */
bogdanm 0:9b334a45a8ff 1619 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
bogdanm 0:9b334a45a8ff 1620 {
bogdanm 0:9b334a45a8ff 1621 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1622 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1623 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
bogdanm 0:9b334a45a8ff 1624
bogdanm 0:9b334a45a8ff 1625 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 1626
bogdanm 0:9b334a45a8ff 1627 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
bogdanm 0:9b334a45a8ff 1628 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
bogdanm 0:9b334a45a8ff 1629 {
bogdanm 0:9b334a45a8ff 1630 /* Select the Input trigger */
bogdanm 0:9b334a45a8ff 1631 htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm 0:9b334a45a8ff 1632 htim->Instance->SMCR |= InputTrigger;
bogdanm 0:9b334a45a8ff 1633 }
bogdanm 0:9b334a45a8ff 1634
bogdanm 0:9b334a45a8ff 1635 /* Select the Capture Compare preload feature */
bogdanm 0:9b334a45a8ff 1636 htim->Instance->CR2 |= TIM_CR2_CCPC;
bogdanm 0:9b334a45a8ff 1637 /* Select the Commutation event source */
bogdanm 0:9b334a45a8ff 1638 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
bogdanm 0:9b334a45a8ff 1639 htim->Instance->CR2 |= CommutationSource;
bogdanm 0:9b334a45a8ff 1640
bogdanm 0:9b334a45a8ff 1641 /* Enable the Commutation Interrupt Request */
bogdanm 0:9b334a45a8ff 1642 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
bogdanm 0:9b334a45a8ff 1643
bogdanm 0:9b334a45a8ff 1644 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 1645
bogdanm 0:9b334a45a8ff 1646 return HAL_OK;
bogdanm 0:9b334a45a8ff 1647 }
bogdanm 0:9b334a45a8ff 1648
bogdanm 0:9b334a45a8ff 1649 /**
bogdanm 0:9b334a45a8ff 1650 * @brief Configure the TIM commutation event sequence with DMA.
bogdanm 0:9b334a45a8ff 1651 * @note This function is mandatory to use the commutation event in order to
bogdanm 0:9b334a45a8ff 1652 * update the configuration at each commutation detection on the TRGI input of the Timer,
bogdanm 0:9b334a45a8ff 1653 * the typical use of this feature is with the use of another Timer(interface Timer)
bogdanm 0:9b334a45a8ff 1654 * configured in Hall sensor interface, this interface Timer will generate the
bogdanm 0:9b334a45a8ff 1655 * commutation at its TRGO output (connected to Timer used in this function) each time
bogdanm 0:9b334a45a8ff 1656 * the TI1 of the Interface Timer detect a commutation at its input TI1.
bogdanm 0:9b334a45a8ff 1657 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
bogdanm 0:9b334a45a8ff 1658 * @param htim: TIM handle
bogdanm 0:9b334a45a8ff 1659 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
bogdanm 0:9b334a45a8ff 1660 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1661 * @arg TIM_TS_ITR0: Internal trigger 0 selected
bogdanm 0:9b334a45a8ff 1662 * @arg TIM_TS_ITR1: Internal trigger 1 selected
bogdanm 0:9b334a45a8ff 1663 * @arg TIM_TS_ITR2: Internal trigger 2 selected
bogdanm 0:9b334a45a8ff 1664 * @arg TIM_TS_ITR3: Internal trigger 3 selected
bogdanm 0:9b334a45a8ff 1665 * @arg TIM_TS_NONE: No trigger is needed
bogdanm 0:9b334a45a8ff 1666 * @param CommutationSource : the Commutation Event source
bogdanm 0:9b334a45a8ff 1667 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1668 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
bogdanm 0:9b334a45a8ff 1669 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
bogdanm 0:9b334a45a8ff 1670 * @retval HAL status
bogdanm 0:9b334a45a8ff 1671 */
bogdanm 0:9b334a45a8ff 1672 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
bogdanm 0:9b334a45a8ff 1673 {
bogdanm 0:9b334a45a8ff 1674 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1675 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1676 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
bogdanm 0:9b334a45a8ff 1677
bogdanm 0:9b334a45a8ff 1678 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 1679
bogdanm 0:9b334a45a8ff 1680 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
bogdanm 0:9b334a45a8ff 1681 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
bogdanm 0:9b334a45a8ff 1682 {
bogdanm 0:9b334a45a8ff 1683 /* Select the Input trigger */
bogdanm 0:9b334a45a8ff 1684 htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm 0:9b334a45a8ff 1685 htim->Instance->SMCR |= InputTrigger;
bogdanm 0:9b334a45a8ff 1686 }
bogdanm 0:9b334a45a8ff 1687
bogdanm 0:9b334a45a8ff 1688 /* Select the Capture Compare preload feature */
bogdanm 0:9b334a45a8ff 1689 htim->Instance->CR2 |= TIM_CR2_CCPC;
bogdanm 0:9b334a45a8ff 1690 /* Select the Commutation event source */
bogdanm 0:9b334a45a8ff 1691 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
bogdanm 0:9b334a45a8ff 1692 htim->Instance->CR2 |= CommutationSource;
bogdanm 0:9b334a45a8ff 1693
bogdanm 0:9b334a45a8ff 1694 /* Enable the Commutation DMA Request */
bogdanm 0:9b334a45a8ff 1695 /* Set the DMA Commutation Callback */
bogdanm 0:9b334a45a8ff 1696 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
bogdanm 0:9b334a45a8ff 1697 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1698 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
bogdanm 0:9b334a45a8ff 1699
bogdanm 0:9b334a45a8ff 1700 /* Enable the Commutation DMA Request */
bogdanm 0:9b334a45a8ff 1701 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
bogdanm 0:9b334a45a8ff 1702
bogdanm 0:9b334a45a8ff 1703 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 1704
bogdanm 0:9b334a45a8ff 1705 return HAL_OK;
bogdanm 0:9b334a45a8ff 1706 }
bogdanm 0:9b334a45a8ff 1707
bogdanm 0:9b334a45a8ff 1708 /**
bogdanm 0:9b334a45a8ff 1709 * @brief Initializes the TIM Output Compare Channels according to the specified
bogdanm 0:9b334a45a8ff 1710 * parameters in the TIM_OC_InitTypeDef.
bogdanm 0:9b334a45a8ff 1711 * @param htim: TIM Output Compare handle
bogdanm 0:9b334a45a8ff 1712 * @param sConfig: TIM Output Compare configuration structure
bogdanm 0:9b334a45a8ff 1713 * @param Channel : TIM Channels to configure
bogdanm 0:9b334a45a8ff 1714 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1715 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1716 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1717 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1718 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1719 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm 0:9b334a45a8ff 1720 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm 0:9b334a45a8ff 1721 * @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected
bogdanm 0:9b334a45a8ff 1722 * @retval HAL status
bogdanm 0:9b334a45a8ff 1723 */
bogdanm 0:9b334a45a8ff 1724 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
bogdanm 0:9b334a45a8ff 1725 TIM_OC_InitTypeDef* sConfig,
bogdanm 0:9b334a45a8ff 1726 uint32_t Channel)
bogdanm 0:9b334a45a8ff 1727 {
bogdanm 0:9b334a45a8ff 1728 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1729 assert_param(IS_TIM_CHANNELS(Channel));
bogdanm 0:9b334a45a8ff 1730 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
bogdanm 0:9b334a45a8ff 1731 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm 0:9b334a45a8ff 1732 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
bogdanm 0:9b334a45a8ff 1733 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
bogdanm 0:9b334a45a8ff 1734 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
bogdanm 0:9b334a45a8ff 1735
bogdanm 0:9b334a45a8ff 1736 /* Check input state */
bogdanm 0:9b334a45a8ff 1737 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 1738
bogdanm 0:9b334a45a8ff 1739 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1740
bogdanm 0:9b334a45a8ff 1741 switch (Channel)
bogdanm 0:9b334a45a8ff 1742 {
bogdanm 0:9b334a45a8ff 1743 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1744 {
bogdanm 0:9b334a45a8ff 1745 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1746 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1747
bogdanm 0:9b334a45a8ff 1748 /* Configure the TIM Channel 1 in Output Compare */
bogdanm 0:9b334a45a8ff 1749 TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1750 }
bogdanm 0:9b334a45a8ff 1751 break;
bogdanm 0:9b334a45a8ff 1752
bogdanm 0:9b334a45a8ff 1753 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1754 {
bogdanm 0:9b334a45a8ff 1755 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1756 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1757
bogdanm 0:9b334a45a8ff 1758 /* Configure the TIM Channel 2 in Output Compare */
bogdanm 0:9b334a45a8ff 1759 TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1760 }
bogdanm 0:9b334a45a8ff 1761 break;
bogdanm 0:9b334a45a8ff 1762
bogdanm 0:9b334a45a8ff 1763 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1764 {
bogdanm 0:9b334a45a8ff 1765 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1766 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1767
bogdanm 0:9b334a45a8ff 1768 /* Configure the TIM Channel 3 in Output Compare */
bogdanm 0:9b334a45a8ff 1769 TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1770 }
bogdanm 0:9b334a45a8ff 1771 break;
bogdanm 0:9b334a45a8ff 1772
bogdanm 0:9b334a45a8ff 1773 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1774 {
bogdanm 0:9b334a45a8ff 1775 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1776 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1777
bogdanm 0:9b334a45a8ff 1778 /* Configure the TIM Channel 4 in Output Compare */
bogdanm 0:9b334a45a8ff 1779 TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1780 }
bogdanm 0:9b334a45a8ff 1781 break;
bogdanm 0:9b334a45a8ff 1782
bogdanm 0:9b334a45a8ff 1783 case TIM_CHANNEL_5:
bogdanm 0:9b334a45a8ff 1784 {
bogdanm 0:9b334a45a8ff 1785 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1786 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1787
bogdanm 0:9b334a45a8ff 1788 /* Configure the TIM Channel 5 in Output Compare */
bogdanm 0:9b334a45a8ff 1789 TIM_OC5_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1790 }
bogdanm 0:9b334a45a8ff 1791 break;
bogdanm 0:9b334a45a8ff 1792
bogdanm 0:9b334a45a8ff 1793 case TIM_CHANNEL_6:
bogdanm 0:9b334a45a8ff 1794 {
bogdanm 0:9b334a45a8ff 1795 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1796 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1797
bogdanm 0:9b334a45a8ff 1798 /* Configure the TIM Channel 6 in Output Compare */
bogdanm 0:9b334a45a8ff 1799 TIM_OC6_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1800 }
bogdanm 0:9b334a45a8ff 1801 break;
bogdanm 0:9b334a45a8ff 1802
bogdanm 0:9b334a45a8ff 1803 default:
bogdanm 0:9b334a45a8ff 1804 break;
bogdanm 0:9b334a45a8ff 1805 }
bogdanm 0:9b334a45a8ff 1806
bogdanm 0:9b334a45a8ff 1807 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 1808
bogdanm 0:9b334a45a8ff 1809 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 1810
bogdanm 0:9b334a45a8ff 1811 return HAL_OK;
bogdanm 0:9b334a45a8ff 1812 }
bogdanm 0:9b334a45a8ff 1813
bogdanm 0:9b334a45a8ff 1814 /**
bogdanm 0:9b334a45a8ff 1815 * @brief Initializes the TIM PWM channels according to the specified
bogdanm 0:9b334a45a8ff 1816 * parameters in the TIM_OC_InitTypeDef.
bogdanm 0:9b334a45a8ff 1817 * @param htim: TIM PWM handle
bogdanm 0:9b334a45a8ff 1818 * @param sConfig: TIM PWM configuration structure
bogdanm 0:9b334a45a8ff 1819 * @param Channel : TIM Channels to be configured
bogdanm 0:9b334a45a8ff 1820 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1821 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1822 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1823 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1824 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1825 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm 0:9b334a45a8ff 1826 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm 0:9b334a45a8ff 1827 * @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected
bogdanm 0:9b334a45a8ff 1828 * @retval HAL status
bogdanm 0:9b334a45a8ff 1829 */
bogdanm 0:9b334a45a8ff 1830 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
bogdanm 0:9b334a45a8ff 1831 TIM_OC_InitTypeDef* sConfig,
bogdanm 0:9b334a45a8ff 1832 uint32_t Channel)
bogdanm 0:9b334a45a8ff 1833 {
bogdanm 0:9b334a45a8ff 1834 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1835 assert_param(IS_TIM_CHANNELS(Channel));
bogdanm 0:9b334a45a8ff 1836 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
bogdanm 0:9b334a45a8ff 1837 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm 0:9b334a45a8ff 1838 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
bogdanm 0:9b334a45a8ff 1839 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
bogdanm 0:9b334a45a8ff 1840 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
bogdanm 0:9b334a45a8ff 1841 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
bogdanm 0:9b334a45a8ff 1842
bogdanm 0:9b334a45a8ff 1843 /* Check input state */
bogdanm 0:9b334a45a8ff 1844 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 1845
bogdanm 0:9b334a45a8ff 1846 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1847
bogdanm 0:9b334a45a8ff 1848 switch (Channel)
bogdanm 0:9b334a45a8ff 1849 {
bogdanm 0:9b334a45a8ff 1850 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1851 {
bogdanm 0:9b334a45a8ff 1852 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1853 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1854
bogdanm 0:9b334a45a8ff 1855 /* Configure the Channel 1 in PWM mode */
bogdanm 0:9b334a45a8ff 1856 TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1857
bogdanm 0:9b334a45a8ff 1858 /* Set the Preload enable bit for channel1 */
bogdanm 0:9b334a45a8ff 1859 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
bogdanm 0:9b334a45a8ff 1860
bogdanm 0:9b334a45a8ff 1861 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 1862 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
bogdanm 0:9b334a45a8ff 1863 htim->Instance->CCMR1 |= sConfig->OCFastMode;
bogdanm 0:9b334a45a8ff 1864 }
bogdanm 0:9b334a45a8ff 1865 break;
bogdanm 0:9b334a45a8ff 1866
bogdanm 0:9b334a45a8ff 1867 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1868 {
bogdanm 0:9b334a45a8ff 1869 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1870 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1871
bogdanm 0:9b334a45a8ff 1872 /* Configure the Channel 2 in PWM mode */
bogdanm 0:9b334a45a8ff 1873 TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1874
bogdanm 0:9b334a45a8ff 1875 /* Set the Preload enable bit for channel2 */
bogdanm 0:9b334a45a8ff 1876 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
bogdanm 0:9b334a45a8ff 1877
bogdanm 0:9b334a45a8ff 1878 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 1879 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
bogdanm 0:9b334a45a8ff 1880 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
bogdanm 0:9b334a45a8ff 1881 }
bogdanm 0:9b334a45a8ff 1882 break;
bogdanm 0:9b334a45a8ff 1883
bogdanm 0:9b334a45a8ff 1884 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1885 {
bogdanm 0:9b334a45a8ff 1886 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1887 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1888
bogdanm 0:9b334a45a8ff 1889 /* Configure the Channel 3 in PWM mode */
bogdanm 0:9b334a45a8ff 1890 TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1891
bogdanm 0:9b334a45a8ff 1892 /* Set the Preload enable bit for channel3 */
bogdanm 0:9b334a45a8ff 1893 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
bogdanm 0:9b334a45a8ff 1894
bogdanm 0:9b334a45a8ff 1895 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 1896 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
bogdanm 0:9b334a45a8ff 1897 htim->Instance->CCMR2 |= sConfig->OCFastMode;
bogdanm 0:9b334a45a8ff 1898 }
bogdanm 0:9b334a45a8ff 1899 break;
bogdanm 0:9b334a45a8ff 1900
bogdanm 0:9b334a45a8ff 1901 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1902 {
bogdanm 0:9b334a45a8ff 1903 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1904 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1905
bogdanm 0:9b334a45a8ff 1906 /* Configure the Channel 4 in PWM mode */
bogdanm 0:9b334a45a8ff 1907 TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1908
bogdanm 0:9b334a45a8ff 1909 /* Set the Preload enable bit for channel4 */
bogdanm 0:9b334a45a8ff 1910 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
bogdanm 0:9b334a45a8ff 1911
bogdanm 0:9b334a45a8ff 1912 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 1913 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
bogdanm 0:9b334a45a8ff 1914 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
bogdanm 0:9b334a45a8ff 1915 }
bogdanm 0:9b334a45a8ff 1916 break;
bogdanm 0:9b334a45a8ff 1917
bogdanm 0:9b334a45a8ff 1918 case TIM_CHANNEL_5:
bogdanm 0:9b334a45a8ff 1919 {
bogdanm 0:9b334a45a8ff 1920 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1921 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1922
bogdanm 0:9b334a45a8ff 1923 /* Configure the Channel 5 in PWM mode */
bogdanm 0:9b334a45a8ff 1924 TIM_OC5_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1925
bogdanm 0:9b334a45a8ff 1926 /* Set the Preload enable bit for channel5*/
bogdanm 0:9b334a45a8ff 1927 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
bogdanm 0:9b334a45a8ff 1928
bogdanm 0:9b334a45a8ff 1929 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 1930 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
bogdanm 0:9b334a45a8ff 1931 htim->Instance->CCMR3 |= sConfig->OCFastMode;
bogdanm 0:9b334a45a8ff 1932 }
bogdanm 0:9b334a45a8ff 1933 break;
bogdanm 0:9b334a45a8ff 1934
bogdanm 0:9b334a45a8ff 1935 case TIM_CHANNEL_6:
bogdanm 0:9b334a45a8ff 1936 {
bogdanm 0:9b334a45a8ff 1937 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1938 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1939
bogdanm 0:9b334a45a8ff 1940 /* Configure the Channel 5 in PWM mode */
bogdanm 0:9b334a45a8ff 1941 TIM_OC6_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 1942
bogdanm 0:9b334a45a8ff 1943 /* Set the Preload enable bit for channel6 */
bogdanm 0:9b334a45a8ff 1944 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
bogdanm 0:9b334a45a8ff 1945
bogdanm 0:9b334a45a8ff 1946 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 1947 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
bogdanm 0:9b334a45a8ff 1948 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
bogdanm 0:9b334a45a8ff 1949 }
bogdanm 0:9b334a45a8ff 1950 break;
bogdanm 0:9b334a45a8ff 1951
bogdanm 0:9b334a45a8ff 1952 default:
bogdanm 0:9b334a45a8ff 1953 break;
bogdanm 0:9b334a45a8ff 1954 }
bogdanm 0:9b334a45a8ff 1955
bogdanm 0:9b334a45a8ff 1956 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 1957
bogdanm 0:9b334a45a8ff 1958 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 1959
bogdanm 0:9b334a45a8ff 1960 return HAL_OK;
bogdanm 0:9b334a45a8ff 1961 }
bogdanm 0:9b334a45a8ff 1962
bogdanm 0:9b334a45a8ff 1963 /**
bogdanm 0:9b334a45a8ff 1964 * @brief Configures the OCRef clear feature
bogdanm 0:9b334a45a8ff 1965 * @param htim: TIM handle
bogdanm 0:9b334a45a8ff 1966 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
bogdanm 0:9b334a45a8ff 1967 * contains the OCREF clear feature and parameters for the TIM peripheral.
bogdanm 0:9b334a45a8ff 1968 * @param Channel: specifies the TIM Channel
bogdanm 0:9b334a45a8ff 1969 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1970 * @arg TIM_Channel_1: TIM Channel 1
bogdanm 0:9b334a45a8ff 1971 * @arg TIM_Channel_2: TIM Channel 2
bogdanm 0:9b334a45a8ff 1972 * @arg TIM_Channel_3: TIM Channel 3
bogdanm 0:9b334a45a8ff 1973 * @arg TIM_Channel_4: TIM Channel 4
bogdanm 0:9b334a45a8ff 1974 * @arg TIM_Channel_5: TIM Channel 5
bogdanm 0:9b334a45a8ff 1975 * @arg TIM_Channel_6: TIM Channel 6
bogdanm 0:9b334a45a8ff 1976 * @retval None
bogdanm 0:9b334a45a8ff 1977 */
bogdanm 0:9b334a45a8ff 1978 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
bogdanm 0:9b334a45a8ff 1979 TIM_ClearInputConfigTypeDef *sClearInputConfig,
bogdanm 0:9b334a45a8ff 1980 uint32_t Channel)
bogdanm 0:9b334a45a8ff 1981 {
bogdanm 0:9b334a45a8ff 1982 uint32_t tmpsmcr = 0;
bogdanm 0:9b334a45a8ff 1983
bogdanm 0:9b334a45a8ff 1984 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1985 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1986 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
bogdanm 0:9b334a45a8ff 1987
bogdanm 0:9b334a45a8ff 1988 /* Check input state */
bogdanm 0:9b334a45a8ff 1989 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 1990
bogdanm 0:9b334a45a8ff 1991 switch (sClearInputConfig->ClearInputSource)
bogdanm 0:9b334a45a8ff 1992 {
bogdanm 0:9b334a45a8ff 1993 case TIM_CLEARINPUTSOURCE_NONE:
bogdanm 0:9b334a45a8ff 1994 {
bogdanm 0:9b334a45a8ff 1995 /* Get the TIMx SMCR register value */
bogdanm 0:9b334a45a8ff 1996 tmpsmcr = htim->Instance->SMCR;
bogdanm 0:9b334a45a8ff 1997
bogdanm 0:9b334a45a8ff 1998 /* Clear the OCREF clear selection bit */
bogdanm 0:9b334a45a8ff 1999 tmpsmcr &= ~TIM_SMCR_OCCS;
bogdanm 0:9b334a45a8ff 2000
bogdanm 0:9b334a45a8ff 2001 /* Clear the ETR Bits */
bogdanm 0:9b334a45a8ff 2002 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
bogdanm 0:9b334a45a8ff 2003
bogdanm 0:9b334a45a8ff 2004 /* Set TIMx_SMCR */
bogdanm 0:9b334a45a8ff 2005 htim->Instance->SMCR = tmpsmcr;
bogdanm 0:9b334a45a8ff 2006 }
bogdanm 0:9b334a45a8ff 2007 break;
bogdanm 0:9b334a45a8ff 2008
bogdanm 0:9b334a45a8ff 2009 case TIM_CLEARINPUTSOURCE_OCREFCLR:
bogdanm 0:9b334a45a8ff 2010 {
bogdanm 0:9b334a45a8ff 2011 /* Clear the OCREF clear selection bit */
bogdanm 0:9b334a45a8ff 2012 htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
bogdanm 0:9b334a45a8ff 2013 }
bogdanm 0:9b334a45a8ff 2014 break;
bogdanm 0:9b334a45a8ff 2015
bogdanm 0:9b334a45a8ff 2016 case TIM_CLEARINPUTSOURCE_ETR:
bogdanm 0:9b334a45a8ff 2017 {
bogdanm 0:9b334a45a8ff 2018 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2019 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
bogdanm 0:9b334a45a8ff 2020 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
bogdanm 0:9b334a45a8ff 2021 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
bogdanm 0:9b334a45a8ff 2022
bogdanm 0:9b334a45a8ff 2023 TIM_ETR_SetConfig(htim->Instance,
bogdanm 0:9b334a45a8ff 2024 sClearInputConfig->ClearInputPrescaler,
bogdanm 0:9b334a45a8ff 2025 sClearInputConfig->ClearInputPolarity,
bogdanm 0:9b334a45a8ff 2026 sClearInputConfig->ClearInputFilter);
bogdanm 0:9b334a45a8ff 2027
bogdanm 0:9b334a45a8ff 2028 /* Set the OCREF clear selection bit */
bogdanm 0:9b334a45a8ff 2029 htim->Instance->SMCR |= TIM_SMCR_OCCS;
bogdanm 0:9b334a45a8ff 2030 }
bogdanm 0:9b334a45a8ff 2031 break;
bogdanm 0:9b334a45a8ff 2032
bogdanm 0:9b334a45a8ff 2033 default:
bogdanm 0:9b334a45a8ff 2034 break;
bogdanm 0:9b334a45a8ff 2035 }
bogdanm 0:9b334a45a8ff 2036
bogdanm 0:9b334a45a8ff 2037 switch (Channel)
bogdanm 0:9b334a45a8ff 2038 {
bogdanm 0:9b334a45a8ff 2039 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 2040 {
bogdanm 0:9b334a45a8ff 2041 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 2042 {
bogdanm 0:9b334a45a8ff 2043 /* Enable the OCREF clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 2044 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
bogdanm 0:9b334a45a8ff 2045 }
bogdanm 0:9b334a45a8ff 2046 else
bogdanm 0:9b334a45a8ff 2047 {
bogdanm 0:9b334a45a8ff 2048 /* Disable the OCREF clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 2049 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
bogdanm 0:9b334a45a8ff 2050 }
bogdanm 0:9b334a45a8ff 2051 }
bogdanm 0:9b334a45a8ff 2052 break;
bogdanm 0:9b334a45a8ff 2053 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 2054 {
bogdanm 0:9b334a45a8ff 2055 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 2056 {
bogdanm 0:9b334a45a8ff 2057 /* Enable the OCREF clear feature for Channel 2 */
bogdanm 0:9b334a45a8ff 2058 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
bogdanm 0:9b334a45a8ff 2059 }
bogdanm 0:9b334a45a8ff 2060 else
bogdanm 0:9b334a45a8ff 2061 {
bogdanm 0:9b334a45a8ff 2062 /* Disable the OCREF clear feature for Channel 2 */
bogdanm 0:9b334a45a8ff 2063 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
bogdanm 0:9b334a45a8ff 2064 }
bogdanm 0:9b334a45a8ff 2065 }
bogdanm 0:9b334a45a8ff 2066 break;
bogdanm 0:9b334a45a8ff 2067 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 2068 {
bogdanm 0:9b334a45a8ff 2069 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 2070 {
bogdanm 0:9b334a45a8ff 2071 /* Enable the OCREF clear feature for Channel 3 */
bogdanm 0:9b334a45a8ff 2072 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
bogdanm 0:9b334a45a8ff 2073 }
bogdanm 0:9b334a45a8ff 2074 else
bogdanm 0:9b334a45a8ff 2075 {
bogdanm 0:9b334a45a8ff 2076 /* Disable the OCREF clear feature for Channel 3 */
bogdanm 0:9b334a45a8ff 2077 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
bogdanm 0:9b334a45a8ff 2078 }
bogdanm 0:9b334a45a8ff 2079 }
bogdanm 0:9b334a45a8ff 2080 break;
bogdanm 0:9b334a45a8ff 2081 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 2082 {
bogdanm 0:9b334a45a8ff 2083 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 2084 {
bogdanm 0:9b334a45a8ff 2085 /* Enable the OCREF clear feature for Channel 4 */
bogdanm 0:9b334a45a8ff 2086 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
bogdanm 0:9b334a45a8ff 2087 }
bogdanm 0:9b334a45a8ff 2088 else
bogdanm 0:9b334a45a8ff 2089 {
bogdanm 0:9b334a45a8ff 2090 /* Disable the OCREF clear feature for Channel 4 */
bogdanm 0:9b334a45a8ff 2091 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
bogdanm 0:9b334a45a8ff 2092 }
bogdanm 0:9b334a45a8ff 2093 }
bogdanm 0:9b334a45a8ff 2094 break;
bogdanm 0:9b334a45a8ff 2095 case TIM_CHANNEL_5:
bogdanm 0:9b334a45a8ff 2096 {
bogdanm 0:9b334a45a8ff 2097 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 2098 {
bogdanm 0:9b334a45a8ff 2099 /* Enable the OCREF clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 2100 htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
bogdanm 0:9b334a45a8ff 2101 }
bogdanm 0:9b334a45a8ff 2102 else
bogdanm 0:9b334a45a8ff 2103 {
bogdanm 0:9b334a45a8ff 2104 /* Disable the OCREF clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 2105 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
bogdanm 0:9b334a45a8ff 2106 }
bogdanm 0:9b334a45a8ff 2107 }
bogdanm 0:9b334a45a8ff 2108 break;
bogdanm 0:9b334a45a8ff 2109 case TIM_CHANNEL_6:
bogdanm 0:9b334a45a8ff 2110 {
bogdanm 0:9b334a45a8ff 2111 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 2112 {
bogdanm 0:9b334a45a8ff 2113 /* Enable the OCREF clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 2114 htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
bogdanm 0:9b334a45a8ff 2115 }
bogdanm 0:9b334a45a8ff 2116 else
bogdanm 0:9b334a45a8ff 2117 {
bogdanm 0:9b334a45a8ff 2118 /* Disable the OCREF clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 2119 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
bogdanm 0:9b334a45a8ff 2120 }
bogdanm 0:9b334a45a8ff 2121 }
bogdanm 0:9b334a45a8ff 2122 break;
bogdanm 0:9b334a45a8ff 2123 default:
bogdanm 0:9b334a45a8ff 2124 break;
bogdanm 0:9b334a45a8ff 2125 }
bogdanm 0:9b334a45a8ff 2126
bogdanm 0:9b334a45a8ff 2127 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2128
bogdanm 0:9b334a45a8ff 2129 return HAL_OK;
bogdanm 0:9b334a45a8ff 2130 }
bogdanm 0:9b334a45a8ff 2131
bogdanm 0:9b334a45a8ff 2132 /**
bogdanm 0:9b334a45a8ff 2133 * @brief Configures the TIM in master mode.
bogdanm 0:9b334a45a8ff 2134 * @param htim: TIM handle.
bogdanm 0:9b334a45a8ff 2135 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
bogdanm 0:9b334a45a8ff 2136 * contains the selected trigger output (TRGO) and the Master/Slave
bogdanm 0:9b334a45a8ff 2137 * mode.
bogdanm 0:9b334a45a8ff 2138 * @retval HAL status
bogdanm 0:9b334a45a8ff 2139 */
bogdanm 0:9b334a45a8ff 2140 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
bogdanm 0:9b334a45a8ff 2141 TIM_MasterConfigTypeDef * sMasterConfig)
bogdanm 0:9b334a45a8ff 2142 {
bogdanm 0:9b334a45a8ff 2143 uint32_t tmpcr2;
bogdanm 0:9b334a45a8ff 2144 uint32_t tmpsmcr;
bogdanm 0:9b334a45a8ff 2145
bogdanm 0:9b334a45a8ff 2146 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2147 assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2148 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
bogdanm 0:9b334a45a8ff 2149 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
bogdanm 0:9b334a45a8ff 2150
bogdanm 0:9b334a45a8ff 2151 /* Check input state */
bogdanm 0:9b334a45a8ff 2152 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 2153
bogdanm 0:9b334a45a8ff 2154 /* Get the TIMx CR2 register value */
bogdanm 0:9b334a45a8ff 2155 tmpcr2 = htim->Instance->CR2;
bogdanm 0:9b334a45a8ff 2156
bogdanm 0:9b334a45a8ff 2157 /* Get the TIMx SMCR register value */
bogdanm 0:9b334a45a8ff 2158 tmpsmcr = htim->Instance->SMCR;
bogdanm 0:9b334a45a8ff 2159
bogdanm 0:9b334a45a8ff 2160 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
bogdanm 0:9b334a45a8ff 2161 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
bogdanm 0:9b334a45a8ff 2162 {
bogdanm 0:9b334a45a8ff 2163 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2164 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
bogdanm 0:9b334a45a8ff 2165
bogdanm 0:9b334a45a8ff 2166 /* Clear the MMS2 bits */
bogdanm 0:9b334a45a8ff 2167 tmpcr2 &= ~TIM_CR2_MMS2;
bogdanm 0:9b334a45a8ff 2168 /* Select the TRGO2 source*/
bogdanm 0:9b334a45a8ff 2169 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
bogdanm 0:9b334a45a8ff 2170 }
bogdanm 0:9b334a45a8ff 2171
bogdanm 0:9b334a45a8ff 2172 /* Reset the MMS Bits */
bogdanm 0:9b334a45a8ff 2173 tmpcr2 &= ~TIM_CR2_MMS;
bogdanm 0:9b334a45a8ff 2174 /* Select the TRGO source */
bogdanm 0:9b334a45a8ff 2175 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
bogdanm 0:9b334a45a8ff 2176
bogdanm 0:9b334a45a8ff 2177 /* Reset the MSM Bit */
bogdanm 0:9b334a45a8ff 2178 tmpsmcr &= ~TIM_SMCR_MSM;
bogdanm 0:9b334a45a8ff 2179 /* Set master mode */
bogdanm 0:9b334a45a8ff 2180 tmpsmcr |= sMasterConfig->MasterSlaveMode;
bogdanm 0:9b334a45a8ff 2181
bogdanm 0:9b334a45a8ff 2182 /* Update TIMx CR2 */
bogdanm 0:9b334a45a8ff 2183 htim->Instance->CR2 = tmpcr2;
bogdanm 0:9b334a45a8ff 2184
bogdanm 0:9b334a45a8ff 2185 /* Update TIMx SMCR */
bogdanm 0:9b334a45a8ff 2186 htim->Instance->SMCR = tmpsmcr;
bogdanm 0:9b334a45a8ff 2187
bogdanm 0:9b334a45a8ff 2188 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2189
bogdanm 0:9b334a45a8ff 2190 return HAL_OK;
bogdanm 0:9b334a45a8ff 2191 }
bogdanm 0:9b334a45a8ff 2192
bogdanm 0:9b334a45a8ff 2193 /**
bogdanm 0:9b334a45a8ff 2194 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
bogdanm 0:9b334a45a8ff 2195 * and the AOE(automatic output enable).
bogdanm 0:9b334a45a8ff 2196 * @param htim: TIM handle
bogdanm 0:9b334a45a8ff 2197 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
bogdanm 0:9b334a45a8ff 2198 * contains the BDTR Register configuration information for the TIM peripheral.
bogdanm 0:9b334a45a8ff 2199 * @retval HAL status
bogdanm 0:9b334a45a8ff 2200 */
bogdanm 0:9b334a45a8ff 2201 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
bogdanm 0:9b334a45a8ff 2202 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
bogdanm 0:9b334a45a8ff 2203 {
bogdanm 0:9b334a45a8ff 2204 uint32_t tmpbdtr = 0;
bogdanm 0:9b334a45a8ff 2205
bogdanm 0:9b334a45a8ff 2206 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2207 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2208 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
bogdanm 0:9b334a45a8ff 2209 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
bogdanm 0:9b334a45a8ff 2210 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
bogdanm 0:9b334a45a8ff 2211 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
bogdanm 0:9b334a45a8ff 2212 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
bogdanm 0:9b334a45a8ff 2213 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
bogdanm 0:9b334a45a8ff 2214 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
bogdanm 0:9b334a45a8ff 2215 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
bogdanm 0:9b334a45a8ff 2216
bogdanm 0:9b334a45a8ff 2217 /* Check input state */
bogdanm 0:9b334a45a8ff 2218 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 2219
bogdanm 0:9b334a45a8ff 2220 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
bogdanm 0:9b334a45a8ff 2221 the OSSI State, the dead time value and the Automatic Output Enable Bit */
bogdanm 0:9b334a45a8ff 2222 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
bogdanm 0:9b334a45a8ff 2223 {
bogdanm 0:9b334a45a8ff 2224 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
bogdanm 0:9b334a45a8ff 2225 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
bogdanm 0:9b334a45a8ff 2226 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
bogdanm 0:9b334a45a8ff 2227
bogdanm 0:9b334a45a8ff 2228 /* Clear the BDTR bits */
bogdanm 0:9b334a45a8ff 2229 tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
bogdanm 0:9b334a45a8ff 2230 TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
bogdanm 0:9b334a45a8ff 2231 TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
bogdanm 0:9b334a45a8ff 2232 TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
bogdanm 0:9b334a45a8ff 2233
bogdanm 0:9b334a45a8ff 2234 /* Set the BDTR bits */
bogdanm 0:9b334a45a8ff 2235 tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
bogdanm 0:9b334a45a8ff 2236 tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
bogdanm 0:9b334a45a8ff 2237 tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
bogdanm 0:9b334a45a8ff 2238 tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
bogdanm 0:9b334a45a8ff 2239 tmpbdtr |= sBreakDeadTimeConfig->BreakState;
bogdanm 0:9b334a45a8ff 2240 tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
bogdanm 0:9b334a45a8ff 2241 tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
bogdanm 0:9b334a45a8ff 2242 tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
bogdanm 0:9b334a45a8ff 2243 tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
bogdanm 0:9b334a45a8ff 2244 tmpbdtr |= sBreakDeadTimeConfig->Break2State;
bogdanm 0:9b334a45a8ff 2245 tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
bogdanm 0:9b334a45a8ff 2246 }
bogdanm 0:9b334a45a8ff 2247 else
bogdanm 0:9b334a45a8ff 2248 {
bogdanm 0:9b334a45a8ff 2249 /* Clear the BDTR bits */
bogdanm 0:9b334a45a8ff 2250 tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
bogdanm 0:9b334a45a8ff 2251 TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
bogdanm 0:9b334a45a8ff 2252 TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF);
bogdanm 0:9b334a45a8ff 2253
bogdanm 0:9b334a45a8ff 2254 /* Set the BDTR bits */
bogdanm 0:9b334a45a8ff 2255 tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
bogdanm 0:9b334a45a8ff 2256 tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
bogdanm 0:9b334a45a8ff 2257 tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
bogdanm 0:9b334a45a8ff 2258 tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
bogdanm 0:9b334a45a8ff 2259 tmpbdtr |= sBreakDeadTimeConfig->BreakState;
bogdanm 0:9b334a45a8ff 2260 tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
bogdanm 0:9b334a45a8ff 2261 tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
bogdanm 0:9b334a45a8ff 2262 tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
bogdanm 0:9b334a45a8ff 2263 }
bogdanm 0:9b334a45a8ff 2264
bogdanm 0:9b334a45a8ff 2265 /* Set TIMx_BDTR */
bogdanm 0:9b334a45a8ff 2266 htim->Instance->BDTR = tmpbdtr;
bogdanm 0:9b334a45a8ff 2267
bogdanm 0:9b334a45a8ff 2268 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2269
bogdanm 0:9b334a45a8ff 2270 return HAL_OK;
bogdanm 0:9b334a45a8ff 2271 }
bogdanm 0:9b334a45a8ff 2272
bogdanm 0:9b334a45a8ff 2273 /**
bogdanm 0:9b334a45a8ff 2274 * @brief Configures the break input source.
bogdanm 0:9b334a45a8ff 2275 * @param htim: TIM handle.
bogdanm 0:9b334a45a8ff 2276 * @param BreakInput: Break input to configure
bogdanm 0:9b334a45a8ff 2277 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2278 * @arg TIM_BREAKINPUT_BRK: Timer break input
bogdanm 0:9b334a45a8ff 2279 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
bogdanm 0:9b334a45a8ff 2280 * @param sBreakInputConfig: Break input source configuration
bogdanm 0:9b334a45a8ff 2281 * @retval HAL status
bogdanm 0:9b334a45a8ff 2282 */
bogdanm 0:9b334a45a8ff 2283 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
bogdanm 0:9b334a45a8ff 2284 uint32_t BreakInput,
bogdanm 0:9b334a45a8ff 2285 TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
bogdanm 0:9b334a45a8ff 2286
bogdanm 0:9b334a45a8ff 2287 {
bogdanm 0:9b334a45a8ff 2288 uint32_t tmporx = 0;
bogdanm 0:9b334a45a8ff 2289 uint32_t bkin_enable_mask = 0;
bogdanm 0:9b334a45a8ff 2290 uint32_t bkin_polarity_mask = 0;
bogdanm 0:9b334a45a8ff 2291 uint32_t bkin_enable_bitpos = 0;
bogdanm 0:9b334a45a8ff 2292 uint32_t bkin_polarity_bitpos = 0;
bogdanm 0:9b334a45a8ff 2293
bogdanm 0:9b334a45a8ff 2294 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2295 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2296 assert_param(IS_TIM_BREAKINPUT(BreakInput));
bogdanm 0:9b334a45a8ff 2297 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
bogdanm 0:9b334a45a8ff 2298 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
bogdanm 0:9b334a45a8ff 2299 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM)
bogdanm 0:9b334a45a8ff 2300 {
bogdanm 0:9b334a45a8ff 2301 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
bogdanm 0:9b334a45a8ff 2302 }
bogdanm 0:9b334a45a8ff 2303
bogdanm 0:9b334a45a8ff 2304 /* Check input state */
bogdanm 0:9b334a45a8ff 2305 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 2306
bogdanm 0:9b334a45a8ff 2307 switch(sBreakInputConfig->Source)
bogdanm 0:9b334a45a8ff 2308 {
bogdanm 0:9b334a45a8ff 2309 case TIM_BREAKINPUTSOURCE_BKIN:
bogdanm 0:9b334a45a8ff 2310 {
bogdanm 0:9b334a45a8ff 2311 bkin_enable_mask = TIM1_OR2_BKINE;
bogdanm 0:9b334a45a8ff 2312 bkin_enable_bitpos = 0;
bogdanm 0:9b334a45a8ff 2313 bkin_polarity_mask = TIM1_OR2_BKINP;
bogdanm 0:9b334a45a8ff 2314 bkin_polarity_bitpos = 9;
bogdanm 0:9b334a45a8ff 2315 }
bogdanm 0:9b334a45a8ff 2316 break;
bogdanm 0:9b334a45a8ff 2317 case TIM_BREAKINPUTSOURCE_COMP1:
bogdanm 0:9b334a45a8ff 2318 {
bogdanm 0:9b334a45a8ff 2319 bkin_enable_mask = TIM1_OR2_BKCMP1E;
bogdanm 0:9b334a45a8ff 2320 bkin_enable_bitpos = 1;
bogdanm 0:9b334a45a8ff 2321 bkin_polarity_mask = TIM1_OR2_BKCMP1P;
bogdanm 0:9b334a45a8ff 2322 bkin_polarity_bitpos = 10;
bogdanm 0:9b334a45a8ff 2323 }
bogdanm 0:9b334a45a8ff 2324 break;
bogdanm 0:9b334a45a8ff 2325 case TIM_BREAKINPUTSOURCE_COMP2:
bogdanm 0:9b334a45a8ff 2326 {
bogdanm 0:9b334a45a8ff 2327 bkin_enable_mask = TIM1_OR2_BKCMP2E;
bogdanm 0:9b334a45a8ff 2328 bkin_enable_bitpos = 2;
bogdanm 0:9b334a45a8ff 2329 bkin_polarity_mask = TIM1_OR2_BKCMP2P;
bogdanm 0:9b334a45a8ff 2330 bkin_polarity_bitpos = 11;
bogdanm 0:9b334a45a8ff 2331 }
bogdanm 0:9b334a45a8ff 2332 break;
bogdanm 0:9b334a45a8ff 2333 case TIM_BREAKINPUTSOURCE_DFSDM:
bogdanm 0:9b334a45a8ff 2334 {
bogdanm 0:9b334a45a8ff 2335 bkin_enable_mask = TIM1_OR2_BKDFBK0E;
bogdanm 0:9b334a45a8ff 2336 bkin_enable_bitpos = 8;
bogdanm 0:9b334a45a8ff 2337 }
bogdanm 0:9b334a45a8ff 2338 break;
bogdanm 0:9b334a45a8ff 2339 default:
bogdanm 0:9b334a45a8ff 2340 break;
bogdanm 0:9b334a45a8ff 2341 }
bogdanm 0:9b334a45a8ff 2342
bogdanm 0:9b334a45a8ff 2343 switch(BreakInput)
bogdanm 0:9b334a45a8ff 2344 {
bogdanm 0:9b334a45a8ff 2345 case TIM_BREAKINPUT_BRK:
bogdanm 0:9b334a45a8ff 2346 {
bogdanm 0:9b334a45a8ff 2347 /* Get the TIMx_OR2 register value */
bogdanm 0:9b334a45a8ff 2348 tmporx = htim->Instance->OR2;
bogdanm 0:9b334a45a8ff 2349
bogdanm 0:9b334a45a8ff 2350 /* Enable the break input */
bogdanm 0:9b334a45a8ff 2351 tmporx &= ~bkin_enable_mask;
bogdanm 0:9b334a45a8ff 2352 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
bogdanm 0:9b334a45a8ff 2353
bogdanm 0:9b334a45a8ff 2354 /* Set the break input polarity */
bogdanm 0:9b334a45a8ff 2355 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM)
bogdanm 0:9b334a45a8ff 2356 {
bogdanm 0:9b334a45a8ff 2357 tmporx &= ~bkin_polarity_mask;
bogdanm 0:9b334a45a8ff 2358 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
bogdanm 0:9b334a45a8ff 2359 }
bogdanm 0:9b334a45a8ff 2360
bogdanm 0:9b334a45a8ff 2361 /* Set TIMx_OR2 */
bogdanm 0:9b334a45a8ff 2362 htim->Instance->OR2 = tmporx;
bogdanm 0:9b334a45a8ff 2363 }
bogdanm 0:9b334a45a8ff 2364 break;
bogdanm 0:9b334a45a8ff 2365 case TIM_BREAKINPUT_BRK2:
bogdanm 0:9b334a45a8ff 2366 {
bogdanm 0:9b334a45a8ff 2367 /* Get the TIMx_OR3 register value */
bogdanm 0:9b334a45a8ff 2368 tmporx = htim->Instance->OR3;
bogdanm 0:9b334a45a8ff 2369
bogdanm 0:9b334a45a8ff 2370 /* Enable the break input */
bogdanm 0:9b334a45a8ff 2371 tmporx &= ~bkin_enable_mask;
bogdanm 0:9b334a45a8ff 2372 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
bogdanm 0:9b334a45a8ff 2373
bogdanm 0:9b334a45a8ff 2374 /* Set the break input polarity */
bogdanm 0:9b334a45a8ff 2375 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM)
bogdanm 0:9b334a45a8ff 2376 {
bogdanm 0:9b334a45a8ff 2377 tmporx &= ~bkin_polarity_mask;
bogdanm 0:9b334a45a8ff 2378 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
bogdanm 0:9b334a45a8ff 2379 }
bogdanm 0:9b334a45a8ff 2380
bogdanm 0:9b334a45a8ff 2381 /* Set TIMx_OR3 */
bogdanm 0:9b334a45a8ff 2382 htim->Instance->OR3 = tmporx;
bogdanm 0:9b334a45a8ff 2383 }
bogdanm 0:9b334a45a8ff 2384 break;
bogdanm 0:9b334a45a8ff 2385 default:
bogdanm 0:9b334a45a8ff 2386 break;
bogdanm 0:9b334a45a8ff 2387 }
bogdanm 0:9b334a45a8ff 2388
bogdanm 0:9b334a45a8ff 2389 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2390
bogdanm 0:9b334a45a8ff 2391 return HAL_OK;
bogdanm 0:9b334a45a8ff 2392 }
bogdanm 0:9b334a45a8ff 2393
bogdanm 0:9b334a45a8ff 2394 /**
bogdanm 0:9b334a45a8ff 2395 * @brief Configures the TIMx Remapping input capabilities.
bogdanm 0:9b334a45a8ff 2396 * @param htim: TIM handle.
bogdanm 0:9b334a45a8ff 2397 * @param Remap: specifies the TIM remapping source.
bogdanm 0:9b334a45a8ff 2398 * For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):
bogdanm 0:9b334a45a8ff 2399 * field1 can have the following values:
bogdanm 0:9b334a45a8ff 2400 * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
bogdanm 0:9b334a45a8ff 2401 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
bogdanm 0:9b334a45a8ff 2402 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
bogdanm 0:9b334a45a8ff 2403 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
bogdanm 0:9b334a45a8ff 2404 * field2 can have the following values:
bogdanm 0:9b334a45a8ff 2405 * @arg TIM_TIM1_ETR_ADC3_NONE: TIM1_ETR is not connected to any ADC3 AWD (analog watchdog)
bogdanm 0:9b334a45a8ff 2406 * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
bogdanm 0:9b334a45a8ff 2407 * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
bogdanm 0:9b334a45a8ff 2408 * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
bogdanm 0:9b334a45a8ff 2409 * field3 can have the following values:
bogdanm 0:9b334a45a8ff 2410 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
bogdanm 0:9b334a45a8ff 2411 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
bogdanm 0:9b334a45a8ff 2412 * field4 can have the following values:
bogdanm 0:9b334a45a8ff 2413 * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
bogdanm 0:9b334a45a8ff 2414 * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
bogdanm 0:9b334a45a8ff 2415 * @note When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant
bogdanm 0:9b334a45a8ff 2416 *
bogdanm 0:9b334a45a8ff 2417 * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
bogdanm 0:9b334a45a8ff 2418 * field1 can have the following values:
bogdanm 0:9b334a45a8ff 2419 * @arg TIM_TIM2_ITR1_TIM8_TRGO: TIM2_ITR1 is connected to TIM8_TRGO
bogdanm 0:9b334a45a8ff 2420 * @arg TIM_TIM2_ITR1_OTG_FS_SOF: TIM2_ITR1 is connected to OTG_FS SOF
bogdanm 0:9b334a45a8ff 2421 * field2 can have the following values:
bogdanm 0:9b334a45a8ff 2422 * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
bogdanm 0:9b334a45a8ff 2423 * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
bogdanm 0:9b334a45a8ff 2424 * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
bogdanm 0:9b334a45a8ff 2425 * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
bogdanm 0:9b334a45a8ff 2426 * field3 can have the following values:
bogdanm 0:9b334a45a8ff 2427 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
bogdanm 0:9b334a45a8ff 2428 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
bogdanm 0:9b334a45a8ff 2429 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
bogdanm 0:9b334a45a8ff 2430 * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
bogdanm 0:9b334a45a8ff 2431 *
bogdanm 0:9b334a45a8ff 2432 * For TIM3, the parameter is a combination 2 fields(field1 | field2):
bogdanm 0:9b334a45a8ff 2433 * field1 can have the following values:
bogdanm 0:9b334a45a8ff 2434 * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
bogdanm 0:9b334a45a8ff 2435 * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
bogdanm 0:9b334a45a8ff 2436 * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
bogdanm 0:9b334a45a8ff 2437 * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
bogdanm 0:9b334a45a8ff 2438 * field2 can have the following values:
bogdanm 0:9b334a45a8ff 2439 * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO
bogdanm 0:9b334a45a8ff 2440 * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output
bogdanm 0:9b334a45a8ff 2441 *
bogdanm 0:9b334a45a8ff 2442 * For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3):
bogdanm 0:9b334a45a8ff 2443 * field1 can have the following values:
bogdanm 0:9b334a45a8ff 2444 * @arg TIM_TIM8_ETR_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD (analog watchdog)
bogdanm 0:9b334a45a8ff 2445 * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
bogdanm 0:9b334a45a8ff 2446 * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
bogdanm 0:9b334a45a8ff 2447 * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
bogdanm 0:9b334a45a8ff 2448 * field2 can have the following values:
bogdanm 0:9b334a45a8ff 2449 * @arg TIM_TIM8_ETR_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD (analog watchdog)
bogdanm 0:9b334a45a8ff 2450 * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
bogdanm 0:9b334a45a8ff 2451 * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
bogdanm 0:9b334a45a8ff 2452 * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
bogdanm 0:9b334a45a8ff 2453 * field3 can have the following values:
bogdanm 0:9b334a45a8ff 2454 * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
bogdanm 0:9b334a45a8ff 2455 * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
bogdanm 0:9b334a45a8ff 2456 * field4 can have the following values:
bogdanm 0:9b334a45a8ff 2457 * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output
bogdanm 0:9b334a45a8ff 2458 * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output
bogdanm 0:9b334a45a8ff 2459 * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant
bogdanm 0:9b334a45a8ff 2460 *
bogdanm 0:9b334a45a8ff 2461 * For TIM15, the parameter is a combination of 3 fields (field1 | field2):
bogdanm 0:9b334a45a8ff 2462 * field1 can have the following values:
bogdanm 0:9b334a45a8ff 2463 * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
bogdanm 0:9b334a45a8ff 2464 * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
bogdanm 0:9b334a45a8ff 2465 * field2 can have the following values:
bogdanm 0:9b334a45a8ff 2466 * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection
bogdanm 0:9b334a45a8ff 2467 * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
bogdanm 0:9b334a45a8ff 2468 * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
bogdanm 0:9b334a45a8ff 2469 * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
bogdanm 0:9b334a45a8ff 2470 *
bogdanm 0:9b334a45a8ff 2471 * For TIM16, the parameter can have the following values:
bogdanm 0:9b334a45a8ff 2472 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
bogdanm 0:9b334a45a8ff 2473 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
bogdanm 0:9b334a45a8ff 2474 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
bogdanm 0:9b334a45a8ff 2475 * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
bogdanm 0:9b334a45a8ff 2476 *
bogdanm 0:9b334a45a8ff 2477 * For TIM17, the parameter can have the following values:
bogdanm 0:9b334a45a8ff 2478 * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
bogdanm 0:9b334a45a8ff 2479 * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI
bogdanm 0:9b334a45a8ff 2480 * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32
bogdanm 0:9b334a45a8ff 2481 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
bogdanm 0:9b334a45a8ff 2482 *
bogdanm 0:9b334a45a8ff 2483 * @retval HAL status
bogdanm 0:9b334a45a8ff 2484 */
bogdanm 0:9b334a45a8ff 2485 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
bogdanm 0:9b334a45a8ff 2486 {
bogdanm 0:9b334a45a8ff 2487 uint32_t tmpor1 = 0;
bogdanm 0:9b334a45a8ff 2488 uint32_t tmpor2 = 0;
bogdanm 0:9b334a45a8ff 2489
bogdanm 0:9b334a45a8ff 2490 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 2491
bogdanm 0:9b334a45a8ff 2492 /* Check parameters */
bogdanm 0:9b334a45a8ff 2493 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2494 assert_param(IS_TIM_REMAP(Remap));
bogdanm 0:9b334a45a8ff 2495
bogdanm 0:9b334a45a8ff 2496 /* Set ETR_SEL bit field (if required) */
bogdanm 0:9b334a45a8ff 2497 if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))
bogdanm 0:9b334a45a8ff 2498 {
bogdanm 0:9b334a45a8ff 2499 tmpor2 = htim->Instance->OR2;
bogdanm 0:9b334a45a8ff 2500 tmpor2 &= ~TIMx_ETRSEL_MASK;
bogdanm 0:9b334a45a8ff 2501 tmpor2 |= (Remap & TIMx_ETRSEL_MASK);
bogdanm 0:9b334a45a8ff 2502
bogdanm 0:9b334a45a8ff 2503 /* Set TIMx_OR2 */
bogdanm 0:9b334a45a8ff 2504 htim->Instance->OR2 = tmpor2;
bogdanm 0:9b334a45a8ff 2505 }
bogdanm 0:9b334a45a8ff 2506
bogdanm 0:9b334a45a8ff 2507 /* Set other remapping capabilities */
bogdanm 0:9b334a45a8ff 2508 tmpor1 = Remap;
bogdanm 0:9b334a45a8ff 2509 tmpor1 &= ~TIMx_ETRSEL_MASK;
bogdanm 0:9b334a45a8ff 2510
bogdanm 0:9b334a45a8ff 2511 /* Set TIMx_OR1 */
bogdanm 0:9b334a45a8ff 2512 htim->Instance->OR1 = Remap;
bogdanm 0:9b334a45a8ff 2513
bogdanm 0:9b334a45a8ff 2514 /* Set TIMx_OR1 */
bogdanm 0:9b334a45a8ff 2515 htim->Instance->OR1 = tmpor1;
bogdanm 0:9b334a45a8ff 2516
bogdanm 0:9b334a45a8ff 2517 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 2518
bogdanm 0:9b334a45a8ff 2519 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2520
bogdanm 0:9b334a45a8ff 2521 return HAL_OK;
bogdanm 0:9b334a45a8ff 2522 }
bogdanm 0:9b334a45a8ff 2523
bogdanm 0:9b334a45a8ff 2524 /**
bogdanm 0:9b334a45a8ff 2525 * @brief Group channel 5 and channel 1, 2 or 3
bogdanm 0:9b334a45a8ff 2526 * @param htim: TIM handle.
bogdanm 0:9b334a45a8ff 2527 * @param Channels: specifies the reference signal(s) the OC5REF is combined with.
bogdanm 0:9b334a45a8ff 2528 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 2529 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
bogdanm 0:9b334a45a8ff 2530 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
bogdanm 0:9b334a45a8ff 2531 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
bogdanm 0:9b334a45a8ff 2532 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
bogdanm 0:9b334a45a8ff 2533 * @retval HAL status
bogdanm 0:9b334a45a8ff 2534 */
bogdanm 0:9b334a45a8ff 2535 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
bogdanm 0:9b334a45a8ff 2536 {
bogdanm 0:9b334a45a8ff 2537 /* Check parameters */
bogdanm 0:9b334a45a8ff 2538 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2539 assert_param(IS_TIM_GROUPCH5(Channels));
bogdanm 0:9b334a45a8ff 2540
bogdanm 0:9b334a45a8ff 2541 /* Process Locked */
bogdanm 0:9b334a45a8ff 2542 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 2543
bogdanm 0:9b334a45a8ff 2544 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 2545
bogdanm 0:9b334a45a8ff 2546 /* Clear GC5Cx bit fields */
bogdanm 0:9b334a45a8ff 2547 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
bogdanm 0:9b334a45a8ff 2548
bogdanm 0:9b334a45a8ff 2549 /* Set GC5Cx bit fields */
bogdanm 0:9b334a45a8ff 2550 htim->Instance->CCR5 |= Channels;
bogdanm 0:9b334a45a8ff 2551
bogdanm 0:9b334a45a8ff 2552 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 2553
bogdanm 0:9b334a45a8ff 2554 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2555
bogdanm 0:9b334a45a8ff 2556 return HAL_OK;
bogdanm 0:9b334a45a8ff 2557 }
bogdanm 0:9b334a45a8ff 2558
bogdanm 0:9b334a45a8ff 2559 /**
bogdanm 0:9b334a45a8ff 2560 * @}
bogdanm 0:9b334a45a8ff 2561 */
bogdanm 0:9b334a45a8ff 2562
bogdanm 0:9b334a45a8ff 2563 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
bogdanm 0:9b334a45a8ff 2564 * @brief Extended Callbacks functions
bogdanm 0:9b334a45a8ff 2565 *
bogdanm 0:9b334a45a8ff 2566 @verbatim
bogdanm 0:9b334a45a8ff 2567 ==============================================================================
bogdanm 0:9b334a45a8ff 2568 ##### Extended Callbacks functions #####
bogdanm 0:9b334a45a8ff 2569 ==============================================================================
bogdanm 0:9b334a45a8ff 2570 [..]
bogdanm 0:9b334a45a8ff 2571 This section provides Extended TIM callback functions:
bogdanm 0:9b334a45a8ff 2572 (+) Timer Commutation callback
bogdanm 0:9b334a45a8ff 2573 (+) Timer Break callback
bogdanm 0:9b334a45a8ff 2574
bogdanm 0:9b334a45a8ff 2575 @endverbatim
bogdanm 0:9b334a45a8ff 2576 * @{
bogdanm 0:9b334a45a8ff 2577 */
bogdanm 0:9b334a45a8ff 2578
bogdanm 0:9b334a45a8ff 2579 /**
bogdanm 0:9b334a45a8ff 2580 * @brief Hall commutation changed callback in non-blocking mode
bogdanm 0:9b334a45a8ff 2581 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 2582 * @retval None
bogdanm 0:9b334a45a8ff 2583 */
bogdanm 0:9b334a45a8ff 2584 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 2585 {
bogdanm 0:9b334a45a8ff 2586 /* NOTE : This function should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 2587 the HAL_TIMEx_CommutationCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 2588 */
bogdanm 0:9b334a45a8ff 2589 }
bogdanm 0:9b334a45a8ff 2590
bogdanm 0:9b334a45a8ff 2591 /**
bogdanm 0:9b334a45a8ff 2592 * @brief Hall Break detection callback in non-blocking mode
bogdanm 0:9b334a45a8ff 2593 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 2594 * @retval None
bogdanm 0:9b334a45a8ff 2595 */
bogdanm 0:9b334a45a8ff 2596 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 2597 {
bogdanm 0:9b334a45a8ff 2598 /* NOTE : This function should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 2599 the HAL_TIMEx_BreakCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 2600 */
bogdanm 0:9b334a45a8ff 2601 }
bogdanm 0:9b334a45a8ff 2602
bogdanm 0:9b334a45a8ff 2603 /**
bogdanm 0:9b334a45a8ff 2604 * @}
bogdanm 0:9b334a45a8ff 2605 */
bogdanm 0:9b334a45a8ff 2606
bogdanm 0:9b334a45a8ff 2607 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
bogdanm 0:9b334a45a8ff 2608 * @brief Extended Peripheral State functions
bogdanm 0:9b334a45a8ff 2609 *
bogdanm 0:9b334a45a8ff 2610 @verbatim
bogdanm 0:9b334a45a8ff 2611 ==============================================================================
bogdanm 0:9b334a45a8ff 2612 ##### Extended Peripheral State functions #####
bogdanm 0:9b334a45a8ff 2613 ==============================================================================
bogdanm 0:9b334a45a8ff 2614 [..]
bogdanm 0:9b334a45a8ff 2615 This subsection permits to get in run-time the status of the peripheral
bogdanm 0:9b334a45a8ff 2616 and the data flow.
bogdanm 0:9b334a45a8ff 2617
bogdanm 0:9b334a45a8ff 2618 @endverbatim
bogdanm 0:9b334a45a8ff 2619 * @{
bogdanm 0:9b334a45a8ff 2620 */
bogdanm 0:9b334a45a8ff 2621
bogdanm 0:9b334a45a8ff 2622 /**
bogdanm 0:9b334a45a8ff 2623 * @brief Return the TIM Hall Sensor interface handle state.
bogdanm 0:9b334a45a8ff 2624 * @param htim: TIM Hall Sensor handle
bogdanm 0:9b334a45a8ff 2625 * @retval HAL state
bogdanm 0:9b334a45a8ff 2626 */
bogdanm 0:9b334a45a8ff 2627 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 2628 {
bogdanm 0:9b334a45a8ff 2629 return htim->State;
bogdanm 0:9b334a45a8ff 2630 }
bogdanm 0:9b334a45a8ff 2631
bogdanm 0:9b334a45a8ff 2632 /**
bogdanm 0:9b334a45a8ff 2633 * @}
bogdanm 0:9b334a45a8ff 2634 */
bogdanm 0:9b334a45a8ff 2635
bogdanm 0:9b334a45a8ff 2636 /**
bogdanm 0:9b334a45a8ff 2637 * @brief TIM DMA Commutation callback.
bogdanm 0:9b334a45a8ff 2638 * @param hdma : pointer to DMA handle.
bogdanm 0:9b334a45a8ff 2639 * @retval None
bogdanm 0:9b334a45a8ff 2640 */
bogdanm 0:9b334a45a8ff 2641 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 2642 {
bogdanm 0:9b334a45a8ff 2643 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm 0:9b334a45a8ff 2644
bogdanm 0:9b334a45a8ff 2645 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 2646
bogdanm 0:9b334a45a8ff 2647 HAL_TIMEx_CommutationCallback(htim);
bogdanm 0:9b334a45a8ff 2648 }
bogdanm 0:9b334a45a8ff 2649
bogdanm 0:9b334a45a8ff 2650 /**
bogdanm 0:9b334a45a8ff 2651 * @brief Enables or disables the TIM Capture Compare Channel xN.
bogdanm 0:9b334a45a8ff 2652 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 2653 * @param Channel: specifies the TIM Channel
bogdanm 0:9b334a45a8ff 2654 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2655 * @arg TIM_Channel_1: TIM Channel 1
bogdanm 0:9b334a45a8ff 2656 * @arg TIM_Channel_2: TIM Channel 2
bogdanm 0:9b334a45a8ff 2657 * @arg TIM_Channel_3: TIM Channel 3
bogdanm 0:9b334a45a8ff 2658 * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
bogdanm 0:9b334a45a8ff 2659 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
bogdanm 0:9b334a45a8ff 2660 * @retval None
bogdanm 0:9b334a45a8ff 2661 */
bogdanm 0:9b334a45a8ff 2662 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
bogdanm 0:9b334a45a8ff 2663 {
bogdanm 0:9b334a45a8ff 2664 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 2665
bogdanm 0:9b334a45a8ff 2666 tmp = TIM_CCER_CC1NE << Channel;
bogdanm 0:9b334a45a8ff 2667
bogdanm 0:9b334a45a8ff 2668 /* Reset the CCxNE Bit */
bogdanm 0:9b334a45a8ff 2669 TIMx->CCER &= ~tmp;
bogdanm 0:9b334a45a8ff 2670
bogdanm 0:9b334a45a8ff 2671 /* Set or reset the CCxNE Bit */
bogdanm 0:9b334a45a8ff 2672 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
bogdanm 0:9b334a45a8ff 2673 }
bogdanm 0:9b334a45a8ff 2674
bogdanm 0:9b334a45a8ff 2675 /**
bogdanm 0:9b334a45a8ff 2676 * @}
bogdanm 0:9b334a45a8ff 2677 */
bogdanm 0:9b334a45a8ff 2678
bogdanm 0:9b334a45a8ff 2679 #endif /* HAL_TIM_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 2680 /**
bogdanm 0:9b334a45a8ff 2681 * @}
bogdanm 0:9b334a45a8ff 2682 */
bogdanm 0:9b334a45a8ff 2683
bogdanm 0:9b334a45a8ff 2684 /**
bogdanm 0:9b334a45a8ff 2685 * @}
bogdanm 0:9b334a45a8ff 2686 */
bogdanm 0:9b334a45a8ff 2687
bogdanm 0:9b334a45a8ff 2688 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/