fix LPC812 PWM
Fork of mbed-dev by
targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_smbus.c@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /** |
bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 3 | * @file stm32l4xx_hal_smbus.c |
bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
bogdanm | 0:9b334a45a8ff | 5 | * @version V1.0.0 |
bogdanm | 0:9b334a45a8ff | 6 | * @date 26-June-2015 |
bogdanm | 0:9b334a45a8ff | 7 | * @brief SMBUS HAL module driver. |
bogdanm | 0:9b334a45a8ff | 8 | * This file provides firmware functions to manage the following |
bogdanm | 0:9b334a45a8ff | 9 | * functionalities of the System Management Bus (SMBus) peripheral, |
bogdanm | 0:9b334a45a8ff | 10 | * based on I2C principles of operation : |
bogdanm | 0:9b334a45a8ff | 11 | * + Initialization and de-initialization functions |
bogdanm | 0:9b334a45a8ff | 12 | * + IO operation functions |
bogdanm | 0:9b334a45a8ff | 13 | * + Peripheral State and Errors functions |
bogdanm | 0:9b334a45a8ff | 14 | * |
bogdanm | 0:9b334a45a8ff | 15 | @verbatim |
bogdanm | 0:9b334a45a8ff | 16 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 17 | ##### How to use this driver ##### |
bogdanm | 0:9b334a45a8ff | 18 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 19 | [..] |
bogdanm | 0:9b334a45a8ff | 20 | The SMBUS HAL driver can be used as follows: |
bogdanm | 0:9b334a45a8ff | 21 | |
bogdanm | 0:9b334a45a8ff | 22 | (#) Declare a SMBUS_HandleTypeDef handle structure, for example: |
bogdanm | 0:9b334a45a8ff | 23 | SMBUS_HandleTypeDef hsmbus; |
bogdanm | 0:9b334a45a8ff | 24 | |
bogdanm | 0:9b334a45a8ff | 25 | (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: |
bogdanm | 0:9b334a45a8ff | 26 | (++) Enable the SMBUSx interface clock with __HAL_RCC_I2Cx_CLK_ENABLE() |
bogdanm | 0:9b334a45a8ff | 27 | (++) SMBUS pins configuration |
bogdanm | 0:9b334a45a8ff | 28 | (+++) Enable the clock for the SMBUS GPIOs |
bogdanm | 0:9b334a45a8ff | 29 | (+++) Configure SMBUS pins as alternate function open-drain |
bogdanm | 0:9b334a45a8ff | 30 | (++) NVIC configuration if you need to use interrupt process |
bogdanm | 0:9b334a45a8ff | 31 | (+++) Configure the SMBUSx interrupt priority |
bogdanm | 0:9b334a45a8ff | 32 | (+++) Enable the NVIC SMBUS IRQ Channel |
bogdanm | 0:9b334a45a8ff | 33 | |
bogdanm | 0:9b334a45a8ff | 34 | (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing Mode, |
bogdanm | 0:9b334a45a8ff | 35 | Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, |
bogdanm | 0:9b334a45a8ff | 36 | Peripheral mode and Packet Error Check mode in the hsmbus Init structure. |
bogdanm | 0:9b334a45a8ff | 37 | |
bogdanm | 0:9b334a45a8ff | 38 | (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: |
bogdanm | 0:9b334a45a8ff | 39 | (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) |
bogdanm | 0:9b334a45a8ff | 40 | by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. |
bogdanm | 0:9b334a45a8ff | 41 | |
bogdanm | 0:9b334a45a8ff | 42 | (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() |
bogdanm | 0:9b334a45a8ff | 43 | |
bogdanm | 0:9b334a45a8ff | 44 | (#) For SMBUS IO operations, only one mode of operations is available within this driver : |
bogdanm | 0:9b334a45a8ff | 45 | |
bogdanm | 0:9b334a45a8ff | 46 | *** Interrupt mode IO operation *** |
bogdanm | 0:9b334a45a8ff | 47 | =================================== |
bogdanm | 0:9b334a45a8ff | 48 | [..] |
bogdanm | 0:9b334a45a8ff | 49 | (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT() |
bogdanm | 0:9b334a45a8ff | 50 | (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can |
bogdanm | 0:9b334a45a8ff | 51 | add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() |
bogdanm | 0:9b334a45a8ff | 52 | (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT() |
bogdanm | 0:9b334a45a8ff | 53 | (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can |
bogdanm | 0:9b334a45a8ff | 54 | add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() |
bogdanm | 0:9b334a45a8ff | 55 | (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() |
bogdanm | 0:9b334a45a8ff | 56 | (++) The associated previous transfer callback is called at the end of abort process |
bogdanm | 0:9b334a45a8ff | 57 | (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit |
bogdanm | 0:9b334a45a8ff | 58 | (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive |
bogdanm | 0:9b334a45a8ff | 59 | (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode |
bogdanm | 0:9b334a45a8ff | 60 | using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() |
bogdanm | 0:9b334a45a8ff | 61 | (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can |
bogdanm | 0:9b334a45a8ff | 62 | add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). |
bogdanm | 0:9b334a45a8ff | 63 | (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can |
bogdanm | 0:9b334a45a8ff | 64 | add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() |
bogdanm | 0:9b334a45a8ff | 65 | (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT() |
bogdanm | 0:9b334a45a8ff | 66 | (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can |
bogdanm | 0:9b334a45a8ff | 67 | add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() |
bogdanm | 0:9b334a45a8ff | 68 | (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT() |
bogdanm | 0:9b334a45a8ff | 69 | (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can |
bogdanm | 0:9b334a45a8ff | 70 | add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() |
bogdanm | 0:9b334a45a8ff | 71 | (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT() |
bogdanm | 0:9b334a45a8ff | 72 | (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can |
bogdanm | 0:9b334a45a8ff | 73 | add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() |
bogdanm | 0:9b334a45a8ff | 74 | to check the Alert Error Code using function HAL_SMBUS_GetError() |
bogdanm | 0:9b334a45a8ff | 75 | (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() |
bogdanm | 0:9b334a45a8ff | 76 | (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can |
bogdanm | 0:9b334a45a8ff | 77 | add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() |
bogdanm | 0:9b334a45a8ff | 78 | to check the Error Code using function HAL_SMBUS_GetError() |
bogdanm | 0:9b334a45a8ff | 79 | |
bogdanm | 0:9b334a45a8ff | 80 | *** SMBUS HAL driver macros list *** |
bogdanm | 0:9b334a45a8ff | 81 | ================================== |
bogdanm | 0:9b334a45a8ff | 82 | [..] |
bogdanm | 0:9b334a45a8ff | 83 | Below the list of most used macros in SMBUS HAL driver. |
bogdanm | 0:9b334a45a8ff | 84 | |
bogdanm | 0:9b334a45a8ff | 85 | (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral |
bogdanm | 0:9b334a45a8ff | 86 | (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral |
bogdanm | 0:9b334a45a8ff | 87 | (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not |
bogdanm | 0:9b334a45a8ff | 88 | (+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag |
bogdanm | 0:9b334a45a8ff | 89 | (+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt |
bogdanm | 0:9b334a45a8ff | 90 | (+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt |
bogdanm | 0:9b334a45a8ff | 91 | |
bogdanm | 0:9b334a45a8ff | 92 | [..] |
bogdanm | 0:9b334a45a8ff | 93 | (@) You can refer to the SMBUS HAL driver header file for more useful macros |
bogdanm | 0:9b334a45a8ff | 94 | |
bogdanm | 0:9b334a45a8ff | 95 | |
bogdanm | 0:9b334a45a8ff | 96 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 97 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 98 | * @attention |
bogdanm | 0:9b334a45a8ff | 99 | * |
bogdanm | 0:9b334a45a8ff | 100 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
bogdanm | 0:9b334a45a8ff | 101 | * |
bogdanm | 0:9b334a45a8ff | 102 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 0:9b334a45a8ff | 103 | * are permitted provided that the following conditions are met: |
bogdanm | 0:9b334a45a8ff | 104 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 105 | * this list of conditions and the following disclaimer. |
bogdanm | 0:9b334a45a8ff | 106 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 107 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 0:9b334a45a8ff | 108 | * and/or other materials provided with the distribution. |
bogdanm | 0:9b334a45a8ff | 109 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 0:9b334a45a8ff | 110 | * may be used to endorse or promote products derived from this software |
bogdanm | 0:9b334a45a8ff | 111 | * without specific prior written permission. |
bogdanm | 0:9b334a45a8ff | 112 | * |
bogdanm | 0:9b334a45a8ff | 113 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 0:9b334a45a8ff | 114 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 0:9b334a45a8ff | 115 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 0:9b334a45a8ff | 116 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 0:9b334a45a8ff | 117 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 0:9b334a45a8ff | 118 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 0:9b334a45a8ff | 119 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 0:9b334a45a8ff | 120 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 0:9b334a45a8ff | 121 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 0:9b334a45a8ff | 122 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 0:9b334a45a8ff | 123 | * |
bogdanm | 0:9b334a45a8ff | 124 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 125 | */ |
bogdanm | 0:9b334a45a8ff | 126 | |
bogdanm | 0:9b334a45a8ff | 127 | /* Includes ------------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 128 | #include "stm32l4xx_hal.h" |
bogdanm | 0:9b334a45a8ff | 129 | |
bogdanm | 0:9b334a45a8ff | 130 | /** @addtogroup STM32L4xx_HAL_Driver |
bogdanm | 0:9b334a45a8ff | 131 | * @{ |
bogdanm | 0:9b334a45a8ff | 132 | */ |
bogdanm | 0:9b334a45a8ff | 133 | |
bogdanm | 0:9b334a45a8ff | 134 | /** @defgroup SMBUS SMBUS |
bogdanm | 0:9b334a45a8ff | 135 | * @brief SMBUS HAL module driver |
bogdanm | 0:9b334a45a8ff | 136 | * @{ |
bogdanm | 0:9b334a45a8ff | 137 | */ |
bogdanm | 0:9b334a45a8ff | 138 | |
bogdanm | 0:9b334a45a8ff | 139 | #ifdef HAL_SMBUS_MODULE_ENABLED |
bogdanm | 0:9b334a45a8ff | 140 | |
bogdanm | 0:9b334a45a8ff | 141 | /* Private typedef -----------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 142 | /* Private constants ---------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 143 | /** @defgroup SMBUS_Private_Define SMBUS Private Constants |
bogdanm | 0:9b334a45a8ff | 144 | * @{ |
bogdanm | 0:9b334a45a8ff | 145 | */ |
bogdanm | 0:9b334a45a8ff | 146 | #define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */ |
bogdanm | 0:9b334a45a8ff | 147 | #define HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */ |
bogdanm | 0:9b334a45a8ff | 148 | #define HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */ |
bogdanm | 0:9b334a45a8ff | 149 | #define HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */ |
bogdanm | 0:9b334a45a8ff | 150 | #define HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */ |
bogdanm | 0:9b334a45a8ff | 151 | #define HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */ |
bogdanm | 0:9b334a45a8ff | 152 | #define HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */ |
bogdanm | 0:9b334a45a8ff | 153 | #define HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */ |
bogdanm | 0:9b334a45a8ff | 154 | #define HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */ |
bogdanm | 0:9b334a45a8ff | 155 | #define MAX_NBYTE_SIZE 255 |
bogdanm | 0:9b334a45a8ff | 156 | /** |
bogdanm | 0:9b334a45a8ff | 157 | * @} |
bogdanm | 0:9b334a45a8ff | 158 | */ |
bogdanm | 0:9b334a45a8ff | 159 | |
bogdanm | 0:9b334a45a8ff | 160 | /* Private macro -------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 161 | /* Private variables ---------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 162 | /* Private function prototypes -----------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 163 | /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions |
bogdanm | 0:9b334a45a8ff | 164 | * @{ |
bogdanm | 0:9b334a45a8ff | 165 | */ |
bogdanm | 0:9b334a45a8ff | 166 | static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); |
bogdanm | 0:9b334a45a8ff | 167 | |
bogdanm | 0:9b334a45a8ff | 168 | static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); |
bogdanm | 0:9b334a45a8ff | 169 | static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); |
bogdanm | 0:9b334a45a8ff | 170 | static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus); |
bogdanm | 0:9b334a45a8ff | 171 | static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); |
bogdanm | 0:9b334a45a8ff | 172 | |
bogdanm | 0:9b334a45a8ff | 173 | static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); |
bogdanm | 0:9b334a45a8ff | 174 | /** |
bogdanm | 0:9b334a45a8ff | 175 | * @} |
bogdanm | 0:9b334a45a8ff | 176 | */ |
bogdanm | 0:9b334a45a8ff | 177 | |
bogdanm | 0:9b334a45a8ff | 178 | /* Exported functions --------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 179 | |
bogdanm | 0:9b334a45a8ff | 180 | /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions |
bogdanm | 0:9b334a45a8ff | 181 | * @{ |
bogdanm | 0:9b334a45a8ff | 182 | */ |
bogdanm | 0:9b334a45a8ff | 183 | |
bogdanm | 0:9b334a45a8ff | 184 | /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions |
bogdanm | 0:9b334a45a8ff | 185 | * @brief Initialization and Configuration functions |
bogdanm | 0:9b334a45a8ff | 186 | * |
bogdanm | 0:9b334a45a8ff | 187 | @verbatim |
bogdanm | 0:9b334a45a8ff | 188 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 189 | ##### Initialization and de-initialization functions ##### |
bogdanm | 0:9b334a45a8ff | 190 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 191 | [..] This subsection provides a set of functions allowing to initialize and |
bogdanm | 0:9b334a45a8ff | 192 | de-initialize the SMBUSx peripheral: |
bogdanm | 0:9b334a45a8ff | 193 | |
bogdanm | 0:9b334a45a8ff | 194 | (+) User must Implement HAL_SMBUS_MspInit() function in which he configures |
bogdanm | 0:9b334a45a8ff | 195 | all related peripherals resources (CLOCK, GPIO, IT and NVIC ). |
bogdanm | 0:9b334a45a8ff | 196 | |
bogdanm | 0:9b334a45a8ff | 197 | (+) Call the function HAL_SMBUS_Init() to configure the selected device with |
bogdanm | 0:9b334a45a8ff | 198 | the selected configuration: |
bogdanm | 0:9b334a45a8ff | 199 | (++) Clock Timing |
bogdanm | 0:9b334a45a8ff | 200 | (++) Bus Timeout |
bogdanm | 0:9b334a45a8ff | 201 | (++) Analog Filer mode |
bogdanm | 0:9b334a45a8ff | 202 | (++) Own Address 1 |
bogdanm | 0:9b334a45a8ff | 203 | (++) Addressing mode (Master, Slave) |
bogdanm | 0:9b334a45a8ff | 204 | (++) Dual Addressing mode |
bogdanm | 0:9b334a45a8ff | 205 | (++) Own Address 2 |
bogdanm | 0:9b334a45a8ff | 206 | (++) Own Address 2 Mask |
bogdanm | 0:9b334a45a8ff | 207 | (++) General call mode |
bogdanm | 0:9b334a45a8ff | 208 | (++) Nostretch mode |
bogdanm | 0:9b334a45a8ff | 209 | (++) Packet Error Check mode |
bogdanm | 0:9b334a45a8ff | 210 | (++) Peripheral mode |
bogdanm | 0:9b334a45a8ff | 211 | |
bogdanm | 0:9b334a45a8ff | 212 | |
bogdanm | 0:9b334a45a8ff | 213 | (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration |
bogdanm | 0:9b334a45a8ff | 214 | of the selected SMBUSx peripheral. |
bogdanm | 0:9b334a45a8ff | 215 | |
bogdanm | 0:9b334a45a8ff | 216 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 217 | * @{ |
bogdanm | 0:9b334a45a8ff | 218 | */ |
bogdanm | 0:9b334a45a8ff | 219 | |
bogdanm | 0:9b334a45a8ff | 220 | /** |
bogdanm | 0:9b334a45a8ff | 221 | * @brief Initialize the SMBUS according to the specified parameters |
bogdanm | 0:9b334a45a8ff | 222 | * in the SMBUS_InitTypeDef and initialize the associated handle. |
bogdanm | 0:9b334a45a8ff | 223 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 224 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 225 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 226 | */ |
bogdanm | 0:9b334a45a8ff | 227 | HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 228 | { |
bogdanm | 0:9b334a45a8ff | 229 | /* Check the SMBUS handle allocation */ |
bogdanm | 0:9b334a45a8ff | 230 | if(hsmbus == NULL) |
bogdanm | 0:9b334a45a8ff | 231 | { |
bogdanm | 0:9b334a45a8ff | 232 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 233 | } |
bogdanm | 0:9b334a45a8ff | 234 | |
bogdanm | 0:9b334a45a8ff | 235 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 236 | assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); |
bogdanm | 0:9b334a45a8ff | 237 | assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter)); |
bogdanm | 0:9b334a45a8ff | 238 | assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1)); |
bogdanm | 0:9b334a45a8ff | 239 | assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode)); |
bogdanm | 0:9b334a45a8ff | 240 | assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode)); |
bogdanm | 0:9b334a45a8ff | 241 | assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2)); |
bogdanm | 0:9b334a45a8ff | 242 | assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks)); |
bogdanm | 0:9b334a45a8ff | 243 | assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode)); |
bogdanm | 0:9b334a45a8ff | 244 | assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode)); |
bogdanm | 0:9b334a45a8ff | 245 | assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); |
bogdanm | 0:9b334a45a8ff | 246 | assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); |
bogdanm | 0:9b334a45a8ff | 247 | |
bogdanm | 0:9b334a45a8ff | 248 | if(hsmbus->State == HAL_SMBUS_STATE_RESET) |
bogdanm | 0:9b334a45a8ff | 249 | { |
bogdanm | 0:9b334a45a8ff | 250 | /* Allocate lock resource and initialize it */ |
bogdanm | 0:9b334a45a8ff | 251 | hsmbus->Lock = HAL_UNLOCKED; |
bogdanm | 0:9b334a45a8ff | 252 | |
bogdanm | 0:9b334a45a8ff | 253 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
bogdanm | 0:9b334a45a8ff | 254 | HAL_SMBUS_MspInit(hsmbus); |
bogdanm | 0:9b334a45a8ff | 255 | } |
bogdanm | 0:9b334a45a8ff | 256 | |
bogdanm | 0:9b334a45a8ff | 257 | hsmbus->State = HAL_SMBUS_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 258 | |
bogdanm | 0:9b334a45a8ff | 259 | /* Disable the selected SMBUS peripheral */ |
bogdanm | 0:9b334a45a8ff | 260 | __HAL_SMBUS_DISABLE(hsmbus); |
bogdanm | 0:9b334a45a8ff | 261 | |
bogdanm | 0:9b334a45a8ff | 262 | /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ |
bogdanm | 0:9b334a45a8ff | 263 | /* Configure SMBUSx: Frequency range */ |
bogdanm | 0:9b334a45a8ff | 264 | hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK; |
bogdanm | 0:9b334a45a8ff | 265 | |
bogdanm | 0:9b334a45a8ff | 266 | /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ |
bogdanm | 0:9b334a45a8ff | 267 | /* Configure SMBUSx: Bus Timeout */ |
bogdanm | 0:9b334a45a8ff | 268 | hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN; |
bogdanm | 0:9b334a45a8ff | 269 | hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN; |
bogdanm | 0:9b334a45a8ff | 270 | hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout; |
bogdanm | 0:9b334a45a8ff | 271 | |
bogdanm | 0:9b334a45a8ff | 272 | /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/ |
bogdanm | 0:9b334a45a8ff | 273 | /* Configure SMBUSx: Own Address1 and ack own address1 mode */ |
bogdanm | 0:9b334a45a8ff | 274 | hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; |
bogdanm | 0:9b334a45a8ff | 275 | |
bogdanm | 0:9b334a45a8ff | 276 | if(hsmbus->Init.OwnAddress1 != 0) |
bogdanm | 0:9b334a45a8ff | 277 | { |
bogdanm | 0:9b334a45a8ff | 278 | if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) |
bogdanm | 0:9b334a45a8ff | 279 | { |
bogdanm | 0:9b334a45a8ff | 280 | hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); |
bogdanm | 0:9b334a45a8ff | 281 | } |
bogdanm | 0:9b334a45a8ff | 282 | else /* SMBUS_ADDRESSINGMODE_10BIT */ |
bogdanm | 0:9b334a45a8ff | 283 | { |
bogdanm | 0:9b334a45a8ff | 284 | hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1); |
bogdanm | 0:9b334a45a8ff | 285 | } |
bogdanm | 0:9b334a45a8ff | 286 | } |
bogdanm | 0:9b334a45a8ff | 287 | |
bogdanm | 0:9b334a45a8ff | 288 | /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ |
bogdanm | 0:9b334a45a8ff | 289 | /* Configure SMBUSx: Addressing Master mode */ |
bogdanm | 0:9b334a45a8ff | 290 | if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) |
bogdanm | 0:9b334a45a8ff | 291 | { |
bogdanm | 0:9b334a45a8ff | 292 | hsmbus->Instance->CR2 = (I2C_CR2_ADD10); |
bogdanm | 0:9b334a45a8ff | 293 | } |
bogdanm | 0:9b334a45a8ff | 294 | /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ |
bogdanm | 0:9b334a45a8ff | 295 | /* AUTOEND and NACK bit will be manage during Transfer process */ |
bogdanm | 0:9b334a45a8ff | 296 | hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); |
bogdanm | 0:9b334a45a8ff | 297 | |
bogdanm | 0:9b334a45a8ff | 298 | /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ |
bogdanm | 0:9b334a45a8ff | 299 | /* Configure SMBUSx: Dual mode and Own Address2 */ |
bogdanm | 0:9b334a45a8ff | 300 | hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8)); |
bogdanm | 0:9b334a45a8ff | 301 | |
bogdanm | 0:9b334a45a8ff | 302 | /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ |
bogdanm | 0:9b334a45a8ff | 303 | /* Configure SMBUSx: Generalcall and NoStretch mode */ |
bogdanm | 0:9b334a45a8ff | 304 | hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); |
bogdanm | 0:9b334a45a8ff | 305 | |
bogdanm | 0:9b334a45a8ff | 306 | /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ |
bogdanm | 0:9b334a45a8ff | 307 | if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) |
bogdanm | 0:9b334a45a8ff | 308 | && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) ) |
bogdanm | 0:9b334a45a8ff | 309 | { |
bogdanm | 0:9b334a45a8ff | 310 | hsmbus->Instance->CR1 |= I2C_CR1_SBC; |
bogdanm | 0:9b334a45a8ff | 311 | } |
bogdanm | 0:9b334a45a8ff | 312 | |
bogdanm | 0:9b334a45a8ff | 313 | /* Enable the selected SMBUS peripheral */ |
bogdanm | 0:9b334a45a8ff | 314 | __HAL_SMBUS_ENABLE(hsmbus); |
bogdanm | 0:9b334a45a8ff | 315 | |
bogdanm | 0:9b334a45a8ff | 316 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
bogdanm | 0:9b334a45a8ff | 317 | hsmbus->PreviousState = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 318 | hsmbus->State = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 319 | |
bogdanm | 0:9b334a45a8ff | 320 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 321 | } |
bogdanm | 0:9b334a45a8ff | 322 | |
bogdanm | 0:9b334a45a8ff | 323 | /** |
bogdanm | 0:9b334a45a8ff | 324 | * @brief DeInitialize the SMBUS peripheral. |
bogdanm | 0:9b334a45a8ff | 325 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 326 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 327 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 328 | */ |
bogdanm | 0:9b334a45a8ff | 329 | HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 330 | { |
bogdanm | 0:9b334a45a8ff | 331 | /* Check the SMBUS handle allocation */ |
bogdanm | 0:9b334a45a8ff | 332 | if(hsmbus == NULL) |
bogdanm | 0:9b334a45a8ff | 333 | { |
bogdanm | 0:9b334a45a8ff | 334 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 335 | } |
bogdanm | 0:9b334a45a8ff | 336 | |
bogdanm | 0:9b334a45a8ff | 337 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 338 | assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); |
bogdanm | 0:9b334a45a8ff | 339 | |
bogdanm | 0:9b334a45a8ff | 340 | hsmbus->State = HAL_SMBUS_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 341 | |
bogdanm | 0:9b334a45a8ff | 342 | /* Disable the SMBUS Peripheral Clock */ |
bogdanm | 0:9b334a45a8ff | 343 | __HAL_SMBUS_DISABLE(hsmbus); |
bogdanm | 0:9b334a45a8ff | 344 | |
bogdanm | 0:9b334a45a8ff | 345 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
bogdanm | 0:9b334a45a8ff | 346 | HAL_SMBUS_MspDeInit(hsmbus); |
bogdanm | 0:9b334a45a8ff | 347 | |
bogdanm | 0:9b334a45a8ff | 348 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
bogdanm | 0:9b334a45a8ff | 349 | hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; |
bogdanm | 0:9b334a45a8ff | 350 | hsmbus->State = HAL_SMBUS_STATE_RESET; |
bogdanm | 0:9b334a45a8ff | 351 | |
bogdanm | 0:9b334a45a8ff | 352 | /* Release Lock */ |
bogdanm | 0:9b334a45a8ff | 353 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 354 | |
bogdanm | 0:9b334a45a8ff | 355 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 356 | } |
bogdanm | 0:9b334a45a8ff | 357 | |
bogdanm | 0:9b334a45a8ff | 358 | /** |
bogdanm | 0:9b334a45a8ff | 359 | * @brief Initialize the SMBUS MSP. |
bogdanm | 0:9b334a45a8ff | 360 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 361 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 362 | * @retval None |
bogdanm | 0:9b334a45a8ff | 363 | */ |
bogdanm | 0:9b334a45a8ff | 364 | __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 365 | { |
bogdanm | 0:9b334a45a8ff | 366 | /* NOTE : This function should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 367 | the HAL_SMBUS_MspInit could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 368 | */ |
bogdanm | 0:9b334a45a8ff | 369 | } |
bogdanm | 0:9b334a45a8ff | 370 | |
bogdanm | 0:9b334a45a8ff | 371 | /** |
bogdanm | 0:9b334a45a8ff | 372 | * @brief DeInitialize the SMBUS MSP. |
bogdanm | 0:9b334a45a8ff | 373 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 374 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 375 | * @retval None |
bogdanm | 0:9b334a45a8ff | 376 | */ |
bogdanm | 0:9b334a45a8ff | 377 | __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 378 | { |
bogdanm | 0:9b334a45a8ff | 379 | /* NOTE : This function should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 380 | the HAL_SMBUS_MspDeInit could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 381 | */ |
bogdanm | 0:9b334a45a8ff | 382 | } |
bogdanm | 0:9b334a45a8ff | 383 | |
bogdanm | 0:9b334a45a8ff | 384 | /** |
bogdanm | 0:9b334a45a8ff | 385 | * @} |
bogdanm | 0:9b334a45a8ff | 386 | */ |
bogdanm | 0:9b334a45a8ff | 387 | |
bogdanm | 0:9b334a45a8ff | 388 | /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions |
bogdanm | 0:9b334a45a8ff | 389 | * @brief Data transfers functions |
bogdanm | 0:9b334a45a8ff | 390 | * |
bogdanm | 0:9b334a45a8ff | 391 | @verbatim |
bogdanm | 0:9b334a45a8ff | 392 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 393 | ##### IO operation functions ##### |
bogdanm | 0:9b334a45a8ff | 394 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 395 | [..] |
bogdanm | 0:9b334a45a8ff | 396 | This subsection provides a set of functions allowing to manage the SMBUS data |
bogdanm | 0:9b334a45a8ff | 397 | transfers. |
bogdanm | 0:9b334a45a8ff | 398 | |
bogdanm | 0:9b334a45a8ff | 399 | (#) Blocking mode function to check if device is ready for usage is : |
bogdanm | 0:9b334a45a8ff | 400 | (++) HAL_SMBUS_IsDeviceReady() |
bogdanm | 0:9b334a45a8ff | 401 | |
bogdanm | 0:9b334a45a8ff | 402 | (#) There is only one mode of transfer: |
bogdanm | 0:9b334a45a8ff | 403 | (++) No-Blocking mode : The communication is performed using Interrupts. |
bogdanm | 0:9b334a45a8ff | 404 | These functions return the status of the transfer startup. |
bogdanm | 0:9b334a45a8ff | 405 | The end of the data processing will be indicated through the |
bogdanm | 0:9b334a45a8ff | 406 | dedicated SMBUS IRQ when using Interrupt mode. |
bogdanm | 0:9b334a45a8ff | 407 | |
bogdanm | 0:9b334a45a8ff | 408 | (#) No-Blocking mode functions with Interrupt are : |
bogdanm | 0:9b334a45a8ff | 409 | (++) HAL_SMBUS_Master_Transmit_IT() |
bogdanm | 0:9b334a45a8ff | 410 | (++) HAL_SMBUS_Master_Receive_IT() |
bogdanm | 0:9b334a45a8ff | 411 | (++) HAL_SMBUS_Slave_Transmit_IT() |
bogdanm | 0:9b334a45a8ff | 412 | (++) HAL_SMBUS_Slave_Receive_IT() |
bogdanm | 0:9b334a45a8ff | 413 | (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT() |
bogdanm | 0:9b334a45a8ff | 414 | (++) HAL_SMBUS_DisableListen_IT() |
bogdanm | 0:9b334a45a8ff | 415 | (++) HAL_SMBUS_EnableAlert_IT() |
bogdanm | 0:9b334a45a8ff | 416 | (++) HAL_SMBUS_DisableAlert_IT() |
bogdanm | 0:9b334a45a8ff | 417 | |
bogdanm | 0:9b334a45a8ff | 418 | (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: |
bogdanm | 0:9b334a45a8ff | 419 | (++) HAL_SMBUS_MasterTxCpltCallback() |
bogdanm | 0:9b334a45a8ff | 420 | (++) HAL_SMBUS_MasterRxCpltCallback() |
bogdanm | 0:9b334a45a8ff | 421 | (++) HAL_SMBUS_SlaveTxCpltCallback() |
bogdanm | 0:9b334a45a8ff | 422 | (++) HAL_SMBUS_SlaveRxCpltCallback() |
bogdanm | 0:9b334a45a8ff | 423 | (++) HAL_SMBUS_AddrCallback() |
bogdanm | 0:9b334a45a8ff | 424 | (++) HAL_SMBUS_ListenCpltCallback() |
bogdanm | 0:9b334a45a8ff | 425 | (++) HAL_SMBUS_ErrorCallback() |
bogdanm | 0:9b334a45a8ff | 426 | |
bogdanm | 0:9b334a45a8ff | 427 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 428 | * @{ |
bogdanm | 0:9b334a45a8ff | 429 | */ |
bogdanm | 0:9b334a45a8ff | 430 | |
bogdanm | 0:9b334a45a8ff | 431 | /** |
bogdanm | 0:9b334a45a8ff | 432 | * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. |
bogdanm | 0:9b334a45a8ff | 433 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 434 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 435 | * @param DevAddress: Target device address |
bogdanm | 0:9b334a45a8ff | 436 | * @param pData: Pointer to data buffer |
bogdanm | 0:9b334a45a8ff | 437 | * @param Size: Amount of data to be sent |
bogdanm | 0:9b334a45a8ff | 438 | * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition |
bogdanm | 0:9b334a45a8ff | 439 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 440 | */ |
bogdanm | 0:9b334a45a8ff | 441 | HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
bogdanm | 0:9b334a45a8ff | 442 | { |
bogdanm | 0:9b334a45a8ff | 443 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 444 | assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
bogdanm | 0:9b334a45a8ff | 445 | |
bogdanm | 0:9b334a45a8ff | 446 | if(hsmbus->State == HAL_SMBUS_STATE_READY) |
bogdanm | 0:9b334a45a8ff | 447 | { |
bogdanm | 0:9b334a45a8ff | 448 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 449 | __HAL_LOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 450 | |
bogdanm | 0:9b334a45a8ff | 451 | hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; |
bogdanm | 0:9b334a45a8ff | 452 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
bogdanm | 0:9b334a45a8ff | 453 | /* Prepare transfer parameters */ |
bogdanm | 0:9b334a45a8ff | 454 | hsmbus->pBuffPtr = pData; |
bogdanm | 0:9b334a45a8ff | 455 | hsmbus->XferCount = Size; |
bogdanm | 0:9b334a45a8ff | 456 | hsmbus->XferOptions = XferOptions; |
bogdanm | 0:9b334a45a8ff | 457 | |
bogdanm | 0:9b334a45a8ff | 458 | /* In case of Quick command, remove autoend mode */ |
bogdanm | 0:9b334a45a8ff | 459 | /* Manage the stop generation by software */ |
bogdanm | 0:9b334a45a8ff | 460 | if(hsmbus->pBuffPtr == NULL) |
bogdanm | 0:9b334a45a8ff | 461 | { |
bogdanm | 0:9b334a45a8ff | 462 | hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; |
bogdanm | 0:9b334a45a8ff | 463 | } |
bogdanm | 0:9b334a45a8ff | 464 | |
bogdanm | 0:9b334a45a8ff | 465 | if(Size > MAX_NBYTE_SIZE) |
bogdanm | 0:9b334a45a8ff | 466 | { |
bogdanm | 0:9b334a45a8ff | 467 | hsmbus->XferSize = MAX_NBYTE_SIZE; |
bogdanm | 0:9b334a45a8ff | 468 | } |
bogdanm | 0:9b334a45a8ff | 469 | else |
bogdanm | 0:9b334a45a8ff | 470 | { |
bogdanm | 0:9b334a45a8ff | 471 | hsmbus->XferSize = Size; |
bogdanm | 0:9b334a45a8ff | 472 | } |
bogdanm | 0:9b334a45a8ff | 473 | |
bogdanm | 0:9b334a45a8ff | 474 | /* Send Slave Address */ |
bogdanm | 0:9b334a45a8ff | 475 | /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ |
bogdanm | 0:9b334a45a8ff | 476 | if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) |
bogdanm | 0:9b334a45a8ff | 477 | { |
bogdanm | 0:9b334a45a8ff | 478 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); |
bogdanm | 0:9b334a45a8ff | 479 | } |
bogdanm | 0:9b334a45a8ff | 480 | else |
bogdanm | 0:9b334a45a8ff | 481 | { |
bogdanm | 0:9b334a45a8ff | 482 | /* If transfer direction not change, do not generate Restart Condition */ |
bogdanm | 0:9b334a45a8ff | 483 | /* Mean Previous state is same as current state */ |
bogdanm | 0:9b334a45a8ff | 484 | if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
bogdanm | 0:9b334a45a8ff | 485 | { |
bogdanm | 0:9b334a45a8ff | 486 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 487 | } |
bogdanm | 0:9b334a45a8ff | 488 | /* Else transfer direction change, so generate Restart with new transfer direction */ |
bogdanm | 0:9b334a45a8ff | 489 | else |
bogdanm | 0:9b334a45a8ff | 490 | { |
bogdanm | 0:9b334a45a8ff | 491 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); |
bogdanm | 0:9b334a45a8ff | 492 | } |
bogdanm | 0:9b334a45a8ff | 493 | |
bogdanm | 0:9b334a45a8ff | 494 | /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ |
bogdanm | 0:9b334a45a8ff | 495 | /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ |
bogdanm | 0:9b334a45a8ff | 496 | if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) |
bogdanm | 0:9b334a45a8ff | 497 | { |
bogdanm | 0:9b334a45a8ff | 498 | hsmbus->XferSize--; |
bogdanm | 0:9b334a45a8ff | 499 | hsmbus->XferCount--; |
bogdanm | 0:9b334a45a8ff | 500 | } |
bogdanm | 0:9b334a45a8ff | 501 | } |
bogdanm | 0:9b334a45a8ff | 502 | |
bogdanm | 0:9b334a45a8ff | 503 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 504 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 505 | |
bogdanm | 0:9b334a45a8ff | 506 | /* Note : The SMBUS interrupts must be enabled after unlocking current process |
bogdanm | 0:9b334a45a8ff | 507 | to avoid the risk of SMBUS interrupt handle execution before current |
bogdanm | 0:9b334a45a8ff | 508 | process unlock */ |
bogdanm | 0:9b334a45a8ff | 509 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); |
bogdanm | 0:9b334a45a8ff | 510 | |
bogdanm | 0:9b334a45a8ff | 511 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 512 | } |
bogdanm | 0:9b334a45a8ff | 513 | else |
bogdanm | 0:9b334a45a8ff | 514 | { |
bogdanm | 0:9b334a45a8ff | 515 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 516 | } |
bogdanm | 0:9b334a45a8ff | 517 | } |
bogdanm | 0:9b334a45a8ff | 518 | |
bogdanm | 0:9b334a45a8ff | 519 | /** |
bogdanm | 0:9b334a45a8ff | 520 | * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. |
bogdanm | 0:9b334a45a8ff | 521 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 522 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 523 | * @param DevAddress: Target device address |
bogdanm | 0:9b334a45a8ff | 524 | * @param pData: Pointer to data buffer |
bogdanm | 0:9b334a45a8ff | 525 | * @param Size: Amount of data to be sent |
bogdanm | 0:9b334a45a8ff | 526 | * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition |
bogdanm | 0:9b334a45a8ff | 527 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 528 | */ |
bogdanm | 0:9b334a45a8ff | 529 | HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
bogdanm | 0:9b334a45a8ff | 530 | { |
bogdanm | 0:9b334a45a8ff | 531 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 532 | assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
bogdanm | 0:9b334a45a8ff | 533 | |
bogdanm | 0:9b334a45a8ff | 534 | if(hsmbus->State == HAL_SMBUS_STATE_READY) |
bogdanm | 0:9b334a45a8ff | 535 | { |
bogdanm | 0:9b334a45a8ff | 536 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 537 | __HAL_LOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 538 | |
bogdanm | 0:9b334a45a8ff | 539 | hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; |
bogdanm | 0:9b334a45a8ff | 540 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
bogdanm | 0:9b334a45a8ff | 541 | |
bogdanm | 0:9b334a45a8ff | 542 | /* Prepare transfer parameters */ |
bogdanm | 0:9b334a45a8ff | 543 | hsmbus->pBuffPtr = pData; |
bogdanm | 0:9b334a45a8ff | 544 | hsmbus->XferCount = Size; |
bogdanm | 0:9b334a45a8ff | 545 | hsmbus->XferOptions = XferOptions; |
bogdanm | 0:9b334a45a8ff | 546 | |
bogdanm | 0:9b334a45a8ff | 547 | /* In case of Quick command, remove autoend mode */ |
bogdanm | 0:9b334a45a8ff | 548 | /* Manage the stop generation by software */ |
bogdanm | 0:9b334a45a8ff | 549 | if(hsmbus->pBuffPtr == NULL) |
bogdanm | 0:9b334a45a8ff | 550 | { |
bogdanm | 0:9b334a45a8ff | 551 | hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; |
bogdanm | 0:9b334a45a8ff | 552 | } |
bogdanm | 0:9b334a45a8ff | 553 | |
bogdanm | 0:9b334a45a8ff | 554 | if(Size > MAX_NBYTE_SIZE) |
bogdanm | 0:9b334a45a8ff | 555 | { |
bogdanm | 0:9b334a45a8ff | 556 | hsmbus->XferSize = MAX_NBYTE_SIZE; |
bogdanm | 0:9b334a45a8ff | 557 | } |
bogdanm | 0:9b334a45a8ff | 558 | else |
bogdanm | 0:9b334a45a8ff | 559 | { |
bogdanm | 0:9b334a45a8ff | 560 | hsmbus->XferSize = Size; |
bogdanm | 0:9b334a45a8ff | 561 | } |
bogdanm | 0:9b334a45a8ff | 562 | |
bogdanm | 0:9b334a45a8ff | 563 | /* Send Slave Address */ |
bogdanm | 0:9b334a45a8ff | 564 | /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ |
bogdanm | 0:9b334a45a8ff | 565 | if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) |
bogdanm | 0:9b334a45a8ff | 566 | { |
bogdanm | 0:9b334a45a8ff | 567 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); |
bogdanm | 0:9b334a45a8ff | 568 | } |
bogdanm | 0:9b334a45a8ff | 569 | else |
bogdanm | 0:9b334a45a8ff | 570 | { |
bogdanm | 0:9b334a45a8ff | 571 | /* If transfer direction not change, do not generate Restart Condition */ |
bogdanm | 0:9b334a45a8ff | 572 | /* Mean Previous state is same as current state */ |
bogdanm | 0:9b334a45a8ff | 573 | if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
bogdanm | 0:9b334a45a8ff | 574 | { |
bogdanm | 0:9b334a45a8ff | 575 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 576 | } |
bogdanm | 0:9b334a45a8ff | 577 | /* Else transfer direction change, so generate Restart with new transfer direction */ |
bogdanm | 0:9b334a45a8ff | 578 | else |
bogdanm | 0:9b334a45a8ff | 579 | { |
bogdanm | 0:9b334a45a8ff | 580 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); |
bogdanm | 0:9b334a45a8ff | 581 | } |
bogdanm | 0:9b334a45a8ff | 582 | } |
bogdanm | 0:9b334a45a8ff | 583 | |
bogdanm | 0:9b334a45a8ff | 584 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 585 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 586 | |
bogdanm | 0:9b334a45a8ff | 587 | /* Note : The SMBUS interrupts must be enabled after unlocking current process |
bogdanm | 0:9b334a45a8ff | 588 | to avoid the risk of SMBUS interrupt handle execution before current |
bogdanm | 0:9b334a45a8ff | 589 | process unlock */ |
bogdanm | 0:9b334a45a8ff | 590 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); |
bogdanm | 0:9b334a45a8ff | 591 | |
bogdanm | 0:9b334a45a8ff | 592 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 593 | } |
bogdanm | 0:9b334a45a8ff | 594 | else |
bogdanm | 0:9b334a45a8ff | 595 | { |
bogdanm | 0:9b334a45a8ff | 596 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 597 | } |
bogdanm | 0:9b334a45a8ff | 598 | } |
bogdanm | 0:9b334a45a8ff | 599 | |
bogdanm | 0:9b334a45a8ff | 600 | /** |
bogdanm | 0:9b334a45a8ff | 601 | * @brief Abort a master/host SMBUS process communication with Interrupt. |
bogdanm | 0:9b334a45a8ff | 602 | * @note This abort can be called only if state is ready |
bogdanm | 0:9b334a45a8ff | 603 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 604 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 605 | * @param DevAddress: Target device address |
bogdanm | 0:9b334a45a8ff | 606 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 607 | */ |
bogdanm | 0:9b334a45a8ff | 608 | HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) |
bogdanm | 0:9b334a45a8ff | 609 | { |
bogdanm | 0:9b334a45a8ff | 610 | if(hsmbus->State == HAL_SMBUS_STATE_READY) |
bogdanm | 0:9b334a45a8ff | 611 | { |
bogdanm | 0:9b334a45a8ff | 612 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 613 | __HAL_LOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 614 | |
bogdanm | 0:9b334a45a8ff | 615 | /* Keep the same state as previous */ |
bogdanm | 0:9b334a45a8ff | 616 | /* to perform as well the call of the corresponding end of transfer callback */ |
bogdanm | 0:9b334a45a8ff | 617 | if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
bogdanm | 0:9b334a45a8ff | 618 | { |
bogdanm | 0:9b334a45a8ff | 619 | hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; |
bogdanm | 0:9b334a45a8ff | 620 | } |
bogdanm | 0:9b334a45a8ff | 621 | else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
bogdanm | 0:9b334a45a8ff | 622 | { |
bogdanm | 0:9b334a45a8ff | 623 | hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; |
bogdanm | 0:9b334a45a8ff | 624 | } |
bogdanm | 0:9b334a45a8ff | 625 | else |
bogdanm | 0:9b334a45a8ff | 626 | { |
bogdanm | 0:9b334a45a8ff | 627 | /* Wrong usage of abort function */ |
bogdanm | 0:9b334a45a8ff | 628 | /* This function should be used only in case of abort monitored by master device */ |
bogdanm | 0:9b334a45a8ff | 629 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 630 | } |
bogdanm | 0:9b334a45a8ff | 631 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
bogdanm | 0:9b334a45a8ff | 632 | |
bogdanm | 0:9b334a45a8ff | 633 | /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ |
bogdanm | 0:9b334a45a8ff | 634 | /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ |
bogdanm | 0:9b334a45a8ff | 635 | SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 636 | |
bogdanm | 0:9b334a45a8ff | 637 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 638 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 639 | |
bogdanm | 0:9b334a45a8ff | 640 | /* Note : The SMBUS interrupts must be enabled after unlocking current process |
bogdanm | 0:9b334a45a8ff | 641 | to avoid the risk of SMBUS interrupt handle execution before current |
bogdanm | 0:9b334a45a8ff | 642 | process unlock */ |
bogdanm | 0:9b334a45a8ff | 643 | if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
bogdanm | 0:9b334a45a8ff | 644 | { |
bogdanm | 0:9b334a45a8ff | 645 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); |
bogdanm | 0:9b334a45a8ff | 646 | } |
bogdanm | 0:9b334a45a8ff | 647 | else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
bogdanm | 0:9b334a45a8ff | 648 | { |
bogdanm | 0:9b334a45a8ff | 649 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); |
bogdanm | 0:9b334a45a8ff | 650 | } |
bogdanm | 0:9b334a45a8ff | 651 | |
bogdanm | 0:9b334a45a8ff | 652 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 653 | } |
bogdanm | 0:9b334a45a8ff | 654 | else |
bogdanm | 0:9b334a45a8ff | 655 | { |
bogdanm | 0:9b334a45a8ff | 656 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 657 | } |
bogdanm | 0:9b334a45a8ff | 658 | } |
bogdanm | 0:9b334a45a8ff | 659 | |
bogdanm | 0:9b334a45a8ff | 660 | /** |
bogdanm | 0:9b334a45a8ff | 661 | * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. |
bogdanm | 0:9b334a45a8ff | 662 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 663 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 664 | * @param pData: Pointer to data buffer |
bogdanm | 0:9b334a45a8ff | 665 | * @param Size: Amount of data to be sent |
bogdanm | 0:9b334a45a8ff | 666 | * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition |
bogdanm | 0:9b334a45a8ff | 667 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 668 | */ |
bogdanm | 0:9b334a45a8ff | 669 | HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
bogdanm | 0:9b334a45a8ff | 670 | { |
bogdanm | 0:9b334a45a8ff | 671 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 672 | assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
bogdanm | 0:9b334a45a8ff | 673 | |
bogdanm | 0:9b334a45a8ff | 674 | if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) |
bogdanm | 0:9b334a45a8ff | 675 | { |
bogdanm | 0:9b334a45a8ff | 676 | if((pData == NULL) || (Size == 0)) |
bogdanm | 0:9b334a45a8ff | 677 | { |
bogdanm | 0:9b334a45a8ff | 678 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 679 | } |
bogdanm | 0:9b334a45a8ff | 680 | |
bogdanm | 0:9b334a45a8ff | 681 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
bogdanm | 0:9b334a45a8ff | 682 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX); |
bogdanm | 0:9b334a45a8ff | 683 | |
bogdanm | 0:9b334a45a8ff | 684 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 685 | __HAL_LOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 686 | |
bogdanm | 0:9b334a45a8ff | 687 | hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX; |
bogdanm | 0:9b334a45a8ff | 688 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
bogdanm | 0:9b334a45a8ff | 689 | |
bogdanm | 0:9b334a45a8ff | 690 | /* Set SBC bit to manage Acknowledge at each bit */ |
bogdanm | 0:9b334a45a8ff | 691 | hsmbus->Instance->CR1 |= I2C_CR1_SBC; |
bogdanm | 0:9b334a45a8ff | 692 | |
bogdanm | 0:9b334a45a8ff | 693 | /* Enable Address Acknowledge */ |
bogdanm | 0:9b334a45a8ff | 694 | hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; |
bogdanm | 0:9b334a45a8ff | 695 | |
bogdanm | 0:9b334a45a8ff | 696 | /* Prepare transfer parameters */ |
bogdanm | 0:9b334a45a8ff | 697 | hsmbus->pBuffPtr = pData; |
bogdanm | 0:9b334a45a8ff | 698 | hsmbus->XferSize = Size; |
bogdanm | 0:9b334a45a8ff | 699 | hsmbus->XferCount = Size; |
bogdanm | 0:9b334a45a8ff | 700 | hsmbus->XferOptions = XferOptions; |
bogdanm | 0:9b334a45a8ff | 701 | |
bogdanm | 0:9b334a45a8ff | 702 | if(Size > MAX_NBYTE_SIZE) |
bogdanm | 0:9b334a45a8ff | 703 | { |
bogdanm | 0:9b334a45a8ff | 704 | hsmbus->XferSize = MAX_NBYTE_SIZE; |
bogdanm | 0:9b334a45a8ff | 705 | } |
bogdanm | 0:9b334a45a8ff | 706 | else |
bogdanm | 0:9b334a45a8ff | 707 | { |
bogdanm | 0:9b334a45a8ff | 708 | hsmbus->XferSize = Size; |
bogdanm | 0:9b334a45a8ff | 709 | } |
bogdanm | 0:9b334a45a8ff | 710 | |
bogdanm | 0:9b334a45a8ff | 711 | /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ |
bogdanm | 0:9b334a45a8ff | 712 | if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) |
bogdanm | 0:9b334a45a8ff | 713 | { |
bogdanm | 0:9b334a45a8ff | 714 | SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 715 | } |
bogdanm | 0:9b334a45a8ff | 716 | else |
bogdanm | 0:9b334a45a8ff | 717 | { |
bogdanm | 0:9b334a45a8ff | 718 | /* Set NBYTE to transmit */ |
bogdanm | 0:9b334a45a8ff | 719 | SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 720 | |
bogdanm | 0:9b334a45a8ff | 721 | /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ |
bogdanm | 0:9b334a45a8ff | 722 | /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ |
bogdanm | 0:9b334a45a8ff | 723 | if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) |
bogdanm | 0:9b334a45a8ff | 724 | { |
bogdanm | 0:9b334a45a8ff | 725 | hsmbus->XferSize--; |
bogdanm | 0:9b334a45a8ff | 726 | hsmbus->XferCount--; |
bogdanm | 0:9b334a45a8ff | 727 | } |
bogdanm | 0:9b334a45a8ff | 728 | } |
bogdanm | 0:9b334a45a8ff | 729 | |
bogdanm | 0:9b334a45a8ff | 730 | /* Clear ADDR flag after prepare the transfer parameters */ |
bogdanm | 0:9b334a45a8ff | 731 | /* This action will generate an acknowledge to the HOST */ |
bogdanm | 0:9b334a45a8ff | 732 | __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); |
bogdanm | 0:9b334a45a8ff | 733 | |
bogdanm | 0:9b334a45a8ff | 734 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 735 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 736 | |
bogdanm | 0:9b334a45a8ff | 737 | /* Note : The SMBUS interrupts must be enabled after unlocking current process |
bogdanm | 0:9b334a45a8ff | 738 | to avoid the risk of SMBUS interrupt handle execution before current |
bogdanm | 0:9b334a45a8ff | 739 | process unlock */ |
bogdanm | 0:9b334a45a8ff | 740 | /* REnable ADDR interrupt */ |
bogdanm | 0:9b334a45a8ff | 741 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR); |
bogdanm | 0:9b334a45a8ff | 742 | |
bogdanm | 0:9b334a45a8ff | 743 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 744 | } |
bogdanm | 0:9b334a45a8ff | 745 | else |
bogdanm | 0:9b334a45a8ff | 746 | { |
bogdanm | 0:9b334a45a8ff | 747 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 748 | } |
bogdanm | 0:9b334a45a8ff | 749 | } |
bogdanm | 0:9b334a45a8ff | 750 | |
bogdanm | 0:9b334a45a8ff | 751 | /** |
bogdanm | 0:9b334a45a8ff | 752 | * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. |
bogdanm | 0:9b334a45a8ff | 753 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 754 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 755 | * @param pData: Pointer to data buffer |
bogdanm | 0:9b334a45a8ff | 756 | * @param Size: Amount of data to be sent |
bogdanm | 0:9b334a45a8ff | 757 | * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition |
bogdanm | 0:9b334a45a8ff | 758 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 759 | */ |
bogdanm | 0:9b334a45a8ff | 760 | HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
bogdanm | 0:9b334a45a8ff | 761 | { |
bogdanm | 0:9b334a45a8ff | 762 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 763 | assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
bogdanm | 0:9b334a45a8ff | 764 | |
bogdanm | 0:9b334a45a8ff | 765 | if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) |
bogdanm | 0:9b334a45a8ff | 766 | { |
bogdanm | 0:9b334a45a8ff | 767 | if((pData == NULL) || (Size == 0)) |
bogdanm | 0:9b334a45a8ff | 768 | { |
bogdanm | 0:9b334a45a8ff | 769 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 770 | } |
bogdanm | 0:9b334a45a8ff | 771 | |
bogdanm | 0:9b334a45a8ff | 772 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
bogdanm | 0:9b334a45a8ff | 773 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX); |
bogdanm | 0:9b334a45a8ff | 774 | |
bogdanm | 0:9b334a45a8ff | 775 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 776 | __HAL_LOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 777 | |
bogdanm | 0:9b334a45a8ff | 778 | hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX; |
bogdanm | 0:9b334a45a8ff | 779 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
bogdanm | 0:9b334a45a8ff | 780 | |
bogdanm | 0:9b334a45a8ff | 781 | /* Set SBC bit to manage Acknowledge at each bit */ |
bogdanm | 0:9b334a45a8ff | 782 | hsmbus->Instance->CR1 |= I2C_CR1_SBC; |
bogdanm | 0:9b334a45a8ff | 783 | |
bogdanm | 0:9b334a45a8ff | 784 | /* Enable Address Acknowledge */ |
bogdanm | 0:9b334a45a8ff | 785 | hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; |
bogdanm | 0:9b334a45a8ff | 786 | |
bogdanm | 0:9b334a45a8ff | 787 | /* Prepare transfer parameters */ |
bogdanm | 0:9b334a45a8ff | 788 | hsmbus->pBuffPtr = pData; |
bogdanm | 0:9b334a45a8ff | 789 | hsmbus->XferSize = Size; |
bogdanm | 0:9b334a45a8ff | 790 | hsmbus->XferCount = Size; |
bogdanm | 0:9b334a45a8ff | 791 | hsmbus->XferOptions = XferOptions; |
bogdanm | 0:9b334a45a8ff | 792 | |
bogdanm | 0:9b334a45a8ff | 793 | /* Set NBYTE to receive */ |
bogdanm | 0:9b334a45a8ff | 794 | /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */ |
bogdanm | 0:9b334a45a8ff | 795 | /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ |
bogdanm | 0:9b334a45a8ff | 796 | /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ |
bogdanm | 0:9b334a45a8ff | 797 | /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ |
bogdanm | 0:9b334a45a8ff | 798 | if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) |
bogdanm | 0:9b334a45a8ff | 799 | { |
bogdanm | 0:9b334a45a8ff | 800 | SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 801 | } |
bogdanm | 0:9b334a45a8ff | 802 | else |
bogdanm | 0:9b334a45a8ff | 803 | { |
bogdanm | 0:9b334a45a8ff | 804 | SMBUS_TransferConfig(hsmbus,0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 805 | } |
bogdanm | 0:9b334a45a8ff | 806 | |
bogdanm | 0:9b334a45a8ff | 807 | /* Clear ADDR flag after prepare the transfer parameters */ |
bogdanm | 0:9b334a45a8ff | 808 | /* This action will generate an acknowledge to the HOST */ |
bogdanm | 0:9b334a45a8ff | 809 | __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); |
bogdanm | 0:9b334a45a8ff | 810 | |
bogdanm | 0:9b334a45a8ff | 811 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 812 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 813 | |
bogdanm | 0:9b334a45a8ff | 814 | /* Note : The SMBUS interrupts must be enabled after unlocking current process |
bogdanm | 0:9b334a45a8ff | 815 | to avoid the risk of SMBUS interrupt handle execution before current |
bogdanm | 0:9b334a45a8ff | 816 | process unlock */ |
bogdanm | 0:9b334a45a8ff | 817 | /* REnable ADDR interrupt */ |
bogdanm | 0:9b334a45a8ff | 818 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR); |
bogdanm | 0:9b334a45a8ff | 819 | |
bogdanm | 0:9b334a45a8ff | 820 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 821 | } |
bogdanm | 0:9b334a45a8ff | 822 | else |
bogdanm | 0:9b334a45a8ff | 823 | { |
bogdanm | 0:9b334a45a8ff | 824 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 825 | } |
bogdanm | 0:9b334a45a8ff | 826 | } |
bogdanm | 0:9b334a45a8ff | 827 | |
bogdanm | 0:9b334a45a8ff | 828 | /** |
bogdanm | 0:9b334a45a8ff | 829 | * @brief Enable the Address listen mode with Interrupt. |
bogdanm | 0:9b334a45a8ff | 830 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 831 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 832 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 833 | */ |
bogdanm | 0:9b334a45a8ff | 834 | HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 835 | { |
bogdanm | 0:9b334a45a8ff | 836 | hsmbus->State = HAL_SMBUS_STATE_LISTEN; |
bogdanm | 0:9b334a45a8ff | 837 | |
bogdanm | 0:9b334a45a8ff | 838 | /* Enable the Address Match interrupt */ |
bogdanm | 0:9b334a45a8ff | 839 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR); |
bogdanm | 0:9b334a45a8ff | 840 | |
bogdanm | 0:9b334a45a8ff | 841 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 842 | } |
bogdanm | 0:9b334a45a8ff | 843 | |
bogdanm | 0:9b334a45a8ff | 844 | /** |
bogdanm | 0:9b334a45a8ff | 845 | * @brief Disable the Address listen mode with Interrupt. |
bogdanm | 0:9b334a45a8ff | 846 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 847 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 848 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 849 | */ |
bogdanm | 0:9b334a45a8ff | 850 | HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 851 | { |
bogdanm | 0:9b334a45a8ff | 852 | /* Disable Address listen mode only if a transfer is not ongoing */ |
bogdanm | 0:9b334a45a8ff | 853 | if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) |
bogdanm | 0:9b334a45a8ff | 854 | { |
bogdanm | 0:9b334a45a8ff | 855 | hsmbus->State = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 856 | |
bogdanm | 0:9b334a45a8ff | 857 | /* Disable the Address Match interrupt */ |
bogdanm | 0:9b334a45a8ff | 858 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); |
bogdanm | 0:9b334a45a8ff | 859 | |
bogdanm | 0:9b334a45a8ff | 860 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 861 | } |
bogdanm | 0:9b334a45a8ff | 862 | else |
bogdanm | 0:9b334a45a8ff | 863 | { |
bogdanm | 0:9b334a45a8ff | 864 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 865 | } |
bogdanm | 0:9b334a45a8ff | 866 | } |
bogdanm | 0:9b334a45a8ff | 867 | |
bogdanm | 0:9b334a45a8ff | 868 | /** |
bogdanm | 0:9b334a45a8ff | 869 | * @brief Enable the SMBUS alert mode with Interrupt. |
bogdanm | 0:9b334a45a8ff | 870 | * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 871 | * the configuration information for the specified SMBUSx peripheral. |
bogdanm | 0:9b334a45a8ff | 872 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 873 | */ |
bogdanm | 0:9b334a45a8ff | 874 | HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 875 | { |
bogdanm | 0:9b334a45a8ff | 876 | /* Enable SMBus alert */ |
bogdanm | 0:9b334a45a8ff | 877 | hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; |
bogdanm | 0:9b334a45a8ff | 878 | |
bogdanm | 0:9b334a45a8ff | 879 | /* Clear ALERT flag */ |
bogdanm | 0:9b334a45a8ff | 880 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); |
bogdanm | 0:9b334a45a8ff | 881 | |
bogdanm | 0:9b334a45a8ff | 882 | /* Enable Alert Interrupt */ |
bogdanm | 0:9b334a45a8ff | 883 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT); |
bogdanm | 0:9b334a45a8ff | 884 | |
bogdanm | 0:9b334a45a8ff | 885 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 886 | } |
bogdanm | 0:9b334a45a8ff | 887 | /** |
bogdanm | 0:9b334a45a8ff | 888 | * @brief Disable the SMBUS alert mode with Interrupt. |
bogdanm | 0:9b334a45a8ff | 889 | * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 890 | * the configuration information for the specified SMBUSx peripheral. |
bogdanm | 0:9b334a45a8ff | 891 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 892 | */ |
bogdanm | 0:9b334a45a8ff | 893 | HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 894 | { |
bogdanm | 0:9b334a45a8ff | 895 | /* Enable SMBus alert */ |
bogdanm | 0:9b334a45a8ff | 896 | hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; |
bogdanm | 0:9b334a45a8ff | 897 | |
bogdanm | 0:9b334a45a8ff | 898 | /* Disable Alert Interrupt */ |
bogdanm | 0:9b334a45a8ff | 899 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT); |
bogdanm | 0:9b334a45a8ff | 900 | |
bogdanm | 0:9b334a45a8ff | 901 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 902 | } |
bogdanm | 0:9b334a45a8ff | 903 | |
bogdanm | 0:9b334a45a8ff | 904 | /** |
bogdanm | 0:9b334a45a8ff | 905 | * @brief Check if target device is ready for communication. |
bogdanm | 0:9b334a45a8ff | 906 | * @note This function is used with Memory devices |
bogdanm | 0:9b334a45a8ff | 907 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 908 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 909 | * @param DevAddress: Target device address |
bogdanm | 0:9b334a45a8ff | 910 | * @param Trials: Number of trials |
bogdanm | 0:9b334a45a8ff | 911 | * @param Timeout: Timeout duration |
bogdanm | 0:9b334a45a8ff | 912 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 913 | */ |
bogdanm | 0:9b334a45a8ff | 914 | HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) |
bogdanm | 0:9b334a45a8ff | 915 | { |
bogdanm | 0:9b334a45a8ff | 916 | uint32_t tickstart = 0; |
bogdanm | 0:9b334a45a8ff | 917 | |
bogdanm | 0:9b334a45a8ff | 918 | __IO uint32_t SMBUS_Trials = 0; |
bogdanm | 0:9b334a45a8ff | 919 | |
bogdanm | 0:9b334a45a8ff | 920 | if(hsmbus->State == HAL_SMBUS_STATE_READY) |
bogdanm | 0:9b334a45a8ff | 921 | { |
bogdanm | 0:9b334a45a8ff | 922 | if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) |
bogdanm | 0:9b334a45a8ff | 923 | { |
bogdanm | 0:9b334a45a8ff | 924 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 925 | } |
bogdanm | 0:9b334a45a8ff | 926 | |
bogdanm | 0:9b334a45a8ff | 927 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 928 | __HAL_LOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 929 | |
bogdanm | 0:9b334a45a8ff | 930 | hsmbus->State = HAL_SMBUS_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 931 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
bogdanm | 0:9b334a45a8ff | 932 | |
bogdanm | 0:9b334a45a8ff | 933 | do |
bogdanm | 0:9b334a45a8ff | 934 | { |
bogdanm | 0:9b334a45a8ff | 935 | /* Generate Start */ |
bogdanm | 0:9b334a45a8ff | 936 | hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); |
bogdanm | 0:9b334a45a8ff | 937 | |
bogdanm | 0:9b334a45a8ff | 938 | /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ |
bogdanm | 0:9b334a45a8ff | 939 | /* Wait until STOPF flag is set or a NACK flag is set*/ |
bogdanm | 0:9b334a45a8ff | 940 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 941 | while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) |
bogdanm | 0:9b334a45a8ff | 942 | { |
bogdanm | 0:9b334a45a8ff | 943 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 944 | { |
bogdanm | 0:9b334a45a8ff | 945 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 946 | { |
bogdanm | 0:9b334a45a8ff | 947 | /* Device is ready */ |
bogdanm | 0:9b334a45a8ff | 948 | hsmbus->State = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 949 | |
bogdanm | 0:9b334a45a8ff | 950 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 951 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 952 | return HAL_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 953 | } |
bogdanm | 0:9b334a45a8ff | 954 | } |
bogdanm | 0:9b334a45a8ff | 955 | } |
bogdanm | 0:9b334a45a8ff | 956 | |
bogdanm | 0:9b334a45a8ff | 957 | /* Check if the NACKF flag has not been set */ |
bogdanm | 0:9b334a45a8ff | 958 | if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) |
bogdanm | 0:9b334a45a8ff | 959 | { |
bogdanm | 0:9b334a45a8ff | 960 | /* Wait until STOPF flag is reset */ |
bogdanm | 0:9b334a45a8ff | 961 | if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) |
bogdanm | 0:9b334a45a8ff | 962 | { |
bogdanm | 0:9b334a45a8ff | 963 | return HAL_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 964 | } |
bogdanm | 0:9b334a45a8ff | 965 | |
bogdanm | 0:9b334a45a8ff | 966 | /* Clear STOP Flag */ |
bogdanm | 0:9b334a45a8ff | 967 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); |
bogdanm | 0:9b334a45a8ff | 968 | |
bogdanm | 0:9b334a45a8ff | 969 | /* Device is ready */ |
bogdanm | 0:9b334a45a8ff | 970 | hsmbus->State = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 971 | |
bogdanm | 0:9b334a45a8ff | 972 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 973 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 974 | |
bogdanm | 0:9b334a45a8ff | 975 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 976 | } |
bogdanm | 0:9b334a45a8ff | 977 | else |
bogdanm | 0:9b334a45a8ff | 978 | { |
bogdanm | 0:9b334a45a8ff | 979 | /* Wait until STOPF flag is reset */ |
bogdanm | 0:9b334a45a8ff | 980 | if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) |
bogdanm | 0:9b334a45a8ff | 981 | { |
bogdanm | 0:9b334a45a8ff | 982 | return HAL_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 983 | } |
bogdanm | 0:9b334a45a8ff | 984 | |
bogdanm | 0:9b334a45a8ff | 985 | /* Clear NACK Flag */ |
bogdanm | 0:9b334a45a8ff | 986 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); |
bogdanm | 0:9b334a45a8ff | 987 | |
bogdanm | 0:9b334a45a8ff | 988 | /* Clear STOP Flag, auto generated with autoend*/ |
bogdanm | 0:9b334a45a8ff | 989 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); |
bogdanm | 0:9b334a45a8ff | 990 | } |
bogdanm | 0:9b334a45a8ff | 991 | |
bogdanm | 0:9b334a45a8ff | 992 | /* Check if the maximum allowed number of trials has been reached */ |
bogdanm | 0:9b334a45a8ff | 993 | if (SMBUS_Trials++ == Trials) |
bogdanm | 0:9b334a45a8ff | 994 | { |
bogdanm | 0:9b334a45a8ff | 995 | /* Generate Stop */ |
bogdanm | 0:9b334a45a8ff | 996 | hsmbus->Instance->CR2 |= I2C_CR2_STOP; |
bogdanm | 0:9b334a45a8ff | 997 | |
bogdanm | 0:9b334a45a8ff | 998 | /* Wait until STOPF flag is reset */ |
bogdanm | 0:9b334a45a8ff | 999 | if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) |
bogdanm | 0:9b334a45a8ff | 1000 | { |
bogdanm | 0:9b334a45a8ff | 1001 | return HAL_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 1002 | } |
bogdanm | 0:9b334a45a8ff | 1003 | |
bogdanm | 0:9b334a45a8ff | 1004 | /* Clear STOP Flag */ |
bogdanm | 0:9b334a45a8ff | 1005 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); |
bogdanm | 0:9b334a45a8ff | 1006 | } |
bogdanm | 0:9b334a45a8ff | 1007 | }while(SMBUS_Trials < Trials); |
bogdanm | 0:9b334a45a8ff | 1008 | |
bogdanm | 0:9b334a45a8ff | 1009 | hsmbus->State = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1010 | |
bogdanm | 0:9b334a45a8ff | 1011 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1012 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1013 | |
bogdanm | 0:9b334a45a8ff | 1014 | return HAL_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 1015 | } |
bogdanm | 0:9b334a45a8ff | 1016 | else |
bogdanm | 0:9b334a45a8ff | 1017 | { |
bogdanm | 0:9b334a45a8ff | 1018 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 1019 | } |
bogdanm | 0:9b334a45a8ff | 1020 | } |
bogdanm | 0:9b334a45a8ff | 1021 | /** |
bogdanm | 0:9b334a45a8ff | 1022 | * @} |
bogdanm | 0:9b334a45a8ff | 1023 | */ |
bogdanm | 0:9b334a45a8ff | 1024 | |
bogdanm | 0:9b334a45a8ff | 1025 | /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
bogdanm | 0:9b334a45a8ff | 1026 | * @{ |
bogdanm | 0:9b334a45a8ff | 1027 | */ |
bogdanm | 0:9b334a45a8ff | 1028 | |
bogdanm | 0:9b334a45a8ff | 1029 | /** |
bogdanm | 0:9b334a45a8ff | 1030 | * @brief Handle SMBUS event interrupt request. |
bogdanm | 0:9b334a45a8ff | 1031 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1032 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1033 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1034 | */ |
bogdanm | 0:9b334a45a8ff | 1035 | void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 1036 | { |
bogdanm | 0:9b334a45a8ff | 1037 | uint32_t tmpisrvalue = 0; |
bogdanm | 0:9b334a45a8ff | 1038 | |
bogdanm | 0:9b334a45a8ff | 1039 | /* Use a local variable to store the current ISR flags */ |
bogdanm | 0:9b334a45a8ff | 1040 | /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ |
bogdanm | 0:9b334a45a8ff | 1041 | tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1042 | |
bogdanm | 0:9b334a45a8ff | 1043 | /* SMBUS in mode Transmitter ---------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1044 | if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) |
bogdanm | 0:9b334a45a8ff | 1045 | { |
bogdanm | 0:9b334a45a8ff | 1046 | /* Slave mode selected */ |
bogdanm | 0:9b334a45a8ff | 1047 | if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) |
bogdanm | 0:9b334a45a8ff | 1048 | { |
bogdanm | 0:9b334a45a8ff | 1049 | SMBUS_Slave_ISR(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1050 | } |
bogdanm | 0:9b334a45a8ff | 1051 | /* Master mode selected */ |
bogdanm | 0:9b334a45a8ff | 1052 | else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
bogdanm | 0:9b334a45a8ff | 1053 | { |
bogdanm | 0:9b334a45a8ff | 1054 | SMBUS_Master_ISR(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1055 | } |
bogdanm | 0:9b334a45a8ff | 1056 | } |
bogdanm | 0:9b334a45a8ff | 1057 | |
bogdanm | 0:9b334a45a8ff | 1058 | /* SMBUS in mode Receiver ----------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1059 | if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) |
bogdanm | 0:9b334a45a8ff | 1060 | { |
bogdanm | 0:9b334a45a8ff | 1061 | /* Slave mode selected */ |
bogdanm | 0:9b334a45a8ff | 1062 | if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) |
bogdanm | 0:9b334a45a8ff | 1063 | { |
bogdanm | 0:9b334a45a8ff | 1064 | SMBUS_Slave_ISR(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1065 | } |
bogdanm | 0:9b334a45a8ff | 1066 | /* Master mode selected */ |
bogdanm | 0:9b334a45a8ff | 1067 | else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
bogdanm | 0:9b334a45a8ff | 1068 | { |
bogdanm | 0:9b334a45a8ff | 1069 | SMBUS_Master_ISR(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1070 | } |
bogdanm | 0:9b334a45a8ff | 1071 | } |
bogdanm | 0:9b334a45a8ff | 1072 | |
bogdanm | 0:9b334a45a8ff | 1073 | /* SMBUS in mode Listener Only --------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1074 | if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) |
bogdanm | 0:9b334a45a8ff | 1075 | && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) |
bogdanm | 0:9b334a45a8ff | 1076 | { |
bogdanm | 0:9b334a45a8ff | 1077 | if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) |
bogdanm | 0:9b334a45a8ff | 1078 | { |
bogdanm | 0:9b334a45a8ff | 1079 | SMBUS_Slave_ISR(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1080 | } |
bogdanm | 0:9b334a45a8ff | 1081 | } |
bogdanm | 0:9b334a45a8ff | 1082 | } |
bogdanm | 0:9b334a45a8ff | 1083 | |
bogdanm | 0:9b334a45a8ff | 1084 | /** |
bogdanm | 0:9b334a45a8ff | 1085 | * @brief Handle SMBUS error interrupt request. |
bogdanm | 0:9b334a45a8ff | 1086 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1087 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1088 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1089 | */ |
bogdanm | 0:9b334a45a8ff | 1090 | void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 1091 | { |
bogdanm | 0:9b334a45a8ff | 1092 | /* SMBUS Bus error interrupt occurred ------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1093 | if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) |
bogdanm | 0:9b334a45a8ff | 1094 | { |
bogdanm | 0:9b334a45a8ff | 1095 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; |
bogdanm | 0:9b334a45a8ff | 1096 | |
bogdanm | 0:9b334a45a8ff | 1097 | /* Clear BERR flag */ |
bogdanm | 0:9b334a45a8ff | 1098 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); |
bogdanm | 0:9b334a45a8ff | 1099 | } |
bogdanm | 0:9b334a45a8ff | 1100 | |
bogdanm | 0:9b334a45a8ff | 1101 | /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1102 | if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) |
bogdanm | 0:9b334a45a8ff | 1103 | { |
bogdanm | 0:9b334a45a8ff | 1104 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; |
bogdanm | 0:9b334a45a8ff | 1105 | |
bogdanm | 0:9b334a45a8ff | 1106 | /* Clear OVR flag */ |
bogdanm | 0:9b334a45a8ff | 1107 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); |
bogdanm | 0:9b334a45a8ff | 1108 | } |
bogdanm | 0:9b334a45a8ff | 1109 | |
bogdanm | 0:9b334a45a8ff | 1110 | /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1111 | if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) |
bogdanm | 0:9b334a45a8ff | 1112 | { |
bogdanm | 0:9b334a45a8ff | 1113 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; |
bogdanm | 0:9b334a45a8ff | 1114 | |
bogdanm | 0:9b334a45a8ff | 1115 | /* Clear ARLO flag */ |
bogdanm | 0:9b334a45a8ff | 1116 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); |
bogdanm | 0:9b334a45a8ff | 1117 | } |
bogdanm | 0:9b334a45a8ff | 1118 | |
bogdanm | 0:9b334a45a8ff | 1119 | /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1120 | if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) |
bogdanm | 0:9b334a45a8ff | 1121 | { |
bogdanm | 0:9b334a45a8ff | 1122 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; |
bogdanm | 0:9b334a45a8ff | 1123 | |
bogdanm | 0:9b334a45a8ff | 1124 | /* Clear TIMEOUT flag */ |
bogdanm | 0:9b334a45a8ff | 1125 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); |
bogdanm | 0:9b334a45a8ff | 1126 | } |
bogdanm | 0:9b334a45a8ff | 1127 | |
bogdanm | 0:9b334a45a8ff | 1128 | /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1129 | if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) |
bogdanm | 0:9b334a45a8ff | 1130 | { |
bogdanm | 0:9b334a45a8ff | 1131 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; |
bogdanm | 0:9b334a45a8ff | 1132 | |
bogdanm | 0:9b334a45a8ff | 1133 | /* Clear ALERT flag */ |
bogdanm | 0:9b334a45a8ff | 1134 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); |
bogdanm | 0:9b334a45a8ff | 1135 | } |
bogdanm | 0:9b334a45a8ff | 1136 | |
bogdanm | 0:9b334a45a8ff | 1137 | /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1138 | if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) |
bogdanm | 0:9b334a45a8ff | 1139 | { |
bogdanm | 0:9b334a45a8ff | 1140 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; |
bogdanm | 0:9b334a45a8ff | 1141 | |
bogdanm | 0:9b334a45a8ff | 1142 | /* Clear PEC error flag */ |
bogdanm | 0:9b334a45a8ff | 1143 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); |
bogdanm | 0:9b334a45a8ff | 1144 | } |
bogdanm | 0:9b334a45a8ff | 1145 | |
bogdanm | 0:9b334a45a8ff | 1146 | /* Call the Error Callback() in case of Error detected */ |
bogdanm | 0:9b334a45a8ff | 1147 | if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) |
bogdanm | 0:9b334a45a8ff | 1148 | { |
bogdanm | 0:9b334a45a8ff | 1149 | /* Do not Reset the HAL state in case of ALERT error */ |
bogdanm | 0:9b334a45a8ff | 1150 | if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) |
bogdanm | 0:9b334a45a8ff | 1151 | { |
bogdanm | 0:9b334a45a8ff | 1152 | if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) |
bogdanm | 0:9b334a45a8ff | 1153 | || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) |
bogdanm | 0:9b334a45a8ff | 1154 | { |
bogdanm | 0:9b334a45a8ff | 1155 | /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ |
bogdanm | 0:9b334a45a8ff | 1156 | /* keep HAL_SMBUS_STATE_LISTEN if set */ |
bogdanm | 0:9b334a45a8ff | 1157 | hsmbus->PreviousState = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1158 | hsmbus->State = HAL_SMBUS_STATE_LISTEN; |
bogdanm | 0:9b334a45a8ff | 1159 | } |
bogdanm | 0:9b334a45a8ff | 1160 | } |
bogdanm | 0:9b334a45a8ff | 1161 | |
bogdanm | 0:9b334a45a8ff | 1162 | /* Call the Error callback to prevent upper layer */ |
bogdanm | 0:9b334a45a8ff | 1163 | HAL_SMBUS_ErrorCallback(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1164 | } |
bogdanm | 0:9b334a45a8ff | 1165 | } |
bogdanm | 0:9b334a45a8ff | 1166 | |
bogdanm | 0:9b334a45a8ff | 1167 | /** |
bogdanm | 0:9b334a45a8ff | 1168 | * @brief Master Tx Transfer completed callback. |
bogdanm | 0:9b334a45a8ff | 1169 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1170 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1171 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1172 | */ |
bogdanm | 0:9b334a45a8ff | 1173 | __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 1174 | { |
bogdanm | 0:9b334a45a8ff | 1175 | /* NOTE : This function should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 1176 | the HAL_SMBUS_TxCpltCallback() could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 1177 | */ |
bogdanm | 0:9b334a45a8ff | 1178 | } |
bogdanm | 0:9b334a45a8ff | 1179 | |
bogdanm | 0:9b334a45a8ff | 1180 | /** |
bogdanm | 0:9b334a45a8ff | 1181 | * @brief Master Rx Transfer completed callback. |
bogdanm | 0:9b334a45a8ff | 1182 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1183 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1184 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1185 | */ |
bogdanm | 0:9b334a45a8ff | 1186 | __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 1187 | { |
bogdanm | 0:9b334a45a8ff | 1188 | /* NOTE : This function should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 1189 | the HAL_SMBUS_TxCpltCallback() could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 1190 | */ |
bogdanm | 0:9b334a45a8ff | 1191 | } |
bogdanm | 0:9b334a45a8ff | 1192 | |
bogdanm | 0:9b334a45a8ff | 1193 | /** @brief Slave Tx Transfer completed callback. |
bogdanm | 0:9b334a45a8ff | 1194 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1195 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1196 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1197 | */ |
bogdanm | 0:9b334a45a8ff | 1198 | __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 1199 | { |
bogdanm | 0:9b334a45a8ff | 1200 | /* NOTE : This function should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 1201 | the HAL_SMBUS_TxCpltCallback() could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 1202 | */ |
bogdanm | 0:9b334a45a8ff | 1203 | } |
bogdanm | 0:9b334a45a8ff | 1204 | |
bogdanm | 0:9b334a45a8ff | 1205 | /** |
bogdanm | 0:9b334a45a8ff | 1206 | * @brief Slave Rx Transfer completed callback. |
bogdanm | 0:9b334a45a8ff | 1207 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1208 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1209 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1210 | */ |
bogdanm | 0:9b334a45a8ff | 1211 | __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 1212 | { |
bogdanm | 0:9b334a45a8ff | 1213 | /* NOTE : This function should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 1214 | the HAL_SMBUS_TxCpltCallback() could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 1215 | */ |
bogdanm | 0:9b334a45a8ff | 1216 | } |
bogdanm | 0:9b334a45a8ff | 1217 | |
bogdanm | 0:9b334a45a8ff | 1218 | /** |
bogdanm | 0:9b334a45a8ff | 1219 | * @brief Slave Address Match callback. |
bogdanm | 0:9b334a45a8ff | 1220 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1221 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1222 | * @param TransferDirection: Master request Transfer Direction (Write/Read) |
bogdanm | 0:9b334a45a8ff | 1223 | * @param AddrMatchCode: Address Match Code |
bogdanm | 0:9b334a45a8ff | 1224 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1225 | */ |
bogdanm | 0:9b334a45a8ff | 1226 | __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) |
bogdanm | 0:9b334a45a8ff | 1227 | { |
bogdanm | 0:9b334a45a8ff | 1228 | /* NOTE : This function should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 1229 | the HAL_SMBUS_AddrCallback() could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 1230 | */ |
bogdanm | 0:9b334a45a8ff | 1231 | } |
bogdanm | 0:9b334a45a8ff | 1232 | |
bogdanm | 0:9b334a45a8ff | 1233 | /** |
bogdanm | 0:9b334a45a8ff | 1234 | * @brief Listen Complete callback. |
bogdanm | 0:9b334a45a8ff | 1235 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1236 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1237 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1238 | */ |
bogdanm | 0:9b334a45a8ff | 1239 | __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 1240 | { |
bogdanm | 0:9b334a45a8ff | 1241 | /* NOTE : This function should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 1242 | the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 1243 | */ |
bogdanm | 0:9b334a45a8ff | 1244 | } |
bogdanm | 0:9b334a45a8ff | 1245 | |
bogdanm | 0:9b334a45a8ff | 1246 | /** |
bogdanm | 0:9b334a45a8ff | 1247 | * @brief SMBUS error callback. |
bogdanm | 0:9b334a45a8ff | 1248 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1249 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1250 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1251 | */ |
bogdanm | 0:9b334a45a8ff | 1252 | __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 1253 | { |
bogdanm | 0:9b334a45a8ff | 1254 | /* NOTE : This function should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 1255 | the HAL_SMBUS_ErrorCallback() could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 1256 | */ |
bogdanm | 0:9b334a45a8ff | 1257 | } |
bogdanm | 0:9b334a45a8ff | 1258 | |
bogdanm | 0:9b334a45a8ff | 1259 | /** |
bogdanm | 0:9b334a45a8ff | 1260 | * @} |
bogdanm | 0:9b334a45a8ff | 1261 | */ |
bogdanm | 0:9b334a45a8ff | 1262 | |
bogdanm | 0:9b334a45a8ff | 1263 | /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions |
bogdanm | 0:9b334a45a8ff | 1264 | * @brief Peripheral State and Errors functions |
bogdanm | 0:9b334a45a8ff | 1265 | * |
bogdanm | 0:9b334a45a8ff | 1266 | @verbatim |
bogdanm | 0:9b334a45a8ff | 1267 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 1268 | ##### Peripheral State and Errors functions ##### |
bogdanm | 0:9b334a45a8ff | 1269 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 1270 | [..] |
bogdanm | 0:9b334a45a8ff | 1271 | This subsection permits to get in run-time the status of the peripheral |
bogdanm | 0:9b334a45a8ff | 1272 | and the data flow. |
bogdanm | 0:9b334a45a8ff | 1273 | |
bogdanm | 0:9b334a45a8ff | 1274 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 1275 | * @{ |
bogdanm | 0:9b334a45a8ff | 1276 | */ |
bogdanm | 0:9b334a45a8ff | 1277 | |
bogdanm | 0:9b334a45a8ff | 1278 | /** |
bogdanm | 0:9b334a45a8ff | 1279 | * @brief Return the SMBUS handle state. |
bogdanm | 0:9b334a45a8ff | 1280 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1281 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1282 | * @retval HAL state |
bogdanm | 0:9b334a45a8ff | 1283 | */ |
bogdanm | 0:9b334a45a8ff | 1284 | uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 1285 | { |
bogdanm | 0:9b334a45a8ff | 1286 | /* Return SMBUS handle state */ |
bogdanm | 0:9b334a45a8ff | 1287 | return hsmbus->State; |
bogdanm | 0:9b334a45a8ff | 1288 | } |
bogdanm | 0:9b334a45a8ff | 1289 | |
bogdanm | 0:9b334a45a8ff | 1290 | /** |
bogdanm | 0:9b334a45a8ff | 1291 | * @brief Return the SMBUS error code. |
bogdanm | 0:9b334a45a8ff | 1292 | * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1293 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1294 | * @retval SMBUS Error Code |
bogdanm | 0:9b334a45a8ff | 1295 | */ |
bogdanm | 0:9b334a45a8ff | 1296 | uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 1297 | { |
bogdanm | 0:9b334a45a8ff | 1298 | return hsmbus->ErrorCode; |
bogdanm | 0:9b334a45a8ff | 1299 | } |
bogdanm | 0:9b334a45a8ff | 1300 | |
bogdanm | 0:9b334a45a8ff | 1301 | /** |
bogdanm | 0:9b334a45a8ff | 1302 | * @} |
bogdanm | 0:9b334a45a8ff | 1303 | */ |
bogdanm | 0:9b334a45a8ff | 1304 | |
bogdanm | 0:9b334a45a8ff | 1305 | /** |
bogdanm | 0:9b334a45a8ff | 1306 | * @} |
bogdanm | 0:9b334a45a8ff | 1307 | */ |
bogdanm | 0:9b334a45a8ff | 1308 | |
bogdanm | 0:9b334a45a8ff | 1309 | /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions |
bogdanm | 0:9b334a45a8ff | 1310 | * @brief Data transfers Private functions |
bogdanm | 0:9b334a45a8ff | 1311 | * @{ |
bogdanm | 0:9b334a45a8ff | 1312 | */ |
bogdanm | 0:9b334a45a8ff | 1313 | |
bogdanm | 0:9b334a45a8ff | 1314 | /** |
bogdanm | 0:9b334a45a8ff | 1315 | * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode. |
bogdanm | 0:9b334a45a8ff | 1316 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1317 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1318 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1319 | */ |
bogdanm | 0:9b334a45a8ff | 1320 | static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 1321 | { |
bogdanm | 0:9b334a45a8ff | 1322 | uint16_t DevAddress; |
bogdanm | 0:9b334a45a8ff | 1323 | |
bogdanm | 0:9b334a45a8ff | 1324 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 1325 | __HAL_LOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1326 | |
bogdanm | 0:9b334a45a8ff | 1327 | if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) |
bogdanm | 0:9b334a45a8ff | 1328 | { |
bogdanm | 0:9b334a45a8ff | 1329 | /* Clear NACK Flag */ |
bogdanm | 0:9b334a45a8ff | 1330 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); |
bogdanm | 0:9b334a45a8ff | 1331 | |
bogdanm | 0:9b334a45a8ff | 1332 | /* Set corresponding Error Code */ |
bogdanm | 0:9b334a45a8ff | 1333 | /* No need to generate STOP, it is automatically done */ |
bogdanm | 0:9b334a45a8ff | 1334 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; |
bogdanm | 0:9b334a45a8ff | 1335 | |
bogdanm | 0:9b334a45a8ff | 1336 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1337 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1338 | |
bogdanm | 0:9b334a45a8ff | 1339 | /* Call the Error callback to prevent upper layer */ |
bogdanm | 0:9b334a45a8ff | 1340 | HAL_SMBUS_ErrorCallback(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1341 | } |
bogdanm | 0:9b334a45a8ff | 1342 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) |
bogdanm | 0:9b334a45a8ff | 1343 | { |
bogdanm | 0:9b334a45a8ff | 1344 | |
bogdanm | 0:9b334a45a8ff | 1345 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
bogdanm | 0:9b334a45a8ff | 1346 | if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
bogdanm | 0:9b334a45a8ff | 1347 | { |
bogdanm | 0:9b334a45a8ff | 1348 | /* Disable Interrupt */ |
bogdanm | 0:9b334a45a8ff | 1349 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); |
bogdanm | 0:9b334a45a8ff | 1350 | |
bogdanm | 0:9b334a45a8ff | 1351 | /* Clear STOP Flag */ |
bogdanm | 0:9b334a45a8ff | 1352 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); |
bogdanm | 0:9b334a45a8ff | 1353 | |
bogdanm | 0:9b334a45a8ff | 1354 | /* Clear Configuration Register 2 */ |
bogdanm | 0:9b334a45a8ff | 1355 | SMBUS_RESET_CR2(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1356 | |
bogdanm | 0:9b334a45a8ff | 1357 | /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ |
bogdanm | 0:9b334a45a8ff | 1358 | /* Disable the selected SMBUS peripheral */ |
bogdanm | 0:9b334a45a8ff | 1359 | __HAL_SMBUS_DISABLE(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1360 | |
bogdanm | 0:9b334a45a8ff | 1361 | hsmbus->PreviousState = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1362 | hsmbus->State = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1363 | |
bogdanm | 0:9b334a45a8ff | 1364 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1365 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1366 | |
bogdanm | 0:9b334a45a8ff | 1367 | /* REenable the selected SMBUS peripheral */ |
bogdanm | 0:9b334a45a8ff | 1368 | __HAL_SMBUS_ENABLE(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1369 | |
bogdanm | 0:9b334a45a8ff | 1370 | HAL_SMBUS_MasterTxCpltCallback(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1371 | } |
bogdanm | 0:9b334a45a8ff | 1372 | else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
bogdanm | 0:9b334a45a8ff | 1373 | { |
bogdanm | 0:9b334a45a8ff | 1374 | /* Disable Interrupt */ |
bogdanm | 0:9b334a45a8ff | 1375 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); |
bogdanm | 0:9b334a45a8ff | 1376 | |
bogdanm | 0:9b334a45a8ff | 1377 | /* Clear STOP Flag */ |
bogdanm | 0:9b334a45a8ff | 1378 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); |
bogdanm | 0:9b334a45a8ff | 1379 | |
bogdanm | 0:9b334a45a8ff | 1380 | /* Clear Configuration Register 2 */ |
bogdanm | 0:9b334a45a8ff | 1381 | SMBUS_RESET_CR2(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1382 | |
bogdanm | 0:9b334a45a8ff | 1383 | hsmbus->PreviousState = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1384 | hsmbus->State = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1385 | |
bogdanm | 0:9b334a45a8ff | 1386 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1387 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1388 | |
bogdanm | 0:9b334a45a8ff | 1389 | HAL_SMBUS_MasterRxCpltCallback(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1390 | } |
bogdanm | 0:9b334a45a8ff | 1391 | } |
bogdanm | 0:9b334a45a8ff | 1392 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) |
bogdanm | 0:9b334a45a8ff | 1393 | { |
bogdanm | 0:9b334a45a8ff | 1394 | /* Read data from RXDR */ |
bogdanm | 0:9b334a45a8ff | 1395 | (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; |
bogdanm | 0:9b334a45a8ff | 1396 | hsmbus->XferSize--; |
bogdanm | 0:9b334a45a8ff | 1397 | hsmbus->XferCount--; |
bogdanm | 0:9b334a45a8ff | 1398 | } |
bogdanm | 0:9b334a45a8ff | 1399 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) |
bogdanm | 0:9b334a45a8ff | 1400 | { |
bogdanm | 0:9b334a45a8ff | 1401 | /* Write data to TXDR */ |
bogdanm | 0:9b334a45a8ff | 1402 | hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); |
bogdanm | 0:9b334a45a8ff | 1403 | hsmbus->XferSize--; |
bogdanm | 0:9b334a45a8ff | 1404 | hsmbus->XferCount--; |
bogdanm | 0:9b334a45a8ff | 1405 | } |
bogdanm | 0:9b334a45a8ff | 1406 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) |
bogdanm | 0:9b334a45a8ff | 1407 | { |
bogdanm | 0:9b334a45a8ff | 1408 | if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0)) |
bogdanm | 0:9b334a45a8ff | 1409 | { |
bogdanm | 0:9b334a45a8ff | 1410 | DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); |
bogdanm | 0:9b334a45a8ff | 1411 | |
bogdanm | 0:9b334a45a8ff | 1412 | if(hsmbus->XferCount > MAX_NBYTE_SIZE) |
bogdanm | 0:9b334a45a8ff | 1413 | { |
bogdanm | 0:9b334a45a8ff | 1414 | SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 1415 | hsmbus->XferSize = MAX_NBYTE_SIZE; |
bogdanm | 0:9b334a45a8ff | 1416 | } |
bogdanm | 0:9b334a45a8ff | 1417 | else |
bogdanm | 0:9b334a45a8ff | 1418 | { |
bogdanm | 0:9b334a45a8ff | 1419 | hsmbus->XferSize = hsmbus->XferCount; |
bogdanm | 0:9b334a45a8ff | 1420 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 1421 | /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ |
bogdanm | 0:9b334a45a8ff | 1422 | /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ |
bogdanm | 0:9b334a45a8ff | 1423 | if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) |
bogdanm | 0:9b334a45a8ff | 1424 | { |
bogdanm | 0:9b334a45a8ff | 1425 | hsmbus->XferSize--; |
bogdanm | 0:9b334a45a8ff | 1426 | hsmbus->XferCount--; |
bogdanm | 0:9b334a45a8ff | 1427 | } |
bogdanm | 0:9b334a45a8ff | 1428 | } |
bogdanm | 0:9b334a45a8ff | 1429 | } |
bogdanm | 0:9b334a45a8ff | 1430 | else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0)) |
bogdanm | 0:9b334a45a8ff | 1431 | { |
bogdanm | 0:9b334a45a8ff | 1432 | /* Call TxCpltCallback() if no stop mode is set */ |
bogdanm | 0:9b334a45a8ff | 1433 | if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) |
bogdanm | 0:9b334a45a8ff | 1434 | { |
bogdanm | 0:9b334a45a8ff | 1435 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
bogdanm | 0:9b334a45a8ff | 1436 | if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
bogdanm | 0:9b334a45a8ff | 1437 | { |
bogdanm | 0:9b334a45a8ff | 1438 | /* Disable Interrupt */ |
bogdanm | 0:9b334a45a8ff | 1439 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); |
bogdanm | 0:9b334a45a8ff | 1440 | hsmbus->PreviousState = hsmbus->State; |
bogdanm | 0:9b334a45a8ff | 1441 | hsmbus->State = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1442 | |
bogdanm | 0:9b334a45a8ff | 1443 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1444 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1445 | |
bogdanm | 0:9b334a45a8ff | 1446 | HAL_SMBUS_MasterTxCpltCallback(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1447 | } |
bogdanm | 0:9b334a45a8ff | 1448 | else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
bogdanm | 0:9b334a45a8ff | 1449 | { |
bogdanm | 0:9b334a45a8ff | 1450 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); |
bogdanm | 0:9b334a45a8ff | 1451 | hsmbus->PreviousState = hsmbus->State; |
bogdanm | 0:9b334a45a8ff | 1452 | hsmbus->State = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1453 | |
bogdanm | 0:9b334a45a8ff | 1454 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1455 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1456 | |
bogdanm | 0:9b334a45a8ff | 1457 | HAL_SMBUS_MasterRxCpltCallback(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1458 | } |
bogdanm | 0:9b334a45a8ff | 1459 | } |
bogdanm | 0:9b334a45a8ff | 1460 | } |
bogdanm | 0:9b334a45a8ff | 1461 | } |
bogdanm | 0:9b334a45a8ff | 1462 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) |
bogdanm | 0:9b334a45a8ff | 1463 | { |
bogdanm | 0:9b334a45a8ff | 1464 | if(hsmbus->XferCount == 0) |
bogdanm | 0:9b334a45a8ff | 1465 | { |
bogdanm | 0:9b334a45a8ff | 1466 | /* Specific use case for Quick command */ |
bogdanm | 0:9b334a45a8ff | 1467 | if(hsmbus->pBuffPtr == NULL) |
bogdanm | 0:9b334a45a8ff | 1468 | { |
bogdanm | 0:9b334a45a8ff | 1469 | /* Generate a Stop command */ |
bogdanm | 0:9b334a45a8ff | 1470 | hsmbus->Instance->CR2 |= I2C_CR2_STOP; |
bogdanm | 0:9b334a45a8ff | 1471 | } |
bogdanm | 0:9b334a45a8ff | 1472 | /* Call TxCpltCallback() if no stop mode is set */ |
bogdanm | 0:9b334a45a8ff | 1473 | else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) |
bogdanm | 0:9b334a45a8ff | 1474 | { |
bogdanm | 0:9b334a45a8ff | 1475 | /* No Generate Stop, to permit restart mode */ |
bogdanm | 0:9b334a45a8ff | 1476 | /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ |
bogdanm | 0:9b334a45a8ff | 1477 | |
bogdanm | 0:9b334a45a8ff | 1478 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
bogdanm | 0:9b334a45a8ff | 1479 | if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
bogdanm | 0:9b334a45a8ff | 1480 | { |
bogdanm | 0:9b334a45a8ff | 1481 | /* Disable Interrupt */ |
bogdanm | 0:9b334a45a8ff | 1482 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); |
bogdanm | 0:9b334a45a8ff | 1483 | hsmbus->PreviousState = hsmbus->State; |
bogdanm | 0:9b334a45a8ff | 1484 | hsmbus->State = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1485 | |
bogdanm | 0:9b334a45a8ff | 1486 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1487 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1488 | |
bogdanm | 0:9b334a45a8ff | 1489 | HAL_SMBUS_MasterTxCpltCallback(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1490 | } |
bogdanm | 0:9b334a45a8ff | 1491 | else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
bogdanm | 0:9b334a45a8ff | 1492 | { |
bogdanm | 0:9b334a45a8ff | 1493 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); |
bogdanm | 0:9b334a45a8ff | 1494 | hsmbus->PreviousState = hsmbus->State; |
bogdanm | 0:9b334a45a8ff | 1495 | hsmbus->State = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1496 | |
bogdanm | 0:9b334a45a8ff | 1497 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1498 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1499 | |
bogdanm | 0:9b334a45a8ff | 1500 | HAL_SMBUS_MasterRxCpltCallback(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1501 | } |
bogdanm | 0:9b334a45a8ff | 1502 | } |
bogdanm | 0:9b334a45a8ff | 1503 | } |
bogdanm | 0:9b334a45a8ff | 1504 | } |
bogdanm | 0:9b334a45a8ff | 1505 | |
bogdanm | 0:9b334a45a8ff | 1506 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1507 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1508 | |
bogdanm | 0:9b334a45a8ff | 1509 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1510 | } |
bogdanm | 0:9b334a45a8ff | 1511 | /** |
bogdanm | 0:9b334a45a8ff | 1512 | * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. |
bogdanm | 0:9b334a45a8ff | 1513 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1514 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1515 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1516 | */ |
bogdanm | 0:9b334a45a8ff | 1517 | static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) |
bogdanm | 0:9b334a45a8ff | 1518 | { |
bogdanm | 0:9b334a45a8ff | 1519 | uint8_t TransferDirection = 0; |
bogdanm | 0:9b334a45a8ff | 1520 | uint16_t SlaveAddrCode = 0; |
bogdanm | 0:9b334a45a8ff | 1521 | |
bogdanm | 0:9b334a45a8ff | 1522 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 1523 | __HAL_LOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1524 | |
bogdanm | 0:9b334a45a8ff | 1525 | if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) |
bogdanm | 0:9b334a45a8ff | 1526 | { |
bogdanm | 0:9b334a45a8ff | 1527 | /* Check that SMBUS transfer finished */ |
bogdanm | 0:9b334a45a8ff | 1528 | /* if yes, normal use case, a NACK is sent by the HOST when Transfer is finished */ |
bogdanm | 0:9b334a45a8ff | 1529 | /* Mean XferCount == 0*/ |
bogdanm | 0:9b334a45a8ff | 1530 | /* So clear Flag NACKF only */ |
bogdanm | 0:9b334a45a8ff | 1531 | if(hsmbus->XferCount == 0) |
bogdanm | 0:9b334a45a8ff | 1532 | { |
bogdanm | 0:9b334a45a8ff | 1533 | /* Clear NACK Flag */ |
bogdanm | 0:9b334a45a8ff | 1534 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); |
bogdanm | 0:9b334a45a8ff | 1535 | |
bogdanm | 0:9b334a45a8ff | 1536 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1537 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1538 | } |
bogdanm | 0:9b334a45a8ff | 1539 | else |
bogdanm | 0:9b334a45a8ff | 1540 | { |
bogdanm | 0:9b334a45a8ff | 1541 | /* if no, error use case, a Non-Acknowledge of last Data is generated by the HOST*/ |
bogdanm | 0:9b334a45a8ff | 1542 | /* Clear NACK Flag */ |
bogdanm | 0:9b334a45a8ff | 1543 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); |
bogdanm | 0:9b334a45a8ff | 1544 | |
bogdanm | 0:9b334a45a8ff | 1545 | /* Set HAL State to "Idle" State, mean to LISTEN state */ |
bogdanm | 0:9b334a45a8ff | 1546 | /* So reset Slave Busy state */ |
bogdanm | 0:9b334a45a8ff | 1547 | hsmbus->PreviousState = hsmbus->State; |
bogdanm | 0:9b334a45a8ff | 1548 | hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); |
bogdanm | 0:9b334a45a8ff | 1549 | hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); |
bogdanm | 0:9b334a45a8ff | 1550 | |
bogdanm | 0:9b334a45a8ff | 1551 | /* Disable RX/TX Interrupts, keep only ADDR Interrupt */ |
bogdanm | 0:9b334a45a8ff | 1552 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); |
bogdanm | 0:9b334a45a8ff | 1553 | |
bogdanm | 0:9b334a45a8ff | 1554 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
bogdanm | 0:9b334a45a8ff | 1555 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; |
bogdanm | 0:9b334a45a8ff | 1556 | |
bogdanm | 0:9b334a45a8ff | 1557 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1558 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1559 | |
bogdanm | 0:9b334a45a8ff | 1560 | /* Call the Error callback to prevent upper layer */ |
bogdanm | 0:9b334a45a8ff | 1561 | HAL_SMBUS_ErrorCallback(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1562 | } |
bogdanm | 0:9b334a45a8ff | 1563 | } |
bogdanm | 0:9b334a45a8ff | 1564 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) |
bogdanm | 0:9b334a45a8ff | 1565 | { |
bogdanm | 0:9b334a45a8ff | 1566 | TransferDirection = SMBUS_GET_DIR(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1567 | SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1568 | |
bogdanm | 0:9b334a45a8ff | 1569 | /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ |
bogdanm | 0:9b334a45a8ff | 1570 | /* Other ADDRInterrupt will be treat in next Listen use case */ |
bogdanm | 0:9b334a45a8ff | 1571 | __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI); |
bogdanm | 0:9b334a45a8ff | 1572 | |
bogdanm | 0:9b334a45a8ff | 1573 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1574 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1575 | |
bogdanm | 0:9b334a45a8ff | 1576 | /* Call Slave Addr callback */ |
bogdanm | 0:9b334a45a8ff | 1577 | HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); |
bogdanm | 0:9b334a45a8ff | 1578 | } |
bogdanm | 0:9b334a45a8ff | 1579 | else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) |
bogdanm | 0:9b334a45a8ff | 1580 | { |
bogdanm | 0:9b334a45a8ff | 1581 | if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) |
bogdanm | 0:9b334a45a8ff | 1582 | { |
bogdanm | 0:9b334a45a8ff | 1583 | /* Read data from RXDR */ |
bogdanm | 0:9b334a45a8ff | 1584 | (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; |
bogdanm | 0:9b334a45a8ff | 1585 | hsmbus->XferSize--; |
bogdanm | 0:9b334a45a8ff | 1586 | hsmbus->XferCount--; |
bogdanm | 0:9b334a45a8ff | 1587 | |
bogdanm | 0:9b334a45a8ff | 1588 | if(hsmbus->XferCount == 1) |
bogdanm | 0:9b334a45a8ff | 1589 | { |
bogdanm | 0:9b334a45a8ff | 1590 | /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ |
bogdanm | 0:9b334a45a8ff | 1591 | /* or only the last Byte of Transfer */ |
bogdanm | 0:9b334a45a8ff | 1592 | /* So reset the RELOAD bit mode */ |
bogdanm | 0:9b334a45a8ff | 1593 | hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; |
bogdanm | 0:9b334a45a8ff | 1594 | SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 1595 | } |
bogdanm | 0:9b334a45a8ff | 1596 | else if(hsmbus->XferCount == 0) |
bogdanm | 0:9b334a45a8ff | 1597 | { |
bogdanm | 0:9b334a45a8ff | 1598 | /* Last Byte is received, disable Interrupt */ |
bogdanm | 0:9b334a45a8ff | 1599 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); |
bogdanm | 0:9b334a45a8ff | 1600 | |
bogdanm | 0:9b334a45a8ff | 1601 | /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ |
bogdanm | 0:9b334a45a8ff | 1602 | hsmbus->PreviousState = hsmbus->State; |
bogdanm | 0:9b334a45a8ff | 1603 | hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); |
bogdanm | 0:9b334a45a8ff | 1604 | |
bogdanm | 0:9b334a45a8ff | 1605 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1606 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1607 | |
bogdanm | 0:9b334a45a8ff | 1608 | /* Call the Rx complete callback to inform upper layer of the end of receive process */ |
bogdanm | 0:9b334a45a8ff | 1609 | HAL_SMBUS_SlaveRxCpltCallback(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1610 | } |
bogdanm | 0:9b334a45a8ff | 1611 | else |
bogdanm | 0:9b334a45a8ff | 1612 | { |
bogdanm | 0:9b334a45a8ff | 1613 | /* Set Reload for next Bytes */ |
bogdanm | 0:9b334a45a8ff | 1614 | SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 1615 | |
bogdanm | 0:9b334a45a8ff | 1616 | /* Ack last Byte Read */ |
bogdanm | 0:9b334a45a8ff | 1617 | hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; |
bogdanm | 0:9b334a45a8ff | 1618 | } |
bogdanm | 0:9b334a45a8ff | 1619 | } |
bogdanm | 0:9b334a45a8ff | 1620 | else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) |
bogdanm | 0:9b334a45a8ff | 1621 | { |
bogdanm | 0:9b334a45a8ff | 1622 | if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0)) |
bogdanm | 0:9b334a45a8ff | 1623 | { |
bogdanm | 0:9b334a45a8ff | 1624 | if(hsmbus->XferCount > MAX_NBYTE_SIZE) |
bogdanm | 0:9b334a45a8ff | 1625 | { |
bogdanm | 0:9b334a45a8ff | 1626 | SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 1627 | hsmbus->XferSize = MAX_NBYTE_SIZE; |
bogdanm | 0:9b334a45a8ff | 1628 | } |
bogdanm | 0:9b334a45a8ff | 1629 | else |
bogdanm | 0:9b334a45a8ff | 1630 | { |
bogdanm | 0:9b334a45a8ff | 1631 | hsmbus->XferSize = hsmbus->XferCount; |
bogdanm | 0:9b334a45a8ff | 1632 | SMBUS_TransferConfig(hsmbus, 0, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
bogdanm | 0:9b334a45a8ff | 1633 | /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ |
bogdanm | 0:9b334a45a8ff | 1634 | /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ |
bogdanm | 0:9b334a45a8ff | 1635 | if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) |
bogdanm | 0:9b334a45a8ff | 1636 | { |
bogdanm | 0:9b334a45a8ff | 1637 | hsmbus->XferSize--; |
bogdanm | 0:9b334a45a8ff | 1638 | hsmbus->XferCount--; |
bogdanm | 0:9b334a45a8ff | 1639 | } |
bogdanm | 0:9b334a45a8ff | 1640 | } |
bogdanm | 0:9b334a45a8ff | 1641 | } |
bogdanm | 0:9b334a45a8ff | 1642 | } |
bogdanm | 0:9b334a45a8ff | 1643 | } |
bogdanm | 0:9b334a45a8ff | 1644 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) |
bogdanm | 0:9b334a45a8ff | 1645 | { |
bogdanm | 0:9b334a45a8ff | 1646 | /* Write data to TXDR only if XferCount not reach "0" */ |
bogdanm | 0:9b334a45a8ff | 1647 | /* A TXIS flag can be set, during STOP treatment */ |
bogdanm | 0:9b334a45a8ff | 1648 | /* Check if all Data have already been sent */ |
bogdanm | 0:9b334a45a8ff | 1649 | /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ |
bogdanm | 0:9b334a45a8ff | 1650 | if(hsmbus->XferCount > 0) |
bogdanm | 0:9b334a45a8ff | 1651 | { |
bogdanm | 0:9b334a45a8ff | 1652 | /* Write data to TXDR */ |
bogdanm | 0:9b334a45a8ff | 1653 | hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); |
bogdanm | 0:9b334a45a8ff | 1654 | hsmbus->XferCount--; |
bogdanm | 0:9b334a45a8ff | 1655 | hsmbus->XferSize--; |
bogdanm | 0:9b334a45a8ff | 1656 | } |
bogdanm | 0:9b334a45a8ff | 1657 | |
bogdanm | 0:9b334a45a8ff | 1658 | if(hsmbus->XferCount == 0) |
bogdanm | 0:9b334a45a8ff | 1659 | { |
bogdanm | 0:9b334a45a8ff | 1660 | /* Last Byte is Transmitted */ |
bogdanm | 0:9b334a45a8ff | 1661 | /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ |
bogdanm | 0:9b334a45a8ff | 1662 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); |
bogdanm | 0:9b334a45a8ff | 1663 | hsmbus->PreviousState = hsmbus->State; |
bogdanm | 0:9b334a45a8ff | 1664 | hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); |
bogdanm | 0:9b334a45a8ff | 1665 | |
bogdanm | 0:9b334a45a8ff | 1666 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1667 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1668 | |
bogdanm | 0:9b334a45a8ff | 1669 | /* Call the Tx complete callback to inform upper layer of the end of transmit process */ |
bogdanm | 0:9b334a45a8ff | 1670 | HAL_SMBUS_SlaveTxCpltCallback(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1671 | } |
bogdanm | 0:9b334a45a8ff | 1672 | } |
bogdanm | 0:9b334a45a8ff | 1673 | |
bogdanm | 0:9b334a45a8ff | 1674 | /* Check if STOPF is set */ |
bogdanm | 0:9b334a45a8ff | 1675 | if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) |
bogdanm | 0:9b334a45a8ff | 1676 | { |
bogdanm | 0:9b334a45a8ff | 1677 | if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) |
bogdanm | 0:9b334a45a8ff | 1678 | { |
bogdanm | 0:9b334a45a8ff | 1679 | /* Disable RX and TX Interrupts */ |
bogdanm | 0:9b334a45a8ff | 1680 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); |
bogdanm | 0:9b334a45a8ff | 1681 | |
bogdanm | 0:9b334a45a8ff | 1682 | /* Disable ADDR Interrupt */ |
bogdanm | 0:9b334a45a8ff | 1683 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); |
bogdanm | 0:9b334a45a8ff | 1684 | |
bogdanm | 0:9b334a45a8ff | 1685 | /* Disable Address Acknowledge */ |
bogdanm | 0:9b334a45a8ff | 1686 | hsmbus->Instance->CR2 |= I2C_CR2_NACK; |
bogdanm | 0:9b334a45a8ff | 1687 | |
bogdanm | 0:9b334a45a8ff | 1688 | /* Clear Configuration Register 2 */ |
bogdanm | 0:9b334a45a8ff | 1689 | SMBUS_RESET_CR2(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1690 | |
bogdanm | 0:9b334a45a8ff | 1691 | /* Clear STOP Flag */ |
bogdanm | 0:9b334a45a8ff | 1692 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); |
bogdanm | 0:9b334a45a8ff | 1693 | |
bogdanm | 0:9b334a45a8ff | 1694 | /* Clear ADDR flag */ |
bogdanm | 0:9b334a45a8ff | 1695 | __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); |
bogdanm | 0:9b334a45a8ff | 1696 | |
bogdanm | 0:9b334a45a8ff | 1697 | hsmbus->XferOptions = 0; |
bogdanm | 0:9b334a45a8ff | 1698 | hsmbus->PreviousState = hsmbus->State; |
bogdanm | 0:9b334a45a8ff | 1699 | hsmbus->State = HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1700 | |
bogdanm | 0:9b334a45a8ff | 1701 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1702 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1703 | |
bogdanm | 0:9b334a45a8ff | 1704 | /* Call the Listen Complete callback, to prevent upper layer of the end of Listen use case */ |
bogdanm | 0:9b334a45a8ff | 1705 | HAL_SMBUS_ListenCpltCallback(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1706 | } |
bogdanm | 0:9b334a45a8ff | 1707 | } |
bogdanm | 0:9b334a45a8ff | 1708 | |
bogdanm | 0:9b334a45a8ff | 1709 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1710 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1711 | |
bogdanm | 0:9b334a45a8ff | 1712 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1713 | } |
bogdanm | 0:9b334a45a8ff | 1714 | /** |
bogdanm | 0:9b334a45a8ff | 1715 | * @brief Manage the enabling of Interrupts. |
bogdanm | 0:9b334a45a8ff | 1716 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1717 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1718 | * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition. |
bogdanm | 0:9b334a45a8ff | 1719 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1720 | */ |
bogdanm | 0:9b334a45a8ff | 1721 | static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) |
bogdanm | 0:9b334a45a8ff | 1722 | { |
bogdanm | 0:9b334a45a8ff | 1723 | uint32_t tmpisr = 0; |
bogdanm | 0:9b334a45a8ff | 1724 | |
bogdanm | 0:9b334a45a8ff | 1725 | if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) |
bogdanm | 0:9b334a45a8ff | 1726 | { |
bogdanm | 0:9b334a45a8ff | 1727 | /* Enable ERR interrupt */ |
bogdanm | 0:9b334a45a8ff | 1728 | tmpisr |= SMBUS_IT_ERRI; |
bogdanm | 0:9b334a45a8ff | 1729 | } |
bogdanm | 0:9b334a45a8ff | 1730 | |
bogdanm | 0:9b334a45a8ff | 1731 | if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) |
bogdanm | 0:9b334a45a8ff | 1732 | { |
bogdanm | 0:9b334a45a8ff | 1733 | /* Enable ADDR, STOP interrupt */ |
bogdanm | 0:9b334a45a8ff | 1734 | tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI; |
bogdanm | 0:9b334a45a8ff | 1735 | } |
bogdanm | 0:9b334a45a8ff | 1736 | |
bogdanm | 0:9b334a45a8ff | 1737 | if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) |
bogdanm | 0:9b334a45a8ff | 1738 | { |
bogdanm | 0:9b334a45a8ff | 1739 | /* Enable ERR, TC, STOP, NACK, RXI interrupt */ |
bogdanm | 0:9b334a45a8ff | 1740 | tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI; |
bogdanm | 0:9b334a45a8ff | 1741 | } |
bogdanm | 0:9b334a45a8ff | 1742 | |
bogdanm | 0:9b334a45a8ff | 1743 | if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) |
bogdanm | 0:9b334a45a8ff | 1744 | { |
bogdanm | 0:9b334a45a8ff | 1745 | /* Enable ERR, TC, STOP, NACK, TXI interrupt */ |
bogdanm | 0:9b334a45a8ff | 1746 | tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI; |
bogdanm | 0:9b334a45a8ff | 1747 | } |
bogdanm | 0:9b334a45a8ff | 1748 | |
bogdanm | 0:9b334a45a8ff | 1749 | /* Enable interrupts only at the end */ |
bogdanm | 0:9b334a45a8ff | 1750 | /* to avoid the risk of SMBUS interrupt handle execution before */ |
bogdanm | 0:9b334a45a8ff | 1751 | /* all interrupts requested done */ |
bogdanm | 0:9b334a45a8ff | 1752 | __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); |
bogdanm | 0:9b334a45a8ff | 1753 | |
bogdanm | 0:9b334a45a8ff | 1754 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1755 | } |
bogdanm | 0:9b334a45a8ff | 1756 | /** |
bogdanm | 0:9b334a45a8ff | 1757 | * @brief Manage the disabling of Interrupts. |
bogdanm | 0:9b334a45a8ff | 1758 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1759 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1760 | * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition. |
bogdanm | 0:9b334a45a8ff | 1761 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1762 | */ |
bogdanm | 0:9b334a45a8ff | 1763 | static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) |
bogdanm | 0:9b334a45a8ff | 1764 | { |
bogdanm | 0:9b334a45a8ff | 1765 | uint32_t tmpisr = 0; |
bogdanm | 0:9b334a45a8ff | 1766 | |
bogdanm | 0:9b334a45a8ff | 1767 | if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) ) |
bogdanm | 0:9b334a45a8ff | 1768 | { |
bogdanm | 0:9b334a45a8ff | 1769 | /* Disable ERR interrupt */ |
bogdanm | 0:9b334a45a8ff | 1770 | tmpisr |= SMBUS_IT_ERRI; |
bogdanm | 0:9b334a45a8ff | 1771 | } |
bogdanm | 0:9b334a45a8ff | 1772 | |
bogdanm | 0:9b334a45a8ff | 1773 | if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) |
bogdanm | 0:9b334a45a8ff | 1774 | { |
bogdanm | 0:9b334a45a8ff | 1775 | /* Disable TC, STOP, NACK, TXI interrupt */ |
bogdanm | 0:9b334a45a8ff | 1776 | tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; |
bogdanm | 0:9b334a45a8ff | 1777 | |
bogdanm | 0:9b334a45a8ff | 1778 | if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) |
bogdanm | 0:9b334a45a8ff | 1779 | && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) |
bogdanm | 0:9b334a45a8ff | 1780 | { |
bogdanm | 0:9b334a45a8ff | 1781 | /* Disable ERR interrupt */ |
bogdanm | 0:9b334a45a8ff | 1782 | tmpisr |= SMBUS_IT_ERRI; |
bogdanm | 0:9b334a45a8ff | 1783 | } |
bogdanm | 0:9b334a45a8ff | 1784 | |
bogdanm | 0:9b334a45a8ff | 1785 | if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) |
bogdanm | 0:9b334a45a8ff | 1786 | { |
bogdanm | 0:9b334a45a8ff | 1787 | /* Disable STOPI, NACKI */ |
bogdanm | 0:9b334a45a8ff | 1788 | tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; |
bogdanm | 0:9b334a45a8ff | 1789 | } |
bogdanm | 0:9b334a45a8ff | 1790 | } |
bogdanm | 0:9b334a45a8ff | 1791 | |
bogdanm | 0:9b334a45a8ff | 1792 | if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) |
bogdanm | 0:9b334a45a8ff | 1793 | { |
bogdanm | 0:9b334a45a8ff | 1794 | /* Disable TC, STOP, NACK, RXI interrupt */ |
bogdanm | 0:9b334a45a8ff | 1795 | tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; |
bogdanm | 0:9b334a45a8ff | 1796 | |
bogdanm | 0:9b334a45a8ff | 1797 | if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) |
bogdanm | 0:9b334a45a8ff | 1798 | && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) |
bogdanm | 0:9b334a45a8ff | 1799 | { |
bogdanm | 0:9b334a45a8ff | 1800 | /* Disable ERR interrupt */ |
bogdanm | 0:9b334a45a8ff | 1801 | tmpisr |= SMBUS_IT_ERRI; |
bogdanm | 0:9b334a45a8ff | 1802 | } |
bogdanm | 0:9b334a45a8ff | 1803 | |
bogdanm | 0:9b334a45a8ff | 1804 | if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) |
bogdanm | 0:9b334a45a8ff | 1805 | { |
bogdanm | 0:9b334a45a8ff | 1806 | /* Disable STOPI, NACKI */ |
bogdanm | 0:9b334a45a8ff | 1807 | tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; |
bogdanm | 0:9b334a45a8ff | 1808 | } |
bogdanm | 0:9b334a45a8ff | 1809 | } |
bogdanm | 0:9b334a45a8ff | 1810 | |
bogdanm | 0:9b334a45a8ff | 1811 | if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) |
bogdanm | 0:9b334a45a8ff | 1812 | { |
bogdanm | 0:9b334a45a8ff | 1813 | /* Enable ADDR, STOP interrupt */ |
bogdanm | 0:9b334a45a8ff | 1814 | tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; |
bogdanm | 0:9b334a45a8ff | 1815 | |
bogdanm | 0:9b334a45a8ff | 1816 | if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) |
bogdanm | 0:9b334a45a8ff | 1817 | { |
bogdanm | 0:9b334a45a8ff | 1818 | /* Disable ERR interrupt */ |
bogdanm | 0:9b334a45a8ff | 1819 | tmpisr |= SMBUS_IT_ERRI; |
bogdanm | 0:9b334a45a8ff | 1820 | } |
bogdanm | 0:9b334a45a8ff | 1821 | } |
bogdanm | 0:9b334a45a8ff | 1822 | |
bogdanm | 0:9b334a45a8ff | 1823 | /* Disable interrupts only at the end */ |
bogdanm | 0:9b334a45a8ff | 1824 | /* to avoid a breaking situation like at "t" time */ |
bogdanm | 0:9b334a45a8ff | 1825 | /* all disable interrupts request are not done */ |
bogdanm | 0:9b334a45a8ff | 1826 | __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); |
bogdanm | 0:9b334a45a8ff | 1827 | |
bogdanm | 0:9b334a45a8ff | 1828 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1829 | } |
bogdanm | 0:9b334a45a8ff | 1830 | /** |
bogdanm | 0:9b334a45a8ff | 1831 | * @brief Handle SMBUS Communication Timeout. |
bogdanm | 0:9b334a45a8ff | 1832 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1833 | * the configuration information for the specified SMBUS. |
bogdanm | 0:9b334a45a8ff | 1834 | * @param Flag: specifies the SMBUS flag to check. |
bogdanm | 0:9b334a45a8ff | 1835 | * @param Status: The new Flag status (SET or RESET). |
bogdanm | 0:9b334a45a8ff | 1836 | * @param Timeout: Timeout duration |
bogdanm | 0:9b334a45a8ff | 1837 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1838 | */ |
bogdanm | 0:9b334a45a8ff | 1839 | static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) |
bogdanm | 0:9b334a45a8ff | 1840 | { |
bogdanm | 0:9b334a45a8ff | 1841 | uint32_t tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 1842 | |
bogdanm | 0:9b334a45a8ff | 1843 | /* Wait until flag is set */ |
bogdanm | 0:9b334a45a8ff | 1844 | if(Status == RESET) |
bogdanm | 0:9b334a45a8ff | 1845 | { |
bogdanm | 0:9b334a45a8ff | 1846 | while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) |
bogdanm | 0:9b334a45a8ff | 1847 | { |
bogdanm | 0:9b334a45a8ff | 1848 | /* Check for the Timeout */ |
bogdanm | 0:9b334a45a8ff | 1849 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 1850 | { |
bogdanm | 0:9b334a45a8ff | 1851 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 1852 | { |
bogdanm | 0:9b334a45a8ff | 1853 | hsmbus->PreviousState = hsmbus->State; |
bogdanm | 0:9b334a45a8ff | 1854 | hsmbus->State= HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1855 | |
bogdanm | 0:9b334a45a8ff | 1856 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1857 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1858 | |
bogdanm | 0:9b334a45a8ff | 1859 | return HAL_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 1860 | } |
bogdanm | 0:9b334a45a8ff | 1861 | } |
bogdanm | 0:9b334a45a8ff | 1862 | } |
bogdanm | 0:9b334a45a8ff | 1863 | } |
bogdanm | 0:9b334a45a8ff | 1864 | else |
bogdanm | 0:9b334a45a8ff | 1865 | { |
bogdanm | 0:9b334a45a8ff | 1866 | while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) |
bogdanm | 0:9b334a45a8ff | 1867 | { |
bogdanm | 0:9b334a45a8ff | 1868 | /* Check for the Timeout */ |
bogdanm | 0:9b334a45a8ff | 1869 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 1870 | { |
bogdanm | 0:9b334a45a8ff | 1871 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 1872 | { |
bogdanm | 0:9b334a45a8ff | 1873 | hsmbus->PreviousState = hsmbus->State; |
bogdanm | 0:9b334a45a8ff | 1874 | hsmbus->State= HAL_SMBUS_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1875 | |
bogdanm | 0:9b334a45a8ff | 1876 | /* Process Unlocked */ |
bogdanm | 0:9b334a45a8ff | 1877 | __HAL_UNLOCK(hsmbus); |
bogdanm | 0:9b334a45a8ff | 1878 | |
bogdanm | 0:9b334a45a8ff | 1879 | return HAL_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 1880 | } |
bogdanm | 0:9b334a45a8ff | 1881 | } |
bogdanm | 0:9b334a45a8ff | 1882 | } |
bogdanm | 0:9b334a45a8ff | 1883 | } |
bogdanm | 0:9b334a45a8ff | 1884 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1885 | } |
bogdanm | 0:9b334a45a8ff | 1886 | |
bogdanm | 0:9b334a45a8ff | 1887 | /** |
bogdanm | 0:9b334a45a8ff | 1888 | * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). |
bogdanm | 0:9b334a45a8ff | 1889 | * @param hsmbus: SMBUS handle. |
bogdanm | 0:9b334a45a8ff | 1890 | * @param DevAddress: specifies the slave address to be programmed. |
bogdanm | 0:9b334a45a8ff | 1891 | * @param Size: specifies the number of bytes to be programmed. |
bogdanm | 0:9b334a45a8ff | 1892 | * This parameter must be a value between 0 and 255. |
bogdanm | 0:9b334a45a8ff | 1893 | * @param Mode: new state of the SMBUS START condition generation. |
bogdanm | 0:9b334a45a8ff | 1894 | * This parameter can be one or a combination of the following values: |
bogdanm | 0:9b334a45a8ff | 1895 | * @arg SMBUS_NO_MODE: No specific mode enabled. |
bogdanm | 0:9b334a45a8ff | 1896 | * @arg SMBUS_RELOAD_MODE: Enable Reload mode. |
bogdanm | 0:9b334a45a8ff | 1897 | * @arg SMBUS_AUTOEND_MODE: Enable Automatic end mode. |
bogdanm | 0:9b334a45a8ff | 1898 | * @arg SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode. |
bogdanm | 0:9b334a45a8ff | 1899 | * @param Request: new state of the SMBUS START condition generation. |
bogdanm | 0:9b334a45a8ff | 1900 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1901 | * @arg SMBUS_NO_STARTSTOP: Don't Generate stop and start condition. |
bogdanm | 0:9b334a45a8ff | 1902 | * @arg SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0). |
bogdanm | 0:9b334a45a8ff | 1903 | * @arg SMBUS_GENERATE_START_READ: Generate Restart for read request. |
bogdanm | 0:9b334a45a8ff | 1904 | * @arg SMBUS_GENERATE_START_WRITE: Generate Restart for write request. |
bogdanm | 0:9b334a45a8ff | 1905 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1906 | */ |
bogdanm | 0:9b334a45a8ff | 1907 | static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) |
bogdanm | 0:9b334a45a8ff | 1908 | { |
bogdanm | 0:9b334a45a8ff | 1909 | uint32_t tmpreg = 0; |
bogdanm | 0:9b334a45a8ff | 1910 | |
bogdanm | 0:9b334a45a8ff | 1911 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1912 | assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); |
bogdanm | 0:9b334a45a8ff | 1913 | assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); |
bogdanm | 0:9b334a45a8ff | 1914 | assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); |
bogdanm | 0:9b334a45a8ff | 1915 | |
bogdanm | 0:9b334a45a8ff | 1916 | /* Get the CR2 register value */ |
bogdanm | 0:9b334a45a8ff | 1917 | tmpreg = hsmbus->Instance->CR2; |
bogdanm | 0:9b334a45a8ff | 1918 | |
bogdanm | 0:9b334a45a8ff | 1919 | /* clear tmpreg specific bits */ |
bogdanm | 0:9b334a45a8ff | 1920 | tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)); |
bogdanm | 0:9b334a45a8ff | 1921 | |
bogdanm | 0:9b334a45a8ff | 1922 | /* update tmpreg */ |
bogdanm | 0:9b334a45a8ff | 1923 | tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ |
bogdanm | 0:9b334a45a8ff | 1924 | (uint32_t)Mode | (uint32_t)Request); |
bogdanm | 0:9b334a45a8ff | 1925 | |
bogdanm | 0:9b334a45a8ff | 1926 | /* update CR2 register */ |
bogdanm | 0:9b334a45a8ff | 1927 | hsmbus->Instance->CR2 = tmpreg; |
bogdanm | 0:9b334a45a8ff | 1928 | } |
bogdanm | 0:9b334a45a8ff | 1929 | /** |
bogdanm | 0:9b334a45a8ff | 1930 | * @} |
bogdanm | 0:9b334a45a8ff | 1931 | */ |
bogdanm | 0:9b334a45a8ff | 1932 | |
bogdanm | 0:9b334a45a8ff | 1933 | #endif /* HAL_SMBUS_MODULE_ENABLED */ |
bogdanm | 0:9b334a45a8ff | 1934 | /** |
bogdanm | 0:9b334a45a8ff | 1935 | * @} |
bogdanm | 0:9b334a45a8ff | 1936 | */ |
bogdanm | 0:9b334a45a8ff | 1937 | |
bogdanm | 0:9b334a45a8ff | 1938 | /** |
bogdanm | 0:9b334a45a8ff | 1939 | * @} |
bogdanm | 0:9b334a45a8ff | 1940 | */ |
bogdanm | 0:9b334a45a8ff | 1941 | |
bogdanm | 0:9b334a45a8ff | 1942 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |