fix LPC812 PWM
Fork of mbed-dev by
targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc_ex.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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bogdanm | 0:9b334a45a8ff | 1 | /** |
bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 3 | * @file stm32l4xx_hal_rcc_ex.h |
bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
bogdanm | 0:9b334a45a8ff | 5 | * @version V1.0.0 |
bogdanm | 0:9b334a45a8ff | 6 | * @date 26-June-2015 |
bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file of RCC HAL Extended module. |
bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 9 | * @attention |
bogdanm | 0:9b334a45a8ff | 10 | * |
bogdanm | 0:9b334a45a8ff | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
bogdanm | 0:9b334a45a8ff | 12 | * |
bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
bogdanm | 0:9b334a45a8ff | 23 | * |
bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 0:9b334a45a8ff | 34 | * |
bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 36 | */ |
bogdanm | 0:9b334a45a8ff | 37 | |
bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32L4xx_HAL_RCC_EX_H |
bogdanm | 0:9b334a45a8ff | 40 | #define __STM32L4xx_HAL_RCC_EX_H |
bogdanm | 0:9b334a45a8ff | 41 | |
bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
bogdanm | 0:9b334a45a8ff | 44 | #endif |
bogdanm | 0:9b334a45a8ff | 45 | |
bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 47 | #include "stm32l4xx_hal_def.h" |
bogdanm | 0:9b334a45a8ff | 48 | |
bogdanm | 0:9b334a45a8ff | 49 | /** @addtogroup STM32L4xx_HAL_Driver |
bogdanm | 0:9b334a45a8ff | 50 | * @{ |
bogdanm | 0:9b334a45a8ff | 51 | */ |
bogdanm | 0:9b334a45a8ff | 52 | |
bogdanm | 0:9b334a45a8ff | 53 | /** @addtogroup RCCEx |
bogdanm | 0:9b334a45a8ff | 54 | * @{ |
bogdanm | 0:9b334a45a8ff | 55 | */ |
bogdanm | 0:9b334a45a8ff | 56 | |
bogdanm | 0:9b334a45a8ff | 57 | /* Exported types ------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 58 | |
bogdanm | 0:9b334a45a8ff | 59 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
bogdanm | 0:9b334a45a8ff | 60 | * @{ |
bogdanm | 0:9b334a45a8ff | 61 | */ |
bogdanm | 0:9b334a45a8ff | 62 | |
bogdanm | 0:9b334a45a8ff | 63 | /** |
bogdanm | 0:9b334a45a8ff | 64 | * @brief PLLSAI1 Clock structure definition |
bogdanm | 0:9b334a45a8ff | 65 | */ |
bogdanm | 0:9b334a45a8ff | 66 | typedef struct |
bogdanm | 0:9b334a45a8ff | 67 | { |
bogdanm | 0:9b334a45a8ff | 68 | |
bogdanm | 0:9b334a45a8ff | 69 | uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. |
bogdanm | 0:9b334a45a8ff | 70 | This parameter must be a number between 8 and 86. */ |
bogdanm | 0:9b334a45a8ff | 71 | |
bogdanm | 0:9b334a45a8ff | 72 | uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock. |
bogdanm | 0:9b334a45a8ff | 73 | This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ |
bogdanm | 0:9b334a45a8ff | 74 | |
bogdanm | 0:9b334a45a8ff | 75 | uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. |
bogdanm | 0:9b334a45a8ff | 76 | This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ |
bogdanm | 0:9b334a45a8ff | 77 | |
bogdanm | 0:9b334a45a8ff | 78 | uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock. |
bogdanm | 0:9b334a45a8ff | 79 | This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ |
bogdanm | 0:9b334a45a8ff | 80 | |
bogdanm | 0:9b334a45a8ff | 81 | uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. |
bogdanm | 0:9b334a45a8ff | 82 | This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ |
bogdanm | 0:9b334a45a8ff | 83 | }RCC_PLLSAI1InitTypeDef; |
bogdanm | 0:9b334a45a8ff | 84 | |
bogdanm | 0:9b334a45a8ff | 85 | /** |
bogdanm | 0:9b334a45a8ff | 86 | * @brief PLLSAI2 Clock structure definition |
bogdanm | 0:9b334a45a8ff | 87 | */ |
bogdanm | 0:9b334a45a8ff | 88 | typedef struct |
bogdanm | 0:9b334a45a8ff | 89 | { |
bogdanm | 0:9b334a45a8ff | 90 | |
bogdanm | 0:9b334a45a8ff | 91 | uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. |
bogdanm | 0:9b334a45a8ff | 92 | This parameter must be a number between 8 and 86. */ |
bogdanm | 0:9b334a45a8ff | 93 | |
bogdanm | 0:9b334a45a8ff | 94 | uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. |
bogdanm | 0:9b334a45a8ff | 95 | This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ |
bogdanm | 0:9b334a45a8ff | 96 | |
bogdanm | 0:9b334a45a8ff | 97 | uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock. |
bogdanm | 0:9b334a45a8ff | 98 | This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ |
bogdanm | 0:9b334a45a8ff | 99 | |
bogdanm | 0:9b334a45a8ff | 100 | uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled. |
bogdanm | 0:9b334a45a8ff | 101 | This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */ |
bogdanm | 0:9b334a45a8ff | 102 | }RCC_PLLSAI2InitTypeDef; |
bogdanm | 0:9b334a45a8ff | 103 | |
bogdanm | 0:9b334a45a8ff | 104 | /** |
bogdanm | 0:9b334a45a8ff | 105 | * @brief RCC extended clocks structure definition |
bogdanm | 0:9b334a45a8ff | 106 | */ |
bogdanm | 0:9b334a45a8ff | 107 | typedef struct |
bogdanm | 0:9b334a45a8ff | 108 | { |
bogdanm | 0:9b334a45a8ff | 109 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
bogdanm | 0:9b334a45a8ff | 110 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
bogdanm | 0:9b334a45a8ff | 111 | |
bogdanm | 0:9b334a45a8ff | 112 | RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. |
bogdanm | 0:9b334a45a8ff | 113 | This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ |
bogdanm | 0:9b334a45a8ff | 114 | |
bogdanm | 0:9b334a45a8ff | 115 | RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. |
bogdanm | 0:9b334a45a8ff | 116 | This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */ |
bogdanm | 0:9b334a45a8ff | 117 | |
bogdanm | 0:9b334a45a8ff | 118 | uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. |
bogdanm | 0:9b334a45a8ff | 119 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 120 | |
bogdanm | 0:9b334a45a8ff | 121 | uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. |
bogdanm | 0:9b334a45a8ff | 122 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 123 | |
bogdanm | 0:9b334a45a8ff | 124 | uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. |
bogdanm | 0:9b334a45a8ff | 125 | This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 126 | |
bogdanm | 0:9b334a45a8ff | 127 | uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. |
bogdanm | 0:9b334a45a8ff | 128 | This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 129 | |
bogdanm | 0:9b334a45a8ff | 130 | uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. |
bogdanm | 0:9b334a45a8ff | 131 | This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 132 | |
bogdanm | 0:9b334a45a8ff | 133 | uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. |
bogdanm | 0:9b334a45a8ff | 134 | This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 135 | |
bogdanm | 0:9b334a45a8ff | 136 | uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. |
bogdanm | 0:9b334a45a8ff | 137 | This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 138 | |
bogdanm | 0:9b334a45a8ff | 139 | uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. |
bogdanm | 0:9b334a45a8ff | 140 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 141 | |
bogdanm | 0:9b334a45a8ff | 142 | uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. |
bogdanm | 0:9b334a45a8ff | 143 | This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 144 | |
bogdanm | 0:9b334a45a8ff | 145 | uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. |
bogdanm | 0:9b334a45a8ff | 146 | This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 147 | |
bogdanm | 0:9b334a45a8ff | 148 | uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. |
bogdanm | 0:9b334a45a8ff | 149 | This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 150 | |
bogdanm | 0:9b334a45a8ff | 151 | uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. |
bogdanm | 0:9b334a45a8ff | 152 | This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 153 | |
bogdanm | 0:9b334a45a8ff | 154 | uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. |
bogdanm | 0:9b334a45a8ff | 155 | This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 156 | |
bogdanm | 0:9b334a45a8ff | 157 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 158 | |
bogdanm | 0:9b334a45a8ff | 159 | uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG). |
bogdanm | 0:9b334a45a8ff | 160 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 161 | |
bogdanm | 0:9b334a45a8ff | 162 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 163 | |
bogdanm | 0:9b334a45a8ff | 164 | uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG). |
bogdanm | 0:9b334a45a8ff | 165 | This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 166 | |
bogdanm | 0:9b334a45a8ff | 167 | uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). |
bogdanm | 0:9b334a45a8ff | 168 | This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 169 | |
bogdanm | 0:9b334a45a8ff | 170 | uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. |
bogdanm | 0:9b334a45a8ff | 171 | This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 172 | |
bogdanm | 0:9b334a45a8ff | 173 | uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source. |
bogdanm | 0:9b334a45a8ff | 174 | This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 175 | |
bogdanm | 0:9b334a45a8ff | 176 | uint32_t DfsdmClockSelection; /*!< Specifies DFSDM clock source. |
bogdanm | 0:9b334a45a8ff | 177 | This parameter can be a value of @ref RCCEx_DFSDM_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 178 | |
bogdanm | 0:9b334a45a8ff | 179 | uint32_t RTCClockSelection; /*!< Specifies RTC clock source. |
bogdanm | 0:9b334a45a8ff | 180 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
bogdanm | 0:9b334a45a8ff | 181 | }RCC_PeriphCLKInitTypeDef; |
bogdanm | 0:9b334a45a8ff | 182 | |
bogdanm | 0:9b334a45a8ff | 183 | /** |
bogdanm | 0:9b334a45a8ff | 184 | * @} |
bogdanm | 0:9b334a45a8ff | 185 | */ |
bogdanm | 0:9b334a45a8ff | 186 | |
bogdanm | 0:9b334a45a8ff | 187 | /* Exported constants --------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 188 | /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
bogdanm | 0:9b334a45a8ff | 189 | * @{ |
bogdanm | 0:9b334a45a8ff | 190 | */ |
bogdanm | 0:9b334a45a8ff | 191 | |
bogdanm | 0:9b334a45a8ff | 192 | /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source |
bogdanm | 0:9b334a45a8ff | 193 | * @{ |
bogdanm | 0:9b334a45a8ff | 194 | */ |
bogdanm | 0:9b334a45a8ff | 195 | #define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000 /*!< LSI selection for low speed clock output */ |
bogdanm | 0:9b334a45a8ff | 196 | #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ |
bogdanm | 0:9b334a45a8ff | 197 | /** |
bogdanm | 0:9b334a45a8ff | 198 | * @} |
bogdanm | 0:9b334a45a8ff | 199 | */ |
bogdanm | 0:9b334a45a8ff | 200 | |
bogdanm | 0:9b334a45a8ff | 201 | /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection |
bogdanm | 0:9b334a45a8ff | 202 | * @{ |
bogdanm | 0:9b334a45a8ff | 203 | */ |
bogdanm | 0:9b334a45a8ff | 204 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
bogdanm | 0:9b334a45a8ff | 205 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
bogdanm | 0:9b334a45a8ff | 206 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
bogdanm | 0:9b334a45a8ff | 207 | #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) |
bogdanm | 0:9b334a45a8ff | 208 | #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) |
bogdanm | 0:9b334a45a8ff | 209 | #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020) |
bogdanm | 0:9b334a45a8ff | 210 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040) |
bogdanm | 0:9b334a45a8ff | 211 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080) |
bogdanm | 0:9b334a45a8ff | 212 | #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100) |
bogdanm | 0:9b334a45a8ff | 213 | #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200) |
bogdanm | 0:9b334a45a8ff | 214 | #define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400) |
bogdanm | 0:9b334a45a8ff | 215 | #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800) |
bogdanm | 0:9b334a45a8ff | 216 | #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000) |
bogdanm | 0:9b334a45a8ff | 217 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 218 | #define RCC_PERIPHCLK_USB ((uint32_t)0x00002000) |
bogdanm | 0:9b334a45a8ff | 219 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 220 | #define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000) |
bogdanm | 0:9b334a45a8ff | 221 | #define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000) |
bogdanm | 0:9b334a45a8ff | 222 | #define RCC_PERIPHCLK_DFSDM ((uint32_t)0x00010000) |
bogdanm | 0:9b334a45a8ff | 223 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000) |
bogdanm | 0:9b334a45a8ff | 224 | #define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000) |
bogdanm | 0:9b334a45a8ff | 225 | #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000) |
bogdanm | 0:9b334a45a8ff | 226 | /** |
bogdanm | 0:9b334a45a8ff | 227 | * @} |
bogdanm | 0:9b334a45a8ff | 228 | */ |
bogdanm | 0:9b334a45a8ff | 229 | |
bogdanm | 0:9b334a45a8ff | 230 | |
bogdanm | 0:9b334a45a8ff | 231 | /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source |
bogdanm | 0:9b334a45a8ff | 232 | * @{ |
bogdanm | 0:9b334a45a8ff | 233 | */ |
bogdanm | 0:9b334a45a8ff | 234 | #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 235 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 |
bogdanm | 0:9b334a45a8ff | 236 | #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 |
bogdanm | 0:9b334a45a8ff | 237 | #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) |
bogdanm | 0:9b334a45a8ff | 238 | /** |
bogdanm | 0:9b334a45a8ff | 239 | * @} |
bogdanm | 0:9b334a45a8ff | 240 | */ |
bogdanm | 0:9b334a45a8ff | 241 | |
bogdanm | 0:9b334a45a8ff | 242 | /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source |
bogdanm | 0:9b334a45a8ff | 243 | * @{ |
bogdanm | 0:9b334a45a8ff | 244 | */ |
bogdanm | 0:9b334a45a8ff | 245 | #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 246 | #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 |
bogdanm | 0:9b334a45a8ff | 247 | #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 |
bogdanm | 0:9b334a45a8ff | 248 | #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) |
bogdanm | 0:9b334a45a8ff | 249 | /** |
bogdanm | 0:9b334a45a8ff | 250 | * @} |
bogdanm | 0:9b334a45a8ff | 251 | */ |
bogdanm | 0:9b334a45a8ff | 252 | |
bogdanm | 0:9b334a45a8ff | 253 | /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source |
bogdanm | 0:9b334a45a8ff | 254 | * @{ |
bogdanm | 0:9b334a45a8ff | 255 | */ |
bogdanm | 0:9b334a45a8ff | 256 | #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 257 | #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 |
bogdanm | 0:9b334a45a8ff | 258 | #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 |
bogdanm | 0:9b334a45a8ff | 259 | #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) |
bogdanm | 0:9b334a45a8ff | 260 | /** |
bogdanm | 0:9b334a45a8ff | 261 | * @} |
bogdanm | 0:9b334a45a8ff | 262 | */ |
bogdanm | 0:9b334a45a8ff | 263 | |
bogdanm | 0:9b334a45a8ff | 264 | /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source |
bogdanm | 0:9b334a45a8ff | 265 | * @{ |
bogdanm | 0:9b334a45a8ff | 266 | */ |
bogdanm | 0:9b334a45a8ff | 267 | #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 268 | #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 |
bogdanm | 0:9b334a45a8ff | 269 | #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 |
bogdanm | 0:9b334a45a8ff | 270 | #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) |
bogdanm | 0:9b334a45a8ff | 271 | /** |
bogdanm | 0:9b334a45a8ff | 272 | * @} |
bogdanm | 0:9b334a45a8ff | 273 | */ |
bogdanm | 0:9b334a45a8ff | 274 | |
bogdanm | 0:9b334a45a8ff | 275 | /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source |
bogdanm | 0:9b334a45a8ff | 276 | * @{ |
bogdanm | 0:9b334a45a8ff | 277 | */ |
bogdanm | 0:9b334a45a8ff | 278 | #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 279 | #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 |
bogdanm | 0:9b334a45a8ff | 280 | #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 |
bogdanm | 0:9b334a45a8ff | 281 | #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) |
bogdanm | 0:9b334a45a8ff | 282 | /** |
bogdanm | 0:9b334a45a8ff | 283 | * @} |
bogdanm | 0:9b334a45a8ff | 284 | */ |
bogdanm | 0:9b334a45a8ff | 285 | |
bogdanm | 0:9b334a45a8ff | 286 | /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source |
bogdanm | 0:9b334a45a8ff | 287 | * @{ |
bogdanm | 0:9b334a45a8ff | 288 | */ |
bogdanm | 0:9b334a45a8ff | 289 | #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 290 | #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 |
bogdanm | 0:9b334a45a8ff | 291 | #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 |
bogdanm | 0:9b334a45a8ff | 292 | #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) |
bogdanm | 0:9b334a45a8ff | 293 | /** |
bogdanm | 0:9b334a45a8ff | 294 | * @} |
bogdanm | 0:9b334a45a8ff | 295 | */ |
bogdanm | 0:9b334a45a8ff | 296 | |
bogdanm | 0:9b334a45a8ff | 297 | /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source |
bogdanm | 0:9b334a45a8ff | 298 | * @{ |
bogdanm | 0:9b334a45a8ff | 299 | */ |
bogdanm | 0:9b334a45a8ff | 300 | #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 301 | #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 |
bogdanm | 0:9b334a45a8ff | 302 | #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 |
bogdanm | 0:9b334a45a8ff | 303 | /** |
bogdanm | 0:9b334a45a8ff | 304 | * @} |
bogdanm | 0:9b334a45a8ff | 305 | */ |
bogdanm | 0:9b334a45a8ff | 306 | |
bogdanm | 0:9b334a45a8ff | 307 | /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source |
bogdanm | 0:9b334a45a8ff | 308 | * @{ |
bogdanm | 0:9b334a45a8ff | 309 | */ |
bogdanm | 0:9b334a45a8ff | 310 | #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 311 | #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 |
bogdanm | 0:9b334a45a8ff | 312 | #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 |
bogdanm | 0:9b334a45a8ff | 313 | /** |
bogdanm | 0:9b334a45a8ff | 314 | * @} |
bogdanm | 0:9b334a45a8ff | 315 | */ |
bogdanm | 0:9b334a45a8ff | 316 | |
bogdanm | 0:9b334a45a8ff | 317 | /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source |
bogdanm | 0:9b334a45a8ff | 318 | * @{ |
bogdanm | 0:9b334a45a8ff | 319 | */ |
bogdanm | 0:9b334a45a8ff | 320 | #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 321 | #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 |
bogdanm | 0:9b334a45a8ff | 322 | #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 |
bogdanm | 0:9b334a45a8ff | 323 | /** |
bogdanm | 0:9b334a45a8ff | 324 | * @} |
bogdanm | 0:9b334a45a8ff | 325 | */ |
bogdanm | 0:9b334a45a8ff | 326 | |
bogdanm | 0:9b334a45a8ff | 327 | /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source |
bogdanm | 0:9b334a45a8ff | 328 | * @{ |
bogdanm | 0:9b334a45a8ff | 329 | */ |
bogdanm | 0:9b334a45a8ff | 330 | #define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 331 | #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0 |
bogdanm | 0:9b334a45a8ff | 332 | #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1 |
bogdanm | 0:9b334a45a8ff | 333 | #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL |
bogdanm | 0:9b334a45a8ff | 334 | /** |
bogdanm | 0:9b334a45a8ff | 335 | * @} |
bogdanm | 0:9b334a45a8ff | 336 | */ |
bogdanm | 0:9b334a45a8ff | 337 | |
bogdanm | 0:9b334a45a8ff | 338 | /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source |
bogdanm | 0:9b334a45a8ff | 339 | * @{ |
bogdanm | 0:9b334a45a8ff | 340 | */ |
bogdanm | 0:9b334a45a8ff | 341 | #define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 342 | #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0 |
bogdanm | 0:9b334a45a8ff | 343 | #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1 |
bogdanm | 0:9b334a45a8ff | 344 | #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL |
bogdanm | 0:9b334a45a8ff | 345 | /** |
bogdanm | 0:9b334a45a8ff | 346 | * @} |
bogdanm | 0:9b334a45a8ff | 347 | */ |
bogdanm | 0:9b334a45a8ff | 348 | |
bogdanm | 0:9b334a45a8ff | 349 | /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source |
bogdanm | 0:9b334a45a8ff | 350 | * @{ |
bogdanm | 0:9b334a45a8ff | 351 | */ |
bogdanm | 0:9b334a45a8ff | 352 | #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 353 | #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 |
bogdanm | 0:9b334a45a8ff | 354 | #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 |
bogdanm | 0:9b334a45a8ff | 355 | #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL |
bogdanm | 0:9b334a45a8ff | 356 | /** |
bogdanm | 0:9b334a45a8ff | 357 | * @} |
bogdanm | 0:9b334a45a8ff | 358 | */ |
bogdanm | 0:9b334a45a8ff | 359 | |
bogdanm | 0:9b334a45a8ff | 360 | /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source |
bogdanm | 0:9b334a45a8ff | 361 | * @{ |
bogdanm | 0:9b334a45a8ff | 362 | */ |
bogdanm | 0:9b334a45a8ff | 363 | #define RCC_LPTIM2CLKSOURCE_PCLK ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 364 | #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 |
bogdanm | 0:9b334a45a8ff | 365 | #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 |
bogdanm | 0:9b334a45a8ff | 366 | #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL |
bogdanm | 0:9b334a45a8ff | 367 | /** |
bogdanm | 0:9b334a45a8ff | 368 | * @} |
bogdanm | 0:9b334a45a8ff | 369 | */ |
bogdanm | 0:9b334a45a8ff | 370 | |
bogdanm | 0:9b334a45a8ff | 371 | /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source |
bogdanm | 0:9b334a45a8ff | 372 | * @{ |
bogdanm | 0:9b334a45a8ff | 373 | */ |
bogdanm | 0:9b334a45a8ff | 374 | #define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 375 | #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 |
bogdanm | 0:9b334a45a8ff | 376 | #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 |
bogdanm | 0:9b334a45a8ff | 377 | #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL |
bogdanm | 0:9b334a45a8ff | 378 | /** |
bogdanm | 0:9b334a45a8ff | 379 | * @} |
bogdanm | 0:9b334a45a8ff | 380 | */ |
bogdanm | 0:9b334a45a8ff | 381 | |
bogdanm | 0:9b334a45a8ff | 382 | /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source |
bogdanm | 0:9b334a45a8ff | 383 | * @{ |
bogdanm | 0:9b334a45a8ff | 384 | */ |
bogdanm | 0:9b334a45a8ff | 385 | #define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 386 | #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 |
bogdanm | 0:9b334a45a8ff | 387 | #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 |
bogdanm | 0:9b334a45a8ff | 388 | #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL |
bogdanm | 0:9b334a45a8ff | 389 | /** |
bogdanm | 0:9b334a45a8ff | 390 | * @} |
bogdanm | 0:9b334a45a8ff | 391 | */ |
bogdanm | 0:9b334a45a8ff | 392 | |
bogdanm | 0:9b334a45a8ff | 393 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 394 | /** @defgroup RCCEx_USB_Clock_Source USB Clock Source |
bogdanm | 0:9b334a45a8ff | 395 | * @{ |
bogdanm | 0:9b334a45a8ff | 396 | */ |
bogdanm | 0:9b334a45a8ff | 397 | #define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 398 | #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 |
bogdanm | 0:9b334a45a8ff | 399 | #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 |
bogdanm | 0:9b334a45a8ff | 400 | #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL |
bogdanm | 0:9b334a45a8ff | 401 | /** |
bogdanm | 0:9b334a45a8ff | 402 | * @} |
bogdanm | 0:9b334a45a8ff | 403 | */ |
bogdanm | 0:9b334a45a8ff | 404 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 405 | |
bogdanm | 0:9b334a45a8ff | 406 | /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source |
bogdanm | 0:9b334a45a8ff | 407 | * @{ |
bogdanm | 0:9b334a45a8ff | 408 | */ |
bogdanm | 0:9b334a45a8ff | 409 | #define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 410 | #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 |
bogdanm | 0:9b334a45a8ff | 411 | #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 |
bogdanm | 0:9b334a45a8ff | 412 | #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL |
bogdanm | 0:9b334a45a8ff | 413 | /** |
bogdanm | 0:9b334a45a8ff | 414 | * @} |
bogdanm | 0:9b334a45a8ff | 415 | */ |
bogdanm | 0:9b334a45a8ff | 416 | |
bogdanm | 0:9b334a45a8ff | 417 | /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source |
bogdanm | 0:9b334a45a8ff | 418 | * @{ |
bogdanm | 0:9b334a45a8ff | 419 | */ |
bogdanm | 0:9b334a45a8ff | 420 | #define RCC_SWPMI1CLKSOURCE_PCLK ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 421 | #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL |
bogdanm | 0:9b334a45a8ff | 422 | /** |
bogdanm | 0:9b334a45a8ff | 423 | * @} |
bogdanm | 0:9b334a45a8ff | 424 | */ |
bogdanm | 0:9b334a45a8ff | 425 | |
bogdanm | 0:9b334a45a8ff | 426 | /** @defgroup RCCEx_DFSDM_Clock_Source DFSDM Clock Source |
bogdanm | 0:9b334a45a8ff | 427 | * @{ |
bogdanm | 0:9b334a45a8ff | 428 | */ |
bogdanm | 0:9b334a45a8ff | 429 | #define RCC_DFSDMCLKSOURCE_PCLK ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 430 | #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_CCIPR_DFSDMSEL |
bogdanm | 0:9b334a45a8ff | 431 | /** |
bogdanm | 0:9b334a45a8ff | 432 | * @} |
bogdanm | 0:9b334a45a8ff | 433 | */ |
bogdanm | 0:9b334a45a8ff | 434 | |
bogdanm | 0:9b334a45a8ff | 435 | /** |
bogdanm | 0:9b334a45a8ff | 436 | * @} |
bogdanm | 0:9b334a45a8ff | 437 | */ |
bogdanm | 0:9b334a45a8ff | 438 | |
bogdanm | 0:9b334a45a8ff | 439 | /* Exported macros -----------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 440 | /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros |
bogdanm | 0:9b334a45a8ff | 441 | * @{ |
bogdanm | 0:9b334a45a8ff | 442 | */ |
bogdanm | 0:9b334a45a8ff | 443 | |
bogdanm | 0:9b334a45a8ff | 444 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable |
bogdanm | 0:9b334a45a8ff | 445 | * @brief Enable or disable the AHB2 peripheral clock. |
bogdanm | 0:9b334a45a8ff | 446 | * @note After reset, the peripheral clock (used for registers read/write access) |
bogdanm | 0:9b334a45a8ff | 447 | * is disabled and the application software has to enable this clock before |
bogdanm | 0:9b334a45a8ff | 448 | * using it. |
bogdanm | 0:9b334a45a8ff | 449 | * @{ |
bogdanm | 0:9b334a45a8ff | 450 | */ |
bogdanm | 0:9b334a45a8ff | 451 | |
bogdanm | 0:9b334a45a8ff | 452 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 453 | #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ |
bogdanm | 0:9b334a45a8ff | 454 | __IO uint32_t tmpreg; \ |
bogdanm | 0:9b334a45a8ff | 455 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ |
bogdanm | 0:9b334a45a8ff | 456 | /* Delay after an RCC peripheral clock enabling */ \ |
bogdanm | 0:9b334a45a8ff | 457 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ |
bogdanm | 0:9b334a45a8ff | 458 | UNUSED(tmpreg); \ |
bogdanm | 0:9b334a45a8ff | 459 | } while(0) |
bogdanm | 0:9b334a45a8ff | 460 | |
bogdanm | 0:9b334a45a8ff | 461 | #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); |
bogdanm | 0:9b334a45a8ff | 462 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 463 | |
bogdanm | 0:9b334a45a8ff | 464 | |
bogdanm | 0:9b334a45a8ff | 465 | #if defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 466 | #define __HAL_RCC_AES_CLK_ENABLE() do { \ |
bogdanm | 0:9b334a45a8ff | 467 | __IO uint32_t tmpreg; \ |
bogdanm | 0:9b334a45a8ff | 468 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ |
bogdanm | 0:9b334a45a8ff | 469 | /* Delay after an RCC peripheral clock enabling */ \ |
bogdanm | 0:9b334a45a8ff | 470 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ |
bogdanm | 0:9b334a45a8ff | 471 | UNUSED(tmpreg); \ |
bogdanm | 0:9b334a45a8ff | 472 | } while(0) |
bogdanm | 0:9b334a45a8ff | 473 | |
bogdanm | 0:9b334a45a8ff | 474 | #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); |
bogdanm | 0:9b334a45a8ff | 475 | #endif /* STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 476 | |
bogdanm | 0:9b334a45a8ff | 477 | /** |
bogdanm | 0:9b334a45a8ff | 478 | * @} |
bogdanm | 0:9b334a45a8ff | 479 | */ |
bogdanm | 0:9b334a45a8ff | 480 | |
bogdanm | 0:9b334a45a8ff | 481 | /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable |
bogdanm | 0:9b334a45a8ff | 482 | * @brief Enable or disable the APB1 peripheral clock. |
bogdanm | 0:9b334a45a8ff | 483 | * @note After reset, the peripheral clock (used for registers read/write access) |
bogdanm | 0:9b334a45a8ff | 484 | * is disabled and the application software has to enable this clock before |
bogdanm | 0:9b334a45a8ff | 485 | * using it. |
bogdanm | 0:9b334a45a8ff | 486 | * @{ |
bogdanm | 0:9b334a45a8ff | 487 | */ |
bogdanm | 0:9b334a45a8ff | 488 | #if defined(STM32L476xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 489 | #define __HAL_RCC_LCD_CLK_ENABLE() do { \ |
bogdanm | 0:9b334a45a8ff | 490 | __IO uint32_t tmpreg; \ |
bogdanm | 0:9b334a45a8ff | 491 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ |
bogdanm | 0:9b334a45a8ff | 492 | /* Delay after an RCC peripheral clock enabling */ \ |
bogdanm | 0:9b334a45a8ff | 493 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ |
bogdanm | 0:9b334a45a8ff | 494 | UNUSED(tmpreg); \ |
bogdanm | 0:9b334a45a8ff | 495 | } while(0) |
bogdanm | 0:9b334a45a8ff | 496 | |
bogdanm | 0:9b334a45a8ff | 497 | #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); |
bogdanm | 0:9b334a45a8ff | 498 | #endif /* STM32L476xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 499 | |
bogdanm | 0:9b334a45a8ff | 500 | /** |
bogdanm | 0:9b334a45a8ff | 501 | * @} |
bogdanm | 0:9b334a45a8ff | 502 | */ |
bogdanm | 0:9b334a45a8ff | 503 | |
bogdanm | 0:9b334a45a8ff | 504 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status |
bogdanm | 0:9b334a45a8ff | 505 | * @brief Macros to get the status of the AHB2 peripheral clock. |
bogdanm | 0:9b334a45a8ff | 506 | * @note After reset, the peripheral clock (used for registers read/write access) |
bogdanm | 0:9b334a45a8ff | 507 | * is disabled and the application software has to enable this clock before |
bogdanm | 0:9b334a45a8ff | 508 | * using it. |
bogdanm | 0:9b334a45a8ff | 509 | * @{ |
bogdanm | 0:9b334a45a8ff | 510 | */ |
bogdanm | 0:9b334a45a8ff | 511 | |
bogdanm | 0:9b334a45a8ff | 512 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 513 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET) |
bogdanm | 0:9b334a45a8ff | 514 | |
bogdanm | 0:9b334a45a8ff | 515 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET) |
bogdanm | 0:9b334a45a8ff | 516 | #endif /* STM32L475xx || STM32L476xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 517 | |
bogdanm | 0:9b334a45a8ff | 518 | |
bogdanm | 0:9b334a45a8ff | 519 | #if defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 520 | #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET) |
bogdanm | 0:9b334a45a8ff | 521 | |
bogdanm | 0:9b334a45a8ff | 522 | #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET) |
bogdanm | 0:9b334a45a8ff | 523 | #endif /* STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 524 | |
bogdanm | 0:9b334a45a8ff | 525 | /** |
bogdanm | 0:9b334a45a8ff | 526 | * @} |
bogdanm | 0:9b334a45a8ff | 527 | */ |
bogdanm | 0:9b334a45a8ff | 528 | |
bogdanm | 0:9b334a45a8ff | 529 | /** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status |
bogdanm | 0:9b334a45a8ff | 530 | * @brief Macros to get the status of the APB1 peripheral clock. |
bogdanm | 0:9b334a45a8ff | 531 | * @note After reset, the peripheral clock (used for registers read/write access) |
bogdanm | 0:9b334a45a8ff | 532 | * is disabled and the application software has to enable this clock before |
bogdanm | 0:9b334a45a8ff | 533 | * using it. |
bogdanm | 0:9b334a45a8ff | 534 | * @{ |
bogdanm | 0:9b334a45a8ff | 535 | */ |
bogdanm | 0:9b334a45a8ff | 536 | #if defined(STM32L476xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 537 | #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET) |
bogdanm | 0:9b334a45a8ff | 538 | |
bogdanm | 0:9b334a45a8ff | 539 | #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET) |
bogdanm | 0:9b334a45a8ff | 540 | #endif /* STM32L476xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 541 | |
bogdanm | 0:9b334a45a8ff | 542 | /** |
bogdanm | 0:9b334a45a8ff | 543 | * @} |
bogdanm | 0:9b334a45a8ff | 544 | */ |
bogdanm | 0:9b334a45a8ff | 545 | |
bogdanm | 0:9b334a45a8ff | 546 | /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset |
bogdanm | 0:9b334a45a8ff | 547 | * @brief Force or release AHB2 peripheral reset. |
bogdanm | 0:9b334a45a8ff | 548 | * @{ |
bogdanm | 0:9b334a45a8ff | 549 | */ |
bogdanm | 0:9b334a45a8ff | 550 | |
bogdanm | 0:9b334a45a8ff | 551 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 552 | #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) |
bogdanm | 0:9b334a45a8ff | 553 | |
bogdanm | 0:9b334a45a8ff | 554 | #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) |
bogdanm | 0:9b334a45a8ff | 555 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 556 | |
bogdanm | 0:9b334a45a8ff | 557 | #if defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 558 | #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) |
bogdanm | 0:9b334a45a8ff | 559 | |
bogdanm | 0:9b334a45a8ff | 560 | #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) |
bogdanm | 0:9b334a45a8ff | 561 | #endif /* STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 562 | |
bogdanm | 0:9b334a45a8ff | 563 | /** |
bogdanm | 0:9b334a45a8ff | 564 | * @} |
bogdanm | 0:9b334a45a8ff | 565 | */ |
bogdanm | 0:9b334a45a8ff | 566 | |
bogdanm | 0:9b334a45a8ff | 567 | |
bogdanm | 0:9b334a45a8ff | 568 | /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset |
bogdanm | 0:9b334a45a8ff | 569 | * @brief Force or release APB1 peripheral reset. |
bogdanm | 0:9b334a45a8ff | 570 | * @{ |
bogdanm | 0:9b334a45a8ff | 571 | */ |
bogdanm | 0:9b334a45a8ff | 572 | #if defined(STM32L476xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 573 | #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) |
bogdanm | 0:9b334a45a8ff | 574 | |
bogdanm | 0:9b334a45a8ff | 575 | #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) |
bogdanm | 0:9b334a45a8ff | 576 | #endif /* STM32L476xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 577 | |
bogdanm | 0:9b334a45a8ff | 578 | /** |
bogdanm | 0:9b334a45a8ff | 579 | * @} |
bogdanm | 0:9b334a45a8ff | 580 | */ |
bogdanm | 0:9b334a45a8ff | 581 | |
bogdanm | 0:9b334a45a8ff | 582 | |
bogdanm | 0:9b334a45a8ff | 583 | /** @defgroup RCCEx_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable |
bogdanm | 0:9b334a45a8ff | 584 | * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. |
bogdanm | 0:9b334a45a8ff | 585 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
bogdanm | 0:9b334a45a8ff | 586 | * power consumption. |
bogdanm | 0:9b334a45a8ff | 587 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
bogdanm | 0:9b334a45a8ff | 588 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
bogdanm | 0:9b334a45a8ff | 589 | * @{ |
bogdanm | 0:9b334a45a8ff | 590 | */ |
bogdanm | 0:9b334a45a8ff | 591 | |
bogdanm | 0:9b334a45a8ff | 592 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 593 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) |
bogdanm | 0:9b334a45a8ff | 594 | |
bogdanm | 0:9b334a45a8ff | 595 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) |
bogdanm | 0:9b334a45a8ff | 596 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 597 | |
bogdanm | 0:9b334a45a8ff | 598 | #if defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 599 | #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) |
bogdanm | 0:9b334a45a8ff | 600 | |
bogdanm | 0:9b334a45a8ff | 601 | #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) |
bogdanm | 0:9b334a45a8ff | 602 | #endif /* STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 603 | |
bogdanm | 0:9b334a45a8ff | 604 | /** |
bogdanm | 0:9b334a45a8ff | 605 | * @} |
bogdanm | 0:9b334a45a8ff | 606 | */ |
bogdanm | 0:9b334a45a8ff | 607 | |
bogdanm | 0:9b334a45a8ff | 608 | |
bogdanm | 0:9b334a45a8ff | 609 | /** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable |
bogdanm | 0:9b334a45a8ff | 610 | * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
bogdanm | 0:9b334a45a8ff | 611 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
bogdanm | 0:9b334a45a8ff | 612 | * power consumption. |
bogdanm | 0:9b334a45a8ff | 613 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
bogdanm | 0:9b334a45a8ff | 614 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
bogdanm | 0:9b334a45a8ff | 615 | * @{ |
bogdanm | 0:9b334a45a8ff | 616 | */ |
bogdanm | 0:9b334a45a8ff | 617 | |
bogdanm | 0:9b334a45a8ff | 618 | #if defined(STM32L476xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 619 | #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) |
bogdanm | 0:9b334a45a8ff | 620 | |
bogdanm | 0:9b334a45a8ff | 621 | #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) |
bogdanm | 0:9b334a45a8ff | 622 | #endif /* STM32L476xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 623 | |
bogdanm | 0:9b334a45a8ff | 624 | /** |
bogdanm | 0:9b334a45a8ff | 625 | * @} |
bogdanm | 0:9b334a45a8ff | 626 | */ |
bogdanm | 0:9b334a45a8ff | 627 | |
bogdanm | 0:9b334a45a8ff | 628 | /** @defgroup RCCEx_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enable Disable Status |
bogdanm | 0:9b334a45a8ff | 629 | * @brief Macros to get the status of the AHB2 peripheral clock during Low Power (Sleep) mode. |
bogdanm | 0:9b334a45a8ff | 630 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
bogdanm | 0:9b334a45a8ff | 631 | * power consumption. |
bogdanm | 0:9b334a45a8ff | 632 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
bogdanm | 0:9b334a45a8ff | 633 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
bogdanm | 0:9b334a45a8ff | 634 | * @{ |
bogdanm | 0:9b334a45a8ff | 635 | */ |
bogdanm | 0:9b334a45a8ff | 636 | |
bogdanm | 0:9b334a45a8ff | 637 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 638 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET) |
bogdanm | 0:9b334a45a8ff | 639 | |
bogdanm | 0:9b334a45a8ff | 640 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET) |
bogdanm | 0:9b334a45a8ff | 641 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 642 | |
bogdanm | 0:9b334a45a8ff | 643 | #if defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 644 | #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET) |
bogdanm | 0:9b334a45a8ff | 645 | |
bogdanm | 0:9b334a45a8ff | 646 | #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET) |
bogdanm | 0:9b334a45a8ff | 647 | #endif /* STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 648 | |
bogdanm | 0:9b334a45a8ff | 649 | /** |
bogdanm | 0:9b334a45a8ff | 650 | * @} |
bogdanm | 0:9b334a45a8ff | 651 | */ |
bogdanm | 0:9b334a45a8ff | 652 | |
bogdanm | 0:9b334a45a8ff | 653 | |
bogdanm | 0:9b334a45a8ff | 654 | /** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status |
bogdanm | 0:9b334a45a8ff | 655 | * @brief Macros to get the status of the APB1 peripheral clock during Low Power (Sleep) mode. |
bogdanm | 0:9b334a45a8ff | 656 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
bogdanm | 0:9b334a45a8ff | 657 | * power consumption. |
bogdanm | 0:9b334a45a8ff | 658 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
bogdanm | 0:9b334a45a8ff | 659 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
bogdanm | 0:9b334a45a8ff | 660 | * @{ |
bogdanm | 0:9b334a45a8ff | 661 | */ |
bogdanm | 0:9b334a45a8ff | 662 | |
bogdanm | 0:9b334a45a8ff | 663 | #if defined(STM32L476xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 664 | #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) |
bogdanm | 0:9b334a45a8ff | 665 | |
bogdanm | 0:9b334a45a8ff | 666 | #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) |
bogdanm | 0:9b334a45a8ff | 667 | #endif /* STM32L476xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 668 | |
bogdanm | 0:9b334a45a8ff | 669 | /** |
bogdanm | 0:9b334a45a8ff | 670 | * @} |
bogdanm | 0:9b334a45a8ff | 671 | */ |
bogdanm | 0:9b334a45a8ff | 672 | |
bogdanm | 0:9b334a45a8ff | 673 | /** |
bogdanm | 0:9b334a45a8ff | 674 | * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. |
bogdanm | 0:9b334a45a8ff | 675 | * |
bogdanm | 0:9b334a45a8ff | 676 | * @note This function must be used only when the PLLSAI1 is disabled. |
bogdanm | 0:9b334a45a8ff | 677 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
bogdanm | 0:9b334a45a8ff | 678 | * __HAL_RCC_PLL_CONFIG() macro) |
bogdanm | 0:9b334a45a8ff | 679 | * |
bogdanm | 0:9b334a45a8ff | 680 | * @param __PLLSAI1N__: specifies the multiplication factor for PLLSAI1 VCO output clock. |
bogdanm | 0:9b334a45a8ff | 681 | * This parameter must be a number between 8 and 86. |
bogdanm | 0:9b334a45a8ff | 682 | * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO |
bogdanm | 0:9b334a45a8ff | 683 | * output frequency is between 64 and 344 MHz. |
bogdanm | 0:9b334a45a8ff | 684 | * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N |
bogdanm | 0:9b334a45a8ff | 685 | * |
bogdanm | 0:9b334a45a8ff | 686 | * @param __PLLSAI1P__: specifies the division factor for SAI clock. |
bogdanm | 0:9b334a45a8ff | 687 | * This parameter must be a number in the range (7 or 17). |
bogdanm | 0:9b334a45a8ff | 688 | * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P |
bogdanm | 0:9b334a45a8ff | 689 | * |
bogdanm | 0:9b334a45a8ff | 690 | * @param __PLLSAI1Q__: specifies the division factor for USB/RNG/SDMMC1 clock. |
bogdanm | 0:9b334a45a8ff | 691 | * This parameter must be in the range (2, 4, 6 or 8). |
bogdanm | 0:9b334a45a8ff | 692 | * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q |
bogdanm | 0:9b334a45a8ff | 693 | * |
bogdanm | 0:9b334a45a8ff | 694 | * @param __PLLSAI1R__: specifies the division factor for SAR ADC clock. |
bogdanm | 0:9b334a45a8ff | 695 | * This parameter must be in the range (2, 4, 6 or 8). |
bogdanm | 0:9b334a45a8ff | 696 | * ADC clock frequency = f(PLLSAI1) / PLLSAI1R |
bogdanm | 0:9b334a45a8ff | 697 | * |
bogdanm | 0:9b334a45a8ff | 698 | * @retval None |
bogdanm | 0:9b334a45a8ff | 699 | */ |
bogdanm | 0:9b334a45a8ff | 700 | #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ |
bogdanm | 0:9b334a45a8ff | 701 | WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << 8U) | (((__PLLSAI1P__) >> 4U) << 17U) | \ |
bogdanm | 0:9b334a45a8ff | 702 | ((((__PLLSAI1Q__) >> 1U) - 1) << 21U) | ((((__PLLSAI1R__) >> 1U) - 1) << 25U)) |
bogdanm | 0:9b334a45a8ff | 703 | |
bogdanm | 0:9b334a45a8ff | 704 | /** |
bogdanm | 0:9b334a45a8ff | 705 | * @brief Macro to configure the PLLSAI1 clock multiplication factor N. |
bogdanm | 0:9b334a45a8ff | 706 | * |
bogdanm | 0:9b334a45a8ff | 707 | * @note This function must be used only when the PLLSAI1 is disabled. |
bogdanm | 0:9b334a45a8ff | 708 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
bogdanm | 0:9b334a45a8ff | 709 | * __HAL_RCC_PLL_CONFIG() macro) |
bogdanm | 0:9b334a45a8ff | 710 | * |
bogdanm | 0:9b334a45a8ff | 711 | * @param __PLLSAI1N__: specifies the multiplication factor for PLLSAI1 VCO output clock. |
bogdanm | 0:9b334a45a8ff | 712 | * This parameter must be a number between 8 and 86. |
bogdanm | 0:9b334a45a8ff | 713 | * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO |
bogdanm | 0:9b334a45a8ff | 714 | * output frequency is between 64 and 344 MHz. |
bogdanm | 0:9b334a45a8ff | 715 | * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N |
bogdanm | 0:9b334a45a8ff | 716 | * |
bogdanm | 0:9b334a45a8ff | 717 | * @retval None |
bogdanm | 0:9b334a45a8ff | 718 | */ |
bogdanm | 0:9b334a45a8ff | 719 | #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ |
bogdanm | 0:9b334a45a8ff | 720 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << 8U) |
bogdanm | 0:9b334a45a8ff | 721 | |
bogdanm | 0:9b334a45a8ff | 722 | /** @brief Macro to configure the PLLSAI1 clock division factor P. |
bogdanm | 0:9b334a45a8ff | 723 | * |
bogdanm | 0:9b334a45a8ff | 724 | * @note This function must be used only when the PLLSAI1 is disabled. |
bogdanm | 0:9b334a45a8ff | 725 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
bogdanm | 0:9b334a45a8ff | 726 | * __HAL_RCC_PLL_CONFIG() macro) |
bogdanm | 0:9b334a45a8ff | 727 | * |
bogdanm | 0:9b334a45a8ff | 728 | * @param __PLLSAI1P__: specifies the division factor for SAI clock. |
bogdanm | 0:9b334a45a8ff | 729 | * This parameter must be a number in the range (7 or 17). |
bogdanm | 0:9b334a45a8ff | 730 | * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P |
bogdanm | 0:9b334a45a8ff | 731 | * |
bogdanm | 0:9b334a45a8ff | 732 | * @retval None |
bogdanm | 0:9b334a45a8ff | 733 | */ |
bogdanm | 0:9b334a45a8ff | 734 | #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ |
bogdanm | 0:9b334a45a8ff | 735 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << 17U) |
bogdanm | 0:9b334a45a8ff | 736 | |
bogdanm | 0:9b334a45a8ff | 737 | /** @brief Macro to configure the PLLSAI1 clock division factor Q. |
bogdanm | 0:9b334a45a8ff | 738 | * |
bogdanm | 0:9b334a45a8ff | 739 | * @note This function must be used only when the PLLSAI1 is disabled. |
bogdanm | 0:9b334a45a8ff | 740 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
bogdanm | 0:9b334a45a8ff | 741 | * __HAL_RCC_PLL_CONFIG() macro) |
bogdanm | 0:9b334a45a8ff | 742 | * |
bogdanm | 0:9b334a45a8ff | 743 | * @param __PLLSAI1Q__: specifies the division factor for USB/RNG/SDMMC1 clock. |
bogdanm | 0:9b334a45a8ff | 744 | * This parameter must be in the range (2, 4, 6 or 8). |
bogdanm | 0:9b334a45a8ff | 745 | * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q |
bogdanm | 0:9b334a45a8ff | 746 | * |
bogdanm | 0:9b334a45a8ff | 747 | * @retval None |
bogdanm | 0:9b334a45a8ff | 748 | */ |
bogdanm | 0:9b334a45a8ff | 749 | #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ |
bogdanm | 0:9b334a45a8ff | 750 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1) << 21U) |
bogdanm | 0:9b334a45a8ff | 751 | |
bogdanm | 0:9b334a45a8ff | 752 | /** @brief Macro to configure the PLLSAI1 clock division factor R. |
bogdanm | 0:9b334a45a8ff | 753 | * |
bogdanm | 0:9b334a45a8ff | 754 | * @note This function must be used only when the PLLSAI1 is disabled. |
bogdanm | 0:9b334a45a8ff | 755 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
bogdanm | 0:9b334a45a8ff | 756 | * __HAL_RCC_PLL_CONFIG() macro) |
bogdanm | 0:9b334a45a8ff | 757 | * |
bogdanm | 0:9b334a45a8ff | 758 | * @param __PLLSAI1R__: specifies the division factor for ADC clock. |
bogdanm | 0:9b334a45a8ff | 759 | * This parameter must be in the range (2, 4, 6 or 8) |
bogdanm | 0:9b334a45a8ff | 760 | * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R |
bogdanm | 0:9b334a45a8ff | 761 | * |
bogdanm | 0:9b334a45a8ff | 762 | * @retval None |
bogdanm | 0:9b334a45a8ff | 763 | */ |
bogdanm | 0:9b334a45a8ff | 764 | #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ |
bogdanm | 0:9b334a45a8ff | 765 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1) << 25U) |
bogdanm | 0:9b334a45a8ff | 766 | |
bogdanm | 0:9b334a45a8ff | 767 | /** |
bogdanm | 0:9b334a45a8ff | 768 | * @brief Macros to enable or disable the PLLSAI1. |
bogdanm | 0:9b334a45a8ff | 769 | * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. |
bogdanm | 0:9b334a45a8ff | 770 | * @retval None |
bogdanm | 0:9b334a45a8ff | 771 | */ |
bogdanm | 0:9b334a45a8ff | 772 | |
bogdanm | 0:9b334a45a8ff | 773 | #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON) |
bogdanm | 0:9b334a45a8ff | 774 | |
bogdanm | 0:9b334a45a8ff | 775 | #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON) |
bogdanm | 0:9b334a45a8ff | 776 | |
bogdanm | 0:9b334a45a8ff | 777 | /** |
bogdanm | 0:9b334a45a8ff | 778 | * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). |
bogdanm | 0:9b334a45a8ff | 779 | * @note Enabling and disabling those clocks can be done without the need to stop the PLL. |
bogdanm | 0:9b334a45a8ff | 780 | * This is mainly used to save Power. |
bogdanm | 0:9b334a45a8ff | 781 | * @param __PLLSAI1_CLOCKOUT__: specifies the PLLSAI1 clock to be output. |
bogdanm | 0:9b334a45a8ff | 782 | * This parameter can be one or a combination of the following values: |
bogdanm | 0:9b334a45a8ff | 783 | * @arg RCC_PLLSAI1_SAI1CLK: This clock is used to generate an accurate clock to achieve |
bogdanm | 0:9b334a45a8ff | 784 | * high-quality audio performance on SAI interface in case. |
bogdanm | 0:9b334a45a8ff | 785 | * @arg RCC_PLLSAI1_USB2CLK: This clock is used to generate the clock for the USB OTG FS (48 MHz), |
bogdanm | 0:9b334a45a8ff | 786 | * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). |
bogdanm | 0:9b334a45a8ff | 787 | * @arg RCC_PLLSAI1_ADC1CLK: Clock used to clock ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 788 | * @retval None |
bogdanm | 0:9b334a45a8ff | 789 | */ |
bogdanm | 0:9b334a45a8ff | 790 | |
bogdanm | 0:9b334a45a8ff | 791 | #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) |
bogdanm | 0:9b334a45a8ff | 792 | |
bogdanm | 0:9b334a45a8ff | 793 | #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) |
bogdanm | 0:9b334a45a8ff | 794 | |
bogdanm | 0:9b334a45a8ff | 795 | /** |
bogdanm | 0:9b334a45a8ff | 796 | * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). |
bogdanm | 0:9b334a45a8ff | 797 | * @param __PLLSAI1_CLOCKOUT__: specifies the PLLSAI1 clock to be output. |
bogdanm | 0:9b334a45a8ff | 798 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 799 | * @arg RCC_PLLSAI1_SAI1CLK: This clock is used to generate an accurate clock to achieve |
bogdanm | 0:9b334a45a8ff | 800 | * high-quality audio performance on SAI interface in case. |
bogdanm | 0:9b334a45a8ff | 801 | * @arg RCC_PLLSAI1_USB2CLK: This clock is used to generate the clock for the USB OTG FS (48 MHz), |
bogdanm | 0:9b334a45a8ff | 802 | * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). |
bogdanm | 0:9b334a45a8ff | 803 | * @arg RCC_PLLSAI1_ADC1CLK: Clock used to clock ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 804 | * @retval SET / RESET |
bogdanm | 0:9b334a45a8ff | 805 | */ |
bogdanm | 0:9b334a45a8ff | 806 | #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) |
bogdanm | 0:9b334a45a8ff | 807 | |
bogdanm | 0:9b334a45a8ff | 808 | /** |
bogdanm | 0:9b334a45a8ff | 809 | * @brief Macro to configure the PLLSAI2 clock multiplication and division factors. |
bogdanm | 0:9b334a45a8ff | 810 | * |
bogdanm | 0:9b334a45a8ff | 811 | * @note This function must be used only when the PLLSAI2 is disabled. |
bogdanm | 0:9b334a45a8ff | 812 | * @note PLLSAI2 clock source is common with the main PLL (configured through |
bogdanm | 0:9b334a45a8ff | 813 | * __HAL_RCC_PLL_CONFIG() macro) |
bogdanm | 0:9b334a45a8ff | 814 | * |
bogdanm | 0:9b334a45a8ff | 815 | * @param __PLLSAI2N__: specifies the multiplication factor for PLLSAI2 VCO output clock. |
bogdanm | 0:9b334a45a8ff | 816 | * This parameter must be a number between 8 and 86. |
bogdanm | 0:9b334a45a8ff | 817 | * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO |
bogdanm | 0:9b334a45a8ff | 818 | * output frequency is between 64 and 344 MHz. |
bogdanm | 0:9b334a45a8ff | 819 | * |
bogdanm | 0:9b334a45a8ff | 820 | * @param __PLLSAI2P__: specifies the division factor for SAI clock. |
bogdanm | 0:9b334a45a8ff | 821 | * This parameter must be a number in the range (7 or 17). |
bogdanm | 0:9b334a45a8ff | 822 | * |
bogdanm | 0:9b334a45a8ff | 823 | * |
bogdanm | 0:9b334a45a8ff | 824 | * @param __PLLSAI2R__: specifies the division factor for SAR ADC clock. |
bogdanm | 0:9b334a45a8ff | 825 | * This parameter must be in the range (2, 4, 6 or 8) |
bogdanm | 0:9b334a45a8ff | 826 | * |
bogdanm | 0:9b334a45a8ff | 827 | * @retval None |
bogdanm | 0:9b334a45a8ff | 828 | */ |
bogdanm | 0:9b334a45a8ff | 829 | |
bogdanm | 0:9b334a45a8ff | 830 | #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ |
bogdanm | 0:9b334a45a8ff | 831 | WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << 8U) | (((__PLLSAI2P__) >> 4U) << 17U) | \ |
bogdanm | 0:9b334a45a8ff | 832 | ((((__PLLSAI2R__) >> 1U) - 1) << 25U)) |
bogdanm | 0:9b334a45a8ff | 833 | |
bogdanm | 0:9b334a45a8ff | 834 | /** |
bogdanm | 0:9b334a45a8ff | 835 | * @brief Macro to configure the PLLSAI2 clock multiplication factor N. |
bogdanm | 0:9b334a45a8ff | 836 | * |
bogdanm | 0:9b334a45a8ff | 837 | * @note This function must be used only when the PLLSAI2 is disabled. |
bogdanm | 0:9b334a45a8ff | 838 | * @note PLLSAI2 clock source is common with the main PLL (configured through |
bogdanm | 0:9b334a45a8ff | 839 | * __HAL_RCC_PLL_CONFIG() macro) |
bogdanm | 0:9b334a45a8ff | 840 | * |
bogdanm | 0:9b334a45a8ff | 841 | * @param __PLLSAI2N__: specifies the multiplication factor for PLLSAI2 VCO output clock. |
bogdanm | 0:9b334a45a8ff | 842 | * This parameter must be a number between 8 and 86. |
bogdanm | 0:9b334a45a8ff | 843 | * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO |
bogdanm | 0:9b334a45a8ff | 844 | * output frequency is between 64 and 344 MHz. |
bogdanm | 0:9b334a45a8ff | 845 | * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N |
bogdanm | 0:9b334a45a8ff | 846 | * |
bogdanm | 0:9b334a45a8ff | 847 | * @retval None |
bogdanm | 0:9b334a45a8ff | 848 | */ |
bogdanm | 0:9b334a45a8ff | 849 | #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ |
bogdanm | 0:9b334a45a8ff | 850 | MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << 8U) |
bogdanm | 0:9b334a45a8ff | 851 | |
bogdanm | 0:9b334a45a8ff | 852 | /** @brief Macro to configure the PLLSAI2 clock division factor P. |
bogdanm | 0:9b334a45a8ff | 853 | * |
bogdanm | 0:9b334a45a8ff | 854 | * @note This function must be used only when the PLLSAI2 is disabled. |
bogdanm | 0:9b334a45a8ff | 855 | * @note PLLSAI2 clock source is common with the main PLL (configured through |
bogdanm | 0:9b334a45a8ff | 856 | * __HAL_RCC_PLL_CONFIG() macro) |
bogdanm | 0:9b334a45a8ff | 857 | * |
bogdanm | 0:9b334a45a8ff | 858 | * @param __PLLSAI2P__: specifies the division factor. |
bogdanm | 0:9b334a45a8ff | 859 | * This parameter must be a number in the range (7 or 17). |
bogdanm | 0:9b334a45a8ff | 860 | * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__ |
bogdanm | 0:9b334a45a8ff | 861 | * |
bogdanm | 0:9b334a45a8ff | 862 | * @retval None |
bogdanm | 0:9b334a45a8ff | 863 | */ |
bogdanm | 0:9b334a45a8ff | 864 | #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ |
bogdanm | 0:9b334a45a8ff | 865 | MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << 17U) |
bogdanm | 0:9b334a45a8ff | 866 | |
bogdanm | 0:9b334a45a8ff | 867 | /** @brief Macro to configure the PLLSAI2 clock division factor R. |
bogdanm | 0:9b334a45a8ff | 868 | * |
bogdanm | 0:9b334a45a8ff | 869 | * @note This function must be used only when the PLLSAI2 is disabled. |
bogdanm | 0:9b334a45a8ff | 870 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
bogdanm | 0:9b334a45a8ff | 871 | * __HAL_RCC_PLL_CONFIG() macro) |
bogdanm | 0:9b334a45a8ff | 872 | * |
bogdanm | 0:9b334a45a8ff | 873 | * @param __PLLSAI2R__: specifies the division factor. |
bogdanm | 0:9b334a45a8ff | 874 | * This parameter must be in the range (2, 4, 6 or 8). |
bogdanm | 0:9b334a45a8ff | 875 | * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2Q__ |
bogdanm | 0:9b334a45a8ff | 876 | * |
bogdanm | 0:9b334a45a8ff | 877 | * @retval None |
bogdanm | 0:9b334a45a8ff | 878 | */ |
bogdanm | 0:9b334a45a8ff | 879 | #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \ |
bogdanm | 0:9b334a45a8ff | 880 | MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1) << 25U) |
bogdanm | 0:9b334a45a8ff | 881 | |
bogdanm | 0:9b334a45a8ff | 882 | /** |
bogdanm | 0:9b334a45a8ff | 883 | * @brief Macros to enable or disable the PLLSAI2. |
bogdanm | 0:9b334a45a8ff | 884 | * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes. |
bogdanm | 0:9b334a45a8ff | 885 | * @retval None |
bogdanm | 0:9b334a45a8ff | 886 | */ |
bogdanm | 0:9b334a45a8ff | 887 | |
bogdanm | 0:9b334a45a8ff | 888 | #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON) |
bogdanm | 0:9b334a45a8ff | 889 | |
bogdanm | 0:9b334a45a8ff | 890 | #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) |
bogdanm | 0:9b334a45a8ff | 891 | |
bogdanm | 0:9b334a45a8ff | 892 | /** |
bogdanm | 0:9b334a45a8ff | 893 | * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2). |
bogdanm | 0:9b334a45a8ff | 894 | * @note Enabling and disabling those clocks can be done without the need to stop the PLL. |
bogdanm | 0:9b334a45a8ff | 895 | * This is mainly used to save Power. |
bogdanm | 0:9b334a45a8ff | 896 | * @param __PLLSAI2_CLOCKOUT__: specifies the PLLSAI2 clock to be output. |
bogdanm | 0:9b334a45a8ff | 897 | * This parameter can be one or a combination of the following values: |
bogdanm | 0:9b334a45a8ff | 898 | * @arg RCC_PLLSAI2_SAI2CLK: This clock is used to generate an accurate clock to achieve |
bogdanm | 0:9b334a45a8ff | 899 | * high-quality audio performance on SAI interface in case. |
bogdanm | 0:9b334a45a8ff | 900 | * @arg RCC_PLLSAI2_ADC2CLK: Clock used to clock ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 901 | * @retval None |
bogdanm | 0:9b334a45a8ff | 902 | */ |
bogdanm | 0:9b334a45a8ff | 903 | |
bogdanm | 0:9b334a45a8ff | 904 | #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) |
bogdanm | 0:9b334a45a8ff | 905 | |
bogdanm | 0:9b334a45a8ff | 906 | #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) |
bogdanm | 0:9b334a45a8ff | 907 | |
bogdanm | 0:9b334a45a8ff | 908 | /** |
bogdanm | 0:9b334a45a8ff | 909 | * @brief Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2). |
bogdanm | 0:9b334a45a8ff | 910 | * @param __PLLSAI2_CLOCKOUT__: specifies the PLLSAI2 clock to be output. |
bogdanm | 0:9b334a45a8ff | 911 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 912 | * @arg RCC_PLLSAI2_SAI2CLK: This clock is used to generate an accurate clock to achieve |
bogdanm | 0:9b334a45a8ff | 913 | * high-quality audio performance on SAI interface in case. |
bogdanm | 0:9b334a45a8ff | 914 | * @arg RCC_PLLSAI2_ADC2CLK: Clock used to clock ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 915 | * @retval SET / RESET |
bogdanm | 0:9b334a45a8ff | 916 | */ |
bogdanm | 0:9b334a45a8ff | 917 | #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) |
bogdanm | 0:9b334a45a8ff | 918 | |
bogdanm | 0:9b334a45a8ff | 919 | /** |
bogdanm | 0:9b334a45a8ff | 920 | * @brief Macro to configure the SAI1 clock source. |
bogdanm | 0:9b334a45a8ff | 921 | * @param __SAI1_CLKSOURCE__: defines the SAI1 clock source. This clock is derived |
bogdanm | 0:9b334a45a8ff | 922 | * from the PLLSAI1, system PLL or external clock (through a dedicated pin). |
bogdanm | 0:9b334a45a8ff | 923 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 924 | * @arg RCC_SAI1CLKSOURCE_PLLSAI1: SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) |
bogdanm | 0:9b334a45a8ff | 925 | * @arg RCC_SAI1CLKSOURCE_PLLSAI2: SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) |
bogdanm | 0:9b334a45a8ff | 926 | * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL "P" clock (PLLSAI3CLK) |
bogdanm | 0:9b334a45a8ff | 927 | * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock (SAI1_EXTCLK) |
bogdanm | 0:9b334a45a8ff | 928 | * @retval None |
bogdanm | 0:9b334a45a8ff | 929 | */ |
bogdanm | 0:9b334a45a8ff | 930 | #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ |
bogdanm | 0:9b334a45a8ff | 931 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 932 | |
bogdanm | 0:9b334a45a8ff | 933 | /** @brief Macro to get the SAI1 clock source. |
bogdanm | 0:9b334a45a8ff | 934 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 935 | * @arg RCC_SAI1CLKSOURCE_PLLSAI1: SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) |
bogdanm | 0:9b334a45a8ff | 936 | * @arg RCC_SAI1CLKSOURCE_PLLSAI2: SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) |
bogdanm | 0:9b334a45a8ff | 937 | * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL "P" clock (PLLSAI3CLK) |
bogdanm | 0:9b334a45a8ff | 938 | * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock (SAI1_EXTCLK) |
bogdanm | 0:9b334a45a8ff | 939 | */ |
bogdanm | 0:9b334a45a8ff | 940 | #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))) |
bogdanm | 0:9b334a45a8ff | 941 | |
bogdanm | 0:9b334a45a8ff | 942 | /** |
bogdanm | 0:9b334a45a8ff | 943 | * @brief Macro to configure the SAI2 clock source. |
bogdanm | 0:9b334a45a8ff | 944 | * @param __SAI2_CLKSOURCE__: defines the SAI2 clock source. This clock is derived |
bogdanm | 0:9b334a45a8ff | 945 | * from the PLLSAI2, system PLL or external clock (through a dedicated pin). |
bogdanm | 0:9b334a45a8ff | 946 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 947 | * @arg RCC_SAI2CLKSOURCE_PLLSAI1: SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) |
bogdanm | 0:9b334a45a8ff | 948 | * @arg RCC_SAI2CLKSOURCE_PLLSAI2: SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) |
bogdanm | 0:9b334a45a8ff | 949 | * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL "P" clock (PLLSAI3CLK) |
bogdanm | 0:9b334a45a8ff | 950 | * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock (SAI2_EXTCLK) |
bogdanm | 0:9b334a45a8ff | 951 | * @retval None |
bogdanm | 0:9b334a45a8ff | 952 | */ |
bogdanm | 0:9b334a45a8ff | 953 | #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ |
bogdanm | 0:9b334a45a8ff | 954 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 955 | |
bogdanm | 0:9b334a45a8ff | 956 | /** @brief Macro to get the SAI2 clock source. |
bogdanm | 0:9b334a45a8ff | 957 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 958 | * @arg RCC_SAI2CLKSOURCE_PLLSAI1: SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) |
bogdanm | 0:9b334a45a8ff | 959 | * @arg RCC_SAI2CLKSOURCE_PLLSAI2: SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) |
bogdanm | 0:9b334a45a8ff | 960 | * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL "P" clock (PLLSAI3CLK) |
bogdanm | 0:9b334a45a8ff | 961 | * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock (SAI2_EXTCLK) |
bogdanm | 0:9b334a45a8ff | 962 | */ |
bogdanm | 0:9b334a45a8ff | 963 | #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))) |
bogdanm | 0:9b334a45a8ff | 964 | |
bogdanm | 0:9b334a45a8ff | 965 | /** @brief Macro to configure the I2C1 clock (I2C1CLK). |
bogdanm | 0:9b334a45a8ff | 966 | * |
bogdanm | 0:9b334a45a8ff | 967 | * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source. |
bogdanm | 0:9b334a45a8ff | 968 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 969 | * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock |
bogdanm | 0:9b334a45a8ff | 970 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
bogdanm | 0:9b334a45a8ff | 971 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
bogdanm | 0:9b334a45a8ff | 972 | * @retval None |
bogdanm | 0:9b334a45a8ff | 973 | */ |
bogdanm | 0:9b334a45a8ff | 974 | #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 975 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 976 | |
bogdanm | 0:9b334a45a8ff | 977 | /** @brief Macro to get the I2C1 clock source. |
bogdanm | 0:9b334a45a8ff | 978 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 979 | * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock |
bogdanm | 0:9b334a45a8ff | 980 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
bogdanm | 0:9b334a45a8ff | 981 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
bogdanm | 0:9b334a45a8ff | 982 | */ |
bogdanm | 0:9b334a45a8ff | 983 | #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) |
bogdanm | 0:9b334a45a8ff | 984 | |
bogdanm | 0:9b334a45a8ff | 985 | /** @brief Macro to configure the I2C2 clock (I2C2CLK). |
bogdanm | 0:9b334a45a8ff | 986 | * |
bogdanm | 0:9b334a45a8ff | 987 | * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source. |
bogdanm | 0:9b334a45a8ff | 988 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 989 | * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock |
bogdanm | 0:9b334a45a8ff | 990 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
bogdanm | 0:9b334a45a8ff | 991 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
bogdanm | 0:9b334a45a8ff | 992 | * @retval None |
bogdanm | 0:9b334a45a8ff | 993 | */ |
bogdanm | 0:9b334a45a8ff | 994 | #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 995 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 996 | |
bogdanm | 0:9b334a45a8ff | 997 | /** @brief Macro to get the I2C2 clock source. |
bogdanm | 0:9b334a45a8ff | 998 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 999 | * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock |
bogdanm | 0:9b334a45a8ff | 1000 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
bogdanm | 0:9b334a45a8ff | 1001 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
bogdanm | 0:9b334a45a8ff | 1002 | */ |
bogdanm | 0:9b334a45a8ff | 1003 | #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))) |
bogdanm | 0:9b334a45a8ff | 1004 | |
bogdanm | 0:9b334a45a8ff | 1005 | /** @brief Macro to configure the I2C3 clock (I2C3CLK). |
bogdanm | 0:9b334a45a8ff | 1006 | * |
bogdanm | 0:9b334a45a8ff | 1007 | * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source. |
bogdanm | 0:9b334a45a8ff | 1008 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1009 | * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock |
bogdanm | 0:9b334a45a8ff | 1010 | * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
bogdanm | 0:9b334a45a8ff | 1011 | * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
bogdanm | 0:9b334a45a8ff | 1012 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1013 | */ |
bogdanm | 0:9b334a45a8ff | 1014 | #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1015 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1016 | |
bogdanm | 0:9b334a45a8ff | 1017 | /** @brief Macro to get the I2C3 clock source. |
bogdanm | 0:9b334a45a8ff | 1018 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1019 | * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock |
bogdanm | 0:9b334a45a8ff | 1020 | * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
bogdanm | 0:9b334a45a8ff | 1021 | * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
bogdanm | 0:9b334a45a8ff | 1022 | */ |
bogdanm | 0:9b334a45a8ff | 1023 | #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))) |
bogdanm | 0:9b334a45a8ff | 1024 | |
bogdanm | 0:9b334a45a8ff | 1025 | /** @brief Macro to configure the USART1 clock (USART1CLK). |
bogdanm | 0:9b334a45a8ff | 1026 | * |
bogdanm | 0:9b334a45a8ff | 1027 | * @param __USART1_CLKSOURCE__: specifies the USART1 clock source. |
bogdanm | 0:9b334a45a8ff | 1028 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1029 | * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock |
bogdanm | 0:9b334a45a8ff | 1030 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
bogdanm | 0:9b334a45a8ff | 1031 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
bogdanm | 0:9b334a45a8ff | 1032 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
bogdanm | 0:9b334a45a8ff | 1033 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1034 | */ |
bogdanm | 0:9b334a45a8ff | 1035 | #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1036 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1037 | |
bogdanm | 0:9b334a45a8ff | 1038 | /** @brief Macro to get the USART1 clock source. |
bogdanm | 0:9b334a45a8ff | 1039 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1040 | * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock |
bogdanm | 0:9b334a45a8ff | 1041 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
bogdanm | 0:9b334a45a8ff | 1042 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
bogdanm | 0:9b334a45a8ff | 1043 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
bogdanm | 0:9b334a45a8ff | 1044 | */ |
bogdanm | 0:9b334a45a8ff | 1045 | #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) |
bogdanm | 0:9b334a45a8ff | 1046 | |
bogdanm | 0:9b334a45a8ff | 1047 | /** @brief Macro to configure the USART2 clock (USART2CLK). |
bogdanm | 0:9b334a45a8ff | 1048 | * |
bogdanm | 0:9b334a45a8ff | 1049 | * @param __USART2_CLKSOURCE__: specifies the USART2 clock source. |
bogdanm | 0:9b334a45a8ff | 1050 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1051 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
bogdanm | 0:9b334a45a8ff | 1052 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
bogdanm | 0:9b334a45a8ff | 1053 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
bogdanm | 0:9b334a45a8ff | 1054 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
bogdanm | 0:9b334a45a8ff | 1055 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1056 | */ |
bogdanm | 0:9b334a45a8ff | 1057 | #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1058 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1059 | |
bogdanm | 0:9b334a45a8ff | 1060 | /** @brief Macro to get the USART2 clock source. |
bogdanm | 0:9b334a45a8ff | 1061 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1062 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
bogdanm | 0:9b334a45a8ff | 1063 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
bogdanm | 0:9b334a45a8ff | 1064 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
bogdanm | 0:9b334a45a8ff | 1065 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
bogdanm | 0:9b334a45a8ff | 1066 | */ |
bogdanm | 0:9b334a45a8ff | 1067 | #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) |
bogdanm | 0:9b334a45a8ff | 1068 | |
bogdanm | 0:9b334a45a8ff | 1069 | /** @brief Macro to configure the USART3 clock (USART3CLK). |
bogdanm | 0:9b334a45a8ff | 1070 | * |
bogdanm | 0:9b334a45a8ff | 1071 | * @param __USART3_CLKSOURCE__: specifies the USART3 clock source. |
bogdanm | 0:9b334a45a8ff | 1072 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1073 | * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
bogdanm | 0:9b334a45a8ff | 1074 | * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
bogdanm | 0:9b334a45a8ff | 1075 | * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
bogdanm | 0:9b334a45a8ff | 1076 | * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
bogdanm | 0:9b334a45a8ff | 1077 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1078 | */ |
bogdanm | 0:9b334a45a8ff | 1079 | #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1080 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1081 | |
bogdanm | 0:9b334a45a8ff | 1082 | /** @brief Macro to get the USART3 clock source. |
bogdanm | 0:9b334a45a8ff | 1083 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1084 | * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
bogdanm | 0:9b334a45a8ff | 1085 | * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
bogdanm | 0:9b334a45a8ff | 1086 | * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
bogdanm | 0:9b334a45a8ff | 1087 | * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
bogdanm | 0:9b334a45a8ff | 1088 | */ |
bogdanm | 0:9b334a45a8ff | 1089 | #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))) |
bogdanm | 0:9b334a45a8ff | 1090 | |
bogdanm | 0:9b334a45a8ff | 1091 | /** @brief Macro to configure the UART4 clock (UART4CLK). |
bogdanm | 0:9b334a45a8ff | 1092 | * |
bogdanm | 0:9b334a45a8ff | 1093 | * @param __UART4_CLKSOURCE__: specifies the UART4 clock source. |
bogdanm | 0:9b334a45a8ff | 1094 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1095 | * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock |
bogdanm | 0:9b334a45a8ff | 1096 | * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock |
bogdanm | 0:9b334a45a8ff | 1097 | * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock |
bogdanm | 0:9b334a45a8ff | 1098 | * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock |
bogdanm | 0:9b334a45a8ff | 1099 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1100 | */ |
bogdanm | 0:9b334a45a8ff | 1101 | #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1102 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1103 | |
bogdanm | 0:9b334a45a8ff | 1104 | /** @brief Macro to get the UART4 clock source. |
bogdanm | 0:9b334a45a8ff | 1105 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1106 | * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock |
bogdanm | 0:9b334a45a8ff | 1107 | * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock |
bogdanm | 0:9b334a45a8ff | 1108 | * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock |
bogdanm | 0:9b334a45a8ff | 1109 | * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock |
bogdanm | 0:9b334a45a8ff | 1110 | */ |
bogdanm | 0:9b334a45a8ff | 1111 | #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))) |
bogdanm | 0:9b334a45a8ff | 1112 | |
bogdanm | 0:9b334a45a8ff | 1113 | /** @brief Macro to configure the UART5 clock (UART5CLK). |
bogdanm | 0:9b334a45a8ff | 1114 | * |
bogdanm | 0:9b334a45a8ff | 1115 | * @param __UART5_CLKSOURCE__: specifies the UART5 clock source. |
bogdanm | 0:9b334a45a8ff | 1116 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1117 | * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock |
bogdanm | 0:9b334a45a8ff | 1118 | * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock |
bogdanm | 0:9b334a45a8ff | 1119 | * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock |
bogdanm | 0:9b334a45a8ff | 1120 | * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock |
bogdanm | 0:9b334a45a8ff | 1121 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1122 | */ |
bogdanm | 0:9b334a45a8ff | 1123 | #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1124 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1125 | |
bogdanm | 0:9b334a45a8ff | 1126 | /** @brief Macro to get the UART5 clock source. |
bogdanm | 0:9b334a45a8ff | 1127 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1128 | * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock |
bogdanm | 0:9b334a45a8ff | 1129 | * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock |
bogdanm | 0:9b334a45a8ff | 1130 | * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock |
bogdanm | 0:9b334a45a8ff | 1131 | * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock |
bogdanm | 0:9b334a45a8ff | 1132 | */ |
bogdanm | 0:9b334a45a8ff | 1133 | #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))) |
bogdanm | 0:9b334a45a8ff | 1134 | |
bogdanm | 0:9b334a45a8ff | 1135 | /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). |
bogdanm | 0:9b334a45a8ff | 1136 | * |
bogdanm | 0:9b334a45a8ff | 1137 | * @param __LPUART1_CLKSOURCE__: specifies the LPUART1 clock source. |
bogdanm | 0:9b334a45a8ff | 1138 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1139 | * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1140 | * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1141 | * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1142 | * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1143 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1144 | */ |
bogdanm | 0:9b334a45a8ff | 1145 | #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1146 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1147 | |
bogdanm | 0:9b334a45a8ff | 1148 | /** @brief Macro to get the LPUART1 clock source. |
bogdanm | 0:9b334a45a8ff | 1149 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1150 | * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1151 | * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1152 | * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1153 | * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1154 | */ |
bogdanm | 0:9b334a45a8ff | 1155 | #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) |
bogdanm | 0:9b334a45a8ff | 1156 | |
bogdanm | 0:9b334a45a8ff | 1157 | /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). |
bogdanm | 0:9b334a45a8ff | 1158 | * |
bogdanm | 0:9b334a45a8ff | 1159 | * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source. |
bogdanm | 0:9b334a45a8ff | 1160 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1161 | * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock |
bogdanm | 0:9b334a45a8ff | 1162 | * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock |
bogdanm | 0:9b334a45a8ff | 1163 | * @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock |
bogdanm | 0:9b334a45a8ff | 1164 | * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock |
bogdanm | 0:9b334a45a8ff | 1165 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1166 | */ |
bogdanm | 0:9b334a45a8ff | 1167 | #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1168 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1169 | |
bogdanm | 0:9b334a45a8ff | 1170 | /** @brief Macro to get the LPTIM1 clock source. |
bogdanm | 0:9b334a45a8ff | 1171 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1172 | * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1173 | * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1174 | * @arg RCC_LPTIM1CLKSOURCE_HSI : System Clock selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1175 | * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1176 | */ |
bogdanm | 0:9b334a45a8ff | 1177 | #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) |
bogdanm | 0:9b334a45a8ff | 1178 | |
bogdanm | 0:9b334a45a8ff | 1179 | /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). |
bogdanm | 0:9b334a45a8ff | 1180 | * |
bogdanm | 0:9b334a45a8ff | 1181 | * @param __LPTIM2_CLKSOURCE__: specifies the LPTIM2 clock source. |
bogdanm | 0:9b334a45a8ff | 1182 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1183 | * @arg RCC_LPTIM2CLKSOURCE_PCLK: PCLK selected as LPTIM2 clock |
bogdanm | 0:9b334a45a8ff | 1184 | * @arg RCC_LPTIM2CLKSOURCE_LSI : HSI selected as LPTIM2 clock |
bogdanm | 0:9b334a45a8ff | 1185 | * @arg RCC_LPTIM2CLKSOURCE_HSI : LSI selected as LPTIM2 clock |
bogdanm | 0:9b334a45a8ff | 1186 | * @arg RCC_LPTIM2CLKSOURCE_LSE : LSE selected as LPTIM2 clock |
bogdanm | 0:9b334a45a8ff | 1187 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1188 | */ |
bogdanm | 0:9b334a45a8ff | 1189 | #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1190 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1191 | |
bogdanm | 0:9b334a45a8ff | 1192 | /** @brief Macro to get the LPTIM2 clock source. |
bogdanm | 0:9b334a45a8ff | 1193 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1194 | * @arg RCC_LPTIM2CLKSOURCE_PCLK: PCLK selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1195 | * @arg RCC_LPTIM2CLKSOURCE_LSI : HSI selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1196 | * @arg RCC_LPTIM2CLKSOURCE_HSI : System Clock selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1197 | * @arg RCC_LPTIM2CLKSOURCE_LSE : LSE selected as LPUART1 clock |
bogdanm | 0:9b334a45a8ff | 1198 | */ |
bogdanm | 0:9b334a45a8ff | 1199 | #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))) |
bogdanm | 0:9b334a45a8ff | 1200 | |
bogdanm | 0:9b334a45a8ff | 1201 | /** @brief Macro to configure the SDMMC1 clock. |
bogdanm | 0:9b334a45a8ff | 1202 | * |
bogdanm | 0:9b334a45a8ff | 1203 | * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. |
bogdanm | 0:9b334a45a8ff | 1204 | * |
bogdanm | 0:9b334a45a8ff | 1205 | * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source. |
bogdanm | 0:9b334a45a8ff | 1206 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1207 | * @arg RCC_SDMMC1CLKSOURCE_NONE: No clock selected as SDMMC1 clock |
bogdanm | 0:9b334a45a8ff | 1208 | * @arg RCC_SDMMC1CLKSOURCE_MSI: MSI selected as SDMMC1 clock |
bogdanm | 0:9b334a45a8ff | 1209 | * @arg RCC_SDMMC1CLKSOURCE_PLLSAI1: PLLSAI1 Clock selected as SDMMC1 clock |
bogdanm | 0:9b334a45a8ff | 1210 | * @arg RCC_SDMMC1CLKSOURCE_PLL: PLL Clock selected as SDMMC1 clock |
bogdanm | 0:9b334a45a8ff | 1211 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1212 | */ |
bogdanm | 0:9b334a45a8ff | 1213 | #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1214 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1215 | |
bogdanm | 0:9b334a45a8ff | 1216 | /** @brief Macro to get the SDMMC1 clock. |
bogdanm | 0:9b334a45a8ff | 1217 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1218 | * @arg RCC_SDMMC1CLKSOURCE_NONE: No clock selected as SDMMC1 clock |
bogdanm | 0:9b334a45a8ff | 1219 | * @arg RCC_SDMMC1CLKSOURCE_MSI: MSI selected as SDMMC1 clock |
bogdanm | 0:9b334a45a8ff | 1220 | * @arg RCC_SDMMC1CLKSOURCE_PLLSAI1: PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock |
bogdanm | 0:9b334a45a8ff | 1221 | * @arg RCC_SDMMC1CLKSOURCE_PLL: PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock |
bogdanm | 0:9b334a45a8ff | 1222 | */ |
bogdanm | 0:9b334a45a8ff | 1223 | #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) |
bogdanm | 0:9b334a45a8ff | 1224 | |
bogdanm | 0:9b334a45a8ff | 1225 | /** @brief Macro to configure the RNG clock. |
bogdanm | 0:9b334a45a8ff | 1226 | * |
bogdanm | 0:9b334a45a8ff | 1227 | * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. |
bogdanm | 0:9b334a45a8ff | 1228 | * |
bogdanm | 0:9b334a45a8ff | 1229 | * @param __RNG_CLKSOURCE__: specifies the RNG clock source. |
bogdanm | 0:9b334a45a8ff | 1230 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1231 | * @arg RCC_RNGCLKSOURCE_NONE: No clock selected as RNG clock |
bogdanm | 0:9b334a45a8ff | 1232 | * @arg RCC_RNGCLKSOURCE_MSI: MSI selected as RNG clock |
bogdanm | 0:9b334a45a8ff | 1233 | * @arg RCC_RNGCLKSOURCE_PLLSAI1: PLLSAI1 Clock selected as RNG clock |
bogdanm | 0:9b334a45a8ff | 1234 | * @arg RCC_RNGCLKSOURCE_PLL: PLL Clock selected as RNG clock |
bogdanm | 0:9b334a45a8ff | 1235 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1236 | */ |
bogdanm | 0:9b334a45a8ff | 1237 | #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1238 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1239 | |
bogdanm | 0:9b334a45a8ff | 1240 | /** @brief Macro to get the RNG clock. |
bogdanm | 0:9b334a45a8ff | 1241 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1242 | * @arg RCC_RNGCLKSOURCE_NONE: No clock selected as RNG clock |
bogdanm | 0:9b334a45a8ff | 1243 | * @arg RCC_RNGCLKSOURCE_MSI: MSI selected as RNG clock |
bogdanm | 0:9b334a45a8ff | 1244 | * @arg RCC_RNGCLKSOURCE_PLLSAI1: PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock |
bogdanm | 0:9b334a45a8ff | 1245 | * @arg RCC_RNGCLKSOURCE_PLL: PLL "Q" clock (PLL48M1CLK) selected as RNG clock |
bogdanm | 0:9b334a45a8ff | 1246 | */ |
bogdanm | 0:9b334a45a8ff | 1247 | #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) |
bogdanm | 0:9b334a45a8ff | 1248 | |
bogdanm | 0:9b334a45a8ff | 1249 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 1250 | /** @brief Macro to configure the USB clock (USBCLK). |
bogdanm | 0:9b334a45a8ff | 1251 | * |
bogdanm | 0:9b334a45a8ff | 1252 | * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. |
bogdanm | 0:9b334a45a8ff | 1253 | * |
bogdanm | 0:9b334a45a8ff | 1254 | * @param __USB_CLKSOURCE__: specifies the USB clock source. |
bogdanm | 0:9b334a45a8ff | 1255 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1256 | * @arg RCC_USBCLKSOURCE_NONE: No clock selected as 48MHz clock |
bogdanm | 0:9b334a45a8ff | 1257 | * @arg RCC_USBCLKSOURCE_MSI: MSI selected as USB clock |
bogdanm | 0:9b334a45a8ff | 1258 | * @arg RCC_USBCLKSOURCE_PLLSAI1: PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock |
bogdanm | 0:9b334a45a8ff | 1259 | * @arg RCC_USBCLKSOURCE_PLL: PLL "Q" clock (PLL48M1CLK) selected as USB clock |
bogdanm | 0:9b334a45a8ff | 1260 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1261 | */ |
bogdanm | 0:9b334a45a8ff | 1262 | #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1263 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1264 | |
bogdanm | 0:9b334a45a8ff | 1265 | /** @brief Macro to get the USB clock source. |
bogdanm | 0:9b334a45a8ff | 1266 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1267 | * @arg RCC_USBCLKSOURCE_NONE: No clock selected as 48MHz clock |
bogdanm | 0:9b334a45a8ff | 1268 | * @arg RCC_USBCLKSOURCE_MSI: MSI selected as USB clock |
bogdanm | 0:9b334a45a8ff | 1269 | * @arg RCC_USBCLKSOURCE_PLLSAI1: PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock |
bogdanm | 0:9b334a45a8ff | 1270 | * @arg RCC_USBCLKSOURCE_PLL: PLL "Q" clock (PLL48M1CLK) selected as USB clock |
bogdanm | 0:9b334a45a8ff | 1271 | */ |
bogdanm | 0:9b334a45a8ff | 1272 | #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) |
bogdanm | 0:9b334a45a8ff | 1273 | |
bogdanm | 0:9b334a45a8ff | 1274 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 1275 | |
bogdanm | 0:9b334a45a8ff | 1276 | /** @brief Macro to configure the ADC interface clock. |
bogdanm | 0:9b334a45a8ff | 1277 | * @param __ADC_CLKSOURCE__: specifies the ADC digital interface clock source. |
bogdanm | 0:9b334a45a8ff | 1278 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1279 | * @arg RCC_ADCCLKSOURCE_PLLSAI1: PLLSAI1 Clock selected as ADC clock |
bogdanm | 0:9b334a45a8ff | 1280 | * @arg RCC_ADCCLKSOURCE_PLLSAI2: PLLSAI2 Clock selected as ADC clock |
bogdanm | 0:9b334a45a8ff | 1281 | * @arg RCC_ADCCLKSOURCE_SYSCLK: System Clock selected as ADC clock |
bogdanm | 0:9b334a45a8ff | 1282 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1283 | */ |
bogdanm | 0:9b334a45a8ff | 1284 | #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1285 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1286 | |
bogdanm | 0:9b334a45a8ff | 1287 | /** @brief Macro to get the ADC clock source. |
bogdanm | 0:9b334a45a8ff | 1288 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1289 | * @arg RCC_ADCCLKSOURCE_PLLSAI1: PLLSAI1 Clock selected as ADC clock |
bogdanm | 0:9b334a45a8ff | 1290 | * @arg RCC_ADCCLKSOURCE_PLLSAI2: PLLSAI2 Clock selected as ADC clock |
bogdanm | 0:9b334a45a8ff | 1291 | * @arg RCC_ADCCLKSOURCE_SYSCLK: System Clock selected as ADC clock |
bogdanm | 0:9b334a45a8ff | 1292 | */ |
bogdanm | 0:9b334a45a8ff | 1293 | #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) |
bogdanm | 0:9b334a45a8ff | 1294 | |
bogdanm | 0:9b334a45a8ff | 1295 | /** @brief Macro to configure the SWPMI1 clock. |
bogdanm | 0:9b334a45a8ff | 1296 | * @param __SWPMI1_CLKSOURCE__: specifies the SWPMI1 clock source. |
bogdanm | 0:9b334a45a8ff | 1297 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1298 | * @arg RCC_SWPMI1CLKSOURCE_PCLK: PCLK Clock selected as SWPMI1 clock |
bogdanm | 0:9b334a45a8ff | 1299 | * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock |
bogdanm | 0:9b334a45a8ff | 1300 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1301 | */ |
bogdanm | 0:9b334a45a8ff | 1302 | #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1303 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1304 | |
bogdanm | 0:9b334a45a8ff | 1305 | /** @brief Macro to get the SWPMI1 clock source. |
bogdanm | 0:9b334a45a8ff | 1306 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1307 | * @arg RCC_SWPMI1CLKSOURCE_PCLK: PCLK Clock selected as SWPMI1 clock |
bogdanm | 0:9b334a45a8ff | 1308 | * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock |
bogdanm | 0:9b334a45a8ff | 1309 | */ |
bogdanm | 0:9b334a45a8ff | 1310 | #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))) |
bogdanm | 0:9b334a45a8ff | 1311 | |
bogdanm | 0:9b334a45a8ff | 1312 | /** @brief Macro to configure the DFSDM clock. |
bogdanm | 0:9b334a45a8ff | 1313 | * @param __DFSDM_CLKSOURCE__: specifies the DFSDM clock source. |
bogdanm | 0:9b334a45a8ff | 1314 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1315 | * @arg RCC_DFSDMCLKSOURCE_PCLK: PCLK Clock selected as DFSDM clock |
bogdanm | 0:9b334a45a8ff | 1316 | * @arg RCC_DFSDMCLKSOURCE_HSI: HSI Clock selected as DFSDM clock |
bogdanm | 0:9b334a45a8ff | 1317 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1318 | */ |
bogdanm | 0:9b334a45a8ff | 1319 | #define __HAL_RCC_DFSDM_CONFIG(__DFSDM_CLKSOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1320 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDMSEL, (uint32_t)(__DFSDM_CLKSOURCE__)) |
bogdanm | 0:9b334a45a8ff | 1321 | |
bogdanm | 0:9b334a45a8ff | 1322 | /** @brief Macro to get the DFSDM clock source. |
bogdanm | 0:9b334a45a8ff | 1323 | * @retval The clock source can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 1324 | * @arg RCC_DFSDMCLKSOURCE_PCLK: PCLK Clock selected as DFSDM clock |
bogdanm | 0:9b334a45a8ff | 1325 | * @arg RCC_DFSDMCLKSOURCE_HSI: HSI Clock selected as DFSDM clock |
bogdanm | 0:9b334a45a8ff | 1326 | */ |
bogdanm | 0:9b334a45a8ff | 1327 | #define __HAL_RCC_GET_DFSDM_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDMSEL))) |
bogdanm | 0:9b334a45a8ff | 1328 | |
bogdanm | 0:9b334a45a8ff | 1329 | |
bogdanm | 0:9b334a45a8ff | 1330 | /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management |
bogdanm | 0:9b334a45a8ff | 1331 | * @brief macros to manage the specified RCC Flags and interrupts. |
bogdanm | 0:9b334a45a8ff | 1332 | * @{ |
bogdanm | 0:9b334a45a8ff | 1333 | */ |
bogdanm | 0:9b334a45a8ff | 1334 | |
bogdanm | 0:9b334a45a8ff | 1335 | /** @brief Enable PLLSAI1RDY interrupt. |
bogdanm | 0:9b334a45a8ff | 1336 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1337 | */ |
bogdanm | 0:9b334a45a8ff | 1338 | #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) |
bogdanm | 0:9b334a45a8ff | 1339 | |
bogdanm | 0:9b334a45a8ff | 1340 | /** @brief Disable PLLSAI1RDY interrupt. |
bogdanm | 0:9b334a45a8ff | 1341 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1342 | */ |
bogdanm | 0:9b334a45a8ff | 1343 | #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) |
bogdanm | 0:9b334a45a8ff | 1344 | |
bogdanm | 0:9b334a45a8ff | 1345 | /** @brief Clear the PLLSAI1RDY interrupt pending bit. |
bogdanm | 0:9b334a45a8ff | 1346 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1347 | */ |
bogdanm | 0:9b334a45a8ff | 1348 | #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC) |
bogdanm | 0:9b334a45a8ff | 1349 | |
bogdanm | 0:9b334a45a8ff | 1350 | /** @brief Check whether PLLSAI1RDY interrupt has occurred or not. |
bogdanm | 0:9b334a45a8ff | 1351 | * @retval TRUE or FALSE. |
bogdanm | 0:9b334a45a8ff | 1352 | */ |
bogdanm | 0:9b334a45a8ff | 1353 | #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) |
bogdanm | 0:9b334a45a8ff | 1354 | |
bogdanm | 0:9b334a45a8ff | 1355 | /** @brief Check whether the PLLSAI1RDY flag is set or not. |
bogdanm | 0:9b334a45a8ff | 1356 | * @retval TRUE or FALSE. |
bogdanm | 0:9b334a45a8ff | 1357 | */ |
bogdanm | 0:9b334a45a8ff | 1358 | #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) |
bogdanm | 0:9b334a45a8ff | 1359 | |
bogdanm | 0:9b334a45a8ff | 1360 | /** @brief Enable PLLSAI2RDY interrupt. |
bogdanm | 0:9b334a45a8ff | 1361 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1362 | */ |
bogdanm | 0:9b334a45a8ff | 1363 | #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) |
bogdanm | 0:9b334a45a8ff | 1364 | |
bogdanm | 0:9b334a45a8ff | 1365 | /** @brief Disable PLLSAI2RDY interrupt. |
bogdanm | 0:9b334a45a8ff | 1366 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1367 | */ |
bogdanm | 0:9b334a45a8ff | 1368 | #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) |
bogdanm | 0:9b334a45a8ff | 1369 | |
bogdanm | 0:9b334a45a8ff | 1370 | /** @brief Clear the PLLSAI2RDY interrupt pending bit. |
bogdanm | 0:9b334a45a8ff | 1371 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1372 | */ |
bogdanm | 0:9b334a45a8ff | 1373 | #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC) |
bogdanm | 0:9b334a45a8ff | 1374 | |
bogdanm | 0:9b334a45a8ff | 1375 | /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not. |
bogdanm | 0:9b334a45a8ff | 1376 | * @retval TRUE or FALSE. |
bogdanm | 0:9b334a45a8ff | 1377 | */ |
bogdanm | 0:9b334a45a8ff | 1378 | #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) |
bogdanm | 0:9b334a45a8ff | 1379 | |
bogdanm | 0:9b334a45a8ff | 1380 | /** @brief Check whether the PLLSAI2RDY flag is set or not. |
bogdanm | 0:9b334a45a8ff | 1381 | * @retval TRUE or FALSE. |
bogdanm | 0:9b334a45a8ff | 1382 | */ |
bogdanm | 0:9b334a45a8ff | 1383 | #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)) |
bogdanm | 0:9b334a45a8ff | 1384 | |
bogdanm | 0:9b334a45a8ff | 1385 | /** |
bogdanm | 0:9b334a45a8ff | 1386 | * @} |
bogdanm | 0:9b334a45a8ff | 1387 | */ |
bogdanm | 0:9b334a45a8ff | 1388 | |
bogdanm | 0:9b334a45a8ff | 1389 | /** |
bogdanm | 0:9b334a45a8ff | 1390 | * @} |
bogdanm | 0:9b334a45a8ff | 1391 | */ |
bogdanm | 0:9b334a45a8ff | 1392 | |
bogdanm | 0:9b334a45a8ff | 1393 | /* Exported functions --------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1394 | /** @addtogroup RCCEx_Exported_Functions |
bogdanm | 0:9b334a45a8ff | 1395 | * @{ |
bogdanm | 0:9b334a45a8ff | 1396 | */ |
bogdanm | 0:9b334a45a8ff | 1397 | |
bogdanm | 0:9b334a45a8ff | 1398 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
bogdanm | 0:9b334a45a8ff | 1399 | * @{ |
bogdanm | 0:9b334a45a8ff | 1400 | */ |
bogdanm | 0:9b334a45a8ff | 1401 | |
bogdanm | 0:9b334a45a8ff | 1402 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
bogdanm | 0:9b334a45a8ff | 1403 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
bogdanm | 0:9b334a45a8ff | 1404 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); |
bogdanm | 0:9b334a45a8ff | 1405 | |
bogdanm | 0:9b334a45a8ff | 1406 | /** |
bogdanm | 0:9b334a45a8ff | 1407 | * @} |
bogdanm | 0:9b334a45a8ff | 1408 | */ |
bogdanm | 0:9b334a45a8ff | 1409 | |
bogdanm | 0:9b334a45a8ff | 1410 | /** @addtogroup RCCEx_Exported_Functions_Group2 |
bogdanm | 0:9b334a45a8ff | 1411 | * @{ |
bogdanm | 0:9b334a45a8ff | 1412 | */ |
bogdanm | 0:9b334a45a8ff | 1413 | |
bogdanm | 0:9b334a45a8ff | 1414 | HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); |
bogdanm | 0:9b334a45a8ff | 1415 | HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); |
bogdanm | 0:9b334a45a8ff | 1416 | HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); |
bogdanm | 0:9b334a45a8ff | 1417 | HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void); |
bogdanm | 0:9b334a45a8ff | 1418 | void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); |
bogdanm | 0:9b334a45a8ff | 1419 | void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); |
bogdanm | 0:9b334a45a8ff | 1420 | void HAL_RCCEx_EnableLSECSS(void); |
bogdanm | 0:9b334a45a8ff | 1421 | void HAL_RCCEx_DisableLSECSS(void); |
bogdanm | 0:9b334a45a8ff | 1422 | void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); |
bogdanm | 0:9b334a45a8ff | 1423 | void HAL_RCCEx_DisableLSCO(void); |
bogdanm | 0:9b334a45a8ff | 1424 | void HAL_RCCEx_EnableMSIPLLMode(void); |
bogdanm | 0:9b334a45a8ff | 1425 | void HAL_RCCEx_DisableMSIPLLMode(void); |
bogdanm | 0:9b334a45a8ff | 1426 | |
bogdanm | 0:9b334a45a8ff | 1427 | /** |
bogdanm | 0:9b334a45a8ff | 1428 | * @} |
bogdanm | 0:9b334a45a8ff | 1429 | */ |
bogdanm | 0:9b334a45a8ff | 1430 | |
bogdanm | 0:9b334a45a8ff | 1431 | /** |
bogdanm | 0:9b334a45a8ff | 1432 | * @} |
bogdanm | 0:9b334a45a8ff | 1433 | */ |
bogdanm | 0:9b334a45a8ff | 1434 | |
bogdanm | 0:9b334a45a8ff | 1435 | /* Private macros ------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1436 | /** @addtogroup RCCEx_Private_Macros |
bogdanm | 0:9b334a45a8ff | 1437 | * @{ |
bogdanm | 0:9b334a45a8ff | 1438 | */ |
bogdanm | 0:9b334a45a8ff | 1439 | |
bogdanm | 0:9b334a45a8ff | 1440 | #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ |
bogdanm | 0:9b334a45a8ff | 1441 | ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) |
bogdanm | 0:9b334a45a8ff | 1442 | |
bogdanm | 0:9b334a45a8ff | 1443 | #if defined(STM32L471xx) |
bogdanm | 0:9b334a45a8ff | 1444 | |
bogdanm | 0:9b334a45a8ff | 1445 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
bogdanm | 0:9b334a45a8ff | 1446 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
bogdanm | 0:9b334a45a8ff | 1447 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
bogdanm | 0:9b334a45a8ff | 1448 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
bogdanm | 0:9b334a45a8ff | 1449 | (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
bogdanm | 0:9b334a45a8ff | 1450 | (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
bogdanm | 0:9b334a45a8ff | 1451 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
bogdanm | 0:9b334a45a8ff | 1452 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
bogdanm | 0:9b334a45a8ff | 1453 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
bogdanm | 0:9b334a45a8ff | 1454 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
bogdanm | 0:9b334a45a8ff | 1455 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
bogdanm | 0:9b334a45a8ff | 1456 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
bogdanm | 0:9b334a45a8ff | 1457 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
bogdanm | 0:9b334a45a8ff | 1458 | (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
bogdanm | 0:9b334a45a8ff | 1459 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
bogdanm | 0:9b334a45a8ff | 1460 | (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ |
bogdanm | 0:9b334a45a8ff | 1461 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM) == RCC_PERIPHCLK_DFSDM) || \ |
bogdanm | 0:9b334a45a8ff | 1462 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
bogdanm | 0:9b334a45a8ff | 1463 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
bogdanm | 0:9b334a45a8ff | 1464 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) |
bogdanm | 0:9b334a45a8ff | 1465 | |
bogdanm | 0:9b334a45a8ff | 1466 | #else /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 1467 | |
bogdanm | 0:9b334a45a8ff | 1468 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
bogdanm | 0:9b334a45a8ff | 1469 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
bogdanm | 0:9b334a45a8ff | 1470 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
bogdanm | 0:9b334a45a8ff | 1471 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
bogdanm | 0:9b334a45a8ff | 1472 | (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
bogdanm | 0:9b334a45a8ff | 1473 | (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
bogdanm | 0:9b334a45a8ff | 1474 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
bogdanm | 0:9b334a45a8ff | 1475 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
bogdanm | 0:9b334a45a8ff | 1476 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
bogdanm | 0:9b334a45a8ff | 1477 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
bogdanm | 0:9b334a45a8ff | 1478 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
bogdanm | 0:9b334a45a8ff | 1479 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
bogdanm | 0:9b334a45a8ff | 1480 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
bogdanm | 0:9b334a45a8ff | 1481 | (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
bogdanm | 0:9b334a45a8ff | 1482 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ |
bogdanm | 0:9b334a45a8ff | 1483 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
bogdanm | 0:9b334a45a8ff | 1484 | (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ |
bogdanm | 0:9b334a45a8ff | 1485 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM) == RCC_PERIPHCLK_DFSDM) || \ |
bogdanm | 0:9b334a45a8ff | 1486 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
bogdanm | 0:9b334a45a8ff | 1487 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
bogdanm | 0:9b334a45a8ff | 1488 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) |
bogdanm | 0:9b334a45a8ff | 1489 | |
bogdanm | 0:9b334a45a8ff | 1490 | #endif /* STM32L471xx */ |
bogdanm | 0:9b334a45a8ff | 1491 | |
bogdanm | 0:9b334a45a8ff | 1492 | #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1493 | (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ |
bogdanm | 0:9b334a45a8ff | 1494 | ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
bogdanm | 0:9b334a45a8ff | 1495 | ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ |
bogdanm | 0:9b334a45a8ff | 1496 | ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) |
bogdanm | 0:9b334a45a8ff | 1497 | |
bogdanm | 0:9b334a45a8ff | 1498 | #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1499 | (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ |
bogdanm | 0:9b334a45a8ff | 1500 | ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
bogdanm | 0:9b334a45a8ff | 1501 | ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ |
bogdanm | 0:9b334a45a8ff | 1502 | ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) |
bogdanm | 0:9b334a45a8ff | 1503 | |
bogdanm | 0:9b334a45a8ff | 1504 | #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1505 | (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ |
bogdanm | 0:9b334a45a8ff | 1506 | ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ |
bogdanm | 0:9b334a45a8ff | 1507 | ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ |
bogdanm | 0:9b334a45a8ff | 1508 | ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) |
bogdanm | 0:9b334a45a8ff | 1509 | |
bogdanm | 0:9b334a45a8ff | 1510 | #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1511 | (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ |
bogdanm | 0:9b334a45a8ff | 1512 | ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ |
bogdanm | 0:9b334a45a8ff | 1513 | ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ |
bogdanm | 0:9b334a45a8ff | 1514 | ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) |
bogdanm | 0:9b334a45a8ff | 1515 | |
bogdanm | 0:9b334a45a8ff | 1516 | #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1517 | (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ |
bogdanm | 0:9b334a45a8ff | 1518 | ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ |
bogdanm | 0:9b334a45a8ff | 1519 | ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ |
bogdanm | 0:9b334a45a8ff | 1520 | ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) |
bogdanm | 0:9b334a45a8ff | 1521 | |
bogdanm | 0:9b334a45a8ff | 1522 | #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1523 | (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ |
bogdanm | 0:9b334a45a8ff | 1524 | ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ |
bogdanm | 0:9b334a45a8ff | 1525 | ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ |
bogdanm | 0:9b334a45a8ff | 1526 | ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) |
bogdanm | 0:9b334a45a8ff | 1527 | |
bogdanm | 0:9b334a45a8ff | 1528 | #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1529 | (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ |
bogdanm | 0:9b334a45a8ff | 1530 | ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ |
bogdanm | 0:9b334a45a8ff | 1531 | ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) |
bogdanm | 0:9b334a45a8ff | 1532 | |
bogdanm | 0:9b334a45a8ff | 1533 | #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1534 | (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ |
bogdanm | 0:9b334a45a8ff | 1535 | ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ |
bogdanm | 0:9b334a45a8ff | 1536 | ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) |
bogdanm | 0:9b334a45a8ff | 1537 | |
bogdanm | 0:9b334a45a8ff | 1538 | #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1539 | (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ |
bogdanm | 0:9b334a45a8ff | 1540 | ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ |
bogdanm | 0:9b334a45a8ff | 1541 | ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) |
bogdanm | 0:9b334a45a8ff | 1542 | |
bogdanm | 0:9b334a45a8ff | 1543 | #define IS_RCC_SAI1CLK(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1544 | (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ |
bogdanm | 0:9b334a45a8ff | 1545 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ |
bogdanm | 0:9b334a45a8ff | 1546 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ |
bogdanm | 0:9b334a45a8ff | 1547 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) |
bogdanm | 0:9b334a45a8ff | 1548 | |
bogdanm | 0:9b334a45a8ff | 1549 | #define IS_RCC_SAI2CLK(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1550 | (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ |
bogdanm | 0:9b334a45a8ff | 1551 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ |
bogdanm | 0:9b334a45a8ff | 1552 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ |
bogdanm | 0:9b334a45a8ff | 1553 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) |
bogdanm | 0:9b334a45a8ff | 1554 | |
bogdanm | 0:9b334a45a8ff | 1555 | #define IS_RCC_LPTIM1CLK(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1556 | (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK) || \ |
bogdanm | 0:9b334a45a8ff | 1557 | ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ |
bogdanm | 0:9b334a45a8ff | 1558 | ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ |
bogdanm | 0:9b334a45a8ff | 1559 | ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) |
bogdanm | 0:9b334a45a8ff | 1560 | |
bogdanm | 0:9b334a45a8ff | 1561 | #define IS_RCC_LPTIM2CLK(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1562 | (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK) || \ |
bogdanm | 0:9b334a45a8ff | 1563 | ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ |
bogdanm | 0:9b334a45a8ff | 1564 | ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ |
bogdanm | 0:9b334a45a8ff | 1565 | ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) |
bogdanm | 0:9b334a45a8ff | 1566 | |
bogdanm | 0:9b334a45a8ff | 1567 | #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1568 | (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \ |
bogdanm | 0:9b334a45a8ff | 1569 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ |
bogdanm | 0:9b334a45a8ff | 1570 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ |
bogdanm | 0:9b334a45a8ff | 1571 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) |
bogdanm | 0:9b334a45a8ff | 1572 | |
bogdanm | 0:9b334a45a8ff | 1573 | #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1574 | (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ |
bogdanm | 0:9b334a45a8ff | 1575 | ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ |
bogdanm | 0:9b334a45a8ff | 1576 | ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ |
bogdanm | 0:9b334a45a8ff | 1577 | ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) |
bogdanm | 0:9b334a45a8ff | 1578 | |
bogdanm | 0:9b334a45a8ff | 1579 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
bogdanm | 0:9b334a45a8ff | 1580 | #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1581 | (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \ |
bogdanm | 0:9b334a45a8ff | 1582 | ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ |
bogdanm | 0:9b334a45a8ff | 1583 | ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ |
bogdanm | 0:9b334a45a8ff | 1584 | ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) |
bogdanm | 0:9b334a45a8ff | 1585 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
bogdanm | 0:9b334a45a8ff | 1586 | |
bogdanm | 0:9b334a45a8ff | 1587 | #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1588 | (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ |
bogdanm | 0:9b334a45a8ff | 1589 | ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ |
bogdanm | 0:9b334a45a8ff | 1590 | ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \ |
bogdanm | 0:9b334a45a8ff | 1591 | ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) |
bogdanm | 0:9b334a45a8ff | 1592 | |
bogdanm | 0:9b334a45a8ff | 1593 | #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1594 | (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK) || \ |
bogdanm | 0:9b334a45a8ff | 1595 | ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI)) |
bogdanm | 0:9b334a45a8ff | 1596 | |
bogdanm | 0:9b334a45a8ff | 1597 | #define IS_RCC_DFSDMCLKSOURCE(__SOURCE__) \ |
bogdanm | 0:9b334a45a8ff | 1598 | (((__SOURCE__) == RCC_DFSDMCLKSOURCE_PCLK) || \ |
bogdanm | 0:9b334a45a8ff | 1599 | ((__SOURCE__) == RCC_DFSDMCLKSOURCE_SYSCLK)) |
bogdanm | 0:9b334a45a8ff | 1600 | |
bogdanm | 0:9b334a45a8ff | 1601 | |
bogdanm | 0:9b334a45a8ff | 1602 | #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86)) |
bogdanm | 0:9b334a45a8ff | 1603 | |
bogdanm | 0:9b334a45a8ff | 1604 | #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7) || ((__VALUE__) == 17)) |
bogdanm | 0:9b334a45a8ff | 1605 | |
bogdanm | 0:9b334a45a8ff | 1606 | #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2 ) || ((__VALUE__) == 4) || \ |
bogdanm | 0:9b334a45a8ff | 1607 | ((__VALUE__) == 6) || ((__VALUE__) == 8)) |
bogdanm | 0:9b334a45a8ff | 1608 | |
bogdanm | 0:9b334a45a8ff | 1609 | #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2 ) || ((__VALUE__) == 4) || \ |
bogdanm | 0:9b334a45a8ff | 1610 | ((__VALUE__) == 6) || ((__VALUE__) == 8)) |
bogdanm | 0:9b334a45a8ff | 1611 | |
bogdanm | 0:9b334a45a8ff | 1612 | #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86)) |
bogdanm | 0:9b334a45a8ff | 1613 | |
bogdanm | 0:9b334a45a8ff | 1614 | #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7) || ((__VALUE__) == 17)) |
bogdanm | 0:9b334a45a8ff | 1615 | |
bogdanm | 0:9b334a45a8ff | 1616 | #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2 ) || ((__VALUE__) == 4) || \ |
bogdanm | 0:9b334a45a8ff | 1617 | ((__VALUE__) == 6) || ((__VALUE__) == 8)) |
bogdanm | 0:9b334a45a8ff | 1618 | |
bogdanm | 0:9b334a45a8ff | 1619 | /** |
bogdanm | 0:9b334a45a8ff | 1620 | * @} |
bogdanm | 0:9b334a45a8ff | 1621 | */ |
bogdanm | 0:9b334a45a8ff | 1622 | |
bogdanm | 0:9b334a45a8ff | 1623 | /** |
bogdanm | 0:9b334a45a8ff | 1624 | * @} |
bogdanm | 0:9b334a45a8ff | 1625 | */ |
bogdanm | 0:9b334a45a8ff | 1626 | |
bogdanm | 0:9b334a45a8ff | 1627 | /** |
bogdanm | 0:9b334a45a8ff | 1628 | * @} |
bogdanm | 0:9b334a45a8ff | 1629 | */ |
bogdanm | 0:9b334a45a8ff | 1630 | |
bogdanm | 0:9b334a45a8ff | 1631 | #ifdef __cplusplus |
bogdanm | 0:9b334a45a8ff | 1632 | } |
bogdanm | 0:9b334a45a8ff | 1633 | #endif |
bogdanm | 0:9b334a45a8ff | 1634 | |
bogdanm | 0:9b334a45a8ff | 1635 | #endif /* __STM32L4xx_HAL_RCC_EX_H */ |
bogdanm | 0:9b334a45a8ff | 1636 | |
bogdanm | 0:9b334a45a8ff | 1637 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |