en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_pwr_ex.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l4xx_hal_pwr_ex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief Extended PWR HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Power Controller (PWR) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Extended Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 ******************************************************************************
bogdanm 0:9b334a45a8ff 14 * @attention
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 17 *
bogdanm 0:9b334a45a8ff 18 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 19 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 20 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 21 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 23 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 24 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 26 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 27 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 28 *
bogdanm 0:9b334a45a8ff 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 39 *
bogdanm 0:9b334a45a8ff 40 ******************************************************************************
bogdanm 0:9b334a45a8ff 41 */
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 44 #include "stm32l4xx_hal.h"
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /** @addtogroup STM32L4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 47 * @{
bogdanm 0:9b334a45a8ff 48 */
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 /** @defgroup PWREx PWREx
bogdanm 0:9b334a45a8ff 51 * @brief PWR Extended HAL module driver
bogdanm 0:9b334a45a8ff 52 * @{
bogdanm 0:9b334a45a8ff 53 */
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 #ifdef HAL_PWR_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
bogdanm 0:9b334a45a8ff 61 * @{
bogdanm 0:9b334a45a8ff 62 */
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
bogdanm 0:9b334a45a8ff 65 * @{
bogdanm 0:9b334a45a8ff 66 */
bogdanm 0:9b334a45a8ff 67 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */
bogdanm 0:9b334a45a8ff 68 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */
bogdanm 0:9b334a45a8ff 69 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */
bogdanm 0:9b334a45a8ff 70 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */
bogdanm 0:9b334a45a8ff 71 /**
bogdanm 0:9b334a45a8ff 72 * @}
bogdanm 0:9b334a45a8ff 73 */
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
bogdanm 0:9b334a45a8ff 76 * @{
bogdanm 0:9b334a45a8ff 77 */
bogdanm 0:9b334a45a8ff 78 #define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */
bogdanm 0:9b334a45a8ff 79 /**
bogdanm 0:9b334a45a8ff 80 * @}
bogdanm 0:9b334a45a8ff 81 */
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /**
bogdanm 0:9b334a45a8ff 86 * @}
bogdanm 0:9b334a45a8ff 87 */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 92 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 93 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 94 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
bogdanm 0:9b334a45a8ff 97 * @{
bogdanm 0:9b334a45a8ff 98 */
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 101 * @brief Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 102 *
bogdanm 0:9b334a45a8ff 103 @verbatim
bogdanm 0:9b334a45a8ff 104 ===============================================================================
bogdanm 0:9b334a45a8ff 105 ##### Extended Peripheral Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 106 ===============================================================================
bogdanm 0:9b334a45a8ff 107 [..]
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 @endverbatim
bogdanm 0:9b334a45a8ff 110 * @{
bogdanm 0:9b334a45a8ff 111 */
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /**
bogdanm 0:9b334a45a8ff 115 * @brief Return Voltage Scaling Range.
bogdanm 0:9b334a45a8ff 116 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118 uint32_t HAL_PWREx_GetVoltageRange(void)
bogdanm 0:9b334a45a8ff 119 {
bogdanm 0:9b334a45a8ff 120 return (PWR->CR1 & PWR_CR1_VOS);
bogdanm 0:9b334a45a8ff 121 }
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 /**
bogdanm 0:9b334a45a8ff 126 * @brief Configure the main internal regulator output voltage.
bogdanm 0:9b334a45a8ff 127 * @param VoltageScaling: specifies the regulator output voltage to achieve
bogdanm 0:9b334a45a8ff 128 * a tradeoff between performance and power consumption.
bogdanm 0:9b334a45a8ff 129 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 130 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
bogdanm 0:9b334a45a8ff 131 * typical output voltage at 1.2 V,
bogdanm 0:9b334a45a8ff 132 * system frequency up to 80 MHz.
bogdanm 0:9b334a45a8ff 133 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
bogdanm 0:9b334a45a8ff 134 * typical output voltage at 1.0 V,
bogdanm 0:9b334a45a8ff 135 * system frequency up to 26 MHz.
bogdanm 0:9b334a45a8ff 136 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
bogdanm 0:9b334a45a8ff 137 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
bogdanm 0:9b334a45a8ff 138 * When moving from Range 2 to Range 1, the system frequency can be increased to
bogdanm 0:9b334a45a8ff 139 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
bogdanm 0:9b334a45a8ff 140 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
bogdanm 0:9b334a45a8ff 141 * cleared before returning the status. If the flag is not cleared within
bogdanm 0:9b334a45a8ff 142 * 50 microseconds, HAL_TIMEOUT status is reported.
bogdanm 0:9b334a45a8ff 143 * @retval HAL Status
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
bogdanm 0:9b334a45a8ff 146 {
bogdanm 0:9b334a45a8ff 147 uint32_t wait_loop_index = 0;
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /* If Set Range 1 */
bogdanm 0:9b334a45a8ff 152 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
bogdanm 0:9b334a45a8ff 153 {
bogdanm 0:9b334a45a8ff 154 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
bogdanm 0:9b334a45a8ff 155 {
bogdanm 0:9b334a45a8ff 156 /* Set Range 1 */
bogdanm 0:9b334a45a8ff 157 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 /* Wait until VOSF is cleared */
bogdanm 0:9b334a45a8ff 160 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
bogdanm 0:9b334a45a8ff 161 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)))
bogdanm 0:9b334a45a8ff 162 {
bogdanm 0:9b334a45a8ff 163 wait_loop_index--;
bogdanm 0:9b334a45a8ff 164 }
bogdanm 0:9b334a45a8ff 165 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
bogdanm 0:9b334a45a8ff 166 {
bogdanm 0:9b334a45a8ff 167 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 168 }
bogdanm 0:9b334a45a8ff 169 }
bogdanm 0:9b334a45a8ff 170 }
bogdanm 0:9b334a45a8ff 171 else
bogdanm 0:9b334a45a8ff 172 {
bogdanm 0:9b334a45a8ff 173 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
bogdanm 0:9b334a45a8ff 174 {
bogdanm 0:9b334a45a8ff 175 /* Set Range 2 */
bogdanm 0:9b334a45a8ff 176 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
bogdanm 0:9b334a45a8ff 177 /* No need to wait for VOSF to be cleared for this transition */
bogdanm 0:9b334a45a8ff 178 }
bogdanm 0:9b334a45a8ff 179 }
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 return HAL_OK;
bogdanm 0:9b334a45a8ff 182 }
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /**
bogdanm 0:9b334a45a8ff 186 * @brief Enable battery charging.
bogdanm 0:9b334a45a8ff 187 * When VDD is present, charge the external battery on VBAT thru an internal resistor.
bogdanm 0:9b334a45a8ff 188 * @param ResistorSelection: specifies the resistor impedance.
bogdanm 0:9b334a45a8ff 189 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 190 * @arg PWR_BATTERY_CHARGING_RESISTOR_5: 5 kOhms resistor
bogdanm 0:9b334a45a8ff 191 * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 kOhms resistor
bogdanm 0:9b334a45a8ff 192 * @retval None
bogdanm 0:9b334a45a8ff 193 */
bogdanm 0:9b334a45a8ff 194 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
bogdanm 0:9b334a45a8ff 195 {
bogdanm 0:9b334a45a8ff 196 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 /* Specify resistor selection */
bogdanm 0:9b334a45a8ff 199 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 /* Enable battery charging */
bogdanm 0:9b334a45a8ff 202 SET_BIT(PWR->CR4, PWR_CR4_VBE);
bogdanm 0:9b334a45a8ff 203 }
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /**
bogdanm 0:9b334a45a8ff 207 * @brief Disable battery charging.
bogdanm 0:9b334a45a8ff 208 * @retval None
bogdanm 0:9b334a45a8ff 209 */
bogdanm 0:9b334a45a8ff 210 void HAL_PWREx_DisableBatteryCharging(void)
bogdanm 0:9b334a45a8ff 211 {
bogdanm 0:9b334a45a8ff 212 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
bogdanm 0:9b334a45a8ff 213 }
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
bogdanm 0:9b334a45a8ff 217 /**
bogdanm 0:9b334a45a8ff 218 * @brief Enable VDDUSB supply.
bogdanm 0:9b334a45a8ff 219 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
bogdanm 0:9b334a45a8ff 220 * @retval None
bogdanm 0:9b334a45a8ff 221 */
bogdanm 0:9b334a45a8ff 222 void HAL_PWREx_EnableVddUSB(void)
bogdanm 0:9b334a45a8ff 223 {
bogdanm 0:9b334a45a8ff 224 SET_BIT(PWR->CR2, PWR_CR2_USV);
bogdanm 0:9b334a45a8ff 225 }
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /**
bogdanm 0:9b334a45a8ff 229 * @brief Disable VDDUSB supply.
bogdanm 0:9b334a45a8ff 230 * @retval None
bogdanm 0:9b334a45a8ff 231 */
bogdanm 0:9b334a45a8ff 232 void HAL_PWREx_DisableVddUSB(void)
bogdanm 0:9b334a45a8ff 233 {
bogdanm 0:9b334a45a8ff 234 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
bogdanm 0:9b334a45a8ff 235 }
bogdanm 0:9b334a45a8ff 236 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 /**
bogdanm 0:9b334a45a8ff 239 * @brief Enable VDDIO2 supply.
bogdanm 0:9b334a45a8ff 240 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
bogdanm 0:9b334a45a8ff 241 * @retval None
bogdanm 0:9b334a45a8ff 242 */
bogdanm 0:9b334a45a8ff 243 void HAL_PWREx_EnableVddIO2(void)
bogdanm 0:9b334a45a8ff 244 {
bogdanm 0:9b334a45a8ff 245 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
bogdanm 0:9b334a45a8ff 246 }
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /**
bogdanm 0:9b334a45a8ff 250 * @brief Disable VDDIO2 supply.
bogdanm 0:9b334a45a8ff 251 * @retval None
bogdanm 0:9b334a45a8ff 252 */
bogdanm 0:9b334a45a8ff 253 void HAL_PWREx_DisableVddIO2(void)
bogdanm 0:9b334a45a8ff 254 {
bogdanm 0:9b334a45a8ff 255 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
bogdanm 0:9b334a45a8ff 256 }
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 /**
bogdanm 0:9b334a45a8ff 260 * @brief Enable Internal Wake-up Line.
bogdanm 0:9b334a45a8ff 261 * @retval None
bogdanm 0:9b334a45a8ff 262 */
bogdanm 0:9b334a45a8ff 263 void HAL_PWREx_EnableInternalWakeUpLine(void)
bogdanm 0:9b334a45a8ff 264 {
bogdanm 0:9b334a45a8ff 265 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
bogdanm 0:9b334a45a8ff 266 }
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268
bogdanm 0:9b334a45a8ff 269 /**
bogdanm 0:9b334a45a8ff 270 * @brief Disable Internal Wake-up Line.
bogdanm 0:9b334a45a8ff 271 * @retval None
bogdanm 0:9b334a45a8ff 272 */
bogdanm 0:9b334a45a8ff 273 void HAL_PWREx_DisableInternalWakeUpLine(void)
bogdanm 0:9b334a45a8ff 274 {
bogdanm 0:9b334a45a8ff 275 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
bogdanm 0:9b334a45a8ff 276 }
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /**
bogdanm 0:9b334a45a8ff 281 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
bogdanm 0:9b334a45a8ff 282 * @note Set the relevant PUy bit of PWR_PUCRx register to configure the I/O in
bogdanm 0:9b334a45a8ff 283 * pull-up state in Standby and Shutdown modes.
bogdanm 0:9b334a45a8ff 284 * @note This state is effective in Standby and Shutdown modes only if APC bit
bogdanm 0:9b334a45a8ff 285 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
bogdanm 0:9b334a45a8ff 286 * @note The configuration is lost when exiting the Shutdown mode due to the
bogdanm 0:9b334a45a8ff 287 * power-on reset, maintained when exiting the Standby mode.
bogdanm 0:9b334a45a8ff 288 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
bogdanm 0:9b334a45a8ff 289 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
bogdanm 0:9b334a45a8ff 290 * @note The API returns HAL_ERROR when PUy bit is reserved.
bogdanm 0:9b334a45a8ff 291 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
bogdanm 0:9b334a45a8ff 292 * to select the GPIO peripheral.
bogdanm 0:9b334a45a8ff 293 * @param GPIONumber: Specify the I/O pins numbers.
bogdanm 0:9b334a45a8ff 294 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 295 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
bogdanm 0:9b334a45a8ff 296 * I/O pins are available) or the logical OR of several of them to set
bogdanm 0:9b334a45a8ff 297 * several bits for a given port in a single API call.
bogdanm 0:9b334a45a8ff 298 * @retval HAL Status
bogdanm 0:9b334a45a8ff 299 */
bogdanm 0:9b334a45a8ff 300 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
bogdanm 0:9b334a45a8ff 301 {
bogdanm 0:9b334a45a8ff 302 uint32_t position = 0x00;
bogdanm 0:9b334a45a8ff 303 uint32_t gpiocurrent = 0x00;
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 assert_param(IS_PWR_GPIO(GPIO));
bogdanm 0:9b334a45a8ff 306 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 while ((GPIONumber >> position) != RESET)
bogdanm 0:9b334a45a8ff 309 {
bogdanm 0:9b334a45a8ff 310 /* Get current gpio position */
bogdanm 0:9b334a45a8ff 311 gpiocurrent = (GPIONumber) & (1U << position);
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 if (gpiocurrent)
bogdanm 0:9b334a45a8ff 314 {
bogdanm 0:9b334a45a8ff 315 switch (GPIO)
bogdanm 0:9b334a45a8ff 316 {
bogdanm 0:9b334a45a8ff 317 case PWR_GPIO_A:
bogdanm 0:9b334a45a8ff 318 if (gpiocurrent == PWR_GPIO_BIT_14)
bogdanm 0:9b334a45a8ff 319 {
bogdanm 0:9b334a45a8ff 320 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 321 }
bogdanm 0:9b334a45a8ff 322 else
bogdanm 0:9b334a45a8ff 323 {
bogdanm 0:9b334a45a8ff 324 SET_BIT(PWR->PUCRA, gpiocurrent);
bogdanm 0:9b334a45a8ff 325 if ((gpiocurrent != PWR_GPIO_BIT_13) && (gpiocurrent != PWR_GPIO_BIT_14))
bogdanm 0:9b334a45a8ff 326 {
bogdanm 0:9b334a45a8ff 327 CLEAR_BIT(PWR->PDCRA, gpiocurrent);
bogdanm 0:9b334a45a8ff 328 }
bogdanm 0:9b334a45a8ff 329 }
bogdanm 0:9b334a45a8ff 330 break;
bogdanm 0:9b334a45a8ff 331 case PWR_GPIO_B:
bogdanm 0:9b334a45a8ff 332 SET_BIT(PWR->PUCRB, gpiocurrent);
bogdanm 0:9b334a45a8ff 333 if (gpiocurrent != PWR_GPIO_BIT_4)
bogdanm 0:9b334a45a8ff 334 {
bogdanm 0:9b334a45a8ff 335 CLEAR_BIT(PWR->PDCRB, gpiocurrent);
bogdanm 0:9b334a45a8ff 336 }
bogdanm 0:9b334a45a8ff 337 break;
bogdanm 0:9b334a45a8ff 338 case PWR_GPIO_C:
bogdanm 0:9b334a45a8ff 339 SET_BIT(PWR->PUCRC, gpiocurrent);
bogdanm 0:9b334a45a8ff 340 CLEAR_BIT(PWR->PDCRC, gpiocurrent);
bogdanm 0:9b334a45a8ff 341 break;
bogdanm 0:9b334a45a8ff 342 case PWR_GPIO_D:
bogdanm 0:9b334a45a8ff 343 SET_BIT(PWR->PUCRD, gpiocurrent);
bogdanm 0:9b334a45a8ff 344 CLEAR_BIT(PWR->PDCRD, gpiocurrent);
bogdanm 0:9b334a45a8ff 345 break;
bogdanm 0:9b334a45a8ff 346 case PWR_GPIO_E:
bogdanm 0:9b334a45a8ff 347 SET_BIT(PWR->PUCRE, gpiocurrent);
bogdanm 0:9b334a45a8ff 348 CLEAR_BIT(PWR->PDCRE, gpiocurrent);
bogdanm 0:9b334a45a8ff 349 break;
bogdanm 0:9b334a45a8ff 350 case PWR_GPIO_F:
bogdanm 0:9b334a45a8ff 351 SET_BIT(PWR->PUCRF, gpiocurrent);
bogdanm 0:9b334a45a8ff 352 CLEAR_BIT(PWR->PDCRF, gpiocurrent);
bogdanm 0:9b334a45a8ff 353 break;
bogdanm 0:9b334a45a8ff 354 case PWR_GPIO_G:
bogdanm 0:9b334a45a8ff 355 SET_BIT(PWR->PUCRG, gpiocurrent);
bogdanm 0:9b334a45a8ff 356 CLEAR_BIT(PWR->PDCRG, gpiocurrent);
bogdanm 0:9b334a45a8ff 357 break;
bogdanm 0:9b334a45a8ff 358 case PWR_GPIO_H:
bogdanm 0:9b334a45a8ff 359 if ((gpiocurrent != PWR_GPIO_BIT_0) && (gpiocurrent != PWR_GPIO_BIT_1))
bogdanm 0:9b334a45a8ff 360 {
bogdanm 0:9b334a45a8ff 361 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 362 }
bogdanm 0:9b334a45a8ff 363 else
bogdanm 0:9b334a45a8ff 364 {
bogdanm 0:9b334a45a8ff 365 SET_BIT(PWR->PUCRH, gpiocurrent);
bogdanm 0:9b334a45a8ff 366 CLEAR_BIT(PWR->PDCRH, gpiocurrent);
bogdanm 0:9b334a45a8ff 367 }
bogdanm 0:9b334a45a8ff 368 break;
bogdanm 0:9b334a45a8ff 369 default:
bogdanm 0:9b334a45a8ff 370 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 371 }
bogdanm 0:9b334a45a8ff 372 } /* if (gpiocurrent) */
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 position++;
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 } /* while (GPIONumber >> position) */
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378 return HAL_OK;
bogdanm 0:9b334a45a8ff 379 }
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /**
bogdanm 0:9b334a45a8ff 383 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
bogdanm 0:9b334a45a8ff 384 * @note Reset the relevant PUy bit of PWR_PUCRx register used to configure the I/O
bogdanm 0:9b334a45a8ff 385 * in pull-up state in Standby and Shutdown modes.
bogdanm 0:9b334a45a8ff 386 * @note The API returns HAL_ERROR when PUy bit is reserved.
bogdanm 0:9b334a45a8ff 387 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
bogdanm 0:9b334a45a8ff 388 * to select the GPIO peripheral.
bogdanm 0:9b334a45a8ff 389 * @param GPIONumber: Specify the I/O pins numbers.
bogdanm 0:9b334a45a8ff 390 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 391 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
bogdanm 0:9b334a45a8ff 392 * I/O pins are available) or the logical OR of several of them to reset
bogdanm 0:9b334a45a8ff 393 * several bits for a given port in a single API call.
bogdanm 0:9b334a45a8ff 394 * @retval HAL Status
bogdanm 0:9b334a45a8ff 395 */
bogdanm 0:9b334a45a8ff 396 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
bogdanm 0:9b334a45a8ff 397 {
bogdanm 0:9b334a45a8ff 398 uint32_t position = 0x00;
bogdanm 0:9b334a45a8ff 399 uint32_t gpiocurrent = 0x00;
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 assert_param(IS_PWR_GPIO(GPIO));
bogdanm 0:9b334a45a8ff 402 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 while ((GPIONumber >> position) != RESET)
bogdanm 0:9b334a45a8ff 405 {
bogdanm 0:9b334a45a8ff 406 /* Get current gpio position */
bogdanm 0:9b334a45a8ff 407 gpiocurrent = (GPIONumber) & (1U << position);
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 if (gpiocurrent)
bogdanm 0:9b334a45a8ff 410 {
bogdanm 0:9b334a45a8ff 411 switch (GPIO)
bogdanm 0:9b334a45a8ff 412 {
bogdanm 0:9b334a45a8ff 413 case PWR_GPIO_A:
bogdanm 0:9b334a45a8ff 414 if (GPIONumber == PWR_GPIO_BIT_14)
bogdanm 0:9b334a45a8ff 415 {
bogdanm 0:9b334a45a8ff 416 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 417 }
bogdanm 0:9b334a45a8ff 418 else
bogdanm 0:9b334a45a8ff 419 {
bogdanm 0:9b334a45a8ff 420 CLEAR_BIT(PWR->PUCRA, GPIONumber);
bogdanm 0:9b334a45a8ff 421 }
bogdanm 0:9b334a45a8ff 422 break;
bogdanm 0:9b334a45a8ff 423 case PWR_GPIO_B:
bogdanm 0:9b334a45a8ff 424 CLEAR_BIT(PWR->PUCRB, GPIONumber);
bogdanm 0:9b334a45a8ff 425 break;
bogdanm 0:9b334a45a8ff 426 case PWR_GPIO_C:
bogdanm 0:9b334a45a8ff 427 CLEAR_BIT(PWR->PUCRC, GPIONumber);
bogdanm 0:9b334a45a8ff 428 break;
bogdanm 0:9b334a45a8ff 429 case PWR_GPIO_D:
bogdanm 0:9b334a45a8ff 430 CLEAR_BIT(PWR->PUCRD, GPIONumber);
bogdanm 0:9b334a45a8ff 431 break;
bogdanm 0:9b334a45a8ff 432 case PWR_GPIO_E:
bogdanm 0:9b334a45a8ff 433 CLEAR_BIT(PWR->PUCRE, GPIONumber);
bogdanm 0:9b334a45a8ff 434 break;
bogdanm 0:9b334a45a8ff 435 case PWR_GPIO_F:
bogdanm 0:9b334a45a8ff 436 CLEAR_BIT(PWR->PUCRF, GPIONumber);
bogdanm 0:9b334a45a8ff 437 break;
bogdanm 0:9b334a45a8ff 438 case PWR_GPIO_G:
bogdanm 0:9b334a45a8ff 439 CLEAR_BIT(PWR->PUCRG, GPIONumber);
bogdanm 0:9b334a45a8ff 440 break;
bogdanm 0:9b334a45a8ff 441 case PWR_GPIO_H:
bogdanm 0:9b334a45a8ff 442 if ((gpiocurrent != PWR_GPIO_BIT_0) && (gpiocurrent != PWR_GPIO_BIT_1))
bogdanm 0:9b334a45a8ff 443 {
bogdanm 0:9b334a45a8ff 444 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 445 }
bogdanm 0:9b334a45a8ff 446 else
bogdanm 0:9b334a45a8ff 447 {
bogdanm 0:9b334a45a8ff 448 CLEAR_BIT(PWR->PUCRH, GPIONumber);
bogdanm 0:9b334a45a8ff 449 }
bogdanm 0:9b334a45a8ff 450 break;
bogdanm 0:9b334a45a8ff 451 default:
bogdanm 0:9b334a45a8ff 452 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 453 }
bogdanm 0:9b334a45a8ff 454 } /* if (gpiocurrent) */
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 position++;
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 } /* while (GPIONumber >> position) */
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 return HAL_OK;
bogdanm 0:9b334a45a8ff 461 }
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 /**
bogdanm 0:9b334a45a8ff 466 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
bogdanm 0:9b334a45a8ff 467 * @note Set the relevant PDy bit of PWR_PDCRx register to configure the I/O in
bogdanm 0:9b334a45a8ff 468 * pull-down state in Standby and Shutdown modes.
bogdanm 0:9b334a45a8ff 469 * @note This state is effective in Standby and Shutdown modes only if APC bit
bogdanm 0:9b334a45a8ff 470 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
bogdanm 0:9b334a45a8ff 471 * @note The configuration is lost when exiting the Shutdown mode due to the
bogdanm 0:9b334a45a8ff 472 * power-on reset, maintained when exiting the Standby mode.
bogdanm 0:9b334a45a8ff 473 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
bogdanm 0:9b334a45a8ff 474 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
bogdanm 0:9b334a45a8ff 475 * @note The API returns HAL_ERROR when PDy bit is reserved.
bogdanm 0:9b334a45a8ff 476 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
bogdanm 0:9b334a45a8ff 477 * to select the GPIO peripheral.
bogdanm 0:9b334a45a8ff 478 * @param GPIONumber: Specify the I/O pins numbers.
bogdanm 0:9b334a45a8ff 479 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 480 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
bogdanm 0:9b334a45a8ff 481 * I/O pins are available) or the logical OR of several of them to set
bogdanm 0:9b334a45a8ff 482 * several bits for a given port in a single API call.
bogdanm 0:9b334a45a8ff 483 * @retval HAL Status
bogdanm 0:9b334a45a8ff 484 */
bogdanm 0:9b334a45a8ff 485 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
bogdanm 0:9b334a45a8ff 486 {
bogdanm 0:9b334a45a8ff 487 uint32_t position = 0x00;
bogdanm 0:9b334a45a8ff 488 uint32_t gpiocurrent = 0x00;
bogdanm 0:9b334a45a8ff 489
bogdanm 0:9b334a45a8ff 490 assert_param(IS_PWR_GPIO(GPIO));
bogdanm 0:9b334a45a8ff 491 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 while ((GPIONumber >> position) != RESET)
bogdanm 0:9b334a45a8ff 494 {
bogdanm 0:9b334a45a8ff 495 /* Get current gpio position */
bogdanm 0:9b334a45a8ff 496 gpiocurrent = (GPIONumber) & (1U << position);
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 if (gpiocurrent)
bogdanm 0:9b334a45a8ff 499 {
bogdanm 0:9b334a45a8ff 500 switch (GPIO)
bogdanm 0:9b334a45a8ff 501 {
bogdanm 0:9b334a45a8ff 502 case PWR_GPIO_A:
bogdanm 0:9b334a45a8ff 503 if ((GPIONumber == PWR_GPIO_BIT_13) || (GPIONumber == PWR_GPIO_BIT_15))
bogdanm 0:9b334a45a8ff 504 {
bogdanm 0:9b334a45a8ff 505 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 506 }
bogdanm 0:9b334a45a8ff 507 else
bogdanm 0:9b334a45a8ff 508 {
bogdanm 0:9b334a45a8ff 509 SET_BIT(PWR->PDCRA, GPIONumber);
bogdanm 0:9b334a45a8ff 510 if (GPIONumber != PWR_GPIO_BIT_14)
bogdanm 0:9b334a45a8ff 511 {
bogdanm 0:9b334a45a8ff 512 CLEAR_BIT(PWR->PUCRA, GPIONumber);
bogdanm 0:9b334a45a8ff 513 }
bogdanm 0:9b334a45a8ff 514 }
bogdanm 0:9b334a45a8ff 515 break;
bogdanm 0:9b334a45a8ff 516 case PWR_GPIO_B:
bogdanm 0:9b334a45a8ff 517 if (GPIONumber == PWR_GPIO_BIT_4)
bogdanm 0:9b334a45a8ff 518 {
bogdanm 0:9b334a45a8ff 519 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 520 }
bogdanm 0:9b334a45a8ff 521 else
bogdanm 0:9b334a45a8ff 522 {
bogdanm 0:9b334a45a8ff 523 SET_BIT(PWR->PDCRB, GPIONumber);
bogdanm 0:9b334a45a8ff 524 CLEAR_BIT(PWR->PUCRB, GPIONumber);
bogdanm 0:9b334a45a8ff 525 }
bogdanm 0:9b334a45a8ff 526 break;
bogdanm 0:9b334a45a8ff 527 case PWR_GPIO_C:
bogdanm 0:9b334a45a8ff 528 SET_BIT(PWR->PDCRC, GPIONumber);
bogdanm 0:9b334a45a8ff 529 CLEAR_BIT(PWR->PUCRC, GPIONumber);
bogdanm 0:9b334a45a8ff 530 break;
bogdanm 0:9b334a45a8ff 531 case PWR_GPIO_D:
bogdanm 0:9b334a45a8ff 532 SET_BIT(PWR->PDCRD, GPIONumber);
bogdanm 0:9b334a45a8ff 533 CLEAR_BIT(PWR->PUCRD, GPIONumber);
bogdanm 0:9b334a45a8ff 534 break;
bogdanm 0:9b334a45a8ff 535 case PWR_GPIO_E:
bogdanm 0:9b334a45a8ff 536 SET_BIT(PWR->PDCRE, GPIONumber);
bogdanm 0:9b334a45a8ff 537 CLEAR_BIT(PWR->PUCRE, GPIONumber);
bogdanm 0:9b334a45a8ff 538 break;
bogdanm 0:9b334a45a8ff 539 case PWR_GPIO_F:
bogdanm 0:9b334a45a8ff 540 SET_BIT(PWR->PDCRF, GPIONumber);
bogdanm 0:9b334a45a8ff 541 CLEAR_BIT(PWR->PUCRF, GPIONumber);
bogdanm 0:9b334a45a8ff 542 break;
bogdanm 0:9b334a45a8ff 543 case PWR_GPIO_G:
bogdanm 0:9b334a45a8ff 544 SET_BIT(PWR->PDCRG, GPIONumber);
bogdanm 0:9b334a45a8ff 545 CLEAR_BIT(PWR->PUCRG, GPIONumber);
bogdanm 0:9b334a45a8ff 546 break;
bogdanm 0:9b334a45a8ff 547 case PWR_GPIO_H:
bogdanm 0:9b334a45a8ff 548 if ((gpiocurrent != PWR_GPIO_BIT_0) && (gpiocurrent != PWR_GPIO_BIT_1))
bogdanm 0:9b334a45a8ff 549 {
bogdanm 0:9b334a45a8ff 550 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 551 }
bogdanm 0:9b334a45a8ff 552 else
bogdanm 0:9b334a45a8ff 553 {
bogdanm 0:9b334a45a8ff 554 SET_BIT(PWR->PDCRH, GPIONumber);
bogdanm 0:9b334a45a8ff 555 CLEAR_BIT(PWR->PUCRH, GPIONumber);
bogdanm 0:9b334a45a8ff 556 }
bogdanm 0:9b334a45a8ff 557 break;
bogdanm 0:9b334a45a8ff 558 default:
bogdanm 0:9b334a45a8ff 559 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 560 }
bogdanm 0:9b334a45a8ff 561 } /* if (gpiocurrent) */
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 position++;
bogdanm 0:9b334a45a8ff 564
bogdanm 0:9b334a45a8ff 565 } /* while (GPIONumber >> position) */
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 return HAL_OK;
bogdanm 0:9b334a45a8ff 568 }
bogdanm 0:9b334a45a8ff 569
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571 /**
bogdanm 0:9b334a45a8ff 572 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
bogdanm 0:9b334a45a8ff 573 * @note Reset the relevant PDy bit of PWR_PDCRx register used to configure the I/O
bogdanm 0:9b334a45a8ff 574 * in pull-down state in Standby and Shutdown modes.
bogdanm 0:9b334a45a8ff 575 * @note The API returns HAL_ERROR when PDy bit is reserved.
bogdanm 0:9b334a45a8ff 576 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
bogdanm 0:9b334a45a8ff 577 * to select the GPIO peripheral.
bogdanm 0:9b334a45a8ff 578 * @param GPIONumber: Specify the I/O pins numbers.
bogdanm 0:9b334a45a8ff 579 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 580 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
bogdanm 0:9b334a45a8ff 581 * I/O pins are available) or the logical OR of several of them to reset
bogdanm 0:9b334a45a8ff 582 * several bits for a given port in a single API call.
bogdanm 0:9b334a45a8ff 583 * @retval HAL Status
bogdanm 0:9b334a45a8ff 584 */
bogdanm 0:9b334a45a8ff 585 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
bogdanm 0:9b334a45a8ff 586 {
bogdanm 0:9b334a45a8ff 587 uint32_t position = 0x00;
bogdanm 0:9b334a45a8ff 588 uint32_t gpiocurrent = 0x00;
bogdanm 0:9b334a45a8ff 589
bogdanm 0:9b334a45a8ff 590 assert_param(IS_PWR_GPIO(GPIO));
bogdanm 0:9b334a45a8ff 591 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
bogdanm 0:9b334a45a8ff 592
bogdanm 0:9b334a45a8ff 593 while ((GPIONumber >> position) != RESET)
bogdanm 0:9b334a45a8ff 594 {
bogdanm 0:9b334a45a8ff 595 /* Get current gpio position */
bogdanm 0:9b334a45a8ff 596 gpiocurrent = (GPIONumber) & (1U << position);
bogdanm 0:9b334a45a8ff 597
bogdanm 0:9b334a45a8ff 598 if (gpiocurrent)
bogdanm 0:9b334a45a8ff 599 {
bogdanm 0:9b334a45a8ff 600 switch (GPIO)
bogdanm 0:9b334a45a8ff 601 {
bogdanm 0:9b334a45a8ff 602 case PWR_GPIO_A:
bogdanm 0:9b334a45a8ff 603 if ((GPIONumber == PWR_GPIO_BIT_13) || (GPIONumber == PWR_GPIO_BIT_15))
bogdanm 0:9b334a45a8ff 604 {
bogdanm 0:9b334a45a8ff 605 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 606 }
bogdanm 0:9b334a45a8ff 607 else
bogdanm 0:9b334a45a8ff 608 {
bogdanm 0:9b334a45a8ff 609 CLEAR_BIT(PWR->PDCRA, GPIONumber);
bogdanm 0:9b334a45a8ff 610 }
bogdanm 0:9b334a45a8ff 611 break;
bogdanm 0:9b334a45a8ff 612 case PWR_GPIO_B:
bogdanm 0:9b334a45a8ff 613 if (GPIONumber == PWR_GPIO_BIT_4)
bogdanm 0:9b334a45a8ff 614 {
bogdanm 0:9b334a45a8ff 615 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 616 }
bogdanm 0:9b334a45a8ff 617 else
bogdanm 0:9b334a45a8ff 618 {
bogdanm 0:9b334a45a8ff 619 CLEAR_BIT(PWR->PDCRB, GPIONumber);
bogdanm 0:9b334a45a8ff 620 }
bogdanm 0:9b334a45a8ff 621 break;
bogdanm 0:9b334a45a8ff 622 case PWR_GPIO_C:
bogdanm 0:9b334a45a8ff 623 CLEAR_BIT(PWR->PDCRC, GPIONumber);
bogdanm 0:9b334a45a8ff 624 break;
bogdanm 0:9b334a45a8ff 625 case PWR_GPIO_D:
bogdanm 0:9b334a45a8ff 626 CLEAR_BIT(PWR->PDCRD, GPIONumber);
bogdanm 0:9b334a45a8ff 627 break;
bogdanm 0:9b334a45a8ff 628 case PWR_GPIO_E:
bogdanm 0:9b334a45a8ff 629 CLEAR_BIT(PWR->PDCRE, GPIONumber);
bogdanm 0:9b334a45a8ff 630 break;
bogdanm 0:9b334a45a8ff 631 case PWR_GPIO_F:
bogdanm 0:9b334a45a8ff 632 CLEAR_BIT(PWR->PDCRF, GPIONumber);
bogdanm 0:9b334a45a8ff 633 break;
bogdanm 0:9b334a45a8ff 634 case PWR_GPIO_G:
bogdanm 0:9b334a45a8ff 635 CLEAR_BIT(PWR->PDCRG, GPIONumber);
bogdanm 0:9b334a45a8ff 636 break;
bogdanm 0:9b334a45a8ff 637 case PWR_GPIO_H:
bogdanm 0:9b334a45a8ff 638 if ((gpiocurrent != PWR_GPIO_BIT_0) && (gpiocurrent != PWR_GPIO_BIT_1))
bogdanm 0:9b334a45a8ff 639 {
bogdanm 0:9b334a45a8ff 640 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 641 }
bogdanm 0:9b334a45a8ff 642 else
bogdanm 0:9b334a45a8ff 643 {
bogdanm 0:9b334a45a8ff 644 CLEAR_BIT(PWR->PDCRH, GPIONumber);
bogdanm 0:9b334a45a8ff 645 }
bogdanm 0:9b334a45a8ff 646 break;
bogdanm 0:9b334a45a8ff 647 default:
bogdanm 0:9b334a45a8ff 648 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 649 }
bogdanm 0:9b334a45a8ff 650 } /* if (gpiocurrent) */
bogdanm 0:9b334a45a8ff 651
bogdanm 0:9b334a45a8ff 652 position++;
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 } /* while (GPIONumber >> position) */
bogdanm 0:9b334a45a8ff 655
bogdanm 0:9b334a45a8ff 656 return HAL_OK;
bogdanm 0:9b334a45a8ff 657 }
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 /**
bogdanm 0:9b334a45a8ff 662 * @brief Enable pull-up and pull-down configuration.
bogdanm 0:9b334a45a8ff 663 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
bogdanm 0:9b334a45a8ff 664 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
bogdanm 0:9b334a45a8ff 665 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
bogdanm 0:9b334a45a8ff 666 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
bogdanm 0:9b334a45a8ff 667 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
bogdanm 0:9b334a45a8ff 668 * is no conflict when setting PUy or PDy bit.
bogdanm 0:9b334a45a8ff 669 * @retval None
bogdanm 0:9b334a45a8ff 670 */
bogdanm 0:9b334a45a8ff 671 void HAL_PWREx_EnablePullUpPullDownConfig(void)
bogdanm 0:9b334a45a8ff 672 {
bogdanm 0:9b334a45a8ff 673 SET_BIT(PWR->CR3, PWR_CR3_APC);
bogdanm 0:9b334a45a8ff 674 }
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 /**
bogdanm 0:9b334a45a8ff 678 * @brief Disable pull-up and pull-down configuration.
bogdanm 0:9b334a45a8ff 679 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
bogdanm 0:9b334a45a8ff 680 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
bogdanm 0:9b334a45a8ff 681 * @retval None
bogdanm 0:9b334a45a8ff 682 */
bogdanm 0:9b334a45a8ff 683 void HAL_PWREx_DisablePullUpPullDownConfig(void)
bogdanm 0:9b334a45a8ff 684 {
bogdanm 0:9b334a45a8ff 685 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
bogdanm 0:9b334a45a8ff 686 }
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 /**
bogdanm 0:9b334a45a8ff 691 * @brief Enable SRAM2 content retention in Standby mode.
bogdanm 0:9b334a45a8ff 692 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
bogdanm 0:9b334a45a8ff 693 * Standby mode and its content is kept.
bogdanm 0:9b334a45a8ff 694 * @retval None
bogdanm 0:9b334a45a8ff 695 */
bogdanm 0:9b334a45a8ff 696 void HAL_PWREx_EnableSRAM2ContentRetention(void)
bogdanm 0:9b334a45a8ff 697 {
bogdanm 0:9b334a45a8ff 698 SET_BIT(PWR->CR3, PWR_CR3_RRS);
bogdanm 0:9b334a45a8ff 699 }
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701
bogdanm 0:9b334a45a8ff 702 /**
bogdanm 0:9b334a45a8ff 703 * @brief Disable SRAM2 content retention in Standby mode.
bogdanm 0:9b334a45a8ff 704 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode
bogdanm 0:9b334a45a8ff 705 * and its content is lost.
bogdanm 0:9b334a45a8ff 706 * @retval None
bogdanm 0:9b334a45a8ff 707 */
bogdanm 0:9b334a45a8ff 708 void HAL_PWREx_DisableSRAM2ContentRetention(void)
bogdanm 0:9b334a45a8ff 709 {
bogdanm 0:9b334a45a8ff 710 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
bogdanm 0:9b334a45a8ff 711 }
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713
bogdanm 0:9b334a45a8ff 714
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
bogdanm 0:9b334a45a8ff 717 /**
bogdanm 0:9b334a45a8ff 718 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
bogdanm 0:9b334a45a8ff 719 * @retval None
bogdanm 0:9b334a45a8ff 720 */
bogdanm 0:9b334a45a8ff 721 void HAL_PWREx_EnablePVM1(void)
bogdanm 0:9b334a45a8ff 722 {
bogdanm 0:9b334a45a8ff 723 SET_BIT(PWR->CR2, PWR_PVM_1);
bogdanm 0:9b334a45a8ff 724 }
bogdanm 0:9b334a45a8ff 725
bogdanm 0:9b334a45a8ff 726 /**
bogdanm 0:9b334a45a8ff 727 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
bogdanm 0:9b334a45a8ff 728 * @retval None
bogdanm 0:9b334a45a8ff 729 */
bogdanm 0:9b334a45a8ff 730 void HAL_PWREx_DisablePVM1(void)
bogdanm 0:9b334a45a8ff 731 {
bogdanm 0:9b334a45a8ff 732 CLEAR_BIT(PWR->CR2, PWR_PVM_1);
bogdanm 0:9b334a45a8ff 733 }
bogdanm 0:9b334a45a8ff 734 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
bogdanm 0:9b334a45a8ff 735
bogdanm 0:9b334a45a8ff 736 /**
bogdanm 0:9b334a45a8ff 737 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
bogdanm 0:9b334a45a8ff 738 * @retval None
bogdanm 0:9b334a45a8ff 739 */
bogdanm 0:9b334a45a8ff 740 void HAL_PWREx_EnablePVM2(void)
bogdanm 0:9b334a45a8ff 741 {
bogdanm 0:9b334a45a8ff 742 SET_BIT(PWR->CR2, PWR_PVM_2);
bogdanm 0:9b334a45a8ff 743 }
bogdanm 0:9b334a45a8ff 744
bogdanm 0:9b334a45a8ff 745 /**
bogdanm 0:9b334a45a8ff 746 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
bogdanm 0:9b334a45a8ff 747 * @retval None
bogdanm 0:9b334a45a8ff 748 */
bogdanm 0:9b334a45a8ff 749 void HAL_PWREx_DisablePVM2(void)
bogdanm 0:9b334a45a8ff 750 {
bogdanm 0:9b334a45a8ff 751 CLEAR_BIT(PWR->CR2, PWR_PVM_2);
bogdanm 0:9b334a45a8ff 752 }
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754
bogdanm 0:9b334a45a8ff 755 /**
bogdanm 0:9b334a45a8ff 756 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
bogdanm 0:9b334a45a8ff 757 * @retval None
bogdanm 0:9b334a45a8ff 758 */
bogdanm 0:9b334a45a8ff 759 void HAL_PWREx_EnablePVM3(void)
bogdanm 0:9b334a45a8ff 760 {
bogdanm 0:9b334a45a8ff 761 SET_BIT(PWR->CR2, PWR_PVM_3);
bogdanm 0:9b334a45a8ff 762 }
bogdanm 0:9b334a45a8ff 763
bogdanm 0:9b334a45a8ff 764 /**
bogdanm 0:9b334a45a8ff 765 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
bogdanm 0:9b334a45a8ff 766 * @retval None
bogdanm 0:9b334a45a8ff 767 */
bogdanm 0:9b334a45a8ff 768 void HAL_PWREx_DisablePVM3(void)
bogdanm 0:9b334a45a8ff 769 {
bogdanm 0:9b334a45a8ff 770 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
bogdanm 0:9b334a45a8ff 771 }
bogdanm 0:9b334a45a8ff 772
bogdanm 0:9b334a45a8ff 773
bogdanm 0:9b334a45a8ff 774 /**
bogdanm 0:9b334a45a8ff 775 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.
bogdanm 0:9b334a45a8ff 776 * @retval None
bogdanm 0:9b334a45a8ff 777 */
bogdanm 0:9b334a45a8ff 778 void HAL_PWREx_EnablePVM4(void)
bogdanm 0:9b334a45a8ff 779 {
bogdanm 0:9b334a45a8ff 780 SET_BIT(PWR->CR2, PWR_PVM_4);
bogdanm 0:9b334a45a8ff 781 }
bogdanm 0:9b334a45a8ff 782
bogdanm 0:9b334a45a8ff 783 /**
bogdanm 0:9b334a45a8ff 784 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.
bogdanm 0:9b334a45a8ff 785 * @retval None
bogdanm 0:9b334a45a8ff 786 */
bogdanm 0:9b334a45a8ff 787 void HAL_PWREx_DisablePVM4(void)
bogdanm 0:9b334a45a8ff 788 {
bogdanm 0:9b334a45a8ff 789 CLEAR_BIT(PWR->CR2, PWR_PVM_4);
bogdanm 0:9b334a45a8ff 790 }
bogdanm 0:9b334a45a8ff 791
bogdanm 0:9b334a45a8ff 792
bogdanm 0:9b334a45a8ff 793
bogdanm 0:9b334a45a8ff 794
bogdanm 0:9b334a45a8ff 795 /**
bogdanm 0:9b334a45a8ff 796 * @brief Configure the Peripheral Voltage Monitoring (PVM).
bogdanm 0:9b334a45a8ff 797 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
bogdanm 0:9b334a45a8ff 798 * PVM configuration information.
bogdanm 0:9b334a45a8ff 799 * @note The API configures a single PVM according to the information contained
bogdanm 0:9b334a45a8ff 800 * in the input structure. To configure several PVMs, the API must be singly
bogdanm 0:9b334a45a8ff 801 * called for each PVM used.
bogdanm 0:9b334a45a8ff 802 * @note Refer to the electrical characteristics of your device datasheet for
bogdanm 0:9b334a45a8ff 803 * more details about the voltage thresholds corresponding to each
bogdanm 0:9b334a45a8ff 804 * detection level and to each monitored supply.
bogdanm 0:9b334a45a8ff 805 * @retval HAL status
bogdanm 0:9b334a45a8ff 806 */
bogdanm 0:9b334a45a8ff 807 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
bogdanm 0:9b334a45a8ff 808 {
bogdanm 0:9b334a45a8ff 809 /* Check the parameters */
bogdanm 0:9b334a45a8ff 810 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
bogdanm 0:9b334a45a8ff 811 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
bogdanm 0:9b334a45a8ff 812
bogdanm 0:9b334a45a8ff 813
bogdanm 0:9b334a45a8ff 814 /* Configure EXTI 35 to 38 interrupts if so required:
bogdanm 0:9b334a45a8ff 815 scan thru PVMType to detect which PVMx is set and
bogdanm 0:9b334a45a8ff 816 configure the corresponding EXTI line accordingly. */
bogdanm 0:9b334a45a8ff 817 switch (sConfigPVM->PVMType)
bogdanm 0:9b334a45a8ff 818 {
bogdanm 0:9b334a45a8ff 819 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
bogdanm 0:9b334a45a8ff 820 case PWR_PVM_1:
bogdanm 0:9b334a45a8ff 821 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
bogdanm 0:9b334a45a8ff 822 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
bogdanm 0:9b334a45a8ff 823 __HAL_PWR_PVM1_EXTI_DISABLE_IT();
bogdanm 0:9b334a45a8ff 824 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 825 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 826
bogdanm 0:9b334a45a8ff 827 /* Configure interrupt mode */
bogdanm 0:9b334a45a8ff 828 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
bogdanm 0:9b334a45a8ff 829 {
bogdanm 0:9b334a45a8ff 830 __HAL_PWR_PVM1_EXTI_ENABLE_IT();
bogdanm 0:9b334a45a8ff 831 }
bogdanm 0:9b334a45a8ff 832
bogdanm 0:9b334a45a8ff 833 /* Configure event mode */
bogdanm 0:9b334a45a8ff 834 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
bogdanm 0:9b334a45a8ff 835 {
bogdanm 0:9b334a45a8ff 836 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
bogdanm 0:9b334a45a8ff 837 }
bogdanm 0:9b334a45a8ff 838
bogdanm 0:9b334a45a8ff 839 /* Configure the edge */
bogdanm 0:9b334a45a8ff 840 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
bogdanm 0:9b334a45a8ff 841 {
bogdanm 0:9b334a45a8ff 842 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 843 }
bogdanm 0:9b334a45a8ff 844
bogdanm 0:9b334a45a8ff 845 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
bogdanm 0:9b334a45a8ff 846 {
bogdanm 0:9b334a45a8ff 847 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 848 }
bogdanm 0:9b334a45a8ff 849 break;
bogdanm 0:9b334a45a8ff 850 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
bogdanm 0:9b334a45a8ff 851
bogdanm 0:9b334a45a8ff 852 case PWR_PVM_2:
bogdanm 0:9b334a45a8ff 853 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
bogdanm 0:9b334a45a8ff 854 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
bogdanm 0:9b334a45a8ff 855 __HAL_PWR_PVM2_EXTI_DISABLE_IT();
bogdanm 0:9b334a45a8ff 856 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 857 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 858
bogdanm 0:9b334a45a8ff 859 /* Configure interrupt mode */
bogdanm 0:9b334a45a8ff 860 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
bogdanm 0:9b334a45a8ff 861 {
bogdanm 0:9b334a45a8ff 862 __HAL_PWR_PVM2_EXTI_ENABLE_IT();
bogdanm 0:9b334a45a8ff 863 }
bogdanm 0:9b334a45a8ff 864
bogdanm 0:9b334a45a8ff 865 /* Configure event mode */
bogdanm 0:9b334a45a8ff 866 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
bogdanm 0:9b334a45a8ff 867 {
bogdanm 0:9b334a45a8ff 868 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
bogdanm 0:9b334a45a8ff 869 }
bogdanm 0:9b334a45a8ff 870
bogdanm 0:9b334a45a8ff 871 /* Configure the edge */
bogdanm 0:9b334a45a8ff 872 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
bogdanm 0:9b334a45a8ff 873 {
bogdanm 0:9b334a45a8ff 874 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 875 }
bogdanm 0:9b334a45a8ff 876
bogdanm 0:9b334a45a8ff 877 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
bogdanm 0:9b334a45a8ff 878 {
bogdanm 0:9b334a45a8ff 879 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 880 }
bogdanm 0:9b334a45a8ff 881 break;
bogdanm 0:9b334a45a8ff 882
bogdanm 0:9b334a45a8ff 883 case PWR_PVM_3:
bogdanm 0:9b334a45a8ff 884 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
bogdanm 0:9b334a45a8ff 885 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
bogdanm 0:9b334a45a8ff 886 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
bogdanm 0:9b334a45a8ff 887 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 888 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 889
bogdanm 0:9b334a45a8ff 890 /* Configure interrupt mode */
bogdanm 0:9b334a45a8ff 891 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
bogdanm 0:9b334a45a8ff 892 {
bogdanm 0:9b334a45a8ff 893 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
bogdanm 0:9b334a45a8ff 894 }
bogdanm 0:9b334a45a8ff 895
bogdanm 0:9b334a45a8ff 896 /* Configure event mode */
bogdanm 0:9b334a45a8ff 897 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
bogdanm 0:9b334a45a8ff 898 {
bogdanm 0:9b334a45a8ff 899 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
bogdanm 0:9b334a45a8ff 900 }
bogdanm 0:9b334a45a8ff 901
bogdanm 0:9b334a45a8ff 902 /* Configure the edge */
bogdanm 0:9b334a45a8ff 903 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
bogdanm 0:9b334a45a8ff 904 {
bogdanm 0:9b334a45a8ff 905 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 906 }
bogdanm 0:9b334a45a8ff 907
bogdanm 0:9b334a45a8ff 908 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
bogdanm 0:9b334a45a8ff 909 {
bogdanm 0:9b334a45a8ff 910 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 911 }
bogdanm 0:9b334a45a8ff 912 break;
bogdanm 0:9b334a45a8ff 913
bogdanm 0:9b334a45a8ff 914 case PWR_PVM_4:
bogdanm 0:9b334a45a8ff 915 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
bogdanm 0:9b334a45a8ff 916 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
bogdanm 0:9b334a45a8ff 917 __HAL_PWR_PVM4_EXTI_DISABLE_IT();
bogdanm 0:9b334a45a8ff 918 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 919 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 920
bogdanm 0:9b334a45a8ff 921 /* Configure interrupt mode */
bogdanm 0:9b334a45a8ff 922 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
bogdanm 0:9b334a45a8ff 923 {
bogdanm 0:9b334a45a8ff 924 __HAL_PWR_PVM4_EXTI_ENABLE_IT();
bogdanm 0:9b334a45a8ff 925 }
bogdanm 0:9b334a45a8ff 926
bogdanm 0:9b334a45a8ff 927 /* Configure event mode */
bogdanm 0:9b334a45a8ff 928 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
bogdanm 0:9b334a45a8ff 929 {
bogdanm 0:9b334a45a8ff 930 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
bogdanm 0:9b334a45a8ff 931 }
bogdanm 0:9b334a45a8ff 932
bogdanm 0:9b334a45a8ff 933 /* Configure the edge */
bogdanm 0:9b334a45a8ff 934 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
bogdanm 0:9b334a45a8ff 935 {
bogdanm 0:9b334a45a8ff 936 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 937 }
bogdanm 0:9b334a45a8ff 938
bogdanm 0:9b334a45a8ff 939 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
bogdanm 0:9b334a45a8ff 940 {
bogdanm 0:9b334a45a8ff 941 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 942 }
bogdanm 0:9b334a45a8ff 943 break;
bogdanm 0:9b334a45a8ff 944
bogdanm 0:9b334a45a8ff 945 default:
bogdanm 0:9b334a45a8ff 946 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 947
bogdanm 0:9b334a45a8ff 948 }
bogdanm 0:9b334a45a8ff 949
bogdanm 0:9b334a45a8ff 950
bogdanm 0:9b334a45a8ff 951 return HAL_OK;
bogdanm 0:9b334a45a8ff 952 }
bogdanm 0:9b334a45a8ff 953
bogdanm 0:9b334a45a8ff 954
bogdanm 0:9b334a45a8ff 955
bogdanm 0:9b334a45a8ff 956 /**
bogdanm 0:9b334a45a8ff 957 * @brief Enter Low-power Run mode
bogdanm 0:9b334a45a8ff 958 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 959 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
bogdanm 0:9b334a45a8ff 960 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
bogdanm 0:9b334a45a8ff 961 * Additionally, the clock frequency must be reduced below 2 MHz.
bogdanm 0:9b334a45a8ff 962 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
bogdanm 0:9b334a45a8ff 963 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
bogdanm 0:9b334a45a8ff 964 * @retval None
bogdanm 0:9b334a45a8ff 965 */
bogdanm 0:9b334a45a8ff 966 void HAL_PWREx_EnableLowPowerRunMode(void)
bogdanm 0:9b334a45a8ff 967 {
bogdanm 0:9b334a45a8ff 968 /* Set Regulator parameter */
bogdanm 0:9b334a45a8ff 969 SET_BIT(PWR->CR1, PWR_CR1_LPR);
bogdanm 0:9b334a45a8ff 970 }
bogdanm 0:9b334a45a8ff 971
bogdanm 0:9b334a45a8ff 972
bogdanm 0:9b334a45a8ff 973 /**
bogdanm 0:9b334a45a8ff 974 * @brief Exit Low-power Run mode.
bogdanm 0:9b334a45a8ff 975 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
bogdanm 0:9b334a45a8ff 976 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
bogdanm 0:9b334a45a8ff 977 * returns HAL_TIMEOUT status). The system clock frequency can then be
bogdanm 0:9b334a45a8ff 978 * increased above 2 MHz.
bogdanm 0:9b334a45a8ff 979 * @retval HAL Status
bogdanm 0:9b334a45a8ff 980 */
bogdanm 0:9b334a45a8ff 981 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
bogdanm 0:9b334a45a8ff 982 {
bogdanm 0:9b334a45a8ff 983 uint32_t wait_loop_index = 0;
bogdanm 0:9b334a45a8ff 984
bogdanm 0:9b334a45a8ff 985 /* Clear LPR bit */
bogdanm 0:9b334a45a8ff 986 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
bogdanm 0:9b334a45a8ff 987
bogdanm 0:9b334a45a8ff 988 /* Wait until REGLPF is reset */
bogdanm 0:9b334a45a8ff 989 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
bogdanm 0:9b334a45a8ff 990 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)))
bogdanm 0:9b334a45a8ff 991 {
bogdanm 0:9b334a45a8ff 992 wait_loop_index--;
bogdanm 0:9b334a45a8ff 993 }
bogdanm 0:9b334a45a8ff 994 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
bogdanm 0:9b334a45a8ff 995 {
bogdanm 0:9b334a45a8ff 996 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 997 }
bogdanm 0:9b334a45a8ff 998
bogdanm 0:9b334a45a8ff 999 return HAL_OK;
bogdanm 0:9b334a45a8ff 1000 }
bogdanm 0:9b334a45a8ff 1001
bogdanm 0:9b334a45a8ff 1002
bogdanm 0:9b334a45a8ff 1003 /**
bogdanm 0:9b334a45a8ff 1004 * @brief Enter Stop 1 mode.
bogdanm 0:9b334a45a8ff 1005 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 1006 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
bogdanm 0:9b334a45a8ff 1007 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
bogdanm 0:9b334a45a8ff 1008 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
bogdanm 0:9b334a45a8ff 1009 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
bogdanm 0:9b334a45a8ff 1010 * only to the peripheral requesting it.
bogdanm 0:9b334a45a8ff 1011 * SRAM1, SRAM2 and register contents are preserved.
bogdanm 0:9b334a45a8ff 1012 * The BOR is available.
bogdanm 0:9b334a45a8ff 1013 * The voltage regulator can be configured either in normal or low-power mode.
bogdanm 0:9b334a45a8ff 1014 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
bogdanm 0:9b334a45a8ff 1015 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
bogdanm 0:9b334a45a8ff 1016 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
bogdanm 0:9b334a45a8ff 1017 * @note When the voltage regulator operates in low power mode, an additional
bogdanm 0:9b334a45a8ff 1018 * startup delay is incurred when waking up from Stop 1 mode.
bogdanm 0:9b334a45a8ff 1019 * By keeping the internal regulator ON during Stop 1 mode, the consumption
bogdanm 0:9b334a45a8ff 1020 * is higher although the startup time is reduced.
bogdanm 0:9b334a45a8ff 1021 * @param Regulator: Specifies the regulator state in Stop 1 mode.
bogdanm 0:9b334a45a8ff 1022 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1023 * @arg PWR_MAINREGULATOR_ON: Stop 1 mode with regulator ON
bogdanm 0:9b334a45a8ff 1024 * @arg PWR_LOWPOWERREGULATOR_ON: Stop 1 mode with low power regulator ON
bogdanm 0:9b334a45a8ff 1025 * This parameter has no effect when entering stop mode 2.
bogdanm 0:9b334a45a8ff 1026 * @param STOPEntry: specifies if Stop mode in entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 1027 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1028 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
bogdanm 0:9b334a45a8ff 1029 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
bogdanm 0:9b334a45a8ff 1030 * @retval None
bogdanm 0:9b334a45a8ff 1031 */
bogdanm 0:9b334a45a8ff 1032 void HAL_PWREx_EnterSTOP1Mode(uint32_t Regulator, uint8_t STOPEntry)
bogdanm 0:9b334a45a8ff 1033 {
bogdanm 0:9b334a45a8ff 1034 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1035 assert_param(IS_PWR_REGULATOR(Regulator));
bogdanm 0:9b334a45a8ff 1036 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
bogdanm 0:9b334a45a8ff 1037
bogdanm 0:9b334a45a8ff 1038 if (Regulator == PWR_MAINREGULATOR_ON)
bogdanm 0:9b334a45a8ff 1039 {
bogdanm 0:9b334a45a8ff 1040 /* Stop 1 mode with Main Regulator */
bogdanm 0:9b334a45a8ff 1041 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1MR);
bogdanm 0:9b334a45a8ff 1042 }
bogdanm 0:9b334a45a8ff 1043 else
bogdanm 0:9b334a45a8ff 1044 {
bogdanm 0:9b334a45a8ff 1045 /* Stop 1 mode with Low-Power Regulator */
bogdanm 0:9b334a45a8ff 1046 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1LPR);
bogdanm 0:9b334a45a8ff 1047 }
bogdanm 0:9b334a45a8ff 1048
bogdanm 0:9b334a45a8ff 1049 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 1050 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 1051
bogdanm 0:9b334a45a8ff 1052 /* Select Stop mode entry --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1053 if(STOPEntry == PWR_STOPENTRY_WFI)
bogdanm 0:9b334a45a8ff 1054 {
bogdanm 0:9b334a45a8ff 1055 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 1056 __WFI();
bogdanm 0:9b334a45a8ff 1057 }
bogdanm 0:9b334a45a8ff 1058 else
bogdanm 0:9b334a45a8ff 1059 {
bogdanm 0:9b334a45a8ff 1060 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 1061 __SEV();
bogdanm 0:9b334a45a8ff 1062 __WFE();
bogdanm 0:9b334a45a8ff 1063 __WFE();
bogdanm 0:9b334a45a8ff 1064 }
bogdanm 0:9b334a45a8ff 1065
bogdanm 0:9b334a45a8ff 1066 /* Reset SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 1067 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 1068 }
bogdanm 0:9b334a45a8ff 1069
bogdanm 0:9b334a45a8ff 1070
bogdanm 0:9b334a45a8ff 1071 /**
bogdanm 0:9b334a45a8ff 1072 * @brief Enter Stop 2 mode.
bogdanm 0:9b334a45a8ff 1073 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 1074 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
bogdanm 0:9b334a45a8ff 1075 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
bogdanm 0:9b334a45a8ff 1076 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
bogdanm 0:9b334a45a8ff 1077 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
bogdanm 0:9b334a45a8ff 1078 * to the peripheral requesting it.
bogdanm 0:9b334a45a8ff 1079 * SRAM1, SRAM2 and register contents are preserved.
bogdanm 0:9b334a45a8ff 1080 * The BOR is available.
bogdanm 0:9b334a45a8ff 1081 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
bogdanm 0:9b334a45a8ff 1082 * Otherwise, Stop 1 mode is entered.
bogdanm 0:9b334a45a8ff 1083 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
bogdanm 0:9b334a45a8ff 1084 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
bogdanm 0:9b334a45a8ff 1085 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
bogdanm 0:9b334a45a8ff 1086 * @param STOPEntry: specifies if Stop mode in entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 1087 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1088 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
bogdanm 0:9b334a45a8ff 1089 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
bogdanm 0:9b334a45a8ff 1090 * @retval None
bogdanm 0:9b334a45a8ff 1091 */
bogdanm 0:9b334a45a8ff 1092 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
bogdanm 0:9b334a45a8ff 1093 {
bogdanm 0:9b334a45a8ff 1094 /* Check the parameter */
bogdanm 0:9b334a45a8ff 1095 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
bogdanm 0:9b334a45a8ff 1096
bogdanm 0:9b334a45a8ff 1097 /* Set Stop mode 2 */
bogdanm 0:9b334a45a8ff 1098 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
bogdanm 0:9b334a45a8ff 1099
bogdanm 0:9b334a45a8ff 1100
bogdanm 0:9b334a45a8ff 1101 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 1102 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 1103
bogdanm 0:9b334a45a8ff 1104 /* Select Stop mode entry --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1105 if(STOPEntry == PWR_STOPENTRY_WFI)
bogdanm 0:9b334a45a8ff 1106 {
bogdanm 0:9b334a45a8ff 1107 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 1108 __WFI();
bogdanm 0:9b334a45a8ff 1109 }
bogdanm 0:9b334a45a8ff 1110 else
bogdanm 0:9b334a45a8ff 1111 {
bogdanm 0:9b334a45a8ff 1112 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 1113 __SEV();
bogdanm 0:9b334a45a8ff 1114 __WFE();
bogdanm 0:9b334a45a8ff 1115 __WFE();
bogdanm 0:9b334a45a8ff 1116 }
bogdanm 0:9b334a45a8ff 1117
bogdanm 0:9b334a45a8ff 1118 /* Reset SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 1119 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 1120 }
bogdanm 0:9b334a45a8ff 1121
bogdanm 0:9b334a45a8ff 1122
bogdanm 0:9b334a45a8ff 1123
bogdanm 0:9b334a45a8ff 1124
bogdanm 0:9b334a45a8ff 1125
bogdanm 0:9b334a45a8ff 1126 /**
bogdanm 0:9b334a45a8ff 1127 * @brief Enter Shutdown mode.
bogdanm 0:9b334a45a8ff 1128 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
bogdanm 0:9b334a45a8ff 1129 * off. The voltage regulator is disabled and Vcore domain is powered off.
bogdanm 0:9b334a45a8ff 1130 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
bogdanm 0:9b334a45a8ff 1131 * The BOR is not available.
bogdanm 0:9b334a45a8ff 1132 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
bogdanm 0:9b334a45a8ff 1133 * @retval None
bogdanm 0:9b334a45a8ff 1134 */
bogdanm 0:9b334a45a8ff 1135 void HAL_PWREx_EnterSHUTDOWNMode(void)
bogdanm 0:9b334a45a8ff 1136 {
bogdanm 0:9b334a45a8ff 1137
bogdanm 0:9b334a45a8ff 1138 /* Set Shutdown mode */
bogdanm 0:9b334a45a8ff 1139 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
bogdanm 0:9b334a45a8ff 1140
bogdanm 0:9b334a45a8ff 1141 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 1142 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 1143
bogdanm 0:9b334a45a8ff 1144 /* This option is used to ensure that store operations are completed */
bogdanm 0:9b334a45a8ff 1145 #if defined ( __CC_ARM)
bogdanm 0:9b334a45a8ff 1146 __force_stores();
bogdanm 0:9b334a45a8ff 1147 #endif
bogdanm 0:9b334a45a8ff 1148 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 1149 __WFI();
bogdanm 0:9b334a45a8ff 1150 }
bogdanm 0:9b334a45a8ff 1151
bogdanm 0:9b334a45a8ff 1152
bogdanm 0:9b334a45a8ff 1153
bogdanm 0:9b334a45a8ff 1154
bogdanm 0:9b334a45a8ff 1155 /**
bogdanm 0:9b334a45a8ff 1156 * @brief This function handles the PWR PVD/PVMx interrupt request.
bogdanm 0:9b334a45a8ff 1157 * @note This API should be called under the PVD_PVM_IRQHandler().
bogdanm 0:9b334a45a8ff 1158 * @retval None
bogdanm 0:9b334a45a8ff 1159 */
bogdanm 0:9b334a45a8ff 1160 void HAL_PWREx_PVD_PVM_IRQHandler(void)
bogdanm 0:9b334a45a8ff 1161 {
bogdanm 0:9b334a45a8ff 1162 /* Check PWR exti flag */
bogdanm 0:9b334a45a8ff 1163 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
bogdanm 0:9b334a45a8ff 1164 {
bogdanm 0:9b334a45a8ff 1165 /* PWR PVD interrupt user callback */
bogdanm 0:9b334a45a8ff 1166 HAL_PWR_PVDCallback();
bogdanm 0:9b334a45a8ff 1167
bogdanm 0:9b334a45a8ff 1168 /* Clear PVD exti pending bit */
bogdanm 0:9b334a45a8ff 1169 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
bogdanm 0:9b334a45a8ff 1170 }
bogdanm 0:9b334a45a8ff 1171 /* Next, successively check PVMx exti flags */
bogdanm 0:9b334a45a8ff 1172 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
bogdanm 0:9b334a45a8ff 1173 if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET)
bogdanm 0:9b334a45a8ff 1174 {
bogdanm 0:9b334a45a8ff 1175 /* PWR PVM1 interrupt user callback */
bogdanm 0:9b334a45a8ff 1176 HAL_PWREx_PVM1Callback();
bogdanm 0:9b334a45a8ff 1177
bogdanm 0:9b334a45a8ff 1178 /* Clear PVM1 exti pending bit */
bogdanm 0:9b334a45a8ff 1179 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
bogdanm 0:9b334a45a8ff 1180 }
bogdanm 0:9b334a45a8ff 1181 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
bogdanm 0:9b334a45a8ff 1182 if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET)
bogdanm 0:9b334a45a8ff 1183 {
bogdanm 0:9b334a45a8ff 1184 /* PWR PVM2 interrupt user callback */
bogdanm 0:9b334a45a8ff 1185 HAL_PWREx_PVM2Callback();
bogdanm 0:9b334a45a8ff 1186
bogdanm 0:9b334a45a8ff 1187 /* Clear PVM2 exti pending bit */
bogdanm 0:9b334a45a8ff 1188 __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
bogdanm 0:9b334a45a8ff 1189 }
bogdanm 0:9b334a45a8ff 1190 if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET)
bogdanm 0:9b334a45a8ff 1191 {
bogdanm 0:9b334a45a8ff 1192 /* PWR PVM3 interrupt user callback */
bogdanm 0:9b334a45a8ff 1193 HAL_PWREx_PVM3Callback();
bogdanm 0:9b334a45a8ff 1194
bogdanm 0:9b334a45a8ff 1195 /* Clear PVM3 exti pending bit */
bogdanm 0:9b334a45a8ff 1196 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
bogdanm 0:9b334a45a8ff 1197 }
bogdanm 0:9b334a45a8ff 1198 if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET)
bogdanm 0:9b334a45a8ff 1199 {
bogdanm 0:9b334a45a8ff 1200 /* PWR PVM4 interrupt user callback */
bogdanm 0:9b334a45a8ff 1201 HAL_PWREx_PVM4Callback();
bogdanm 0:9b334a45a8ff 1202
bogdanm 0:9b334a45a8ff 1203 /* Clear PVM4 exti pending bit */
bogdanm 0:9b334a45a8ff 1204 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
bogdanm 0:9b334a45a8ff 1205 }
bogdanm 0:9b334a45a8ff 1206 }
bogdanm 0:9b334a45a8ff 1207
bogdanm 0:9b334a45a8ff 1208
bogdanm 0:9b334a45a8ff 1209 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
bogdanm 0:9b334a45a8ff 1210 /**
bogdanm 0:9b334a45a8ff 1211 * @brief PWR PVM1 interrupt callback
bogdanm 0:9b334a45a8ff 1212 * @retval None
bogdanm 0:9b334a45a8ff 1213 */
bogdanm 0:9b334a45a8ff 1214 __weak void HAL_PWREx_PVM1Callback(void)
bogdanm 0:9b334a45a8ff 1215 {
bogdanm 0:9b334a45a8ff 1216 /* NOTE : This function should not be modified; when the callback is needed,
bogdanm 0:9b334a45a8ff 1217 HAL_PWREx_PVM1Callback() API can be implemented in the user file
bogdanm 0:9b334a45a8ff 1218 */
bogdanm 0:9b334a45a8ff 1219 }
bogdanm 0:9b334a45a8ff 1220 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
bogdanm 0:9b334a45a8ff 1221
bogdanm 0:9b334a45a8ff 1222 /**
bogdanm 0:9b334a45a8ff 1223 * @brief PWR PVM2 interrupt callback
bogdanm 0:9b334a45a8ff 1224 * @retval None
bogdanm 0:9b334a45a8ff 1225 */
bogdanm 0:9b334a45a8ff 1226 __weak void HAL_PWREx_PVM2Callback(void)
bogdanm 0:9b334a45a8ff 1227 {
bogdanm 0:9b334a45a8ff 1228 /* NOTE : This function should not be modified; when the callback is needed,
bogdanm 0:9b334a45a8ff 1229 HAL_PWREx_PVM2Callback() API can be implemented in the user file
bogdanm 0:9b334a45a8ff 1230 */
bogdanm 0:9b334a45a8ff 1231 }
bogdanm 0:9b334a45a8ff 1232
bogdanm 0:9b334a45a8ff 1233 /**
bogdanm 0:9b334a45a8ff 1234 * @brief PWR PVM3 interrupt callback
bogdanm 0:9b334a45a8ff 1235 * @retval None
bogdanm 0:9b334a45a8ff 1236 */
bogdanm 0:9b334a45a8ff 1237 __weak void HAL_PWREx_PVM3Callback(void)
bogdanm 0:9b334a45a8ff 1238 {
bogdanm 0:9b334a45a8ff 1239 /* NOTE : This function should not be modified; when the callback is needed,
bogdanm 0:9b334a45a8ff 1240 HAL_PWREx_PVM3Callback() API can be implemented in the user file
bogdanm 0:9b334a45a8ff 1241 */
bogdanm 0:9b334a45a8ff 1242 }
bogdanm 0:9b334a45a8ff 1243
bogdanm 0:9b334a45a8ff 1244 /**
bogdanm 0:9b334a45a8ff 1245 * @brief PWR PVM4 interrupt callback
bogdanm 0:9b334a45a8ff 1246 * @retval None
bogdanm 0:9b334a45a8ff 1247 */
bogdanm 0:9b334a45a8ff 1248 __weak void HAL_PWREx_PVM4Callback(void)
bogdanm 0:9b334a45a8ff 1249 {
bogdanm 0:9b334a45a8ff 1250 /* NOTE : This function should not be modified; when the callback is needed,
bogdanm 0:9b334a45a8ff 1251 HAL_PWREx_PVM4Callback() API can be implemented in the user file
bogdanm 0:9b334a45a8ff 1252 */
bogdanm 0:9b334a45a8ff 1253 }
bogdanm 0:9b334a45a8ff 1254
bogdanm 0:9b334a45a8ff 1255
bogdanm 0:9b334a45a8ff 1256 /**
bogdanm 0:9b334a45a8ff 1257 * @}
bogdanm 0:9b334a45a8ff 1258 */
bogdanm 0:9b334a45a8ff 1259
bogdanm 0:9b334a45a8ff 1260 /**
bogdanm 0:9b334a45a8ff 1261 * @}
bogdanm 0:9b334a45a8ff 1262 */
bogdanm 0:9b334a45a8ff 1263
bogdanm 0:9b334a45a8ff 1264 #endif /* HAL_PWR_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1265 /**
bogdanm 0:9b334a45a8ff 1266 * @}
bogdanm 0:9b334a45a8ff 1267 */
bogdanm 0:9b334a45a8ff 1268
bogdanm 0:9b334a45a8ff 1269 /**
bogdanm 0:9b334a45a8ff 1270 * @}
bogdanm 0:9b334a45a8ff 1271 */
bogdanm 0:9b334a45a8ff 1272
bogdanm 0:9b334a45a8ff 1273 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/