mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_adc_ex.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l4xx_hal_adc_ex.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of ADC HAL extended module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32L4xx_ADC_EX_H
bogdanm	0:9b334a45a8ff	40	#define __STM32L4xx_ADC_EX_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32l4xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32L4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup ADCEx ADCEx
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62	/**
bogdanm	0:9b334a45a8ff	63	* @brief ADC Injected Conversion Oversampling structure definition
bogdanm	0:9b334a45a8ff	64	*/
bogdanm	0:9b334a45a8ff	65	typedef struct
bogdanm	0:9b334a45a8ff	66	{
bogdanm	0:9b334a45a8ff	67	uint32_t Ratio; /*!< Configures the oversampling ratio.
bogdanm	0:9b334a45a8ff	68	This parameter can be a value of @ref ADCEx_Oversampling_Ratio */
bogdanm	0:9b334a45a8ff	69
bogdanm	0:9b334a45a8ff	70	uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
bogdanm	0:9b334a45a8ff	71	This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
bogdanm	0:9b334a45a8ff	72	}ADC_InjOversamplingTypeDef;
bogdanm	0:9b334a45a8ff	73
bogdanm	0:9b334a45a8ff	74
bogdanm	0:9b334a45a8ff	75
bogdanm	0:9b334a45a8ff	76	/**
bogdanm	0:9b334a45a8ff	77	* @brief Structure definition of ADC injected group and ADC channel for injected group
bogdanm	0:9b334a45a8ff	78	* @note Parameters of this structure are shared within 2 scopes:
bogdanm	0:9b334a45a8ff	79	* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
bogdanm	0:9b334a45a8ff	80	* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
bogdanm	0:9b334a45a8ff	81	* AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv, InjecOversamplingMode, InjecOversampling.
bogdanm	0:9b334a45a8ff	82	* @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned by ADC state.
bogdanm	0:9b334a45a8ff	83	* ADC state can be either:
bogdanm	0:9b334a45a8ff	84	* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
bogdanm	0:9b334a45a8ff	85	* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
bogdanm	0:9b334a45a8ff	86	* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
bogdanm	0:9b334a45a8ff	87	* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
bogdanm	0:9b334a45a8ff	88	* on regular and injected groups.
bogdanm	0:9b334a45a8ff	89	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
bogdanm	0:9b334a45a8ff	90	* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
bogdanm	0:9b334a45a8ff	91	*/
bogdanm	0:9b334a45a8ff	92	typedef struct
bogdanm	0:9b334a45a8ff	93	{
bogdanm	0:9b334a45a8ff	94	uint32_t InjectedChannel; /*!< Configure the ADC injected channel.
bogdanm	0:9b334a45a8ff	95	This parameter can be a value of @ref ADC_channels
bogdanm	0:9b334a45a8ff	96	Note: Depending on devices and ADC instances, some channels may not be available. Refer to device DataSheet for channels availability. */
bogdanm	0:9b334a45a8ff	97	uint32_t InjectedRank; /*!< The rank in the injected group sequencer.
bogdanm	0:9b334a45a8ff	98	This parameter must be a value of @ref ADCEx_injected_rank.
bogdanm	0:9b334a45a8ff	99	Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
bogdanm	0:9b334a45a8ff	100	the new channel setting (or parameter number of conversions adjusted). */
bogdanm	0:9b334a45a8ff	101	uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
bogdanm	0:9b334a45a8ff	102	Unit: ADC clock cycles.
bogdanm	0:9b334a45a8ff	103	Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
bogdanm	0:9b334a45a8ff	104	8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
bogdanm	0:9b334a45a8ff	105	This parameter can be a value of @ref ADC_sampling_times.
bogdanm	0:9b334a45a8ff	106	Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
bogdanm	0:9b334a45a8ff	107	It overwrites the last setting.
bogdanm	0:9b334a45a8ff	108	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
bogdanm	0:9b334a45a8ff	109	sampling time constraints must be respected (sampling time can be adjusted with respect to the ADC clock frequency and sampling time
bogdanm	0:9b334a45a8ff	110	setting). Refer to device DataSheet for timings values. */
bogdanm	0:9b334a45a8ff	111	uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
bogdanm	0:9b334a45a8ff	112	In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
bogdanm	0:9b334a45a8ff	113	Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
bogdanm	0:9b334a45a8ff	114	This parameter must be a value of @ref ADCEx_SingleDifferential.
bogdanm	0:9b334a45a8ff	115	Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
bogdanm	0:9b334a45a8ff	116	It overwrites the last setting.
bogdanm	0:9b334a45a8ff	117	Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
bogdanm	0:9b334a45a8ff	118	Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
bogdanm	0:9b334a45a8ff	119	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
bogdanm	0:9b334a45a8ff	120	If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case
bogdanm	0:9b334a45a8ff	121	of another parameter update on the fly) */
bogdanm	0:9b334a45a8ff	122	uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
bogdanm	0:9b334a45a8ff	123	This parameter can be a value of @ref ADCEx_OffsetNumber.
bogdanm	0:9b334a45a8ff	124	Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
bogdanm	0:9b334a45a8ff	125	uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
bogdanm	0:9b334a45a8ff	126	Offset value must be a positive number.
bogdanm	0:9b334a45a8ff	127	Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
bogdanm	0:9b334a45a8ff	128	0x3FF, 0xFF or 0x3F respectively.
bogdanm	0:9b334a45a8ff	129	Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
bogdanm	0:9b334a45a8ff	130	without continuous mode or external trigger that could launch a conversion). */
bogdanm	0:9b334a45a8ff	131	uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
bogdanm	0:9b334a45a8ff	132	To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
bogdanm	0:9b334a45a8ff	133	This parameter must be a number between Min_Data = 1 and Max_Data = 4.
bogdanm	0:9b334a45a8ff	134	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
bogdanm	0:9b334a45a8ff	135	configure a channel on injected group can impact the configuration of other channels previously set. */
bogdanm	0:9b334a45a8ff	136	uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence
bogdanm	0:9b334a45a8ff	137	subdivided in successive parts).
bogdanm	0:9b334a45a8ff	138	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
bogdanm	0:9b334a45a8ff	139	Discontinuous mode can be enabled only if continuous mode is disabled.
bogdanm	0:9b334a45a8ff	140	This parameter can be set to ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	141	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
bogdanm	0:9b334a45a8ff	142	Note: For injected group, discontinuous mode converts the sequence channel by channel (only one channel at a time).
bogdanm	0:9b334a45a8ff	143	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
bogdanm	0:9b334a45a8ff	144	configure a channel on injected group can impact the configuration of other channels previously set. */
bogdanm	0:9b334a45a8ff	145	uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
bogdanm	0:9b334a45a8ff	146	This parameter can be set to ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	147	Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
bogdanm	0:9b334a45a8ff	148	Note: To use Automatic injected conversion, injected group external triggers must be disabled.
bogdanm	0:9b334a45a8ff	149	Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
bogdanm	0:9b334a45a8ff	150	To maintain JAUTO always enabled, DMA must be configured in circular mode.
bogdanm	0:9b334a45a8ff	151	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
bogdanm	0:9b334a45a8ff	152	configure a channel on injected group can impact the configuration of other channels previously set. */
bogdanm	0:9b334a45a8ff	153	uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
bogdanm	0:9b334a45a8ff	154	This parameter can be set to ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	155	If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
bogdanm	0:9b334a45a8ff	156	new injected context is set when queue is full, error is triggered by interruption and through function
bogdanm	0:9b334a45a8ff	157	'HAL_ADCEx_InjectedQueueOverflowCallback'.
bogdanm	0:9b334a45a8ff	158	Caution: This feature request that the sequence is fully configured before injected conversion start.
bogdanm	0:9b334a45a8ff	159	Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
bogdanm	0:9b334a45a8ff	160	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
bogdanm	0:9b334a45a8ff	161	configure a channel on injected group can impact the configuration of other channels previously set.
bogdanm	0:9b334a45a8ff	162	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
bogdanm	0:9b334a45a8ff	163	uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
bogdanm	0:9b334a45a8ff	164	If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
bogdanm	0:9b334a45a8ff	165	This parameter can be a value of @ref ADCEx_Injected_External_Trigger_Source.
bogdanm	0:9b334a45a8ff	166	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
bogdanm	0:9b334a45a8ff	167	configure a channel on injected group can impact the configuration of other channels previously set. */
bogdanm	0:9b334a45a8ff	168	uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
bogdanm	0:9b334a45a8ff	169	This parameter can be a value of @ref ADCEx_Injected_External_Trigger_Source_Edge.
bogdanm	0:9b334a45a8ff	170	If trigger edge is set to ADC_EXTERNALTRIGINJECCONV_EDGE_NONE, external triggers are disabled and software trigger is used instead.
bogdanm	0:9b334a45a8ff	171	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
bogdanm	0:9b334a45a8ff	172	configure a channel on injected group can impact the configuration of other channels previously set. */
bogdanm	0:9b334a45a8ff	173
bogdanm	0:9b334a45a8ff	174	uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
bogdanm	0:9b334a45a8ff	175	This parameter can be set to ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	176	Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
bogdanm	0:9b334a45a8ff	177
bogdanm	0:9b334a45a8ff	178	ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
bogdanm	0:9b334a45a8ff	179	Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
bogdanm	0:9b334a45a8ff	180	Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
bogdanm	0:9b334a45a8ff	181	}ADC_InjectionConfTypeDef;
bogdanm	0:9b334a45a8ff	182
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	/**
bogdanm	0:9b334a45a8ff	185	* @brief Structure definition of ADC multimode
bogdanm	0:9b334a45a8ff	186	* @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
bogdanm	0:9b334a45a8ff	187	* Both Master and Slave ADCs must be disabled.
bogdanm	0:9b334a45a8ff	188	*/
bogdanm	0:9b334a45a8ff	189	typedef struct
bogdanm	0:9b334a45a8ff	190	{
bogdanm	0:9b334a45a8ff	191	uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode.
bogdanm	0:9b334a45a8ff	192	This parameter can be a value of @ref ADCEx_Common_mode. */
bogdanm	0:9b334a45a8ff	193	uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC:
bogdanm	0:9b334a45a8ff	194	selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
bogdanm	0:9b334a45a8ff	195	This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode. */
bogdanm	0:9b334a45a8ff	196	uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
bogdanm	0:9b334a45a8ff	197	This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases.
bogdanm	0:9b334a45a8ff	198	Delay range depends on selected resolution:
bogdanm	0:9b334a45a8ff	199	from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
bogdanm	0:9b334a45a8ff	200	from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */
bogdanm	0:9b334a45a8ff	201	}ADC_MultiModeTypeDef;
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	/**
bogdanm	0:9b334a45a8ff	204	* @}
bogdanm	0:9b334a45a8ff	205	*/
bogdanm	0:9b334a45a8ff	206
bogdanm	0:9b334a45a8ff	207	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209	/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
bogdanm	0:9b334a45a8ff	210	* @{
bogdanm	0:9b334a45a8ff	211	*/
bogdanm	0:9b334a45a8ff	212
bogdanm	0:9b334a45a8ff	213	/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
bogdanm	0:9b334a45a8ff	214	* @{
bogdanm	0:9b334a45a8ff	215	*/
bogdanm	0:9b334a45a8ff	216	#define ADC_SINGLE_ENDED ((uint32_t)0x00000000) /!< ADC channel set in single-ended input mode /
bogdanm	0:9b334a45a8ff	217	#define ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF) /!< ADC channel set in differential mode /
bogdanm	0:9b334a45a8ff	218	/**
bogdanm	0:9b334a45a8ff	219	* @}
bogdanm	0:9b334a45a8ff	220	*/
bogdanm	0:9b334a45a8ff	221
bogdanm	0:9b334a45a8ff	222	/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
bogdanm	0:9b334a45a8ff	223	* @{
bogdanm	0:9b334a45a8ff	224	*/
bogdanm	0:9b334a45a8ff	225	#define ADC_OFFSET_NONE ((uint32_t)0x00) /!< No offset correction /
bogdanm	0:9b334a45a8ff	226	#define ADC_OFFSET_1 ((uint32_t)0x01) /!< Offset correction to apply to a first channel /
bogdanm	0:9b334a45a8ff	227	#define ADC_OFFSET_2 ((uint32_t)0x02) /!< Offset correction to apply to a second channel /
bogdanm	0:9b334a45a8ff	228	#define ADC_OFFSET_3 ((uint32_t)0x03) /!< Offset correction to apply to a third channel /
bogdanm	0:9b334a45a8ff	229	#define ADC_OFFSET_4 ((uint32_t)0x04) /!< Offset correction to apply to a fourth channel /
bogdanm	0:9b334a45a8ff	230	/**
bogdanm	0:9b334a45a8ff	231	* @}
bogdanm	0:9b334a45a8ff	232	*/
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	/** @defgroup ADCEx_regular_rank ADC Extended Regular Channel Rank
bogdanm	0:9b334a45a8ff	235	* @{
bogdanm	0:9b334a45a8ff	236	*/
bogdanm	0:9b334a45a8ff	237	#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /!< ADC regular conversion rank 1 /
bogdanm	0:9b334a45a8ff	238	#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /!< ADC regular conversion rank 2 /
bogdanm	0:9b334a45a8ff	239	#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /!< ADC regular conversion rank 3 /
bogdanm	0:9b334a45a8ff	240	#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /!< ADC regular conversion rank 4 /
bogdanm	0:9b334a45a8ff	241	#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /!< ADC regular conversion rank 5 /
bogdanm	0:9b334a45a8ff	242	#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /!< ADC regular conversion rank 6 /
bogdanm	0:9b334a45a8ff	243	#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /!< ADC regular conversion rank 7 /
bogdanm	0:9b334a45a8ff	244	#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /!< ADC regular conversion rank 8 /
bogdanm	0:9b334a45a8ff	245	#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /!< ADC regular conversion rank 9 /
bogdanm	0:9b334a45a8ff	246	#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /!< ADC regular conversion rank 10 /
bogdanm	0:9b334a45a8ff	247	#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /!< ADC regular conversion rank 11 /
bogdanm	0:9b334a45a8ff	248	#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /!< ADC regular conversion rank 12 /
bogdanm	0:9b334a45a8ff	249	#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /!< ADC regular conversion rank 13 /
bogdanm	0:9b334a45a8ff	250	#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /!< ADC regular conversion rank 14 /
bogdanm	0:9b334a45a8ff	251	#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /!< ADC regular conversion rank 15 /
bogdanm	0:9b334a45a8ff	252	#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /!< ADC regular conversion rank 16 /
bogdanm	0:9b334a45a8ff	253	/**
bogdanm	0:9b334a45a8ff	254	* @}
bogdanm	0:9b334a45a8ff	255	*/
bogdanm	0:9b334a45a8ff	256
bogdanm	0:9b334a45a8ff	257	/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
bogdanm	0:9b334a45a8ff	258	* @{
bogdanm	0:9b334a45a8ff	259	*/
bogdanm	0:9b334a45a8ff	260	#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /!< ADC injected conversion rank 1 /
bogdanm	0:9b334a45a8ff	261	#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /!< ADC injected conversion rank 2 /
bogdanm	0:9b334a45a8ff	262	#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /!< ADC injected conversion rank 3 /
bogdanm	0:9b334a45a8ff	263	#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /!< ADC injected conversion rank 4 /
bogdanm	0:9b334a45a8ff	264	/**injected
bogdanm	0:9b334a45a8ff	265	* @}
bogdanm	0:9b334a45a8ff	266	*/
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	/** @defgroup ADCEx_Injected_External_Trigger_Source_Edge ADC External Trigger Source Edge for Injected Group
bogdanm	0:9b334a45a8ff	269	* @{
bogdanm	0:9b334a45a8ff	270	*/
bogdanm	0:9b334a45a8ff	271	#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) /!< Injected conversions hardware trigger detection disabled /
bogdanm	0:9b334a45a8ff	272	#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0) /!< Injected conversions hardware trigger detection on the rising edge /
bogdanm	0:9b334a45a8ff	273	#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1) /!< Injected conversions hardware trigger detection on the falling edge /
bogdanm	0:9b334a45a8ff	274	#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN) /!< Injected conversions hardware trigger detection on both the rising and falling edges /
bogdanm	0:9b334a45a8ff	275	/**
bogdanm	0:9b334a45a8ff	276	* @}
bogdanm	0:9b334a45a8ff	277	*/
bogdanm	0:9b334a45a8ff	278
bogdanm	0:9b334a45a8ff	279	/** @defgroup ADCEx_Injected_External_Trigger_Source ADC Extended External Trigger Source for Injected Group
bogdanm	0:9b334a45a8ff	280	* @{
bogdanm	0:9b334a45a8ff	281	*/
bogdanm	0:9b334a45a8ff	282	#define ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) /!< Event 0 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	283	#define ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) /!< Event 1 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	284	#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) /!< Event 2 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	285	#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0)) /!< Event 3 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	286	#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) /!< Event 4 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	287	#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0)) /!< Event 5 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	288	#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1)) /!< Event 6 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	289	#define ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0)) /!< Event 7 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	290	#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) /!< Event 8 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	291	#define ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_0)) /!< Event 9 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	292	#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1)) /!< Event 10 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	293	#define ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0)) /!< Event 11 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	294	#define ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2)) /!< Event 12 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	295	#define ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0)) /!< Event 13 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	296	#define ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1)) /!< Event 14 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	297	#define ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) /!< Event 15 triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	298
bogdanm	0:9b334a45a8ff	299	#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) /!< Software triggers injected group conversion start /
bogdanm	0:9b334a45a8ff	300	/**
bogdanm	0:9b334a45a8ff	301	* @}
bogdanm	0:9b334a45a8ff	302	*/
bogdanm	0:9b334a45a8ff	303
bogdanm	0:9b334a45a8ff	304	/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
bogdanm	0:9b334a45a8ff	305	* @{
bogdanm	0:9b334a45a8ff	306	*/
bogdanm	0:9b334a45a8ff	307	#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /!< Independent ADC conversions mode /
bogdanm	0:9b334a45a8ff	308	#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0)) /!< Combined regular simultaneous + injected simultaneous mode /
bogdanm	0:9b334a45a8ff	309	#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1)) /!< Combined regular simultaneous + alternate trigger mode /
bogdanm	0:9b334a45a8ff	310	#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 \| ADC_CCR_DUAL_0)) /!< Combined Interleaved mode + injected simultaneous mode /
bogdanm	0:9b334a45a8ff	311	#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_0)) /!< Injected simultaneous mode only /
bogdanm	0:9b334a45a8ff	312	#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_1)) /!< Regular simultaneous mode only /
bogdanm	0:9b334a45a8ff	313	#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_1 \| ADC_CCR_DUAL_0)) /!< Interleaved mode only /
bogdanm	0:9b334a45a8ff	314	#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 \| ADC_CCR_DUAL_0)) /!< Alternate trigger mode only /
bogdanm	0:9b334a45a8ff	315	/**
bogdanm	0:9b334a45a8ff	316	* @}
bogdanm	0:9b334a45a8ff	317	*/
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320	/** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode
bogdanm	0:9b334a45a8ff	321	* @{
bogdanm	0:9b334a45a8ff	322	*/
bogdanm	0:9b334a45a8ff	323	#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /!< DMA multimode disabled: each ADC uses its own DMA channel /
bogdanm	0:9b334a45a8ff	324	#define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC_CCR_MDMA_1) /!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution /
bogdanm	0:9b334a45a8ff	325	#define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC_CCR_MDMA) /!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution /
bogdanm	0:9b334a45a8ff	326	/**
bogdanm	0:9b334a45a8ff	327	* @}
bogdanm	0:9b334a45a8ff	328	*/
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases
bogdanm	0:9b334a45a8ff	331	* @{
bogdanm	0:9b334a45a8ff	332	*/
bogdanm	0:9b334a45a8ff	333	#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000)) /!< 1 ADC clock cycle delay /
bogdanm	0:9b334a45a8ff	334	#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0)) /!< 2 ADC clock cycles delay /
bogdanm	0:9b334a45a8ff	335	#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1)) /!< 3 ADC clock cycles delay /
bogdanm	0:9b334a45a8ff	336	#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)) /!< 4 ADC clock cycles delay /
bogdanm	0:9b334a45a8ff	337	#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2)) /!< 5 ADC clock cycles delay /
bogdanm	0:9b334a45a8ff	338	#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0)) /!< 6 ADC clock cycles delay /
bogdanm	0:9b334a45a8ff	339	#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1)) /!< 7 ADC clock cycles delay (lower for non 12-bit resolution) /
bogdanm	0:9b334a45a8ff	340	#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)) /!< 8 ADC clock cycles delay (lower for non 12-bit resolution) /
bogdanm	0:9b334a45a8ff	341	#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3)) /!< 9 ADC clock cycles delay (lower for non 12-bit resolution) /
bogdanm	0:9b334a45a8ff	342	#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_0)) /!< 10 ADC clock cycles delay (lower for non 12-bit resolution) /
bogdanm	0:9b334a45a8ff	343	#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1)) /!< 11 ADC clock cycles delay (lower for non 12-bit resolution) /
bogdanm	0:9b334a45a8ff	344	#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)) /!< 12 ADC clock cycles delay (lower for non 12-bit resolution) /
bogdanm	0:9b334a45a8ff	345	/**
bogdanm	0:9b334a45a8ff	346	* @}
bogdanm	0:9b334a45a8ff	347	*/
bogdanm	0:9b334a45a8ff	348
bogdanm	0:9b334a45a8ff	349	/** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
bogdanm	0:9b334a45a8ff	350	* @{
bogdanm	0:9b334a45a8ff	351	*/
bogdanm	0:9b334a45a8ff	352	#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001) /!< Analog watchdog 1 selection /
bogdanm	0:9b334a45a8ff	353	#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002) /!< Analog watchdog 2 selection /
bogdanm	0:9b334a45a8ff	354	#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003) /!< Analog watchdog 3 selection /
bogdanm	0:9b334a45a8ff	355	/**
bogdanm	0:9b334a45a8ff	356	* @}
bogdanm	0:9b334a45a8ff	357	*/
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	/** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
bogdanm	0:9b334a45a8ff	360	* @{
bogdanm	0:9b334a45a8ff	361	*/
bogdanm	0:9b334a45a8ff	362	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) /!< No analog watchdog selected /
bogdanm	0:9b334a45a8ff	363	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_AWD1EN)) /!< Analog watchdog applied to a regular group single channel /
bogdanm	0:9b334a45a8ff	364	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_JAWD1EN)) /!< Analog watchdog applied to an injected group single channel /
bogdanm	0:9b334a45a8ff	365	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_AWD1EN \| ADC_CFGR_JAWD1EN)) /!< Analog watchdog applied to a regular and injected groups single channel /
bogdanm	0:9b334a45a8ff	366	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN) /!< Analog watchdog applied to regular group all channels /
bogdanm	0:9b334a45a8ff	367	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN) /!< Analog watchdog applied to injected group all channels /
bogdanm	0:9b334a45a8ff	368	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN \| ADC_CFGR_JAWD1EN)) /!< Analog watchdog applied to regular and injected groups all channels /
bogdanm	0:9b334a45a8ff	369	/**
bogdanm	0:9b334a45a8ff	370	* @}
bogdanm	0:9b334a45a8ff	371	*/
bogdanm	0:9b334a45a8ff	372
bogdanm	0:9b334a45a8ff	373	/** @defgroup ADCEx_conversion_group ADC Extended Conversion Group
bogdanm	0:9b334a45a8ff	374	* @{
bogdanm	0:9b334a45a8ff	375	*/
bogdanm	0:9b334a45a8ff	376	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_EOS)) /!< ADC regular group selection /
bogdanm	0:9b334a45a8ff	377	#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC \| ADC_FLAG_JEOS)) /!< ADC injected group selection /
bogdanm	0:9b334a45a8ff	378	#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_JEOC \| ADC_FLAG_JEOS)) /!< ADC regular and injected groups selection /
bogdanm	0:9b334a45a8ff	379	/**
bogdanm	0:9b334a45a8ff	380	* @}
bogdanm	0:9b334a45a8ff	381	*/
bogdanm	0:9b334a45a8ff	382
bogdanm	0:9b334a45a8ff	383	/** @defgroup ADCEx_Event_type ADC Extended Event Type
bogdanm	0:9b334a45a8ff	384	* @{
bogdanm	0:9b334a45a8ff	385	*/
bogdanm	0:9b334a45a8ff	386	#define ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP) /!< ADC End of Sampling event /
bogdanm	0:9b334a45a8ff	387	#define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /!< ADC Analog watchdog 1 event (main analog watchdog) /
bogdanm	0:9b334a45a8ff	388	#define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /!< ADC Analog watchdog 2 event (additional analog watchdog) /
bogdanm	0:9b334a45a8ff	389	#define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /!< ADC Analog watchdog 3 event (additional analog watchdog) /
bogdanm	0:9b334a45a8ff	390	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /!< ADC overrun event /
bogdanm	0:9b334a45a8ff	391	#define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /!< ADC Injected Context Queue Overflow event /
bogdanm	0:9b334a45a8ff	392
bogdanm	0:9b334a45a8ff	393	#define ADC_AWD_EVENT ADC_AWD1_EVENT /!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog /
bogdanm	0:9b334a45a8ff	394	/**
bogdanm	0:9b334a45a8ff	395	* @}
bogdanm	0:9b334a45a8ff	396	*/
bogdanm	0:9b334a45a8ff	397
bogdanm	0:9b334a45a8ff	398	/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
bogdanm	0:9b334a45a8ff	399	* @{
bogdanm	0:9b334a45a8ff	400	*/
bogdanm	0:9b334a45a8ff	401	#define ADC_IT_RDY ADC_IER_ADRDY /!< ADC Ready (ADRDY) interrupt source /
bogdanm	0:9b334a45a8ff	402	#define ADC_IT_EOSMP ADC_IER_EOSMP /!< ADC End of sampling interrupt source /
bogdanm	0:9b334a45a8ff	403	#define ADC_IT_EOC ADC_IER_EOC /!< ADC End of regular conversion interrupt source /
bogdanm	0:9b334a45a8ff	404	#define ADC_IT_EOS ADC_IER_EOS /!< ADC End of regular sequence of conversions interrupt source /
bogdanm	0:9b334a45a8ff	405	#define ADC_IT_OVR ADC_IER_OVR /!< ADC overrun interrupt source /
bogdanm	0:9b334a45a8ff	406	#define ADC_IT_JEOC ADC_IER_JEOC /!< ADC End of injected conversion interrupt source /
bogdanm	0:9b334a45a8ff	407	#define ADC_IT_JEOS ADC_IER_JEOS /!< ADC End of injected sequence of conversions interrupt source /
bogdanm	0:9b334a45a8ff	408	#define ADC_IT_AWD1 ADC_IER_AWD1 /!< ADC Analog watchdog 1 interrupt source (main analog watchdog) /
bogdanm	0:9b334a45a8ff	409	#define ADC_IT_AWD2 ADC_IER_AWD2 /!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) /
bogdanm	0:9b334a45a8ff	410	#define ADC_IT_AWD3 ADC_IER_AWD3 /!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) /
bogdanm	0:9b334a45a8ff	411	#define ADC_IT_JQOVF ADC_IER_JQOVF /!< ADC Injected Context Queue Overflow interrupt source /
bogdanm	0:9b334a45a8ff	412
bogdanm	0:9b334a45a8ff	413	#define ADC_IT_AWD ADC_IT_AWD1 /!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog /
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	/**
bogdanm	0:9b334a45a8ff	416	* @}
bogdanm	0:9b334a45a8ff	417	*/
bogdanm	0:9b334a45a8ff	418
bogdanm	0:9b334a45a8ff	419	/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
bogdanm	0:9b334a45a8ff	420	* @{
bogdanm	0:9b334a45a8ff	421	*/
bogdanm	0:9b334a45a8ff	422	#define ADC_FLAG_RDY ADC_ISR_ADRDY /!< ADC Ready (ADRDY) flag /
bogdanm	0:9b334a45a8ff	423	#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC End of Sampling flag /
bogdanm	0:9b334a45a8ff	424	#define ADC_FLAG_EOC ADC_ISR_EOC /!< ADC End of Regular Conversion flag /
bogdanm	0:9b334a45a8ff	425	#define ADC_FLAG_EOS ADC_ISR_EOS /!< ADC End of Regular sequence of Conversions flag /
bogdanm	0:9b334a45a8ff	426	#define ADC_FLAG_OVR ADC_ISR_OVR /!< ADC overrun flag /
bogdanm	0:9b334a45a8ff	427	#define ADC_FLAG_JEOC ADC_ISR_JEOC /!< ADC End of Injected Conversion flag /
bogdanm	0:9b334a45a8ff	428	#define ADC_FLAG_JEOS ADC_ISR_JEOS /!< ADC End of Injected sequence of Conversions flag /
bogdanm	0:9b334a45a8ff	429	#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /!< ADC Analog watchdog 1 flag (main analog watchdog) /
bogdanm	0:9b334a45a8ff	430	#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /!< ADC Analog watchdog 2 flag (additional analog watchdog) /
bogdanm	0:9b334a45a8ff	431	#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /!< ADC Analog watchdog 3 flag (additional analog watchdog) /
bogdanm	0:9b334a45a8ff	432	#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /!< ADC Injected Context Queue Overflow flag /
bogdanm	0:9b334a45a8ff	433
bogdanm	0:9b334a45a8ff	434	#define ADC_FLAG_AWD ADC_FLAG_AWD1 /!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog /
bogdanm	0:9b334a45a8ff	435
bogdanm	0:9b334a45a8ff	436	#define ADC_FLAG_ALL (ADC_FLAG_RDY \| ADC_FLAG_EOSMP \| ADC_FLAG_EOC \| ADC_FLAG_EOS \| \
bogdanm	0:9b334a45a8ff	437	ADC_FLAG_JEOC \| ADC_FLAG_JEOS \| ADC_FLAG_OVR \| ADC_FLAG_AWD1 \| \
bogdanm	0:9b334a45a8ff	438	ADC_FLAG_AWD2 \| ADC_FLAG_AWD3 \| ADC_FLAG_JQOVF) /!< ADC all flags /
bogdanm	0:9b334a45a8ff	439
bogdanm	0:9b334a45a8ff	440	/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */
bogdanm	0:9b334a45a8ff	441	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_JEOC \| ADC_FLAG_JEOS \| \
bogdanm	0:9b334a45a8ff	442	ADC_FLAG_OVR \| ADC_FLAG_AWD1 \| ADC_FLAG_AWD2 \| ADC_FLAG_AWD3 \| \
bogdanm	0:9b334a45a8ff	443	ADC_FLAG_JQOVF) /!< ADC post-conversion all flags /
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	/**
bogdanm	0:9b334a45a8ff	446	* @}
bogdanm	0:9b334a45a8ff	447	*/
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
bogdanm	0:9b334a45a8ff	451	* @{
bogdanm	0:9b334a45a8ff	452	*/
bogdanm	0:9b334a45a8ff	453	#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /!< ADC injected conversion rank 1 /
bogdanm	0:9b334a45a8ff	454	#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /!< ADC injected conversion rank 2 /
bogdanm	0:9b334a45a8ff	455	#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /!< ADC injected conversion rank 3 /
bogdanm	0:9b334a45a8ff	456	#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /!< ADC injected conversion rank 4 /
bogdanm	0:9b334a45a8ff	457	/**
bogdanm	0:9b334a45a8ff	458	* @}
bogdanm	0:9b334a45a8ff	459	*/
bogdanm	0:9b334a45a8ff	460
bogdanm	0:9b334a45a8ff	461
bogdanm	0:9b334a45a8ff	462
bogdanm	0:9b334a45a8ff	463	/** @defgroup ADCEx_Oversampling_Ratio ADC Extended Oversampling Ratio
bogdanm	0:9b334a45a8ff	464	* @{
bogdanm	0:9b334a45a8ff	465	*/
bogdanm	0:9b334a45a8ff	466
bogdanm	0:9b334a45a8ff	467	#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /!< ADC Oversampling ratio 2x /
bogdanm	0:9b334a45a8ff	468	#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)ADC_CFGR2_OVSR_0) /!< ADC Oversampling ratio 4x /
bogdanm	0:9b334a45a8ff	469	#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)ADC_CFGR2_OVSR_1) /!< ADC Oversampling ratio 8x /
bogdanm	0:9b334a45a8ff	470	#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)(ADC_CFGR2_OVSR_1 \| ADC_CFGR2_OVSR_0)) /!< ADC Oversampling ratio 16x /
bogdanm	0:9b334a45a8ff	471	#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)ADC_CFGR2_OVSR_2) /!< ADC Oversampling ratio 32x /
bogdanm	0:9b334a45a8ff	472	#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)(ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_0)) /!< ADC Oversampling ratio 64x /
bogdanm	0:9b334a45a8ff	473	#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)(ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_1)) /!< ADC Oversampling ratio 128x /
bogdanm	0:9b334a45a8ff	474	#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)(ADC_CFGR2_OVSR)) /!< ADC Oversampling ratio 256x /
bogdanm	0:9b334a45a8ff	475	/**
bogdanm	0:9b334a45a8ff	476	* @}
bogdanm	0:9b334a45a8ff	477	*/
bogdanm	0:9b334a45a8ff	478
bogdanm	0:9b334a45a8ff	479	/** @defgroup ADCEx_Right_Bit_Shift ADC Extended Oversampling Right Shift
bogdanm	0:9b334a45a8ff	480	* @{
bogdanm	0:9b334a45a8ff	481	*/
bogdanm	0:9b334a45a8ff	482	#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /!< ADC No bit shift for oversampling /
bogdanm	0:9b334a45a8ff	483	#define ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0) /!< ADC 1 bit shift for oversampling /
bogdanm	0:9b334a45a8ff	484	#define ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1) /!< ADC 2 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	485	#define ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 \| ADC_CFGR2_OVSS_0)) /!< ADC 3 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	486	#define ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2) /!< ADC 4 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	487	#define ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_0)) /!< ADC 5 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	488	#define ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_1)) /!< ADC 6 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	489	#define ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_1 \| ADC_CFGR2_OVSS_0)) /!< ADC 7 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	490	#define ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3) /!< ADC 8 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	491	/**
bogdanm	0:9b334a45a8ff	492	* @}
bogdanm	0:9b334a45a8ff	493	*/
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	/** @defgroup ADCEx_Triggered_Oversampling_Mode ADC Extended Triggered Regular Oversampling
bogdanm	0:9b334a45a8ff	496	* @{
bogdanm	0:9b334a45a8ff	497	*/
bogdanm	0:9b334a45a8ff	498	#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /!< A single trigger for all channel oversampled conversions /
bogdanm	0:9b334a45a8ff	499	#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS) /!< A trigger for each oversampled conversion /
bogdanm	0:9b334a45a8ff	500	/**
bogdanm	0:9b334a45a8ff	501	* @}
bogdanm	0:9b334a45a8ff	502	*/
bogdanm	0:9b334a45a8ff	503
bogdanm	0:9b334a45a8ff	504	/** @defgroup ADCEx_Regular_Oversampling_Mode ADC Extended Regular Oversampling Continued or Resumed Mode
bogdanm	0:9b334a45a8ff	505	* @{
bogdanm	0:9b334a45a8ff	506	*/
bogdanm	0:9b334a45a8ff	507	#define ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000) /!< Oversampling buffer maintained during injection sequence /
bogdanm	0:9b334a45a8ff	508	#define ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM) /!< Oversampling buffer zeroed during injection sequence /
bogdanm	0:9b334a45a8ff	509	/**
bogdanm	0:9b334a45a8ff	510	* @}
bogdanm	0:9b334a45a8ff	511	*/
bogdanm	0:9b334a45a8ff	512
bogdanm	0:9b334a45a8ff	513	/**
bogdanm	0:9b334a45a8ff	514	* @}
bogdanm	0:9b334a45a8ff	515	*/
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518
bogdanm	0:9b334a45a8ff	519	/* Private macros -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
bogdanm	0:9b334a45a8ff	522	* @{
bogdanm	0:9b334a45a8ff	523	*/
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525	/**
bogdanm	0:9b334a45a8ff	526	* @brief Test if conversion trigger of injected group is software start
bogdanm	0:9b334a45a8ff	527	* or external trigger.
bogdanm	0:9b334a45a8ff	528	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	529	* @retval SET (software start) or RESET (external trigger).
bogdanm	0:9b334a45a8ff	530	*/
bogdanm	0:9b334a45a8ff	531	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
bogdanm	0:9b334a45a8ff	532	(((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
bogdanm	0:9b334a45a8ff	533
bogdanm	0:9b334a45a8ff	534	/**
bogdanm	0:9b334a45a8ff	535	* @brief Check if conversion is on going on regular or injected groups.
bogdanm	0:9b334a45a8ff	536	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	537	* @retval SET (conversion is on going) or RESET (no conversion is on going).
bogdanm	0:9b334a45a8ff	538	*/
bogdanm	0:9b334a45a8ff	539	#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
bogdanm	0:9b334a45a8ff	540	(( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART \| ADC_CR_JADSTART)) == RESET \
bogdanm	0:9b334a45a8ff	541	) ? RESET : SET)
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	/**
bogdanm	0:9b334a45a8ff	545	* @brief Check if conversion is on going on injected group.
bogdanm	0:9b334a45a8ff	546	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	547	* @retval SET (conversion is on going) or RESET (no conversion is on going).
bogdanm	0:9b334a45a8ff	548	*/
bogdanm	0:9b334a45a8ff	549	#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
bogdanm	0:9b334a45a8ff	550	(( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \
bogdanm	0:9b334a45a8ff	551	) ? RESET : SET)
bogdanm	0:9b334a45a8ff	552
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554	/**
bogdanm	0:9b334a45a8ff	555	* @brief Check whether or not ADC is independent.
bogdanm	0:9b334a45a8ff	556	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	557	* @retval SET (ADC is independent) or RESET (ADC is not).
bogdanm	0:9b334a45a8ff	558	*/
bogdanm	0:9b334a45a8ff	559	#define ADC_IS_INDEPENDENT(__HANDLE__) \
bogdanm	0:9b334a45a8ff	560	( ( ( ((__HANDLE__)->Instance) == ADC3) \
bogdanm	0:9b334a45a8ff	561	)? \
bogdanm	0:9b334a45a8ff	562	SET \
bogdanm	0:9b334a45a8ff	563	: \
bogdanm	0:9b334a45a8ff	564	RESET \
bogdanm	0:9b334a45a8ff	565	)
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567
bogdanm	0:9b334a45a8ff	568
bogdanm	0:9b334a45a8ff	569	/**
bogdanm	0:9b334a45a8ff	570	* @brief Set the sample time for Channels numbers between 0 and 9.
bogdanm	0:9b334a45a8ff	571	* @param __SAMPLETIME__: Sample time parameter.
bogdanm	0:9b334a45a8ff	572	* @param __CHANNELNB__: Channel number.
bogdanm	0:9b334a45a8ff	573	* @retval None
bogdanm	0:9b334a45a8ff	574	*/
bogdanm	0:9b334a45a8ff	575	#define ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))
bogdanm	0:9b334a45a8ff	576
bogdanm	0:9b334a45a8ff	577	/**
bogdanm	0:9b334a45a8ff	578	* @brief Set the sample time for Channels numbers between 10 and 18.
bogdanm	0:9b334a45a8ff	579	* @param __SAMPLETIME__: Sample time parameter.
bogdanm	0:9b334a45a8ff	580	* @param __CHANNELNB__: Channel number.
bogdanm	0:9b334a45a8ff	581	* @retval None
bogdanm	0:9b334a45a8ff	582	*/
bogdanm	0:9b334a45a8ff	583	#define ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))
bogdanm	0:9b334a45a8ff	584
bogdanm	0:9b334a45a8ff	585
bogdanm	0:9b334a45a8ff	586	/**
bogdanm	0:9b334a45a8ff	587	* @brief Set the selected regular Channel rank for rank between 1 and 4.
bogdanm	0:9b334a45a8ff	588	* @param __CHANNELNB__: Channel number.
bogdanm	0:9b334a45a8ff	589	* @param __RANKNB__: Rank number.
bogdanm	0:9b334a45a8ff	590	* @retval None
bogdanm	0:9b334a45a8ff	591	*/
bogdanm	0:9b334a45a8ff	592	#define ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))
bogdanm	0:9b334a45a8ff	593
bogdanm	0:9b334a45a8ff	594	/**
bogdanm	0:9b334a45a8ff	595	* @brief Set the selected regular Channel rank for rank between 5 and 9.
bogdanm	0:9b334a45a8ff	596	* @param __CHANNELNB__: Channel number.
bogdanm	0:9b334a45a8ff	597	* @param __RANKNB__: Rank number.
bogdanm	0:9b334a45a8ff	598	* @retval None
bogdanm	0:9b334a45a8ff	599	*/
bogdanm	0:9b334a45a8ff	600	#define ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	/**
bogdanm	0:9b334a45a8ff	603	* @brief Set the selected regular Channel rank for rank between 10 and 14.
bogdanm	0:9b334a45a8ff	604	* @param __CHANNELNB__: Channel number.
bogdanm	0:9b334a45a8ff	605	* @param __RANKNB__: Rank number.
bogdanm	0:9b334a45a8ff	606	* @retval None
bogdanm	0:9b334a45a8ff	607	*/
bogdanm	0:9b334a45a8ff	608	#define ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	/**
bogdanm	0:9b334a45a8ff	611	* @brief Set the selected regular Channel rank for rank between 15 and 16.
bogdanm	0:9b334a45a8ff	612	* @param __CHANNELNB__: Channel number.
bogdanm	0:9b334a45a8ff	613	* @param __RANKNB__: Rank number.
bogdanm	0:9b334a45a8ff	614	* @retval None
bogdanm	0:9b334a45a8ff	615	*/
bogdanm	0:9b334a45a8ff	616	#define ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))
bogdanm	0:9b334a45a8ff	617
bogdanm	0:9b334a45a8ff	618	/**
bogdanm	0:9b334a45a8ff	619	* @brief Set the selected injected Channel rank.
bogdanm	0:9b334a45a8ff	620	* @param __CHANNELNB__: Channel number.
bogdanm	0:9b334a45a8ff	621	* @param __RANKNB__: Rank number.
bogdanm	0:9b334a45a8ff	622	* @retval None
bogdanm	0:9b334a45a8ff	623	*/
bogdanm	0:9b334a45a8ff	624	#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-2) * (__RANKNB__) +2))
bogdanm	0:9b334a45a8ff	625
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	/**
bogdanm	0:9b334a45a8ff	628	* @brief Set the Analog Watchdog 1 channel.
bogdanm	0:9b334a45a8ff	629	* @param __CHANNEL__: channel to be monitored by Analog Watchdog 1.
bogdanm	0:9b334a45a8ff	630	* @retval None
bogdanm	0:9b334a45a8ff	631	*/
bogdanm	0:9b334a45a8ff	632	#define ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))
bogdanm	0:9b334a45a8ff	633
bogdanm	0:9b334a45a8ff	634	/**
bogdanm	0:9b334a45a8ff	635	* @brief Configure the channel number in Analog Watchdog 2 or 3.
bogdanm	0:9b334a45a8ff	636	* @param __CHANNEL__: ADC Channel
bogdanm	0:9b334a45a8ff	637	* @retval None
bogdanm	0:9b334a45a8ff	638	*/
bogdanm	0:9b334a45a8ff	639	#define ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__))
bogdanm	0:9b334a45a8ff	640
bogdanm	0:9b334a45a8ff	641	/**
bogdanm	0:9b334a45a8ff	642	* @brief Configure ADC injected context queue
bogdanm	0:9b334a45a8ff	643	* @param __INJECT_CONTEXT_QUEUE_MODE__: Injected context queue mode.
bogdanm	0:9b334a45a8ff	644	* @retval None
bogdanm	0:9b334a45a8ff	645	*/
bogdanm	0:9b334a45a8ff	646	#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	/**
bogdanm	0:9b334a45a8ff	649	* @brief Configure ADC discontinuous conversion mode for injected group
bogdanm	0:9b334a45a8ff	650	* @param __INJECT_DISCONTINUOUS_MODE__: Injected discontinuous mode.
bogdanm	0:9b334a45a8ff	651	* @retval None
bogdanm	0:9b334a45a8ff	652	*/
bogdanm	0:9b334a45a8ff	653	#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN))
bogdanm	0:9b334a45a8ff	654
bogdanm	0:9b334a45a8ff	655	/**
bogdanm	0:9b334a45a8ff	656	* @brief Configure ADC discontinuous conversion mode for regular group
bogdanm	0:9b334a45a8ff	657	* @param __REG_DISCONTINUOUS_MODE__: Regular discontinuous mode.
bogdanm	0:9b334a45a8ff	658	* @retval None
bogdanm	0:9b334a45a8ff	659	*/
bogdanm	0:9b334a45a8ff	660	#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))
bogdanm	0:9b334a45a8ff	661	/**
bogdanm	0:9b334a45a8ff	662	* @brief Configure the number of discontinuous conversions for regular group.
bogdanm	0:9b334a45a8ff	663	* @param __NBR_DISCONTINUOUS_CONV__: Number of discontinuous conversions.
bogdanm	0:9b334a45a8ff	664	* @retval None
bogdanm	0:9b334a45a8ff	665	*/
bogdanm	0:9b334a45a8ff	666	#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))
bogdanm	0:9b334a45a8ff	667
bogdanm	0:9b334a45a8ff	668	/**
bogdanm	0:9b334a45a8ff	669	* @brief Configure the ADC auto delay mode.
bogdanm	0:9b334a45a8ff	670	* @param __AUTOWAIT__: Auto delay bit enable or disable.
bogdanm	0:9b334a45a8ff	671	* @retval None
bogdanm	0:9b334a45a8ff	672	*/
bogdanm	0:9b334a45a8ff	673	#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))
bogdanm	0:9b334a45a8ff	674
bogdanm	0:9b334a45a8ff	675	/**
bogdanm	0:9b334a45a8ff	676	* @brief Configure ADC continuous conversion mode.
bogdanm	0:9b334a45a8ff	677	* @param __CONTINUOUS_MODE__: Continuous mode.
bogdanm	0:9b334a45a8ff	678	* @retval None
bogdanm	0:9b334a45a8ff	679	*/
bogdanm	0:9b334a45a8ff	680	#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682	/**
bogdanm	0:9b334a45a8ff	683	* @brief Configure the ADC DMA continuous request.
bogdanm	0:9b334a45a8ff	684	* @param __DMACONTREQ_MODE__: DMA continuous request mode.
bogdanm	0:9b334a45a8ff	685	* @retval None
bogdanm	0:9b334a45a8ff	686	*/
bogdanm	0:9b334a45a8ff	687	#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CFGR_DMACFG))
bogdanm	0:9b334a45a8ff	688
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	/**
bogdanm	0:9b334a45a8ff	691	* @brief Configure the channel number into offset OFRx register.
bogdanm	0:9b334a45a8ff	692	* @param __CHANNEL__: ADC Channel.
bogdanm	0:9b334a45a8ff	693	* @retval None
bogdanm	0:9b334a45a8ff	694	*/
bogdanm	0:9b334a45a8ff	695	#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697	/**
bogdanm	0:9b334a45a8ff	698	* @brief Configure the channel number into differential mode selection register.
bogdanm	0:9b334a45a8ff	699	* @param __CHANNEL__: ADC Channel.
bogdanm	0:9b334a45a8ff	700	* @retval None
bogdanm	0:9b334a45a8ff	701	*/
bogdanm	0:9b334a45a8ff	702	#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__))
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	/**
bogdanm	0:9b334a45a8ff	705	* @brief Configure calibration factor in differential mode to be set into calibration register.
bogdanm	0:9b334a45a8ff	706	* @param __CALIBRATION_FACTOR__: Calibration factor value.
bogdanm	0:9b334a45a8ff	707	* @retval None
bogdanm	0:9b334a45a8ff	708	*/
bogdanm	0:9b334a45a8ff	709	#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))
bogdanm	0:9b334a45a8ff	710	/**
bogdanm	0:9b334a45a8ff	711	* @brief Calibration factor in differential mode to be retrieved from calibration register.
bogdanm	0:9b334a45a8ff	712	* @param __CALIBRATION_FACTOR__: Calibration factor value.
bogdanm	0:9b334a45a8ff	713	* @retval None
bogdanm	0:9b334a45a8ff	714	*/
bogdanm	0:9b334a45a8ff	715	#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))
bogdanm	0:9b334a45a8ff	716
bogdanm	0:9b334a45a8ff	717	/**
bogdanm	0:9b334a45a8ff	718	* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
bogdanm	0:9b334a45a8ff	719	* @param __THRESHOLD__: Threshold value.
bogdanm	0:9b334a45a8ff	720	* @retval None
bogdanm	0:9b334a45a8ff	721	*/
bogdanm	0:9b334a45a8ff	722	#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	/**
bogdanm	0:9b334a45a8ff	725	* @brief Configure the ADC DMA continuous request for ADC multimode.
bogdanm	0:9b334a45a8ff	726	* @param __DMACONTREQ_MODE__: DMA continuous request mode.
bogdanm	0:9b334a45a8ff	727	* @retval None
bogdanm	0:9b334a45a8ff	728	*/
bogdanm	0:9b334a45a8ff	729	#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731
bogdanm	0:9b334a45a8ff	732	/**
bogdanm	0:9b334a45a8ff	733	* @brief Enable the ADC peripheral.
bogdanm	0:9b334a45a8ff	734	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	735	* @retval None
bogdanm	0:9b334a45a8ff	736	*/
bogdanm	0:9b334a45a8ff	737	#define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= ADC_CR_ADEN)
bogdanm	0:9b334a45a8ff	738
bogdanm	0:9b334a45a8ff	739	/**
bogdanm	0:9b334a45a8ff	740	* @brief Verification of hardware constraints before ADC can be enabled.
bogdanm	0:9b334a45a8ff	741	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	742	* @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
bogdanm	0:9b334a45a8ff	743	*/
bogdanm	0:9b334a45a8ff	744	#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
bogdanm	0:9b334a45a8ff	745	(( ( ((__HANDLE__)->Instance->CR) & \
bogdanm	0:9b334a45a8ff	746	(ADC_CR_ADCAL \| ADC_CR_JADSTP \| ADC_CR_ADSTP \| ADC_CR_JADSTART \| \
bogdanm	0:9b334a45a8ff	747	ADC_CR_ADSTART \| ADC_CR_ADDIS \| ADC_CR_ADEN ) \
bogdanm	0:9b334a45a8ff	748	) == RESET \
bogdanm	0:9b334a45a8ff	749	) ? SET : RESET)
bogdanm	0:9b334a45a8ff	750
bogdanm	0:9b334a45a8ff	751	/**
bogdanm	0:9b334a45a8ff	752	* @brief Disable the ADC peripheral.
bogdanm	0:9b334a45a8ff	753	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	754	* @retval None
bogdanm	0:9b334a45a8ff	755	*/
bogdanm	0:9b334a45a8ff	756	#define ADC_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	757	do{ \
bogdanm	0:9b334a45a8ff	758	(__HANDLE__)->Instance->CR \|= ADC_CR_ADDIS; \
bogdanm	0:9b334a45a8ff	759	__HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP \| ADC_FLAG_RDY)); \
bogdanm	0:9b334a45a8ff	760	} while(0)
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762	/**
bogdanm	0:9b334a45a8ff	763	* @brief Verification of hardware constraints before ADC can be disabled.
bogdanm	0:9b334a45a8ff	764	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	765	* @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
bogdanm	0:9b334a45a8ff	766	*/
bogdanm	0:9b334a45a8ff	767	#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
bogdanm	0:9b334a45a8ff	768	(( ( ((__HANDLE__)->Instance->CR) & \
bogdanm	0:9b334a45a8ff	769	(ADC_CR_JADSTART \| ADC_CR_ADSTART \| ADC_CR_ADEN)) == ADC_CR_ADEN \
bogdanm	0:9b334a45a8ff	770	) ? SET : RESET)
bogdanm	0:9b334a45a8ff	771
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773	/**
bogdanm	0:9b334a45a8ff	774	* @brief Shift the offset with respect to the selected ADC resolution.
bogdanm	0:9b334a45a8ff	775	* @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
bogdanm	0:9b334a45a8ff	776	* If resolution 12 bits, no shift.
bogdanm	0:9b334a45a8ff	777	* If resolution 10 bits, shift of 2 ranks on the left.
bogdanm	0:9b334a45a8ff	778	* If resolution 8 bits, shift of 4 ranks on the left.
bogdanm	0:9b334a45a8ff	779	* If resolution 6 bits, shift of 6 ranks on the left.
bogdanm	0:9b334a45a8ff	780	* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
bogdanm	0:9b334a45a8ff	781	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	782	* @param __OFFSET__: Value to be shifted
bogdanm	0:9b334a45a8ff	783	* @retval None
bogdanm	0:9b334a45a8ff	784	*/
bogdanm	0:9b334a45a8ff	785	#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
bogdanm	0:9b334a45a8ff	786	((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
bogdanm	0:9b334a45a8ff	787
bogdanm	0:9b334a45a8ff	788
bogdanm	0:9b334a45a8ff	789	/**
bogdanm	0:9b334a45a8ff	790	* @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
bogdanm	0:9b334a45a8ff	791	* @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
bogdanm	0:9b334a45a8ff	792	* If resolution 12 bits, no shift.
bogdanm	0:9b334a45a8ff	793	* If resolution 10 bits, shift of 2 ranks on the left.
bogdanm	0:9b334a45a8ff	794	* If resolution 8 bits, shift of 4 ranks on the left.
bogdanm	0:9b334a45a8ff	795	* If resolution 6 bits, shift of 6 ranks on the left.
bogdanm	0:9b334a45a8ff	796	* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
bogdanm	0:9b334a45a8ff	797	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	798	* @param __THRESHOLD__: Value to be shifted
bogdanm	0:9b334a45a8ff	799	* @retval None
bogdanm	0:9b334a45a8ff	800	*/
bogdanm	0:9b334a45a8ff	801	#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
bogdanm	0:9b334a45a8ff	802	((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
bogdanm	0:9b334a45a8ff	803
bogdanm	0:9b334a45a8ff	804	/**
bogdanm	0:9b334a45a8ff	805	* @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
bogdanm	0:9b334a45a8ff	806	* @note Thresholds have to be left-aligned on bit 7.
bogdanm	0:9b334a45a8ff	807	* If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
bogdanm	0:9b334a45a8ff	808	* If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
bogdanm	0:9b334a45a8ff	809	* If resolution 8 bits, no shift.
bogdanm	0:9b334a45a8ff	810	* If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
bogdanm	0:9b334a45a8ff	811	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	812	* @param __THRESHOLD__: Value to be shifted
bogdanm	0:9b334a45a8ff	813	* @retval None
bogdanm	0:9b334a45a8ff	814	*/
bogdanm	0:9b334a45a8ff	815	#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
bogdanm	0:9b334a45a8ff	816	( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 \| ADC_CFGR_RES_0) ? \
bogdanm	0:9b334a45a8ff	817	((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
bogdanm	0:9b334a45a8ff	818	(__THRESHOLD__) << 2 )
bogdanm	0:9b334a45a8ff	819
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	/**
bogdanm	0:9b334a45a8ff	822	* @brief Report common register to ADC1, ADC2 and ADC3.
bogdanm	0:9b334a45a8ff	823	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	824	* @retval Common control register
bogdanm	0:9b334a45a8ff	825	*/
bogdanm	0:9b334a45a8ff	826	#define ADC_COMMON_REGISTER(__HANDLE__) (ADC123_COMMON)
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828
bogdanm	0:9b334a45a8ff	829	/**
bogdanm	0:9b334a45a8ff	830	* @brief Report Master Instance.
bogdanm	0:9b334a45a8ff	831	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	832	* @note return same instance if ADC of input handle is independent ADC.
bogdanm	0:9b334a45a8ff	833	* @retval Master Instance
bogdanm	0:9b334a45a8ff	834	*/
bogdanm	0:9b334a45a8ff	835	#define ADC_MASTER_REGISTER(__HANDLE__) \
bogdanm	0:9b334a45a8ff	836	( ( ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC3)) \
bogdanm	0:9b334a45a8ff	837	)? \
bogdanm	0:9b334a45a8ff	838	((__HANDLE__)->Instance) \
bogdanm	0:9b334a45a8ff	839	: \
bogdanm	0:9b334a45a8ff	840	(ADC1) \
bogdanm	0:9b334a45a8ff	841	)
bogdanm	0:9b334a45a8ff	842
bogdanm	0:9b334a45a8ff	843	/**
bogdanm	0:9b334a45a8ff	844	* @brief Clear Common Control Register.
bogdanm	0:9b334a45a8ff	845	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	846	* @retval None
bogdanm	0:9b334a45a8ff	847	*/
bogdanm	0:9b334a45a8ff	848	#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE \| \
bogdanm	0:9b334a45a8ff	849	ADC_CCR_PRESC \| \
bogdanm	0:9b334a45a8ff	850	ADC_CCR_VBATEN \| \
bogdanm	0:9b334a45a8ff	851	ADC_CCR_TSEN \| \
bogdanm	0:9b334a45a8ff	852	ADC_CCR_VREFEN \| \
bogdanm	0:9b334a45a8ff	853	ADC_CCR_MDMA \| \
bogdanm	0:9b334a45a8ff	854	ADC_CCR_DMACFG \| \
bogdanm	0:9b334a45a8ff	855	ADC_CCR_DELAY \| \
bogdanm	0:9b334a45a8ff	856	ADC_CCR_DUAL )
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	/**
bogdanm	0:9b334a45a8ff	860	* @brief Check whether or not dual conversions are enabled.
bogdanm	0:9b334a45a8ff	861	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	862	* @note Return RESET if ADC of input handle is independent ADC.
bogdanm	0:9b334a45a8ff	863	* @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
bogdanm	0:9b334a45a8ff	864	*/
bogdanm	0:9b334a45a8ff	865	#define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	866	( ( ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC2)) \
bogdanm	0:9b334a45a8ff	867	)? \
bogdanm	0:9b334a45a8ff	868	( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) ) \
bogdanm	0:9b334a45a8ff	869	: \
bogdanm	0:9b334a45a8ff	870	RESET \
bogdanm	0:9b334a45a8ff	871	)
bogdanm	0:9b334a45a8ff	872
bogdanm	0:9b334a45a8ff	873	/**
bogdanm	0:9b334a45a8ff	874	* @brief Check whether or not dual regular conversions are enabled.
bogdanm	0:9b334a45a8ff	875	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	876	* @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
bogdanm	0:9b334a45a8ff	877	*/
bogdanm	0:9b334a45a8ff	878	#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	879	( ( ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC2)) \
bogdanm	0:9b334a45a8ff	880	)? \
bogdanm	0:9b334a45a8ff	881	( (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
bogdanm	0:9b334a45a8ff	882	(((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
bogdanm	0:9b334a45a8ff	883	(((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
bogdanm	0:9b334a45a8ff	884	: \
bogdanm	0:9b334a45a8ff	885	RESET \
bogdanm	0:9b334a45a8ff	886	)
bogdanm	0:9b334a45a8ff	887
bogdanm	0:9b334a45a8ff	888
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/**
bogdanm	0:9b334a45a8ff	891	* @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master.
bogdanm	0:9b334a45a8ff	892	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	893	* @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
bogdanm	0:9b334a45a8ff	894	*/
bogdanm	0:9b334a45a8ff	895	#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
bogdanm	0:9b334a45a8ff	896	( ( ((__HANDLE__)->Instance == ADC1) \|\| ((__HANDLE__)->Instance == ADC3) \
bogdanm	0:9b334a45a8ff	897	)? \
bogdanm	0:9b334a45a8ff	898	SET \
bogdanm	0:9b334a45a8ff	899	: \
bogdanm	0:9b334a45a8ff	900	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
bogdanm	0:9b334a45a8ff	901	)
bogdanm	0:9b334a45a8ff	902
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	/**
bogdanm	0:9b334a45a8ff	905	* @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
bogdanm	0:9b334a45a8ff	906	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	907	* @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
bogdanm	0:9b334a45a8ff	908	*/
bogdanm	0:9b334a45a8ff	909	#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	910	( ( ((__HANDLE__)->Instance == ADC1) \|\| ((__HANDLE__)->Instance == ADC3) \
bogdanm	0:9b334a45a8ff	911	)? \
bogdanm	0:9b334a45a8ff	912	SET \
bogdanm	0:9b334a45a8ff	913	: \
bogdanm	0:9b334a45a8ff	914	( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) \|\| \
bogdanm	0:9b334a45a8ff	915	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) \|\| \
bogdanm	0:9b334a45a8ff	916	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	/**
bogdanm	0:9b334a45a8ff	919	* @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
bogdanm	0:9b334a45a8ff	920	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	921	* @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
bogdanm	0:9b334a45a8ff	922	*/
bogdanm	0:9b334a45a8ff	923	#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	924	( ( ((__HANDLE__)->Instance == ADC1) \|\| ((__HANDLE__)->Instance == ADC3) \
bogdanm	0:9b334a45a8ff	925	)? \
bogdanm	0:9b334a45a8ff	926	SET \
bogdanm	0:9b334a45a8ff	927	: \
bogdanm	0:9b334a45a8ff	928	( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) \|\| \
bogdanm	0:9b334a45a8ff	929	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) \|\| \
bogdanm	0:9b334a45a8ff	930	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	/**
bogdanm	0:9b334a45a8ff	933	* @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.
bogdanm	0:9b334a45a8ff	934	* @param __INSTANCE__: ADC instance.
bogdanm	0:9b334a45a8ff	935	* @retval SET (ADC enabled) or RESET (ADC disabled)
bogdanm	0:9b334a45a8ff	936	*/
bogdanm	0:9b334a45a8ff	937	#define ADC_INSTANCE_IS_ENABLED(__INSTANCE__) \
bogdanm	0:9b334a45a8ff	938	(( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN \| ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
bogdanm	0:9b334a45a8ff	939	((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
bogdanm	0:9b334a45a8ff	940	) ? SET : RESET)
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	/**
bogdanm	0:9b334a45a8ff	943	* @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.
bogdanm	0:9b334a45a8ff	944	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	945	* @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled)
bogdanm	0:9b334a45a8ff	946	*/
bogdanm	0:9b334a45a8ff	947	#define ADC_ANY_OTHER_ENABLED(__HANDLE__) \
bogdanm	0:9b334a45a8ff	948	( ( ((__HANDLE__)->Instance == ADC1) \
bogdanm	0:9b334a45a8ff	949	)? \
bogdanm	0:9b334a45a8ff	950	(ADC_INSTANCE_IS_ENABLED(ADC2)) \|\| (ADC_INSTANCE_IS_ENABLED(ADC3)) \
bogdanm	0:9b334a45a8ff	951	: \
bogdanm	0:9b334a45a8ff	952	( ( ((__HANDLE__)->Instance == ADC2) \
bogdanm	0:9b334a45a8ff	953	)? \
bogdanm	0:9b334a45a8ff	954	(ADC_INSTANCE_IS_ENABLED(ADC1)) \|\| (ADC_INSTANCE_IS_ENABLED(ADC3)) \
bogdanm	0:9b334a45a8ff	955	: \
bogdanm	0:9b334a45a8ff	956	ADC_INSTANCE_IS_ENABLED(ADC1)) \|\| (ADC_INSTANCE_IS_ENABLED(ADC2)) \
bogdanm	0:9b334a45a8ff	957	) \
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	/**
bogdanm	0:9b334a45a8ff	963	* @brief Set handle instance of the ADC slave associated to the ADC master.
bogdanm	0:9b334a45a8ff	964	* @param __HANDLE_MASTER__: ADC master handle.
bogdanm	0:9b334a45a8ff	965	* @param __HANDLE_SLAVE__: ADC slave handle.
bogdanm	0:9b334a45a8ff	966	* @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL.
bogdanm	0:9b334a45a8ff	967	* @retval None
bogdanm	0:9b334a45a8ff	968	*/
bogdanm	0:9b334a45a8ff	969	#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
bogdanm	0:9b334a45a8ff	970	( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/**
bogdanm	0:9b334a45a8ff	973	* @brief Check whether or not multimode is configured in DMA mode.
bogdanm	0:9b334a45a8ff	974	* @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled)
bogdanm	0:9b334a45a8ff	975	*/
bogdanm	0:9b334a45a8ff	976	#define ADC_MULTIMODE_DMA_ENABLED() \
bogdanm	0:9b334a45a8ff	977	((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \
bogdanm	0:9b334a45a8ff	978	\|\| (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS))
bogdanm	0:9b334a45a8ff	979
bogdanm	0:9b334a45a8ff	980	/**
bogdanm	0:9b334a45a8ff	981	* @brief Verify the length of scheduled injected conversions group.
bogdanm	0:9b334a45a8ff	982	* @param __LENGTH__: number of programmed conversions.
bogdanm	0:9b334a45a8ff	983	* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
bogdanm	0:9b334a45a8ff	984	*/
bogdanm	0:9b334a45a8ff	985	#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
bogdanm	0:9b334a45a8ff	986
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988	/**
bogdanm	0:9b334a45a8ff	989	* @brief Calibration factor size verification (7 bits maximum).
bogdanm	0:9b334a45a8ff	990	* @param __CALIBRATION_FACTOR__: Calibration factor value.
bogdanm	0:9b334a45a8ff	991	* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
bogdanm	0:9b334a45a8ff	992	*/
bogdanm	0:9b334a45a8ff	993	#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F))
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995
bogdanm	0:9b334a45a8ff	996	/**
bogdanm	0:9b334a45a8ff	997	* @brief Verify the ADC channel setting.
bogdanm	0:9b334a45a8ff	998	* @param __CHANNEL__: programmed ADC channel.
bogdanm	0:9b334a45a8ff	999	* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
bogdanm	0:9b334a45a8ff	1000	*/
bogdanm	0:9b334a45a8ff	1001	#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) \|\| \
bogdanm	0:9b334a45a8ff	1002	((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	1003	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	1004	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	1005	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	1006	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
bogdanm	0:9b334a45a8ff	1007	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
bogdanm	0:9b334a45a8ff	1008	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
bogdanm	0:9b334a45a8ff	1009	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
bogdanm	0:9b334a45a8ff	1010	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
bogdanm	0:9b334a45a8ff	1011	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
bogdanm	0:9b334a45a8ff	1012	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
bogdanm	0:9b334a45a8ff	1013	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
bogdanm	0:9b334a45a8ff	1014	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
bogdanm	0:9b334a45a8ff	1015	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
bogdanm	0:9b334a45a8ff	1016	((__CHANNEL__) == ADC_CHANNEL_15) \|\| \
bogdanm	0:9b334a45a8ff	1017	((__CHANNEL__) == ADC_CHANNEL_16) \|\| \
bogdanm	0:9b334a45a8ff	1018	((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) \|\| \
bogdanm	0:9b334a45a8ff	1019	((__CHANNEL__) == ADC_CHANNEL_VBAT) \|\| \
bogdanm	0:9b334a45a8ff	1020	((__CHANNEL__) == ADC_CHANNEL_VREFINT) )
bogdanm	0:9b334a45a8ff	1021
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/**
bogdanm	0:9b334a45a8ff	1024	* @brief Verify the ADC1 or ADC2 channel setting in differential mode.
bogdanm	0:9b334a45a8ff	1025	* @param __CHANNEL__: programmed ADC1 or ADC2 channel.
bogdanm	0:9b334a45a8ff	1026	* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
bogdanm	0:9b334a45a8ff	1027	*/
bogdanm	0:9b334a45a8ff	1028	#define IS_ADC12_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)\|\| \
bogdanm	0:9b334a45a8ff	1029	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	1030	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	1031	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	1032	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
bogdanm	0:9b334a45a8ff	1033	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
bogdanm	0:9b334a45a8ff	1034	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
bogdanm	0:9b334a45a8ff	1035	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
bogdanm	0:9b334a45a8ff	1036	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
bogdanm	0:9b334a45a8ff	1037	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
bogdanm	0:9b334a45a8ff	1038	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
bogdanm	0:9b334a45a8ff	1039	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
bogdanm	0:9b334a45a8ff	1040	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
bogdanm	0:9b334a45a8ff	1041	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
bogdanm	0:9b334a45a8ff	1042	((__CHANNEL__) == ADC_CHANNEL_15) )
bogdanm	0:9b334a45a8ff	1043
bogdanm	0:9b334a45a8ff	1044	/**
bogdanm	0:9b334a45a8ff	1045	* @brief Verify the ADC3 channel setting in differential mode.
bogdanm	0:9b334a45a8ff	1046	* @param __CHANNEL__: programmed ADC3 channel.
bogdanm	0:9b334a45a8ff	1047	* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
bogdanm	0:9b334a45a8ff	1048	*/
bogdanm	0:9b334a45a8ff	1049	#define IS_ADC3_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	1050	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	1051	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	1052	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	1053	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
bogdanm	0:9b334a45a8ff	1054	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
bogdanm	0:9b334a45a8ff	1055	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
bogdanm	0:9b334a45a8ff	1056	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
bogdanm	0:9b334a45a8ff	1057	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
bogdanm	0:9b334a45a8ff	1058	((__CHANNEL__) == ADC_CHANNEL_10)\|\| \
bogdanm	0:9b334a45a8ff	1059	((__CHANNEL__) == ADC_CHANNEL_11) )
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061
bogdanm	0:9b334a45a8ff	1062	/**
bogdanm	0:9b334a45a8ff	1063	* @brief Verify the ADC single-ended input or differential mode setting.
bogdanm	0:9b334a45a8ff	1064	* @param __SING_DIFF__: programmed channel setting.
bogdanm	0:9b334a45a8ff	1065	* @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
bogdanm	0:9b334a45a8ff	1066	*/
bogdanm	0:9b334a45a8ff	1067	#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) \|\| \
bogdanm	0:9b334a45a8ff	1068	((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
bogdanm	0:9b334a45a8ff	1069
bogdanm	0:9b334a45a8ff	1070
bogdanm	0:9b334a45a8ff	1071	/**
bogdanm	0:9b334a45a8ff	1072	* @brief Verify the ADC offset management setting.
bogdanm	0:9b334a45a8ff	1073	* @param __OFFSET_NUMBER__: ADC offset management.
bogdanm	0:9b334a45a8ff	1074	* @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
bogdanm	0:9b334a45a8ff	1075	*/
bogdanm	0:9b334a45a8ff	1076	#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1077	((__OFFSET_NUMBER__) == ADC_OFFSET_1) \|\| \
bogdanm	0:9b334a45a8ff	1078	((__OFFSET_NUMBER__) == ADC_OFFSET_2) \|\| \
bogdanm	0:9b334a45a8ff	1079	((__OFFSET_NUMBER__) == ADC_OFFSET_3) \|\| \
bogdanm	0:9b334a45a8ff	1080	((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
bogdanm	0:9b334a45a8ff	1081
bogdanm	0:9b334a45a8ff	1082	/**
bogdanm	0:9b334a45a8ff	1083	* @brief Verify the ADC regular channel setting.
bogdanm	0:9b334a45a8ff	1084	* @param __CHANNEL__: programmed ADC regular channel.
bogdanm	0:9b334a45a8ff	1085	* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
bogdanm	0:9b334a45a8ff	1086	*/
bogdanm	0:9b334a45a8ff	1087	#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) \|\| \
bogdanm	0:9b334a45a8ff	1088	((__CHANNEL__) == ADC_REGULAR_RANK_2 ) \|\| \
bogdanm	0:9b334a45a8ff	1089	((__CHANNEL__) == ADC_REGULAR_RANK_3 ) \|\| \
bogdanm	0:9b334a45a8ff	1090	((__CHANNEL__) == ADC_REGULAR_RANK_4 ) \|\| \
bogdanm	0:9b334a45a8ff	1091	((__CHANNEL__) == ADC_REGULAR_RANK_5 ) \|\| \
bogdanm	0:9b334a45a8ff	1092	((__CHANNEL__) == ADC_REGULAR_RANK_6 ) \|\| \
bogdanm	0:9b334a45a8ff	1093	((__CHANNEL__) == ADC_REGULAR_RANK_7 ) \|\| \
bogdanm	0:9b334a45a8ff	1094	((__CHANNEL__) == ADC_REGULAR_RANK_8 ) \|\| \
bogdanm	0:9b334a45a8ff	1095	((__CHANNEL__) == ADC_REGULAR_RANK_9 ) \|\| \
bogdanm	0:9b334a45a8ff	1096	((__CHANNEL__) == ADC_REGULAR_RANK_10) \|\| \
bogdanm	0:9b334a45a8ff	1097	((__CHANNEL__) == ADC_REGULAR_RANK_11) \|\| \
bogdanm	0:9b334a45a8ff	1098	((__CHANNEL__) == ADC_REGULAR_RANK_12) \|\| \
bogdanm	0:9b334a45a8ff	1099	((__CHANNEL__) == ADC_REGULAR_RANK_13) \|\| \
bogdanm	0:9b334a45a8ff	1100	((__CHANNEL__) == ADC_REGULAR_RANK_14) \|\| \
bogdanm	0:9b334a45a8ff	1101	((__CHANNEL__) == ADC_REGULAR_RANK_15) \|\| \
bogdanm	0:9b334a45a8ff	1102	((__CHANNEL__) == ADC_REGULAR_RANK_16) )
bogdanm	0:9b334a45a8ff	1103
bogdanm	0:9b334a45a8ff	1104
bogdanm	0:9b334a45a8ff	1105	/**
bogdanm	0:9b334a45a8ff	1106	* @brief Verify the ADC injected channel setting.
bogdanm	0:9b334a45a8ff	1107	* @param __CHANNEL__: programmed ADC injected channel.
bogdanm	0:9b334a45a8ff	1108	* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
bogdanm	0:9b334a45a8ff	1109	*/
bogdanm	0:9b334a45a8ff	1110	#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) \|\| \
bogdanm	0:9b334a45a8ff	1111	((__CHANNEL__) == ADC_INJECTED_RANK_2) \|\| \
bogdanm	0:9b334a45a8ff	1112	((__CHANNEL__) == ADC_INJECTED_RANK_3) \|\| \
bogdanm	0:9b334a45a8ff	1113	((__CHANNEL__) == ADC_INJECTED_RANK_4) )
bogdanm	0:9b334a45a8ff	1114
bogdanm	0:9b334a45a8ff	1115	/**
bogdanm	0:9b334a45a8ff	1116	* @brief Verify the ADC edge trigger setting for injected group.
bogdanm	0:9b334a45a8ff	1117	* @param __EDGE__: programmed ADC edge trigger setting.
bogdanm	0:9b334a45a8ff	1118	* @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
bogdanm	0:9b334a45a8ff	1119	*/
bogdanm	0:9b334a45a8ff	1120	#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1121	((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) \|\| \
bogdanm	0:9b334a45a8ff	1122	((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	1123	((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
bogdanm	0:9b334a45a8ff	1124
bogdanm	0:9b334a45a8ff	1125
bogdanm	0:9b334a45a8ff	1126	/**
bogdanm	0:9b334a45a8ff	1127	* @brief Verify the ADC injected conversions external trigger.
bogdanm	0:9b334a45a8ff	1128	* @param __INJTRIG__: programmed ADC injected conversions external trigger.
bogdanm	0:9b334a45a8ff	1129	* @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
bogdanm	0:9b334a45a8ff	1130	*/
bogdanm	0:9b334a45a8ff	1131	#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	1132	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) \|\| \
bogdanm	0:9b334a45a8ff	1133	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	1134	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) \|\| \
bogdanm	0:9b334a45a8ff	1135	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) \|\| \
bogdanm	0:9b334a45a8ff	1136	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	1137	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) \|\| \
bogdanm	0:9b334a45a8ff	1138	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) \|\| \
bogdanm	0:9b334a45a8ff	1139	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) \|\| \
bogdanm	0:9b334a45a8ff	1140	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	1141	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) \|\| \
bogdanm	0:9b334a45a8ff	1142	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) \|\| \
bogdanm	0:9b334a45a8ff	1143	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	1144	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) \|\| \
bogdanm	0:9b334a45a8ff	1145	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	1146	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	1147	\
bogdanm	0:9b334a45a8ff	1148	((__INJTRIG__) == ADC_SOFTWARE_START) )
bogdanm	0:9b334a45a8ff	1149
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	/**
bogdanm	0:9b334a45a8ff	1152	* @brief Verify the ADC multimode setting.
bogdanm	0:9b334a45a8ff	1153	* @param __MODE__: programmed ADC multimode setting.
bogdanm	0:9b334a45a8ff	1154	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
bogdanm	0:9b334a45a8ff	1155	*/
bogdanm	0:9b334a45a8ff	1156	#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) \|\| \
bogdanm	0:9b334a45a8ff	1157	((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) \|\| \
bogdanm	0:9b334a45a8ff	1158	((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) \|\| \
bogdanm	0:9b334a45a8ff	1159	((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) \|\| \
bogdanm	0:9b334a45a8ff	1160	((__MODE__) == ADC_DUALMODE_INJECSIMULT) \|\| \
bogdanm	0:9b334a45a8ff	1161	((__MODE__) == ADC_DUALMODE_REGSIMULT) \|\| \
bogdanm	0:9b334a45a8ff	1162	((__MODE__) == ADC_DUALMODE_INTERL) \|\| \
bogdanm	0:9b334a45a8ff	1163	((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165
bogdanm	0:9b334a45a8ff	1166	/**
bogdanm	0:9b334a45a8ff	1167	* @brief Verify the ADC multimode DMA access setting.
bogdanm	0:9b334a45a8ff	1168	* @param __MODE__: programmed ADC multimode DMA access setting.
bogdanm	0:9b334a45a8ff	1169	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
bogdanm	0:9b334a45a8ff	1170	*/
bogdanm	0:9b334a45a8ff	1171	#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	1172	((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) \|\| \
bogdanm	0:9b334a45a8ff	1173	((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) )
bogdanm	0:9b334a45a8ff	1174
bogdanm	0:9b334a45a8ff	1175	/**
bogdanm	0:9b334a45a8ff	1176	* @brief Verify the ADC multimode delay setting.
bogdanm	0:9b334a45a8ff	1177	* @param __DELAY__: programmed ADC multimode delay setting.
bogdanm	0:9b334a45a8ff	1178	* @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
bogdanm	0:9b334a45a8ff	1179	*/
bogdanm	0:9b334a45a8ff	1180	#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) \|\| \
bogdanm	0:9b334a45a8ff	1181	((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	1182	((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	1183	((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	1184	((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	1185	((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	1186	((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	1187	((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	1188	((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	1189	((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	1190	((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	1191	((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	/**
bogdanm	0:9b334a45a8ff	1195	* @brief Verify the ADC analog watchdog setting.
bogdanm	0:9b334a45a8ff	1196	* @param __WATCHDOG__: programmed ADC analog watchdog setting.
bogdanm	0:9b334a45a8ff	1197	* @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
bogdanm	0:9b334a45a8ff	1198	*/
bogdanm	0:9b334a45a8ff	1199	#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) \|\| \
bogdanm	0:9b334a45a8ff	1200	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) \|\| \
bogdanm	0:9b334a45a8ff	1201	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	/**
bogdanm	0:9b334a45a8ff	1204	* @brief Verify the ADC analog watchdog mode setting.
bogdanm	0:9b334a45a8ff	1205	* @param __WATCHDOG_MODE__: programmed ADC analog watchdog mode setting.
bogdanm	0:9b334a45a8ff	1206	* @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
bogdanm	0:9b334a45a8ff	1207	*/
bogdanm	0:9b334a45a8ff	1208	#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1209	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
bogdanm	0:9b334a45a8ff	1210	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
bogdanm	0:9b334a45a8ff	1211	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
bogdanm	0:9b334a45a8ff	1212	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
bogdanm	0:9b334a45a8ff	1213	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
bogdanm	0:9b334a45a8ff	1214	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
bogdanm	0:9b334a45a8ff	1215
bogdanm	0:9b334a45a8ff	1216	/**
bogdanm	0:9b334a45a8ff	1217	* @brief Verify the ADC conversion (regular or injected or both).
bogdanm	0:9b334a45a8ff	1218	* @param __CONVERSION__: ADC conversion group.
bogdanm	0:9b334a45a8ff	1219	* @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
bogdanm	0:9b334a45a8ff	1220	*/
bogdanm	0:9b334a45a8ff	1221	#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) \|\| \
bogdanm	0:9b334a45a8ff	1222	((__CONVERSION__) == ADC_INJECTED_GROUP) \|\| \
bogdanm	0:9b334a45a8ff	1223	((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
bogdanm	0:9b334a45a8ff	1224
bogdanm	0:9b334a45a8ff	1225	/**
bogdanm	0:9b334a45a8ff	1226	* @brief Verify the ADC event type.
bogdanm	0:9b334a45a8ff	1227	* @param __EVENT__: ADC event.
bogdanm	0:9b334a45a8ff	1228	* @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
bogdanm	0:9b334a45a8ff	1229	*/
bogdanm	0:9b334a45a8ff	1230	#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) \|\| \
bogdanm	0:9b334a45a8ff	1231	((__EVENT__) == ADC_AWD_EVENT) \|\| \
bogdanm	0:9b334a45a8ff	1232	((__EVENT__) == ADC_AWD2_EVENT) \|\| \
bogdanm	0:9b334a45a8ff	1233	((__EVENT__) == ADC_AWD3_EVENT) \|\| \
bogdanm	0:9b334a45a8ff	1234	((__EVENT__) == ADC_OVR_EVENT) \|\| \
bogdanm	0:9b334a45a8ff	1235	((__EVENT__) == ADC_JQOVF_EVENT) )
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	/**
bogdanm	0:9b334a45a8ff	1238	* @brief Verify the ADC oversampling ratio.
bogdanm	0:9b334a45a8ff	1239	* @param __RATIO__: programmed ADC oversampling ratio.
bogdanm	0:9b334a45a8ff	1240	* @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
bogdanm	0:9b334a45a8ff	1241	*/
bogdanm	0:9b334a45a8ff	1242	#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) \|\| \
bogdanm	0:9b334a45a8ff	1243	((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) \|\| \
bogdanm	0:9b334a45a8ff	1244	((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) \|\| \
bogdanm	0:9b334a45a8ff	1245	((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) \|\| \
bogdanm	0:9b334a45a8ff	1246	((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) \|\| \
bogdanm	0:9b334a45a8ff	1247	((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) \|\| \
bogdanm	0:9b334a45a8ff	1248	((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) \|\| \
bogdanm	0:9b334a45a8ff	1249	((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
bogdanm	0:9b334a45a8ff	1250
bogdanm	0:9b334a45a8ff	1251	/**
bogdanm	0:9b334a45a8ff	1252	* @brief Verify the ADC oversampling shift.
bogdanm	0:9b334a45a8ff	1253	* @param __SHIFT__: programmed ADC oversampling shift.
bogdanm	0:9b334a45a8ff	1254	* @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
bogdanm	0:9b334a45a8ff	1255	*/
bogdanm	0:9b334a45a8ff	1256	#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1257	((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) \|\| \
bogdanm	0:9b334a45a8ff	1258	((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) \|\| \
bogdanm	0:9b334a45a8ff	1259	((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) \|\| \
bogdanm	0:9b334a45a8ff	1260	((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) \|\| \
bogdanm	0:9b334a45a8ff	1261	((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) \|\| \
bogdanm	0:9b334a45a8ff	1262	((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) \|\| \
bogdanm	0:9b334a45a8ff	1263	((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) \|\| \
bogdanm	0:9b334a45a8ff	1264	((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
bogdanm	0:9b334a45a8ff	1265
bogdanm	0:9b334a45a8ff	1266	/**
bogdanm	0:9b334a45a8ff	1267	* @brief Verify the ADC oversampling triggered mode.
bogdanm	0:9b334a45a8ff	1268	* @param __MODE__: programmed ADC oversampling triggered mode.
bogdanm	0:9b334a45a8ff	1269	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
bogdanm	0:9b334a45a8ff	1270	*/
bogdanm	0:9b334a45a8ff	1271	#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) \|\| \
bogdanm	0:9b334a45a8ff	1272	((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/**
bogdanm	0:9b334a45a8ff	1275	* @brief Verify the ADC oversampling regular conversion resumed or continued mode.
bogdanm	0:9b334a45a8ff	1276	* @param __MODE__: programmed ADC oversampling regular conversion resumed or continued mode.
bogdanm	0:9b334a45a8ff	1277	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
bogdanm	0:9b334a45a8ff	1278	*/
bogdanm	0:9b334a45a8ff	1279	#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) \|\| \
bogdanm	0:9b334a45a8ff	1280	((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
bogdanm	0:9b334a45a8ff	1281
bogdanm	0:9b334a45a8ff	1282	/**
bogdanm	0:9b334a45a8ff	1283	* @}
bogdanm	0:9b334a45a8ff	1284	*/
bogdanm	0:9b334a45a8ff	1285
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1288	/** @addtogroup ADCEx_Exported_Functions ADC Extended Exported Functions
bogdanm	0:9b334a45a8ff	1289	* @{
bogdanm	0:9b334a45a8ff	1290	*/
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	/* Initialization/de-initialization functions *********************************/
bogdanm	0:9b334a45a8ff	1293
bogdanm	0:9b334a45a8ff	1294	/** @addtogroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
bogdanm	0:9b334a45a8ff	1295	* @brief Extended IO operation functions
bogdanm	0:9b334a45a8ff	1296	* @{
bogdanm	0:9b334a45a8ff	1297	*/
bogdanm	0:9b334a45a8ff	1298	/* I/O operation functions ****************************************************/
bogdanm	0:9b334a45a8ff	1299
bogdanm	0:9b334a45a8ff	1300	/* ADC calibration */
bogdanm	0:9b334a45a8ff	1301
bogdanm	0:9b334a45a8ff	1302	HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
bogdanm	0:9b334a45a8ff	1303	uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
bogdanm	0:9b334a45a8ff	1304	HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
bogdanm	0:9b334a45a8ff	1305
bogdanm	0:9b334a45a8ff	1306
bogdanm	0:9b334a45a8ff	1307
bogdanm	0:9b334a45a8ff	1308	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1309	HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1310	HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1311	HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	1312
bogdanm	0:9b334a45a8ff	1313	/* Non-blocking mode: Interruption */
bogdanm	0:9b334a45a8ff	1314	HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1315	HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1316
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	/* ADC multimode */
bogdanm	0:9b334a45a8ff	1319	HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef hadc, uint32_t pData, uint32_t Length);
bogdanm	0:9b334a45a8ff	1320	HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
bogdanm	0:9b334a45a8ff	1321	uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
bogdanm	0:9b334a45a8ff	1322
bogdanm	0:9b334a45a8ff	1323
bogdanm	0:9b334a45a8ff	1324	/* ADC retrieve conversion value intended to be used with polling or interruption */
bogdanm	0:9b334a45a8ff	1325	uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
bogdanm	0:9b334a45a8ff	1328	void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1329	void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1330	void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1331	void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1332	void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334
bogdanm	0:9b334a45a8ff	1335	/* ADC Regular conversions stop */
bogdanm	0:9b334a45a8ff	1336	HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1337	HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1338	HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1339	HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1340
bogdanm	0:9b334a45a8ff	1341	/**
bogdanm	0:9b334a45a8ff	1342	* @}
bogdanm	0:9b334a45a8ff	1343	*/
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	/** @addtogroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	1346	* @brief Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	1347	* @{
bogdanm	0:9b334a45a8ff	1348	*/
bogdanm	0:9b334a45a8ff	1349	/* Peripheral Control functions ***********************************************/
bogdanm	0:9b334a45a8ff	1350	HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
bogdanm	0:9b334a45a8ff	1351	HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef hadc, ADC_MultiModeTypeDef multimode);
bogdanm	0:9b334a45a8ff	1352	HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1353	HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1354	HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1355	HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1356
bogdanm	0:9b334a45a8ff	1357	/**
bogdanm	0:9b334a45a8ff	1358	* @}
bogdanm	0:9b334a45a8ff	1359	*/
bogdanm	0:9b334a45a8ff	1360
bogdanm	0:9b334a45a8ff	1361	/**
bogdanm	0:9b334a45a8ff	1362	* @}
bogdanm	0:9b334a45a8ff	1363	*/
bogdanm	0:9b334a45a8ff	1364
bogdanm	0:9b334a45a8ff	1365	/**
bogdanm	0:9b334a45a8ff	1366	* @}
bogdanm	0:9b334a45a8ff	1367	*/
bogdanm	0:9b334a45a8ff	1368
bogdanm	0:9b334a45a8ff	1369	/**
bogdanm	0:9b334a45a8ff	1370	* @}
bogdanm	0:9b334a45a8ff	1371	*/
bogdanm	0:9b334a45a8ff	1372
bogdanm	0:9b334a45a8ff	1373	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1374	}
bogdanm	0:9b334a45a8ff	1375	#endif
bogdanm	0:9b334a45a8ff	1376
bogdanm	0:9b334a45a8ff	1377	#endif /__STM32L4xx_ADC_EX_H /
bogdanm	0:9b334a45a8ff	1378
bogdanm	0:9b334a45a8ff	1379
bogdanm	0:9b334a45a8ff	1380	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_adc_ex.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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