mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_adc.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l4xx_hal_adc.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application conversion
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	8	* functionalities of the Analog to Digital Convertor (ADC)
bogdanm	0:9b334a45a8ff	9	* peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* ++ Configuration of ADC
bogdanm	0:9b334a45a8ff	12	* + Operation functions
bogdanm	0:9b334a45a8ff	13	* ++ Start, stop, get result of regular conversions of regular
bogdanm	0:9b334a45a8ff	14	* using 3 possible modes: polling, interruption or DMA.
bogdanm	0:9b334a45a8ff	15	* + Control functions
bogdanm	0:9b334a45a8ff	16	* ++ Analog Watchdog configuration
bogdanm	0:9b334a45a8ff	17	* ++ Channels configuration on regular group
bogdanm	0:9b334a45a8ff	18	* + State functions
bogdanm	0:9b334a45a8ff	19	* ++ ADC state machine management
bogdanm	0:9b334a45a8ff	20	* ++ Interrupts and flags management
bogdanm	0:9b334a45a8ff	21	*
bogdanm	0:9b334a45a8ff	22	@verbatim
bogdanm	0:9b334a45a8ff	23	==============================================================================
bogdanm	0:9b334a45a8ff	24	##### ADC specific features #####
bogdanm	0:9b334a45a8ff	25	==============================================================================
bogdanm	0:9b334a45a8ff	26	[..]
bogdanm	0:9b334a45a8ff	27	(#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
bogdanm	0:9b334a45a8ff	28
bogdanm	0:9b334a45a8ff	29	(#) Interrupt generation at the end of regular conversion and in case of
bogdanm	0:9b334a45a8ff	30	analog watchdog and overrun events.
bogdanm	0:9b334a45a8ff	31
bogdanm	0:9b334a45a8ff	32	(#) Single and continuous conversion modes.
bogdanm	0:9b334a45a8ff	33
bogdanm	0:9b334a45a8ff	34	(#) Scan mode for automatic conversion of channel 0 to channel 'n'.
bogdanm	0:9b334a45a8ff	35
bogdanm	0:9b334a45a8ff	36	(#) Data alignment with in-built data coherency.
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	(#) Channel-wise programmable sampling time.
bogdanm	0:9b334a45a8ff	39
bogdanm	0:9b334a45a8ff	40	(#) External trigger (timer or EXTI) with configurable polarity for
bogdanm	0:9b334a45a8ff	41	regular groups.
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	(#) DMA request generation for transfer of regular group converted data.
bogdanm	0:9b334a45a8ff	44
bogdanm	0:9b334a45a8ff	45	(#) Configurable delay between conversions in Dual interleaved mode.
bogdanm	0:9b334a45a8ff	46
bogdanm	0:9b334a45a8ff	47	(#) ADC channels selectable single/differential input.
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	(#) ADC offset on regular groups.
bogdanm	0:9b334a45a8ff	50
bogdanm	0:9b334a45a8ff	51	(#) ADC supply requirements: 1.62 V to 3.6 V.
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	(#) ADC input range: from Vref_ (connected to Vssa) to Vref+ (connected to
bogdanm	0:9b334a45a8ff	54	Vdda or to an external voltage reference).
bogdanm	0:9b334a45a8ff	55
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57
bogdanm	0:9b334a45a8ff	58	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	59	==============================================================================
bogdanm	0:9b334a45a8ff	60	[..]
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62	(#) Enable the ADC interface
bogdanm	0:9b334a45a8ff	63	As prerequisite, in HAL_ADC_MspInit(), ADC clock source must be
bogdanm	0:9b334a45a8ff	64	configured at RCC top level.
bogdanm	0:9b334a45a8ff	65
bogdanm	0:9b334a45a8ff	66	Two different clock sources are available:
bogdanm	0:9b334a45a8ff	67	(++) - the ADC clock can be a specific clock source, coming from the system
bogdanm	0:9b334a45a8ff	68	clock, the PLLSAI1 or the PLLSAI2 running up to 80MHz.
bogdanm	0:9b334a45a8ff	69	(++) - or the ADC clock can be derived from the AHB clock of the ADC bus
bogdanm	0:9b334a45a8ff	70	interface, divided by a programmable factor
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	(++) For example, in case of PLLSAI2:
bogdanm	0:9b334a45a8ff	74	(+++) __HAL_RCC_ADC_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	75	(+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
bogdanm	0:9b334a45a8ff	76	(+++) where
bogdanm	0:9b334a45a8ff	77	(+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
bogdanm	0:9b334a45a8ff	78	(+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI2
bogdanm	0:9b334a45a8ff	79
bogdanm	0:9b334a45a8ff	80
bogdanm	0:9b334a45a8ff	81	(#) ADC pins configuration
bogdanm	0:9b334a45a8ff	82	(++) Enable the clock for the ADC GPIOs using the following function:
bogdanm	0:9b334a45a8ff	83	__HAL_RCC_GPIOx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	84	(++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	(#) Configure the ADC parameters (conversion resolution, data alignment,
bogdanm	0:9b334a45a8ff	87	continuous mode, ...) using the HAL_ADC_Init() function.
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	(#) Optionally, perform an automatic ADC calibration to improve the
bogdanm	0:9b334a45a8ff	90	conversion accuracy using function HAL_ADCEx_Calibration_Start().
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	(#) Activate the ADC peripheral using one of the start functions:
bogdanm	0:9b334a45a8ff	93	HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(),
bogdanm	0:9b334a45a8ff	94	HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() or
bogdanm	0:9b334a45a8ff	95	HAL_ADCEx_MultiModeStart_DMA().
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97	* Channels to regular group configuration *
bogdanm	0:9b334a45a8ff	98	============================================
bogdanm	0:9b334a45a8ff	99	[..]
bogdanm	0:9b334a45a8ff	100	(+) To configure the ADC regular group features, use
bogdanm	0:9b334a45a8ff	101	HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
bogdanm	0:9b334a45a8ff	102	(+) To activate the continuous mode, use the HAL_ADC_Init() function.
bogdanm	0:9b334a45a8ff	103	(+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
bogdanm	0:9b334a45a8ff	104
bogdanm	0:9b334a45a8ff	105	* DMA for regular configuration *
bogdanm	0:9b334a45a8ff	106	=============================================================
bogdanm	0:9b334a45a8ff	107	[..]
bogdanm	0:9b334a45a8ff	108	(+) To enable the DMA mode for regular group, use the
bogdanm	0:9b334a45a8ff	109	HAL_ADC_Start_DMA() function.
bogdanm	0:9b334a45a8ff	110	(+) To enable the generation of DMA requests continuously at the end of
bogdanm	0:9b334a45a8ff	111	the last DMA transfer, resort to DMAContinuousRequests parameter of
bogdanm	0:9b334a45a8ff	112	ADC handle initialization structure.
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114
bogdanm	0:9b334a45a8ff	115
bogdanm	0:9b334a45a8ff	116	@endverbatim
bogdanm	0:9b334a45a8ff	117	******************************************************************************
bogdanm	0:9b334a45a8ff	118	* @attention
bogdanm	0:9b334a45a8ff	119	*
bogdanm	0:9b334a45a8ff	120	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	121	*
bogdanm	0:9b334a45a8ff	122	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	123	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	124	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	125	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	126	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	127	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	128	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	129	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	130	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	131	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	132	*
bogdanm	0:9b334a45a8ff	133	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	134	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	135	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	136	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	137	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	138	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	139	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	140	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	141	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	142	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	143	*
bogdanm	0:9b334a45a8ff	144	******************************************************************************
bogdanm	0:9b334a45a8ff	145	*/
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	148	#include "stm32l4xx_hal.h"
bogdanm	0:9b334a45a8ff	149
bogdanm	0:9b334a45a8ff	150	/** @addtogroup STM32L4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	151	* @{
bogdanm	0:9b334a45a8ff	152	*/
bogdanm	0:9b334a45a8ff	153
bogdanm	0:9b334a45a8ff	154	/** @defgroup ADC ADC
bogdanm	0:9b334a45a8ff	155	* @brief ADC HAL module driver
bogdanm	0:9b334a45a8ff	156	* @{
bogdanm	0:9b334a45a8ff	157	*/
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	#ifdef HAL_ADC_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	160
bogdanm	0:9b334a45a8ff	161	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	162	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	163
bogdanm	0:9b334a45a8ff	164	/** @defgroup ADC_Private_Constants ADC Private Constants
bogdanm	0:9b334a45a8ff	165	* @{
bogdanm	0:9b334a45a8ff	166	*/
bogdanm	0:9b334a45a8ff	167
bogdanm	0:9b334a45a8ff	168	#define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES \| ADC_CFGR_ALIGN \|\
bogdanm	0:9b334a45a8ff	169	ADC_CFGR_CONT \| ADC_CFGR_OVRMOD \|\
bogdanm	0:9b334a45a8ff	170	ADC_CFGR_DISCEN \| ADC_CFGR_DISCNUM \|\
bogdanm	0:9b334a45a8ff	171	ADC_CFGR_EXTEN \| ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
bogdanm	0:9b334a45a8ff	172	when no regular conversion is on-going */
bogdanm	0:9b334a45a8ff	173
bogdanm	0:9b334a45a8ff	174	#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG \| ADC_CFGR_AUTDLY)) /*!< ADC_CFGR fields of parameters that can be updated when no conversion
bogdanm	0:9b334a45a8ff	175	(neither regular nor injected) is on-going */
bogdanm	0:9b334a45a8ff	176
bogdanm	0:9b334a45a8ff	177	#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE \| ADC_CFGR2_OVSR \|\
bogdanm	0:9b334a45a8ff	178	ADC_CFGR2_OVSS \| ADC_CFGR2_TROVS \|\
bogdanm	0:9b334a45a8ff	179	ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
bogdanm	0:9b334a45a8ff	180	(neither regular nor injected) is on-going */
bogdanm	0:9b334a45a8ff	181
bogdanm	0:9b334a45a8ff	182	#define ADC_CFGR_WD_FIELDS ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_JAWD1EN \| \
bogdanm	0:9b334a45a8ff	183	ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1CH)) /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no
bogdanm	0:9b334a45a8ff	184	conversion (neither regular nor injected) is on-going */
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	#define ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 \| ADC_OFR1_OFFSET1_CH \| ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion
bogdanm	0:9b334a45a8ff	187	(neither regular nor injected) is on-going */
bogdanm	0:9b334a45a8ff	188
bogdanm	0:9b334a45a8ff	189
bogdanm	0:9b334a45a8ff	190
bogdanm	0:9b334a45a8ff	191	/* Delay to wait before setting ADEN once ADCAL has been reset
bogdanm	0:9b334a45a8ff	192	must be at least 4 ADC clock cycles.
bogdanm	0:9b334a45a8ff	193	Assuming lowest ADC clock (140 KHz according to DS), this
bogdanm	0:9b334a45a8ff	194	4 ADC clock cycles duration is equal to
bogdanm	0:9b334a45a8ff	195	4 / 140,000 = 0.028 ms.
bogdanm	0:9b334a45a8ff	196	ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure
bogdanm	0:9b334a45a8ff	197	the 4 ADC clock cycles have elapsed while waiting for ADRDY
bogdanm	0:9b334a45a8ff	198	to become 1 */
bogdanm	0:9b334a45a8ff	199	#define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /!< ADC enable time-out value /
bogdanm	0:9b334a45a8ff	200	#define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /!< ADC disable time-out value /
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203
bogdanm	0:9b334a45a8ff	204	/* Delay for ADC voltage regulator startup time */
bogdanm	0:9b334a45a8ff	205	/* Maximum delay is 10 microseconds */
bogdanm	0:9b334a45a8ff	206	/* (refer device RM, parameter Tadcvreg_stup). */
bogdanm	0:9b334a45a8ff	207	#define ADC_STAB_DELAY_US ((uint32_t) 10) /!< ADC voltage regulator startup time /
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209
bogdanm	0:9b334a45a8ff	210	/* Timeout to wait for current conversion on going to be completed. */
bogdanm	0:9b334a45a8ff	211	/* Timeout fixed to worst case, for 1 channel. */
bogdanm	0:9b334a45a8ff	212	/* - maximum sampling time (640.5 adc_clk) */
bogdanm	0:9b334a45a8ff	213	/* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
bogdanm	0:9b334a45a8ff	214	/* - ADC clock with prescaler 256 */
bogdanm	0:9b334a45a8ff	215	/* 653 * 256 = 167168 clock cycles max */
bogdanm	0:9b334a45a8ff	216	/* Unit: cycles of CPU clock. */
bogdanm	0:9b334a45a8ff	217	#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168) /!< ADC conversion completion time-out value /
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219
bogdanm	0:9b334a45a8ff	220
bogdanm	0:9b334a45a8ff	221
bogdanm	0:9b334a45a8ff	222	/**
bogdanm	0:9b334a45a8ff	223	* @}
bogdanm	0:9b334a45a8ff	224	*/
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	227	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	228	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	229	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	/** @defgroup ADC_Exported_Functions ADC Exported Functions
bogdanm	0:9b334a45a8ff	232	* @{
bogdanm	0:9b334a45a8ff	233	*/
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	236	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	237	*
bogdanm	0:9b334a45a8ff	238	@verbatim
bogdanm	0:9b334a45a8ff	239	===============================================================================
bogdanm	0:9b334a45a8ff	240	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	241	===============================================================================
bogdanm	0:9b334a45a8ff	242	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	243	(+) Initialize and configure the ADC.
bogdanm	0:9b334a45a8ff	244	(+) De-initialize the ADC.
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	@endverbatim
bogdanm	0:9b334a45a8ff	247	* @{
bogdanm	0:9b334a45a8ff	248	*/
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	/**
bogdanm	0:9b334a45a8ff	251	* @brief Initialize the ADC peripheral and regular group according to
bogdanm	0:9b334a45a8ff	252	* parameters specified in structure "ADC_InitTypeDef".
bogdanm	0:9b334a45a8ff	253	* @note As prerequisite, ADC clock must be configured at RCC top level
bogdanm	0:9b334a45a8ff	254	* depending on possible clock sources: System/PLLSAI1/PLLSAI2 clocks
bogdanm	0:9b334a45a8ff	255	* or AHB clock.
bogdanm	0:9b334a45a8ff	256	* @note Possibility to update parameters on the fly:
bogdanm	0:9b334a45a8ff	257	* this function initializes the ADC MSP (HAL_ADC_MspInit()) only when
bogdanm	0:9b334a45a8ff	258	* coming from ADC state reset. Following calls to this function can
bogdanm	0:9b334a45a8ff	259	* be used to reconfigure some parameters of ADC_InitTypeDef
bogdanm	0:9b334a45a8ff	260	* structure on the fly, without modifying MSP configuration. If ADC
bogdanm	0:9b334a45a8ff	261	* MSP has to be modified again, HAL_ADC_DeInit() must be called
bogdanm	0:9b334a45a8ff	262	* before HAL_ADC_Init().
bogdanm	0:9b334a45a8ff	263	* The setting of these parameters is conditioned by ADC state.
bogdanm	0:9b334a45a8ff	264	* For parameters constraints, see comments of structure
bogdanm	0:9b334a45a8ff	265	* "ADC_InitTypeDef".
bogdanm	0:9b334a45a8ff	266	* @note This function configures the ADC within 2 scopes: scope of entire
bogdanm	0:9b334a45a8ff	267	* ADC and scope of regular group. For parameters details, see comments
bogdanm	0:9b334a45a8ff	268	* of structure "ADC_InitTypeDef".
bogdanm	0:9b334a45a8ff	269	* @note Parameters related to common ADC registers (ADC clock mode) are set
bogdanm	0:9b334a45a8ff	270	* only if all ADCs are disabled.
bogdanm	0:9b334a45a8ff	271	* If this is not the case, these common parameters setting are
bogdanm	0:9b334a45a8ff	272	* bypassed without error reporting: it can be the intended behaviour in
bogdanm	0:9b334a45a8ff	273	* case of update of a parameter of ADC_InitTypeDef on the fly,
bogdanm	0:9b334a45a8ff	274	* without disabling the other ADCs.
bogdanm	0:9b334a45a8ff	275	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	276	* @retval HAL status
bogdanm	0:9b334a45a8ff	277	*/
bogdanm	0:9b334a45a8ff	278	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	279	{
bogdanm	0:9b334a45a8ff	280	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282	ADC_Common_TypeDef *tmpADC_Common;
bogdanm	0:9b334a45a8ff	283	uint32_t tmpCFGR = 0;
bogdanm	0:9b334a45a8ff	284	uint32_t wait_loop_index = 0;
bogdanm	0:9b334a45a8ff	285
bogdanm	0:9b334a45a8ff	286	/* Check ADC handle */
bogdanm	0:9b334a45a8ff	287	if(hadc == NULL)
bogdanm	0:9b334a45a8ff	288	{
bogdanm	0:9b334a45a8ff	289	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	290	}
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/* Check the parameters */
bogdanm	0:9b334a45a8ff	293	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	294	assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
bogdanm	0:9b334a45a8ff	295	assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
bogdanm	0:9b334a45a8ff	296	assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
bogdanm	0:9b334a45a8ff	297	assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
bogdanm	0:9b334a45a8ff	298	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	299	assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
bogdanm	0:9b334a45a8ff	300	assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
bogdanm	0:9b334a45a8ff	301	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
bogdanm	0:9b334a45a8ff	302	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
bogdanm	0:9b334a45a8ff	303	assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
bogdanm	0:9b334a45a8ff	304	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
bogdanm	0:9b334a45a8ff	305	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
bogdanm	0:9b334a45a8ff	306
bogdanm	0:9b334a45a8ff	307	if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
bogdanm	0:9b334a45a8ff	308	{
bogdanm	0:9b334a45a8ff	309	assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
bogdanm	0:9b334a45a8ff	310	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	if (hadc->Init.DiscontinuousConvMode == ENABLE)
bogdanm	0:9b334a45a8ff	313	{
bogdanm	0:9b334a45a8ff	314	assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
bogdanm	0:9b334a45a8ff	315	}
bogdanm	0:9b334a45a8ff	316	}
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319	/* DISCEN and CONT bits can't be set at the same time */
bogdanm	0:9b334a45a8ff	320	assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
bogdanm	0:9b334a45a8ff	321
bogdanm	0:9b334a45a8ff	322
bogdanm	0:9b334a45a8ff	323	/* Actions performed only if ADC is coming from state reset: */
bogdanm	0:9b334a45a8ff	324	/* - Initialization of ADC MSP */
bogdanm	0:9b334a45a8ff	325	if (hadc->State == HAL_ADC_STATE_RESET)
bogdanm	0:9b334a45a8ff	326	{
bogdanm	0:9b334a45a8ff	327	/* Init the low level hardware */
bogdanm	0:9b334a45a8ff	328	HAL_ADC_MspInit(hadc);
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	331	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	/* Initialize Lock */
bogdanm	0:9b334a45a8ff	334	hadc->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	335	}
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	/* - Exit from deep-power-down mode and ADC voltage regulator enable */
bogdanm	0:9b334a45a8ff	339	/* Exit deep power down mode if still in that state */
bogdanm	0:9b334a45a8ff	340	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
bogdanm	0:9b334a45a8ff	341	{
bogdanm	0:9b334a45a8ff	342	/* Exit deep power down mode */
bogdanm	0:9b334a45a8ff	343	CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	/* System was in deep power down mode, calibration must
bogdanm	0:9b334a45a8ff	346	be relaunched or a previously saved calibration factor
bogdanm	0:9b334a45a8ff	347	re-applied once the ADC voltage regulator is enabled */
bogdanm	0:9b334a45a8ff	348	}
bogdanm	0:9b334a45a8ff	349
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
bogdanm	0:9b334a45a8ff	352	{
bogdanm	0:9b334a45a8ff	353	/* Enable ADC internal voltage regulator then
bogdanm	0:9b334a45a8ff	354	wait for start-up time */
bogdanm	0:9b334a45a8ff	355	SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
bogdanm	0:9b334a45a8ff	356	wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
bogdanm	0:9b334a45a8ff	357	while(wait_loop_index != 0)
bogdanm	0:9b334a45a8ff	358	{
bogdanm	0:9b334a45a8ff	359	wait_loop_index--;
bogdanm	0:9b334a45a8ff	360	}
bogdanm	0:9b334a45a8ff	361	}
bogdanm	0:9b334a45a8ff	362
bogdanm	0:9b334a45a8ff	363
bogdanm	0:9b334a45a8ff	364
bogdanm	0:9b334a45a8ff	365
bogdanm	0:9b334a45a8ff	366	/* Verification that ADC voltage regulator is correctly enabled, whether */
bogdanm	0:9b334a45a8ff	367	/* or not ADC is coming from state reset (if any potential problem of */
bogdanm	0:9b334a45a8ff	368	/* clocking, voltage regulator would not be enabled). */
bogdanm	0:9b334a45a8ff	369	if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
bogdanm	0:9b334a45a8ff	370	{
bogdanm	0:9b334a45a8ff	371	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	372	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	375	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	376
bogdanm	0:9b334a45a8ff	377	tmp_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	378	}
bogdanm	0:9b334a45a8ff	379
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	/* Configuration of ADC parameters if previous preliminary actions are */
bogdanm	0:9b334a45a8ff	382	/* correctly completed and if there is no conversion on going on regular */
bogdanm	0:9b334a45a8ff	383	/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
bogdanm	0:9b334a45a8ff	384	/* called to update a parameter on the fly). */
bogdanm	0:9b334a45a8ff	385	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
bogdanm	0:9b334a45a8ff	386	(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
bogdanm	0:9b334a45a8ff	387	{
bogdanm	0:9b334a45a8ff	388
bogdanm	0:9b334a45a8ff	389	/* Initialize the ADC state */
bogdanm	0:9b334a45a8ff	390	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	/* Configuration of common ADC parameters */
bogdanm	0:9b334a45a8ff	393
bogdanm	0:9b334a45a8ff	394	/* Pointer to the common control register */
bogdanm	0:9b334a45a8ff	395	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397
bogdanm	0:9b334a45a8ff	398	/* Parameters update conditioned to ADC state: */
bogdanm	0:9b334a45a8ff	399	/* Parameters that can be updated only when ADC is disabled: */
bogdanm	0:9b334a45a8ff	400	/* - clock configuration */
bogdanm	0:9b334a45a8ff	401	if ((ADC_IS_ENABLE(hadc) == RESET) &&
bogdanm	0:9b334a45a8ff	402	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
bogdanm	0:9b334a45a8ff	403	{
bogdanm	0:9b334a45a8ff	404	/* Reset configuration of ADC common register CCR: */
bogdanm	0:9b334a45a8ff	405	/* */
bogdanm	0:9b334a45a8ff	406	/* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
bogdanm	0:9b334a45a8ff	407	/* according to adc->Init.ClockPrescaler. It selects the clock */
bogdanm	0:9b334a45a8ff	408	/* source and sets the clock division factor. */
bogdanm	0:9b334a45a8ff	409	/* */
bogdanm	0:9b334a45a8ff	410	/* Some parameters of this register are not reset, since they are set */
bogdanm	0:9b334a45a8ff	411	/* by other functions and must be kept in case of usage of this */
bogdanm	0:9b334a45a8ff	412	/* function on the fly (update of a parameter of ADC_InitTypeDef */
bogdanm	0:9b334a45a8ff	413	/* without needing to reconfigure all other ADC groups/channels */
bogdanm	0:9b334a45a8ff	414	/* parameters): */
bogdanm	0:9b334a45a8ff	415	/* - multimode related parameters: MDMA, DMACFG, DELAY, DUAL (set */
bogdanm	0:9b334a45a8ff	416	/* into HAL_ADCEx_MultiModeConfigChannel() ) */
bogdanm	0:9b334a45a8ff	417	/* - internal measurement paths: Vbat, temperature sensor, Vref */
bogdanm	0:9b334a45a8ff	418	/* (set into HAL_ADC_ConfigChannel() or */
bogdanm	0:9b334a45a8ff	419	/* HAL_ADCEx_InjectedConfigChannel() ) */
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC\|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler);
bogdanm	0:9b334a45a8ff	422	}
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424
bogdanm	0:9b334a45a8ff	425	/* Configuration of ADC: */
bogdanm	0:9b334a45a8ff	426	/* - resolution Init.Resolution */
bogdanm	0:9b334a45a8ff	427	/* - data alignment Init.DataAlign */
bogdanm	0:9b334a45a8ff	428	/* - external trigger to start conversion Init.ExternalTrigConv */
bogdanm	0:9b334a45a8ff	429	/* - external trigger polarity Init.ExternalTrigConvEdge */
bogdanm	0:9b334a45a8ff	430	/* - continuous conversion mode Init.ContinuousConvMode */
bogdanm	0:9b334a45a8ff	431	/* - overrun Init.Overrun */
bogdanm	0:9b334a45a8ff	432	/* - discontinuous mode Init.DiscontinuousConvMode */
bogdanm	0:9b334a45a8ff	433	/* - discontinuous mode channel count Init.NbrOfDiscConversion */
bogdanm	0:9b334a45a8ff	434	tmpCFGR = ( ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) \|
bogdanm	0:9b334a45a8ff	435	hadc->Init.Overrun \|
bogdanm	0:9b334a45a8ff	436	hadc->Init.DataAlign \|
bogdanm	0:9b334a45a8ff	437	hadc->Init.Resolution \|
bogdanm	0:9b334a45a8ff	438	ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode) \|
bogdanm	0:9b334a45a8ff	439	ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
bogdanm	0:9b334a45a8ff	440
bogdanm	0:9b334a45a8ff	441	/* Enable external trigger if trigger selection is different of software */
bogdanm	0:9b334a45a8ff	442	/* start. */
bogdanm	0:9b334a45a8ff	443	/* - external trigger to start conversion Init.ExternalTrigConv */
bogdanm	0:9b334a45a8ff	444	/* - external trigger polarity Init.ExternalTrigConvEdge */
bogdanm	0:9b334a45a8ff	445	/* Note: parameter ExternalTrigConvEdge set to "trigger edge none" is */
bogdanm	0:9b334a45a8ff	446	/* equivalent to software start. */
bogdanm	0:9b334a45a8ff	447	if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
bogdanm	0:9b334a45a8ff	448	&& (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE))
bogdanm	0:9b334a45a8ff	449	{
bogdanm	0:9b334a45a8ff	450	tmpCFGR \|= ( hadc->Init.ExternalTrigConv \| hadc->Init.ExternalTrigConvEdge);
bogdanm	0:9b334a45a8ff	451	}
bogdanm	0:9b334a45a8ff	452
bogdanm	0:9b334a45a8ff	453	/* Update Configuration Register CFGR */
bogdanm	0:9b334a45a8ff	454	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
bogdanm	0:9b334a45a8ff	455
bogdanm	0:9b334a45a8ff	456
bogdanm	0:9b334a45a8ff	457	/* Parameters update conditioned to ADC state: */
bogdanm	0:9b334a45a8ff	458	/* Parameters that can be updated when ADC is disabled or enabled without */
bogdanm	0:9b334a45a8ff	459	/* conversion on going on regular and injected groups: */
bogdanm	0:9b334a45a8ff	460	/* - DMA continuous request Init.DMAContinuousRequests */
bogdanm	0:9b334a45a8ff	461	/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
bogdanm	0:9b334a45a8ff	462	/* - Oversampling parameters Init.Oversampling */
bogdanm	0:9b334a45a8ff	463	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	464	{
bogdanm	0:9b334a45a8ff	465	tmpCFGR = ( ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) \|
bogdanm	0:9b334a45a8ff	466	ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
bogdanm	0:9b334a45a8ff	467
bogdanm	0:9b334a45a8ff	468	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470
bogdanm	0:9b334a45a8ff	471	if (hadc->Init.OversamplingMode == ENABLE)
bogdanm	0:9b334a45a8ff	472	{
bogdanm	0:9b334a45a8ff	473	assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
bogdanm	0:9b334a45a8ff	474	assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
bogdanm	0:9b334a45a8ff	475	assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
bogdanm	0:9b334a45a8ff	476	assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478	if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
bogdanm	0:9b334a45a8ff	479	\|\| (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
bogdanm	0:9b334a45a8ff	480	{
bogdanm	0:9b334a45a8ff	481	/* Multi trigger is not applicable to software-triggered conversions */
bogdanm	0:9b334a45a8ff	482	assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
bogdanm	0:9b334a45a8ff	483	}
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485
bogdanm	0:9b334a45a8ff	486	/* Configuration of Oversampler: */
bogdanm	0:9b334a45a8ff	487	/* - Oversampling Ratio */
bogdanm	0:9b334a45a8ff	488	/* - Right bit shift */
bogdanm	0:9b334a45a8ff	489	/* - Triggered mode */
bogdanm	0:9b334a45a8ff	490	/* - Oversampling mode (continued/resumed) */
bogdanm	0:9b334a45a8ff	491	MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
bogdanm	0:9b334a45a8ff	492	ADC_CFGR2_ROVSE \|
bogdanm	0:9b334a45a8ff	493	hadc->Init.Oversampling.Ratio \|
bogdanm	0:9b334a45a8ff	494	hadc->Init.Oversampling.RightBitShift \|
bogdanm	0:9b334a45a8ff	495	hadc->Init.Oversampling.TriggeredMode \|
bogdanm	0:9b334a45a8ff	496	hadc->Init.Oversampling.OversamplingStopReset);
bogdanm	0:9b334a45a8ff	497	}
bogdanm	0:9b334a45a8ff	498	else
bogdanm	0:9b334a45a8ff	499	{
bogdanm	0:9b334a45a8ff	500	/* Disable Regular OverSampling */
bogdanm	0:9b334a45a8ff	501	CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
bogdanm	0:9b334a45a8ff	502	}
bogdanm	0:9b334a45a8ff	503
bogdanm	0:9b334a45a8ff	504
bogdanm	0:9b334a45a8ff	505	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
bogdanm	0:9b334a45a8ff	506
bogdanm	0:9b334a45a8ff	507
bogdanm	0:9b334a45a8ff	508
bogdanm	0:9b334a45a8ff	509
bogdanm	0:9b334a45a8ff	510	/* Configuration of regular group sequencer: */
bogdanm	0:9b334a45a8ff	511	/* - if scan mode is disabled, regular channels sequence length is set to */
bogdanm	0:9b334a45a8ff	512	/* 0x00: 1 channel converted (channel on regular rank 1) */
bogdanm	0:9b334a45a8ff	513	/* Parameter "NbrOfConversion" is discarded. */
bogdanm	0:9b334a45a8ff	514	/* Note: Scan mode is not present by hardware on this device, but */
bogdanm	0:9b334a45a8ff	515	/* emulated by software for alignment over all STM32 devices. */
bogdanm	0:9b334a45a8ff	516	/* - if scan mode is enabled, regular channels sequence length is set to */
bogdanm	0:9b334a45a8ff	517	/* parameter "NbrOfConversion" */
bogdanm	0:9b334a45a8ff	518
bogdanm	0:9b334a45a8ff	519	if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
bogdanm	0:9b334a45a8ff	520	{
bogdanm	0:9b334a45a8ff	521	/* Set number of ranks in regular group sequencer */
bogdanm	0:9b334a45a8ff	522	MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
bogdanm	0:9b334a45a8ff	523	}
bogdanm	0:9b334a45a8ff	524	else
bogdanm	0:9b334a45a8ff	525	{
bogdanm	0:9b334a45a8ff	526	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
bogdanm	0:9b334a45a8ff	527	}
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/* Initialize the ADC state */
bogdanm	0:9b334a45a8ff	531	/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	532	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	533	}
bogdanm	0:9b334a45a8ff	534	else
bogdanm	0:9b334a45a8ff	535	{
bogdanm	0:9b334a45a8ff	536	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	537	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	538
bogdanm	0:9b334a45a8ff	539	tmp_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	540	} /* if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) */
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543	/* Return function status */
bogdanm	0:9b334a45a8ff	544	return tmp_status;
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	}
bogdanm	0:9b334a45a8ff	547
bogdanm	0:9b334a45a8ff	548	/**
bogdanm	0:9b334a45a8ff	549	* @brief Deinitialize the ADC peripheral registers to their default reset
bogdanm	0:9b334a45a8ff	550	* values, with deinitialization of the ADC MSP.
bogdanm	0:9b334a45a8ff	551	* @note Keep in mind that all ADCs use the same clock: disabling
bogdanm	0:9b334a45a8ff	552	* the clock will reset all ADCs.
bogdanm	0:9b334a45a8ff	553	* @note By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by
bogdanm	0:9b334a45a8ff	554	* reducing the leakage currents and is particularly interesting before
bogdanm	0:9b334a45a8ff	555	* entering STOP 1 or STOP 2 modes.
bogdanm	0:9b334a45a8ff	556	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	557	* @retval HAL status
bogdanm	0:9b334a45a8ff	558	*/
bogdanm	0:9b334a45a8ff	559	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	560	{
bogdanm	0:9b334a45a8ff	561	ADC_Common_TypeDef *tmpADC_Common;
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	/* Check ADC handle */
bogdanm	0:9b334a45a8ff	564	if(hadc == NULL)
bogdanm	0:9b334a45a8ff	565	{
bogdanm	0:9b334a45a8ff	566	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	567	}
bogdanm	0:9b334a45a8ff	568
bogdanm	0:9b334a45a8ff	569	/* Check the parameters */
bogdanm	0:9b334a45a8ff	570	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	/* Change ADC state */
bogdanm	0:9b334a45a8ff	573	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	576	/* No check on ADC_ConversionStop() return status, if the conversion
bogdanm	0:9b334a45a8ff	577	stop failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
bogdanm	0:9b334a45a8ff	578	ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	/* Disable ADC peripheral if conversions are effectively stopped */
bogdanm	0:9b334a45a8ff	582	/* Flush register JSQR: reset the queue sequencer when injected */
bogdanm	0:9b334a45a8ff	583	/* queue sequencer is enabled and ADC disabled. */
bogdanm	0:9b334a45a8ff	584	/* The software and hardware triggers of the injected sequence are both */
bogdanm	0:9b334a45a8ff	585	/* internally disabled just after the completion of the last valid */
bogdanm	0:9b334a45a8ff	586	/* injected sequence. */
bogdanm	0:9b334a45a8ff	587	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
bogdanm	0:9b334a45a8ff	588
bogdanm	0:9b334a45a8ff	589	/* Disable the ADC peripheral */
bogdanm	0:9b334a45a8ff	590	/* No check on ADC_Disable() return status, if the ADC disabling process
bogdanm	0:9b334a45a8ff	591	failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
bogdanm	0:9b334a45a8ff	592	ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	593
bogdanm	0:9b334a45a8ff	594
bogdanm	0:9b334a45a8ff	595	/* ========== Reset ADC registers ========== */
bogdanm	0:9b334a45a8ff	596	/* Reset register IER */
bogdanm	0:9b334a45a8ff	597	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 \| ADC_IT_AWD2 \| ADC_IT_AWD1 \|
bogdanm	0:9b334a45a8ff	598	ADC_IT_JQOVF \| ADC_IT_OVR \|
bogdanm	0:9b334a45a8ff	599	ADC_IT_JEOS \| ADC_IT_JEOC \|
bogdanm	0:9b334a45a8ff	600	ADC_IT_EOS \| ADC_IT_EOC \|
bogdanm	0:9b334a45a8ff	601	ADC_IT_EOSMP \| ADC_IT_RDY ) );
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	/* Reset register ISR */
bogdanm	0:9b334a45a8ff	604	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 \| ADC_FLAG_AWD2 \| ADC_FLAG_AWD1 \|
bogdanm	0:9b334a45a8ff	605	ADC_FLAG_JQOVF \| ADC_FLAG_OVR \|
bogdanm	0:9b334a45a8ff	606	ADC_FLAG_JEOS \| ADC_FLAG_JEOC \|
bogdanm	0:9b334a45a8ff	607	ADC_FLAG_EOS \| ADC_FLAG_EOC \|
bogdanm	0:9b334a45a8ff	608	ADC_FLAG_EOSMP \| ADC_FLAG_RDY ) );
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	/* Reset register CR */
bogdanm	0:9b334a45a8ff	611	/* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
bogdanm	0:9b334a45a8ff	612	ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
bogdanm	0:9b334a45a8ff	613	no direct reset applicable.
bogdanm	0:9b334a45a8ff	614	Update CR register to reset value where doable by software */
bogdanm	0:9b334a45a8ff	615	CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN \| ADC_CR_ADCALDIF);
bogdanm	0:9b334a45a8ff	616	SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
bogdanm	0:9b334a45a8ff	617
bogdanm	0:9b334a45a8ff	618	/* Reset register CFGR */
bogdanm	0:9b334a45a8ff	619	CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH \| ADC_CFGR_JAUTO \| ADC_CFGR_JAWD1EN \|
bogdanm	0:9b334a45a8ff	620	ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL \| ADC_CFGR_JQM \|
bogdanm	0:9b334a45a8ff	621	ADC_CFGR_JDISCEN \| ADC_CFGR_DISCNUM \| ADC_CFGR_DISCEN \|
bogdanm	0:9b334a45a8ff	622	ADC_CFGR_AUTDLY \| ADC_CFGR_CONT \| ADC_CFGR_OVRMOD \|
bogdanm	0:9b334a45a8ff	623	ADC_CFGR_EXTEN \| ADC_CFGR_EXTSEL \| ADC_CFGR_ALIGN \|
bogdanm	0:9b334a45a8ff	624	ADC_CFGR_RES \| ADC_CFGR_DMACFG \| ADC_CFGR_DMAEN );
bogdanm	0:9b334a45a8ff	625	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	/* Reset register CFGR2 */
bogdanm	0:9b334a45a8ff	628	CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM \| ADC_CFGR2_TROVS \| ADC_CFGR2_OVSS \|
bogdanm	0:9b334a45a8ff	629	ADC_CFGR2_OVSR \| ADC_CFGR2_JOVSE \| ADC_CFGR2_ROVSE );
bogdanm	0:9b334a45a8ff	630
bogdanm	0:9b334a45a8ff	631	/* Reset register SMPR1 */
bogdanm	0:9b334a45a8ff	632	CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_SMP9 \| ADC_SMPR1_SMP8 \| ADC_SMPR1_SMP7 \|
bogdanm	0:9b334a45a8ff	633	ADC_SMPR1_SMP6 \| ADC_SMPR1_SMP5 \| ADC_SMPR1_SMP4 \|
bogdanm	0:9b334a45a8ff	634	ADC_SMPR1_SMP3 \| ADC_SMPR1_SMP2 \| ADC_SMPR1_SMP1 \|
bogdanm	0:9b334a45a8ff	635	ADC_SMPR1_SMP0 );
bogdanm	0:9b334a45a8ff	636
bogdanm	0:9b334a45a8ff	637	/* Reset register SMPR2 */
bogdanm	0:9b334a45a8ff	638	CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 \| ADC_SMPR2_SMP17 \| ADC_SMPR2_SMP16 \|
bogdanm	0:9b334a45a8ff	639	ADC_SMPR2_SMP15 \| ADC_SMPR2_SMP14 \| ADC_SMPR2_SMP13 \|
bogdanm	0:9b334a45a8ff	640	ADC_SMPR2_SMP12 \| ADC_SMPR2_SMP11 \| ADC_SMPR2_SMP10 );
bogdanm	0:9b334a45a8ff	641
bogdanm	0:9b334a45a8ff	642	/* Reset register TR1 */
bogdanm	0:9b334a45a8ff	643	CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 \| ADC_TR1_LT1);
bogdanm	0:9b334a45a8ff	644
bogdanm	0:9b334a45a8ff	645	/* Reset register TR2 */
bogdanm	0:9b334a45a8ff	646	CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 \| ADC_TR2_LT2);
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	/* Reset register TR3 */
bogdanm	0:9b334a45a8ff	649	CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 \| ADC_TR3_LT3);
bogdanm	0:9b334a45a8ff	650
bogdanm	0:9b334a45a8ff	651	/* Reset register SQR1 */
bogdanm	0:9b334a45a8ff	652	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 \| ADC_SQR1_SQ3 \| ADC_SQR1_SQ2 \|
bogdanm	0:9b334a45a8ff	653	ADC_SQR1_SQ1 \| ADC_SQR1_L);
bogdanm	0:9b334a45a8ff	654
bogdanm	0:9b334a45a8ff	655	/* Reset register SQR2 */
bogdanm	0:9b334a45a8ff	656	CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 \| ADC_SQR2_SQ8 \| ADC_SQR2_SQ7 \|
bogdanm	0:9b334a45a8ff	657	ADC_SQR2_SQ6 \| ADC_SQR2_SQ5);
bogdanm	0:9b334a45a8ff	658
bogdanm	0:9b334a45a8ff	659	/* Reset register SQR3 */
bogdanm	0:9b334a45a8ff	660	CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 \| ADC_SQR3_SQ13 \| ADC_SQR3_SQ12 \|
bogdanm	0:9b334a45a8ff	661	ADC_SQR3_SQ11 \| ADC_SQR3_SQ10);
bogdanm	0:9b334a45a8ff	662
bogdanm	0:9b334a45a8ff	663	/* Reset register SQR4 */
bogdanm	0:9b334a45a8ff	664	CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 \| ADC_SQR4_SQ15);
bogdanm	0:9b334a45a8ff	665
bogdanm	0:9b334a45a8ff	666	/* Register JSQR was reset when the ADC was disabled */
bogdanm	0:9b334a45a8ff	667
bogdanm	0:9b334a45a8ff	668	/* Reset register DR */
bogdanm	0:9b334a45a8ff	669	/* bits in access mode read only, no direct reset applicable*/
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	/* Reset register OFR1 */
bogdanm	0:9b334a45a8ff	672	CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN \| ADC_OFR1_OFFSET1_CH \| ADC_OFR1_OFFSET1);
bogdanm	0:9b334a45a8ff	673	/* Reset register OFR2 */
bogdanm	0:9b334a45a8ff	674	CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN \| ADC_OFR2_OFFSET2_CH \| ADC_OFR2_OFFSET2);
bogdanm	0:9b334a45a8ff	675	/* Reset register OFR3 */
bogdanm	0:9b334a45a8ff	676	CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN \| ADC_OFR3_OFFSET3_CH \| ADC_OFR3_OFFSET3);
bogdanm	0:9b334a45a8ff	677	/* Reset register OFR4 */
bogdanm	0:9b334a45a8ff	678	CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN \| ADC_OFR4_OFFSET4_CH \| ADC_OFR4_OFFSET4);
bogdanm	0:9b334a45a8ff	679
bogdanm	0:9b334a45a8ff	680	/* Reset registers JDR1, JDR2, JDR3, JDR4 */
bogdanm	0:9b334a45a8ff	681	/* bits in access mode read only, no direct reset applicable*/
bogdanm	0:9b334a45a8ff	682
bogdanm	0:9b334a45a8ff	683	/* Reset register AWD2CR */
bogdanm	0:9b334a45a8ff	684	CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
bogdanm	0:9b334a45a8ff	685
bogdanm	0:9b334a45a8ff	686	/* Reset register AWD3CR */
bogdanm	0:9b334a45a8ff	687	CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
bogdanm	0:9b334a45a8ff	688
bogdanm	0:9b334a45a8ff	689	/* Reset register DIFSEL */
bogdanm	0:9b334a45a8ff	690	CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692	/* Reset register CALFACT */
bogdanm	0:9b334a45a8ff	693	CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D \| ADC_CALFACT_CALFACT_S);
bogdanm	0:9b334a45a8ff	694
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697
bogdanm	0:9b334a45a8ff	698
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	/* ========== Reset common ADC registers ========== */
bogdanm	0:9b334a45a8ff	701
bogdanm	0:9b334a45a8ff	702	/* Software is allowed to change common parameters only when all the other
bogdanm	0:9b334a45a8ff	703	ADCs are disabled. */
bogdanm	0:9b334a45a8ff	704	if ((ADC_IS_ENABLE(hadc) == RESET) &&
bogdanm	0:9b334a45a8ff	705	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
bogdanm	0:9b334a45a8ff	706	{
bogdanm	0:9b334a45a8ff	707	/* Reset configuration of ADC common register CCR:
bogdanm	0:9b334a45a8ff	708	- clock mode: CKMODE, PRESCEN
bogdanm	0:9b334a45a8ff	709	- multimode related parameters: MDMA, DMACFG, DELAY, DUAL (set into
bogdanm	0:9b334a45a8ff	710	HAL_ADCEx_MultiModeConfigChannel() )
bogdanm	0:9b334a45a8ff	711	- internal measurement paths: Vbat, temperature sensor, Vref (set into
bogdanm	0:9b334a45a8ff	712	HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
bogdanm	0:9b334a45a8ff	713	*/
bogdanm	0:9b334a45a8ff	714	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	715
bogdanm	0:9b334a45a8ff	716	CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_CKMODE \|
bogdanm	0:9b334a45a8ff	717	ADC_CCR_PRESC \|
bogdanm	0:9b334a45a8ff	718	ADC_CCR_VBATEN \|
bogdanm	0:9b334a45a8ff	719	ADC_CCR_TSEN \|
bogdanm	0:9b334a45a8ff	720	ADC_CCR_VREFEN \|
bogdanm	0:9b334a45a8ff	721	ADC_CCR_MDMA \|
bogdanm	0:9b334a45a8ff	722	ADC_CCR_DMACFG \|
bogdanm	0:9b334a45a8ff	723	ADC_CCR_DELAY \|
bogdanm	0:9b334a45a8ff	724	ADC_CCR_DUAL );
bogdanm	0:9b334a45a8ff	725
bogdanm	0:9b334a45a8ff	726	}
bogdanm	0:9b334a45a8ff	727
bogdanm	0:9b334a45a8ff	728	/* DeInit the low level hardware.
bogdanm	0:9b334a45a8ff	729
bogdanm	0:9b334a45a8ff	730	For example:
bogdanm	0:9b334a45a8ff	731	__HAL_RCC_ADC_FORCE_RESET();
bogdanm	0:9b334a45a8ff	732	__HAL_RCC_ADC_RELEASE_RESET();
bogdanm	0:9b334a45a8ff	733	__HAL_RCC_ADC_CLK_DISABLE();
bogdanm	0:9b334a45a8ff	734
bogdanm	0:9b334a45a8ff	735	Keep in mind that all ADCs use the same clock: disabling
bogdanm	0:9b334a45a8ff	736	the clock will reset all ADCs.
bogdanm	0:9b334a45a8ff	737
bogdanm	0:9b334a45a8ff	738	*/
bogdanm	0:9b334a45a8ff	739	HAL_ADC_MspDeInit(hadc);
bogdanm	0:9b334a45a8ff	740
bogdanm	0:9b334a45a8ff	741	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	742	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	/* Reset injected channel configuration parameters */
bogdanm	0:9b334a45a8ff	745	hadc->InjectionConfig.ContextQueue = 0;
bogdanm	0:9b334a45a8ff	746	hadc->InjectionConfig.ChannelCount = 0;
bogdanm	0:9b334a45a8ff	747
bogdanm	0:9b334a45a8ff	748	/* Change ADC state */
bogdanm	0:9b334a45a8ff	749	hadc->State = HAL_ADC_STATE_RESET;
bogdanm	0:9b334a45a8ff	750
bogdanm	0:9b334a45a8ff	751	/* Process unlocked */
bogdanm	0:9b334a45a8ff	752	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	753
bogdanm	0:9b334a45a8ff	754
bogdanm	0:9b334a45a8ff	755	/* Return function status */
bogdanm	0:9b334a45a8ff	756	return HAL_OK;
bogdanm	0:9b334a45a8ff	757
bogdanm	0:9b334a45a8ff	758	}
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760	/**
bogdanm	0:9b334a45a8ff	761	* @brief Initialize the ADC MSP.
bogdanm	0:9b334a45a8ff	762	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	763	* @retval None
bogdanm	0:9b334a45a8ff	764	*/
bogdanm	0:9b334a45a8ff	765	__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	766	{
bogdanm	0:9b334a45a8ff	767	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	768	function HAL_ADC_MspInit must be implemented in the user file.
bogdanm	0:9b334a45a8ff	769	*/
bogdanm	0:9b334a45a8ff	770	}
bogdanm	0:9b334a45a8ff	771
bogdanm	0:9b334a45a8ff	772	/**
bogdanm	0:9b334a45a8ff	773	* @brief DeInitialize the ADC MSP.
bogdanm	0:9b334a45a8ff	774	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	775	* @note All ADCs use the same clock: disabling the clock will reset all ADCs.
bogdanm	0:9b334a45a8ff	776	* @retval None
bogdanm	0:9b334a45a8ff	777	*/
bogdanm	0:9b334a45a8ff	778	__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	779	{
bogdanm	0:9b334a45a8ff	780	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	781	function HAL_ADC_MspDeInit must be implemented in the user file.
bogdanm	0:9b334a45a8ff	782	*/
bogdanm	0:9b334a45a8ff	783	}
bogdanm	0:9b334a45a8ff	784
bogdanm	0:9b334a45a8ff	785	/**
bogdanm	0:9b334a45a8ff	786	* @}
bogdanm	0:9b334a45a8ff	787	*/
bogdanm	0:9b334a45a8ff	788
bogdanm	0:9b334a45a8ff	789	/** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
bogdanm	0:9b334a45a8ff	790	* @brief IO operation functions
bogdanm	0:9b334a45a8ff	791	*
bogdanm	0:9b334a45a8ff	792	@verbatim
bogdanm	0:9b334a45a8ff	793	===============================================================================
bogdanm	0:9b334a45a8ff	794	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	795	===============================================================================
bogdanm	0:9b334a45a8ff	796	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	797	(+) Start conversion of regular group.
bogdanm	0:9b334a45a8ff	798	(+) Stop conversion of regular group.
bogdanm	0:9b334a45a8ff	799	(+) Poll for conversion complete on regular group.
bogdanm	0:9b334a45a8ff	800	(+) Poll for conversion event.
bogdanm	0:9b334a45a8ff	801	(+) Get result of regular channel conversion.
bogdanm	0:9b334a45a8ff	802	(+) Start conversion of regular group and enable interruptions.
bogdanm	0:9b334a45a8ff	803	(+) Stop conversion of regular group and disable interruptions.
bogdanm	0:9b334a45a8ff	804	(+) Handle ADC interrupt request
bogdanm	0:9b334a45a8ff	805	(+) Start conversion of regular group and enable DMA transfer.
bogdanm	0:9b334a45a8ff	806	(+) Stop conversion of regular group and disable ADC DMA transfer.
bogdanm	0:9b334a45a8ff	807
bogdanm	0:9b334a45a8ff	808	@endverbatim
bogdanm	0:9b334a45a8ff	809	* @{
bogdanm	0:9b334a45a8ff	810	*/
bogdanm	0:9b334a45a8ff	811
bogdanm	0:9b334a45a8ff	812	/**
bogdanm	0:9b334a45a8ff	813	* @brief Enable ADC, start conversion of regular group.
bogdanm	0:9b334a45a8ff	814	* @note Interruptions enabled in this function: None.
bogdanm	0:9b334a45a8ff	815	* @note Case of multimode enabled:
bogdanm	0:9b334a45a8ff	816	* if ADC is Slave, ADC is enabled but conversion is not started,
bogdanm	0:9b334a45a8ff	817	* if ADC is master, ADC is enabled and multimode conversion is started.
bogdanm	0:9b334a45a8ff	818	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	819	* @retval HAL status
bogdanm	0:9b334a45a8ff	820	*/
bogdanm	0:9b334a45a8ff	821	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	822	{
bogdanm	0:9b334a45a8ff	823	ADC_TypeDef *tmpADC_Master;
bogdanm	0:9b334a45a8ff	824	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	825
bogdanm	0:9b334a45a8ff	826	/* Check the parameters */
bogdanm	0:9b334a45a8ff	827	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	828
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	/* if a regular conversion is already on-going (i.e. ADSTART is set),
bogdanm	0:9b334a45a8ff	831	don't restart the conversion. */
bogdanm	0:9b334a45a8ff	832	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
bogdanm	0:9b334a45a8ff	833	{
bogdanm	0:9b334a45a8ff	834	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	835	}
bogdanm	0:9b334a45a8ff	836	else
bogdanm	0:9b334a45a8ff	837	{
bogdanm	0:9b334a45a8ff	838	/* Process locked */
bogdanm	0:9b334a45a8ff	839	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	840
bogdanm	0:9b334a45a8ff	841	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	842	tmp_status = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/* Start conversion if ADC is effectively enabled */
bogdanm	0:9b334a45a8ff	845	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	846	{
bogdanm	0:9b334a45a8ff	847	/* State machine update: Check if an injected conversion is ongoing */
bogdanm	0:9b334a45a8ff	848	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
bogdanm	0:9b334a45a8ff	849	{
bogdanm	0:9b334a45a8ff	850	/* Reset ADC error code fields related to regular conversions only */
bogdanm	0:9b334a45a8ff	851	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR\|HAL_ADC_ERROR_DMA));
bogdanm	0:9b334a45a8ff	852	}
bogdanm	0:9b334a45a8ff	853	else
bogdanm	0:9b334a45a8ff	854	{
bogdanm	0:9b334a45a8ff	855	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	856	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	857	}
bogdanm	0:9b334a45a8ff	858	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
bogdanm	0:9b334a45a8ff	859	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_REG_EOC\|HAL_ADC_STATE_REG_OVR\|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
bogdanm	0:9b334a45a8ff	860
bogdanm	0:9b334a45a8ff	861	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
bogdanm	0:9b334a45a8ff	862	- by default if ADC is Master or Independent
bogdanm	0:9b334a45a8ff	863	- if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
bogdanm	0:9b334a45a8ff	864	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
bogdanm	0:9b334a45a8ff	865	{
bogdanm	0:9b334a45a8ff	866	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
bogdanm	0:9b334a45a8ff	867	}
bogdanm	0:9b334a45a8ff	868
bogdanm	0:9b334a45a8ff	869	/* Clear regular group conversion flag and overrun flag */
bogdanm	0:9b334a45a8ff	870	/* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm	0:9b334a45a8ff	871	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
bogdanm	0:9b334a45a8ff	872
bogdanm	0:9b334a45a8ff	873	/* Enable conversion of regular group. */
bogdanm	0:9b334a45a8ff	874	/* If software start has been selected, conversion starts immediately. */
bogdanm	0:9b334a45a8ff	875	/* If external trigger has been selected, conversion starts at next */
bogdanm	0:9b334a45a8ff	876	/* trigger event. */
bogdanm	0:9b334a45a8ff	877	/* Case of multimode enabled: */
bogdanm	0:9b334a45a8ff	878	/* - if ADC is slave and dual regular conversions are enabled, ADC is */
bogdanm	0:9b334a45a8ff	879	/* enabled only (conversion is not started), */
bogdanm	0:9b334a45a8ff	880	/* - if ADC is master, ADC is enabled and conversion is started. */
bogdanm	0:9b334a45a8ff	881	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
bogdanm	0:9b334a45a8ff	882	{
bogdanm	0:9b334a45a8ff	883	/* Set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set */
bogdanm	0:9b334a45a8ff	884	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
bogdanm	0:9b334a45a8ff	885	{
bogdanm	0:9b334a45a8ff	886	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	887	}
bogdanm	0:9b334a45a8ff	888	/* Process unlocked */
bogdanm	0:9b334a45a8ff	889	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	890	/* Start ADC */
bogdanm	0:9b334a45a8ff	891	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
bogdanm	0:9b334a45a8ff	892	}
bogdanm	0:9b334a45a8ff	893	else
bogdanm	0:9b334a45a8ff	894	{
bogdanm	0:9b334a45a8ff	895	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
bogdanm	0:9b334a45a8ff	896	/* if Master ADC JAUTO bit is set, update Slave State in setting
bogdanm	0:9b334a45a8ff	897	HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
bogdanm	0:9b334a45a8ff	898	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	899	if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
bogdanm	0:9b334a45a8ff	900	{
bogdanm	0:9b334a45a8ff	901	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	902
bogdanm	0:9b334a45a8ff	903	} /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
bogdanm	0:9b334a45a8ff	904	/* Process unlocked */
bogdanm	0:9b334a45a8ff	905	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	906	} /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) */
bogdanm	0:9b334a45a8ff	907	}
bogdanm	0:9b334a45a8ff	908
bogdanm	0:9b334a45a8ff	909	/* Return function status */
bogdanm	0:9b334a45a8ff	910	return tmp_status;
bogdanm	0:9b334a45a8ff	911	}
bogdanm	0:9b334a45a8ff	912	}
bogdanm	0:9b334a45a8ff	913
bogdanm	0:9b334a45a8ff	914	/**
bogdanm	0:9b334a45a8ff	915	* @brief Stop ADC conversion of regular and injected groups, disable ADC peripheral.
bogdanm	0:9b334a45a8ff	916	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	917	* @retval HAL status.
bogdanm	0:9b334a45a8ff	918	*/
bogdanm	0:9b334a45a8ff	919	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	920	{
bogdanm	0:9b334a45a8ff	921	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	/* Check the parameters */
bogdanm	0:9b334a45a8ff	924	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	925
bogdanm	0:9b334a45a8ff	926	/* Process locked */
bogdanm	0:9b334a45a8ff	927	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	/* 1. Stop potential regular and injected on-going conversions */
bogdanm	0:9b334a45a8ff	930	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	/* Disable ADC peripheral if conversions are effectively stopped */
bogdanm	0:9b334a45a8ff	933	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	934	{
bogdanm	0:9b334a45a8ff	935	/* 2. Disable the ADC peripheral */
bogdanm	0:9b334a45a8ff	936	tmp_status = ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	937
bogdanm	0:9b334a45a8ff	938	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	939	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	940	{
bogdanm	0:9b334a45a8ff	941	/* Change ADC state */
bogdanm	0:9b334a45a8ff	942	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	943	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	944	}
bogdanm	0:9b334a45a8ff	945	}
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	/* Process unlocked */
bogdanm	0:9b334a45a8ff	948	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950	/* Return function status */
bogdanm	0:9b334a45a8ff	951	return tmp_status;
bogdanm	0:9b334a45a8ff	952	}
bogdanm	0:9b334a45a8ff	953
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	/**
bogdanm	0:9b334a45a8ff	957	* @brief Wait for regular group conversion to be completed.
bogdanm	0:9b334a45a8ff	958	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	959	* @param Timeout: Timeout value in millisecond.
bogdanm	0:9b334a45a8ff	960	* @note Depending on hadc->Init.EOCSelection, EOS or EOC is
bogdanm	0:9b334a45a8ff	961	* checked and cleared depending on AUTDLY bit status.
bogdanm	0:9b334a45a8ff	962	* @note HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a
bogdanm	0:9b334a45a8ff	963	* DMA-managed conversions configuration: indeed, EOC is immediately
bogdanm	0:9b334a45a8ff	964	* reset by the DMA reading the DR register when the converted data is
bogdanm	0:9b334a45a8ff	965	* available. Therefore, EOC is set for a too short period to be
bogdanm	0:9b334a45a8ff	966	* reliably polled.
bogdanm	0:9b334a45a8ff	967	* @retval HAL status
bogdanm	0:9b334a45a8ff	968	*/
bogdanm	0:9b334a45a8ff	969	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	970	{
bogdanm	0:9b334a45a8ff	971	uint32_t tickstart;
bogdanm	0:9b334a45a8ff	972	uint32_t tmp_Flag_End = 0x00;
bogdanm	0:9b334a45a8ff	973	ADC_Common_TypeDef *tmpADC_Common;
bogdanm	0:9b334a45a8ff	974	ADC_TypeDef *tmpADC_Master;
bogdanm	0:9b334a45a8ff	975	uint32_t tmp_cfgr = 0x00;
bogdanm	0:9b334a45a8ff	976	uint32_t tmp_eos_raised = 0x01; /* by default, assume that EOS is set,
bogdanm	0:9b334a45a8ff	977	tmp_eos_raised will be corrected
bogdanm	0:9b334a45a8ff	978	accordingly during API execution */
bogdanm	0:9b334a45a8ff	979
bogdanm	0:9b334a45a8ff	980	/* Check the parameters */
bogdanm	0:9b334a45a8ff	981	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	982
bogdanm	0:9b334a45a8ff	983	/* If end of sequence selected */
bogdanm	0:9b334a45a8ff	984	if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
bogdanm	0:9b334a45a8ff	985	{
bogdanm	0:9b334a45a8ff	986	tmp_Flag_End = ADC_FLAG_EOS;
bogdanm	0:9b334a45a8ff	987	}
bogdanm	0:9b334a45a8ff	988	else /* end of conversion selected */
bogdanm	0:9b334a45a8ff	989	{
bogdanm	0:9b334a45a8ff	990	/* Check that the ADC is not in a DMA-based configuration. Otherwise,
bogdanm	0:9b334a45a8ff	991	returns an error. */
bogdanm	0:9b334a45a8ff	992
bogdanm	0:9b334a45a8ff	993	/* Check whether dual regular conversions are disabled or unavailable. */
bogdanm	0:9b334a45a8ff	994	if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	995	{
bogdanm	0:9b334a45a8ff	996	/* Check DMAEN bit in handle ADC CFGR register */
bogdanm	0:9b334a45a8ff	997	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET)
bogdanm	0:9b334a45a8ff	998	{
bogdanm	0:9b334a45a8ff	999	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	1000	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1001	}
bogdanm	0:9b334a45a8ff	1002	}
bogdanm	0:9b334a45a8ff	1003	else
bogdanm	0:9b334a45a8ff	1004	{
bogdanm	0:9b334a45a8ff	1005	/* Else need to check Common register CCR MDMA bit field. */
bogdanm	0:9b334a45a8ff	1006	/* Set pointer to the common control register */
bogdanm	0:9b334a45a8ff	1007	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	1008	if ((READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS)
bogdanm	0:9b334a45a8ff	1009	\|\| (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS))
bogdanm	0:9b334a45a8ff	1010	{
bogdanm	0:9b334a45a8ff	1011	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	1012	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1013	}
bogdanm	0:9b334a45a8ff	1014	}
bogdanm	0:9b334a45a8ff	1015
bogdanm	0:9b334a45a8ff	1016	/* no DMA transfer detected, polling ADC_FLAG_EOC is possible */
bogdanm	0:9b334a45a8ff	1017	tmp_Flag_End = ADC_FLAG_EOC;
bogdanm	0:9b334a45a8ff	1018	}
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	/* Get timeout */
bogdanm	0:9b334a45a8ff	1021	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/* Wait until End of Conversion or Sequence flag is raised */
bogdanm	0:9b334a45a8ff	1024	while (HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
bogdanm	0:9b334a45a8ff	1025	{
bogdanm	0:9b334a45a8ff	1026	/* Check if timeout is disabled (set to infinite wait) */
bogdanm	0:9b334a45a8ff	1027	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1028	{
bogdanm	0:9b334a45a8ff	1029	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	1030	{
bogdanm	0:9b334a45a8ff	1031	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
bogdanm	0:9b334a45a8ff	1032	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1033	}
bogdanm	0:9b334a45a8ff	1034	}
bogdanm	0:9b334a45a8ff	1035	}
bogdanm	0:9b334a45a8ff	1036
bogdanm	0:9b334a45a8ff	1037	/* Next, to clear the polled flag as well as to update the handle State,
bogdanm	0:9b334a45a8ff	1038	EOS is checked and the relevant configuration register is retrieved. */
bogdanm	0:9b334a45a8ff	1039	/* 1. Check whether or not EOS is set */
bogdanm	0:9b334a45a8ff	1040	if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_EOS))
bogdanm	0:9b334a45a8ff	1041	{
bogdanm	0:9b334a45a8ff	1042	tmp_eos_raised = 0;
bogdanm	0:9b334a45a8ff	1043	}
bogdanm	0:9b334a45a8ff	1044	/* 2. Check whether or not hadc is the handle of a Slave ADC with dual
bogdanm	0:9b334a45a8ff	1045	regular conversions enabled. */
bogdanm	0:9b334a45a8ff	1046	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
bogdanm	0:9b334a45a8ff	1047	{
bogdanm	0:9b334a45a8ff	1048	/* Retrieve handle ADC CFGR register */
bogdanm	0:9b334a45a8ff	1049	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
bogdanm	0:9b334a45a8ff	1050	}
bogdanm	0:9b334a45a8ff	1051	else
bogdanm	0:9b334a45a8ff	1052	{
bogdanm	0:9b334a45a8ff	1053	/* Retrieve Master ADC CFGR register */
bogdanm	0:9b334a45a8ff	1054	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	1055	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
bogdanm	0:9b334a45a8ff	1056	}
bogdanm	0:9b334a45a8ff	1057
bogdanm	0:9b334a45a8ff	1058	/* Clear polled flag */
bogdanm	0:9b334a45a8ff	1059	if (tmp_Flag_End == ADC_FLAG_EOS)
bogdanm	0:9b334a45a8ff	1060	{
bogdanm	0:9b334a45a8ff	1061	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
bogdanm	0:9b334a45a8ff	1062	}
bogdanm	0:9b334a45a8ff	1063	else
bogdanm	0:9b334a45a8ff	1064	{
bogdanm	0:9b334a45a8ff	1065
bogdanm	0:9b334a45a8ff	1066	/* Clear end of conversion EOC flag of regular group if low power feature */
bogdanm	0:9b334a45a8ff	1067	/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
bogdanm	0:9b334a45a8ff	1068	/* until data register is read using function HAL_ADC_GetValue(). */
bogdanm	0:9b334a45a8ff	1069	/* For regular groups, no new conversion will start before EOC is cleared.*/
bogdanm	0:9b334a45a8ff	1070	/* Note that 1. reading DR clears EOC. */
bogdanm	0:9b334a45a8ff	1071	/* 2. in MultiMode with dual regular conversions enabled, */
bogdanm	0:9b334a45a8ff	1072	/* Master AUTDLY bit must be checked */
bogdanm	0:9b334a45a8ff	1073	if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
bogdanm	0:9b334a45a8ff	1074	{
bogdanm	0:9b334a45a8ff	1075	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	1076	}
bogdanm	0:9b334a45a8ff	1077	}
bogdanm	0:9b334a45a8ff	1078
bogdanm	0:9b334a45a8ff	1079
bogdanm	0:9b334a45a8ff	1080	/* Update ADC state machine */
bogdanm	0:9b334a45a8ff	1081	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
bogdanm	0:9b334a45a8ff	1082	/* If 1. EOS is set
bogdanm	0:9b334a45a8ff	1083	2. conversions are software-triggered
bogdanm	0:9b334a45a8ff	1084	3. CONT bit is reset (that of handle ADC or Master ADC if applicable)
bogdanm	0:9b334a45a8ff	1085	Then regular conversions are over and HAL_ADC_STATE_REG_BUSY can be reset.
bogdanm	0:9b334a45a8ff	1086	4. additionally, if no injected conversions are on-going, HAL_ADC_STATE_READY
bogdanm	0:9b334a45a8ff	1087	can be set */
bogdanm	0:9b334a45a8ff	1088	if ((tmp_eos_raised)
bogdanm	0:9b334a45a8ff	1089	&& (ADC_IS_SOFTWARE_START_REGULAR(hadc))
bogdanm	0:9b334a45a8ff	1090	&& (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET))
bogdanm	0:9b334a45a8ff	1091	{
bogdanm	0:9b334a45a8ff	1092	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
bogdanm	0:9b334a45a8ff	1093	/* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	1094	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
bogdanm	0:9b334a45a8ff	1095	{
bogdanm	0:9b334a45a8ff	1096	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1097	}
bogdanm	0:9b334a45a8ff	1098	}
bogdanm	0:9b334a45a8ff	1099
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	/* Return API HAL status */
bogdanm	0:9b334a45a8ff	1102	return HAL_OK;
bogdanm	0:9b334a45a8ff	1103	}
bogdanm	0:9b334a45a8ff	1104
bogdanm	0:9b334a45a8ff	1105	/**
bogdanm	0:9b334a45a8ff	1106	* @brief Poll for ADC event.
bogdanm	0:9b334a45a8ff	1107	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1108	* @param EventType: the ADC event type.
bogdanm	0:9b334a45a8ff	1109	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1110	* @arg ADC_EOSMP_EVENT: ADC End of Sampling event
bogdanm	0:9b334a45a8ff	1111	* @arg ADC_AWD_EVENT: ADC Analog watchdog 1 event
bogdanm	0:9b334a45a8ff	1112	* @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event
bogdanm	0:9b334a45a8ff	1113	* @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event
bogdanm	0:9b334a45a8ff	1114	* @arg ADC_OVR_EVENT: ADC Overrun event
bogdanm	0:9b334a45a8ff	1115	* @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
bogdanm	0:9b334a45a8ff	1116	* @param Timeout: Timeout value in millisecond.
bogdanm	0:9b334a45a8ff	1117	* @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
bogdanm	0:9b334a45a8ff	1118	* Indeed, the latter is reset only if hadc->Init.Overrun field is set
bogdanm	0:9b334a45a8ff	1119	* to ADC_OVR_DATA_OVERWRITTEN. Otherwise, DR may be potentially overwritten
bogdanm	0:9b334a45a8ff	1120	* by a new converted data as soon as OVR is cleared.
bogdanm	0:9b334a45a8ff	1121	* To reset OVR flag once the preserved data is retrieved, the user can resort
bogdanm	0:9b334a45a8ff	1122	* to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
bogdanm	0:9b334a45a8ff	1123	* @retval HAL status
bogdanm	0:9b334a45a8ff	1124	*/
bogdanm	0:9b334a45a8ff	1125	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1126	{
bogdanm	0:9b334a45a8ff	1127	uint32_t tickstart;
bogdanm	0:9b334a45a8ff	1128
bogdanm	0:9b334a45a8ff	1129	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1130	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1131	assert_param(IS_ADC_EVENT_TYPE(EventType));
bogdanm	0:9b334a45a8ff	1132
bogdanm	0:9b334a45a8ff	1133	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1134
bogdanm	0:9b334a45a8ff	1135	/* Check selected event flag */
bogdanm	0:9b334a45a8ff	1136	while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
bogdanm	0:9b334a45a8ff	1137	{
bogdanm	0:9b334a45a8ff	1138	/* Check if timeout is disabled (set to infinite wait) */
bogdanm	0:9b334a45a8ff	1139	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1140	{
bogdanm	0:9b334a45a8ff	1141	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	1142	{
bogdanm	0:9b334a45a8ff	1143	/* Update ADC state machine to timeout */
bogdanm	0:9b334a45a8ff	1144	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1147	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1148
bogdanm	0:9b334a45a8ff	1149	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1150	}
bogdanm	0:9b334a45a8ff	1151	}
bogdanm	0:9b334a45a8ff	1152	}
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	switch(EventType)
bogdanm	0:9b334a45a8ff	1156	{
bogdanm	0:9b334a45a8ff	1157	/* End Of Sampling event */
bogdanm	0:9b334a45a8ff	1158	case ADC_EOSMP_EVENT:
bogdanm	0:9b334a45a8ff	1159	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1160	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
bogdanm	0:9b334a45a8ff	1161
bogdanm	0:9b334a45a8ff	1162	/* Clear the End Of Sampling flag */
bogdanm	0:9b334a45a8ff	1163	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	break;
bogdanm	0:9b334a45a8ff	1166
bogdanm	0:9b334a45a8ff	1167	/* Analog watchdog (level out of window) event */
bogdanm	0:9b334a45a8ff	1168	/* Note: In case of several analog watchdog enabled, if needed to know */
bogdanm	0:9b334a45a8ff	1169	/* which one triggered and on which ADCx, test ADC state of Analog Watchdog */
bogdanm	0:9b334a45a8ff	1170	/* flags HAL_ADC_STATE_AWD/2/3 function. */
bogdanm	0:9b334a45a8ff	1171	/* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) " */
bogdanm	0:9b334a45a8ff	1172	/* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)" */
bogdanm	0:9b334a45a8ff	1173	/* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)" */
bogdanm	0:9b334a45a8ff	1174	case ADC_AWD_EVENT:
bogdanm	0:9b334a45a8ff	1175	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1176	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
bogdanm	0:9b334a45a8ff	1177
bogdanm	0:9b334a45a8ff	1178	/* Clear ADC analog watchdog flag */
bogdanm	0:9b334a45a8ff	1179	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
bogdanm	0:9b334a45a8ff	1180
bogdanm	0:9b334a45a8ff	1181	break;
bogdanm	0:9b334a45a8ff	1182
bogdanm	0:9b334a45a8ff	1183	/* Check analog watchdog 2 flag */
bogdanm	0:9b334a45a8ff	1184	case ADC_AWD2_EVENT:
bogdanm	0:9b334a45a8ff	1185	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1186	SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
bogdanm	0:9b334a45a8ff	1187
bogdanm	0:9b334a45a8ff	1188	/* Clear ADC analog watchdog flag */
bogdanm	0:9b334a45a8ff	1189	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
bogdanm	0:9b334a45a8ff	1190
bogdanm	0:9b334a45a8ff	1191	break;
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	/* Check analog watchdog 3 flag */
bogdanm	0:9b334a45a8ff	1194	case ADC_AWD3_EVENT:
bogdanm	0:9b334a45a8ff	1195	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1196	SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
bogdanm	0:9b334a45a8ff	1197
bogdanm	0:9b334a45a8ff	1198	/* Clear ADC analog watchdog flag */
bogdanm	0:9b334a45a8ff	1199	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
bogdanm	0:9b334a45a8ff	1200
bogdanm	0:9b334a45a8ff	1201	break;
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	/* Injected context queue overflow event */
bogdanm	0:9b334a45a8ff	1204	case ADC_JQOVF_EVENT:
bogdanm	0:9b334a45a8ff	1205	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1206	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
bogdanm	0:9b334a45a8ff	1207
bogdanm	0:9b334a45a8ff	1208	/* Set ADC error code to Injected context queue overflow */
bogdanm	0:9b334a45a8ff	1209	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
bogdanm	0:9b334a45a8ff	1210
bogdanm	0:9b334a45a8ff	1211	/* Clear ADC Injected context queue overflow flag */
bogdanm	0:9b334a45a8ff	1212	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
bogdanm	0:9b334a45a8ff	1213
bogdanm	0:9b334a45a8ff	1214	break;
bogdanm	0:9b334a45a8ff	1215
bogdanm	0:9b334a45a8ff	1216	/* Overrun event */
bogdanm	0:9b334a45a8ff	1217	default: /* Case ADC_OVR_EVENT */
bogdanm	0:9b334a45a8ff	1218	/* If overrun is set to overwrite previous data, overrun event is not */
bogdanm	0:9b334a45a8ff	1219	/* considered as an error. */
bogdanm	0:9b334a45a8ff	1220	/* (cf ref manual "Managing conversions without using the DMA and without */
bogdanm	0:9b334a45a8ff	1221	/* overrun ") */
bogdanm	0:9b334a45a8ff	1222	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
bogdanm	0:9b334a45a8ff	1223	{
bogdanm	0:9b334a45a8ff	1224	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1225	SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227	/* Set ADC error code to overrun */
bogdanm	0:9b334a45a8ff	1228	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
bogdanm	0:9b334a45a8ff	1229	}
bogdanm	0:9b334a45a8ff	1230	else
bogdanm	0:9b334a45a8ff	1231	{
bogdanm	0:9b334a45a8ff	1232	/* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
bogdanm	0:9b334a45a8ff	1233	otherwise, DR is potentially overwritten by new converted data as soon
bogdanm	0:9b334a45a8ff	1234	as OVR is cleared. */
bogdanm	0:9b334a45a8ff	1235	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
bogdanm	0:9b334a45a8ff	1236	}
bogdanm	0:9b334a45a8ff	1237	break;
bogdanm	0:9b334a45a8ff	1238	}
bogdanm	0:9b334a45a8ff	1239
bogdanm	0:9b334a45a8ff	1240	/* Return API HAL status */
bogdanm	0:9b334a45a8ff	1241	return HAL_OK;
bogdanm	0:9b334a45a8ff	1242	}
bogdanm	0:9b334a45a8ff	1243
bogdanm	0:9b334a45a8ff	1244
bogdanm	0:9b334a45a8ff	1245	/**
bogdanm	0:9b334a45a8ff	1246	* @brief Enable ADC, start conversion of regular group with interruption.
bogdanm	0:9b334a45a8ff	1247	* @note Interruptions enabled in this function according to initialization
bogdanm	0:9b334a45a8ff	1248	* setting : EOC (end of conversion), EOS (end of sequence),
bogdanm	0:9b334a45a8ff	1249	* OVR overrun.
bogdanm	0:9b334a45a8ff	1250	* Each of these interruptions has its dedicated callback function.
bogdanm	0:9b334a45a8ff	1251	* @note Case of multimode enabled:
bogdanm	0:9b334a45a8ff	1252	* HAL_ADC_Start_IT() must be called for ADC Slave first, then for
bogdanm	0:9b334a45a8ff	1253	* ADC Master.
bogdanm	0:9b334a45a8ff	1254	* For ADC Slave, ADC is enabled only (conversion is not started).
bogdanm	0:9b334a45a8ff	1255	* For ADC Master, ADC is enabled and multimode conversion is started.
bogdanm	0:9b334a45a8ff	1256	* @note To guarantee a proper reset of all interruptions once all the needed
bogdanm	0:9b334a45a8ff	1257	* conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
bogdanm	0:9b334a45a8ff	1258	* a correct stop of the IT-based conversions.
bogdanm	0:9b334a45a8ff	1259	* @note By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling
bogdanm	0:9b334a45a8ff	1260	* interruption. If required (e.g. in case of oversampling with trigger
bogdanm	0:9b334a45a8ff	1261	* mode), the user must
bogdanm	0:9b334a45a8ff	1262	* 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
bogdanm	0:9b334a45a8ff	1263	* 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
bogdanm	0:9b334a45a8ff	1264	* before calling HAL_ADC_Start_IT().
bogdanm	0:9b334a45a8ff	1265	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1266	* @retval HAL status
bogdanm	0:9b334a45a8ff	1267	*/
bogdanm	0:9b334a45a8ff	1268	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1269	{
bogdanm	0:9b334a45a8ff	1270	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1271	ADC_TypeDef *tmpADC_Master;
bogdanm	0:9b334a45a8ff	1272
bogdanm	0:9b334a45a8ff	1273	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1274	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	/* if a regular conversion is already on-going (i.e. ADSTART is set),
bogdanm	0:9b334a45a8ff	1277	don't restart the conversion. */
bogdanm	0:9b334a45a8ff	1278	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
bogdanm	0:9b334a45a8ff	1279	{
bogdanm	0:9b334a45a8ff	1280	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1281	}
bogdanm	0:9b334a45a8ff	1282	else
bogdanm	0:9b334a45a8ff	1283	{
bogdanm	0:9b334a45a8ff	1284	/* Process locked */
bogdanm	0:9b334a45a8ff	1285	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1288	tmp_status = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	1289
bogdanm	0:9b334a45a8ff	1290	/* Start conversion if ADC is effectively enabled */
bogdanm	0:9b334a45a8ff	1291	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1292	{
bogdanm	0:9b334a45a8ff	1293	/* State machine update: Check if an injected conversion is ongoing */
bogdanm	0:9b334a45a8ff	1294	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
bogdanm	0:9b334a45a8ff	1295	{
bogdanm	0:9b334a45a8ff	1296	/* Reset ADC error code fields related to regular conversions only */
bogdanm	0:9b334a45a8ff	1297	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR\|HAL_ADC_ERROR_DMA));
bogdanm	0:9b334a45a8ff	1298	}
bogdanm	0:9b334a45a8ff	1299	else
bogdanm	0:9b334a45a8ff	1300	{
bogdanm	0:9b334a45a8ff	1301	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	1302	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	1303	}
bogdanm	0:9b334a45a8ff	1304	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
bogdanm	0:9b334a45a8ff	1305	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_REG_EOC\|HAL_ADC_STATE_REG_OVR\|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
bogdanm	0:9b334a45a8ff	1306
bogdanm	0:9b334a45a8ff	1307	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
bogdanm	0:9b334a45a8ff	1308	- by default if ADC is Master or Independent
bogdanm	0:9b334a45a8ff	1309	- if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
bogdanm	0:9b334a45a8ff	1310	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
bogdanm	0:9b334a45a8ff	1311	{
bogdanm	0:9b334a45a8ff	1312	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
bogdanm	0:9b334a45a8ff	1313	}
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	/* Clear regular group conversion flag and overrun flag */
bogdanm	0:9b334a45a8ff	1316	/* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm	0:9b334a45a8ff	1317	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
bogdanm	0:9b334a45a8ff	1318
bogdanm	0:9b334a45a8ff	1319	/* By default, disable all interruptions before enabling the desired ones */
bogdanm	0:9b334a45a8ff	1320	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
bogdanm	0:9b334a45a8ff	1321
bogdanm	0:9b334a45a8ff	1322	/* Enable required interruptions */
bogdanm	0:9b334a45a8ff	1323	switch(hadc->Init.EOCSelection)
bogdanm	0:9b334a45a8ff	1324	{
bogdanm	0:9b334a45a8ff	1325	case ADC_EOC_SEQ_CONV:
bogdanm	0:9b334a45a8ff	1326	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
bogdanm	0:9b334a45a8ff	1327	break;
bogdanm	0:9b334a45a8ff	1328	/* case ADC_EOC_SINGLE_CONV */
bogdanm	0:9b334a45a8ff	1329	default:
bogdanm	0:9b334a45a8ff	1330	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	1331	break;
bogdanm	0:9b334a45a8ff	1332	}
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	/* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
bogdanm	0:9b334a45a8ff	1335	ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
bogdanm	0:9b334a45a8ff	1336	behavior and no CPU time is lost for a non-processed interruption */
bogdanm	0:9b334a45a8ff	1337	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
bogdanm	0:9b334a45a8ff	1338	{
bogdanm	0:9b334a45a8ff	1339	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	1340	}
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	/* Enable conversion of regular group. */
bogdanm	0:9b334a45a8ff	1343	/* If software start has been selected, conversion starts immediately. */
bogdanm	0:9b334a45a8ff	1344	/* If external trigger has been selected, conversion starts at next */
bogdanm	0:9b334a45a8ff	1345	/* trigger event. */
bogdanm	0:9b334a45a8ff	1346	/* Case of multimode enabled: */
bogdanm	0:9b334a45a8ff	1347	/* - if ADC is slave and dual regular conversions are enabled, ADC is */
bogdanm	0:9b334a45a8ff	1348	/* enabled only (conversion is not started), */
bogdanm	0:9b334a45a8ff	1349	/* - if ADC is master, ADC is enabled and conversion is started. */
bogdanm	0:9b334a45a8ff	1350	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) )
bogdanm	0:9b334a45a8ff	1351	{
bogdanm	0:9b334a45a8ff	1352	/* Set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set */
bogdanm	0:9b334a45a8ff	1353	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
bogdanm	0:9b334a45a8ff	1354	{
bogdanm	0:9b334a45a8ff	1355	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	1356
bogdanm	0:9b334a45a8ff	1357	/* Enable as well injected interruptions in case
bogdanm	0:9b334a45a8ff	1358	HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
bogdanm	0:9b334a45a8ff	1359	allows to start regular and injected conversions when JAUTO is
bogdanm	0:9b334a45a8ff	1360	set with a single call to HAL_ADC_Start_IT() */
bogdanm	0:9b334a45a8ff	1361	switch(hadc->Init.EOCSelection)
bogdanm	0:9b334a45a8ff	1362	{
bogdanm	0:9b334a45a8ff	1363	case ADC_EOC_SEQ_CONV:
bogdanm	0:9b334a45a8ff	1364	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
bogdanm	0:9b334a45a8ff	1365	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
bogdanm	0:9b334a45a8ff	1366	break;
bogdanm	0:9b334a45a8ff	1367	/* case ADC_EOC_SINGLE_CONV */
bogdanm	0:9b334a45a8ff	1368	default:
bogdanm	0:9b334a45a8ff	1369	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
bogdanm	0:9b334a45a8ff	1370	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
bogdanm	0:9b334a45a8ff	1371	break;
bogdanm	0:9b334a45a8ff	1372	}
bogdanm	0:9b334a45a8ff	1373	} /* if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) */
bogdanm	0:9b334a45a8ff	1374	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1375	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1376	/* Start ADC */
bogdanm	0:9b334a45a8ff	1377	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
bogdanm	0:9b334a45a8ff	1378	}
bogdanm	0:9b334a45a8ff	1379	else
bogdanm	0:9b334a45a8ff	1380	{
bogdanm	0:9b334a45a8ff	1381	/* hadc is the handle of a Slave ADC with dual regular conversions
bogdanm	0:9b334a45a8ff	1382	enabled. Therefore, ADC_CR_ADSTART is NOT set */
bogdanm	0:9b334a45a8ff	1383	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
bogdanm	0:9b334a45a8ff	1384	/* if Master ADC JAUTO bit is set, Slave injected interruptions
bogdanm	0:9b334a45a8ff	1385	are enabled nevertheless (for same reason as above) */
bogdanm	0:9b334a45a8ff	1386	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	1387	if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
bogdanm	0:9b334a45a8ff	1388	{
bogdanm	0:9b334a45a8ff	1389	/* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
bogdanm	0:9b334a45a8ff	1390	and in resetting HAL_ADC_STATE_INJ_EOC bit */
bogdanm	0:9b334a45a8ff	1391	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	1392	/* Next, set Slave injected interruptions */
bogdanm	0:9b334a45a8ff	1393	switch(hadc->Init.EOCSelection)
bogdanm	0:9b334a45a8ff	1394	{
bogdanm	0:9b334a45a8ff	1395	case ADC_EOC_SEQ_CONV:
bogdanm	0:9b334a45a8ff	1396	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
bogdanm	0:9b334a45a8ff	1397	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
bogdanm	0:9b334a45a8ff	1398	break;
bogdanm	0:9b334a45a8ff	1399	/* case ADC_EOC_SINGLE_CONV */
bogdanm	0:9b334a45a8ff	1400	default:
bogdanm	0:9b334a45a8ff	1401	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
bogdanm	0:9b334a45a8ff	1402	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
bogdanm	0:9b334a45a8ff	1403	break;
bogdanm	0:9b334a45a8ff	1404	}
bogdanm	0:9b334a45a8ff	1405	} /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
bogdanm	0:9b334a45a8ff	1406	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1407	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1408	} /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) ) */
bogdanm	0:9b334a45a8ff	1409	} /* if (tmp_status == HAL_OK) */
bogdanm	0:9b334a45a8ff	1410	else
bogdanm	0:9b334a45a8ff	1411	{
bogdanm	0:9b334a45a8ff	1412	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1413	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1414	}
bogdanm	0:9b334a45a8ff	1415
bogdanm	0:9b334a45a8ff	1416	/* Return function status */
bogdanm	0:9b334a45a8ff	1417	return tmp_status;
bogdanm	0:9b334a45a8ff	1418
bogdanm	0:9b334a45a8ff	1419	}
bogdanm	0:9b334a45a8ff	1420	}
bogdanm	0:9b334a45a8ff	1421
bogdanm	0:9b334a45a8ff	1422
bogdanm	0:9b334a45a8ff	1423
bogdanm	0:9b334a45a8ff	1424	/**
bogdanm	0:9b334a45a8ff	1425	* @brief Stop ADC conversion of regular groups when interruptions are enabled.
bogdanm	0:9b334a45a8ff	1426	* @note Stop as well injected conversions and disable ADC peripheral.
bogdanm	0:9b334a45a8ff	1427	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1428	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1429	*/
bogdanm	0:9b334a45a8ff	1430	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1431	{
bogdanm	0:9b334a45a8ff	1432	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1435	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1436
bogdanm	0:9b334a45a8ff	1437	/* Process locked */
bogdanm	0:9b334a45a8ff	1438	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1439
bogdanm	0:9b334a45a8ff	1440	/* 1. Stop potential regular and injected on-going conversions */
bogdanm	0:9b334a45a8ff	1441	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
bogdanm	0:9b334a45a8ff	1442
bogdanm	0:9b334a45a8ff	1443	/* Disable ADC peripheral if conversions are effectively stopped */
bogdanm	0:9b334a45a8ff	1444	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1445	{
bogdanm	0:9b334a45a8ff	1446	/* Disable all interrupts */
bogdanm	0:9b334a45a8ff	1447	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	/* 2. Disable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1450	tmp_status = ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	1451
bogdanm	0:9b334a45a8ff	1452	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	1453	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1454	{
bogdanm	0:9b334a45a8ff	1455	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1456	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	1457	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1458	}
bogdanm	0:9b334a45a8ff	1459	}
bogdanm	0:9b334a45a8ff	1460
bogdanm	0:9b334a45a8ff	1461	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1462	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1463
bogdanm	0:9b334a45a8ff	1464	/* Return function status */
bogdanm	0:9b334a45a8ff	1465	return tmp_status;
bogdanm	0:9b334a45a8ff	1466	}
bogdanm	0:9b334a45a8ff	1467
bogdanm	0:9b334a45a8ff	1468
bogdanm	0:9b334a45a8ff	1469	/**
bogdanm	0:9b334a45a8ff	1470	* @brief Enable ADC, start conversion of regular group and transfer result through DMA.
bogdanm	0:9b334a45a8ff	1471	* @note Interruptions enabled in this function:
bogdanm	0:9b334a45a8ff	1472	* overrun (if applicable), DMA half transfer, DMA transfer complete.
bogdanm	0:9b334a45a8ff	1473	* Each of these interruptions has its dedicated callback function.
bogdanm	0:9b334a45a8ff	1474	* @note Case of multimode enabled: HAL_ADC_Start_DMA() is for single-ADC
bogdanm	0:9b334a45a8ff	1475	* mode only. For multimode, use the dedicated HAL_ADCEx_MultiModeStart_DMA() function.
bogdanm	0:9b334a45a8ff	1476	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1477	* @param pData: Destination Buffer address.
bogdanm	0:9b334a45a8ff	1478	* @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
bogdanm	0:9b334a45a8ff	1479	* @retval None
bogdanm	0:9b334a45a8ff	1480	*/
bogdanm	0:9b334a45a8ff	1481	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
bogdanm	0:9b334a45a8ff	1482	{
bogdanm	0:9b334a45a8ff	1483	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1484
bogdanm	0:9b334a45a8ff	1485	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1486	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1487
bogdanm	0:9b334a45a8ff	1488	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
bogdanm	0:9b334a45a8ff	1489	{
bogdanm	0:9b334a45a8ff	1490	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1491	}
bogdanm	0:9b334a45a8ff	1492	else
bogdanm	0:9b334a45a8ff	1493	{
bogdanm	0:9b334a45a8ff	1494
bogdanm	0:9b334a45a8ff	1495	/* Process locked */
bogdanm	0:9b334a45a8ff	1496	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1497
bogdanm	0:9b334a45a8ff	1498	/* Ensure that dual regular conversions are not enabled or unavailable. */
bogdanm	0:9b334a45a8ff	1499	/* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
bogdanm	0:9b334a45a8ff	1500	if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1501	{
bogdanm	0:9b334a45a8ff	1502	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1503	tmp_status = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	/* Start conversion if ADC is effectively enabled */
bogdanm	0:9b334a45a8ff	1506	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1507	{
bogdanm	0:9b334a45a8ff	1508	/* State machine update: Check if an injected conversion is ongoing */
bogdanm	0:9b334a45a8ff	1509	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
bogdanm	0:9b334a45a8ff	1510	{
bogdanm	0:9b334a45a8ff	1511	/* Reset ADC error code fields related to regular conversions only */
bogdanm	0:9b334a45a8ff	1512	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR\|HAL_ADC_ERROR_DMA));
bogdanm	0:9b334a45a8ff	1513	}
bogdanm	0:9b334a45a8ff	1514	else
bogdanm	0:9b334a45a8ff	1515	{
bogdanm	0:9b334a45a8ff	1516	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	1517	ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	1518	}
bogdanm	0:9b334a45a8ff	1519	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
bogdanm	0:9b334a45a8ff	1520	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_REG_EOC\|HAL_ADC_STATE_REG_OVR\|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
bogdanm	0:9b334a45a8ff	1521
bogdanm	0:9b334a45a8ff	1522	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
bogdanm	0:9b334a45a8ff	1523	- by default if ADC is Master or Independent
bogdanm	0:9b334a45a8ff	1524	- if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
bogdanm	0:9b334a45a8ff	1525	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
bogdanm	0:9b334a45a8ff	1526	{
bogdanm	0:9b334a45a8ff	1527	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
bogdanm	0:9b334a45a8ff	1528	}
bogdanm	0:9b334a45a8ff	1529
bogdanm	0:9b334a45a8ff	1530	/* Set the DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1531	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
bogdanm	0:9b334a45a8ff	1532
bogdanm	0:9b334a45a8ff	1533	/* Set the DMA half transfer complete callback */
bogdanm	0:9b334a45a8ff	1534	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
bogdanm	0:9b334a45a8ff	1535
bogdanm	0:9b334a45a8ff	1536	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1537	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
bogdanm	0:9b334a45a8ff	1538
bogdanm	0:9b334a45a8ff	1539
bogdanm	0:9b334a45a8ff	1540	/* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
bogdanm	0:9b334a45a8ff	1541	/* ADC start (in case of SW start): */
bogdanm	0:9b334a45a8ff	1542
bogdanm	0:9b334a45a8ff	1543	/* Clear regular group conversion flag and overrun flag */
bogdanm	0:9b334a45a8ff	1544	/* (To ensure of no unknown state from potential previous ADC */
bogdanm	0:9b334a45a8ff	1545	/* operations) */
bogdanm	0:9b334a45a8ff	1546	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
bogdanm	0:9b334a45a8ff	1547
bogdanm	0:9b334a45a8ff	1548	/* With DMA, overrun event is always considered as an error even if
bogdanm	0:9b334a45a8ff	1549	hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
bogdanm	0:9b334a45a8ff	1550	ADC_IT_OVR is enabled. */
bogdanm	0:9b334a45a8ff	1551	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	1552
bogdanm	0:9b334a45a8ff	1553
bogdanm	0:9b334a45a8ff	1554	/* Enable ADC DMA mode */
bogdanm	0:9b334a45a8ff	1555	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
bogdanm	0:9b334a45a8ff	1556
bogdanm	0:9b334a45a8ff	1557	/* Start the DMA channel */
bogdanm	0:9b334a45a8ff	1558	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1559
bogdanm	0:9b334a45a8ff	1560	/* Enable conversion of regular group. */
bogdanm	0:9b334a45a8ff	1561	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1562	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1563	/* If software start has been selected, conversion starts immediately. */
bogdanm	0:9b334a45a8ff	1564	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	1565	/* trigger event. */
bogdanm	0:9b334a45a8ff	1566	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
bogdanm	0:9b334a45a8ff	1567
bogdanm	0:9b334a45a8ff	1568	}
bogdanm	0:9b334a45a8ff	1569	else
bogdanm	0:9b334a45a8ff	1570	{
bogdanm	0:9b334a45a8ff	1571	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1572	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1573	} /* if (tmp_status == HAL_OK) */
bogdanm	0:9b334a45a8ff	1574	}
bogdanm	0:9b334a45a8ff	1575	else
bogdanm	0:9b334a45a8ff	1576	{
bogdanm	0:9b334a45a8ff	1577	tmp_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	1578	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1579	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1580	} /* if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) */
bogdanm	0:9b334a45a8ff	1581
bogdanm	0:9b334a45a8ff	1582
bogdanm	0:9b334a45a8ff	1583
bogdanm	0:9b334a45a8ff	1584	/* Return function status */
bogdanm	0:9b334a45a8ff	1585	return tmp_status;
bogdanm	0:9b334a45a8ff	1586	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) */
bogdanm	0:9b334a45a8ff	1587	}
bogdanm	0:9b334a45a8ff	1588
bogdanm	0:9b334a45a8ff	1589
bogdanm	0:9b334a45a8ff	1590	/**
bogdanm	0:9b334a45a8ff	1591	* @brief Stop ADC conversion of regular groups and disable ADC DMA transfer.
bogdanm	0:9b334a45a8ff	1592	* @note Stop as well injected conversions and disable ADC peripheral.
bogdanm	0:9b334a45a8ff	1593	* @note Case of multimode enabled: HAL_ADC_Stop_DMA() function is
bogdanm	0:9b334a45a8ff	1594	* dedicated to single-ADC mode only. For multimode, use the
bogdanm	0:9b334a45a8ff	1595	* dedicated HAL_ADCEx_MultiModeStop_DMA() API.
bogdanm	0:9b334a45a8ff	1596	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1597	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1598	*/
bogdanm	0:9b334a45a8ff	1599	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1600	{
bogdanm	0:9b334a45a8ff	1601	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	1602
bogdanm	0:9b334a45a8ff	1603	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1604	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1605
bogdanm	0:9b334a45a8ff	1606	/* Process locked */
bogdanm	0:9b334a45a8ff	1607	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	/* 1. Stop potential regular conversion on going */
bogdanm	0:9b334a45a8ff	1610	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
bogdanm	0:9b334a45a8ff	1611
bogdanm	0:9b334a45a8ff	1612	/* Disable ADC peripheral if conversions are effectively stopped */
bogdanm	0:9b334a45a8ff	1613	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1614	{
bogdanm	0:9b334a45a8ff	1615	/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
bogdanm	0:9b334a45a8ff	1616	CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
bogdanm	0:9b334a45a8ff	1617
bogdanm	0:9b334a45a8ff	1618	/* Disable the DMA channel (in case of DMA in circular mode or stop while */
bogdanm	0:9b334a45a8ff	1619	/* while DMA transfer is on going) */
bogdanm	0:9b334a45a8ff	1620	tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
bogdanm	0:9b334a45a8ff	1621
bogdanm	0:9b334a45a8ff	1622	/* Check if DMA channel effectively disabled */
bogdanm	0:9b334a45a8ff	1623	if (tmp_status != HAL_OK)
bogdanm	0:9b334a45a8ff	1624	{
bogdanm	0:9b334a45a8ff	1625	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1626	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	1627	}
bogdanm	0:9b334a45a8ff	1628
bogdanm	0:9b334a45a8ff	1629	/* Disable ADC overrun interrupt */
bogdanm	0:9b334a45a8ff	1630	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	1631
bogdanm	0:9b334a45a8ff	1632	/* 2. Disable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1633	/* Update "tmp_status" only if DMA channel disabling passed, to keep in */
bogdanm	0:9b334a45a8ff	1634	/* memory a potential failing status. */
bogdanm	0:9b334a45a8ff	1635	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1636	{
bogdanm	0:9b334a45a8ff	1637	tmp_status = ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	1638	}
bogdanm	0:9b334a45a8ff	1639	else
bogdanm	0:9b334a45a8ff	1640	{
bogdanm	0:9b334a45a8ff	1641	ADC_Disable(hadc);
bogdanm	0:9b334a45a8ff	1642	}
bogdanm	0:9b334a45a8ff	1643
bogdanm	0:9b334a45a8ff	1644	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	1645	if (tmp_status == HAL_OK)
bogdanm	0:9b334a45a8ff	1646	{
bogdanm	0:9b334a45a8ff	1647	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1648	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	1649	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1650	}
bogdanm	0:9b334a45a8ff	1651
bogdanm	0:9b334a45a8ff	1652	}
bogdanm	0:9b334a45a8ff	1653
bogdanm	0:9b334a45a8ff	1654	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1655	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1656
bogdanm	0:9b334a45a8ff	1657	/* Return function status */
bogdanm	0:9b334a45a8ff	1658	return tmp_status;
bogdanm	0:9b334a45a8ff	1659	}
bogdanm	0:9b334a45a8ff	1660
bogdanm	0:9b334a45a8ff	1661
bogdanm	0:9b334a45a8ff	1662	/**
bogdanm	0:9b334a45a8ff	1663	* @brief Get ADC regular group conversion result.
bogdanm	0:9b334a45a8ff	1664	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1665	* @note Reading DR register automatically clears EOC flag. To reset EOS flag,
bogdanm	0:9b334a45a8ff	1666	* the user must resort to the macro
bogdanm	0:9b334a45a8ff	1667	* __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS)
bogdanm	0:9b334a45a8ff	1668	* @retval Converted value
bogdanm	0:9b334a45a8ff	1669	*/
bogdanm	0:9b334a45a8ff	1670	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1671	{
bogdanm	0:9b334a45a8ff	1672	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1673	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1674
bogdanm	0:9b334a45a8ff	1675	/* Return ADC converted value */
bogdanm	0:9b334a45a8ff	1676	return hadc->Instance->DR;
bogdanm	0:9b334a45a8ff	1677	}
bogdanm	0:9b334a45a8ff	1678
bogdanm	0:9b334a45a8ff	1679
bogdanm	0:9b334a45a8ff	1680	/**
bogdanm	0:9b334a45a8ff	1681	* @brief Handle ADC interrupt request.
bogdanm	0:9b334a45a8ff	1682	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1683	* @retval None
bogdanm	0:9b334a45a8ff	1684	*/
bogdanm	0:9b334a45a8ff	1685	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1686	{
bogdanm	0:9b334a45a8ff	1687	uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
bogdanm	0:9b334a45a8ff	1688	ADC_TypeDef *tmpADC_Master;
bogdanm	0:9b334a45a8ff	1689	uint32_t tmp_isr = hadc->Instance->ISR;
bogdanm	0:9b334a45a8ff	1690	uint32_t tmp_ier = hadc->Instance->IER;
bogdanm	0:9b334a45a8ff	1691	uint32_t tmp_cfgr = 0x0;
bogdanm	0:9b334a45a8ff	1692	uint32_t tmp_cfgr_jqm = 0x0;
bogdanm	0:9b334a45a8ff	1693
bogdanm	0:9b334a45a8ff	1694
bogdanm	0:9b334a45a8ff	1695	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1696	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1697	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
bogdanm	0:9b334a45a8ff	1698
bogdanm	0:9b334a45a8ff	1699
bogdanm	0:9b334a45a8ff	1700	/* ====== Check End of Sampling flag for regular group ===== */
bogdanm	0:9b334a45a8ff	1701	if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
bogdanm	0:9b334a45a8ff	1702	{
bogdanm	0:9b334a45a8ff	1703	/* Update state machine on end of sampling status if not in error state */
bogdanm	0:9b334a45a8ff	1704	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
bogdanm	0:9b334a45a8ff	1705	{
bogdanm	0:9b334a45a8ff	1706	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1707	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
bogdanm	0:9b334a45a8ff	1708	}
bogdanm	0:9b334a45a8ff	1709
bogdanm	0:9b334a45a8ff	1710	/* End Of Sampling callback */
bogdanm	0:9b334a45a8ff	1711	HAL_ADCEx_EndOfSamplingCallback(hadc);
bogdanm	0:9b334a45a8ff	1712
bogdanm	0:9b334a45a8ff	1713	/* Clear regular group conversion flag */
bogdanm	0:9b334a45a8ff	1714	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP );
bogdanm	0:9b334a45a8ff	1715	}
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	/* ====== Check End of Conversion or Sequence flags for regular group ===== */
bogdanm	0:9b334a45a8ff	1718	if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) \|\|
bogdanm	0:9b334a45a8ff	1719	(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) )
bogdanm	0:9b334a45a8ff	1720	{
bogdanm	0:9b334a45a8ff	1721	/* Update state machine on conversion status if not in error state */
bogdanm	0:9b334a45a8ff	1722	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
bogdanm	0:9b334a45a8ff	1723	{
bogdanm	0:9b334a45a8ff	1724	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1725	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
bogdanm	0:9b334a45a8ff	1726	}
bogdanm	0:9b334a45a8ff	1727
bogdanm	0:9b334a45a8ff	1728	/* Disable interruption if no further conversion upcoming by regular */
bogdanm	0:9b334a45a8ff	1729	/* external trigger or by continuous mode, */
bogdanm	0:9b334a45a8ff	1730	/* and if scan sequence if completed. */
bogdanm	0:9b334a45a8ff	1731	if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
bogdanm	0:9b334a45a8ff	1732	{
bogdanm	0:9b334a45a8ff	1733	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
bogdanm	0:9b334a45a8ff	1734	{
bogdanm	0:9b334a45a8ff	1735	/* check CONT bit directly in handle ADC CFGR register */
bogdanm	0:9b334a45a8ff	1736	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
bogdanm	0:9b334a45a8ff	1737	}
bogdanm	0:9b334a45a8ff	1738	else
bogdanm	0:9b334a45a8ff	1739	{
bogdanm	0:9b334a45a8ff	1740	/* else need to check Master ADC CONT bit */
bogdanm	0:9b334a45a8ff	1741	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	1742	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
bogdanm	0:9b334a45a8ff	1743	}
bogdanm	0:9b334a45a8ff	1744
bogdanm	0:9b334a45a8ff	1745	/* Carry on if continuous mode is disabled */
bogdanm	0:9b334a45a8ff	1746	if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
bogdanm	0:9b334a45a8ff	1747	{
bogdanm	0:9b334a45a8ff	1748	/* If End of Sequence is reached, disable interrupts */
bogdanm	0:9b334a45a8ff	1749	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
bogdanm	0:9b334a45a8ff	1750	{
bogdanm	0:9b334a45a8ff	1751	/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
bogdanm	0:9b334a45a8ff	1752	/* ADSTART==0 (no conversion on going) */
bogdanm	0:9b334a45a8ff	1753	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1754	{
bogdanm	0:9b334a45a8ff	1755	/* Disable ADC end of sequence conversion interrupt */
bogdanm	0:9b334a45a8ff	1756	/* Note: if Overrun interrupt was enabled with EOC or EOS interrupt */
bogdanm	0:9b334a45a8ff	1757	/* in HAL_Start_IT(), it isn't disabled here because it can be used */
bogdanm	0:9b334a45a8ff	1758	/* by overrun IRQ process below. */
bogdanm	0:9b334a45a8ff	1759	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC \| ADC_IT_EOS);
bogdanm	0:9b334a45a8ff	1760	/* Clear HAL_ADC_STATE_REG_BUSY bit */
bogdanm	0:9b334a45a8ff	1761	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
bogdanm	0:9b334a45a8ff	1762	/* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	1763	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
bogdanm	0:9b334a45a8ff	1764	{
bogdanm	0:9b334a45a8ff	1765	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1766	}
bogdanm	0:9b334a45a8ff	1767	}
bogdanm	0:9b334a45a8ff	1768	else
bogdanm	0:9b334a45a8ff	1769	{
bogdanm	0:9b334a45a8ff	1770	/* Change ADC state to error state */
bogdanm	0:9b334a45a8ff	1771	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	1772
bogdanm	0:9b334a45a8ff	1773	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	1774	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	1775	}
bogdanm	0:9b334a45a8ff	1776	}
bogdanm	0:9b334a45a8ff	1777	} /* if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) */
bogdanm	0:9b334a45a8ff	1778	} /* if(ADC_IS_SOFTWARE_START_REGULAR(hadc) */
bogdanm	0:9b334a45a8ff	1779
bogdanm	0:9b334a45a8ff	1780	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	1781	/* Note: HAL_ADC_ConvCpltCallback can resort to
bogdanm	0:9b334a45a8ff	1782	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) or
bogdanm	0:9b334a45a8ff	1783	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOC)) to determine whether
bogdanm	0:9b334a45a8ff	1784	interruption has been triggered by end of conversion or end of
bogdanm	0:9b334a45a8ff	1785	sequence. */
bogdanm	0:9b334a45a8ff	1786	HAL_ADC_ConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1787
bogdanm	0:9b334a45a8ff	1788
bogdanm	0:9b334a45a8ff	1789	/* Clear regular group conversion flag */
bogdanm	0:9b334a45a8ff	1790	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS) );
bogdanm	0:9b334a45a8ff	1791	}
bogdanm	0:9b334a45a8ff	1792
bogdanm	0:9b334a45a8ff	1793
bogdanm	0:9b334a45a8ff	1794	/* ========== Check End of Conversion flag for injected group ========== */
bogdanm	0:9b334a45a8ff	1795	if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) \|\|
bogdanm	0:9b334a45a8ff	1796	(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) )
bogdanm	0:9b334a45a8ff	1797	{
bogdanm	0:9b334a45a8ff	1798	/* Update state machine on conversion status if not in error state */
bogdanm	0:9b334a45a8ff	1799	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
bogdanm	0:9b334a45a8ff	1800	{
bogdanm	0:9b334a45a8ff	1801	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1802	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
bogdanm	0:9b334a45a8ff	1803	}
bogdanm	0:9b334a45a8ff	1804
bogdanm	0:9b334a45a8ff	1805
bogdanm	0:9b334a45a8ff	1806	/* Check whether interruptions can be disabled only if
bogdanm	0:9b334a45a8ff	1807	- injected conversions are software-triggered when injected queue management is disabled
bogdanm	0:9b334a45a8ff	1808	OR
bogdanm	0:9b334a45a8ff	1809	- auto-injection is enabled, continuous mode is disabled (CONT = 0)
bogdanm	0:9b334a45a8ff	1810	and regular conversions are software-triggered */
bogdanm	0:9b334a45a8ff	1811	/* If End of Sequence is reached, disable interrupts */
bogdanm	0:9b334a45a8ff	1812	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
bogdanm	0:9b334a45a8ff	1813	{
bogdanm	0:9b334a45a8ff	1814
bogdanm	0:9b334a45a8ff	1815	/* First, retrieve proper registers to check */
bogdanm	0:9b334a45a8ff	1816	/* 1a. Are injected conversions that of a dual Slave ? */
bogdanm	0:9b334a45a8ff	1817	if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
bogdanm	0:9b334a45a8ff	1818	{
bogdanm	0:9b334a45a8ff	1819	/* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
bogdanm	0:9b334a45a8ff	1820	check JQM bit directly in ADC CFGR register */
bogdanm	0:9b334a45a8ff	1821	tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
bogdanm	0:9b334a45a8ff	1822	}
bogdanm	0:9b334a45a8ff	1823	else
bogdanm	0:9b334a45a8ff	1824	{
bogdanm	0:9b334a45a8ff	1825	/* hadc is the handle of a Slave ADC with dual injected conversions enabled:
bogdanm	0:9b334a45a8ff	1826	need to check JQM bit of Master ADC CFGR register */
bogdanm	0:9b334a45a8ff	1827	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	1828	tmp_cfgr_jqm = READ_REG(tmpADC_Master->CFGR);
bogdanm	0:9b334a45a8ff	1829	}
bogdanm	0:9b334a45a8ff	1830	/* 1b. Is hadc the handle of a Slave ADC with regular conversions enabled? */
bogdanm	0:9b334a45a8ff	1831	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
bogdanm	0:9b334a45a8ff	1832	{
bogdanm	0:9b334a45a8ff	1833	/* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
bogdanm	0:9b334a45a8ff	1834	check JAUTO and CONT bits directly in ADC CFGR register */
bogdanm	0:9b334a45a8ff	1835	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
bogdanm	0:9b334a45a8ff	1836	}
bogdanm	0:9b334a45a8ff	1837	else
bogdanm	0:9b334a45a8ff	1838	{
bogdanm	0:9b334a45a8ff	1839	/* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
bogdanm	0:9b334a45a8ff	1840	check JAUTO and CONT bits of Master ADC CFGR register */
bogdanm	0:9b334a45a8ff	1841	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	1842	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
bogdanm	0:9b334a45a8ff	1843	}
bogdanm	0:9b334a45a8ff	1844
bogdanm	0:9b334a45a8ff	1845	/* Secondly, check whether JEOC and JEOS interruptions can be disabled */
bogdanm	0:9b334a45a8ff	1846	if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) != ADC_CFGR_JQM))
bogdanm	0:9b334a45a8ff	1847	&& (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO\|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO\|ADC_CFGR_CONT)) &&
bogdanm	0:9b334a45a8ff	1848	(ADC_IS_SOFTWARE_START_REGULAR(hadc)))) )
bogdanm	0:9b334a45a8ff	1849	{
bogdanm	0:9b334a45a8ff	1850	/* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
bogdanm	0:9b334a45a8ff	1851	/* JADSTART==0 (no conversion on going) */
bogdanm	0:9b334a45a8ff	1852	if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1853	{
bogdanm	0:9b334a45a8ff	1854	/* Disable ADC end of sequence conversion interrupt */
bogdanm	0:9b334a45a8ff	1855	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC \| ADC_IT_JEOS);
bogdanm	0:9b334a45a8ff	1856	/* Clear HAL_ADC_STATE_INJ_BUSY bit */
bogdanm	0:9b334a45a8ff	1857	CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
bogdanm	0:9b334a45a8ff	1858	/* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
bogdanm	0:9b334a45a8ff	1859	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
bogdanm	0:9b334a45a8ff	1860	{
bogdanm	0:9b334a45a8ff	1861	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	1862	}
bogdanm	0:9b334a45a8ff	1863	}
bogdanm	0:9b334a45a8ff	1864	else
bogdanm	0:9b334a45a8ff	1865	{
bogdanm	0:9b334a45a8ff	1866	/* Change ADC state to error state */
bogdanm	0:9b334a45a8ff	1867	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	1868
bogdanm	0:9b334a45a8ff	1869	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	1870	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	1871	}
bogdanm	0:9b334a45a8ff	1872	}
bogdanm	0:9b334a45a8ff	1873	} /* if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) */
bogdanm	0:9b334a45a8ff	1874
bogdanm	0:9b334a45a8ff	1875	/* Injected Conversion complete callback */
bogdanm	0:9b334a45a8ff	1876	/* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
bogdanm	0:9b334a45a8ff	1877	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
bogdanm	0:9b334a45a8ff	1878	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
bogdanm	0:9b334a45a8ff	1879	interruption has been triggered by end of conversion or end of
bogdanm	0:9b334a45a8ff	1880	sequence. */
bogdanm	0:9b334a45a8ff	1881	HAL_ADCEx_InjectedConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1882
bogdanm	0:9b334a45a8ff	1883	/* Clear injected group conversion flag */
bogdanm	0:9b334a45a8ff	1884	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC \| ADC_FLAG_JEOS);
bogdanm	0:9b334a45a8ff	1885	}
bogdanm	0:9b334a45a8ff	1886
bogdanm	0:9b334a45a8ff	1887
bogdanm	0:9b334a45a8ff	1888	/* ========== Check Analog watchdog flags =================================================== */
bogdanm	0:9b334a45a8ff	1889
bogdanm	0:9b334a45a8ff	1890	/* ========== Check Analog watchdog 1 flags ========== */
bogdanm	0:9b334a45a8ff	1891	if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
bogdanm	0:9b334a45a8ff	1892	{
bogdanm	0:9b334a45a8ff	1893	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1894	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
bogdanm	0:9b334a45a8ff	1895
bogdanm	0:9b334a45a8ff	1896	/* Level out of window 1 callback */
bogdanm	0:9b334a45a8ff	1897	HAL_ADC_LevelOutOfWindowCallback(hadc);
bogdanm	0:9b334a45a8ff	1898	/* Clear ADC Analog watchdog flag */
bogdanm	0:9b334a45a8ff	1899	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
bogdanm	0:9b334a45a8ff	1900	}
bogdanm	0:9b334a45a8ff	1901
bogdanm	0:9b334a45a8ff	1902	/* ========== Check Analog watchdog 2 flags ========== */
bogdanm	0:9b334a45a8ff	1903	if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
bogdanm	0:9b334a45a8ff	1904	{
bogdanm	0:9b334a45a8ff	1905	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1906	SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
bogdanm	0:9b334a45a8ff	1907
bogdanm	0:9b334a45a8ff	1908	/* Level out of window 2 callback */
bogdanm	0:9b334a45a8ff	1909	HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
bogdanm	0:9b334a45a8ff	1910	/* Clear ADC Analog watchdog flag */
bogdanm	0:9b334a45a8ff	1911	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
bogdanm	0:9b334a45a8ff	1912	}
bogdanm	0:9b334a45a8ff	1913
bogdanm	0:9b334a45a8ff	1914	/* ========== Check Analog watchdog 3 flags ========== */
bogdanm	0:9b334a45a8ff	1915	if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
bogdanm	0:9b334a45a8ff	1916	{
bogdanm	0:9b334a45a8ff	1917	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1918	SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
bogdanm	0:9b334a45a8ff	1919
bogdanm	0:9b334a45a8ff	1920	/* Level out of window 3 callback */
bogdanm	0:9b334a45a8ff	1921	HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
bogdanm	0:9b334a45a8ff	1922	/* Clear ADC Analog watchdog flag */
bogdanm	0:9b334a45a8ff	1923	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
bogdanm	0:9b334a45a8ff	1924	}
bogdanm	0:9b334a45a8ff	1925
bogdanm	0:9b334a45a8ff	1926
bogdanm	0:9b334a45a8ff	1927	/* ========== Check Overrun flag ========== */
bogdanm	0:9b334a45a8ff	1928	if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
bogdanm	0:9b334a45a8ff	1929	{
bogdanm	0:9b334a45a8ff	1930	/* If overrun is set to overwrite previous data (default setting), */
bogdanm	0:9b334a45a8ff	1931	/* overrun event is not considered as an error. */
bogdanm	0:9b334a45a8ff	1932	/* (cf ref manual "Managing conversions without using the DMA and without */
bogdanm	0:9b334a45a8ff	1933	/* overrun ") */
bogdanm	0:9b334a45a8ff	1934	/* Exception for usage with DMA overrun event always considered as an */
bogdanm	0:9b334a45a8ff	1935	/* error. */
bogdanm	0:9b334a45a8ff	1936
bogdanm	0:9b334a45a8ff	1937	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
bogdanm	0:9b334a45a8ff	1938	{
bogdanm	0:9b334a45a8ff	1939	overrun_error = 1;
bogdanm	0:9b334a45a8ff	1940	}
bogdanm	0:9b334a45a8ff	1941	else
bogdanm	0:9b334a45a8ff	1942	{
bogdanm	0:9b334a45a8ff	1943	/* check DMA configuration, depending on multimode set or not,
bogdanm	0:9b334a45a8ff	1944	or whether or not multimode feature is available */
bogdanm	0:9b334a45a8ff	1945	if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1946	{
bogdanm	0:9b334a45a8ff	1947	/* Multimode not set or ADC independent */
bogdanm	0:9b334a45a8ff	1948	if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
bogdanm	0:9b334a45a8ff	1949	{
bogdanm	0:9b334a45a8ff	1950	overrun_error = 1;
bogdanm	0:9b334a45a8ff	1951	}
bogdanm	0:9b334a45a8ff	1952	}
bogdanm	0:9b334a45a8ff	1953	else
bogdanm	0:9b334a45a8ff	1954	{
bogdanm	0:9b334a45a8ff	1955	/* Multimode (when feature is available) is enabled,
bogdanm	0:9b334a45a8ff	1956	Common Control Register MDMA bits must be checked. */
bogdanm	0:9b334a45a8ff	1957	if (ADC_MULTIMODE_DMA_ENABLED())
bogdanm	0:9b334a45a8ff	1958	{
bogdanm	0:9b334a45a8ff	1959	overrun_error = 1;
bogdanm	0:9b334a45a8ff	1960	}
bogdanm	0:9b334a45a8ff	1961	}
bogdanm	0:9b334a45a8ff	1962	}
bogdanm	0:9b334a45a8ff	1963
bogdanm	0:9b334a45a8ff	1964	if (overrun_error == 1)
bogdanm	0:9b334a45a8ff	1965	{
bogdanm	0:9b334a45a8ff	1966	/* Change ADC state to error state */
bogdanm	0:9b334a45a8ff	1967	SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
bogdanm	0:9b334a45a8ff	1968
bogdanm	0:9b334a45a8ff	1969	/* Set ADC error code to overrun */
bogdanm	0:9b334a45a8ff	1970	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
bogdanm	0:9b334a45a8ff	1971
bogdanm	0:9b334a45a8ff	1972	/* Error callback */
bogdanm	0:9b334a45a8ff	1973	HAL_ADC_ErrorCallback(hadc);
bogdanm	0:9b334a45a8ff	1974	}
bogdanm	0:9b334a45a8ff	1975
bogdanm	0:9b334a45a8ff	1976	/* Clear the Overrun flag, to be done AFTER HAL_ADC_ErrorCallback() since
bogdanm	0:9b334a45a8ff	1977	old data is preserved until OVR is reset */
bogdanm	0:9b334a45a8ff	1978	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
bogdanm	0:9b334a45a8ff	1979
bogdanm	0:9b334a45a8ff	1980	}
bogdanm	0:9b334a45a8ff	1981
bogdanm	0:9b334a45a8ff	1982
bogdanm	0:9b334a45a8ff	1983	/* ========== Check Injected context queue overflow flag ========== */
bogdanm	0:9b334a45a8ff	1984	if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
bogdanm	0:9b334a45a8ff	1985	{
bogdanm	0:9b334a45a8ff	1986	/* Change ADC state to overrun state */
bogdanm	0:9b334a45a8ff	1987	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
bogdanm	0:9b334a45a8ff	1988
bogdanm	0:9b334a45a8ff	1989	/* Set ADC error code to Injected context queue overflow */
bogdanm	0:9b334a45a8ff	1990	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
bogdanm	0:9b334a45a8ff	1991
bogdanm	0:9b334a45a8ff	1992	/* Clear the Injected context queue overflow flag */
bogdanm	0:9b334a45a8ff	1993	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
bogdanm	0:9b334a45a8ff	1994
bogdanm	0:9b334a45a8ff	1995	/* Error callback */
bogdanm	0:9b334a45a8ff	1996	HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
bogdanm	0:9b334a45a8ff	1997	}
bogdanm	0:9b334a45a8ff	1998
bogdanm	0:9b334a45a8ff	1999	}
bogdanm	0:9b334a45a8ff	2000
bogdanm	0:9b334a45a8ff	2001	/**
bogdanm	0:9b334a45a8ff	2002	* @brief Conversion complete callback in non-blocking mode.
bogdanm	0:9b334a45a8ff	2003	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2004	* @retval None
bogdanm	0:9b334a45a8ff	2005	*/
bogdanm	0:9b334a45a8ff	2006	__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	2007	{
bogdanm	0:9b334a45a8ff	2008	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	2009	function HAL_ADC_ConvCpltCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	2010	*/
bogdanm	0:9b334a45a8ff	2011	}
bogdanm	0:9b334a45a8ff	2012
bogdanm	0:9b334a45a8ff	2013	/**
bogdanm	0:9b334a45a8ff	2014	* @brief Conversion DMA half-transfer callback in non-blocking mode.
bogdanm	0:9b334a45a8ff	2015	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2016	* @retval None
bogdanm	0:9b334a45a8ff	2017	*/
bogdanm	0:9b334a45a8ff	2018	__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	2019	{
bogdanm	0:9b334a45a8ff	2020	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	2021	function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	2022	*/
bogdanm	0:9b334a45a8ff	2023	}
bogdanm	0:9b334a45a8ff	2024
bogdanm	0:9b334a45a8ff	2025	/**
bogdanm	0:9b334a45a8ff	2026	* @brief Analog watchdog 1 callback in non-blocking mode.
bogdanm	0:9b334a45a8ff	2027	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2028	* @retval None
bogdanm	0:9b334a45a8ff	2029	*/
bogdanm	0:9b334a45a8ff	2030	__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	2031	{
bogdanm	0:9b334a45a8ff	2032	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	2033	function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	2034	*/
bogdanm	0:9b334a45a8ff	2035	}
bogdanm	0:9b334a45a8ff	2036
bogdanm	0:9b334a45a8ff	2037	/**
bogdanm	0:9b334a45a8ff	2038	* @brief ADC error callback in non-blocking mode
bogdanm	0:9b334a45a8ff	2039	* (ADC conversion with interruption or transfer by DMA).
bogdanm	0:9b334a45a8ff	2040	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2041	* @retval None
bogdanm	0:9b334a45a8ff	2042	*/
bogdanm	0:9b334a45a8ff	2043	__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
bogdanm	0:9b334a45a8ff	2044	{
bogdanm	0:9b334a45a8ff	2045	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	2046	function HAL_ADC_ErrorCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	2047	*/
bogdanm	0:9b334a45a8ff	2048	}
bogdanm	0:9b334a45a8ff	2049
bogdanm	0:9b334a45a8ff	2050	/**
bogdanm	0:9b334a45a8ff	2051	* @}
bogdanm	0:9b334a45a8ff	2052	*/
bogdanm	0:9b334a45a8ff	2053
bogdanm	0:9b334a45a8ff	2054	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
bogdanm	0:9b334a45a8ff	2055	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	2056	*
bogdanm	0:9b334a45a8ff	2057	@verbatim
bogdanm	0:9b334a45a8ff	2058	===============================================================================
bogdanm	0:9b334a45a8ff	2059	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	2060	===============================================================================
bogdanm	0:9b334a45a8ff	2061	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	2062	(+) Configure channels on regular group
bogdanm	0:9b334a45a8ff	2063	(+) Configure the analog watchdog
bogdanm	0:9b334a45a8ff	2064
bogdanm	0:9b334a45a8ff	2065	@endverbatim
bogdanm	0:9b334a45a8ff	2066	* @{
bogdanm	0:9b334a45a8ff	2067	*/
bogdanm	0:9b334a45a8ff	2068
bogdanm	0:9b334a45a8ff	2069
bogdanm	0:9b334a45a8ff	2070	/**
bogdanm	0:9b334a45a8ff	2071	* @brief Configure the selected channel to be linked to the regular group.
bogdanm	0:9b334a45a8ff	2072	* @note In case of usage of internal measurement channels (Vbat / VrefInt /
bogdanm	0:9b334a45a8ff	2073	* TempSensor), the recommended sampling time is provided by the
bogdanm	0:9b334a45a8ff	2074	* datasheet.
bogdanm	0:9b334a45a8ff	2075	* These internal paths can be disabled using function
bogdanm	0:9b334a45a8ff	2076	* HAL_ADC_DeInit().
bogdanm	0:9b334a45a8ff	2077	* @note Possibility to update parameters on the fly:
bogdanm	0:9b334a45a8ff	2078	* HAL_ADC_ConfigChannel() initializes channel into regular group,
bogdanm	0:9b334a45a8ff	2079	* consecutive calls to this function can be used to reconfigure some
bogdanm	0:9b334a45a8ff	2080	* parameters of structure "ADC_ChannelConfTypeDef" on the fly, without
bogdanm	0:9b334a45a8ff	2081	* resetting the ADC.
bogdanm	0:9b334a45a8ff	2082	* The setting of these parameters is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	2083	* For parameters constraints, see comments of structure
bogdanm	0:9b334a45a8ff	2084	* "ADC_ChannelConfTypeDef".
bogdanm	0:9b334a45a8ff	2085	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2086	* @param sConfig: Structure ADC channel for regular group.
bogdanm	0:9b334a45a8ff	2087	* @retval HAL status
bogdanm	0:9b334a45a8ff	2088	*/
bogdanm	0:9b334a45a8ff	2089	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
bogdanm	0:9b334a45a8ff	2090	{
bogdanm	0:9b334a45a8ff	2091	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	2092
bogdanm	0:9b334a45a8ff	2093	ADC_Common_TypeDef *tmpADC_Common;
bogdanm	0:9b334a45a8ff	2094	uint32_t tmpOffsetShifted;
bogdanm	0:9b334a45a8ff	2095	uint32_t WaitLoopIndex = 0;
bogdanm	0:9b334a45a8ff	2096
bogdanm	0:9b334a45a8ff	2097	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2098	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	2099	assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
bogdanm	0:9b334a45a8ff	2100	assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
bogdanm	0:9b334a45a8ff	2101	assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
bogdanm	0:9b334a45a8ff	2102	assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
bogdanm	0:9b334a45a8ff	2103	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
bogdanm	0:9b334a45a8ff	2104
bogdanm	0:9b334a45a8ff	2105	/* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
bogdanm	0:9b334a45a8ff	2106	ignored (considered as reset) */
bogdanm	0:9b334a45a8ff	2107	assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
bogdanm	0:9b334a45a8ff	2108
bogdanm	0:9b334a45a8ff	2109	/* Verification of channel number.
bogdanm	0:9b334a45a8ff	2110	For ADC1 and ADC2, channels 1 to 15 are available in differential mode,
bogdanm	0:9b334a45a8ff	2111	channels 16 to 18 can be only used in single-ended mode.
bogdanm	0:9b334a45a8ff	2112	For ADC3, channels 1 to 11 are available in differential mode,
bogdanm	0:9b334a45a8ff	2113	channels 12 to 18 can only be used in single-ended mode. */
bogdanm	0:9b334a45a8ff	2114	if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
bogdanm	0:9b334a45a8ff	2115	{
bogdanm	0:9b334a45a8ff	2116	assert_param(IS_ADC_CHANNEL(sConfig->Channel));
bogdanm	0:9b334a45a8ff	2117	}
bogdanm	0:9b334a45a8ff	2118	else
bogdanm	0:9b334a45a8ff	2119	{
bogdanm	0:9b334a45a8ff	2120	if (hadc->Instance == ADC3)
bogdanm	0:9b334a45a8ff	2121	{
bogdanm	0:9b334a45a8ff	2122	assert_param(IS_ADC3_DIFF_CHANNEL(sConfig->Channel));
bogdanm	0:9b334a45a8ff	2123	}
bogdanm	0:9b334a45a8ff	2124	else
bogdanm	0:9b334a45a8ff	2125	{
bogdanm	0:9b334a45a8ff	2126	assert_param(IS_ADC12_DIFF_CHANNEL(sConfig->Channel));
bogdanm	0:9b334a45a8ff	2127	}
bogdanm	0:9b334a45a8ff	2128	}
bogdanm	0:9b334a45a8ff	2129
bogdanm	0:9b334a45a8ff	2130	/* Process locked */
bogdanm	0:9b334a45a8ff	2131	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	2132
bogdanm	0:9b334a45a8ff	2133
bogdanm	0:9b334a45a8ff	2134	/* Parameters update conditioned to ADC state: */
bogdanm	0:9b334a45a8ff	2135	/* Parameters that can be updated when ADC is disabled or enabled without */
bogdanm	0:9b334a45a8ff	2136	/* conversion on going on regular group: */
bogdanm	0:9b334a45a8ff	2137	/* - Channel number */
bogdanm	0:9b334a45a8ff	2138	/* - Channel rank */
bogdanm	0:9b334a45a8ff	2139	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
bogdanm	0:9b334a45a8ff	2140	{
bogdanm	0:9b334a45a8ff	2141
bogdanm	0:9b334a45a8ff	2142	/* Regular sequence configuration */
bogdanm	0:9b334a45a8ff	2143	/* Clear the old SQx bits then set the new ones for the selected rank */
bogdanm	0:9b334a45a8ff	2144	/* For Rank 1 to 4 */
bogdanm	0:9b334a45a8ff	2145	if (sConfig->Rank < 5)
bogdanm	0:9b334a45a8ff	2146	{
bogdanm	0:9b334a45a8ff	2147	MODIFY_REG(hadc->Instance->SQR1,
bogdanm	0:9b334a45a8ff	2148	ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank),
bogdanm	0:9b334a45a8ff	2149	ADC_SQR1_RK(sConfig->Channel, sConfig->Rank));
bogdanm	0:9b334a45a8ff	2150	}
bogdanm	0:9b334a45a8ff	2151	/* For Rank 5 to 9 */
bogdanm	0:9b334a45a8ff	2152	else if (sConfig->Rank < 10)
bogdanm	0:9b334a45a8ff	2153	{
bogdanm	0:9b334a45a8ff	2154	MODIFY_REG(hadc->Instance->SQR2,
bogdanm	0:9b334a45a8ff	2155	ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank),
bogdanm	0:9b334a45a8ff	2156	ADC_SQR2_RK(sConfig->Channel, sConfig->Rank));
bogdanm	0:9b334a45a8ff	2157	}
bogdanm	0:9b334a45a8ff	2158	/* For Rank 10 to 14 */
bogdanm	0:9b334a45a8ff	2159	else if (sConfig->Rank < 15)
bogdanm	0:9b334a45a8ff	2160	{
bogdanm	0:9b334a45a8ff	2161	MODIFY_REG(hadc->Instance->SQR3,
bogdanm	0:9b334a45a8ff	2162	ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank),
bogdanm	0:9b334a45a8ff	2163	ADC_SQR3_RK(sConfig->Channel, sConfig->Rank));
bogdanm	0:9b334a45a8ff	2164	}
bogdanm	0:9b334a45a8ff	2165	/* For Rank 15 to 16 */
bogdanm	0:9b334a45a8ff	2166	else
bogdanm	0:9b334a45a8ff	2167	{
bogdanm	0:9b334a45a8ff	2168	MODIFY_REG(hadc->Instance->SQR4,
bogdanm	0:9b334a45a8ff	2169	ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank),
bogdanm	0:9b334a45a8ff	2170	ADC_SQR4_RK(sConfig->Channel, sConfig->Rank));
bogdanm	0:9b334a45a8ff	2171	}
bogdanm	0:9b334a45a8ff	2172
bogdanm	0:9b334a45a8ff	2173
bogdanm	0:9b334a45a8ff	2174	/* Parameters update conditioned to ADC state: */
bogdanm	0:9b334a45a8ff	2175	/* Parameters that can be updated when ADC is disabled or enabled without */
bogdanm	0:9b334a45a8ff	2176	/* conversion on going on regular group: */
bogdanm	0:9b334a45a8ff	2177	/* - Channel sampling time */
bogdanm	0:9b334a45a8ff	2178	/* - Channel offset */
bogdanm	0:9b334a45a8ff	2179	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	2180	{
bogdanm	0:9b334a45a8ff	2181
bogdanm	0:9b334a45a8ff	2182	/* Channel sampling time configuration */
bogdanm	0:9b334a45a8ff	2183	/* Clear the old sample time then set the new one for the selected channel */
bogdanm	0:9b334a45a8ff	2184	/* For channels 10 to 18 */
bogdanm	0:9b334a45a8ff	2185	if (sConfig->Channel >= ADC_CHANNEL_10)
bogdanm	0:9b334a45a8ff	2186	{
bogdanm	0:9b334a45a8ff	2187	MODIFY_REG(hadc->Instance->SMPR2,
bogdanm	0:9b334a45a8ff	2188	ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel),
bogdanm	0:9b334a45a8ff	2189	ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel));
bogdanm	0:9b334a45a8ff	2190	}
bogdanm	0:9b334a45a8ff	2191	else /* For channels 0 to 9 */
bogdanm	0:9b334a45a8ff	2192	{
bogdanm	0:9b334a45a8ff	2193	MODIFY_REG(hadc->Instance->SMPR1,
bogdanm	0:9b334a45a8ff	2194	ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel),
bogdanm	0:9b334a45a8ff	2195	ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel));
bogdanm	0:9b334a45a8ff	2196	}
bogdanm	0:9b334a45a8ff	2197
bogdanm	0:9b334a45a8ff	2198
bogdanm	0:9b334a45a8ff	2199	/* Configure the offset: offset enable/disable, channel, offset value */
bogdanm	0:9b334a45a8ff	2200
bogdanm	0:9b334a45a8ff	2201	/* Shift the offset with respect to the selected ADC resolution. */
bogdanm	0:9b334a45a8ff	2202	/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
bogdanm	0:9b334a45a8ff	2203	tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
bogdanm	0:9b334a45a8ff	2204
bogdanm	0:9b334a45a8ff	2205	switch (sConfig->OffsetNumber)
bogdanm	0:9b334a45a8ff	2206	{
bogdanm	0:9b334a45a8ff	2207	/* Configure offset register i when applicable: */
bogdanm	0:9b334a45a8ff	2208	/* - Enable offset */
bogdanm	0:9b334a45a8ff	2209	/* - Set channel number */
bogdanm	0:9b334a45a8ff	2210	/* - Set offset value */
bogdanm	0:9b334a45a8ff	2211	case ADC_OFFSET_1:
bogdanm	0:9b334a45a8ff	2212	MODIFY_REG(hadc->Instance->OFR1,
bogdanm	0:9b334a45a8ff	2213	ADC_OFR_FIELDS,
bogdanm	0:9b334a45a8ff	2214	ADC_OFR1_OFFSET1_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
bogdanm	0:9b334a45a8ff	2215	break;
bogdanm	0:9b334a45a8ff	2216
bogdanm	0:9b334a45a8ff	2217	case ADC_OFFSET_2:
bogdanm	0:9b334a45a8ff	2218	MODIFY_REG(hadc->Instance->OFR2,
bogdanm	0:9b334a45a8ff	2219	ADC_OFR_FIELDS,
bogdanm	0:9b334a45a8ff	2220	ADC_OFR2_OFFSET2_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
bogdanm	0:9b334a45a8ff	2221	break;
bogdanm	0:9b334a45a8ff	2222
bogdanm	0:9b334a45a8ff	2223	case ADC_OFFSET_3:
bogdanm	0:9b334a45a8ff	2224	MODIFY_REG(hadc->Instance->OFR3,
bogdanm	0:9b334a45a8ff	2225	ADC_OFR_FIELDS,
bogdanm	0:9b334a45a8ff	2226	ADC_OFR3_OFFSET3_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
bogdanm	0:9b334a45a8ff	2227	break;
bogdanm	0:9b334a45a8ff	2228
bogdanm	0:9b334a45a8ff	2229	case ADC_OFFSET_4:
bogdanm	0:9b334a45a8ff	2230	MODIFY_REG(hadc->Instance->OFR4,
bogdanm	0:9b334a45a8ff	2231	ADC_OFR_FIELDS,
bogdanm	0:9b334a45a8ff	2232	ADC_OFR4_OFFSET4_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
bogdanm	0:9b334a45a8ff	2233	break;
bogdanm	0:9b334a45a8ff	2234
bogdanm	0:9b334a45a8ff	2235	/* Case ADC_OFFSET_NONE */
bogdanm	0:9b334a45a8ff	2236	default :
bogdanm	0:9b334a45a8ff	2237	/* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
bogdanm	0:9b334a45a8ff	2238	If this is the case, offset OFRx is disabled since
bogdanm	0:9b334a45a8ff	2239	sConfig->OffsetNumber = ADC_OFFSET_NONE. */
bogdanm	0:9b334a45a8ff	2240	if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
bogdanm	0:9b334a45a8ff	2241	{
bogdanm	0:9b334a45a8ff	2242	CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
bogdanm	0:9b334a45a8ff	2243	}
bogdanm	0:9b334a45a8ff	2244	if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
bogdanm	0:9b334a45a8ff	2245	{
bogdanm	0:9b334a45a8ff	2246	CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
bogdanm	0:9b334a45a8ff	2247	}
bogdanm	0:9b334a45a8ff	2248	if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
bogdanm	0:9b334a45a8ff	2249	{
bogdanm	0:9b334a45a8ff	2250	CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
bogdanm	0:9b334a45a8ff	2251	}
bogdanm	0:9b334a45a8ff	2252	if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
bogdanm	0:9b334a45a8ff	2253	{
bogdanm	0:9b334a45a8ff	2254	CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
bogdanm	0:9b334a45a8ff	2255	}
bogdanm	0:9b334a45a8ff	2256	break;
bogdanm	0:9b334a45a8ff	2257	} /* switch (sConfig->OffsetNumber) */
bogdanm	0:9b334a45a8ff	2258
bogdanm	0:9b334a45a8ff	2259	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
bogdanm	0:9b334a45a8ff	2260
bogdanm	0:9b334a45a8ff	2261
bogdanm	0:9b334a45a8ff	2262
bogdanm	0:9b334a45a8ff	2263	/* Parameters update conditioned to ADC state: */
bogdanm	0:9b334a45a8ff	2264	/* Parameters that can be updated only when ADC is disabled: */
bogdanm	0:9b334a45a8ff	2265	/* - Single or differential mode */
bogdanm	0:9b334a45a8ff	2266	/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
bogdanm	0:9b334a45a8ff	2267	if (ADC_IS_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	2268	{
bogdanm	0:9b334a45a8ff	2269	/* Configuration of differential mode */
bogdanm	0:9b334a45a8ff	2270	if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
bogdanm	0:9b334a45a8ff	2271	{
bogdanm	0:9b334a45a8ff	2272	/* Disable differential mode (default mode: single-ended) */
bogdanm	0:9b334a45a8ff	2273	CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
bogdanm	0:9b334a45a8ff	2274	}
bogdanm	0:9b334a45a8ff	2275	else
bogdanm	0:9b334a45a8ff	2276	{
bogdanm	0:9b334a45a8ff	2277	/* Enable differential mode */
bogdanm	0:9b334a45a8ff	2278	SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
bogdanm	0:9b334a45a8ff	2279
bogdanm	0:9b334a45a8ff	2280	/* Sampling time configuration of channel ADC_IN+1 (negative input) */
bogdanm	0:9b334a45a8ff	2281	/* Clear the old sample time then set the new one for the selected */
bogdanm	0:9b334a45a8ff	2282	/* channel. */
bogdanm	0:9b334a45a8ff	2283	/* For channels 9 to 15 (ADC1, ADC2) or to 11 (ADC3), SMPR2 register
bogdanm	0:9b334a45a8ff	2284	must be configured */
bogdanm	0:9b334a45a8ff	2285	if (sConfig->Channel >= ADC_CHANNEL_9)
bogdanm	0:9b334a45a8ff	2286	{
bogdanm	0:9b334a45a8ff	2287	MODIFY_REG(hadc->Instance->SMPR2,
bogdanm	0:9b334a45a8ff	2288	ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1),
bogdanm	0:9b334a45a8ff	2289	ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1));
bogdanm	0:9b334a45a8ff	2290	}
bogdanm	0:9b334a45a8ff	2291	else /* For channels 0 to 8, SMPR1 must be configured */
bogdanm	0:9b334a45a8ff	2292	{
bogdanm	0:9b334a45a8ff	2293	MODIFY_REG(hadc->Instance->SMPR1,
bogdanm	0:9b334a45a8ff	2294	ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1),
bogdanm	0:9b334a45a8ff	2295	ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1));
bogdanm	0:9b334a45a8ff	2296	}
bogdanm	0:9b334a45a8ff	2297	}
bogdanm	0:9b334a45a8ff	2298
bogdanm	0:9b334a45a8ff	2299
bogdanm	0:9b334a45a8ff	2300
bogdanm	0:9b334a45a8ff	2301	/* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
bogdanm	0:9b334a45a8ff	2302	/* If internal channel selected, enable dedicated internal buffers and */
bogdanm	0:9b334a45a8ff	2303	/* paths. */
bogdanm	0:9b334a45a8ff	2304	/* Note: these internal measurement paths can be disabled using */
bogdanm	0:9b334a45a8ff	2305	/* HAL_ADC_DeInit(). */
bogdanm	0:9b334a45a8ff	2306
bogdanm	0:9b334a45a8ff	2307	/* Configuration of common ADC parameters */
bogdanm	0:9b334a45a8ff	2308	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
bogdanm	0:9b334a45a8ff	2309
bogdanm	0:9b334a45a8ff	2310
bogdanm	0:9b334a45a8ff	2311	/* If the requested internal measurement path has already been enabled, */
bogdanm	0:9b334a45a8ff	2312	/* bypass the configuration processing. */
bogdanm	0:9b334a45a8ff	2313	if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
bogdanm	0:9b334a45a8ff	2314	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) \|\|
bogdanm	0:9b334a45a8ff	2315	( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
bogdanm	0:9b334a45a8ff	2316	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) \|\|
bogdanm	0:9b334a45a8ff	2317	( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
bogdanm	0:9b334a45a8ff	2318	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
bogdanm	0:9b334a45a8ff	2319	)
bogdanm	0:9b334a45a8ff	2320	{
bogdanm	0:9b334a45a8ff	2321	/* Configuration of common ADC parameters (continuation) */
bogdanm	0:9b334a45a8ff	2322
bogdanm	0:9b334a45a8ff	2323	/* Software is allowed to change common parameters only when all ADCs */
bogdanm	0:9b334a45a8ff	2324	/* of the common group are disabled. */
bogdanm	0:9b334a45a8ff	2325	if ((ADC_IS_ENABLE(hadc) == RESET) &&
bogdanm	0:9b334a45a8ff	2326	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
bogdanm	0:9b334a45a8ff	2327	{
bogdanm	0:9b334a45a8ff	2328	/* Enable Temperature sensor measurement path (channel 17) */
bogdanm	0:9b334a45a8ff	2329	/* Note: Temp. sensor internal channels available on ADC1 and ADC3 */
bogdanm	0:9b334a45a8ff	2330	if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
bogdanm	0:9b334a45a8ff	2331	((hadc->Instance == ADC1) \|\| (hadc->Instance == ADC3)))
bogdanm	0:9b334a45a8ff	2332	{
bogdanm	0:9b334a45a8ff	2333	SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
bogdanm	0:9b334a45a8ff	2334
bogdanm	0:9b334a45a8ff	2335	/* Delay for temperature sensor stabilization time */
bogdanm	0:9b334a45a8ff	2336	while(WaitLoopIndex < ADC_TEMPSENSOR_DELAY_CPU_CYCLES)
bogdanm	0:9b334a45a8ff	2337	{
bogdanm	0:9b334a45a8ff	2338	WaitLoopIndex++;
bogdanm	0:9b334a45a8ff	2339	}
bogdanm	0:9b334a45a8ff	2340	}
bogdanm	0:9b334a45a8ff	2341	/* If Channel 18 is selected, enable VBAT measurement path. */
bogdanm	0:9b334a45a8ff	2342	/* Note: VBAT internal channels available on ADC1 and ADC3 */
bogdanm	0:9b334a45a8ff	2343	else if ((sConfig->Channel == ADC_CHANNEL_VBAT) &&
bogdanm	0:9b334a45a8ff	2344	((hadc->Instance == ADC1) \|\| (hadc->Instance == ADC3)))
bogdanm	0:9b334a45a8ff	2345	{
bogdanm	0:9b334a45a8ff	2346	SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
bogdanm	0:9b334a45a8ff	2347	}
bogdanm	0:9b334a45a8ff	2348	/* If Channel 0 is selected, enable VREFINT measurement path */
bogdanm	0:9b334a45a8ff	2349	/* Note: VBAT internal channels available on ADC1 only */
bogdanm	0:9b334a45a8ff	2350	else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && (hadc->Instance == ADC1))
bogdanm	0:9b334a45a8ff	2351	{
bogdanm	0:9b334a45a8ff	2352	SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
bogdanm	0:9b334a45a8ff	2353	}
bogdanm	0:9b334a45a8ff	2354	}
bogdanm	0:9b334a45a8ff	2355	/* If the requested internal measurement path has already been */
bogdanm	0:9b334a45a8ff	2356	/* enabled and other ADC of the common group are enabled, internal */
bogdanm	0:9b334a45a8ff	2357	/* measurement paths cannot be enabled. */
bogdanm	0:9b334a45a8ff	2358	else
bogdanm	0:9b334a45a8ff	2359	{
bogdanm	0:9b334a45a8ff	2360	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	2361	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	2362
bogdanm	0:9b334a45a8ff	2363	tmp_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	2364	}
bogdanm	0:9b334a45a8ff	2365	}
bogdanm	0:9b334a45a8ff	2366
bogdanm	0:9b334a45a8ff	2367	} /* if (ADC_IS_ENABLE(hadc) == RESET) */
bogdanm	0:9b334a45a8ff	2368
bogdanm	0:9b334a45a8ff	2369	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) */
bogdanm	0:9b334a45a8ff	2370
bogdanm	0:9b334a45a8ff	2371	/* If a conversion is on going on regular group, no update on regular */
bogdanm	0:9b334a45a8ff	2372	/* channel could be done on neither of the channel configuration structure */
bogdanm	0:9b334a45a8ff	2373	/* parameters. */
bogdanm	0:9b334a45a8ff	2374	else
bogdanm	0:9b334a45a8ff	2375	{
bogdanm	0:9b334a45a8ff	2376	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	2377	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	2378
bogdanm	0:9b334a45a8ff	2379	tmp_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	2380	}
bogdanm	0:9b334a45a8ff	2381
bogdanm	0:9b334a45a8ff	2382	/* Process unlocked */
bogdanm	0:9b334a45a8ff	2383	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	2384
bogdanm	0:9b334a45a8ff	2385	/* Return function status */
bogdanm	0:9b334a45a8ff	2386	return tmp_status;
bogdanm	0:9b334a45a8ff	2387	}
bogdanm	0:9b334a45a8ff	2388
bogdanm	0:9b334a45a8ff	2389
bogdanm	0:9b334a45a8ff	2390	/**
bogdanm	0:9b334a45a8ff	2391	* @brief Configure the analog watchdog.
bogdanm	0:9b334a45a8ff	2392	* @note Possibility to update parameters on the fly:
bogdanm	0:9b334a45a8ff	2393	* This function initializes the selected analog watchdog, successive
bogdanm	0:9b334a45a8ff	2394	* calls to this function can be used to reconfigure some parameters
bogdanm	0:9b334a45a8ff	2395	* of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
bogdanm	0:9b334a45a8ff	2396	* the ADC, e.g. to set several channels to monitor simultaneously.
bogdanm	0:9b334a45a8ff	2397	* The setting of these parameters is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	2398	* For parameters constraints, see comments of structure
bogdanm	0:9b334a45a8ff	2399	* "ADC_AnalogWDGConfTypeDef".
bogdanm	0:9b334a45a8ff	2400	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2401	* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
bogdanm	0:9b334a45a8ff	2402	* @retval HAL status
bogdanm	0:9b334a45a8ff	2403	*/
bogdanm	0:9b334a45a8ff	2404	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
bogdanm	0:9b334a45a8ff	2405	{
bogdanm	0:9b334a45a8ff	2406	HAL_StatusTypeDef tmp_status = HAL_OK;
bogdanm	0:9b334a45a8ff	2407
bogdanm	0:9b334a45a8ff	2408
bogdanm	0:9b334a45a8ff	2409	uint32_t tmpAWDHighThresholdShifted;
bogdanm	0:9b334a45a8ff	2410	uint32_t tmpAWDLowThresholdShifted;
bogdanm	0:9b334a45a8ff	2411
bogdanm	0:9b334a45a8ff	2412	uint32_t tmpADCFlagAWD2orAWD3;
bogdanm	0:9b334a45a8ff	2413	uint32_t tmpADCITAWD2orAWD3;
bogdanm	0:9b334a45a8ff	2414
bogdanm	0:9b334a45a8ff	2415	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2416	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	2417	assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
bogdanm	0:9b334a45a8ff	2418	assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
bogdanm	0:9b334a45a8ff	2419	assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
bogdanm	0:9b334a45a8ff	2420
bogdanm	0:9b334a45a8ff	2421	if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\|
bogdanm	0:9b334a45a8ff	2422	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\|
bogdanm	0:9b334a45a8ff	2423	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
bogdanm	0:9b334a45a8ff	2424	{
bogdanm	0:9b334a45a8ff	2425	assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
bogdanm	0:9b334a45a8ff	2426	}
bogdanm	0:9b334a45a8ff	2427
bogdanm	0:9b334a45a8ff	2428
bogdanm	0:9b334a45a8ff	2429	/* Verify if threshold is within the selected ADC resolution */
bogdanm	0:9b334a45a8ff	2430	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
bogdanm	0:9b334a45a8ff	2431	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
bogdanm	0:9b334a45a8ff	2432
bogdanm	0:9b334a45a8ff	2433	/* Process locked */
bogdanm	0:9b334a45a8ff	2434	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	2435
bogdanm	0:9b334a45a8ff	2436	/* Parameters update conditioned to ADC state: */
bogdanm	0:9b334a45a8ff	2437	/* Parameters that can be updated when ADC is disabled or enabled without */
bogdanm	0:9b334a45a8ff	2438	/* conversion on going on regular and injected groups: */
bogdanm	0:9b334a45a8ff	2439	/* - Analog watchdog channels */
bogdanm	0:9b334a45a8ff	2440	/* - Analog watchdog thresholds */
bogdanm	0:9b334a45a8ff	2441	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	2442	{
bogdanm	0:9b334a45a8ff	2443
bogdanm	0:9b334a45a8ff	2444	/* Analog watchdogs configuration */
bogdanm	0:9b334a45a8ff	2445	if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
bogdanm	0:9b334a45a8ff	2446	{
bogdanm	0:9b334a45a8ff	2447	/* Configuration of analog watchdog: */
bogdanm	0:9b334a45a8ff	2448	/* - Set the analog watchdog enable mode: regular and/or injected */
bogdanm	0:9b334a45a8ff	2449	/* groups, one or overall group of channels. */
bogdanm	0:9b334a45a8ff	2450	/* - Set the Analog watchdog channel (is not used if watchdog */
bogdanm	0:9b334a45a8ff	2451	/* mode "all channels": ADC_CFGR_AWD1SGL=0). */
bogdanm	0:9b334a45a8ff	2452
bogdanm	0:9b334a45a8ff	2453	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_WD_FIELDS,
bogdanm	0:9b334a45a8ff	2454	AnalogWDGConfig->WatchdogMode \| ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) );
bogdanm	0:9b334a45a8ff	2455
bogdanm	0:9b334a45a8ff	2456	/* Shift the offset with respect to the selected ADC resolution: */
bogdanm	0:9b334a45a8ff	2457	/* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
bogdanm	0:9b334a45a8ff	2458	/* are set to 0 */
bogdanm	0:9b334a45a8ff	2459	tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
bogdanm	0:9b334a45a8ff	2460	tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
bogdanm	0:9b334a45a8ff	2461
bogdanm	0:9b334a45a8ff	2462	/* Set the high and low thresholds */
bogdanm	0:9b334a45a8ff	2463	MODIFY_REG(hadc->Instance->TR1, ADC_TR1_HT1 \| ADC_TR1_LT1,
bogdanm	0:9b334a45a8ff	2464	ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \| tmpAWDLowThresholdShifted );
bogdanm	0:9b334a45a8ff	2465
bogdanm	0:9b334a45a8ff	2466	/* Clear the ADC Analog watchdog flag (in case left enabled by */
bogdanm	0:9b334a45a8ff	2467	/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
bogdanm	0:9b334a45a8ff	2468	/* or HAL_ADC_PollForEvent(). */
bogdanm	0:9b334a45a8ff	2469	__HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
bogdanm	0:9b334a45a8ff	2470
bogdanm	0:9b334a45a8ff	2471	/* Configure ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	2472	if(AnalogWDGConfig->ITMode == ENABLE)
bogdanm	0:9b334a45a8ff	2473	{
bogdanm	0:9b334a45a8ff	2474	/* Enable the ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	2475	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
bogdanm	0:9b334a45a8ff	2476	}
bogdanm	0:9b334a45a8ff	2477	else
bogdanm	0:9b334a45a8ff	2478	{
bogdanm	0:9b334a45a8ff	2479	/* Disable the ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	2480	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
bogdanm	0:9b334a45a8ff	2481	}
bogdanm	0:9b334a45a8ff	2482
bogdanm	0:9b334a45a8ff	2483	/* Update state, clear previous result related to AWD1 */
bogdanm	0:9b334a45a8ff	2484	CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
bogdanm	0:9b334a45a8ff	2485	}
bogdanm	0:9b334a45a8ff	2486	/* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
bogdanm	0:9b334a45a8ff	2487	else
bogdanm	0:9b334a45a8ff	2488	{
bogdanm	0:9b334a45a8ff	2489	/* Shift the threshold with respect to the selected ADC resolution */
bogdanm	0:9b334a45a8ff	2490	/* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
bogdanm	0:9b334a45a8ff	2491	tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
bogdanm	0:9b334a45a8ff	2492	tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
bogdanm	0:9b334a45a8ff	2493
bogdanm	0:9b334a45a8ff	2494	if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
bogdanm	0:9b334a45a8ff	2495	{
bogdanm	0:9b334a45a8ff	2496	/* Set the Analog watchdog channel or group of channels. This also */
bogdanm	0:9b334a45a8ff	2497	/* enables the watchdog. */
bogdanm	0:9b334a45a8ff	2498	/* Note: Conditional register reset, because several channels can be */
bogdanm	0:9b334a45a8ff	2499	/* set by successive calls of this function. */
bogdanm	0:9b334a45a8ff	2500	if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
bogdanm	0:9b334a45a8ff	2501	{
bogdanm	0:9b334a45a8ff	2502	SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
bogdanm	0:9b334a45a8ff	2503	}
bogdanm	0:9b334a45a8ff	2504	else
bogdanm	0:9b334a45a8ff	2505	{
bogdanm	0:9b334a45a8ff	2506	CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
bogdanm	0:9b334a45a8ff	2507	}
bogdanm	0:9b334a45a8ff	2508
bogdanm	0:9b334a45a8ff	2509	/* Set the high and low thresholds */
bogdanm	0:9b334a45a8ff	2510	MODIFY_REG(hadc->Instance->TR2, ADC_TR2_HT2 \| ADC_TR2_LT2,
bogdanm	0:9b334a45a8ff	2511	ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \| tmpAWDLowThresholdShifted );
bogdanm	0:9b334a45a8ff	2512
bogdanm	0:9b334a45a8ff	2513	/* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
bogdanm	0:9b334a45a8ff	2514	/* settings. */
bogdanm	0:9b334a45a8ff	2515	tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
bogdanm	0:9b334a45a8ff	2516	tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
bogdanm	0:9b334a45a8ff	2517
bogdanm	0:9b334a45a8ff	2518	/* Update state, clear previous result related to AWD2 */
bogdanm	0:9b334a45a8ff	2519	CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
bogdanm	0:9b334a45a8ff	2520	}
bogdanm	0:9b334a45a8ff	2521	/* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
bogdanm	0:9b334a45a8ff	2522	else
bogdanm	0:9b334a45a8ff	2523	{
bogdanm	0:9b334a45a8ff	2524	/* Set the Analog watchdog channel or group of channels. This also */
bogdanm	0:9b334a45a8ff	2525	/* enables the watchdog. */
bogdanm	0:9b334a45a8ff	2526	/* Note: Conditional register reset, because several channels can be */
bogdanm	0:9b334a45a8ff	2527	/* set by successive calls of this function. */
bogdanm	0:9b334a45a8ff	2528	if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
bogdanm	0:9b334a45a8ff	2529	{
bogdanm	0:9b334a45a8ff	2530	SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
bogdanm	0:9b334a45a8ff	2531	}
bogdanm	0:9b334a45a8ff	2532	else
bogdanm	0:9b334a45a8ff	2533	{
bogdanm	0:9b334a45a8ff	2534	CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
bogdanm	0:9b334a45a8ff	2535	}
bogdanm	0:9b334a45a8ff	2536
bogdanm	0:9b334a45a8ff	2537	/* Set the high and low thresholds */
bogdanm	0:9b334a45a8ff	2538	MODIFY_REG(hadc->Instance->TR3, ADC_TR3_HT3 \| ADC_TR3_LT3,
bogdanm	0:9b334a45a8ff	2539	ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \| tmpAWDLowThresholdShifted );
bogdanm	0:9b334a45a8ff	2540
bogdanm	0:9b334a45a8ff	2541	/* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
bogdanm	0:9b334a45a8ff	2542	/* settings. */
bogdanm	0:9b334a45a8ff	2543	tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
bogdanm	0:9b334a45a8ff	2544	tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
bogdanm	0:9b334a45a8ff	2545
bogdanm	0:9b334a45a8ff	2546	/* Update state, clear previous result related to AWD3 */
bogdanm	0:9b334a45a8ff	2547	CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
bogdanm	0:9b334a45a8ff	2548	}
bogdanm	0:9b334a45a8ff	2549
bogdanm	0:9b334a45a8ff	2550	/* Clear the ADC Analog watchdog flag (in case left enabled by */
bogdanm	0:9b334a45a8ff	2551	/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
bogdanm	0:9b334a45a8ff	2552	/* or HAL_ADC_PollForEvent(). */
bogdanm	0:9b334a45a8ff	2553	__HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
bogdanm	0:9b334a45a8ff	2554
bogdanm	0:9b334a45a8ff	2555	/* Configure ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	2556	if(AnalogWDGConfig->ITMode == ENABLE)
bogdanm	0:9b334a45a8ff	2557	{
bogdanm	0:9b334a45a8ff	2558	__HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
bogdanm	0:9b334a45a8ff	2559	}
bogdanm	0:9b334a45a8ff	2560	else
bogdanm	0:9b334a45a8ff	2561	{
bogdanm	0:9b334a45a8ff	2562	__HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
bogdanm	0:9b334a45a8ff	2563	}
bogdanm	0:9b334a45a8ff	2564	}
bogdanm	0:9b334a45a8ff	2565
bogdanm	0:9b334a45a8ff	2566	}
bogdanm	0:9b334a45a8ff	2567	/* If a conversion is on going on regular or injected groups, no update */
bogdanm	0:9b334a45a8ff	2568	/* could be done on neither of the AWD configuration structure parameters. */
bogdanm	0:9b334a45a8ff	2569	else
bogdanm	0:9b334a45a8ff	2570	{
bogdanm	0:9b334a45a8ff	2571	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	2572	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
bogdanm	0:9b334a45a8ff	2573
bogdanm	0:9b334a45a8ff	2574	tmp_status = HAL_ERROR;
bogdanm	0:9b334a45a8ff	2575	}
bogdanm	0:9b334a45a8ff	2576
bogdanm	0:9b334a45a8ff	2577
bogdanm	0:9b334a45a8ff	2578	/* Process unlocked */
bogdanm	0:9b334a45a8ff	2579	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	2580
bogdanm	0:9b334a45a8ff	2581
bogdanm	0:9b334a45a8ff	2582	/* Return function status */
bogdanm	0:9b334a45a8ff	2583	return tmp_status;
bogdanm	0:9b334a45a8ff	2584	}
bogdanm	0:9b334a45a8ff	2585
bogdanm	0:9b334a45a8ff	2586
bogdanm	0:9b334a45a8ff	2587	/**
bogdanm	0:9b334a45a8ff	2588	* @}
bogdanm	0:9b334a45a8ff	2589	*/
bogdanm	0:9b334a45a8ff	2590
bogdanm	0:9b334a45a8ff	2591	/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
bogdanm	0:9b334a45a8ff	2592	* @brief ADC Peripheral State functions
bogdanm	0:9b334a45a8ff	2593	*
bogdanm	0:9b334a45a8ff	2594	@verbatim
bogdanm	0:9b334a45a8ff	2595	===============================================================================
bogdanm	0:9b334a45a8ff	2596	##### Peripheral state and errors functions #####
bogdanm	0:9b334a45a8ff	2597	===============================================================================
bogdanm	0:9b334a45a8ff	2598	[..]
bogdanm	0:9b334a45a8ff	2599	This subsection provides functions to get in run-time the status of the
bogdanm	0:9b334a45a8ff	2600	peripheral.
bogdanm	0:9b334a45a8ff	2601	(+) Check the ADC state
bogdanm	0:9b334a45a8ff	2602	(+) Check the ADC error code
bogdanm	0:9b334a45a8ff	2603
bogdanm	0:9b334a45a8ff	2604	@endverbatim
bogdanm	0:9b334a45a8ff	2605	* @{
bogdanm	0:9b334a45a8ff	2606	*/
bogdanm	0:9b334a45a8ff	2607
bogdanm	0:9b334a45a8ff	2608	/**
bogdanm	0:9b334a45a8ff	2609	* @brief Return the ADC handle state.
bogdanm	0:9b334a45a8ff	2610	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2611	* @retval HAL state (uint32_t bit-map)
bogdanm	0:9b334a45a8ff	2612	*/
bogdanm	0:9b334a45a8ff	2613	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	2614	{
bogdanm	0:9b334a45a8ff	2615	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2616	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	2617
bogdanm	0:9b334a45a8ff	2618	/* Return ADC handle state */
bogdanm	0:9b334a45a8ff	2619	return hadc->State;
bogdanm	0:9b334a45a8ff	2620	}
bogdanm	0:9b334a45a8ff	2621
bogdanm	0:9b334a45a8ff	2622
bogdanm	0:9b334a45a8ff	2623	/**
bogdanm	0:9b334a45a8ff	2624	* @brief Return the ADC error code.
bogdanm	0:9b334a45a8ff	2625	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2626	* @retval ADC Error Code (uint32_t bit-map)
bogdanm	0:9b334a45a8ff	2627	*/
bogdanm	0:9b334a45a8ff	2628	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
bogdanm	0:9b334a45a8ff	2629	{
bogdanm	0:9b334a45a8ff	2630	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2631	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	2632
bogdanm	0:9b334a45a8ff	2633	return hadc->ErrorCode;
bogdanm	0:9b334a45a8ff	2634	}
bogdanm	0:9b334a45a8ff	2635
bogdanm	0:9b334a45a8ff	2636	/**
bogdanm	0:9b334a45a8ff	2637	* @}
bogdanm	0:9b334a45a8ff	2638	*/
bogdanm	0:9b334a45a8ff	2639
bogdanm	0:9b334a45a8ff	2640	/**
bogdanm	0:9b334a45a8ff	2641	* @}
bogdanm	0:9b334a45a8ff	2642	*/
bogdanm	0:9b334a45a8ff	2643
bogdanm	0:9b334a45a8ff	2644
bogdanm	0:9b334a45a8ff	2645
bogdanm	0:9b334a45a8ff	2646	/** @defgroup ADC_Private_Functions ADC Private Functions
bogdanm	0:9b334a45a8ff	2647	* @{
bogdanm	0:9b334a45a8ff	2648	*/
bogdanm	0:9b334a45a8ff	2649
bogdanm	0:9b334a45a8ff	2650	/**
bogdanm	0:9b334a45a8ff	2651	* @brief Stop ADC conversion.
bogdanm	0:9b334a45a8ff	2652	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2653	* @param ConversionGroup: ADC group regular and/or injected.
bogdanm	0:9b334a45a8ff	2654	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2655	* @arg ADC_REGULAR_GROUP: ADC regular conversion type.
bogdanm	0:9b334a45a8ff	2656	* @arg ADC_INJECTED_GROUP: ADC injected conversion type.
bogdanm	0:9b334a45a8ff	2657	* @arg ADC_REGULAR_INJECTED_GROUP: ADC regular and injected conversion type.
bogdanm	0:9b334a45a8ff	2658	* @retval HAL status.
bogdanm	0:9b334a45a8ff	2659	*/
bogdanm	0:9b334a45a8ff	2660	HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
bogdanm	0:9b334a45a8ff	2661	{
bogdanm	0:9b334a45a8ff	2662	uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
bogdanm	0:9b334a45a8ff	2663	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	2664	uint32_t Conversion_Timeout_CPU_cycles = 0;
bogdanm	0:9b334a45a8ff	2665
bogdanm	0:9b334a45a8ff	2666	/* Check the parameters */
bogdanm	0:9b334a45a8ff	2667	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	2668	assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
bogdanm	0:9b334a45a8ff	2669
bogdanm	0:9b334a45a8ff	2670	/* Verification if ADC is not already stopped (on regular and injected */
bogdanm	0:9b334a45a8ff	2671	/* groups) to bypass this function if not needed. */
bogdanm	0:9b334a45a8ff	2672	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
bogdanm	0:9b334a45a8ff	2673	{
bogdanm	0:9b334a45a8ff	2674	/* Particular case of continuous auto-injection mode combined with */
bogdanm	0:9b334a45a8ff	2675	/* auto-delay mode. */
bogdanm	0:9b334a45a8ff	2676	/* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
bogdanm	0:9b334a45a8ff	2677	/* injected group stop ADC_CR_JADSTP). */
bogdanm	0:9b334a45a8ff	2678	/* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
bogdanm	0:9b334a45a8ff	2679	/* (see reference manual). */
bogdanm	0:9b334a45a8ff	2680	if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
bogdanm	0:9b334a45a8ff	2681	&& (hadc->Init.ContinuousConvMode==ENABLE)
bogdanm	0:9b334a45a8ff	2682	&& (hadc->Init.LowPowerAutoWait==ENABLE))
bogdanm	0:9b334a45a8ff	2683	{
bogdanm	0:9b334a45a8ff	2684	/* Use stop of regular group */
bogdanm	0:9b334a45a8ff	2685	ConversionGroup = ADC_REGULAR_GROUP;
bogdanm	0:9b334a45a8ff	2686
bogdanm	0:9b334a45a8ff	2687	/* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
bogdanm	0:9b334a45a8ff	2688	while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
bogdanm	0:9b334a45a8ff	2689	{
bogdanm	0:9b334a45a8ff	2690	if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
bogdanm	0:9b334a45a8ff	2691	{
bogdanm	0:9b334a45a8ff	2692	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	2693	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2694
bogdanm	0:9b334a45a8ff	2695	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	2696	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2697
bogdanm	0:9b334a45a8ff	2698	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2699	}
bogdanm	0:9b334a45a8ff	2700	Conversion_Timeout_CPU_cycles ++;
bogdanm	0:9b334a45a8ff	2701	}
bogdanm	0:9b334a45a8ff	2702
bogdanm	0:9b334a45a8ff	2703	/* Clear JEOS */
bogdanm	0:9b334a45a8ff	2704	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
bogdanm	0:9b334a45a8ff	2705	}
bogdanm	0:9b334a45a8ff	2706
bogdanm	0:9b334a45a8ff	2707	/* Stop potential conversion on going on regular group */
bogdanm	0:9b334a45a8ff	2708	if (ConversionGroup != ADC_INJECTED_GROUP)
bogdanm	0:9b334a45a8ff	2709	{
bogdanm	0:9b334a45a8ff	2710	/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
bogdanm	0:9b334a45a8ff	2711	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
bogdanm	0:9b334a45a8ff	2712	HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
bogdanm	0:9b334a45a8ff	2713	{
bogdanm	0:9b334a45a8ff	2714	/* Stop conversions on regular group */
bogdanm	0:9b334a45a8ff	2715	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP);
bogdanm	0:9b334a45a8ff	2716	}
bogdanm	0:9b334a45a8ff	2717	}
bogdanm	0:9b334a45a8ff	2718
bogdanm	0:9b334a45a8ff	2719	/* Stop potential conversion on going on injected group */
bogdanm	0:9b334a45a8ff	2720	if (ConversionGroup != ADC_REGULAR_GROUP)
bogdanm	0:9b334a45a8ff	2721	{
bogdanm	0:9b334a45a8ff	2722	/* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
bogdanm	0:9b334a45a8ff	2723	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
bogdanm	0:9b334a45a8ff	2724	HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
bogdanm	0:9b334a45a8ff	2725	{
bogdanm	0:9b334a45a8ff	2726	/* Stop conversions on injected group */
bogdanm	0:9b334a45a8ff	2727	SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP);
bogdanm	0:9b334a45a8ff	2728	}
bogdanm	0:9b334a45a8ff	2729	}
bogdanm	0:9b334a45a8ff	2730
bogdanm	0:9b334a45a8ff	2731	/* Selection of start and stop bits with respect to the regular or injected group */
bogdanm	0:9b334a45a8ff	2732	switch(ConversionGroup)
bogdanm	0:9b334a45a8ff	2733	{
bogdanm	0:9b334a45a8ff	2734	case ADC_REGULAR_INJECTED_GROUP:
bogdanm	0:9b334a45a8ff	2735	tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART \| ADC_CR_JADSTART);
bogdanm	0:9b334a45a8ff	2736	break;
bogdanm	0:9b334a45a8ff	2737	case ADC_INJECTED_GROUP:
bogdanm	0:9b334a45a8ff	2738	tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
bogdanm	0:9b334a45a8ff	2739	break;
bogdanm	0:9b334a45a8ff	2740	/* Case ADC_REGULAR_GROUP only*/
bogdanm	0:9b334a45a8ff	2741	default:
bogdanm	0:9b334a45a8ff	2742	tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
bogdanm	0:9b334a45a8ff	2743	break;
bogdanm	0:9b334a45a8ff	2744	}
bogdanm	0:9b334a45a8ff	2745
bogdanm	0:9b334a45a8ff	2746	/* Wait for conversion effectively stopped */
bogdanm	0:9b334a45a8ff	2747
bogdanm	0:9b334a45a8ff	2748
bogdanm	0:9b334a45a8ff	2749	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2750
bogdanm	0:9b334a45a8ff	2751	while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
bogdanm	0:9b334a45a8ff	2752	{
bogdanm	0:9b334a45a8ff	2753	if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
bogdanm	0:9b334a45a8ff	2754	{
bogdanm	0:9b334a45a8ff	2755	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	2756	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2757
bogdanm	0:9b334a45a8ff	2758	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	2759	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2760
bogdanm	0:9b334a45a8ff	2761	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2762	}
bogdanm	0:9b334a45a8ff	2763	}
bogdanm	0:9b334a45a8ff	2764
bogdanm	0:9b334a45a8ff	2765	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) */
bogdanm	0:9b334a45a8ff	2766
bogdanm	0:9b334a45a8ff	2767	/* Return HAL status */
bogdanm	0:9b334a45a8ff	2768	return HAL_OK;
bogdanm	0:9b334a45a8ff	2769	}
bogdanm	0:9b334a45a8ff	2770
bogdanm	0:9b334a45a8ff	2771
bogdanm	0:9b334a45a8ff	2772
bogdanm	0:9b334a45a8ff	2773	/**
bogdanm	0:9b334a45a8ff	2774	* @brief Enable the selected ADC.
bogdanm	0:9b334a45a8ff	2775	* @note Prerequisite condition to use this function: ADC must be disabled
bogdanm	0:9b334a45a8ff	2776	* and voltage regulator must be enabled (done into HAL_ADC_Init()).
bogdanm	0:9b334a45a8ff	2777	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2778	* @retval HAL status.
bogdanm	0:9b334a45a8ff	2779	*/
bogdanm	0:9b334a45a8ff	2780	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	2781	{
bogdanm	0:9b334a45a8ff	2782	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	2783
bogdanm	0:9b334a45a8ff	2784	/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
bogdanm	0:9b334a45a8ff	2785	/* enabling phase not yet completed: flag ADC ready not set yet). */
bogdanm	0:9b334a45a8ff	2786	/* Timeout implemented not to be stuck if ADC cannot be enabled (possible */
bogdanm	0:9b334a45a8ff	2787	/* causes: ADC clock not running, ...). */
bogdanm	0:9b334a45a8ff	2788	if (ADC_IS_ENABLE(hadc) == RESET)
bogdanm	0:9b334a45a8ff	2789	{
bogdanm	0:9b334a45a8ff	2790	/* Check if conditions to enable the ADC are fulfilled */
bogdanm	0:9b334a45a8ff	2791	if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
bogdanm	0:9b334a45a8ff	2792	{
bogdanm	0:9b334a45a8ff	2793	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	2794	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2795
bogdanm	0:9b334a45a8ff	2796	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	2797	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2798
bogdanm	0:9b334a45a8ff	2799	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2800	}
bogdanm	0:9b334a45a8ff	2801
bogdanm	0:9b334a45a8ff	2802	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	2803	ADC_ENABLE(hadc);
bogdanm	0:9b334a45a8ff	2804
bogdanm	0:9b334a45a8ff	2805
bogdanm	0:9b334a45a8ff	2806	/* Wait for ADC effectively enabled */
bogdanm	0:9b334a45a8ff	2807	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2808
bogdanm	0:9b334a45a8ff	2809	while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
bogdanm	0:9b334a45a8ff	2810	{
bogdanm	0:9b334a45a8ff	2811	/* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
bogdanm	0:9b334a45a8ff	2812	has been cleared (after a calibration), ADEN bit is reset by the
bogdanm	0:9b334a45a8ff	2813	calibration logic.
bogdanm	0:9b334a45a8ff	2814	The workaround is to continue setting ADEN until ADRDY is becomes 1.
bogdanm	0:9b334a45a8ff	2815	Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
bogdanm	0:9b334a45a8ff	2816	4 ADC clock cycle duration */
bogdanm	0:9b334a45a8ff	2817	ADC_ENABLE(hadc);
bogdanm	0:9b334a45a8ff	2818
bogdanm	0:9b334a45a8ff	2819	if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
bogdanm	0:9b334a45a8ff	2820	{
bogdanm	0:9b334a45a8ff	2821	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	2822	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2823
bogdanm	0:9b334a45a8ff	2824	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	2825	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2826
bogdanm	0:9b334a45a8ff	2827	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2828	}
bogdanm	0:9b334a45a8ff	2829	}
bogdanm	0:9b334a45a8ff	2830	}
bogdanm	0:9b334a45a8ff	2831
bogdanm	0:9b334a45a8ff	2832	/* Return HAL status */
bogdanm	0:9b334a45a8ff	2833	return HAL_OK;
bogdanm	0:9b334a45a8ff	2834	}
bogdanm	0:9b334a45a8ff	2835
bogdanm	0:9b334a45a8ff	2836	/**
bogdanm	0:9b334a45a8ff	2837	* @brief Disable the selected ADC.
bogdanm	0:9b334a45a8ff	2838	* @note Prerequisite condition to use this function: ADC conversions must be
bogdanm	0:9b334a45a8ff	2839	* stopped.
bogdanm	0:9b334a45a8ff	2840	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	2841	* @retval HAL status.
bogdanm	0:9b334a45a8ff	2842	*/
bogdanm	0:9b334a45a8ff	2843	HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	2844	{
bogdanm	0:9b334a45a8ff	2845	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	2846
bogdanm	0:9b334a45a8ff	2847	/* Verification if ADC is not already disabled: */
bogdanm	0:9b334a45a8ff	2848	/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
bogdanm	0:9b334a45a8ff	2849	/* disabled. */
bogdanm	0:9b334a45a8ff	2850	if (ADC_IS_ENABLE(hadc) != RESET )
bogdanm	0:9b334a45a8ff	2851	{
bogdanm	0:9b334a45a8ff	2852	/* Check if conditions to disable the ADC are fulfilled */
bogdanm	0:9b334a45a8ff	2853	if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
bogdanm	0:9b334a45a8ff	2854	{
bogdanm	0:9b334a45a8ff	2855	/* Disable the ADC peripheral */
bogdanm	0:9b334a45a8ff	2856	ADC_DISABLE(hadc);
bogdanm	0:9b334a45a8ff	2857	}
bogdanm	0:9b334a45a8ff	2858	else
bogdanm	0:9b334a45a8ff	2859	{
bogdanm	0:9b334a45a8ff	2860	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	2861	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2862
bogdanm	0:9b334a45a8ff	2863	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	2864	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2865
bogdanm	0:9b334a45a8ff	2866	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2867	}
bogdanm	0:9b334a45a8ff	2868
bogdanm	0:9b334a45a8ff	2869	/* Wait for ADC effectively disabled */
bogdanm	0:9b334a45a8ff	2870	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2871
bogdanm	0:9b334a45a8ff	2872	while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
bogdanm	0:9b334a45a8ff	2873	{
bogdanm	0:9b334a45a8ff	2874	if((HAL_GetTick()-tickstart) > ADC_DISABLE_TIMEOUT)
bogdanm	0:9b334a45a8ff	2875	{
bogdanm	0:9b334a45a8ff	2876	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	2877	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2878
bogdanm	0:9b334a45a8ff	2879	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	2880	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
bogdanm	0:9b334a45a8ff	2881
bogdanm	0:9b334a45a8ff	2882	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2883	}
bogdanm	0:9b334a45a8ff	2884	}
bogdanm	0:9b334a45a8ff	2885	}
bogdanm	0:9b334a45a8ff	2886
bogdanm	0:9b334a45a8ff	2887	/* Return HAL status */
bogdanm	0:9b334a45a8ff	2888	return HAL_OK;
bogdanm	0:9b334a45a8ff	2889	}
bogdanm	0:9b334a45a8ff	2890
bogdanm	0:9b334a45a8ff	2891
bogdanm	0:9b334a45a8ff	2892	/**
bogdanm	0:9b334a45a8ff	2893	* @brief DMA transfer complete callback.
bogdanm	0:9b334a45a8ff	2894	* @param hdma: pointer to DMA handle.
bogdanm	0:9b334a45a8ff	2895	* @retval None
bogdanm	0:9b334a45a8ff	2896	*/
bogdanm	0:9b334a45a8ff	2897	void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2898	{
bogdanm	0:9b334a45a8ff	2899	/* Retrieve ADC handle corresponding to current DMA handle */
bogdanm	0:9b334a45a8ff	2900	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2901
bogdanm	0:9b334a45a8ff	2902	/* Update state machine on conversion status if not in error state */
bogdanm	0:9b334a45a8ff	2903	if (HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL\|HAL_ADC_STATE_ERROR_DMA)))
bogdanm	0:9b334a45a8ff	2904	{
bogdanm	0:9b334a45a8ff	2905	/* Update ADC state machine */
bogdanm	0:9b334a45a8ff	2906	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
bogdanm	0:9b334a45a8ff	2907	/* Is it the end of the regular sequence ? */
bogdanm	0:9b334a45a8ff	2908	if (HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS))
bogdanm	0:9b334a45a8ff	2909	{
bogdanm	0:9b334a45a8ff	2910	/* Are conversions software-triggered ? */
bogdanm	0:9b334a45a8ff	2911	if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
bogdanm	0:9b334a45a8ff	2912	{
bogdanm	0:9b334a45a8ff	2913	/* Is CONT bit set ? */
bogdanm	0:9b334a45a8ff	2914	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET)
bogdanm	0:9b334a45a8ff	2915	{
bogdanm	0:9b334a45a8ff	2916	/* CONT bit is not set, no more conversions expected */
bogdanm	0:9b334a45a8ff	2917	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
bogdanm	0:9b334a45a8ff	2918	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
bogdanm	0:9b334a45a8ff	2919	{
bogdanm	0:9b334a45a8ff	2920	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	2921	}
bogdanm	0:9b334a45a8ff	2922	}
bogdanm	0:9b334a45a8ff	2923	}
bogdanm	0:9b334a45a8ff	2924	}
bogdanm	0:9b334a45a8ff	2925	else
bogdanm	0:9b334a45a8ff	2926	{
bogdanm	0:9b334a45a8ff	2927	/* DMA End of Transfer interrupt was triggered but conversions sequence
bogdanm	0:9b334a45a8ff	2928	is not over. If DMACFG is set to 0, conversions are stopped. */
bogdanm	0:9b334a45a8ff	2929	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET)
bogdanm	0:9b334a45a8ff	2930	{
bogdanm	0:9b334a45a8ff	2931	/* DMACFG bit is not set, conversions are stopped. */
bogdanm	0:9b334a45a8ff	2932	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
bogdanm	0:9b334a45a8ff	2933	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
bogdanm	0:9b334a45a8ff	2934	{
bogdanm	0:9b334a45a8ff	2935	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
bogdanm	0:9b334a45a8ff	2936	}
bogdanm	0:9b334a45a8ff	2937	}
bogdanm	0:9b334a45a8ff	2938	}
bogdanm	0:9b334a45a8ff	2939
bogdanm	0:9b334a45a8ff	2940	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	2941	HAL_ADC_ConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	2942	}
bogdanm	0:9b334a45a8ff	2943	else /* DMA or internal error occurred (or both) */
bogdanm	0:9b334a45a8ff	2944	{
bogdanm	0:9b334a45a8ff	2945	/* In case of internal error, */
bogdanm	0:9b334a45a8ff	2946	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
bogdanm	0:9b334a45a8ff	2947	{
bogdanm	0:9b334a45a8ff	2948	/* call Error Callback function */
bogdanm	0:9b334a45a8ff	2949	HAL_ADC_ErrorCallback(hadc);
bogdanm	0:9b334a45a8ff	2950	}
bogdanm	0:9b334a45a8ff	2951
bogdanm	0:9b334a45a8ff	2952	}
bogdanm	0:9b334a45a8ff	2953
bogdanm	0:9b334a45a8ff	2954
bogdanm	0:9b334a45a8ff	2955	}
bogdanm	0:9b334a45a8ff	2956
bogdanm	0:9b334a45a8ff	2957	/**
bogdanm	0:9b334a45a8ff	2958	* @brief DMA half transfer complete callback.
bogdanm	0:9b334a45a8ff	2959	* @param hdma: pointer to DMA handle.
bogdanm	0:9b334a45a8ff	2960	* @retval None
bogdanm	0:9b334a45a8ff	2961	*/
bogdanm	0:9b334a45a8ff	2962	void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2963	{
bogdanm	0:9b334a45a8ff	2964	/* Retrieve ADC handle corresponding to current DMA handle */
bogdanm	0:9b334a45a8ff	2965	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2966
bogdanm	0:9b334a45a8ff	2967	/* Half conversion callback */
bogdanm	0:9b334a45a8ff	2968	HAL_ADC_ConvHalfCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	2969	}
bogdanm	0:9b334a45a8ff	2970
bogdanm	0:9b334a45a8ff	2971	/**
bogdanm	0:9b334a45a8ff	2972	* @brief DMA error callback.
bogdanm	0:9b334a45a8ff	2973	* @param hdma: pointer to DMA handle.
bogdanm	0:9b334a45a8ff	2974	* @retval None
bogdanm	0:9b334a45a8ff	2975	*/
bogdanm	0:9b334a45a8ff	2976	void ADC_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2977	{
bogdanm	0:9b334a45a8ff	2978	/* Retrieve ADC handle corresponding to current DMA handle */
bogdanm	0:9b334a45a8ff	2979	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2980
bogdanm	0:9b334a45a8ff	2981	/* Change ADC state */
bogdanm	0:9b334a45a8ff	2982	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
bogdanm	0:9b334a45a8ff	2983
bogdanm	0:9b334a45a8ff	2984	/* Set ADC error code to DMA error */
bogdanm	0:9b334a45a8ff	2985	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
bogdanm	0:9b334a45a8ff	2986
bogdanm	0:9b334a45a8ff	2987	/* Error callback */
bogdanm	0:9b334a45a8ff	2988	HAL_ADC_ErrorCallback(hadc);
bogdanm	0:9b334a45a8ff	2989	}
bogdanm	0:9b334a45a8ff	2990
bogdanm	0:9b334a45a8ff	2991
bogdanm	0:9b334a45a8ff	2992	/**
bogdanm	0:9b334a45a8ff	2993	* @}
bogdanm	0:9b334a45a8ff	2994	*/
bogdanm	0:9b334a45a8ff	2995
bogdanm	0:9b334a45a8ff	2996
bogdanm	0:9b334a45a8ff	2997	#endif /* HAL_ADC_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2998	/**
bogdanm	0:9b334a45a8ff	2999	* @}
bogdanm	0:9b334a45a8ff	3000	*/
bogdanm	0:9b334a45a8ff	3001
bogdanm	0:9b334a45a8ff	3002	/**
bogdanm	0:9b334a45a8ff	3003	* @}
bogdanm	0:9b334a45a8ff	3004	*/
bogdanm	0:9b334a45a8ff	3005
bogdanm	0:9b334a45a8ff	3006	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_adc.c@0:9b334a45a8ff, 2015-10-01 (annotated)

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