en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l1xx_hal_nor.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 5-September-2014
bogdanm 0:9b334a45a8ff 7 * @brief Header file of NOR HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32L1xx_HAL_NOR_H
bogdanm 0:9b334a45a8ff 40 #define __STM32L1xx_HAL_NOR_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32l1xx_ll_fsmc.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32L1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @addtogroup NOR
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /* Exported typedef ----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 /** @defgroup NOR_Exported_typedef NOR Exported typedef
bogdanm 0:9b334a45a8ff 62 * @{
bogdanm 0:9b334a45a8ff 63 */
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 /**
bogdanm 0:9b334a45a8ff 66 * @brief HAL SRAM State structures definition
bogdanm 0:9b334a45a8ff 67 */
bogdanm 0:9b334a45a8ff 68 typedef enum
bogdanm 0:9b334a45a8ff 69 {
bogdanm 0:9b334a45a8ff 70 HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
bogdanm 0:9b334a45a8ff 71 HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
bogdanm 0:9b334a45a8ff 72 HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
bogdanm 0:9b334a45a8ff 73 HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
bogdanm 0:9b334a45a8ff 74 HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 }HAL_NOR_StateTypeDef;
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 /**
bogdanm 0:9b334a45a8ff 79 * @brief FSMC NOR Status typedef
bogdanm 0:9b334a45a8ff 80 */
bogdanm 0:9b334a45a8ff 81 typedef enum
bogdanm 0:9b334a45a8ff 82 {
bogdanm 0:9b334a45a8ff 83 NOR_SUCCESS = 0,
bogdanm 0:9b334a45a8ff 84 NOR_ONGOING,
bogdanm 0:9b334a45a8ff 85 NOR_ERROR,
bogdanm 0:9b334a45a8ff 86 NOR_TIMEOUT
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 }NOR_StatusTypedef;
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /**
bogdanm 0:9b334a45a8ff 91 * @brief FSMC NOR ID typedef
bogdanm 0:9b334a45a8ff 92 */
bogdanm 0:9b334a45a8ff 93 typedef struct
bogdanm 0:9b334a45a8ff 94 {
bogdanm 0:9b334a45a8ff 95 uint16_t ManufacturerCode; /*!< Defines the device's manufacturer code used to identify the memory */
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 uint16_t DeviceCode1;
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 uint16_t DeviceCode2;
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 uint16_t DeviceCode3; /*!< Defines the devices' codes used to identify the memory.
bogdanm 0:9b334a45a8ff 102 These codes can be accessed by performing read operations with specific
bogdanm 0:9b334a45a8ff 103 control signals and addresses set.They can also be accessed by issuing
bogdanm 0:9b334a45a8ff 104 an Auto Select command */
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 }NOR_IDTypeDef;
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 /**
bogdanm 0:9b334a45a8ff 110 * @brief FSMC NOR CFI typedef
bogdanm 0:9b334a45a8ff 111 */
bogdanm 0:9b334a45a8ff 112 typedef struct
bogdanm 0:9b334a45a8ff 113 {
bogdanm 0:9b334a45a8ff 114 /*!< Defines the information stored in the memory's Common flash interface
bogdanm 0:9b334a45a8ff 115 which contains a description of various electrical and timing parameters,
bogdanm 0:9b334a45a8ff 116 density information and functions supported by the memory */
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 uint16_t CFI1;
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 uint16_t CFI2;
bogdanm 0:9b334a45a8ff 121
bogdanm 0:9b334a45a8ff 122 uint16_t CFI3;
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 uint16_t CFI4;
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 }NOR_CFITypeDef;
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /**
bogdanm 0:9b334a45a8ff 129 * @brief NOR handle Structure definition
bogdanm 0:9b334a45a8ff 130 */
bogdanm 0:9b334a45a8ff 131 typedef struct
bogdanm 0:9b334a45a8ff 132 {
bogdanm 0:9b334a45a8ff 133 FSMC_NORSRAM_TYPEDEF *Instance; /*!< Register base address */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 FSMC_NORSRAM_EXTENDED_TYPEDEF *Extended; /*!< Extended mode register base address */
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 HAL_LockTypeDef Lock; /*!< NOR locking object */
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 }NOR_HandleTypeDef;
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 /**
bogdanm 0:9b334a45a8ff 146 * @}
bogdanm 0:9b334a45a8ff 147 */
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /** @defgroup NOR_Exported_Constants NOR Exported Constants
bogdanm 0:9b334a45a8ff 152 * @{
bogdanm 0:9b334a45a8ff 153 */
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 /* NOR device IDs addresses */
bogdanm 0:9b334a45a8ff 156 #define MC_ADDRESS ((uint16_t)0x0000)
bogdanm 0:9b334a45a8ff 157 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
bogdanm 0:9b334a45a8ff 158 #define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
bogdanm 0:9b334a45a8ff 159 #define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /* NOR CFI IDs addresses */
bogdanm 0:9b334a45a8ff 162 #define CFI1_ADDRESS ((uint16_t)0x10)
bogdanm 0:9b334a45a8ff 163 #define CFI2_ADDRESS ((uint16_t)0x11)
bogdanm 0:9b334a45a8ff 164 #define CFI3_ADDRESS ((uint16_t)0x12)
bogdanm 0:9b334a45a8ff 165 #define CFI4_ADDRESS ((uint16_t)0x13)
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 /* NOR operation wait timeout */
bogdanm 0:9b334a45a8ff 168 #define NOR_TMEOUT ((uint16_t)0xFFFF)
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /* NOR memory data width */
bogdanm 0:9b334a45a8ff 171 #define NOR_MEMORY_8B ((uint8_t)0x0)
bogdanm 0:9b334a45a8ff 172 #define NOR_MEMORY_16B ((uint8_t)0x1)
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /* NOR memory device read/write start address */
bogdanm 0:9b334a45a8ff 175 #define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
bogdanm 0:9b334a45a8ff 176 #define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
bogdanm 0:9b334a45a8ff 177 #define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
bogdanm 0:9b334a45a8ff 178 #define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /**
bogdanm 0:9b334a45a8ff 181 * @}
bogdanm 0:9b334a45a8ff 182 */
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 /* Exported macro ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 /** @defgroup NOR_Exported_macro NOR Exported macro
bogdanm 0:9b334a45a8ff 187 * @{
bogdanm 0:9b334a45a8ff 188 */
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /** @brief Reset NOR handle state
bogdanm 0:9b334a45a8ff 191 * @param __HANDLE__: NOR handle
bogdanm 0:9b334a45a8ff 192 * @retval None
bogdanm 0:9b334a45a8ff 193 */
bogdanm 0:9b334a45a8ff 194 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 /**
bogdanm 0:9b334a45a8ff 198 * @brief NOR memory address shifting.
bogdanm 0:9b334a45a8ff 199 * @param __NOR_ADDRESS: NOR base address
bogdanm 0:9b334a45a8ff 200 * @param __NOR_MEMORY_WIDTH_: NOR memory width
bogdanm 0:9b334a45a8ff 201 * @param __ADDRESS__: NOR memory address
bogdanm 0:9b334a45a8ff 202 * @retval NOR shifted address value
bogdanm 0:9b334a45a8ff 203 */
bogdanm 0:9b334a45a8ff 204 #define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
bogdanm 0:9b334a45a8ff 205 ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
bogdanm 0:9b334a45a8ff 206 ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
bogdanm 0:9b334a45a8ff 207 ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /**
bogdanm 0:9b334a45a8ff 210 * @brief NOR memory write data to specified address.
bogdanm 0:9b334a45a8ff 211 * @param __ADDRESS__: NOR memory address
bogdanm 0:9b334a45a8ff 212 * @param __DATA__: Data to write
bogdanm 0:9b334a45a8ff 213 * @retval None
bogdanm 0:9b334a45a8ff 214 */
bogdanm 0:9b334a45a8ff 215 #define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /**
bogdanm 0:9b334a45a8ff 218 * @}
bogdanm 0:9b334a45a8ff 219 */
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 /** @addtogroup NOR_Exported_Functions
bogdanm 0:9b334a45a8ff 224 * @{
bogdanm 0:9b334a45a8ff 225 */
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /** @addtogroup NOR_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 228 * @{
bogdanm 0:9b334a45a8ff 229 */
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 /* Initialization/de-initialization functions **********************************/
bogdanm 0:9b334a45a8ff 232 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
bogdanm 0:9b334a45a8ff 233 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 234 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 235 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 236 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 /**
bogdanm 0:9b334a45a8ff 239 * @}
bogdanm 0:9b334a45a8ff 240 */
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 /** @addtogroup NOR_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 243 * @{
bogdanm 0:9b334a45a8ff 244 */
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 /* I/O operation functions *****************************************************/
bogdanm 0:9b334a45a8ff 247 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
bogdanm 0:9b334a45a8ff 248 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 249 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
bogdanm 0:9b334a45a8ff 250 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
bogdanm 0:9b334a45a8ff 253 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
bogdanm 0:9b334a45a8ff 256 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
bogdanm 0:9b334a45a8ff 257 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 /**
bogdanm 0:9b334a45a8ff 260 * @}
bogdanm 0:9b334a45a8ff 261 */
bogdanm 0:9b334a45a8ff 262
bogdanm 0:9b334a45a8ff 263 /** @addtogroup NOR_Exported_Functions_Group3
bogdanm 0:9b334a45a8ff 264 * @{
bogdanm 0:9b334a45a8ff 265 */
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 /* NOR Control functions *******************************************************/
bogdanm 0:9b334a45a8ff 268 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 269 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /**
bogdanm 0:9b334a45a8ff 272 * @}
bogdanm 0:9b334a45a8ff 273 */
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 /** @addtogroup NOR_Exported_Functions_Group4
bogdanm 0:9b334a45a8ff 276 * @{
bogdanm 0:9b334a45a8ff 277 */
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 /* NOR State functions **********************************************************/
bogdanm 0:9b334a45a8ff 280 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
bogdanm 0:9b334a45a8ff 281 NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 /**
bogdanm 0:9b334a45a8ff 284 * @}
bogdanm 0:9b334a45a8ff 285 */
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 /**
bogdanm 0:9b334a45a8ff 288 * @}
bogdanm 0:9b334a45a8ff 289 */
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 /**
bogdanm 0:9b334a45a8ff 294 * @}
bogdanm 0:9b334a45a8ff 295 */
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /**
bogdanm 0:9b334a45a8ff 298 * @}
bogdanm 0:9b334a45a8ff 299 */
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 302 }
bogdanm 0:9b334a45a8ff 303 #endif
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 #endif /* __STM32L1xx_HAL_NOR_H */
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/