mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l1xx_hal_adc.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 5-September-2014
bogdanm	0:9b334a45a8ff	7	* @brief Header file containing functions prototypes of ADC HAL library.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32L1xx_HAL_ADC_H
bogdanm	0:9b334a45a8ff	40	#define __STM32L1xx_HAL_ADC_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32l1xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48	/** @addtogroup STM32L1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	49	* @{
bogdanm	0:9b334a45a8ff	50	*/
bogdanm	0:9b334a45a8ff	51
bogdanm	0:9b334a45a8ff	52	/** @addtogroup ADC
bogdanm	0:9b334a45a8ff	53	* @{
bogdanm	0:9b334a45a8ff	54	*/
bogdanm	0:9b334a45a8ff	55
bogdanm	0:9b334a45a8ff	56	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	57	/** @defgroup ADC_Exported_Types ADC Exported Types
bogdanm	0:9b334a45a8ff	58	* @{
bogdanm	0:9b334a45a8ff	59	*/
bogdanm	0:9b334a45a8ff	60
bogdanm	0:9b334a45a8ff	61	/**
bogdanm	0:9b334a45a8ff	62	* @brief Structure definition of ADC and regular group initialization
bogdanm	0:9b334a45a8ff	63	* @note Parameters of this structure are shared within 2 scopes:
bogdanm	0:9b334a45a8ff	64	* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
bogdanm	0:9b334a45a8ff	65	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
bogdanm	0:9b334a45a8ff	66	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	67	* ADC state can be either:
bogdanm	0:9b334a45a8ff	68	* - For all parameters: ADC disabled
bogdanm	0:9b334a45a8ff	69	* - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
bogdanm	0:9b334a45a8ff	70	* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
bogdanm	0:9b334a45a8ff	71	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
bogdanm	0:9b334a45a8ff	72	* without error reporting without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
bogdanm	0:9b334a45a8ff	73	*/
bogdanm	0:9b334a45a8ff	74	typedef struct
bogdanm	0:9b334a45a8ff	75	{
bogdanm	0:9b334a45a8ff	76	uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler.
bogdanm	0:9b334a45a8ff	77	This parameter can be a value of @ref ADC_ClockPrescaler
bogdanm	0:9b334a45a8ff	78	Note: In case of usage of channels on injected group, ADC frequency should be low than AHB clock frequency /4 for resolution 12 or 10 bits,
bogdanm	0:9b334a45a8ff	79	AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
bogdanm	0:9b334a45a8ff	80	Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */
bogdanm	0:9b334a45a8ff	81	uint32_t Resolution; /*!< Configures the ADC resolution.
bogdanm	0:9b334a45a8ff	82	This parameter can be a value of @ref ADC_Resolution */
bogdanm	0:9b334a45a8ff	83	uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
bogdanm	0:9b334a45a8ff	84	or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
bogdanm	0:9b334a45a8ff	85	This parameter can be a value of @ref ADC_Data_align */
bogdanm	0:9b334a45a8ff	86	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
bogdanm	0:9b334a45a8ff	87	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
bogdanm	0:9b334a45a8ff	88	If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
bogdanm	0:9b334a45a8ff	89	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
bogdanm	0:9b334a45a8ff	90	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
bogdanm	0:9b334a45a8ff	91	Scan direction is upward: from rank1 to rank 'n'.
bogdanm	0:9b334a45a8ff	92	This parameter can be a value of @ref ADC_Scan_mode */
bogdanm	0:9b334a45a8ff	93	uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
bogdanm	0:9b334a45a8ff	94	This parameter can be a value of @ref ADC_EOCSelection.
bogdanm	0:9b334a45a8ff	95	Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
bogdanm	0:9b334a45a8ff	96	Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
bogdanm	0:9b334a45a8ff	97	or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
bogdanm	0:9b334a45a8ff	98	Note: If overrun feature is intending to be used in ADC mode 'interruption' (function HAL_ADC_Start_IT() ), parameter EOCSelection must be set to each conversion (this is not needed for ADC mode 'transfer by DMA', with function HAL_ADC_Start_DMA()) */
bogdanm	0:9b334a45a8ff	99	uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
bogdanm	0:9b334a45a8ff	100	conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
bogdanm	0:9b334a45a8ff	101	This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
bogdanm	0:9b334a45a8ff	102	This parameter can be a value of @ref ADC_LowPowerAutoWait.
bogdanm	0:9b334a45a8ff	103	Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
bogdanm	0:9b334a45a8ff	104	Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
bogdanm	0:9b334a45a8ff	105	and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion.
bogdanm	0:9b334a45a8ff	106	Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */
bogdanm	0:9b334a45a8ff	107	uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
bogdanm	0:9b334a45a8ff	108	This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
bogdanm	0:9b334a45a8ff	109	This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */
bogdanm	0:9b334a45a8ff	110	uint32_t ChannelsBank; /*!< Selects the ADC channels bank.
bogdanm	0:9b334a45a8ff	111	This parameter can be a value of @ref ADC_ChannelsBank.
bogdanm	0:9b334a45a8ff	112	Note: Banks availability depends on devices categories.
bogdanm	0:9b334a45a8ff	113	Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */
bogdanm	0:9b334a45a8ff	114	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
bogdanm	0:9b334a45a8ff	115	after the selected trigger occurred (software start or external trigger).
bogdanm	0:9b334a45a8ff	116	This parameter can be set to ENABLE or DISABLE. */
bogdanm	0:9b334a45a8ff	117	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined (STM32L152xE) \|\| defined (STM32L162xE)
bogdanm	0:9b334a45a8ff	118	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
bogdanm	0:9b334a45a8ff	119	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
bogdanm	0:9b334a45a8ff	120	This parameter must be a number between Min_Data = 1 and Max_Data = 28. */
bogdanm	0:9b334a45a8ff	121	#else
bogdanm	0:9b334a45a8ff	122	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
bogdanm	0:9b334a45a8ff	123	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
bogdanm	0:9b334a45a8ff	124	This parameter must be a number between Min_Data = 1 and Max_Data = 27. */
bogdanm	0:9b334a45a8ff	125	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L152xE \|\| STM32L162xE */
bogdanm	0:9b334a45a8ff	126	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
bogdanm	0:9b334a45a8ff	127	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
bogdanm	0:9b334a45a8ff	128	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
bogdanm	0:9b334a45a8ff	129	This parameter can be set to ENABLE or DISABLE. */
bogdanm	0:9b334a45a8ff	130	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
bogdanm	0:9b334a45a8ff	131	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
bogdanm	0:9b334a45a8ff	132	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
bogdanm	0:9b334a45a8ff	133	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
bogdanm	0:9b334a45a8ff	134	If set to ADC_SOFTWARE_START, external triggers are disabled.
bogdanm	0:9b334a45a8ff	135	If set to external trigger source, triggering is on event rising edge.
bogdanm	0:9b334a45a8ff	136	This parameter can be a value of @ref ADC_External_trigger_source_Regular */
bogdanm	0:9b334a45a8ff	137	uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
bogdanm	0:9b334a45a8ff	138	If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
bogdanm	0:9b334a45a8ff	139	This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
bogdanm	0:9b334a45a8ff	140	uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
bogdanm	0:9b334a45a8ff	141	or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
bogdanm	0:9b334a45a8ff	142	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
bogdanm	0:9b334a45a8ff	143	This parameter can be set to ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	144	Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could lauch a conversion). */
bogdanm	0:9b334a45a8ff	145	}ADC_InitTypeDef;
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	/**
bogdanm	0:9b334a45a8ff	148	* @brief Structure definition of ADC channel for regular group
bogdanm	0:9b334a45a8ff	149	* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	150	* ADC can be either disabled or enabled without conversion on going on regular group.
bogdanm	0:9b334a45a8ff	151	*/
bogdanm	0:9b334a45a8ff	152	typedef struct
bogdanm	0:9b334a45a8ff	153	{
bogdanm	0:9b334a45a8ff	154	uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
bogdanm	0:9b334a45a8ff	155	This parameter can be a value of @ref ADC_channels
bogdanm	0:9b334a45a8ff	156	Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
bogdanm	0:9b334a45a8ff	157	Maximum number of channels by device category (without taking in account each device package constraints):
bogdanm	0:9b334a45a8ff	158	STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26.
bogdanm	0:9b334a45a8ff	159	STM32L1 category 3: 25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
bogdanm	0:9b334a45a8ff	160	STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
bogdanm	0:9b334a45a8ff	161	Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '.
bogdanm	0:9b334a45a8ff	162	Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */
bogdanm	0:9b334a45a8ff	163	uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
bogdanm	0:9b334a45a8ff	164	This parameter can be a value of @ref ADC_regular_rank
bogdanm	0:9b334a45a8ff	165	Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
bogdanm	0:9b334a45a8ff	166	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
bogdanm	0:9b334a45a8ff	167	Unit: ADC clock cycles
bogdanm	0:9b334a45a8ff	168	Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
bogdanm	0:9b334a45a8ff	169	This parameter can be a value of @ref ADC_sampling_times
bogdanm	0:9b334a45a8ff	170	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
bogdanm	0:9b334a45a8ff	171	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
bogdanm	0:9b334a45a8ff	172	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
bogdanm	0:9b334a45a8ff	173	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
bogdanm	0:9b334a45a8ff	174	Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
bogdanm	0:9b334a45a8ff	175	}ADC_ChannelConfTypeDef;
bogdanm	0:9b334a45a8ff	176
bogdanm	0:9b334a45a8ff	177	/**
bogdanm	0:9b334a45a8ff	178	* @brief ADC Configuration analog watchdog definition
bogdanm	0:9b334a45a8ff	179	* @note The setting of these parameters with function is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	180	* ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
bogdanm	0:9b334a45a8ff	181	*/
bogdanm	0:9b334a45a8ff	182	typedef struct
bogdanm	0:9b334a45a8ff	183	{
bogdanm	0:9b334a45a8ff	184	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
bogdanm	0:9b334a45a8ff	185	This parameter can be a value of @ref ADC_analog_watchdog_mode. */
bogdanm	0:9b334a45a8ff	186	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
bogdanm	0:9b334a45a8ff	187	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
bogdanm	0:9b334a45a8ff	188	This parameter can be a value of @ref ADC_channels. */
bogdanm	0:9b334a45a8ff	189	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
bogdanm	0:9b334a45a8ff	190	This parameter can be set to ENABLE or DISABLE */
bogdanm	0:9b334a45a8ff	191	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm	0:9b334a45a8ff	192	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
bogdanm	0:9b334a45a8ff	193	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm	0:9b334a45a8ff	194	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
bogdanm	0:9b334a45a8ff	195	uint32_t WatchdogNumber; /!< Reserved for future use, can be set to 0 /
bogdanm	0:9b334a45a8ff	196	}ADC_AnalogWDGConfTypeDef;
bogdanm	0:9b334a45a8ff	197
bogdanm	0:9b334a45a8ff	198	/**
bogdanm	0:9b334a45a8ff	199	* @brief HAL ADC state machine: ADC States structure definition
bogdanm	0:9b334a45a8ff	200	*/
bogdanm	0:9b334a45a8ff	201	typedef enum
bogdanm	0:9b334a45a8ff	202	{
bogdanm	0:9b334a45a8ff	203	HAL_ADC_STATE_RESET = 0x00, /!< ADC not yet initialized or disabled /
bogdanm	0:9b334a45a8ff	204	HAL_ADC_STATE_READY = 0x01, /!< ADC peripheral ready for use /
bogdanm	0:9b334a45a8ff	205	HAL_ADC_STATE_BUSY = 0x02, /!< An internal process is ongoing /
bogdanm	0:9b334a45a8ff	206	HAL_ADC_STATE_BUSY_REG = 0x12, /!< Regular conversion is ongoing /
bogdanm	0:9b334a45a8ff	207	HAL_ADC_STATE_BUSY_INJ = 0x22, /!< Injected conversion is ongoing /
bogdanm	0:9b334a45a8ff	208	HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /!< Injected and regular conversion are ongoing /
bogdanm	0:9b334a45a8ff	209	HAL_ADC_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	0:9b334a45a8ff	210	HAL_ADC_STATE_ERROR = 0x04, /!< ADC state error /
bogdanm	0:9b334a45a8ff	211	HAL_ADC_STATE_EOC = 0x05, /!< Conversion is completed /
bogdanm	0:9b334a45a8ff	212	HAL_ADC_STATE_EOC_REG = 0x15, /!< Regular conversion is completed /
bogdanm	0:9b334a45a8ff	213	HAL_ADC_STATE_EOC_INJ = 0x25, /!< Injected conversion is completed /
bogdanm	0:9b334a45a8ff	214	HAL_ADC_STATE_EOC_INJ_REG = 0x35, /!< Injected and regular conversion are completed /
bogdanm	0:9b334a45a8ff	215	HAL_ADC_STATE_AWD = 0x06, /!< ADC state analog watchdog /
bogdanm	0:9b334a45a8ff	216	HAL_ADC_STATE_AWD2 = 0x07, /!< Not used on STM32L1xx devices (kept for compatibility with other devices featuring several AWD) /
bogdanm	0:9b334a45a8ff	217	HAL_ADC_STATE_AWD3 = 0x08, /!< Not used on STM32l1xx devices (kept for compatibility with other devices featuring several AWD) /
bogdanm	0:9b334a45a8ff	218	}HAL_ADC_StateTypeDef;
bogdanm	0:9b334a45a8ff	219
bogdanm	0:9b334a45a8ff	220	/**
bogdanm	0:9b334a45a8ff	221	* @brief ADC handle Structure definition
bogdanm	0:9b334a45a8ff	222	*/
bogdanm	0:9b334a45a8ff	223	typedef struct
bogdanm	0:9b334a45a8ff	224	{
bogdanm	0:9b334a45a8ff	225	ADC_TypeDef Instance; /!< Register base address */
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227	ADC_InitTypeDef Init; /!< ADC required parameters /
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	__IO uint32_t NbrOfConversionRank ; /!< ADC conversion rank counter /
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
bogdanm	0:9b334a45a8ff	232
bogdanm	0:9b334a45a8ff	233	HAL_LockTypeDef Lock; /!< ADC locking object /
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	__IO HAL_ADC_StateTypeDef State; /!< ADC communication state /
bogdanm	0:9b334a45a8ff	236
bogdanm	0:9b334a45a8ff	237	__IO uint32_t ErrorCode; /!< ADC Error code /
bogdanm	0:9b334a45a8ff	238	}ADC_HandleTypeDef;
bogdanm	0:9b334a45a8ff	239	/**
bogdanm	0:9b334a45a8ff	240	* @}
bogdanm	0:9b334a45a8ff	241	*/
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	/** @defgroup ADC_Exported_Constants ADC Exported Constants
bogdanm	0:9b334a45a8ff	248	* @{
bogdanm	0:9b334a45a8ff	249	*/
bogdanm	0:9b334a45a8ff	250
bogdanm	0:9b334a45a8ff	251	/** @defgroup ADC_Error_Code ADC Error Code
bogdanm	0:9b334a45a8ff	252	* @{
bogdanm	0:9b334a45a8ff	253	*/
bogdanm	0:9b334a45a8ff	254	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /!< No error /
bogdanm	0:9b334a45a8ff	255	#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
bogdanm	0:9b334a45a8ff	256	enable/disable, erroneous state */
bogdanm	0:9b334a45a8ff	257	#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /!< Overrun error /
bogdanm	0:9b334a45a8ff	258	#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /!< DMA transfer error /
bogdanm	0:9b334a45a8ff	259
bogdanm	0:9b334a45a8ff	260	/**
bogdanm	0:9b334a45a8ff	261	* @}
bogdanm	0:9b334a45a8ff	262	*/
bogdanm	0:9b334a45a8ff	263
bogdanm	0:9b334a45a8ff	264	/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
bogdanm	0:9b334a45a8ff	265	* @{
bogdanm	0:9b334a45a8ff	266	*/
bogdanm	0:9b334a45a8ff	267	#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler /
bogdanm	0:9b334a45a8ff	268	#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 /
bogdanm	0:9b334a45a8ff	269	#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 /
bogdanm	0:9b334a45a8ff	270
bogdanm	0:9b334a45a8ff	271	#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	272	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	273	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) )
bogdanm	0:9b334a45a8ff	274	/**
bogdanm	0:9b334a45a8ff	275	* @}
bogdanm	0:9b334a45a8ff	276	*/
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278	/** @defgroup ADC_Resolution ADC Resolution
bogdanm	0:9b334a45a8ff	279	* @{
bogdanm	0:9b334a45a8ff	280	*/
bogdanm	0:9b334a45a8ff	281	#define ADC_RESOLUTION12b ((uint32_t)0x00000000) /!< ADC 12-bit resolution /
bogdanm	0:9b334a45a8ff	282	#define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0) /!< ADC 10-bit resolution /
bogdanm	0:9b334a45a8ff	283	#define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1) /!< ADC 8-bit resolution /
bogdanm	0:9b334a45a8ff	284	#define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES) /!< ADC 6-bit resolution /
bogdanm	0:9b334a45a8ff	285
bogdanm	0:9b334a45a8ff	286	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) \|\| \
bogdanm	0:9b334a45a8ff	287	((RESOLUTION) == ADC_RESOLUTION10b) \|\| \
bogdanm	0:9b334a45a8ff	288	((RESOLUTION) == ADC_RESOLUTION8b) \|\| \
bogdanm	0:9b334a45a8ff	289	((RESOLUTION) == ADC_RESOLUTION6b) )
bogdanm	0:9b334a45a8ff	290
bogdanm	0:9b334a45a8ff	291	#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION8b) \|\| \
bogdanm	0:9b334a45a8ff	292	((RESOLUTION) == ADC_RESOLUTION6b) )
bogdanm	0:9b334a45a8ff	293	/**
bogdanm	0:9b334a45a8ff	294	* @}
bogdanm	0:9b334a45a8ff	295	*/
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/** @defgroup ADC_Data_align ADC Data_align
bogdanm	0:9b334a45a8ff	298	* @{
bogdanm	0:9b334a45a8ff	299	*/
bogdanm	0:9b334a45a8ff	300	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	301	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
bogdanm	0:9b334a45a8ff	302
bogdanm	0:9b334a45a8ff	303	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
bogdanm	0:9b334a45a8ff	304	((ALIGN) == ADC_DATAALIGN_LEFT) )
bogdanm	0:9b334a45a8ff	305	/**
bogdanm	0:9b334a45a8ff	306	* @}
bogdanm	0:9b334a45a8ff	307	*/
bogdanm	0:9b334a45a8ff	308
bogdanm	0:9b334a45a8ff	309	/** @defgroup ADC_Scan_mode ADC Scan mode
bogdanm	0:9b334a45a8ff	310	* @{
bogdanm	0:9b334a45a8ff	311	*/
bogdanm	0:9b334a45a8ff	312	#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	313	#define ADC_SCAN_ENABLE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	316	((SCAN_MODE) == ADC_SCAN_ENABLE) )
bogdanm	0:9b334a45a8ff	317	/**
bogdanm	0:9b334a45a8ff	318	* @}
bogdanm	0:9b334a45a8ff	319	*/
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	/** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular
bogdanm	0:9b334a45a8ff	322	* @{
bogdanm	0:9b334a45a8ff	323	*/
bogdanm	0:9b334a45a8ff	324	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	325	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
bogdanm	0:9b334a45a8ff	326	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
bogdanm	0:9b334a45a8ff	327	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	330	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
bogdanm	0:9b334a45a8ff	331	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	332	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
bogdanm	0:9b334a45a8ff	333	/**
bogdanm	0:9b334a45a8ff	334	* @}
bogdanm	0:9b334a45a8ff	335	*/
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
bogdanm	0:9b334a45a8ff	338	* @{
bogdanm	0:9b334a45a8ff	339	*/
bogdanm	0:9b334a45a8ff	340	/* List of external triggers with generic trigger name, sorted by trigger */
bogdanm	0:9b334a45a8ff	341	/* name: */
bogdanm	0:9b334a45a8ff	342
bogdanm	0:9b334a45a8ff	343	/* External triggers of regular group for ADC1 */
bogdanm	0:9b334a45a8ff	344	#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC_EXTERNALTRIG_T2_CC3
bogdanm	0:9b334a45a8ff	345	#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
bogdanm	0:9b334a45a8ff	346	#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG_T2_TRGO
bogdanm	0:9b334a45a8ff	347	#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC_EXTERNALTRIG_T3_CC1
bogdanm	0:9b334a45a8ff	348	#define ADC_EXTERNALTRIGCONV_T3_CC3 ADC_EXTERNALTRIG_T3_CC3
bogdanm	0:9b334a45a8ff	349	#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
bogdanm	0:9b334a45a8ff	350	#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4
bogdanm	0:9b334a45a8ff	351	#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC_EXTERNALTRIG_T4_TRGO
bogdanm	0:9b334a45a8ff	352	#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG_T6_TRGO
bogdanm	0:9b334a45a8ff	353	#define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2
bogdanm	0:9b334a45a8ff	354	#define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO
bogdanm	0:9b334a45a8ff	355	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
bogdanm	0:9b334a45a8ff	356
bogdanm	0:9b334a45a8ff	357	#define ADC_SOFTWARE_START ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \|\| \
bogdanm	0:9b334a45a8ff	360	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
bogdanm	0:9b334a45a8ff	361	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	362	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) \|\| \
bogdanm	0:9b334a45a8ff	363	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) \|\| \
bogdanm	0:9b334a45a8ff	364	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	365	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) \|\| \
bogdanm	0:9b334a45a8ff	366	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	367	((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	368	((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) \|\| \
bogdanm	0:9b334a45a8ff	369	((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	370	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
bogdanm	0:9b334a45a8ff	371	((REGTRIG) == ADC_SOFTWARE_START) )
bogdanm	0:9b334a45a8ff	372	/**
bogdanm	0:9b334a45a8ff	373	* @}
bogdanm	0:9b334a45a8ff	374	*/
bogdanm	0:9b334a45a8ff	375
bogdanm	0:9b334a45a8ff	376	/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular
bogdanm	0:9b334a45a8ff	377	* @{
bogdanm	0:9b334a45a8ff	378	*/
bogdanm	0:9b334a45a8ff	379
bogdanm	0:9b334a45a8ff	380	/* List of external triggers of regular group for ADC1: */
bogdanm	0:9b334a45a8ff	381	/* (used internally by HAL driver. To not use into HAL structure parameters) */
bogdanm	0:9b334a45a8ff	382
bogdanm	0:9b334a45a8ff	383	/* External triggers of regular group for ADC1 */
bogdanm	0:9b334a45a8ff	384	#define ADC_EXTERNALTRIG_T9_CC2 ((uint32_t) 0x00000000)
bogdanm	0:9b334a45a8ff	385	#define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0))
bogdanm	0:9b334a45a8ff	386	#define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
bogdanm	0:9b334a45a8ff	387	#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
bogdanm	0:9b334a45a8ff	388	#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 ))
bogdanm	0:9b334a45a8ff	389	#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
bogdanm	0:9b334a45a8ff	390	#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 ))
bogdanm	0:9b334a45a8ff	391	#define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
bogdanm	0:9b334a45a8ff	392	#define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 ))
bogdanm	0:9b334a45a8ff	393	#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_0))
bogdanm	0:9b334a45a8ff	394	#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 ))
bogdanm	0:9b334a45a8ff	395	#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397	/**
bogdanm	0:9b334a45a8ff	398	* @}
bogdanm	0:9b334a45a8ff	399	*/
bogdanm	0:9b334a45a8ff	400
bogdanm	0:9b334a45a8ff	401	/** @defgroup ADC_EOCSelection ADC EOCSelection
bogdanm	0:9b334a45a8ff	402	* @{
bogdanm	0:9b334a45a8ff	403	*/
bogdanm	0:9b334a45a8ff	404	#define EOC_SEQ_CONV ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	405	#define EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS)
bogdanm	0:9b334a45a8ff	406
bogdanm	0:9b334a45a8ff	407	#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) \|\| \
bogdanm	0:9b334a45a8ff	408	((EOC_SELECTION) == EOC_SEQ_CONV) )
bogdanm	0:9b334a45a8ff	409	/**
bogdanm	0:9b334a45a8ff	410	* @}
bogdanm	0:9b334a45a8ff	411	*/
bogdanm	0:9b334a45a8ff	412
bogdanm	0:9b334a45a8ff	413	/** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait
bogdanm	0:9b334a45a8ff	414	* @{
bogdanm	0:9b334a45a8ff	415	*/
bogdanm	0:9b334a45a8ff	416	/!< Note : For compatibility with other STM32 devices with ADC autowait /
bogdanm	0:9b334a45a8ff	417	/* feature limited to enable or disable settings: */
bogdanm	0:9b334a45a8ff	418	/* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */
bogdanm	0:9b334a45a8ff	419
bogdanm	0:9b334a45a8ff	420	#define ADC_AUTOWAIT_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	421	#define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read /
bogdanm	0:9b334a45a8ff	422	#define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /!< Insert a delay between ADC conversions: 7 APB clock cycles /
bogdanm	0:9b334a45a8ff	423	#define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 \| ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: 15 APB clock cycles /
bogdanm	0:9b334a45a8ff	424	#define ADC_AUTOWAIT_31_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 )) /!< Insert a delay between ADC conversions: 31 APB clock cycles /
bogdanm	0:9b334a45a8ff	425	#define ADC_AUTOWAIT_63_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 \| ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: 63 APB clock cycles /
bogdanm	0:9b334a45a8ff	426	#define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 \| ADC_CR2_DELS_1 )) /!< Insert a delay between ADC conversions: 127 APB clock cycles /
bogdanm	0:9b334a45a8ff	427	#define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 \| ADC_CR2_DELS_1 \| ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: 255 APB clock cycles /
bogdanm	0:9b334a45a8ff	428
bogdanm	0:9b334a45a8ff	429	#define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	430	((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) \|\| \
bogdanm	0:9b334a45a8ff	431	((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) \|\| \
bogdanm	0:9b334a45a8ff	432	((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) \|\| \
bogdanm	0:9b334a45a8ff	433	((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) \|\| \
bogdanm	0:9b334a45a8ff	434	((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) \|\| \
bogdanm	0:9b334a45a8ff	435	((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) \|\| \
bogdanm	0:9b334a45a8ff	436	((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) )
bogdanm	0:9b334a45a8ff	437	/**
bogdanm	0:9b334a45a8ff	438	* @}
bogdanm	0:9b334a45a8ff	439	*/
bogdanm	0:9b334a45a8ff	440
bogdanm	0:9b334a45a8ff	441	/** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff
bogdanm	0:9b334a45a8ff	442	* @{
bogdanm	0:9b334a45a8ff	443	*/
bogdanm	0:9b334a45a8ff	444	#define ADC_AUTOPOWEROFF_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	445	#define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /!< ADC power off when ADC is not converting (idle phase) /
bogdanm	0:9b334a45a8ff	446	#define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) /
bogdanm	0:9b334a45a8ff	447	#define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI \| ADC_CR1_PDD)) /!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions /
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	#define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	450	((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) \|\| \
bogdanm	0:9b334a45a8ff	451	((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) \|\| \
bogdanm	0:9b334a45a8ff	452	((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) )
bogdanm	0:9b334a45a8ff	453	/**
bogdanm	0:9b334a45a8ff	454	* @}
bogdanm	0:9b334a45a8ff	455	*/
bogdanm	0:9b334a45a8ff	456
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	/** @defgroup ADC_ChannelsBank ADC ChannelsBank
bogdanm	0:9b334a45a8ff	459	* @{
bogdanm	0:9b334a45a8ff	460	*/
bogdanm	0:9b334a45a8ff	461	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined (STM32L152xE) \|\| defined (STM32L162xE)
bogdanm	0:9b334a45a8ff	462	#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	463	#define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG)
bogdanm	0:9b334a45a8ff	464
bogdanm	0:9b334a45a8ff	465	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) \|\| \
bogdanm	0:9b334a45a8ff	466	((BANK) == ADC_CHANNELS_BANK_B) )
bogdanm	0:9b334a45a8ff	467	#else
bogdanm	0:9b334a45a8ff	468	#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
bogdanm	0:9b334a45a8ff	471	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L152xE \|\| STM32L162xE */
bogdanm	0:9b334a45a8ff	472	/**
bogdanm	0:9b334a45a8ff	473	* @}
bogdanm	0:9b334a45a8ff	474	*/
bogdanm	0:9b334a45a8ff	475
bogdanm	0:9b334a45a8ff	476	/** @defgroup ADC_channels ADC channels
bogdanm	0:9b334a45a8ff	477	* @{
bogdanm	0:9b334a45a8ff	478	*/
bogdanm	0:9b334a45a8ff	479	/* Note: Depending on devices, some channels may not be available on package */
bogdanm	0:9b334a45a8ff	480	/* pins. Refer to device datasheet for channels availability. */
bogdanm	0:9b334a45a8ff	481	#define ADC_CHANNEL_0 ((uint32_t)0x00000000) /* Channel different in bank A and bank B */
bogdanm	0:9b334a45a8ff	482	#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
bogdanm	0:9b334a45a8ff	483	#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
bogdanm	0:9b334a45a8ff	484	#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
bogdanm	0:9b334a45a8ff	485	#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR5_SQ1_2 )) /* Direct (fast) channel */
bogdanm	0:9b334a45a8ff	486	#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
bogdanm	0:9b334a45a8ff	487	#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
bogdanm	0:9b334a45a8ff	488	#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
bogdanm	0:9b334a45a8ff	489	#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR5_SQ1_3 )) /* Channel different in bank A and bank B */
bogdanm	0:9b334a45a8ff	490	#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
bogdanm	0:9b334a45a8ff	491	#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
bogdanm	0:9b334a45a8ff	492	#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
bogdanm	0:9b334a45a8ff	493	#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 )) /* Channel different in bank A and bank B */
bogdanm	0:9b334a45a8ff	494	#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	495	#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	496	#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	497	#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR5_SQ1_4 )) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	498	#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	499	#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	500	#define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	501	#define ADC_CHANNEL_20 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	502	#define ADC_CHANNEL_21 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	503	#define ADC_CHANNEL_22 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Direct (fast) channel */
bogdanm	0:9b334a45a8ff	504	#define ADC_CHANNEL_23 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
bogdanm	0:9b334a45a8ff	505	#define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */
bogdanm	0:9b334a45a8ff	506	#define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
bogdanm	0:9b334a45a8ff	507	#define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	508	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined (STM32L152xE) \|\| defined (STM32L162xE)
bogdanm	0:9b334a45a8ff	509	#define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	510	#define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	511	#define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	512	#define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	513	#define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
bogdanm	0:9b334a45a8ff	514	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L152xE \|\| STM32L162xE */
bogdanm	0:9b334a45a8ff	515
bogdanm	0:9b334a45a8ff	516	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
bogdanm	0:9b334a45a8ff	517	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
bogdanm	0:9b334a45a8ff	518	#define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
bogdanm	0:9b334a45a8ff	519
bogdanm	0:9b334a45a8ff	520	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined (STM32L152xE) \|\| defined (STM32L162xE)
bogdanm	0:9b334a45a8ff	521	#define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */
bogdanm	0:9b334a45a8ff	522	#define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */
bogdanm	0:9b334a45a8ff	523	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD)
bogdanm	0:9b334a45a8ff	524	#define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */
bogdanm	0:9b334a45a8ff	525	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD */
bogdanm	0:9b334a45a8ff	526	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L152xE \|\| STM32L162xE */
bogdanm	0:9b334a45a8ff	527
bogdanm	0:9b334a45a8ff	528	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
bogdanm	0:9b334a45a8ff	529	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
bogdanm	0:9b334a45a8ff	530	((CHANNEL) == ADC_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	531	((CHANNEL) == ADC_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	532	((CHANNEL) == ADC_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	533	((CHANNEL) == ADC_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	534	((CHANNEL) == ADC_CHANNEL_5) \|\| \
bogdanm	0:9b334a45a8ff	535	((CHANNEL) == ADC_CHANNEL_6) \|\| \
bogdanm	0:9b334a45a8ff	536	((CHANNEL) == ADC_CHANNEL_7) \|\| \
bogdanm	0:9b334a45a8ff	537	((CHANNEL) == ADC_CHANNEL_8) \|\| \
bogdanm	0:9b334a45a8ff	538	((CHANNEL) == ADC_CHANNEL_9) \|\| \
bogdanm	0:9b334a45a8ff	539	((CHANNEL) == ADC_CHANNEL_10) \|\| \
bogdanm	0:9b334a45a8ff	540	((CHANNEL) == ADC_CHANNEL_11) \|\| \
bogdanm	0:9b334a45a8ff	541	((CHANNEL) == ADC_CHANNEL_12) \|\| \
bogdanm	0:9b334a45a8ff	542	((CHANNEL) == ADC_CHANNEL_13) \|\| \
bogdanm	0:9b334a45a8ff	543	((CHANNEL) == ADC_CHANNEL_14) \|\| \
bogdanm	0:9b334a45a8ff	544	((CHANNEL) == ADC_CHANNEL_15) \|\| \
bogdanm	0:9b334a45a8ff	545	((CHANNEL) == ADC_CHANNEL_16) \|\| \
bogdanm	0:9b334a45a8ff	546	((CHANNEL) == ADC_CHANNEL_17) \|\| \
bogdanm	0:9b334a45a8ff	547	((CHANNEL) == ADC_CHANNEL_18) \|\| \
bogdanm	0:9b334a45a8ff	548	((CHANNEL) == ADC_CHANNEL_19) \|\| \
bogdanm	0:9b334a45a8ff	549	((CHANNEL) == ADC_CHANNEL_20) \|\| \
bogdanm	0:9b334a45a8ff	550	((CHANNEL) == ADC_CHANNEL_21) \|\| \
bogdanm	0:9b334a45a8ff	551	((CHANNEL) == ADC_CHANNEL_22) \|\| \
bogdanm	0:9b334a45a8ff	552	((CHANNEL) == ADC_CHANNEL_23) \|\| \
bogdanm	0:9b334a45a8ff	553	((CHANNEL) == ADC_CHANNEL_24) \|\| \
bogdanm	0:9b334a45a8ff	554	((CHANNEL) == ADC_CHANNEL_25) \|\| \
bogdanm	0:9b334a45a8ff	555	((CHANNEL) == ADC_CHANNEL_26) )
bogdanm	0:9b334a45a8ff	556	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
bogdanm	0:9b334a45a8ff	557	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined (STM32L152xE) \|\| defined (STM32L162xE)
bogdanm	0:9b334a45a8ff	558	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
bogdanm	0:9b334a45a8ff	559	((CHANNEL) == ADC_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	560	((CHANNEL) == ADC_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	561	((CHANNEL) == ADC_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	562	((CHANNEL) == ADC_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	563	((CHANNEL) == ADC_CHANNEL_5) \|\| \
bogdanm	0:9b334a45a8ff	564	((CHANNEL) == ADC_CHANNEL_6) \|\| \
bogdanm	0:9b334a45a8ff	565	((CHANNEL) == ADC_CHANNEL_7) \|\| \
bogdanm	0:9b334a45a8ff	566	((CHANNEL) == ADC_CHANNEL_8) \|\| \
bogdanm	0:9b334a45a8ff	567	((CHANNEL) == ADC_CHANNEL_9) \|\| \
bogdanm	0:9b334a45a8ff	568	((CHANNEL) == ADC_CHANNEL_10) \|\| \
bogdanm	0:9b334a45a8ff	569	((CHANNEL) == ADC_CHANNEL_11) \|\| \
bogdanm	0:9b334a45a8ff	570	((CHANNEL) == ADC_CHANNEL_12) \|\| \
bogdanm	0:9b334a45a8ff	571	((CHANNEL) == ADC_CHANNEL_13) \|\| \
bogdanm	0:9b334a45a8ff	572	((CHANNEL) == ADC_CHANNEL_14) \|\| \
bogdanm	0:9b334a45a8ff	573	((CHANNEL) == ADC_CHANNEL_15) \|\| \
bogdanm	0:9b334a45a8ff	574	((CHANNEL) == ADC_CHANNEL_16) \|\| \
bogdanm	0:9b334a45a8ff	575	((CHANNEL) == ADC_CHANNEL_17) \|\| \
bogdanm	0:9b334a45a8ff	576	((CHANNEL) == ADC_CHANNEL_18) \|\| \
bogdanm	0:9b334a45a8ff	577	((CHANNEL) == ADC_CHANNEL_19) \|\| \
bogdanm	0:9b334a45a8ff	578	((CHANNEL) == ADC_CHANNEL_20) \|\| \
bogdanm	0:9b334a45a8ff	579	((CHANNEL) == ADC_CHANNEL_21) \|\| \
bogdanm	0:9b334a45a8ff	580	((CHANNEL) == ADC_CHANNEL_22) \|\| \
bogdanm	0:9b334a45a8ff	581	((CHANNEL) == ADC_CHANNEL_23) \|\| \
bogdanm	0:9b334a45a8ff	582	((CHANNEL) == ADC_CHANNEL_24) \|\| \
bogdanm	0:9b334a45a8ff	583	((CHANNEL) == ADC_CHANNEL_25) \|\| \
bogdanm	0:9b334a45a8ff	584	((CHANNEL) == ADC_CHANNEL_26) \|\| \
bogdanm	0:9b334a45a8ff	585	((CHANNEL) == ADC_CHANNEL_27) \|\| \
bogdanm	0:9b334a45a8ff	586	((CHANNEL) == ADC_CHANNEL_28) \|\| \
bogdanm	0:9b334a45a8ff	587	((CHANNEL) == ADC_CHANNEL_29) \|\| \
bogdanm	0:9b334a45a8ff	588	((CHANNEL) == ADC_CHANNEL_30) \|\| \
bogdanm	0:9b334a45a8ff	589	((CHANNEL) == ADC_CHANNEL_31) )
bogdanm	0:9b334a45a8ff	590	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L152xE \|\| STM32L162xE */
bogdanm	0:9b334a45a8ff	591	/**
bogdanm	0:9b334a45a8ff	592	* @}
bogdanm	0:9b334a45a8ff	593	*/
bogdanm	0:9b334a45a8ff	594
bogdanm	0:9b334a45a8ff	595	/** @defgroup ADC_sampling_times ADC sampling times
bogdanm	0:9b334a45a8ff	596	* @{
bogdanm	0:9b334a45a8ff	597	*/
bogdanm	0:9b334a45a8ff	598	#define ADC_SAMPLETIME_4CYCLES ((uint32_t)0x00000000) /!< Sampling time 4 ADC clock cycles /
bogdanm	0:9b334a45a8ff	599	#define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /!< Sampling time 9 ADC clock cycles /
bogdanm	0:9b334a45a8ff	600	#define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /!< Sampling time 16 ADC clock cycles /
bogdanm	0:9b334a45a8ff	601	#define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 \| ADC_SMPR3_SMP0_0)) /!< Sampling time 24 ADC clock cycles /
bogdanm	0:9b334a45a8ff	602	#define ADC_SAMPLETIME_48CYCLES ((uint32_t) ADC_SMPR3_SMP0_2) /!< Sampling time 48 ADC clock cycles /
bogdanm	0:9b334a45a8ff	603	#define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 \| ADC_SMPR3_SMP0_0)) /!< Sampling time 96 ADC clock cycles /
bogdanm	0:9b334a45a8ff	604	#define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 \| ADC_SMPR3_SMP0_1)) /!< Sampling time 192 ADC clock cycles /
bogdanm	0:9b334a45a8ff	605	#define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /!< Sampling time 384 ADC clock cycles /
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	608	((TIME) == ADC_SAMPLETIME_9CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	609	((TIME) == ADC_SAMPLETIME_16CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	610	((TIME) == ADC_SAMPLETIME_24CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	611	((TIME) == ADC_SAMPLETIME_48CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	612	((TIME) == ADC_SAMPLETIME_96CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	613	((TIME) == ADC_SAMPLETIME_192CYCLES) \|\| \
bogdanm	0:9b334a45a8ff	614	((TIME) == ADC_SAMPLETIME_384CYCLES) )
bogdanm	0:9b334a45a8ff	615	/**
bogdanm	0:9b334a45a8ff	616	* @}
bogdanm	0:9b334a45a8ff	617	*/
bogdanm	0:9b334a45a8ff	618
bogdanm	0:9b334a45a8ff	619	/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
bogdanm	0:9b334a45a8ff	620	* @{
bogdanm	0:9b334a45a8ff	621	*/
bogdanm	0:9b334a45a8ff	622	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2 \
bogdanm	0:9b334a45a8ff	623	(ADC_SMPR3_SMP9_2 \| ADC_SMPR3_SMP8_2 \| ADC_SMPR3_SMP7_2 \| ADC_SMPR3_SMP6_2 \| \
bogdanm	0:9b334a45a8ff	624	ADC_SMPR3_SMP5_2 \| ADC_SMPR3_SMP4_2 \| ADC_SMPR3_SMP3_2 \| ADC_SMPR3_SMP2_2 \| \
bogdanm	0:9b334a45a8ff	625	ADC_SMPR3_SMP1_2 \| ADC_SMPR3_SMP0_2)
bogdanm	0:9b334a45a8ff	626	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
bogdanm	0:9b334a45a8ff	627	(ADC_SMPR2_SMP19_2 \| ADC_SMPR2_SMP18_2 \| ADC_SMPR2_SMP17_2 \| ADC_SMPR2_SMP16_2 \| \
bogdanm	0:9b334a45a8ff	628	ADC_SMPR2_SMP15_2 \| ADC_SMPR2_SMP14_2 \| ADC_SMPR2_SMP13_2 \| ADC_SMPR2_SMP12_2 \| \
bogdanm	0:9b334a45a8ff	629	ADC_SMPR2_SMP11_2 \| ADC_SMPR2_SMP10_2)
bogdanm	0:9b334a45a8ff	630	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
bogdanm	0:9b334a45a8ff	631	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
bogdanm	0:9b334a45a8ff	632	(ADC_SMPR1_SMP26_2 \| ADC_SMPR1_SMP25_2 \| ADC_SMPR1_SMP24_2 \| ADC_SMPR1_SMP23_2 \| \
bogdanm	0:9b334a45a8ff	633	ADC_SMPR1_SMP22_2 \| ADC_SMPR1_SMP21_2 \| ADC_SMPR1_SMP20_2)
bogdanm	0:9b334a45a8ff	634	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
bogdanm	0:9b334a45a8ff	635	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined (STM32L152xE) \|\| defined (STM32L162xE)
bogdanm	0:9b334a45a8ff	636	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
bogdanm	0:9b334a45a8ff	637	(ADC_SMPR1_SMP29_2 \| ADC_SMPR1_SMP28_2 \| ADC_SMPR1_SMP27_2 \| ADC_SMPR1_SMP26_2 \| \
bogdanm	0:9b334a45a8ff	638	ADC_SMPR1_SMP25_2 \| ADC_SMPR1_SMP24_2 \| ADC_SMPR1_SMP23_2 \| ADC_SMPR1_SMP22_2 \| \
bogdanm	0:9b334a45a8ff	639	ADC_SMPR1_SMP21_2 \| ADC_SMPR1_SMP20_2)
bogdanm	0:9b334a45a8ff	640	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \
bogdanm	0:9b334a45a8ff	641	(ADC_SMPR0_SMP31_2 \| ADC_SMPR0_SMP30_2 )
bogdanm	0:9b334a45a8ff	642	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L152xE \|\| STM32L162xE */
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \
bogdanm	0:9b334a45a8ff	645	(ADC_SMPR3_SMP9_1 \| ADC_SMPR3_SMP8_1 \| ADC_SMPR3_SMP7_1 \| ADC_SMPR3_SMP6_1 \| \
bogdanm	0:9b334a45a8ff	646	ADC_SMPR3_SMP5_1 \| ADC_SMPR3_SMP4_1 \| ADC_SMPR3_SMP3_1 \| ADC_SMPR3_SMP2_1 \| \
bogdanm	0:9b334a45a8ff	647	ADC_SMPR3_SMP1_1 \| ADC_SMPR3_SMP0_1)
bogdanm	0:9b334a45a8ff	648	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
bogdanm	0:9b334a45a8ff	649	(ADC_SMPR2_SMP19_1 \| ADC_SMPR2_SMP18_1 \| ADC_SMPR2_SMP17_1 \| ADC_SMPR2_SMP16_1 \| \
bogdanm	0:9b334a45a8ff	650	ADC_SMPR2_SMP15_1 \| ADC_SMPR2_SMP14_1 \| ADC_SMPR2_SMP13_1 \| ADC_SMPR2_SMP12_1 \| \
bogdanm	0:9b334a45a8ff	651	ADC_SMPR2_SMP11_1 \| ADC_SMPR2_SMP10_1)
bogdanm	0:9b334a45a8ff	652	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
bogdanm	0:9b334a45a8ff	653	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
bogdanm	0:9b334a45a8ff	654	(ADC_SMPR1_SMP26_1 \| ADC_SMPR1_SMP25_1 \| ADC_SMPR1_SMP24_1 \| ADC_SMPR1_SMP23_1 \| \
bogdanm	0:9b334a45a8ff	655	ADC_SMPR1_SMP22_1 \| ADC_SMPR1_SMP21_1 \| ADC_SMPR1_SMP20_1)
bogdanm	0:9b334a45a8ff	656	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
bogdanm	0:9b334a45a8ff	657	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined (STM32L152xE) \|\| defined (STM32L162xE)
bogdanm	0:9b334a45a8ff	658	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
bogdanm	0:9b334a45a8ff	659	(ADC_SMPR1_SMP29_1 \| ADC_SMPR1_SMP28_1 \| ADC_SMPR1_SMP27_1 \| ADC_SMPR1_SMP26_1 \| \
bogdanm	0:9b334a45a8ff	660	ADC_SMPR1_SMP25_1 \| ADC_SMPR1_SMP24_1 \| ADC_SMPR1_SMP23_1 \| ADC_SMPR1_SMP22_1 \| \
bogdanm	0:9b334a45a8ff	661	ADC_SMPR1_SMP21_1 \| ADC_SMPR1_SMP20_1)
bogdanm	0:9b334a45a8ff	662	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \
bogdanm	0:9b334a45a8ff	663	(ADC_SMPR0_SMP31_1 \| ADC_SMPR0_SMP30_1 )
bogdanm	0:9b334a45a8ff	664	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L152xE \|\| STM32L162xE */
bogdanm	0:9b334a45a8ff	665
bogdanm	0:9b334a45a8ff	666	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \
bogdanm	0:9b334a45a8ff	667	(ADC_SMPR3_SMP9_0 \| ADC_SMPR3_SMP8_0 \| ADC_SMPR3_SMP7_0 \| ADC_SMPR3_SMP6_0 \| \
bogdanm	0:9b334a45a8ff	668	ADC_SMPR3_SMP5_0 \| ADC_SMPR3_SMP4_0 \| ADC_SMPR3_SMP3_0 \| ADC_SMPR3_SMP2_0 \| \
bogdanm	0:9b334a45a8ff	669	ADC_SMPR3_SMP1_0 \| ADC_SMPR3_SMP0_0)
bogdanm	0:9b334a45a8ff	670	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
bogdanm	0:9b334a45a8ff	671	(ADC_SMPR2_SMP19_0 \| ADC_SMPR2_SMP18_0 \| ADC_SMPR2_SMP17_0 \| ADC_SMPR2_SMP16_0 \| \
bogdanm	0:9b334a45a8ff	672	ADC_SMPR2_SMP15_0 \| ADC_SMPR2_SMP14_0 \| ADC_SMPR2_SMP13_0 \| ADC_SMPR2_SMP12_0 \| \
bogdanm	0:9b334a45a8ff	673	ADC_SMPR2_SMP11_0 \| ADC_SMPR2_SMP10_0)
bogdanm	0:9b334a45a8ff	674	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
bogdanm	0:9b334a45a8ff	675	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
bogdanm	0:9b334a45a8ff	676	(ADC_SMPR1_SMP26_0 \| ADC_SMPR1_SMP25_0 \| ADC_SMPR1_SMP24_0 \| ADC_SMPR1_SMP23_0 \| \
bogdanm	0:9b334a45a8ff	677	ADC_SMPR1_SMP22_0 \| ADC_SMPR1_SMP21_0 \| ADC_SMPR1_SMP20_0)
bogdanm	0:9b334a45a8ff	678	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
bogdanm	0:9b334a45a8ff	679	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined (STM32L152xE) \|\| defined (STM32L162xE)
bogdanm	0:9b334a45a8ff	680	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
bogdanm	0:9b334a45a8ff	681	(ADC_SMPR1_SMP29_0 \| ADC_SMPR1_SMP28_0 \| ADC_SMPR1_SMP27_0 \| ADC_SMPR1_SMP26_0 \| \
bogdanm	0:9b334a45a8ff	682	ADC_SMPR1_SMP25_0 \| ADC_SMPR1_SMP24_0 \| ADC_SMPR1_SMP23_0 \| ADC_SMPR1_SMP22_0 \| \
bogdanm	0:9b334a45a8ff	683	ADC_SMPR1_SMP21_0 \| ADC_SMPR1_SMP20_0)
bogdanm	0:9b334a45a8ff	684	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \
bogdanm	0:9b334a45a8ff	685	(ADC_SMPR0_SMP31_0 \| ADC_SMPR0_SMP30_0 )
bogdanm	0:9b334a45a8ff	686	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L152xE \|\| STM32L162xE */
bogdanm	0:9b334a45a8ff	687	/**
bogdanm	0:9b334a45a8ff	688	* @}
bogdanm	0:9b334a45a8ff	689	*/
bogdanm	0:9b334a45a8ff	690
bogdanm	0:9b334a45a8ff	691	/** @defgroup ADC_regular_rank ADC regular rank
bogdanm	0:9b334a45a8ff	692	* @{
bogdanm	0:9b334a45a8ff	693	*/
bogdanm	0:9b334a45a8ff	694	#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	695	#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	696	#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	697	#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	698	#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
bogdanm	0:9b334a45a8ff	699	#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
bogdanm	0:9b334a45a8ff	700	#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
bogdanm	0:9b334a45a8ff	701	#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	702	#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
bogdanm	0:9b334a45a8ff	703	#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
bogdanm	0:9b334a45a8ff	704	#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
bogdanm	0:9b334a45a8ff	705	#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
bogdanm	0:9b334a45a8ff	706	#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
bogdanm	0:9b334a45a8ff	707	#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
bogdanm	0:9b334a45a8ff	708	#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	709	#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	710	#define ADC_REGULAR_RANK_17 ((uint32_t)0x00000011)
bogdanm	0:9b334a45a8ff	711	#define ADC_REGULAR_RANK_18 ((uint32_t)0x00000012)
bogdanm	0:9b334a45a8ff	712	#define ADC_REGULAR_RANK_19 ((uint32_t)0x00000013)
bogdanm	0:9b334a45a8ff	713	#define ADC_REGULAR_RANK_20 ((uint32_t)0x00000014)
bogdanm	0:9b334a45a8ff	714	#define ADC_REGULAR_RANK_21 ((uint32_t)0x00000015)
bogdanm	0:9b334a45a8ff	715	#define ADC_REGULAR_RANK_22 ((uint32_t)0x00000016)
bogdanm	0:9b334a45a8ff	716	#define ADC_REGULAR_RANK_23 ((uint32_t)0x00000017)
bogdanm	0:9b334a45a8ff	717	#define ADC_REGULAR_RANK_24 ((uint32_t)0x00000018)
bogdanm	0:9b334a45a8ff	718	#define ADC_REGULAR_RANK_25 ((uint32_t)0x00000019)
bogdanm	0:9b334a45a8ff	719	#define ADC_REGULAR_RANK_26 ((uint32_t)0x0000001A)
bogdanm	0:9b334a45a8ff	720	#define ADC_REGULAR_RANK_27 ((uint32_t)0x0000001B)
bogdanm	0:9b334a45a8ff	721	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined (STM32L152xE) \|\| defined (STM32L162xE)
bogdanm	0:9b334a45a8ff	722	#define ADC_REGULAR_RANK_28 ((uint32_t)0x0000001C)
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
bogdanm	0:9b334a45a8ff	725	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
bogdanm	0:9b334a45a8ff	726	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
bogdanm	0:9b334a45a8ff	727	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
bogdanm	0:9b334a45a8ff	728	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
bogdanm	0:9b334a45a8ff	729	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
bogdanm	0:9b334a45a8ff	730	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
bogdanm	0:9b334a45a8ff	731	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
bogdanm	0:9b334a45a8ff	732	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
bogdanm	0:9b334a45a8ff	733	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
bogdanm	0:9b334a45a8ff	734	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
bogdanm	0:9b334a45a8ff	735	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
bogdanm	0:9b334a45a8ff	736	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
bogdanm	0:9b334a45a8ff	737	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
bogdanm	0:9b334a45a8ff	738	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
bogdanm	0:9b334a45a8ff	739	((CHANNEL) == ADC_REGULAR_RANK_16) \|\| \
bogdanm	0:9b334a45a8ff	740	((CHANNEL) == ADC_REGULAR_RANK_17) \|\| \
bogdanm	0:9b334a45a8ff	741	((CHANNEL) == ADC_REGULAR_RANK_18) \|\| \
bogdanm	0:9b334a45a8ff	742	((CHANNEL) == ADC_REGULAR_RANK_19) \|\| \
bogdanm	0:9b334a45a8ff	743	((CHANNEL) == ADC_REGULAR_RANK_20) \|\| \
bogdanm	0:9b334a45a8ff	744	((CHANNEL) == ADC_REGULAR_RANK_21) \|\| \
bogdanm	0:9b334a45a8ff	745	((CHANNEL) == ADC_REGULAR_RANK_22) \|\| \
bogdanm	0:9b334a45a8ff	746	((CHANNEL) == ADC_REGULAR_RANK_23) \|\| \
bogdanm	0:9b334a45a8ff	747	((CHANNEL) == ADC_REGULAR_RANK_24) \|\| \
bogdanm	0:9b334a45a8ff	748	((CHANNEL) == ADC_REGULAR_RANK_25) \|\| \
bogdanm	0:9b334a45a8ff	749	((CHANNEL) == ADC_REGULAR_RANK_26) \|\| \
bogdanm	0:9b334a45a8ff	750	((CHANNEL) == ADC_REGULAR_RANK_27) \|\| \
bogdanm	0:9b334a45a8ff	751	((CHANNEL) == ADC_REGULAR_RANK_28) )
bogdanm	0:9b334a45a8ff	752	#else
bogdanm	0:9b334a45a8ff	753
bogdanm	0:9b334a45a8ff	754	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
bogdanm	0:9b334a45a8ff	755	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
bogdanm	0:9b334a45a8ff	756	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
bogdanm	0:9b334a45a8ff	757	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
bogdanm	0:9b334a45a8ff	758	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
bogdanm	0:9b334a45a8ff	759	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
bogdanm	0:9b334a45a8ff	760	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
bogdanm	0:9b334a45a8ff	761	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
bogdanm	0:9b334a45a8ff	762	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
bogdanm	0:9b334a45a8ff	763	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
bogdanm	0:9b334a45a8ff	764	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
bogdanm	0:9b334a45a8ff	765	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
bogdanm	0:9b334a45a8ff	766	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
bogdanm	0:9b334a45a8ff	767	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
bogdanm	0:9b334a45a8ff	768	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
bogdanm	0:9b334a45a8ff	769	((CHANNEL) == ADC_REGULAR_RANK_16) \|\| \
bogdanm	0:9b334a45a8ff	770	((CHANNEL) == ADC_REGULAR_RANK_17) \|\| \
bogdanm	0:9b334a45a8ff	771	((CHANNEL) == ADC_REGULAR_RANK_18) \|\| \
bogdanm	0:9b334a45a8ff	772	((CHANNEL) == ADC_REGULAR_RANK_19) \|\| \
bogdanm	0:9b334a45a8ff	773	((CHANNEL) == ADC_REGULAR_RANK_20) \|\| \
bogdanm	0:9b334a45a8ff	774	((CHANNEL) == ADC_REGULAR_RANK_21) \|\| \
bogdanm	0:9b334a45a8ff	775	((CHANNEL) == ADC_REGULAR_RANK_22) \|\| \
bogdanm	0:9b334a45a8ff	776	((CHANNEL) == ADC_REGULAR_RANK_23) \|\| \
bogdanm	0:9b334a45a8ff	777	((CHANNEL) == ADC_REGULAR_RANK_24) \|\| \
bogdanm	0:9b334a45a8ff	778	((CHANNEL) == ADC_REGULAR_RANK_25) \|\| \
bogdanm	0:9b334a45a8ff	779	((CHANNEL) == ADC_REGULAR_RANK_26) \|\| \
bogdanm	0:9b334a45a8ff	780	((CHANNEL) == ADC_REGULAR_RANK_27) )
bogdanm	0:9b334a45a8ff	781	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L152xE \|\| STM32L162xE */
bogdanm	0:9b334a45a8ff	782	/**
bogdanm	0:9b334a45a8ff	783	* @}
bogdanm	0:9b334a45a8ff	784	*/
bogdanm	0:9b334a45a8ff	785
bogdanm	0:9b334a45a8ff	786	/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
bogdanm	0:9b334a45a8ff	787	* @{
bogdanm	0:9b334a45a8ff	788	*/
bogdanm	0:9b334a45a8ff	789	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	790	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
bogdanm	0:9b334a45a8ff	791	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
bogdanm	0:9b334a45a8ff	792	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
bogdanm	0:9b334a45a8ff	793	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
bogdanm	0:9b334a45a8ff	794	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
bogdanm	0:9b334a45a8ff	795	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) \|\| \
bogdanm	0:9b334a45a8ff	798	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
bogdanm	0:9b334a45a8ff	799	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
bogdanm	0:9b334a45a8ff	800	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
bogdanm	0:9b334a45a8ff	801	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
bogdanm	0:9b334a45a8ff	802	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
bogdanm	0:9b334a45a8ff	803	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
bogdanm	0:9b334a45a8ff	804	/**
bogdanm	0:9b334a45a8ff	805	* @}
bogdanm	0:9b334a45a8ff	806	*/
bogdanm	0:9b334a45a8ff	807
bogdanm	0:9b334a45a8ff	808	/** @defgroup ADC_conversion_group ADC conversion group
bogdanm	0:9b334a45a8ff	809	* @{
bogdanm	0:9b334a45a8ff	810	*/
bogdanm	0:9b334a45a8ff	811	#define REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
bogdanm	0:9b334a45a8ff	812	#define INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
bogdanm	0:9b334a45a8ff	813	#define REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_JEOC))
bogdanm	0:9b334a45a8ff	814
bogdanm	0:9b334a45a8ff	815	#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == REGULAR_GROUP) \|\| \
bogdanm	0:9b334a45a8ff	816	((CONVERSION) == INJECTED_GROUP) \|\| \
bogdanm	0:9b334a45a8ff	817	((CONVERSION) == REGULAR_INJECTED_GROUP) )
bogdanm	0:9b334a45a8ff	818	/**
bogdanm	0:9b334a45a8ff	819	* @}
bogdanm	0:9b334a45a8ff	820	*/
bogdanm	0:9b334a45a8ff	821
bogdanm	0:9b334a45a8ff	822	/** @defgroup ADC_Event_type ADC Event type
bogdanm	0:9b334a45a8ff	823	* @{
bogdanm	0:9b334a45a8ff	824	*/
bogdanm	0:9b334a45a8ff	825	#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /!< ADC Analog watchdog event /
bogdanm	0:9b334a45a8ff	826	#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /!< ADC overrun event /
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) \|\| \
bogdanm	0:9b334a45a8ff	829	((EVENT) == ADC_FLAG_OVR) )
bogdanm	0:9b334a45a8ff	830	/**
bogdanm	0:9b334a45a8ff	831	* @}
bogdanm	0:9b334a45a8ff	832	*/
bogdanm	0:9b334a45a8ff	833
bogdanm	0:9b334a45a8ff	834	/** @defgroup ADC_interrupts_definition ADC interrupts definition
bogdanm	0:9b334a45a8ff	835	* @{
bogdanm	0:9b334a45a8ff	836	*/
bogdanm	0:9b334a45a8ff	837	#define ADC_IT_EOC ADC_CR1_EOCIE /!< ADC End of Regular Conversion interrupt source /
bogdanm	0:9b334a45a8ff	838	#define ADC_IT_JEOC ADC_CR1_JEOCIE /!< ADC End of Injected Conversion interrupt source /
bogdanm	0:9b334a45a8ff	839	#define ADC_IT_AWD ADC_CR1_AWDIE /!< ADC Analog watchdog interrupt source /
bogdanm	0:9b334a45a8ff	840	#define ADC_IT_OVR ADC_CR1_OVRIE /!< ADC overrun interrupt source /
bogdanm	0:9b334a45a8ff	841	/**
bogdanm	0:9b334a45a8ff	842	* @}
bogdanm	0:9b334a45a8ff	843	*/
bogdanm	0:9b334a45a8ff	844
bogdanm	0:9b334a45a8ff	845	/** @defgroup ADC_flags_definition ADC flags definition
bogdanm	0:9b334a45a8ff	846	* @{
bogdanm	0:9b334a45a8ff	847	*/
bogdanm	0:9b334a45a8ff	848	#define ADC_FLAG_AWD ADC_SR_AWD /!< ADC Analog watchdog flag /
bogdanm	0:9b334a45a8ff	849	#define ADC_FLAG_EOC ADC_SR_EOC /!< ADC End of Regular conversion flag /
bogdanm	0:9b334a45a8ff	850	#define ADC_FLAG_JEOC ADC_SR_JEOC /!< ADC End of Injected conversion flag /
bogdanm	0:9b334a45a8ff	851	#define ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC Injected group start flag /
bogdanm	0:9b334a45a8ff	852	#define ADC_FLAG_STRT ADC_SR_STRT /!< ADC Regular group start flag /
bogdanm	0:9b334a45a8ff	853	#define ADC_FLAG_OVR ADC_SR_OVR /!< ADC overrun flag /
bogdanm	0:9b334a45a8ff	854	#define ADC_FLAG_ADONS ADC_SR_ADONS /!< ADC ready status flag /
bogdanm	0:9b334a45a8ff	855	#define ADC_FLAG_RCNR ADC_SR_RCNR /!< ADC Regular group ready status flag /
bogdanm	0:9b334a45a8ff	856	#define ADC_FLAG_JCNR ADC_SR_JCNR /!< ADC Regular group ready status flag /
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858	/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
bogdanm	0:9b334a45a8ff	859	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_JEOC \| ADC_FLAG_AWD \| \
bogdanm	0:9b334a45a8ff	860	ADC_FLAG_OVR)
bogdanm	0:9b334a45a8ff	861	/**
bogdanm	0:9b334a45a8ff	862	* @}
bogdanm	0:9b334a45a8ff	863	*/
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	/** @defgroup ADC_range_verification ADC range verification
bogdanm	0:9b334a45a8ff	866	* For a unique ADC resolution: 12 bits
bogdanm	0:9b334a45a8ff	867	* @{
bogdanm	0:9b334a45a8ff	868	*/
bogdanm	0:9b334a45a8ff	869	#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF))
bogdanm	0:9b334a45a8ff	870	/**
bogdanm	0:9b334a45a8ff	871	* @}
bogdanm	0:9b334a45a8ff	872	*/
bogdanm	0:9b334a45a8ff	873
bogdanm	0:9b334a45a8ff	874	/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
bogdanm	0:9b334a45a8ff	875	* @{
bogdanm	0:9b334a45a8ff	876	*/
bogdanm	0:9b334a45a8ff	877	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined (STM32L152xE) \|\| defined (STM32L162xE)
bogdanm	0:9b334a45a8ff	878	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28)))
bogdanm	0:9b334a45a8ff	879	#else
bogdanm	0:9b334a45a8ff	880	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27)))
bogdanm	0:9b334a45a8ff	881	#endif
bogdanm	0:9b334a45a8ff	882	/**
bogdanm	0:9b334a45a8ff	883	* @}
bogdanm	0:9b334a45a8ff	884	*/
bogdanm	0:9b334a45a8ff	885
bogdanm	0:9b334a45a8ff	886	/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
bogdanm	0:9b334a45a8ff	887	* @{
bogdanm	0:9b334a45a8ff	888	*/
bogdanm	0:9b334a45a8ff	889	#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
bogdanm	0:9b334a45a8ff	890	/**
bogdanm	0:9b334a45a8ff	891	* @}
bogdanm	0:9b334a45a8ff	892	*/
bogdanm	0:9b334a45a8ff	893
bogdanm	0:9b334a45a8ff	894	/**
bogdanm	0:9b334a45a8ff	895	* @}
bogdanm	0:9b334a45a8ff	896	*/
bogdanm	0:9b334a45a8ff	897
bogdanm	0:9b334a45a8ff	898	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	899
bogdanm	0:9b334a45a8ff	900	/** @defgroup ADC_Exported_Macros ADC Exported Macros
bogdanm	0:9b334a45a8ff	901	* @{
bogdanm	0:9b334a45a8ff	902	*/
bogdanm	0:9b334a45a8ff	903	/* Macro for internal HAL driver usage, and possibly can be used into code of */
bogdanm	0:9b334a45a8ff	904	/* final user. */
bogdanm	0:9b334a45a8ff	905
bogdanm	0:9b334a45a8ff	906	/**
bogdanm	0:9b334a45a8ff	907	* @brief Verification of ADC state: enabled or disabled
bogdanm	0:9b334a45a8ff	908	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	909	* @retval SET (ADC enabled) or RESET (ADC disabled)
bogdanm	0:9b334a45a8ff	910	*/
bogdanm	0:9b334a45a8ff	911	#define __HAL_ADC_IS_ENABLED(__HANDLE__) \
bogdanm	0:9b334a45a8ff	912	((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
bogdanm	0:9b334a45a8ff	913	) ? SET : RESET)
bogdanm	0:9b334a45a8ff	914
bogdanm	0:9b334a45a8ff	915	/**
bogdanm	0:9b334a45a8ff	916	* @brief Test if conversion trigger of regular group is software start
bogdanm	0:9b334a45a8ff	917	* or external trigger.
bogdanm	0:9b334a45a8ff	918	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	919	* @retval SET (software start) or RESET (external trigger)
bogdanm	0:9b334a45a8ff	920	*/
bogdanm	0:9b334a45a8ff	921	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
bogdanm	0:9b334a45a8ff	922	(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
bogdanm	0:9b334a45a8ff	923
bogdanm	0:9b334a45a8ff	924	/**
bogdanm	0:9b334a45a8ff	925	* @brief Test if conversion trigger of injected group is software start
bogdanm	0:9b334a45a8ff	926	* or external trigger.
bogdanm	0:9b334a45a8ff	927	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	928	* @retval SET (software start) or RESET (external trigger)
bogdanm	0:9b334a45a8ff	929	*/
bogdanm	0:9b334a45a8ff	930	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
bogdanm	0:9b334a45a8ff	931	(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
bogdanm	0:9b334a45a8ff	932
bogdanm	0:9b334a45a8ff	933	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
bogdanm	0:9b334a45a8ff	934	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	935	* @param __INTERRUPT__: ADC interrupt source to check
bogdanm	0:9b334a45a8ff	936	* @retval State of interruption (SET or RESET)
bogdanm	0:9b334a45a8ff	937	*/
bogdanm	0:9b334a45a8ff	938	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
bogdanm	0:9b334a45a8ff	939	(( ((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__) \
bogdanm	0:9b334a45a8ff	940	)? SET : RESET \
bogdanm	0:9b334a45a8ff	941	)
bogdanm	0:9b334a45a8ff	942
bogdanm	0:9b334a45a8ff	943	/**
bogdanm	0:9b334a45a8ff	944	* @brief Enable the ADC end of conversion interrupt.
bogdanm	0:9b334a45a8ff	945	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	946	* @param __INTERRUPT__: ADC Interrupt
bogdanm	0:9b334a45a8ff	947	* @retval None
bogdanm	0:9b334a45a8ff	948	*/
bogdanm	0:9b334a45a8ff	949	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
bogdanm	0:9b334a45a8ff	950	(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
bogdanm	0:9b334a45a8ff	951
bogdanm	0:9b334a45a8ff	952	/**
bogdanm	0:9b334a45a8ff	953	* @brief Disable the ADC end of conversion interrupt.
bogdanm	0:9b334a45a8ff	954	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	955	* @param __INTERRUPT__: ADC Interrupt
bogdanm	0:9b334a45a8ff	956	* @retval None
bogdanm	0:9b334a45a8ff	957	*/
bogdanm	0:9b334a45a8ff	958	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
bogdanm	0:9b334a45a8ff	959	(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
bogdanm	0:9b334a45a8ff	960
bogdanm	0:9b334a45a8ff	961	/**
bogdanm	0:9b334a45a8ff	962	* @brief Get the selected ADC's flag status.
bogdanm	0:9b334a45a8ff	963	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	964	* @param __FLAG__: ADC flag
bogdanm	0:9b334a45a8ff	965	* @retval None
bogdanm	0:9b334a45a8ff	966	*/
bogdanm	0:9b334a45a8ff	967	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
bogdanm	0:9b334a45a8ff	968	((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	969
bogdanm	0:9b334a45a8ff	970	/**
bogdanm	0:9b334a45a8ff	971	* @brief Clear the ADC's pending flags
bogdanm	0:9b334a45a8ff	972	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	973	* @param __FLAG__: ADC flag
bogdanm	0:9b334a45a8ff	974	* @retval None
bogdanm	0:9b334a45a8ff	975	*/
bogdanm	0:9b334a45a8ff	976	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
bogdanm	0:9b334a45a8ff	977
bogdanm	0:9b334a45a8ff	978	/**
bogdanm	0:9b334a45a8ff	979	* @brief Clear ADC error code (set it to error code: "no error")
bogdanm	0:9b334a45a8ff	980	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	981	* @retval None
bogdanm	0:9b334a45a8ff	982	*/
bogdanm	0:9b334a45a8ff	983	#define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	984	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	/** @brief Reset ADC handle state
bogdanm	0:9b334a45a8ff	987	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	988	* @retval None
bogdanm	0:9b334a45a8ff	989	*/
bogdanm	0:9b334a45a8ff	990	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992	/**
bogdanm	0:9b334a45a8ff	993	* @}
bogdanm	0:9b334a45a8ff	994	*/
bogdanm	0:9b334a45a8ff	995
bogdanm	0:9b334a45a8ff	996	/* Include ADC HAL Extension module */
bogdanm	0:9b334a45a8ff	997	#include "stm32l1xx_hal_adc_ex.h"
bogdanm	0:9b334a45a8ff	998
bogdanm	0:9b334a45a8ff	999	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1000	/** @addtogroup ADC_Exported_Functions
bogdanm	0:9b334a45a8ff	1001	* @{
bogdanm	0:9b334a45a8ff	1002	*/
bogdanm	0:9b334a45a8ff	1003
bogdanm	0:9b334a45a8ff	1004	/** @addtogroup ADC_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	1005	* @{
bogdanm	0:9b334a45a8ff	1006	*/
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008
bogdanm	0:9b334a45a8ff	1009	/* Initialization and de-initialization functions **********************************/
bogdanm	0:9b334a45a8ff	1010	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1011	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
bogdanm	0:9b334a45a8ff	1012	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1013	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1014	/**
bogdanm	0:9b334a45a8ff	1015	* @}
bogdanm	0:9b334a45a8ff	1016	*/
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	/* IO operation functions *****************************************************/
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	/** @addtogroup ADC_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	1021	* @{
bogdanm	0:9b334a45a8ff	1022	*/
bogdanm	0:9b334a45a8ff	1023
bogdanm	0:9b334a45a8ff	1024
bogdanm	0:9b334a45a8ff	1025	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1026	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1027	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1028	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	1029	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	1030
bogdanm	0:9b334a45a8ff	1031	/* Non-blocking mode: Interruption */
bogdanm	0:9b334a45a8ff	1032	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1033	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	/* Non-blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1036	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
bogdanm	0:9b334a45a8ff	1037	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039	/* ADC retrieve conversion value intended to be used with polling or interruption */
bogdanm	0:9b334a45a8ff	1040	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1041
bogdanm	0:9b334a45a8ff	1042	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
bogdanm	0:9b334a45a8ff	1043	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1044	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1045	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1046	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1047	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
bogdanm	0:9b334a45a8ff	1048	/**
bogdanm	0:9b334a45a8ff	1049	* @}
bogdanm	0:9b334a45a8ff	1050	*/
bogdanm	0:9b334a45a8ff	1051
bogdanm	0:9b334a45a8ff	1052
bogdanm	0:9b334a45a8ff	1053	/* Peripheral Control functions ***********************************************/
bogdanm	0:9b334a45a8ff	1054	/** @addtogroup ADC_Exported_Functions_Group3
bogdanm	0:9b334a45a8ff	1055	* @{
bogdanm	0:9b334a45a8ff	1056	*/
bogdanm	0:9b334a45a8ff	1057	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
bogdanm	0:9b334a45a8ff	1058	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
bogdanm	0:9b334a45a8ff	1059	/**
bogdanm	0:9b334a45a8ff	1060	* @}
bogdanm	0:9b334a45a8ff	1061	*/
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	/* Peripheral State functions *************************************************/
bogdanm	0:9b334a45a8ff	1065	/** @addtogroup ADC_Exported_Functions_Group4
bogdanm	0:9b334a45a8ff	1066	* @{
bogdanm	0:9b334a45a8ff	1067	*/
bogdanm	0:9b334a45a8ff	1068	HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1069	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
bogdanm	0:9b334a45a8ff	1070	/**
bogdanm	0:9b334a45a8ff	1071	* @}
bogdanm	0:9b334a45a8ff	1072	*/
bogdanm	0:9b334a45a8ff	1073
bogdanm	0:9b334a45a8ff	1074
bogdanm	0:9b334a45a8ff	1075	/**
bogdanm	0:9b334a45a8ff	1076	* @}
bogdanm	0:9b334a45a8ff	1077	*/
bogdanm	0:9b334a45a8ff	1078
bogdanm	0:9b334a45a8ff	1079
bogdanm	0:9b334a45a8ff	1080	/* Internal HAL driver functions **********************************************/
bogdanm	0:9b334a45a8ff	1081	/** @addtogroup ADC_Private_Functions
bogdanm	0:9b334a45a8ff	1082	* @{
bogdanm	0:9b334a45a8ff	1083	*/
bogdanm	0:9b334a45a8ff	1084
bogdanm	0:9b334a45a8ff	1085	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1086	HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	1087	/**
bogdanm	0:9b334a45a8ff	1088	* @}
bogdanm	0:9b334a45a8ff	1089	*/
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091
bogdanm	0:9b334a45a8ff	1092	/**
bogdanm	0:9b334a45a8ff	1093	* @}
bogdanm	0:9b334a45a8ff	1094	*/
bogdanm	0:9b334a45a8ff	1095
bogdanm	0:9b334a45a8ff	1096	/**
bogdanm	0:9b334a45a8ff	1097	* @}
bogdanm	0:9b334a45a8ff	1098	*/
bogdanm	0:9b334a45a8ff	1099
bogdanm	0:9b334a45a8ff	1100	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1101	}
bogdanm	0:9b334a45a8ff	1102	#endif
bogdanm	0:9b334a45a8ff	1103
bogdanm	0:9b334a45a8ff	1104
bogdanm	0:9b334a45a8ff	1105	#endif /* __STM32L1xx_HAL_ADC_H */
bogdanm	0:9b334a45a8ff	1106
bogdanm	0:9b334a45a8ff	1107	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
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targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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