en 129
fix LPC812 PWM
Fork of
mbed-dev
by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32l1xx_hal.h |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.0.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 5-September-2014 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief This file contains all the functions prototypes for the HAL |
| bogdanm | 0:9b334a45a8ff | 8 | * module driver. |
| bogdanm | 0:9b334a45a8ff | 9 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 10 | * @attention |
| bogdanm | 0:9b334a45a8ff | 11 | * |
| bogdanm | 0:9b334a45a8ff | 12 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 13 | * |
| bogdanm | 0:9b334a45a8ff | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 15 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 17 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 19 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 20 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 22 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 23 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 24 | * |
| bogdanm | 0:9b334a45a8ff | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 35 | * |
| bogdanm | 0:9b334a45a8ff | 36 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 37 | */ |
| bogdanm | 0:9b334a45a8ff | 38 | |
| bogdanm | 0:9b334a45a8ff | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 40 | #ifndef __STM32L1xx_HAL_H |
| bogdanm | 0:9b334a45a8ff | 41 | #define __STM32L1xx_HAL_H |
| bogdanm | 0:9b334a45a8ff | 42 | |
| bogdanm | 0:9b334a45a8ff | 43 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 44 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 45 | #endif |
| bogdanm | 0:9b334a45a8ff | 46 | |
| bogdanm | 0:9b334a45a8ff | 47 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 48 | #include "stm32l1xx_hal_conf.h" |
| bogdanm | 0:9b334a45a8ff | 49 | |
| bogdanm | 0:9b334a45a8ff | 50 | /** @addtogroup STM32L1xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 51 | * @{ |
| bogdanm | 0:9b334a45a8ff | 52 | */ |
| bogdanm | 0:9b334a45a8ff | 53 | |
| bogdanm | 0:9b334a45a8ff | 54 | /** @addtogroup HAL |
| bogdanm | 0:9b334a45a8ff | 55 | * @{ |
| bogdanm | 0:9b334a45a8ff | 56 | */ |
| bogdanm | 0:9b334a45a8ff | 57 | |
| bogdanm | 0:9b334a45a8ff | 58 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 59 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 60 | /** @defgroup HAL_Exported_Constants HAL Exported Constants |
| bogdanm | 0:9b334a45a8ff | 61 | * @{ |
| bogdanm | 0:9b334a45a8ff | 62 | */ |
| bogdanm | 0:9b334a45a8ff | 63 | |
| bogdanm | 0:9b334a45a8ff | 64 | /** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG |
| bogdanm | 0:9b334a45a8ff | 65 | * @{ |
| bogdanm | 0:9b334a45a8ff | 66 | */ |
| bogdanm | 0:9b334a45a8ff | 67 | |
| bogdanm | 0:9b334a45a8ff | 68 | /** @defgroup SYSCFG_BootMode Boot Mode |
| bogdanm | 0:9b334a45a8ff | 69 | * @{ |
| bogdanm | 0:9b334a45a8ff | 70 | */ |
| bogdanm | 0:9b334a45a8ff | 71 | |
| bogdanm | 0:9b334a45a8ff | 72 | #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 73 | #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0) |
| bogdanm | 0:9b334a45a8ff | 74 | #if defined(FSMC_R_BASE) |
| bogdanm | 0:9b334a45a8ff | 75 | #define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1) |
| bogdanm | 0:9b334a45a8ff | 76 | #endif /* FSMC_R_BASE */ |
| bogdanm | 0:9b334a45a8ff | 77 | #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE) |
| bogdanm | 0:9b334a45a8ff | 78 | |
| bogdanm | 0:9b334a45a8ff | 79 | /** |
| bogdanm | 0:9b334a45a8ff | 80 | * @} |
| bogdanm | 0:9b334a45a8ff | 81 | */ |
| bogdanm | 0:9b334a45a8ff | 82 | |
| bogdanm | 0:9b334a45a8ff | 83 | /** |
| bogdanm | 0:9b334a45a8ff | 84 | * @} |
| bogdanm | 0:9b334a45a8ff | 85 | */ |
| bogdanm | 0:9b334a45a8ff | 86 | |
| bogdanm | 0:9b334a45a8ff | 87 | /** @defgroup RI_Constants RI: Routing Interface |
| bogdanm | 0:9b334a45a8ff | 88 | * @{ |
| bogdanm | 0:9b334a45a8ff | 89 | */ |
| bogdanm | 0:9b334a45a8ff | 90 | |
| bogdanm | 0:9b334a45a8ff | 91 | /** @defgroup RI_InputCapture Input Capture |
| bogdanm | 0:9b334a45a8ff | 92 | * @{ |
| bogdanm | 0:9b334a45a8ff | 93 | */ |
| bogdanm | 0:9b334a45a8ff | 94 | |
| bogdanm | 0:9b334a45a8ff | 95 | #define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */ |
| bogdanm | 0:9b334a45a8ff | 96 | #define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */ |
| bogdanm | 0:9b334a45a8ff | 97 | #define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */ |
| bogdanm | 0:9b334a45a8ff | 98 | #define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */ |
| bogdanm | 0:9b334a45a8ff | 99 | |
| bogdanm | 0:9b334a45a8ff | 100 | /** |
| bogdanm | 0:9b334a45a8ff | 101 | * @} |
| bogdanm | 0:9b334a45a8ff | 102 | */ |
| bogdanm | 0:9b334a45a8ff | 103 | |
| bogdanm | 0:9b334a45a8ff | 104 | /** @defgroup TIM_Select TIM Select |
| bogdanm | 0:9b334a45a8ff | 105 | * @{ |
| bogdanm | 0:9b334a45a8ff | 106 | */ |
| bogdanm | 0:9b334a45a8ff | 107 | |
| bogdanm | 0:9b334a45a8ff | 108 | #define TIM_SELECT_NONE ((uint32_t)0x00000000) /*!< None selected */ |
| bogdanm | 0:9b334a45a8ff | 109 | #define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */ |
| bogdanm | 0:9b334a45a8ff | 110 | #define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */ |
| bogdanm | 0:9b334a45a8ff | 111 | #define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */ |
| bogdanm | 0:9b334a45a8ff | 112 | |
| bogdanm | 0:9b334a45a8ff | 113 | #define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \ |
| bogdanm | 0:9b334a45a8ff | 114 | ((__TIM__) == TIM_SELECT_TIM2) || \ |
| bogdanm | 0:9b334a45a8ff | 115 | ((__TIM__) == TIM_SELECT_TIM3) || \ |
| bogdanm | 0:9b334a45a8ff | 116 | ((__TIM__) == TIM_SELECT_TIM4)) |
| bogdanm | 0:9b334a45a8ff | 117 | |
| bogdanm | 0:9b334a45a8ff | 118 | /** |
| bogdanm | 0:9b334a45a8ff | 119 | * @} |
| bogdanm | 0:9b334a45a8ff | 120 | */ |
| bogdanm | 0:9b334a45a8ff | 121 | |
| bogdanm | 0:9b334a45a8ff | 122 | /** @defgroup RI_InputCaptureRouting Input Capture Routing |
| bogdanm | 0:9b334a45a8ff | 123 | * @{ |
| bogdanm | 0:9b334a45a8ff | 124 | */ |
| bogdanm | 0:9b334a45a8ff | 125 | /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ |
| bogdanm | 0:9b334a45a8ff | 126 | #define RI_INPUTCAPTUREROUTING_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */ |
| bogdanm | 0:9b334a45a8ff | 127 | #define RI_INPUTCAPTUREROUTING_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */ |
| bogdanm | 0:9b334a45a8ff | 128 | #define RI_INPUTCAPTUREROUTING_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */ |
| bogdanm | 0:9b334a45a8ff | 129 | #define RI_INPUTCAPTUREROUTING_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */ |
| bogdanm | 0:9b334a45a8ff | 130 | #define RI_INPUTCAPTUREROUTING_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */ |
| bogdanm | 0:9b334a45a8ff | 131 | #define RI_INPUTCAPTUREROUTING_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */ |
| bogdanm | 0:9b334a45a8ff | 132 | #define RI_INPUTCAPTUREROUTING_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */ |
| bogdanm | 0:9b334a45a8ff | 133 | #define RI_INPUTCAPTUREROUTING_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */ |
| bogdanm | 0:9b334a45a8ff | 134 | #define RI_INPUTCAPTUREROUTING_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */ |
| bogdanm | 0:9b334a45a8ff | 135 | #define RI_INPUTCAPTUREROUTING_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */ |
| bogdanm | 0:9b334a45a8ff | 136 | #define RI_INPUTCAPTUREROUTING_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */ |
| bogdanm | 0:9b334a45a8ff | 137 | #define RI_INPUTCAPTUREROUTING_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */ |
| bogdanm | 0:9b334a45a8ff | 138 | #define RI_INPUTCAPTUREROUTING_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */ |
| bogdanm | 0:9b334a45a8ff | 139 | #define RI_INPUTCAPTUREROUTING_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */ |
| bogdanm | 0:9b334a45a8ff | 140 | #define RI_INPUTCAPTUREROUTING_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */ |
| bogdanm | 0:9b334a45a8ff | 141 | #define RI_INPUTCAPTUREROUTING_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */ |
| bogdanm | 0:9b334a45a8ff | 142 | |
| bogdanm | 0:9b334a45a8ff | 143 | #define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \ |
| bogdanm | 0:9b334a45a8ff | 144 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \ |
| bogdanm | 0:9b334a45a8ff | 145 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \ |
| bogdanm | 0:9b334a45a8ff | 146 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \ |
| bogdanm | 0:9b334a45a8ff | 147 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \ |
| bogdanm | 0:9b334a45a8ff | 148 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \ |
| bogdanm | 0:9b334a45a8ff | 149 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \ |
| bogdanm | 0:9b334a45a8ff | 150 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \ |
| bogdanm | 0:9b334a45a8ff | 151 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \ |
| bogdanm | 0:9b334a45a8ff | 152 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \ |
| bogdanm | 0:9b334a45a8ff | 153 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \ |
| bogdanm | 0:9b334a45a8ff | 154 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \ |
| bogdanm | 0:9b334a45a8ff | 155 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \ |
| bogdanm | 0:9b334a45a8ff | 156 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \ |
| bogdanm | 0:9b334a45a8ff | 157 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \ |
| bogdanm | 0:9b334a45a8ff | 158 | ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15)) |
| bogdanm | 0:9b334a45a8ff | 159 | |
| bogdanm | 0:9b334a45a8ff | 160 | /** |
| bogdanm | 0:9b334a45a8ff | 161 | * @} |
| bogdanm | 0:9b334a45a8ff | 162 | */ |
| bogdanm | 0:9b334a45a8ff | 163 | |
| bogdanm | 0:9b334a45a8ff | 164 | /** @defgroup RI_IOSwitch IO Switch |
| bogdanm | 0:9b334a45a8ff | 165 | * @{ |
| bogdanm | 0:9b334a45a8ff | 166 | */ |
| bogdanm | 0:9b334a45a8ff | 167 | #define RI_ASCR1_REGISTER ((uint32_t)0x80000000) |
| bogdanm | 0:9b334a45a8ff | 168 | /* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */ |
| bogdanm | 0:9b334a45a8ff | 169 | #define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0) |
| bogdanm | 0:9b334a45a8ff | 170 | #define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1) |
| bogdanm | 0:9b334a45a8ff | 171 | #define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2) |
| bogdanm | 0:9b334a45a8ff | 172 | #define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3) |
| bogdanm | 0:9b334a45a8ff | 173 | #define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4) |
| bogdanm | 0:9b334a45a8ff | 174 | #define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5) |
| bogdanm | 0:9b334a45a8ff | 175 | #define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6) |
| bogdanm | 0:9b334a45a8ff | 176 | #define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7) |
| bogdanm | 0:9b334a45a8ff | 177 | #define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8) |
| bogdanm | 0:9b334a45a8ff | 178 | #define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9) |
| bogdanm | 0:9b334a45a8ff | 179 | #define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10) |
| bogdanm | 0:9b334a45a8ff | 180 | #define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11) |
| bogdanm | 0:9b334a45a8ff | 181 | #define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12) |
| bogdanm | 0:9b334a45a8ff | 182 | #define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13) |
| bogdanm | 0:9b334a45a8ff | 183 | #define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14) |
| bogdanm | 0:9b334a45a8ff | 184 | #define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15) |
| bogdanm | 0:9b334a45a8ff | 185 | #define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18) |
| bogdanm | 0:9b334a45a8ff | 186 | #define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19) |
| bogdanm | 0:9b334a45a8ff | 187 | #define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20) |
| bogdanm | 0:9b334a45a8ff | 188 | #define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21) |
| bogdanm | 0:9b334a45a8ff | 189 | #define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22) |
| bogdanm | 0:9b334a45a8ff | 190 | #define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23) |
| bogdanm | 0:9b334a45a8ff | 191 | #define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24) |
| bogdanm | 0:9b334a45a8ff | 192 | #define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25) |
| bogdanm | 0:9b334a45a8ff | 193 | #define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */ |
| bogdanm | 0:9b334a45a8ff | 194 | #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ |
| bogdanm | 0:9b334a45a8ff | 195 | #define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27) |
| bogdanm | 0:9b334a45a8ff | 196 | #define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28) |
| bogdanm | 0:9b334a45a8ff | 197 | #define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29) |
| bogdanm | 0:9b334a45a8ff | 198 | #define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30) |
| bogdanm | 0:9b334a45a8ff | 199 | #define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31) |
| bogdanm | 0:9b334a45a8ff | 200 | #endif /* RI_ASCR2_CH1b */ |
| bogdanm | 0:9b334a45a8ff | 201 | |
| bogdanm | 0:9b334a45a8ff | 202 | /* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ |
| bogdanm | 0:9b334a45a8ff | 203 | #define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1) |
| bogdanm | 0:9b334a45a8ff | 204 | #define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2) |
| bogdanm | 0:9b334a45a8ff | 205 | #define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3) |
| bogdanm | 0:9b334a45a8ff | 206 | #define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4) |
| bogdanm | 0:9b334a45a8ff | 207 | #define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1) |
| bogdanm | 0:9b334a45a8ff | 208 | #define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2) |
| bogdanm | 0:9b334a45a8ff | 209 | #define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1) |
| bogdanm | 0:9b334a45a8ff | 210 | #define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2) |
| bogdanm | 0:9b334a45a8ff | 211 | #define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3) |
| bogdanm | 0:9b334a45a8ff | 212 | #define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1) |
| bogdanm | 0:9b334a45a8ff | 213 | #define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2) |
| bogdanm | 0:9b334a45a8ff | 214 | #define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3) |
| bogdanm | 0:9b334a45a8ff | 215 | #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */ |
| bogdanm | 0:9b334a45a8ff | 216 | #define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b) |
| bogdanm | 0:9b334a45a8ff | 217 | #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ |
| bogdanm | 0:9b334a45a8ff | 218 | #define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b) |
| bogdanm | 0:9b334a45a8ff | 219 | #define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b) |
| bogdanm | 0:9b334a45a8ff | 220 | #define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b) |
| bogdanm | 0:9b334a45a8ff | 221 | #define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b) |
| bogdanm | 0:9b334a45a8ff | 222 | #define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b) |
| bogdanm | 0:9b334a45a8ff | 223 | #define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b) |
| bogdanm | 0:9b334a45a8ff | 224 | #define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b) |
| bogdanm | 0:9b334a45a8ff | 225 | #define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b) |
| bogdanm | 0:9b334a45a8ff | 226 | #define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b) |
| bogdanm | 0:9b334a45a8ff | 227 | #define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b) |
| bogdanm | 0:9b334a45a8ff | 228 | #endif /* RI_ASCR2_CH1b */ |
| bogdanm | 0:9b334a45a8ff | 229 | #define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3) |
| bogdanm | 0:9b334a45a8ff | 230 | #define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4) |
| bogdanm | 0:9b334a45a8ff | 231 | #endif /* RI_ASCR2_CH0b */ |
| bogdanm | 0:9b334a45a8ff | 232 | |
| bogdanm | 0:9b334a45a8ff | 233 | |
| bogdanm | 0:9b334a45a8ff | 234 | #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ |
| bogdanm | 0:9b334a45a8ff | 235 | |
| bogdanm | 0:9b334a45a8ff | 236 | #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ |
| bogdanm | 0:9b334a45a8ff | 237 | ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ |
| bogdanm | 0:9b334a45a8ff | 238 | ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ |
| bogdanm | 0:9b334a45a8ff | 239 | ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ |
| bogdanm | 0:9b334a45a8ff | 240 | ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ |
| bogdanm | 0:9b334a45a8ff | 241 | ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ |
| bogdanm | 0:9b334a45a8ff | 242 | ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ |
| bogdanm | 0:9b334a45a8ff | 243 | ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ |
| bogdanm | 0:9b334a45a8ff | 244 | ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ |
| bogdanm | 0:9b334a45a8ff | 245 | ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ |
| bogdanm | 0:9b334a45a8ff | 246 | ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ |
| bogdanm | 0:9b334a45a8ff | 247 | ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ |
| bogdanm | 0:9b334a45a8ff | 248 | ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \ |
| bogdanm | 0:9b334a45a8ff | 249 | ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \ |
| bogdanm | 0:9b334a45a8ff | 250 | ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \ |
| bogdanm | 0:9b334a45a8ff | 251 | ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \ |
| bogdanm | 0:9b334a45a8ff | 252 | ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \ |
| bogdanm | 0:9b334a45a8ff | 253 | ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \ |
| bogdanm | 0:9b334a45a8ff | 254 | ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \ |
| bogdanm | 0:9b334a45a8ff | 255 | ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \ |
| bogdanm | 0:9b334a45a8ff | 256 | ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \ |
| bogdanm | 0:9b334a45a8ff | 257 | ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \ |
| bogdanm | 0:9b334a45a8ff | 258 | ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \ |
| bogdanm | 0:9b334a45a8ff | 259 | ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \ |
| bogdanm | 0:9b334a45a8ff | 260 | ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \ |
| bogdanm | 0:9b334a45a8ff | 261 | ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \ |
| bogdanm | 0:9b334a45a8ff | 262 | ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \ |
| bogdanm | 0:9b334a45a8ff | 263 | ((__IOSWITCH__) == RI_IOSWITCH_CH12b)) |
| bogdanm | 0:9b334a45a8ff | 264 | |
| bogdanm | 0:9b334a45a8ff | 265 | #else /* !RI_ASCR2_CH1b */ |
| bogdanm | 0:9b334a45a8ff | 266 | |
| bogdanm | 0:9b334a45a8ff | 267 | #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */ |
| bogdanm | 0:9b334a45a8ff | 268 | |
| bogdanm | 0:9b334a45a8ff | 269 | #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ |
| bogdanm | 0:9b334a45a8ff | 270 | ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ |
| bogdanm | 0:9b334a45a8ff | 271 | ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ |
| bogdanm | 0:9b334a45a8ff | 272 | ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ |
| bogdanm | 0:9b334a45a8ff | 273 | ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ |
| bogdanm | 0:9b334a45a8ff | 274 | ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ |
| bogdanm | 0:9b334a45a8ff | 275 | ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ |
| bogdanm | 0:9b334a45a8ff | 276 | ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ |
| bogdanm | 0:9b334a45a8ff | 277 | ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ |
| bogdanm | 0:9b334a45a8ff | 278 | ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ |
| bogdanm | 0:9b334a45a8ff | 279 | ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ |
| bogdanm | 0:9b334a45a8ff | 280 | ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ |
| bogdanm | 0:9b334a45a8ff | 281 | ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ |
| bogdanm | 0:9b334a45a8ff | 282 | ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ |
| bogdanm | 0:9b334a45a8ff | 283 | ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ |
| bogdanm | 0:9b334a45a8ff | 284 | ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ |
| bogdanm | 0:9b334a45a8ff | 285 | ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ |
| bogdanm | 0:9b334a45a8ff | 286 | ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ |
| bogdanm | 0:9b334a45a8ff | 287 | ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b)) |
| bogdanm | 0:9b334a45a8ff | 288 | |
| bogdanm | 0:9b334a45a8ff | 289 | #else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */ |
| bogdanm | 0:9b334a45a8ff | 290 | |
| bogdanm | 0:9b334a45a8ff | 291 | #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ |
| bogdanm | 0:9b334a45a8ff | 292 | ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ |
| bogdanm | 0:9b334a45a8ff | 293 | ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ |
| bogdanm | 0:9b334a45a8ff | 294 | ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ |
| bogdanm | 0:9b334a45a8ff | 295 | ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ |
| bogdanm | 0:9b334a45a8ff | 296 | ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ |
| bogdanm | 0:9b334a45a8ff | 297 | ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ |
| bogdanm | 0:9b334a45a8ff | 298 | ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ |
| bogdanm | 0:9b334a45a8ff | 299 | ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ |
| bogdanm | 0:9b334a45a8ff | 300 | ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ |
| bogdanm | 0:9b334a45a8ff | 301 | ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ |
| bogdanm | 0:9b334a45a8ff | 302 | ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ |
| bogdanm | 0:9b334a45a8ff | 303 | ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ |
| bogdanm | 0:9b334a45a8ff | 304 | ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ |
| bogdanm | 0:9b334a45a8ff | 305 | ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ |
| bogdanm | 0:9b334a45a8ff | 306 | ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ |
| bogdanm | 0:9b334a45a8ff | 307 | ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ |
| bogdanm | 0:9b334a45a8ff | 308 | ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ |
| bogdanm | 0:9b334a45a8ff | 309 | ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)) |
| bogdanm | 0:9b334a45a8ff | 310 | |
| bogdanm | 0:9b334a45a8ff | 311 | #endif /* RI_ASCR2_CH0b */ |
| bogdanm | 0:9b334a45a8ff | 312 | #endif /* RI_ASCR2_CH1b */ |
| bogdanm | 0:9b334a45a8ff | 313 | |
| bogdanm | 0:9b334a45a8ff | 314 | /** |
| bogdanm | 0:9b334a45a8ff | 315 | * @} |
| bogdanm | 0:9b334a45a8ff | 316 | */ |
| bogdanm | 0:9b334a45a8ff | 317 | |
| bogdanm | 0:9b334a45a8ff | 318 | /** @defgroup RI_Pin PIN define |
| bogdanm | 0:9b334a45a8ff | 319 | * @{ |
| bogdanm | 0:9b334a45a8ff | 320 | */ |
| bogdanm | 0:9b334a45a8ff | 321 | #define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ |
| bogdanm | 0:9b334a45a8ff | 322 | #define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ |
| bogdanm | 0:9b334a45a8ff | 323 | #define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ |
| bogdanm | 0:9b334a45a8ff | 324 | #define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ |
| bogdanm | 0:9b334a45a8ff | 325 | #define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ |
| bogdanm | 0:9b334a45a8ff | 326 | #define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ |
| bogdanm | 0:9b334a45a8ff | 327 | #define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ |
| bogdanm | 0:9b334a45a8ff | 328 | #define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ |
| bogdanm | 0:9b334a45a8ff | 329 | #define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ |
| bogdanm | 0:9b334a45a8ff | 330 | #define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ |
| bogdanm | 0:9b334a45a8ff | 331 | #define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ |
| bogdanm | 0:9b334a45a8ff | 332 | #define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ |
| bogdanm | 0:9b334a45a8ff | 333 | #define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ |
| bogdanm | 0:9b334a45a8ff | 334 | #define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ |
| bogdanm | 0:9b334a45a8ff | 335 | #define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ |
| bogdanm | 0:9b334a45a8ff | 336 | #define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ |
| bogdanm | 0:9b334a45a8ff | 337 | #define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */ |
| bogdanm | 0:9b334a45a8ff | 338 | |
| bogdanm | 0:9b334a45a8ff | 339 | #define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00) |
| bogdanm | 0:9b334a45a8ff | 340 | |
| bogdanm | 0:9b334a45a8ff | 341 | /** |
| bogdanm | 0:9b334a45a8ff | 342 | * @} |
| bogdanm | 0:9b334a45a8ff | 343 | */ |
| bogdanm | 0:9b334a45a8ff | 344 | |
| bogdanm | 0:9b334a45a8ff | 345 | /** |
| bogdanm | 0:9b334a45a8ff | 346 | * @} |
| bogdanm | 0:9b334a45a8ff | 347 | */ |
| bogdanm | 0:9b334a45a8ff | 348 | |
| bogdanm | 0:9b334a45a8ff | 349 | /** |
| bogdanm | 0:9b334a45a8ff | 350 | * @} |
| bogdanm | 0:9b334a45a8ff | 351 | */ |
| bogdanm | 0:9b334a45a8ff | 352 | |
| bogdanm | 0:9b334a45a8ff | 353 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 354 | |
| bogdanm | 0:9b334a45a8ff | 355 | /** @defgroup HAL_Exported_Macros HAL Exported Macros |
| bogdanm | 0:9b334a45a8ff | 356 | * @{ |
| bogdanm | 0:9b334a45a8ff | 357 | */ |
| bogdanm | 0:9b334a45a8ff | 358 | |
| bogdanm | 0:9b334a45a8ff | 359 | /** @defgroup DBGMCU_Macros DBGMCU: Debug MCU |
| bogdanm | 0:9b334a45a8ff | 360 | * @{ |
| bogdanm | 0:9b334a45a8ff | 361 | */ |
| bogdanm | 0:9b334a45a8ff | 362 | |
| bogdanm | 0:9b334a45a8ff | 363 | /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode |
| bogdanm | 0:9b334a45a8ff | 364 | * @brief Freeze/Unfreeze Peripherals in Debug mode |
| bogdanm | 0:9b334a45a8ff | 365 | * @{ |
| bogdanm | 0:9b334a45a8ff | 366 | */ |
| bogdanm | 0:9b334a45a8ff | 367 | |
| bogdanm | 0:9b334a45a8ff | 368 | /** |
| bogdanm | 0:9b334a45a8ff | 369 | * @brief TIM2 Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 370 | */ |
| bogdanm | 0:9b334a45a8ff | 371 | #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
| bogdanm | 0:9b334a45a8ff | 372 | #define __HAL_FREEZE_TIM2_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
| bogdanm | 0:9b334a45a8ff | 373 | #define __HAL_UNFREEZE_TIM2_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
| bogdanm | 0:9b334a45a8ff | 374 | #endif |
| bogdanm | 0:9b334a45a8ff | 375 | |
| bogdanm | 0:9b334a45a8ff | 376 | /** |
| bogdanm | 0:9b334a45a8ff | 377 | * @brief TIM3 Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 378 | */ |
| bogdanm | 0:9b334a45a8ff | 379 | #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
| bogdanm | 0:9b334a45a8ff | 380 | #define __HAL_FREEZE_TIM3_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
| bogdanm | 0:9b334a45a8ff | 381 | #define __HAL_UNFREEZE_TIM3_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
| bogdanm | 0:9b334a45a8ff | 382 | #endif |
| bogdanm | 0:9b334a45a8ff | 383 | |
| bogdanm | 0:9b334a45a8ff | 384 | /** |
| bogdanm | 0:9b334a45a8ff | 385 | * @brief TIM4 Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 386 | */ |
| bogdanm | 0:9b334a45a8ff | 387 | #if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP) |
| bogdanm | 0:9b334a45a8ff | 388 | #define __HAL_FREEZE_TIM4_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) |
| bogdanm | 0:9b334a45a8ff | 389 | #define __HAL_UNFREEZE_TIM4_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) |
| bogdanm | 0:9b334a45a8ff | 390 | #endif |
| bogdanm | 0:9b334a45a8ff | 391 | |
| bogdanm | 0:9b334a45a8ff | 392 | /** |
| bogdanm | 0:9b334a45a8ff | 393 | * @brief TIM5 Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 394 | */ |
| bogdanm | 0:9b334a45a8ff | 395 | #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP) |
| bogdanm | 0:9b334a45a8ff | 396 | #define __HAL_FREEZE_TIM5_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) |
| bogdanm | 0:9b334a45a8ff | 397 | #define __HAL_UNFREEZE_TIM5_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) |
| bogdanm | 0:9b334a45a8ff | 398 | #endif |
| bogdanm | 0:9b334a45a8ff | 399 | |
| bogdanm | 0:9b334a45a8ff | 400 | /** |
| bogdanm | 0:9b334a45a8ff | 401 | * @brief TIM6 Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 402 | */ |
| bogdanm | 0:9b334a45a8ff | 403 | #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
| bogdanm | 0:9b334a45a8ff | 404 | #define __HAL_FREEZE_TIM6_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
| bogdanm | 0:9b334a45a8ff | 405 | #define __HAL_UNFREEZE_TIM6_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
| bogdanm | 0:9b334a45a8ff | 406 | #endif |
| bogdanm | 0:9b334a45a8ff | 407 | |
| bogdanm | 0:9b334a45a8ff | 408 | /** |
| bogdanm | 0:9b334a45a8ff | 409 | * @brief TIM7 Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 410 | */ |
| bogdanm | 0:9b334a45a8ff | 411 | #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
| bogdanm | 0:9b334a45a8ff | 412 | #define __HAL_FREEZE_TIM7_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
| bogdanm | 0:9b334a45a8ff | 413 | #define __HAL_UNFREEZE_TIM7_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
| bogdanm | 0:9b334a45a8ff | 414 | #endif |
| bogdanm | 0:9b334a45a8ff | 415 | |
| bogdanm | 0:9b334a45a8ff | 416 | /** |
| bogdanm | 0:9b334a45a8ff | 417 | * @brief RTC Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 418 | */ |
| bogdanm | 0:9b334a45a8ff | 419 | #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) |
| bogdanm | 0:9b334a45a8ff | 420 | #define __HAL_FREEZE_RTC_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) |
| bogdanm | 0:9b334a45a8ff | 421 | #define __HAL_UNFREEZE_RTC_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) |
| bogdanm | 0:9b334a45a8ff | 422 | #endif |
| bogdanm | 0:9b334a45a8ff | 423 | |
| bogdanm | 0:9b334a45a8ff | 424 | /** |
| bogdanm | 0:9b334a45a8ff | 425 | * @brief WWDG Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 426 | */ |
| bogdanm | 0:9b334a45a8ff | 427 | #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
| bogdanm | 0:9b334a45a8ff | 428 | #define __HAL_FREEZE_WWDG_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
| bogdanm | 0:9b334a45a8ff | 429 | #define __HAL_UNFREEZE_WWDG_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
| bogdanm | 0:9b334a45a8ff | 430 | #endif |
| bogdanm | 0:9b334a45a8ff | 431 | |
| bogdanm | 0:9b334a45a8ff | 432 | /** |
| bogdanm | 0:9b334a45a8ff | 433 | * @brief IWDG Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 434 | */ |
| bogdanm | 0:9b334a45a8ff | 435 | #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
| bogdanm | 0:9b334a45a8ff | 436 | #define __HAL_FREEZE_IWDG_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
| bogdanm | 0:9b334a45a8ff | 437 | #define __HAL_UNFREEZE_IWDG_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
| bogdanm | 0:9b334a45a8ff | 438 | #endif |
| bogdanm | 0:9b334a45a8ff | 439 | |
| bogdanm | 0:9b334a45a8ff | 440 | /** |
| bogdanm | 0:9b334a45a8ff | 441 | * @brief I2C1 Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 442 | */ |
| bogdanm | 0:9b334a45a8ff | 443 | #if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) |
| bogdanm | 0:9b334a45a8ff | 444 | #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) |
| bogdanm | 0:9b334a45a8ff | 445 | #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) |
| bogdanm | 0:9b334a45a8ff | 446 | #endif |
| bogdanm | 0:9b334a45a8ff | 447 | |
| bogdanm | 0:9b334a45a8ff | 448 | /** |
| bogdanm | 0:9b334a45a8ff | 449 | * @brief I2C2 Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 450 | */ |
| bogdanm | 0:9b334a45a8ff | 451 | #if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) |
| bogdanm | 0:9b334a45a8ff | 452 | #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) |
| bogdanm | 0:9b334a45a8ff | 453 | #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) |
| bogdanm | 0:9b334a45a8ff | 454 | #endif |
| bogdanm | 0:9b334a45a8ff | 455 | |
| bogdanm | 0:9b334a45a8ff | 456 | /** |
| bogdanm | 0:9b334a45a8ff | 457 | * @brief TIM9 Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 458 | */ |
| bogdanm | 0:9b334a45a8ff | 459 | #if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP) |
| bogdanm | 0:9b334a45a8ff | 460 | #define __HAL_FREEZE_TIM9_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) |
| bogdanm | 0:9b334a45a8ff | 461 | #define __HAL_UNFREEZE_TIM9_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) |
| bogdanm | 0:9b334a45a8ff | 462 | #endif |
| bogdanm | 0:9b334a45a8ff | 463 | |
| bogdanm | 0:9b334a45a8ff | 464 | /** |
| bogdanm | 0:9b334a45a8ff | 465 | * @brief TIM10 Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 466 | */ |
| bogdanm | 0:9b334a45a8ff | 467 | #if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP) |
| bogdanm | 0:9b334a45a8ff | 468 | #define __HAL_FREEZE_TIM10_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) |
| bogdanm | 0:9b334a45a8ff | 469 | #define __HAL_UNFREEZE_TIM10_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) |
| bogdanm | 0:9b334a45a8ff | 470 | #endif |
| bogdanm | 0:9b334a45a8ff | 471 | |
| bogdanm | 0:9b334a45a8ff | 472 | /** |
| bogdanm | 0:9b334a45a8ff | 473 | * @brief TIM11 Peripherals Debug mode |
| bogdanm | 0:9b334a45a8ff | 474 | */ |
| bogdanm | 0:9b334a45a8ff | 475 | #if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP) |
| bogdanm | 0:9b334a45a8ff | 476 | #define __HAL_FREEZE_TIM11_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) |
| bogdanm | 0:9b334a45a8ff | 477 | #define __HAL_UNFREEZE_TIM11_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) |
| bogdanm | 0:9b334a45a8ff | 478 | #endif |
| bogdanm | 0:9b334a45a8ff | 479 | |
| bogdanm | 0:9b334a45a8ff | 480 | /** |
| bogdanm | 0:9b334a45a8ff | 481 | * @brief Enables or disables the output of internal reference voltage |
| bogdanm | 0:9b334a45a8ff | 482 | * (VREFINT) on I/O pin. |
| bogdanm | 0:9b334a45a8ff | 483 | * The VREFINT output can be routed to any I/O in group 3: |
| bogdanm | 0:9b334a45a8ff | 484 | * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1). |
| bogdanm | 0:9b334a45a8ff | 485 | * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2). |
| bogdanm | 0:9b334a45a8ff | 486 | * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2), |
| bogdanm | 0:9b334a45a8ff | 487 | * CH1b (PF11) or CH2b (PF12). |
| bogdanm | 0:9b334a45a8ff | 488 | * Note: Comparator peripheral clock must be preliminarility enabled, |
| bogdanm | 0:9b334a45a8ff | 489 | * either in COMP user function "HAL_COMP_MspInit()" (should be |
| bogdanm | 0:9b334a45a8ff | 490 | * done if comparators are used) or by direct clock enable: |
| bogdanm | 0:9b334a45a8ff | 491 | * Refer to macro "__COMP_CLK_ENABLE()". |
| bogdanm | 0:9b334a45a8ff | 492 | * Note: In addition with this macro, Vrefint output buffer must be |
| bogdanm | 0:9b334a45a8ff | 493 | * connected to the selected I/O pin. Refer to macro |
| bogdanm | 0:9b334a45a8ff | 494 | * "__HAL_RI_IOSWITCH_CLOSE()". |
| bogdanm | 0:9b334a45a8ff | 495 | * @note ENABLE: Internal reference voltage connected to I/O group 3 |
| bogdanm | 0:9b334a45a8ff | 496 | * @note DISABLE: Internal reference voltage disconnected from I/O group 3 |
| bogdanm | 0:9b334a45a8ff | 497 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 498 | */ |
| bogdanm | 0:9b334a45a8ff | 499 | #define __HAL_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) |
| bogdanm | 0:9b334a45a8ff | 500 | #define __HAL_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) |
| bogdanm | 0:9b334a45a8ff | 501 | |
| bogdanm | 0:9b334a45a8ff | 502 | /** |
| bogdanm | 0:9b334a45a8ff | 503 | * @} |
| bogdanm | 0:9b334a45a8ff | 504 | */ |
| bogdanm | 0:9b334a45a8ff | 505 | |
| bogdanm | 0:9b334a45a8ff | 506 | /** |
| bogdanm | 0:9b334a45a8ff | 507 | * @} |
| bogdanm | 0:9b334a45a8ff | 508 | */ |
| bogdanm | 0:9b334a45a8ff | 509 | |
| bogdanm | 0:9b334a45a8ff | 510 | /** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG |
| bogdanm | 0:9b334a45a8ff | 511 | * @{ |
| bogdanm | 0:9b334a45a8ff | 512 | */ |
| bogdanm | 0:9b334a45a8ff | 513 | |
| bogdanm | 0:9b334a45a8ff | 514 | /** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration |
| bogdanm | 0:9b334a45a8ff | 515 | * @{ |
| bogdanm | 0:9b334a45a8ff | 516 | */ |
| bogdanm | 0:9b334a45a8ff | 517 | |
| bogdanm | 0:9b334a45a8ff | 518 | /** |
| bogdanm | 0:9b334a45a8ff | 519 | * @brief Main Flash memory mapped at 0x00000000 |
| bogdanm | 0:9b334a45a8ff | 520 | */ |
| bogdanm | 0:9b334a45a8ff | 521 | #define __HAL_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) |
| bogdanm | 0:9b334a45a8ff | 522 | |
| bogdanm | 0:9b334a45a8ff | 523 | /** @brief System Flash memory mapped at 0x00000000 |
| bogdanm | 0:9b334a45a8ff | 524 | */ |
| bogdanm | 0:9b334a45a8ff | 525 | #define __HAL_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) |
| bogdanm | 0:9b334a45a8ff | 526 | |
| bogdanm | 0:9b334a45a8ff | 527 | /** @brief Embedded SRAM mapped at 0x00000000 |
| bogdanm | 0:9b334a45a8ff | 528 | */ |
| bogdanm | 0:9b334a45a8ff | 529 | #define __HAL_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1) |
| bogdanm | 0:9b334a45a8ff | 530 | |
| bogdanm | 0:9b334a45a8ff | 531 | #if defined(FSMC_R_BASE) |
| bogdanm | 0:9b334a45a8ff | 532 | /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 |
| bogdanm | 0:9b334a45a8ff | 533 | */ |
| bogdanm | 0:9b334a45a8ff | 534 | #define __HAL_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) |
| bogdanm | 0:9b334a45a8ff | 535 | |
| bogdanm | 0:9b334a45a8ff | 536 | #endif /* FSMC_R_BASE */ |
| bogdanm | 0:9b334a45a8ff | 537 | |
| bogdanm | 0:9b334a45a8ff | 538 | /** |
| bogdanm | 0:9b334a45a8ff | 539 | * @brief Returns the boot mode as configured by user. |
| bogdanm | 0:9b334a45a8ff | 540 | * @retval The boot mode as configured by user. The returned value can be one |
| bogdanm | 0:9b334a45a8ff | 541 | * of the following values: |
| bogdanm | 0:9b334a45a8ff | 542 | * @arg SYSCFG_BOOT_MAINFLASH |
| bogdanm | 0:9b334a45a8ff | 543 | * @arg SYSCFG_BOOT_SYSTEMFLASH |
| bogdanm | 0:9b334a45a8ff | 544 | * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD) |
| bogdanm | 0:9b334a45a8ff | 545 | * @arg SYSCFG_BOOT_SRAM |
| bogdanm | 0:9b334a45a8ff | 546 | */ |
| bogdanm | 0:9b334a45a8ff | 547 | #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE) |
| bogdanm | 0:9b334a45a8ff | 548 | |
| bogdanm | 0:9b334a45a8ff | 549 | /** |
| bogdanm | 0:9b334a45a8ff | 550 | * @} |
| bogdanm | 0:9b334a45a8ff | 551 | */ |
| bogdanm | 0:9b334a45a8ff | 552 | |
| bogdanm | 0:9b334a45a8ff | 553 | /** @defgroup SYSCFG_USBConfig USB DP line Configuration |
| bogdanm | 0:9b334a45a8ff | 554 | * @{ |
| bogdanm | 0:9b334a45a8ff | 555 | */ |
| bogdanm | 0:9b334a45a8ff | 556 | |
| bogdanm | 0:9b334a45a8ff | 557 | /** |
| bogdanm | 0:9b334a45a8ff | 558 | * @brief Control the internal pull-up on USB DP line. |
| bogdanm | 0:9b334a45a8ff | 559 | */ |
| bogdanm | 0:9b334a45a8ff | 560 | #define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) |
| bogdanm | 0:9b334a45a8ff | 561 | |
| bogdanm | 0:9b334a45a8ff | 562 | #define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) |
| bogdanm | 0:9b334a45a8ff | 563 | |
| bogdanm | 0:9b334a45a8ff | 564 | /** |
| bogdanm | 0:9b334a45a8ff | 565 | * @} |
| bogdanm | 0:9b334a45a8ff | 566 | */ |
| bogdanm | 0:9b334a45a8ff | 567 | |
| bogdanm | 0:9b334a45a8ff | 568 | /** |
| bogdanm | 0:9b334a45a8ff | 569 | * @} |
| bogdanm | 0:9b334a45a8ff | 570 | */ |
| bogdanm | 0:9b334a45a8ff | 571 | |
| bogdanm | 0:9b334a45a8ff | 572 | /** @defgroup RI_Macris RI: Routing Interface |
| bogdanm | 0:9b334a45a8ff | 573 | * @{ |
| bogdanm | 0:9b334a45a8ff | 574 | */ |
| bogdanm | 0:9b334a45a8ff | 575 | |
| bogdanm | 0:9b334a45a8ff | 576 | /** @defgroup RI_InputCaputureConfig Input Capture configuration |
| bogdanm | 0:9b334a45a8ff | 577 | * @{ |
| bogdanm | 0:9b334a45a8ff | 578 | */ |
| bogdanm | 0:9b334a45a8ff | 579 | |
| bogdanm | 0:9b334a45a8ff | 580 | /** |
| bogdanm | 0:9b334a45a8ff | 581 | * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin. |
| bogdanm | 0:9b334a45a8ff | 582 | * @param __TIMSELECT__: Timer select. |
| bogdanm | 0:9b334a45a8ff | 583 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 584 | * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. |
| bogdanm | 0:9b334a45a8ff | 585 | * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. |
| bogdanm | 0:9b334a45a8ff | 586 | * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. |
| bogdanm | 0:9b334a45a8ff | 587 | * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. |
| bogdanm | 0:9b334a45a8ff | 588 | * @param __INPUT__: selects which pin to be routed to Input Capture. |
| bogdanm | 0:9b334a45a8ff | 589 | * This parameter must be a value of @ref RI_InputCaptureRouting |
| bogdanm | 0:9b334a45a8ff | 590 | * e.g. |
| bogdanm | 0:9b334a45a8ff | 591 | * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1) |
| bogdanm | 0:9b334a45a8ff | 592 | * allows routing of Input capture IC1 of TIM2 to PA4. |
| bogdanm | 0:9b334a45a8ff | 593 | * For details about correspondence between RI_INPUTCAPTUREROUTING_x |
| bogdanm | 0:9b334a45a8ff | 594 | * and I/O pins refer to the parameters' description in the header file |
| bogdanm | 0:9b334a45a8ff | 595 | * or refer to the product reference manual. |
| bogdanm | 0:9b334a45a8ff | 596 | * @note Input capture selection bits are not reset by this function. |
| bogdanm | 0:9b334a45a8ff | 597 | * To reset input capture selection bits, use SYSCFG_RIDeInit() function. |
| bogdanm | 0:9b334a45a8ff | 598 | * @note The I/O should be configured in alternate function mode (AF14) using |
| bogdanm | 0:9b334a45a8ff | 599 | * GPIO_PinAFConfig() function. |
| bogdanm | 0:9b334a45a8ff | 600 | * @retval None. |
| bogdanm | 0:9b334a45a8ff | 601 | */ |
| bogdanm | 0:9b334a45a8ff | 602 | #define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \ |
| bogdanm | 0:9b334a45a8ff | 603 | do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ |
| bogdanm | 0:9b334a45a8ff | 604 | assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ |
| bogdanm | 0:9b334a45a8ff | 605 | MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ |
| bogdanm | 0:9b334a45a8ff | 606 | SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \ |
| bogdanm | 0:9b334a45a8ff | 607 | MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \ |
| bogdanm | 0:9b334a45a8ff | 608 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 609 | |
| bogdanm | 0:9b334a45a8ff | 610 | /** |
| bogdanm | 0:9b334a45a8ff | 611 | * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin. |
| bogdanm | 0:9b334a45a8ff | 612 | * @param __TIMSELECT__: Timer select. |
| bogdanm | 0:9b334a45a8ff | 613 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 614 | * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. |
| bogdanm | 0:9b334a45a8ff | 615 | * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. |
| bogdanm | 0:9b334a45a8ff | 616 | * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. |
| bogdanm | 0:9b334a45a8ff | 617 | * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. |
| bogdanm | 0:9b334a45a8ff | 618 | * @param __INPUT__: selects which pin to be routed to Input Capture. |
| bogdanm | 0:9b334a45a8ff | 619 | * This parameter must be a value of @ref RI_InputCaptureRouting |
| bogdanm | 0:9b334a45a8ff | 620 | * @retval None. |
| bogdanm | 0:9b334a45a8ff | 621 | */ |
| bogdanm | 0:9b334a45a8ff | 622 | #define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \ |
| bogdanm | 0:9b334a45a8ff | 623 | do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ |
| bogdanm | 0:9b334a45a8ff | 624 | assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ |
| bogdanm | 0:9b334a45a8ff | 625 | MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ |
| bogdanm | 0:9b334a45a8ff | 626 | SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \ |
| bogdanm | 0:9b334a45a8ff | 627 | MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \ |
| bogdanm | 0:9b334a45a8ff | 628 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 629 | |
| bogdanm | 0:9b334a45a8ff | 630 | /** |
| bogdanm | 0:9b334a45a8ff | 631 | * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin. |
| bogdanm | 0:9b334a45a8ff | 632 | * @param __TIMSELECT__: Timer select. |
| bogdanm | 0:9b334a45a8ff | 633 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 634 | * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. |
| bogdanm | 0:9b334a45a8ff | 635 | * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. |
| bogdanm | 0:9b334a45a8ff | 636 | * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. |
| bogdanm | 0:9b334a45a8ff | 637 | * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. |
| bogdanm | 0:9b334a45a8ff | 638 | * @param __INPUT__: selects which pin to be routed to Input Capture. |
| bogdanm | 0:9b334a45a8ff | 639 | * This parameter must be a value of @ref RI_InputCaptureRouting |
| bogdanm | 0:9b334a45a8ff | 640 | * @retval None. |
| bogdanm | 0:9b334a45a8ff | 641 | */ |
| bogdanm | 0:9b334a45a8ff | 642 | #define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \ |
| bogdanm | 0:9b334a45a8ff | 643 | do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ |
| bogdanm | 0:9b334a45a8ff | 644 | assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ |
| bogdanm | 0:9b334a45a8ff | 645 | MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ |
| bogdanm | 0:9b334a45a8ff | 646 | SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \ |
| bogdanm | 0:9b334a45a8ff | 647 | MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \ |
| bogdanm | 0:9b334a45a8ff | 648 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 649 | |
| bogdanm | 0:9b334a45a8ff | 650 | /** |
| bogdanm | 0:9b334a45a8ff | 651 | * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin. |
| bogdanm | 0:9b334a45a8ff | 652 | * @param __TIMSELECT__: Timer select. |
| bogdanm | 0:9b334a45a8ff | 653 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 654 | * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. |
| bogdanm | 0:9b334a45a8ff | 655 | * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. |
| bogdanm | 0:9b334a45a8ff | 656 | * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. |
| bogdanm | 0:9b334a45a8ff | 657 | * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. |
| bogdanm | 0:9b334a45a8ff | 658 | * @param __INPUT__: selects which pin to be routed to Input Capture. |
| bogdanm | 0:9b334a45a8ff | 659 | * This parameter must be a value of @ref RI_InputCaptureRouting |
| bogdanm | 0:9b334a45a8ff | 660 | * @retval None. |
| bogdanm | 0:9b334a45a8ff | 661 | */ |
| bogdanm | 0:9b334a45a8ff | 662 | #define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \ |
| bogdanm | 0:9b334a45a8ff | 663 | do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ |
| bogdanm | 0:9b334a45a8ff | 664 | assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ |
| bogdanm | 0:9b334a45a8ff | 665 | MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ |
| bogdanm | 0:9b334a45a8ff | 666 | SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \ |
| bogdanm | 0:9b334a45a8ff | 667 | MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \ |
| bogdanm | 0:9b334a45a8ff | 668 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 669 | |
| bogdanm | 0:9b334a45a8ff | 670 | /** |
| bogdanm | 0:9b334a45a8ff | 671 | * @} |
| bogdanm | 0:9b334a45a8ff | 672 | */ |
| bogdanm | 0:9b334a45a8ff | 673 | |
| bogdanm | 0:9b334a45a8ff | 674 | /** @defgroup RI_SwitchControlConfig Switch Control configuration |
| bogdanm | 0:9b334a45a8ff | 675 | * @{ |
| bogdanm | 0:9b334a45a8ff | 676 | */ |
| bogdanm | 0:9b334a45a8ff | 677 | |
| bogdanm | 0:9b334a45a8ff | 678 | /** |
| bogdanm | 0:9b334a45a8ff | 679 | * @brief Enable or disable the switch control mode. |
| bogdanm | 0:9b334a45a8ff | 680 | * @note ENABLE: ADC analog switches closed if the corresponding |
| bogdanm | 0:9b334a45a8ff | 681 | * I/O switch is also closed. |
| bogdanm | 0:9b334a45a8ff | 682 | * When using COMP1, switch control mode must be enabled. |
| bogdanm | 0:9b334a45a8ff | 683 | * @note DISABLE: ADC analog switches open or controlled by the ADC interface. |
| bogdanm | 0:9b334a45a8ff | 684 | * When using the ADC for acquisition, switch control mode |
| bogdanm | 0:9b334a45a8ff | 685 | * must be disabled. |
| bogdanm | 0:9b334a45a8ff | 686 | * @note COMP1 comparator and ADC cannot be used at the same time since |
| bogdanm | 0:9b334a45a8ff | 687 | * they share the ADC switch matrix. |
| bogdanm | 0:9b334a45a8ff | 688 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 689 | */ |
| bogdanm | 0:9b334a45a8ff | 690 | #define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM) |
| bogdanm | 0:9b334a45a8ff | 691 | |
| bogdanm | 0:9b334a45a8ff | 692 | #define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM) |
| bogdanm | 0:9b334a45a8ff | 693 | |
| bogdanm | 0:9b334a45a8ff | 694 | /* |
| bogdanm | 0:9b334a45a8ff | 695 | * @brief Close or Open the routing interface Input Output switches. |
| bogdanm | 0:9b334a45a8ff | 696 | * @param __IOSWITCH__: selects the I/O analog switch number. |
| bogdanm | 0:9b334a45a8ff | 697 | * This parameter must be a value of @ref RI_IOSwitch |
| bogdanm | 0:9b334a45a8ff | 698 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 699 | */ |
| bogdanm | 0:9b334a45a8ff | 700 | #define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ |
| bogdanm | 0:9b334a45a8ff | 701 | if ((__IOSWITCH__) >> 31 != 0 ) \ |
| bogdanm | 0:9b334a45a8ff | 702 | { \ |
| bogdanm | 0:9b334a45a8ff | 703 | SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ |
| bogdanm | 0:9b334a45a8ff | 704 | } \ |
| bogdanm | 0:9b334a45a8ff | 705 | else \ |
| bogdanm | 0:9b334a45a8ff | 706 | { \ |
| bogdanm | 0:9b334a45a8ff | 707 | SET_BIT(RI->ASCR2, (__IOSWITCH__)); \ |
| bogdanm | 0:9b334a45a8ff | 708 | } \ |
| bogdanm | 0:9b334a45a8ff | 709 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 710 | |
| bogdanm | 0:9b334a45a8ff | 711 | #define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ |
| bogdanm | 0:9b334a45a8ff | 712 | if ((__IOSWITCH__) >> 31 != 0 ) \ |
| bogdanm | 0:9b334a45a8ff | 713 | { \ |
| bogdanm | 0:9b334a45a8ff | 714 | CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ |
| bogdanm | 0:9b334a45a8ff | 715 | } \ |
| bogdanm | 0:9b334a45a8ff | 716 | else \ |
| bogdanm | 0:9b334a45a8ff | 717 | { \ |
| bogdanm | 0:9b334a45a8ff | 718 | CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \ |
| bogdanm | 0:9b334a45a8ff | 719 | } \ |
| bogdanm | 0:9b334a45a8ff | 720 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 721 | |
| bogdanm | 0:9b334a45a8ff | 722 | #if defined (COMP_CSR_SW1) |
| bogdanm | 0:9b334a45a8ff | 723 | /** |
| bogdanm | 0:9b334a45a8ff | 724 | * @brief Close or open the internal switch COMP1_SW1. |
| bogdanm | 0:9b334a45a8ff | 725 | * This switch connects I/O pin PC3 (can be used as ADC channel 13) |
| bogdanm | 0:9b334a45a8ff | 726 | * and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel |
| bogdanm | 0:9b334a45a8ff | 727 | * 26) and COMP1 non-inverting input. |
| bogdanm | 0:9b334a45a8ff | 728 | * Pin PC3 connection depends on another switch setting, refer to |
| bogdanm | 0:9b334a45a8ff | 729 | * macro "__HAL_ADC_CHANNEL_SPEED_FAST()". |
| bogdanm | 0:9b334a45a8ff | 730 | * @retval None. |
| bogdanm | 0:9b334a45a8ff | 731 | */ |
| bogdanm | 0:9b334a45a8ff | 732 | #define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1) |
| bogdanm | 0:9b334a45a8ff | 733 | |
| bogdanm | 0:9b334a45a8ff | 734 | #define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1) |
| bogdanm | 0:9b334a45a8ff | 735 | #endif /* COMP_CSR_SW1 */ |
| bogdanm | 0:9b334a45a8ff | 736 | |
| bogdanm | 0:9b334a45a8ff | 737 | /** |
| bogdanm | 0:9b334a45a8ff | 738 | * @} |
| bogdanm | 0:9b334a45a8ff | 739 | */ |
| bogdanm | 0:9b334a45a8ff | 740 | |
| bogdanm | 0:9b334a45a8ff | 741 | /** @defgroup RI_HystConfig Hysteresis Activation and Deactivation |
| bogdanm | 0:9b334a45a8ff | 742 | * @{ |
| bogdanm | 0:9b334a45a8ff | 743 | */ |
| bogdanm | 0:9b334a45a8ff | 744 | |
| bogdanm | 0:9b334a45a8ff | 745 | /** |
| bogdanm | 0:9b334a45a8ff | 746 | * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A |
| bogdanm | 0:9b334a45a8ff | 747 | * When the I/Os are programmed in input mode by standard I/O port |
| bogdanm | 0:9b334a45a8ff | 748 | * registers, the Schmitt trigger and the hysteresis are enabled by default. |
| bogdanm | 0:9b334a45a8ff | 749 | * When hysteresis is disabled, it is possible to read the |
| bogdanm | 0:9b334a45a8ff | 750 | * corresponding port with a trigger level of VDDIO/2. |
| bogdanm | 0:9b334a45a8ff | 751 | * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. |
| bogdanm | 0:9b334a45a8ff | 752 | * This parameter must be a value of @ref RI_Pin |
| bogdanm | 0:9b334a45a8ff | 753 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 754 | */ |
| bogdanm | 0:9b334a45a8ff | 755 | #define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 756 | CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 757 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 758 | |
| bogdanm | 0:9b334a45a8ff | 759 | #define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 760 | SET_BIT(RI->HYSCR1, (__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 761 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 762 | |
| bogdanm | 0:9b334a45a8ff | 763 | /** |
| bogdanm | 0:9b334a45a8ff | 764 | * @brief Enable or disable Hysteresis of the input schmitt triger of Ports B |
| bogdanm | 0:9b334a45a8ff | 765 | * When the I/Os are programmed in input mode by standard I/O port |
| bogdanm | 0:9b334a45a8ff | 766 | * registers, the Schmitt trigger and the hysteresis are enabled by default. |
| bogdanm | 0:9b334a45a8ff | 767 | * When hysteresis is disabled, it is possible to read the |
| bogdanm | 0:9b334a45a8ff | 768 | * corresponding port with a trigger level of VDDIO/2. |
| bogdanm | 0:9b334a45a8ff | 769 | * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. |
| bogdanm | 0:9b334a45a8ff | 770 | * This parameter must be a value of @ref RI_Pin |
| bogdanm | 0:9b334a45a8ff | 771 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 772 | */ |
| bogdanm | 0:9b334a45a8ff | 773 | #define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 774 | CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ |
| bogdanm | 0:9b334a45a8ff | 775 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 776 | |
| bogdanm | 0:9b334a45a8ff | 777 | #define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 778 | SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ |
| bogdanm | 0:9b334a45a8ff | 779 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 780 | |
| bogdanm | 0:9b334a45a8ff | 781 | /** |
| bogdanm | 0:9b334a45a8ff | 782 | * @brief Enable or disable Hysteresis of the input schmitt triger of Ports C |
| bogdanm | 0:9b334a45a8ff | 783 | * When the I/Os are programmed in input mode by standard I/O port |
| bogdanm | 0:9b334a45a8ff | 784 | * registers, the Schmitt trigger and the hysteresis are enabled by default. |
| bogdanm | 0:9b334a45a8ff | 785 | * When hysteresis is disabled, it is possible to read the |
| bogdanm | 0:9b334a45a8ff | 786 | * corresponding port with a trigger level of VDDIO/2. |
| bogdanm | 0:9b334a45a8ff | 787 | * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. |
| bogdanm | 0:9b334a45a8ff | 788 | * This parameter must be a value of @ref RI_Pin |
| bogdanm | 0:9b334a45a8ff | 789 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 790 | */ |
| bogdanm | 0:9b334a45a8ff | 791 | #define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 792 | CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 793 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 794 | |
| bogdanm | 0:9b334a45a8ff | 795 | #define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 796 | SET_BIT(RI->HYSCR2, (__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 797 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 798 | |
| bogdanm | 0:9b334a45a8ff | 799 | /** |
| bogdanm | 0:9b334a45a8ff | 800 | * @brief Enable or disable Hysteresis of the input schmitt triger of Ports D |
| bogdanm | 0:9b334a45a8ff | 801 | * When the I/Os are programmed in input mode by standard I/O port |
| bogdanm | 0:9b334a45a8ff | 802 | * registers, the Schmitt trigger and the hysteresis are enabled by default. |
| bogdanm | 0:9b334a45a8ff | 803 | * When hysteresis is disabled, it is possible to read the |
| bogdanm | 0:9b334a45a8ff | 804 | * corresponding port with a trigger level of VDDIO/2. |
| bogdanm | 0:9b334a45a8ff | 805 | * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. |
| bogdanm | 0:9b334a45a8ff | 806 | * This parameter must be a value of @ref RI_Pin |
| bogdanm | 0:9b334a45a8ff | 807 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 808 | */ |
| bogdanm | 0:9b334a45a8ff | 809 | #define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 810 | CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ |
| bogdanm | 0:9b334a45a8ff | 811 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 812 | |
| bogdanm | 0:9b334a45a8ff | 813 | #define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 814 | SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ |
| bogdanm | 0:9b334a45a8ff | 815 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 816 | |
| bogdanm | 0:9b334a45a8ff | 817 | #if defined (GPIOE_BASE) |
| bogdanm | 0:9b334a45a8ff | 818 | |
| bogdanm | 0:9b334a45a8ff | 819 | /** |
| bogdanm | 0:9b334a45a8ff | 820 | * @brief Enable or disable Hysteresis of the input schmitt triger of Ports E |
| bogdanm | 0:9b334a45a8ff | 821 | * When the I/Os are programmed in input mode by standard I/O port |
| bogdanm | 0:9b334a45a8ff | 822 | * registers, the Schmitt trigger and the hysteresis are enabled by default. |
| bogdanm | 0:9b334a45a8ff | 823 | * When hysteresis is disabled, it is possible to read the |
| bogdanm | 0:9b334a45a8ff | 824 | * corresponding port with a trigger level of VDDIO/2. |
| bogdanm | 0:9b334a45a8ff | 825 | * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. |
| bogdanm | 0:9b334a45a8ff | 826 | * This parameter must be a value of @ref RI_Pin |
| bogdanm | 0:9b334a45a8ff | 827 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 828 | */ |
| bogdanm | 0:9b334a45a8ff | 829 | #define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 830 | CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 831 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 832 | |
| bogdanm | 0:9b334a45a8ff | 833 | #define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 834 | SET_BIT(RI->HYSCR3, (__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 835 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 836 | |
| bogdanm | 0:9b334a45a8ff | 837 | #endif /* GPIOE_BASE */ |
| bogdanm | 0:9b334a45a8ff | 838 | |
| bogdanm | 0:9b334a45a8ff | 839 | #if defined(GPIOF_BASE) || defined(GPIOG_BASE) |
| bogdanm | 0:9b334a45a8ff | 840 | |
| bogdanm | 0:9b334a45a8ff | 841 | /** |
| bogdanm | 0:9b334a45a8ff | 842 | * @brief Enable or disable Hysteresis of the input schmitt triger of Ports F |
| bogdanm | 0:9b334a45a8ff | 843 | * When the I/Os are programmed in input mode by standard I/O port |
| bogdanm | 0:9b334a45a8ff | 844 | * registers, the Schmitt trigger and the hysteresis are enabled by default. |
| bogdanm | 0:9b334a45a8ff | 845 | * When hysteresis is disabled, it is possible to read the |
| bogdanm | 0:9b334a45a8ff | 846 | * corresponding port with a trigger level of VDDIO/2. |
| bogdanm | 0:9b334a45a8ff | 847 | * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. |
| bogdanm | 0:9b334a45a8ff | 848 | * This parameter must be a value of @ref RI_Pin |
| bogdanm | 0:9b334a45a8ff | 849 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 850 | */ |
| bogdanm | 0:9b334a45a8ff | 851 | #define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 852 | CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ |
| bogdanm | 0:9b334a45a8ff | 853 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 854 | |
| bogdanm | 0:9b334a45a8ff | 855 | #define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 856 | SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ |
| bogdanm | 0:9b334a45a8ff | 857 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 858 | |
| bogdanm | 0:9b334a45a8ff | 859 | /** |
| bogdanm | 0:9b334a45a8ff | 860 | * @brief Enable or disable Hysteresis of the input schmitt triger of Ports G |
| bogdanm | 0:9b334a45a8ff | 861 | * When the I/Os are programmed in input mode by standard I/O port |
| bogdanm | 0:9b334a45a8ff | 862 | * registers, the Schmitt trigger and the hysteresis are enabled by default. |
| bogdanm | 0:9b334a45a8ff | 863 | * When hysteresis is disabled, it is possible to read the |
| bogdanm | 0:9b334a45a8ff | 864 | * corresponding port with a trigger level of VDDIO/2. |
| bogdanm | 0:9b334a45a8ff | 865 | * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. |
| bogdanm | 0:9b334a45a8ff | 866 | * This parameter must be a value of @ref RI_Pin |
| bogdanm | 0:9b334a45a8ff | 867 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 868 | */ |
| bogdanm | 0:9b334a45a8ff | 869 | #define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 870 | CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 871 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 872 | |
| bogdanm | 0:9b334a45a8ff | 873 | #define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 874 | SET_BIT(RI->HYSCR4, (__IOPIN__)); \ |
| bogdanm | 0:9b334a45a8ff | 875 | } while(0) |
| bogdanm | 0:9b334a45a8ff | 876 | |
| bogdanm | 0:9b334a45a8ff | 877 | #endif /* GPIOF_BASE || GPIOG_BASE */ |
| bogdanm | 0:9b334a45a8ff | 878 | |
| bogdanm | 0:9b334a45a8ff | 879 | /** |
| bogdanm | 0:9b334a45a8ff | 880 | * @} |
| bogdanm | 0:9b334a45a8ff | 881 | */ |
| bogdanm | 0:9b334a45a8ff | 882 | |
| bogdanm | 0:9b334a45a8ff | 883 | /** |
| bogdanm | 0:9b334a45a8ff | 884 | * @} |
| bogdanm | 0:9b334a45a8ff | 885 | */ |
| bogdanm | 0:9b334a45a8ff | 886 | |
| bogdanm | 0:9b334a45a8ff | 887 | /** |
| bogdanm | 0:9b334a45a8ff | 888 | * @} |
| bogdanm | 0:9b334a45a8ff | 889 | */ |
| bogdanm | 0:9b334a45a8ff | 890 | |
| bogdanm | 0:9b334a45a8ff | 891 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 892 | |
| bogdanm | 0:9b334a45a8ff | 893 | /** @addtogroup HAL_Exported_Functions |
| bogdanm | 0:9b334a45a8ff | 894 | * @{ |
| bogdanm | 0:9b334a45a8ff | 895 | */ |
| bogdanm | 0:9b334a45a8ff | 896 | |
| bogdanm | 0:9b334a45a8ff | 897 | /** @addtogroup HAL_Exported_Functions_Group1 |
| bogdanm | 0:9b334a45a8ff | 898 | * @{ |
| bogdanm | 0:9b334a45a8ff | 899 | */ |
| bogdanm | 0:9b334a45a8ff | 900 | |
| bogdanm | 0:9b334a45a8ff | 901 | /* Initialization and de-initialization functions ******************************/ |
| bogdanm | 0:9b334a45a8ff | 902 | HAL_StatusTypeDef HAL_Init(void); |
| bogdanm | 0:9b334a45a8ff | 903 | HAL_StatusTypeDef HAL_DeInit(void); |
| bogdanm | 0:9b334a45a8ff | 904 | void HAL_MspInit(void); |
| bogdanm | 0:9b334a45a8ff | 905 | void HAL_MspDeInit(void); |
| bogdanm | 0:9b334a45a8ff | 906 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
| bogdanm | 0:9b334a45a8ff | 907 | |
| bogdanm | 0:9b334a45a8ff | 908 | /** |
| bogdanm | 0:9b334a45a8ff | 909 | * @} |
| bogdanm | 0:9b334a45a8ff | 910 | */ |
| bogdanm | 0:9b334a45a8ff | 911 | |
| bogdanm | 0:9b334a45a8ff | 912 | /** @addtogroup HAL_Exported_Functions_Group2 |
| bogdanm | 0:9b334a45a8ff | 913 | * @{ |
| bogdanm | 0:9b334a45a8ff | 914 | */ |
| bogdanm | 0:9b334a45a8ff | 915 | |
| bogdanm | 0:9b334a45a8ff | 916 | /* Peripheral Control functions ************************************************/ |
| bogdanm | 0:9b334a45a8ff | 917 | void HAL_IncTick(void); |
| bogdanm | 0:9b334a45a8ff | 918 | void HAL_Delay(__IO uint32_t Delay); |
| bogdanm | 0:9b334a45a8ff | 919 | uint32_t HAL_GetTick(void); |
| bogdanm | 0:9b334a45a8ff | 920 | void HAL_SuspendTick(void); |
| bogdanm | 0:9b334a45a8ff | 921 | void HAL_ResumeTick(void); |
| bogdanm | 0:9b334a45a8ff | 922 | uint32_t HAL_GetHalVersion(void); |
| bogdanm | 0:9b334a45a8ff | 923 | uint32_t HAL_GetREVID(void); |
| bogdanm | 0:9b334a45a8ff | 924 | uint32_t HAL_GetDEVID(void); |
| bogdanm | 0:9b334a45a8ff | 925 | void HAL_EnableDBGSleepMode(void); |
| bogdanm | 0:9b334a45a8ff | 926 | void HAL_DisableDBGSleepMode(void); |
| bogdanm | 0:9b334a45a8ff | 927 | void HAL_EnableDBGStopMode(void); |
| bogdanm | 0:9b334a45a8ff | 928 | void HAL_DisableDBGStopMode(void); |
| bogdanm | 0:9b334a45a8ff | 929 | void HAL_EnableDBGStandbyMode(void); |
| bogdanm | 0:9b334a45a8ff | 930 | void HAL_DisableDBGStandbyMode(void); |
| bogdanm | 0:9b334a45a8ff | 931 | |
| bogdanm | 0:9b334a45a8ff | 932 | /** |
| bogdanm | 0:9b334a45a8ff | 933 | * @} |
| bogdanm | 0:9b334a45a8ff | 934 | */ |
| bogdanm | 0:9b334a45a8ff | 935 | |
| bogdanm | 0:9b334a45a8ff | 936 | /** |
| bogdanm | 0:9b334a45a8ff | 937 | * @} |
| bogdanm | 0:9b334a45a8ff | 938 | */ |
| bogdanm | 0:9b334a45a8ff | 939 | |
| bogdanm | 0:9b334a45a8ff | 940 | |
| bogdanm | 0:9b334a45a8ff | 941 | /** |
| bogdanm | 0:9b334a45a8ff | 942 | * @} |
| bogdanm | 0:9b334a45a8ff | 943 | */ |
| bogdanm | 0:9b334a45a8ff | 944 | |
| bogdanm | 0:9b334a45a8ff | 945 | /** |
| bogdanm | 0:9b334a45a8ff | 946 | * @} |
| bogdanm | 0:9b334a45a8ff | 947 | */ |
| bogdanm | 0:9b334a45a8ff | 948 | |
| bogdanm | 0:9b334a45a8ff | 949 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 950 | } |
| bogdanm | 0:9b334a45a8ff | 951 | #endif |
| bogdanm | 0:9b334a45a8ff | 952 | |
| bogdanm | 0:9b334a45a8ff | 953 | #endif /* __STM32L1xx_HAL_H */ |
| bogdanm | 0:9b334a45a8ff | 954 | |
| bogdanm | 0:9b334a45a8ff | 955 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |