mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 113:b3775bf36a83

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l0xx_hal_rcc.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.2.0
bogdanm	0:9b334a45a8ff	6	* @date 06-February-2015
bogdanm	0:9b334a45a8ff	7	* @brief RCC HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Reset and Clock Control (RCC) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	@verbatim
bogdanm	0:9b334a45a8ff	14	==============================================================================
bogdanm	0:9b334a45a8ff	15	##### RCC specific features #####
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	[..] After reset the device is running from MSI (2 MHz) with Flash 0 WS,
bogdanm	0:9b334a45a8ff	18	all peripherals are off except internal SRAM, Flash and SW-DP.
bogdanm	0:9b334a45a8ff	19	(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
bogdanm	0:9b334a45a8ff	20	all peripherals mapped on these busses are running at MSI speed.
bogdanm	0:9b334a45a8ff	21	(+) The clock for all peripherals is switched off, except the SRAM and
bogdanm	0:9b334a45a8ff	22	FLASH.
bogdanm	0:9b334a45a8ff	23	(+) All GPIOs are in input floating state, except the SW-DP pins which
bogdanm	0:9b334a45a8ff	24	are assigned to be used for debug purpose.
bogdanm	0:9b334a45a8ff	25	[..] Once the device started from reset, the user application has to:
bogdanm	0:9b334a45a8ff	26	(+) Configure the clock source to be used to drive the System clock
bogdanm	0:9b334a45a8ff	27	(if the application needs higher frequency/performance)
bogdanm	0:9b334a45a8ff	28	(+) Configure the System clock frequency and Flash settings
bogdanm	0:9b334a45a8ff	29	(+) Configure the AHB and APB busses prescalers
bogdanm	0:9b334a45a8ff	30	(+) Enable the clock for the peripheral(s) to be used
bogdanm	0:9b334a45a8ff	31	(+) Configure the clock source(s) for peripherals whose clocks are not
bogdanm	0:9b334a45a8ff	32	derived from the System clock (ADC, RTC/LCD, RNG and IWDG)
bogdanm	0:9b334a45a8ff	33
bogdanm	0:9b334a45a8ff	34	##### RCC Limitations #####
bogdanm	0:9b334a45a8ff	35	==============================================================================
bogdanm	0:9b334a45a8ff	36	[..]
bogdanm	0:9b334a45a8ff	37	A delay between an RCC peripheral clock enable and the effective peripheral
bogdanm	0:9b334a45a8ff	38	enabling should be taken into account in order to manage the peripheral read/write
bogdanm	0:9b334a45a8ff	39	from/to registeres.
bogdanm	0:9b334a45a8ff	40	(+) This delay depends on the peripheral mapping.
bogdanm	0:9b334a45a8ff	41	(+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
bogdanm	0:9b334a45a8ff	42	after the clock enable bit is set on the hardware register
bogdanm	0:9b334a45a8ff	43	(+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
bogdanm	0:9b334a45a8ff	44	after the clock enable bit is set on the hardware register
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	[..]
bogdanm	0:9b334a45a8ff	47	Possible Workarounds:
bogdanm	0:9b334a45a8ff	48	(#) Enable the peripheral clock sometimes before the peripheral read/write
bogdanm	0:9b334a45a8ff	49	register is required.
bogdanm	0:9b334a45a8ff	50	(#) For AHB peripheral, insert two dummy read to the peripheral register.
bogdanm	0:9b334a45a8ff	51	(#) For APB peripheral, insert a dummy read to the peripheral register.
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	@endverbatim
bogdanm	0:9b334a45a8ff	54	******************************************************************************
bogdanm	0:9b334a45a8ff	55	* @attention
bogdanm	0:9b334a45a8ff	56	*
bogdanm	0:9b334a45a8ff	57	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	58	*
bogdanm	0:9b334a45a8ff	59	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	60	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	61	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	62	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	63	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	64	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	65	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	66	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	67	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	68	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	69	*
bogdanm	0:9b334a45a8ff	70	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	71	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	72	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	73	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	74	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	75	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	76	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	77	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	78	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	79	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	80	*
bogdanm	0:9b334a45a8ff	81	******************************************************************************
bogdanm	0:9b334a45a8ff	82	*/
bogdanm	0:9b334a45a8ff	83
bogdanm	0:9b334a45a8ff	84	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	85	#include "stm32l0xx_hal.h"
bogdanm	0:9b334a45a8ff	86
bogdanm	0:9b334a45a8ff	87	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	88	* @{
bogdanm	0:9b334a45a8ff	89	*/
bogdanm	0:9b334a45a8ff	90
bogdanm	0:9b334a45a8ff	91	/** @addtogroup RCC
bogdanm	0:9b334a45a8ff	92	* @brief RCC HAL module driver
bogdanm	0:9b334a45a8ff	93	* @{
bogdanm	0:9b334a45a8ff	94	*/
bogdanm	0:9b334a45a8ff	95
bogdanm	0:9b334a45a8ff	96	#ifdef HAL_RCC_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	/** @defgroup RCC_Private_Constants RCC Private constants
bogdanm	0:9b334a45a8ff	99	* @{
bogdanm	0:9b334a45a8ff	100	*/
bogdanm	0:9b334a45a8ff	101	#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
bogdanm	0:9b334a45a8ff	102	#define RCC_HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	103	#define RCC_LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	104	#define RCC_PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	105	#define RCC_HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	106	#define RCC_MSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	107	#define RCC_CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
bogdanm	0:9b334a45a8ff	108
bogdanm	0:9b334a45a8ff	109	#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
bogdanm	0:9b334a45a8ff	110	#define MCO1_GPIO_PORT GPIOA
bogdanm	0:9b334a45a8ff	111	#define MCO1_PIN GPIO_PIN_8
bogdanm	0:9b334a45a8ff	112	#define MCO2_PIN GPIO_PIN_9
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	/**
bogdanm	0:9b334a45a8ff	115	* @}
bogdanm	0:9b334a45a8ff	116	*/
bogdanm	0:9b334a45a8ff	117
bogdanm	0:9b334a45a8ff	118	/** @defgroup RCC_Private_Vatiables RCC Private Data
bogdanm	0:9b334a45a8ff	119	* @{
bogdanm	0:9b334a45a8ff	120	*/
bogdanm	0:9b334a45a8ff	121	static const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
bogdanm	0:9b334a45a8ff	122	static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm	0:9b334a45a8ff	123
bogdanm	0:9b334a45a8ff	124	/**
bogdanm	0:9b334a45a8ff	125	* @}
bogdanm	0:9b334a45a8ff	126	*/
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	/** @addtogroup RCC_Exported_Functions
bogdanm	0:9b334a45a8ff	129	* @{
bogdanm	0:9b334a45a8ff	130	*/
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132	/** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	133	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	134	*
bogdanm	0:9b334a45a8ff	135	@verbatim
bogdanm	0:9b334a45a8ff	136	===============================================================================
bogdanm	0:9b334a45a8ff	137	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	138	===============================================================================
bogdanm	0:9b334a45a8ff	139	[..]
bogdanm	0:9b334a45a8ff	140	This section provide functions allowing to configure the internal/external
bogdanm	0:9b334a45a8ff	141	clocks, PLL, CSS and MCO.
bogdanm	0:9b334a45a8ff	142	[..] Internal/external clock and PLL configuration
bogdanm	0:9b334a45a8ff	143	(#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly
bogdanm	0:9b334a45a8ff	144	or through the PLL as System clock source.
bogdanm	0:9b334a45a8ff	145	(#) MSI (multi-speed internal), multispeed low power RC
bogdanm	0:9b334a45a8ff	146	(65.536 KHz to 4.194 MHz) MHz used as System clock source.
bogdanm	0:9b334a45a8ff	147	(#) LSI (low-speed internal), 37 KHz low consumption RC used as IWDG
bogdanm	0:9b334a45a8ff	148	and/or RTC clock source.
bogdanm	0:9b334a45a8ff	149	(#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used
bogdanm	0:9b334a45a8ff	150	directly or through the PLL as System clock source. Can be used
bogdanm	0:9b334a45a8ff	151	also as RTC clock source.
bogdanm	0:9b334a45a8ff	152	(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
bogdanm	0:9b334a45a8ff	153	(#) PLL (clocked by HSI or HSE), for System clock and USB (48 MHz).
bogdanm	0:9b334a45a8ff	154	(#) CSS (Clock security system), once enable and if a HSE clock failure
bogdanm	0:9b334a45a8ff	155	occurs (HSE used directly or through PLL as System clock source),
bogdanm	0:9b334a45a8ff	156	the System clock is automatically switched to MSI and an interrupt
bogdanm	0:9b334a45a8ff	157	is generated if enabled.
bogdanm	0:9b334a45a8ff	158	The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt)
bogdanm	0:9b334a45a8ff	159	exception vector.
bogdanm	0:9b334a45a8ff	160	(#) MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI,
bogdanm	0:9b334a45a8ff	161	HSE, PLL, LSI or LSE clock (through a configurable prescaler) on
bogdanm	0:9b334a45a8ff	162	PA8 pin.
bogdanm	0:9b334a45a8ff	163	[..] System, AHB and APB busses clocks configuration
bogdanm	0:9b334a45a8ff	164	(#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
bogdanm	0:9b334a45a8ff	165	HSE and PLL.
bogdanm	0:9b334a45a8ff	166	The AHB clock (HCLK) is derived from System clock through configurable
bogdanm	0:9b334a45a8ff	167	prescaler and used to clock the CPU, memory and peripherals mapped
bogdanm	0:9b334a45a8ff	168	on IOPORT, AHB bus (DMA,Flash...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
bogdanm	0:9b334a45a8ff	169	from AHB clock through configurable prescalers and used to clock
bogdanm	0:9b334a45a8ff	170	the peripherals mapped on these busses. You can use
bogdanm	0:9b334a45a8ff	171	"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
bogdanm	0:9b334a45a8ff	174	(+@) I2S: the I2S clock can be derived from an external clock mapped on the I2S_CKIN pin.
bogdanm	0:9b334a45a8ff	175
bogdanm	0:9b334a45a8ff	176	(+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
bogdanm	0:9b334a45a8ff	177	divided by 2 to 16. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
bogdanm	0:9b334a45a8ff	178	macros to configure this clock.
bogdanm	0:9b334a45a8ff	179	(+@) USB FS,and RNG require a frequency equal to 48 MHz to work correctly
bogdanm	0:9b334a45a8ff	180	This clock is derived from the main PLL or HSI48 RC oscillator.
bogdanm	0:9b334a45a8ff	181	(+@) IWDG clock which is always the LSI clock.
bogdanm	0:9b334a45a8ff	182
bogdanm	0:9b334a45a8ff	183	(#) For the STM32L0xx devices, the maximum
bogdanm	0:9b334a45a8ff	184	frequency of the SYSCLK ,HCLK, APB1 and APB2 is 32 MHz.
bogdanm	0:9b334a45a8ff	185	Depending on the device voltage range, the maximum frequency should
bogdanm	0:9b334a45a8ff	186	be adapted accordingly:
bogdanm	0:9b334a45a8ff	187	----------------------------------------------------------------
bogdanm	0:9b334a45a8ff	188	\| Wait states \| HCLK clock frequency (MHz) \|
bogdanm	0:9b334a45a8ff	189	\| \|------------------------------------------------\|
bogdanm	0:9b334a45a8ff	190	\| (Latency) \| voltage range \| voltage range \|
bogdanm	0:9b334a45a8ff	191	\| \| 1.65 V - 3.6 V \| 2.0 V - 3.6 V \|
bogdanm	0:9b334a45a8ff	192	\| \|----------------\|---------------\|---------------\|
bogdanm	0:9b334a45a8ff	193	\| \| VCORE = 1.2 V \| VCORE = 1.5 V \| VCORE = 1.8 V \|
bogdanm	0:9b334a45a8ff	194	\|-------------- \|----------------\|---------------\|---------------\|
bogdanm	0:9b334a45a8ff	195	\|0WS(1CPU cycle)\|0 < HCLK <= 2 \|0 < HCLK <= 8 \|0 < HCLK <= 16 \|
bogdanm	0:9b334a45a8ff	196	\|---------------\|----------------\|---------------\|---------------\|
bogdanm	0:9b334a45a8ff	197	\|1WS(2CPU cycle)\|2 < HCLK <= 4 \|8 < HCLK <= 16 \|16 < HCLK <= 32\|
bogdanm	0:9b334a45a8ff	198	----------------------------------------------------------------
bogdanm	0:9b334a45a8ff	199	@endverbatim
bogdanm	0:9b334a45a8ff	200	* @{
bogdanm	0:9b334a45a8ff	201	*/
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	/**
bogdanm	0:9b334a45a8ff	204	* @brief Resets the RCC clock configuration to the default reset state.
bogdanm	0:9b334a45a8ff	205	* @note The default reset state of the clock configuration is given below:
bogdanm	0:9b334a45a8ff	206	* - MSI ON and used as system clock source (MSI range is not modified
bogdanm	0:9b334a45a8ff	207	* - by this function, it keep the value configured by user application)
bogdanm	0:9b334a45a8ff	208	* - HSI, HSE and PLL OFF
bogdanm	0:9b334a45a8ff	209	* - AHB, APB1 and APB2 prescaler set to 1.
bogdanm	0:9b334a45a8ff	210	* - CSS and MCO OFF
bogdanm	0:9b334a45a8ff	211	* - All interrupts disabled
bogdanm	0:9b334a45a8ff	212	* @note This function does not modify the configuration of the
bogdanm	0:9b334a45a8ff	213	* @note -Peripheral clocks
bogdanm	0:9b334a45a8ff	214	* @note -HSI48, LSI, LSE and RTC clocks
bogdanm	0:9b334a45a8ff	215	* @param None
bogdanm	0:9b334a45a8ff	216	* @retval None
bogdanm	0:9b334a45a8ff	217	*/
bogdanm	0:9b334a45a8ff	218	__weak void HAL_RCC_DeInit(void)
bogdanm	0:9b334a45a8ff	219	{
bogdanm	0:9b334a45a8ff	220	/* This function is now defined in the file stm32L0xx_rcc_ex.c */
bogdanm	0:9b334a45a8ff	221	}
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	/**
bogdanm	0:9b334a45a8ff	224	* @brief Initializes the RCC Oscillators according to the specified parameters in the
bogdanm	0:9b334a45a8ff	225	* RCC_OscInitTypeDef.
bogdanm	0:9b334a45a8ff	226	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm	0:9b334a45a8ff	227	* contains the configuration information for the RCC Oscillators.
bogdanm	0:9b334a45a8ff	228	* @note The PLL is not disabled when used as system clock.
bogdanm	0:9b334a45a8ff	229	* @retval HAL status
bogdanm	0:9b334a45a8ff	230	*/
bogdanm	0:9b334a45a8ff	231	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm	0:9b334a45a8ff	232	{
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	235
bogdanm	0:9b334a45a8ff	236	/* Check the parameters */
bogdanm	0:9b334a45a8ff	237	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
bogdanm	0:9b334a45a8ff	238	/------------------------------- HSE Configuration ------------------------/
bogdanm	0:9b334a45a8ff	239	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
bogdanm	0:9b334a45a8ff	240	{
bogdanm	0:9b334a45a8ff	241	/* Check the parameters */
bogdanm	0:9b334a45a8ff	242	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
bogdanm	0:9b334a45a8ff	243	/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
bogdanm	0:9b334a45a8ff	244	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSE)))
bogdanm	0:9b334a45a8ff	245	{
bogdanm	0:9b334a45a8ff	246	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
bogdanm	0:9b334a45a8ff	247	{
bogdanm	0:9b334a45a8ff	248	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	249	}
bogdanm	0:9b334a45a8ff	250	}
bogdanm	0:9b334a45a8ff	251	else
bogdanm	0:9b334a45a8ff	252	{
bogdanm	0:9b334a45a8ff	253	/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
bogdanm	0:9b334a45a8ff	254	__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	/* Get timeout */
bogdanm	0:9b334a45a8ff	257	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	258
bogdanm	0:9b334a45a8ff	259	/* Wait till HSE is disabled */
bogdanm	0:9b334a45a8ff	260	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm	0:9b334a45a8ff	261	{
bogdanm	0:9b334a45a8ff	262	if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	263	{
bogdanm	0:9b334a45a8ff	264	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	265	}
bogdanm	0:9b334a45a8ff	266	}
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	/* Set the new HSE configuration ---------------------------------------*/
bogdanm	0:9b334a45a8ff	269	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
bogdanm	0:9b334a45a8ff	270
bogdanm	0:9b334a45a8ff	271	/* Check the HSE State */
bogdanm	0:9b334a45a8ff	272	if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
bogdanm	0:9b334a45a8ff	273	{
bogdanm	0:9b334a45a8ff	274	/* Get timeout */
bogdanm	0:9b334a45a8ff	275	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	276
bogdanm	0:9b334a45a8ff	277	/* Wait till HSE is ready */
bogdanm	0:9b334a45a8ff	278	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm	0:9b334a45a8ff	279	{
bogdanm	0:9b334a45a8ff	280	if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	281	{
bogdanm	0:9b334a45a8ff	282	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	283	}
bogdanm	0:9b334a45a8ff	284	}
bogdanm	0:9b334a45a8ff	285	}
bogdanm	0:9b334a45a8ff	286	else
bogdanm	0:9b334a45a8ff	287	{
bogdanm	0:9b334a45a8ff	288	/* Get timeout */
bogdanm	0:9b334a45a8ff	289	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	290
bogdanm	0:9b334a45a8ff	291	/* Wait till HSE is disabled */
bogdanm	0:9b334a45a8ff	292	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm	0:9b334a45a8ff	293	{
bogdanm	0:9b334a45a8ff	294	if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	295	{
bogdanm	0:9b334a45a8ff	296	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	297	}
bogdanm	0:9b334a45a8ff	298	}
bogdanm	0:9b334a45a8ff	299	}
bogdanm	0:9b334a45a8ff	300	}
bogdanm	0:9b334a45a8ff	301	}
bogdanm	0:9b334a45a8ff	302	/----------------------------- HSI Configuration --------------------------/
bogdanm	0:9b334a45a8ff	303	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
bogdanm	0:9b334a45a8ff	304	{
bogdanm	0:9b334a45a8ff	305	/* Check the parameters */
bogdanm	0:9b334a45a8ff	306	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
bogdanm	0:9b334a45a8ff	307	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
bogdanm	0:9b334a45a8ff	308
bogdanm	0:9b334a45a8ff	309	/* When the HSI is used as system clock it will not disabled */
bogdanm	0:9b334a45a8ff	310	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSI)))
bogdanm	0:9b334a45a8ff	311	{
bogdanm	0:9b334a45a8ff	312	/* When HSI is used as system clock it will not disabled */
bogdanm	0:9b334a45a8ff	313	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
bogdanm	0:9b334a45a8ff	314	{
bogdanm	0:9b334a45a8ff	315	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	316	}
bogdanm	0:9b334a45a8ff	317	/* Otherwise, just the calibration is allowed */
bogdanm	0:9b334a45a8ff	318	else
bogdanm	0:9b334a45a8ff	319	{
bogdanm	0:9b334a45a8ff	320	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm	0:9b334a45a8ff	321	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm	0:9b334a45a8ff	322	}
bogdanm	0:9b334a45a8ff	323	}
bogdanm	0:9b334a45a8ff	324	else
bogdanm	0:9b334a45a8ff	325	{
bogdanm	0:9b334a45a8ff	326	/* Check the HSI State */
bogdanm	0:9b334a45a8ff	327	if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
bogdanm	0:9b334a45a8ff	328	{
bogdanm	0:9b334a45a8ff	329	/* Enable the Internal High Speed oscillator (HSI or HSIdiv4 */
bogdanm	0:9b334a45a8ff	330	__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	333	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	/* Wait till HSI is ready */
bogdanm	0:9b334a45a8ff	336	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	337	{
bogdanm	0:9b334a45a8ff	338	if((HAL_GetTick() - tickstart ) > RCC_HSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	339	{
bogdanm	0:9b334a45a8ff	340	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	341	}
bogdanm	0:9b334a45a8ff	342	}
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm	0:9b334a45a8ff	345	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm	0:9b334a45a8ff	346	}
bogdanm	0:9b334a45a8ff	347	else
bogdanm	0:9b334a45a8ff	348	{
bogdanm	0:9b334a45a8ff	349	/* Disable the Internal High Speed oscillator (HSI). */
bogdanm	0:9b334a45a8ff	350	__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	353	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/* Wait till HSI is ready */
bogdanm	0:9b334a45a8ff	356	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
bogdanm	0:9b334a45a8ff	357	{
bogdanm	0:9b334a45a8ff	358	if((HAL_GetTick() - tickstart ) > RCC_HSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	359	{
bogdanm	0:9b334a45a8ff	360	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	361	}
bogdanm	0:9b334a45a8ff	362	}
bogdanm	0:9b334a45a8ff	363	}
bogdanm	0:9b334a45a8ff	364	}
bogdanm	0:9b334a45a8ff	365	}
bogdanm	0:9b334a45a8ff	366	/----------------------------- MSI Configuration --------------------------/
bogdanm	0:9b334a45a8ff	367	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
bogdanm	0:9b334a45a8ff	368	{
bogdanm	0:9b334a45a8ff	369	/* Check the parameters */
bogdanm	0:9b334a45a8ff	370	assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
bogdanm	0:9b334a45a8ff	371	assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
bogdanm	0:9b334a45a8ff	372
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/* When the MSI is used as system clock it will not disabled */
bogdanm	0:9b334a45a8ff	375	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) )
bogdanm	0:9b334a45a8ff	376	{
bogdanm	0:9b334a45a8ff	377	if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState != RCC_MSI_ON))
bogdanm	0:9b334a45a8ff	378	{
bogdanm	0:9b334a45a8ff	379	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	380	}
bogdanm	0:9b334a45a8ff	381
bogdanm	0:9b334a45a8ff	382	/* Otherwise, just the calibration and MSI range change are allowed */
bogdanm	0:9b334a45a8ff	383	else
bogdanm	0:9b334a45a8ff	384	{
bogdanm	0:9b334a45a8ff	385	/* Selects the Multiple Speed oscillator (MSI) clock range .*/
bogdanm	0:9b334a45a8ff	386	__HAL_RCC_MSI_RANGE_CONFIG (RCC_OscInitStruct->MSIClockRange);
bogdanm	0:9b334a45a8ff	387	/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
bogdanm	0:9b334a45a8ff	388	__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
bogdanm	0:9b334a45a8ff	389	}
bogdanm	0:9b334a45a8ff	390	}
bogdanm	0:9b334a45a8ff	391	else
bogdanm	0:9b334a45a8ff	392	{
bogdanm	0:9b334a45a8ff	393	/* Check the MSI State */
bogdanm	0:9b334a45a8ff	394	if((RCC_OscInitStruct->MSIState)!= RCC_MSI_OFF)
bogdanm	0:9b334a45a8ff	395	{
bogdanm	0:9b334a45a8ff	396	/* Enable the Internal High Speed oscillator (MSI). */
bogdanm	0:9b334a45a8ff	397	__HAL_RCC_MSI_ENABLE();
bogdanm	0:9b334a45a8ff	398
bogdanm	0:9b334a45a8ff	399	/* Get timeout */
bogdanm	0:9b334a45a8ff	400	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	401
bogdanm	0:9b334a45a8ff	402	/* Wait till MSI is ready */
bogdanm	0:9b334a45a8ff	403	while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	404	{
bogdanm	0:9b334a45a8ff	405	if((HAL_GetTick() - tickstart ) > RCC_MSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	406	{
bogdanm	0:9b334a45a8ff	407	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	408	}
bogdanm	0:9b334a45a8ff	409	}
bogdanm	0:9b334a45a8ff	410	/* Selects the Multiple Speed oscillator (MSI) clock range .*/
bogdanm	0:9b334a45a8ff	411	__HAL_RCC_MSI_RANGE_CONFIG (RCC_OscInitStruct->MSIClockRange);
bogdanm	0:9b334a45a8ff	412	/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
bogdanm	0:9b334a45a8ff	413	__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	}
bogdanm	0:9b334a45a8ff	416	else
bogdanm	0:9b334a45a8ff	417	{
bogdanm	0:9b334a45a8ff	418	/* Disable the Internal High Speed oscillator (MSI). */
bogdanm	0:9b334a45a8ff	419	__HAL_RCC_MSI_DISABLE();
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	/* Get timeout */
bogdanm	0:9b334a45a8ff	422	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424	/* Wait till MSI is ready */
bogdanm	0:9b334a45a8ff	425	while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET)
bogdanm	0:9b334a45a8ff	426	{
bogdanm	0:9b334a45a8ff	427	if((HAL_GetTick() - tickstart ) > RCC_MSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	428	{
bogdanm	0:9b334a45a8ff	429	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	430	}
bogdanm	0:9b334a45a8ff	431	}
bogdanm	0:9b334a45a8ff	432	}
bogdanm	0:9b334a45a8ff	433	}
bogdanm	0:9b334a45a8ff	434	}
bogdanm	0:9b334a45a8ff	435	/------------------------------ LSI Configuration -------------------------/
bogdanm	0:9b334a45a8ff	436	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
bogdanm	0:9b334a45a8ff	437	{
bogdanm	0:9b334a45a8ff	438	/* Check the parameters */
bogdanm	0:9b334a45a8ff	439	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
bogdanm	0:9b334a45a8ff	440
bogdanm	0:9b334a45a8ff	441	/* Check the LSI State */
bogdanm	0:9b334a45a8ff	442	if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
bogdanm	0:9b334a45a8ff	443	{
bogdanm	0:9b334a45a8ff	444	/* Enable the Internal Low Speed oscillator (LSI). */
bogdanm	0:9b334a45a8ff	445	__HAL_RCC_LSI_ENABLE();
bogdanm	0:9b334a45a8ff	446
bogdanm	0:9b334a45a8ff	447	/* Get timeout */
bogdanm	0:9b334a45a8ff	448	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	/* Wait till LSI is ready */
bogdanm	0:9b334a45a8ff	451	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	452	{
bogdanm	0:9b334a45a8ff	453	if((HAL_GetTick() - tickstart ) > RCC_LSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	454	{
bogdanm	0:9b334a45a8ff	455	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	456	}
bogdanm	0:9b334a45a8ff	457	}
bogdanm	0:9b334a45a8ff	458	}
bogdanm	0:9b334a45a8ff	459	else
bogdanm	0:9b334a45a8ff	460	{
bogdanm	0:9b334a45a8ff	461	/* Disable the Internal Low Speed oscillator (LSI). */
bogdanm	0:9b334a45a8ff	462	__HAL_RCC_LSI_DISABLE();
bogdanm	0:9b334a45a8ff	463
bogdanm	0:9b334a45a8ff	464	/* Get timeout */
bogdanm	0:9b334a45a8ff	465	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	466
bogdanm	0:9b334a45a8ff	467	/* Wait till LSI is ready */
bogdanm	0:9b334a45a8ff	468	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
bogdanm	0:9b334a45a8ff	469	{
bogdanm	0:9b334a45a8ff	470	if((HAL_GetTick() - tickstart ) > RCC_LSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	471	{
bogdanm	0:9b334a45a8ff	472	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	473	}
bogdanm	0:9b334a45a8ff	474	}
bogdanm	0:9b334a45a8ff	475	}
bogdanm	0:9b334a45a8ff	476	}
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	479	/------------------------------ HSI48 Configuration -------------------------/
bogdanm	0:9b334a45a8ff	480	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
bogdanm	0:9b334a45a8ff	481	{
bogdanm	0:9b334a45a8ff	482	/* Check the parameters */
bogdanm	0:9b334a45a8ff	483	assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485	/* Check the HSI48 State */
bogdanm	0:9b334a45a8ff	486	if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF)
bogdanm	0:9b334a45a8ff	487	{
bogdanm	0:9b334a45a8ff	488	/* Enable the Internal Low Speed oscillator (HSI48). */
bogdanm	0:9b334a45a8ff	489	__HAL_RCC_HSI48_ENABLE();
bogdanm	0:9b334a45a8ff	490
bogdanm	0:9b334a45a8ff	491	/* Get timeout */
bogdanm	0:9b334a45a8ff	492	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	/* Wait till HSI48 is ready */
bogdanm	0:9b334a45a8ff	495	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
bogdanm	0:9b334a45a8ff	496	{
bogdanm	0:9b334a45a8ff	497	if((HAL_GetTick() - tickstart ) > RCC_HSI48_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	498	{
bogdanm	0:9b334a45a8ff	499	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	500	}
bogdanm	0:9b334a45a8ff	501	}
bogdanm	0:9b334a45a8ff	502	}
bogdanm	0:9b334a45a8ff	503	else
bogdanm	0:9b334a45a8ff	504	{
bogdanm	0:9b334a45a8ff	505	/* Disable the Internal Low Speed oscillator (HSI48). */
bogdanm	0:9b334a45a8ff	506	__HAL_RCC_HSI48_DISABLE();
bogdanm	0:9b334a45a8ff	507
bogdanm	0:9b334a45a8ff	508	/* Get timeout */
bogdanm	0:9b334a45a8ff	509	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	510
bogdanm	0:9b334a45a8ff	511	/* Wait till HSI48 is ready */
bogdanm	0:9b334a45a8ff	512	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
bogdanm	0:9b334a45a8ff	513	{
bogdanm	0:9b334a45a8ff	514	if((HAL_GetTick() - tickstart ) > RCC_HSI48_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	515	{
bogdanm	0:9b334a45a8ff	516	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	517	}
bogdanm	0:9b334a45a8ff	518	}
bogdanm	0:9b334a45a8ff	519	}
bogdanm	0:9b334a45a8ff	520	}
bogdanm	0:9b334a45a8ff	521	#endif /* !(STM32L031xx) && !(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)*/
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	/------------------------------ LSE Configuration -------------------------/
bogdanm	0:9b334a45a8ff	524	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
bogdanm	0:9b334a45a8ff	525	{
bogdanm	0:9b334a45a8ff	526	/* Check the parameters */
bogdanm	0:9b334a45a8ff	527	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529	/* Enable Power Clock*/
bogdanm	0:9b334a45a8ff	530	__HAL_RCC_PWR_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532	/* Enable write access to Backup domain */
bogdanm	0:9b334a45a8ff	533	PWR->CR \|= PWR_CR_DBP;
bogdanm	0:9b334a45a8ff	534
bogdanm	0:9b334a45a8ff	535	/* Wait for Backup domain Write protection disable */
bogdanm	0:9b334a45a8ff	536	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	537
bogdanm	0:9b334a45a8ff	538	while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm	0:9b334a45a8ff	539	{
bogdanm	0:9b334a45a8ff	540	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	541	{
bogdanm	0:9b334a45a8ff	542	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	543	}
bogdanm	0:9b334a45a8ff	544	}
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
bogdanm	0:9b334a45a8ff	547	__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
bogdanm	0:9b334a45a8ff	548
bogdanm	0:9b334a45a8ff	549	/* Get timeout */
bogdanm	0:9b334a45a8ff	550	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	553	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm	0:9b334a45a8ff	554	{
bogdanm	0:9b334a45a8ff	555	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	556	{
bogdanm	0:9b334a45a8ff	557	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	558	}
bogdanm	0:9b334a45a8ff	559	}
bogdanm	0:9b334a45a8ff	560
bogdanm	0:9b334a45a8ff	561	/* Set the new LSE configuration -----------------------------------------*/
bogdanm	0:9b334a45a8ff	562	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
bogdanm	0:9b334a45a8ff	563	/* Check the LSE State */
bogdanm	0:9b334a45a8ff	564	if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
bogdanm	0:9b334a45a8ff	565	{
bogdanm	0:9b334a45a8ff	566	/* Get timeout */
bogdanm	0:9b334a45a8ff	567	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	568
bogdanm	0:9b334a45a8ff	569	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	570	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm	0:9b334a45a8ff	571	{
bogdanm	0:9b334a45a8ff	572	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	573	{
bogdanm	0:9b334a45a8ff	574	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	575	}
bogdanm	0:9b334a45a8ff	576	}
bogdanm	0:9b334a45a8ff	577	}
bogdanm	0:9b334a45a8ff	578	else
bogdanm	0:9b334a45a8ff	579	{
bogdanm	0:9b334a45a8ff	580	/* Get timeout */
bogdanm	0:9b334a45a8ff	581	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	582
bogdanm	0:9b334a45a8ff	583	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	584	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm	0:9b334a45a8ff	585	{
bogdanm	0:9b334a45a8ff	586	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	587	{
bogdanm	0:9b334a45a8ff	588	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	589	}
bogdanm	0:9b334a45a8ff	590	}
bogdanm	0:9b334a45a8ff	591	}
bogdanm	0:9b334a45a8ff	592	}
bogdanm	0:9b334a45a8ff	593	/-------------------------------- PLL Configuration -----------------------/
bogdanm	0:9b334a45a8ff	594	/* Check the parameters */
bogdanm	0:9b334a45a8ff	595	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
bogdanm	0:9b334a45a8ff	596	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
bogdanm	0:9b334a45a8ff	597	{
bogdanm	0:9b334a45a8ff	598	/* Check if the PLL is used as system clock or not */
bogdanm	0:9b334a45a8ff	599	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm	0:9b334a45a8ff	600	{
bogdanm	0:9b334a45a8ff	601	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
bogdanm	0:9b334a45a8ff	602	{
bogdanm	0:9b334a45a8ff	603	/* Check the parameters */
bogdanm	0:9b334a45a8ff	604	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
bogdanm	0:9b334a45a8ff	605	assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
bogdanm	0:9b334a45a8ff	606	assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
bogdanm	0:9b334a45a8ff	607
bogdanm	0:9b334a45a8ff	608
bogdanm	0:9b334a45a8ff	609	/* Disable the main PLL. */
bogdanm	0:9b334a45a8ff	610	__HAL_RCC_PLL_DISABLE();
bogdanm	0:9b334a45a8ff	611
bogdanm	0:9b334a45a8ff	612	/* Get timeout */
bogdanm	0:9b334a45a8ff	613	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	614
bogdanm	0:9b334a45a8ff	615	/* Wait till PLL is ready */
bogdanm	0:9b334a45a8ff	616	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm	0:9b334a45a8ff	617	{
bogdanm	0:9b334a45a8ff	618	if((HAL_GetTick() - tickstart ) > RCC_PLL_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	619	{
bogdanm	0:9b334a45a8ff	620	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	621	}
bogdanm	0:9b334a45a8ff	622	}
bogdanm	0:9b334a45a8ff	623
bogdanm	0:9b334a45a8ff	624	/* Configure the main PLL clock source, multiplication and division factors. */
bogdanm	0:9b334a45a8ff	625	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
bogdanm	0:9b334a45a8ff	626	RCC_OscInitStruct->PLL.PLLMUL,
bogdanm	0:9b334a45a8ff	627	RCC_OscInitStruct->PLL.PLLDIV);
bogdanm	0:9b334a45a8ff	628	/* Enable the main PLL. */
bogdanm	0:9b334a45a8ff	629	__HAL_RCC_PLL_ENABLE();
bogdanm	0:9b334a45a8ff	630
bogdanm	0:9b334a45a8ff	631	/* Get timeout */
bogdanm	0:9b334a45a8ff	632	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	633
bogdanm	0:9b334a45a8ff	634	/* Wait till PLL is ready */
bogdanm	0:9b334a45a8ff	635	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm	0:9b334a45a8ff	636	{
bogdanm	0:9b334a45a8ff	637	if((HAL_GetTick() - tickstart ) > RCC_PLL_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	638	{
bogdanm	0:9b334a45a8ff	639	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	640	}
bogdanm	0:9b334a45a8ff	641	}
bogdanm	0:9b334a45a8ff	642	}
bogdanm	0:9b334a45a8ff	643	else
bogdanm	0:9b334a45a8ff	644	{
bogdanm	0:9b334a45a8ff	645	/* Disable the main PLL. */
bogdanm	0:9b334a45a8ff	646	__HAL_RCC_PLL_DISABLE();
bogdanm	0:9b334a45a8ff	647	/* Get timeout */
bogdanm	0:9b334a45a8ff	648	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	649
bogdanm	0:9b334a45a8ff	650	/* Wait till PLL is ready */
bogdanm	0:9b334a45a8ff	651	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm	0:9b334a45a8ff	652	{
bogdanm	0:9b334a45a8ff	653	if((HAL_GetTick() - tickstart ) > RCC_PLL_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	654	{
bogdanm	0:9b334a45a8ff	655	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	656	}
bogdanm	0:9b334a45a8ff	657	}
bogdanm	0:9b334a45a8ff	658	}
bogdanm	0:9b334a45a8ff	659	}
bogdanm	0:9b334a45a8ff	660	else
bogdanm	0:9b334a45a8ff	661	{
bogdanm	0:9b334a45a8ff	662	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	663	}
bogdanm	0:9b334a45a8ff	664	}
bogdanm	0:9b334a45a8ff	665	return HAL_OK;
bogdanm	0:9b334a45a8ff	666	}
bogdanm	0:9b334a45a8ff	667
bogdanm	0:9b334a45a8ff	668	/**
bogdanm	0:9b334a45a8ff	669	* @brief Initializes the CPU, AHB and APB busses clocks according to the specified
bogdanm	0:9b334a45a8ff	670	* parameters in the RCC_ClkInitStruct.
bogdanm	0:9b334a45a8ff	671	* @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm	0:9b334a45a8ff	672	* contains the configuration information for the RCC peripheral.
bogdanm	0:9b334a45a8ff	673	* @param FLatency: FLASH Latency, this parameter depends on System Clock Frequency
bogdanm	0:9b334a45a8ff	674	*
bogdanm	0:9b334a45a8ff	675	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
bogdanm	0:9b334a45a8ff	676	* and updated by HAL_RCC_GetHCLKFreq() function called within this function
bogdanm	0:9b334a45a8ff	677	*
bogdanm	0:9b334a45a8ff	678	* @note The MSI is used (enabled by hardware) as system clock source after
bogdanm	0:9b334a45a8ff	679	* startup from Reset, wake-up from STOP and STANDBY mode, or in case
bogdanm	0:9b334a45a8ff	680	* of failure of the HSE used directly or indirectly as system clock
bogdanm	0:9b334a45a8ff	681	* (if the Clock Security System CSS is enabled).
bogdanm	0:9b334a45a8ff	682	*
bogdanm	0:9b334a45a8ff	683	* @note A switch from one clock source to another occurs only if the target
bogdanm	0:9b334a45a8ff	684	* clock source is ready (clock stable after startup delay or PLL locked).
bogdanm	0:9b334a45a8ff	685	* If a clock source which is not yet ready is selected, the switch will
bogdanm	0:9b334a45a8ff	686	* occur when the clock source will be ready.
bogdanm	0:9b334a45a8ff	687	* @retval None
bogdanm	0:9b334a45a8ff	688	*/
bogdanm	0:9b334a45a8ff	689	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
bogdanm	0:9b334a45a8ff	690	{
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	/* Check the parameters */
bogdanm	0:9b334a45a8ff	695	assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
bogdanm	0:9b334a45a8ff	696	assert_param(IS_FLASH_LATENCY(FLatency));
bogdanm	0:9b334a45a8ff	697
bogdanm	0:9b334a45a8ff	698	/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
bogdanm	0:9b334a45a8ff	699	must be correctly programmed according to the frequency of the CPU clock
bogdanm	0:9b334a45a8ff	700	(HCLK) and the supply voltage of the device. */
bogdanm	0:9b334a45a8ff	701
bogdanm	0:9b334a45a8ff	702	/* Increasing the CPU frequency */
bogdanm	0:9b334a45a8ff	703	if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
bogdanm	0:9b334a45a8ff	704	{
bogdanm	0:9b334a45a8ff	705	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
bogdanm	0:9b334a45a8ff	706	__HAL_FLASH_SET_LATENCY(FLatency);
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	/* Check that the new number of wait states is taken into account to access the Flash
bogdanm	0:9b334a45a8ff	709	memory by reading the FLASH_ACR register */
bogdanm	0:9b334a45a8ff	710	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	713	}
bogdanm	0:9b334a45a8ff	714
bogdanm	0:9b334a45a8ff	715	/-------------------------- HCLK Configuration --------------------------/
bogdanm	0:9b334a45a8ff	716	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
bogdanm	0:9b334a45a8ff	717	{
bogdanm	0:9b334a45a8ff	718	assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
bogdanm	0:9b334a45a8ff	719	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
bogdanm	0:9b334a45a8ff	720	}
bogdanm	0:9b334a45a8ff	721
bogdanm	0:9b334a45a8ff	722	/------------------------- SYSCLK Configuration ---------------------------/
bogdanm	0:9b334a45a8ff	723	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
bogdanm	0:9b334a45a8ff	724	{
bogdanm	0:9b334a45a8ff	725	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
bogdanm	0:9b334a45a8ff	726
bogdanm	0:9b334a45a8ff	727	/* HSE is selected as System Clock Source */
bogdanm	0:9b334a45a8ff	728	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm	0:9b334a45a8ff	729	{
bogdanm	0:9b334a45a8ff	730	/* Check the HSE ready flag */
bogdanm	0:9b334a45a8ff	731	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm	0:9b334a45a8ff	732	{
bogdanm	0:9b334a45a8ff	733	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	734	}
bogdanm	0:9b334a45a8ff	735	}
bogdanm	0:9b334a45a8ff	736
bogdanm	0:9b334a45a8ff	737	/* MSI is selected as System Clock Source */
bogdanm	0:9b334a45a8ff	738	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
bogdanm	0:9b334a45a8ff	739	{
bogdanm	0:9b334a45a8ff	740	/* Check the MSI ready flag */
bogdanm	0:9b334a45a8ff	741	if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	742	{
bogdanm	0:9b334a45a8ff	743	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	744	}
bogdanm	0:9b334a45a8ff	745	}
bogdanm	0:9b334a45a8ff	746	/* PLL is selected as System Clock Source */
bogdanm	0:9b334a45a8ff	747	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm	0:9b334a45a8ff	748	{
bogdanm	0:9b334a45a8ff	749	/* Check the PLL ready flag */
bogdanm	0:9b334a45a8ff	750	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm	0:9b334a45a8ff	751	{
bogdanm	0:9b334a45a8ff	752	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	753	}
bogdanm	0:9b334a45a8ff	754	}
bogdanm	0:9b334a45a8ff	755	/* HSI is selected as System Clock Source */
bogdanm	0:9b334a45a8ff	756	else
bogdanm	0:9b334a45a8ff	757	{
bogdanm	0:9b334a45a8ff	758	/* Check the HSI ready flag */
bogdanm	0:9b334a45a8ff	759	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	760	{
bogdanm	0:9b334a45a8ff	761	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	762	}
bogdanm	0:9b334a45a8ff	763	}
bogdanm	0:9b334a45a8ff	764	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
bogdanm	0:9b334a45a8ff	765
bogdanm	0:9b334a45a8ff	766	/* Get timeout */
bogdanm	0:9b334a45a8ff	767	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	768
bogdanm	0:9b334a45a8ff	769	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm	0:9b334a45a8ff	770	{
bogdanm	0:9b334a45a8ff	771	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm	0:9b334a45a8ff	772	{
bogdanm	0:9b334a45a8ff	773	if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	774	{
bogdanm	0:9b334a45a8ff	775	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	776	}
bogdanm	0:9b334a45a8ff	777	}
bogdanm	0:9b334a45a8ff	778	}
bogdanm	0:9b334a45a8ff	779	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm	0:9b334a45a8ff	780	{
bogdanm	0:9b334a45a8ff	781	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm	0:9b334a45a8ff	782	{
bogdanm	0:9b334a45a8ff	783	if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	784	{
bogdanm	0:9b334a45a8ff	785	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	786	}
bogdanm	0:9b334a45a8ff	787	}
bogdanm	0:9b334a45a8ff	788	}
bogdanm	0:9b334a45a8ff	789	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
bogdanm	0:9b334a45a8ff	790	{
bogdanm	0:9b334a45a8ff	791	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
bogdanm	0:9b334a45a8ff	792	{
bogdanm	0:9b334a45a8ff	793	if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	794	{
bogdanm	0:9b334a45a8ff	795	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	796	}
bogdanm	0:9b334a45a8ff	797	}
bogdanm	0:9b334a45a8ff	798	}
bogdanm	0:9b334a45a8ff	799	else
bogdanm	0:9b334a45a8ff	800	{
bogdanm	0:9b334a45a8ff	801	while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm	0:9b334a45a8ff	802	{
bogdanm	0:9b334a45a8ff	803	if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	804	{
bogdanm	0:9b334a45a8ff	805	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	806	}
bogdanm	0:9b334a45a8ff	807	}
bogdanm	0:9b334a45a8ff	808	}
bogdanm	0:9b334a45a8ff	809	}
bogdanm	0:9b334a45a8ff	810	}
bogdanm	0:9b334a45a8ff	811	/* Decreasing the CPU frequency */
bogdanm	0:9b334a45a8ff	812	else
bogdanm	0:9b334a45a8ff	813	{
bogdanm	0:9b334a45a8ff	814	/-------------------------- HCLK Configuration --------------------------/
bogdanm	0:9b334a45a8ff	815	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
bogdanm	0:9b334a45a8ff	816	{
bogdanm	0:9b334a45a8ff	817	assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
bogdanm	0:9b334a45a8ff	818	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
bogdanm	0:9b334a45a8ff	819	}
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	/------------------------- SYSCLK Configuration -------------------------/
bogdanm	0:9b334a45a8ff	822	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
bogdanm	0:9b334a45a8ff	823	{
bogdanm	0:9b334a45a8ff	824	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
bogdanm	0:9b334a45a8ff	825
bogdanm	0:9b334a45a8ff	826	/* HSE is selected as System Clock Source */
bogdanm	0:9b334a45a8ff	827	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm	0:9b334a45a8ff	828	{
bogdanm	0:9b334a45a8ff	829	/* Check the HSE ready flag */
bogdanm	0:9b334a45a8ff	830	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm	0:9b334a45a8ff	831	{
bogdanm	0:9b334a45a8ff	832	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	833	}
bogdanm	0:9b334a45a8ff	834	}
bogdanm	0:9b334a45a8ff	835
bogdanm	0:9b334a45a8ff	836	/* MSI is selected as System Clock Source */
bogdanm	0:9b334a45a8ff	837	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
bogdanm	0:9b334a45a8ff	838	{
bogdanm	0:9b334a45a8ff	839	/* Check the MSI ready flag */
bogdanm	0:9b334a45a8ff	840	if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	841	{
bogdanm	0:9b334a45a8ff	842	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	843	}
bogdanm	0:9b334a45a8ff	844	}
bogdanm	0:9b334a45a8ff	845	/* PLL is selected as System Clock Source */
bogdanm	0:9b334a45a8ff	846	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm	0:9b334a45a8ff	847	{
bogdanm	0:9b334a45a8ff	848	/* Check the PLL ready flag */
bogdanm	0:9b334a45a8ff	849	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm	0:9b334a45a8ff	850	{
bogdanm	0:9b334a45a8ff	851	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	852	}
bogdanm	0:9b334a45a8ff	853	}
bogdanm	0:9b334a45a8ff	854	/* HSI is selected as System Clock Source */
bogdanm	0:9b334a45a8ff	855	else
bogdanm	0:9b334a45a8ff	856	{
bogdanm	0:9b334a45a8ff	857	/* Check the HSI ready flag */
bogdanm	0:9b334a45a8ff	858	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	859	{
bogdanm	0:9b334a45a8ff	860	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	861	}
bogdanm	0:9b334a45a8ff	862	}
bogdanm	0:9b334a45a8ff	863	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	/* Get timeout */
bogdanm	0:9b334a45a8ff	866	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm	0:9b334a45a8ff	869	{
bogdanm	0:9b334a45a8ff	870	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm	0:9b334a45a8ff	871	{
bogdanm	0:9b334a45a8ff	872	if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	873	{
bogdanm	0:9b334a45a8ff	874	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	875	}
bogdanm	0:9b334a45a8ff	876	}
bogdanm	0:9b334a45a8ff	877	}
bogdanm	0:9b334a45a8ff	878	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm	0:9b334a45a8ff	879	{
bogdanm	0:9b334a45a8ff	880	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm	0:9b334a45a8ff	881	{
bogdanm	0:9b334a45a8ff	882	if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	883	{
bogdanm	0:9b334a45a8ff	884	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	885	}
bogdanm	0:9b334a45a8ff	886	}
bogdanm	0:9b334a45a8ff	887	}
bogdanm	0:9b334a45a8ff	888	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
bogdanm	0:9b334a45a8ff	889	{
bogdanm	0:9b334a45a8ff	890	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
bogdanm	0:9b334a45a8ff	891	{
bogdanm	0:9b334a45a8ff	892	if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	893	{
bogdanm	0:9b334a45a8ff	894	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	895	}
bogdanm	0:9b334a45a8ff	896	}
bogdanm	0:9b334a45a8ff	897	}
bogdanm	0:9b334a45a8ff	898	else
bogdanm	0:9b334a45a8ff	899	{
bogdanm	0:9b334a45a8ff	900	while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm	0:9b334a45a8ff	901	{
bogdanm	0:9b334a45a8ff	902	if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	903	{
bogdanm	0:9b334a45a8ff	904	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	905	}
bogdanm	0:9b334a45a8ff	906	}
bogdanm	0:9b334a45a8ff	907	}
bogdanm	0:9b334a45a8ff	908	}
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
bogdanm	0:9b334a45a8ff	911	__HAL_FLASH_SET_LATENCY(FLatency);
bogdanm	0:9b334a45a8ff	912
bogdanm	0:9b334a45a8ff	913	/* Check that the new number of wait states is taken into account to access the Flash
bogdanm	0:9b334a45a8ff	914	memory by reading the FLASH_ACR register */
bogdanm	0:9b334a45a8ff	915	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
bogdanm	0:9b334a45a8ff	916	{
bogdanm	0:9b334a45a8ff	917	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	918	}
bogdanm	0:9b334a45a8ff	919	}
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	/-------------------------- PCLK1 Configuration ---------------------------/
bogdanm	0:9b334a45a8ff	922	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
bogdanm	0:9b334a45a8ff	923	{
bogdanm	0:9b334a45a8ff	924	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
bogdanm	0:9b334a45a8ff	925	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
bogdanm	0:9b334a45a8ff	926	}
bogdanm	0:9b334a45a8ff	927
bogdanm	0:9b334a45a8ff	928	/-------------------------- PCLK2 Configuration ---------------------------/
bogdanm	0:9b334a45a8ff	929	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
bogdanm	0:9b334a45a8ff	930	{
bogdanm	0:9b334a45a8ff	931	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
bogdanm	0:9b334a45a8ff	932	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
bogdanm	0:9b334a45a8ff	933	}
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	/* Configure the source of time base considering new system clocks settings*/
bogdanm	0:9b334a45a8ff	936	HAL_InitTick (TICK_INT_PRIORITY);
bogdanm	0:9b334a45a8ff	937
bogdanm	0:9b334a45a8ff	938	return HAL_OK;
bogdanm	0:9b334a45a8ff	939	}
bogdanm	0:9b334a45a8ff	940
bogdanm	0:9b334a45a8ff	941	/**
bogdanm	0:9b334a45a8ff	942	* @}
bogdanm	0:9b334a45a8ff	943	*/
bogdanm	0:9b334a45a8ff	944
bogdanm	0:9b334a45a8ff	945	/** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions
bogdanm	0:9b334a45a8ff	946	* @brief RCC clocks control functions
bogdanm	0:9b334a45a8ff	947	*
bogdanm	0:9b334a45a8ff	948	@verbatim
bogdanm	0:9b334a45a8ff	949	===============================================================================
bogdanm	0:9b334a45a8ff	950	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	951	===============================================================================
bogdanm	0:9b334a45a8ff	952	[..]
bogdanm	0:9b334a45a8ff	953	This subsection provides a set of functions allowing to control the RCC Clocks
bogdanm	0:9b334a45a8ff	954	frequencies.
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	@endverbatim
bogdanm	0:9b334a45a8ff	957	* @{
bogdanm	0:9b334a45a8ff	958	*/
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960	/**
bogdanm	0:9b334a45a8ff	961	* @brief Selects the clock source to output on MCO pin.
bogdanm	0:9b334a45a8ff	962	* @note MCO pin should be configured in alternate function mode.
bogdanm	0:9b334a45a8ff	963	* @param RCC_MCOx: specifies the output direction for the clock source.
bogdanm	0:9b334a45a8ff	964	* For STM32L0xx family this parameter can have only one value:
bogdanm	0:9b334a45a8ff	965	* @arg RCC_MCO1: Clock source to output on MCO pin(PA8).
bogdanm	0:9b334a45a8ff	966	* @arg RCC_MCO2: Clock source to output on MCO pin(PA9).
bogdanm	0:9b334a45a8ff	967	* @param RCC_MCOSource: specifies the clock source to output.
bogdanm	0:9b334a45a8ff	968	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	969	* @arg RCC_MCO1SOURCE_NOCLOCK: No clock selected
bogdanm	0:9b334a45a8ff	970	* @arg RCC_MCO1SOURCE_SYSCLK: System clock selected
bogdanm	0:9b334a45a8ff	971	* @arg RCC_MCO1SOURCE_HSI: HSI oscillator clock selected
bogdanm	0:9b334a45a8ff	972	* @arg RCC_MCO1SOURCE_MSI: MSI oscillator clock selected
bogdanm	0:9b334a45a8ff	973	* @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected
bogdanm	0:9b334a45a8ff	974	* @arg RCC_MCO1SOURCE_PLLCLK: PLL clock selected
bogdanm	0:9b334a45a8ff	975	* @arg RCC_MCO1SOURCE_LSI: LSI clock selected
bogdanm	0:9b334a45a8ff	976	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected
bogdanm	0:9b334a45a8ff	977	* and in STM32L052xx,STM32L053xx,STM32L062xx, STM32L063xx
bogdanm	0:9b334a45a8ff	978	* STM32L072xx,STM32L073xx,STM32L082xx, STM32L083xx
bogdanm	0:9b334a45a8ff	979	* @arg RCC_MCO1SOURCE_HSI48: HSI48 clock selected
bogdanm	0:9b334a45a8ff	980	* @param RCC_MCODIV: specifies the MCO DIV.
bogdanm	0:9b334a45a8ff	981	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	982	* @arg RCC_MCODIV_1: no division applied to MCO clock
bogdanm	0:9b334a45a8ff	983	* @arg RCC_MCODIV_2: division by 2 applied to MCO clock
bogdanm	0:9b334a45a8ff	984	* @arg RCC_MCODIV_4: division by 4 applied to MCO clock
bogdanm	0:9b334a45a8ff	985	* @arg RCC_MCODIV_8: division by 8 applied to MCO clock
bogdanm	0:9b334a45a8ff	986	* @arg RCC_MCODIV_16: division by 16 applied to MCO clock
bogdanm	0:9b334a45a8ff	987	* @retval None
bogdanm	0:9b334a45a8ff	988	*/
bogdanm	0:9b334a45a8ff	989	void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
bogdanm	0:9b334a45a8ff	990	{
bogdanm	0:9b334a45a8ff	991	GPIO_InitTypeDef GPIO_InitStruct;
bogdanm	0:9b334a45a8ff	992	/* Check the parameters */
bogdanm	0:9b334a45a8ff	993	assert_param(IS_RCC_MCO(RCC_MCOx));
bogdanm	0:9b334a45a8ff	994	assert_param(IS_RCC_MCODIV(RCC_MCODiv));
bogdanm	0:9b334a45a8ff	995	assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997	/* MCO Clock Enable */
bogdanm	0:9b334a45a8ff	998	__MCO1_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	999
bogdanm	0:9b334a45a8ff	1000	/* Configure the MCO1 pin in alternate function mode */
bogdanm	0:9b334a45a8ff	1001	if(RCC_MCOx == RCC_MCO1)
bogdanm	0:9b334a45a8ff	1002	{
bogdanm	0:9b334a45a8ff	1003	GPIO_InitStruct.Pin = MCO1_PIN;
bogdanm	0:9b334a45a8ff	1004	}
bogdanm	0:9b334a45a8ff	1005	else
bogdanm	0:9b334a45a8ff	1006	{
bogdanm	0:9b334a45a8ff	1007	GPIO_InitStruct.Pin = MCO2_PIN;
bogdanm	0:9b334a45a8ff	1008	}
bogdanm	0:9b334a45a8ff	1009	GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
bogdanm	0:9b334a45a8ff	1010	GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
bogdanm	0:9b334a45a8ff	1011	GPIO_InitStruct.Pull = GPIO_NOPULL;
bogdanm	0:9b334a45a8ff	1012	GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
bogdanm	0:9b334a45a8ff	1013	HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
bogdanm	0:9b334a45a8ff	1014
bogdanm	0:9b334a45a8ff	1015	/* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
bogdanm	0:9b334a45a8ff	1016	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCO_PRE), ((RCC_MCOSource \| RCC_MCODiv )));
bogdanm	0:9b334a45a8ff	1017	}
bogdanm	0:9b334a45a8ff	1018
bogdanm	0:9b334a45a8ff	1019	/**
bogdanm	0:9b334a45a8ff	1020	* @brief Enables the Clock Security System.
bogdanm	0:9b334a45a8ff	1021	* @note If a failure is detected on the HSE oscillator clock, this oscillator
bogdanm	0:9b334a45a8ff	1022	* is automatically disabled and an interrupt is generated to inform the
bogdanm	0:9b334a45a8ff	1023	* software about the failure (Clock Security System Interrupt, CSSI),
bogdanm	0:9b334a45a8ff	1024	* allowing the MCU to perform rescue operations. The CSSI is linked to
bogdanm	0:9b334a45a8ff	1025	* the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector.
bogdanm	0:9b334a45a8ff	1026	* @param None
bogdanm	0:9b334a45a8ff	1027	* @retval None
bogdanm	0:9b334a45a8ff	1028	*/
bogdanm	0:9b334a45a8ff	1029	void HAL_RCC_EnableCSS(void)
bogdanm	0:9b334a45a8ff	1030	{
bogdanm	0:9b334a45a8ff	1031	SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
bogdanm	0:9b334a45a8ff	1032	}
bogdanm	0:9b334a45a8ff	1033
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	/**
bogdanm	0:9b334a45a8ff	1036	* @brief Returns the SYSCLK frequency
bogdanm	0:9b334a45a8ff	1037	*
bogdanm	0:9b334a45a8ff	1038	* @note The system frequency computed by this function is not the real
bogdanm	0:9b334a45a8ff	1039	* frequency in the chip. It is calculated based on the predefined
bogdanm	0:9b334a45a8ff	1040	* constant and the selected clock source:
bogdanm	0:9b334a45a8ff	1041	* @note If SYSCLK source is MSI, function returns values based on MSI
bogdanm	0:9b334a45a8ff	1042	* Value as defined by the MSI range.
bogdanm	0:9b334a45a8ff	1043	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
bogdanm	0:9b334a45a8ff	1044	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
bogdanm	0:9b334a45a8ff	1045	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
bogdanm	0:9b334a45a8ff	1046	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
bogdanm	0:9b334a45a8ff	1047	* @note (*) HSI_VALUE is a constant defined in stm32l0xx_hal_conf.h file (default value
bogdanm	0:9b334a45a8ff	1048	* 16 MHz) but the real value may vary depending on the variations
bogdanm	0:9b334a45a8ff	1049	* in voltage and temperature.
bogdanm	0:9b334a45a8ff	1050	* @note (**) HSE_VALUE is a constant defined in stm32l0xx_hal_conf.h file (default value
bogdanm	0:9b334a45a8ff	1051	* 8 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm	0:9b334a45a8ff	1052	* frequency of the crystal used. Otherwise, this function may
bogdanm	0:9b334a45a8ff	1053	* have wrong result.
bogdanm	0:9b334a45a8ff	1054	*
bogdanm	0:9b334a45a8ff	1055	* @note The result of this function could be not correct when using fractional
bogdanm	0:9b334a45a8ff	1056	* value for HSE crystal.
bogdanm	0:9b334a45a8ff	1057	*
bogdanm	0:9b334a45a8ff	1058	* @note This function can be used by the user application to compute the
bogdanm	0:9b334a45a8ff	1059	* baudrate for the communication peripherals or configure other parameters.
bogdanm	0:9b334a45a8ff	1060	*
bogdanm	0:9b334a45a8ff	1061	* @note Each time SYSCLK changes, this function must be called to update the
bogdanm	0:9b334a45a8ff	1062	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm	0:9b334a45a8ff	1063	*
bogdanm	0:9b334a45a8ff	1064	*
bogdanm	0:9b334a45a8ff	1065	* @param None
bogdanm	0:9b334a45a8ff	1066	* @retval SYSCLK frequency
bogdanm	0:9b334a45a8ff	1067	*/
bogdanm	0:9b334a45a8ff	1068	uint32_t HAL_RCC_GetSysClockFreq(void)
bogdanm	0:9b334a45a8ff	1069	{
bogdanm	0:9b334a45a8ff	1070	uint32_t pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
bogdanm	0:9b334a45a8ff	1071	uint32_t sysclockfreq = 0;
bogdanm	0:9b334a45a8ff	1072
bogdanm	0:9b334a45a8ff	1073	/* Get SYSCLK source -------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1074
bogdanm	0:9b334a45a8ff	1075	/MSI frequency range in HZ/
bogdanm	0:9b334a45a8ff	1076	msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
bogdanm	0:9b334a45a8ff	1077
bogdanm	0:9b334a45a8ff	1078	switch (RCC->CFGR & RCC_CFGR_SWS)
bogdanm	0:9b334a45a8ff	1079	{
bogdanm	0:9b334a45a8ff	1080	case RCC_CFGR_SWS_MSI: /* MSI used as system clock */
bogdanm	0:9b334a45a8ff	1081	{
bogdanm	0:9b334a45a8ff	1082	sysclockfreq = (32768 * (1 << (msirange + 1)));
bogdanm	0:9b334a45a8ff	1083	break;
bogdanm	0:9b334a45a8ff	1084	}
bogdanm	0:9b334a45a8ff	1085	case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock */
bogdanm	0:9b334a45a8ff	1086	{
bogdanm	0:9b334a45a8ff	1087	if ((RCC->CR & RCC_CR_HSIDIVF) != 0)
bogdanm	0:9b334a45a8ff	1088	{
bogdanm	0:9b334a45a8ff	1089	sysclockfreq = (HSI_VALUE >> 2);
bogdanm	0:9b334a45a8ff	1090	}
bogdanm	0:9b334a45a8ff	1091	else
bogdanm	0:9b334a45a8ff	1092	{
bogdanm	0:9b334a45a8ff	1093	sysclockfreq = HSI_VALUE;
bogdanm	0:9b334a45a8ff	1094	}
bogdanm	0:9b334a45a8ff	1095	break;
bogdanm	0:9b334a45a8ff	1096	}
bogdanm	0:9b334a45a8ff	1097	case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
bogdanm	0:9b334a45a8ff	1098	{
bogdanm	0:9b334a45a8ff	1099	sysclockfreq = HSE_VALUE;
bogdanm	0:9b334a45a8ff	1100	break;
bogdanm	0:9b334a45a8ff	1101	}
bogdanm	0:9b334a45a8ff	1102	case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
bogdanm	0:9b334a45a8ff	1103	{
bogdanm	0:9b334a45a8ff	1104	/* Get PLL clock source and multiplication factor ----------------------*/
bogdanm	0:9b334a45a8ff	1105	pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
bogdanm	0:9b334a45a8ff	1106	plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
bogdanm	0:9b334a45a8ff	1107	pllmul = PLLMulTable[(pllmul >> 18)];
bogdanm	0:9b334a45a8ff	1108	plldiv = (plldiv >> 22) + 1;
bogdanm	0:9b334a45a8ff	1109
bogdanm	0:9b334a45a8ff	1110	pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
bogdanm	0:9b334a45a8ff	1111
bogdanm	0:9b334a45a8ff	1112	if (pllsource == RCC_CFGR_PLLSRC_HSI)
bogdanm	0:9b334a45a8ff	1113	{
bogdanm	0:9b334a45a8ff	1114	/* HSI oscillator clock selected as PLL clock source */
bogdanm	0:9b334a45a8ff	1115	if ((RCC->CR & RCC_CR_HSIDIVF) != 0)
bogdanm	0:9b334a45a8ff	1116	{
bogdanm	0:9b334a45a8ff	1117	sysclockfreq = (HSI_VALUE >> 2) * (pllmul / plldiv);
bogdanm	0:9b334a45a8ff	1118	}
bogdanm	0:9b334a45a8ff	1119	else
bogdanm	0:9b334a45a8ff	1120	{
bogdanm	0:9b334a45a8ff	1121	sysclockfreq =(((HSI_VALUE) * pllmul) / plldiv);
bogdanm	0:9b334a45a8ff	1122	}
bogdanm	0:9b334a45a8ff	1123	}
bogdanm	0:9b334a45a8ff	1124	else
bogdanm	0:9b334a45a8ff	1125	{
bogdanm	0:9b334a45a8ff	1126	/* HSE selected as PLL clock source */
bogdanm	0:9b334a45a8ff	1127	sysclockfreq = (((HSE_VALUE) * pllmul) / plldiv);
bogdanm	0:9b334a45a8ff	1128	}
bogdanm	0:9b334a45a8ff	1129	break;
bogdanm	0:9b334a45a8ff	1130	}
bogdanm	0:9b334a45a8ff	1131	default: /* MSI used as system clock */
bogdanm	0:9b334a45a8ff	1132	{
bogdanm	0:9b334a45a8ff	1133	sysclockfreq = (32768 * (1 << (msirange + 1)));
bogdanm	0:9b334a45a8ff	1134	break;
bogdanm	0:9b334a45a8ff	1135	}
bogdanm	0:9b334a45a8ff	1136	}
bogdanm	0:9b334a45a8ff	1137	return sysclockfreq;
bogdanm	0:9b334a45a8ff	1138	}
bogdanm	0:9b334a45a8ff	1139
bogdanm	0:9b334a45a8ff	1140	/**
bogdanm	0:9b334a45a8ff	1141	* @brief Returns the HCLK frequency
bogdanm	0:9b334a45a8ff	1142	* @note Each time HCLK changes, this function must be called to update the
bogdanm	0:9b334a45a8ff	1143	* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm	0:9b334a45a8ff	1144	*
bogdanm	0:9b334a45a8ff	1145	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
bogdanm	0:9b334a45a8ff	1146	* and updated within this function
bogdanm	0:9b334a45a8ff	1147	* @param None
bogdanm	0:9b334a45a8ff	1148	* @retval HCLK frequency
bogdanm	0:9b334a45a8ff	1149	*/
bogdanm	0:9b334a45a8ff	1150	uint32_t HAL_RCC_GetHCLKFreq(void)
bogdanm	0:9b334a45a8ff	1151	{
bogdanm	0:9b334a45a8ff	1152	SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	return (SystemCoreClock);
bogdanm	0:9b334a45a8ff	1155
bogdanm	0:9b334a45a8ff	1156	}
bogdanm	0:9b334a45a8ff	1157
bogdanm	0:9b334a45a8ff	1158	/**
bogdanm	0:9b334a45a8ff	1159	* @brief Returns the PCLK1 frequency
bogdanm	0:9b334a45a8ff	1160	* @note Each time PCLK1 changes, this function must be called to update the
bogdanm	0:9b334a45a8ff	1161	* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
bogdanm	0:9b334a45a8ff	1162	* @param None
bogdanm	0:9b334a45a8ff	1163	* @retval PCLK1 frequency
bogdanm	0:9b334a45a8ff	1164	*/
bogdanm	0:9b334a45a8ff	1165	uint32_t HAL_RCC_GetPCLK1Freq(void)
bogdanm	0:9b334a45a8ff	1166	{
bogdanm	0:9b334a45a8ff	1167
bogdanm	0:9b334a45a8ff	1168	return ( HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE1) >> 8)]);
bogdanm	0:9b334a45a8ff	1169
bogdanm	0:9b334a45a8ff	1170	}
bogdanm	0:9b334a45a8ff	1171
bogdanm	0:9b334a45a8ff	1172	/**
bogdanm	0:9b334a45a8ff	1173	* @brief Returns the PCLK2 frequency
bogdanm	0:9b334a45a8ff	1174	* @note Each time PCLK2 changes, this function must be called to update the
bogdanm	0:9b334a45a8ff	1175	* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
bogdanm	0:9b334a45a8ff	1176	* @param None
bogdanm	0:9b334a45a8ff	1177	* @retval PCLK2 frequency
bogdanm	0:9b334a45a8ff	1178	*/
bogdanm	0:9b334a45a8ff	1179	uint32_t HAL_RCC_GetPCLK2Freq(void)
bogdanm	0:9b334a45a8ff	1180	{
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	return ( HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE2) >> 11)]);
bogdanm	0:9b334a45a8ff	1183
bogdanm	0:9b334a45a8ff	1184	}
bogdanm	0:9b334a45a8ff	1185
bogdanm	0:9b334a45a8ff	1186	/**
bogdanm	0:9b334a45a8ff	1187	* @brief Configures the RCC_OscInitStruct according to the internal
bogdanm	0:9b334a45a8ff	1188	* RCC configuration registers.
bogdanm	0:9b334a45a8ff	1189	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm	0:9b334a45a8ff	1190	* will be configured.
bogdanm	0:9b334a45a8ff	1191	* @retval None
bogdanm	0:9b334a45a8ff	1192	*/
bogdanm	0:9b334a45a8ff	1193	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm	0:9b334a45a8ff	1194	{
bogdanm	0:9b334a45a8ff	1195	/* Set all possible values for the Oscillator type parameter ---------------*/
bogdanm	0:9b334a45a8ff	1196	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_MSI \| RCC_OSCILLATORTYPE_HSI \| \
bogdanm	0:9b334a45a8ff	1197	RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
bogdanm	0:9b334a45a8ff	1198	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1199	RCC_OscInitStruct->OscillatorType \|= RCC_OSCILLATORTYPE_HSI48;
bogdanm	0:9b334a45a8ff	1200	#endif
bogdanm	0:9b334a45a8ff	1201
bogdanm	0:9b334a45a8ff	1202	/* Get the HSE configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1203	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
bogdanm	0:9b334a45a8ff	1204	{
bogdanm	0:9b334a45a8ff	1205	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
bogdanm	0:9b334a45a8ff	1206	}
bogdanm	0:9b334a45a8ff	1207	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
bogdanm	0:9b334a45a8ff	1208	{
bogdanm	0:9b334a45a8ff	1209	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
bogdanm	0:9b334a45a8ff	1210	}
bogdanm	0:9b334a45a8ff	1211	else
bogdanm	0:9b334a45a8ff	1212	{
bogdanm	0:9b334a45a8ff	1213	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
bogdanm	0:9b334a45a8ff	1214	}
bogdanm	0:9b334a45a8ff	1215
bogdanm	0:9b334a45a8ff	1216	/* Get the MSI configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1217	if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION)
bogdanm	0:9b334a45a8ff	1218	{
bogdanm	0:9b334a45a8ff	1219	RCC_OscInitStruct->MSIState = RCC_MSI_ON;
bogdanm	0:9b334a45a8ff	1220	}
bogdanm	0:9b334a45a8ff	1221	else
bogdanm	0:9b334a45a8ff	1222	{
bogdanm	0:9b334a45a8ff	1223	RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
bogdanm	0:9b334a45a8ff	1224	}
bogdanm	0:9b334a45a8ff	1225
bogdanm	0:9b334a45a8ff	1226	RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR &RCC_ICSCR_MSITRIM) >> 24);
bogdanm	0:9b334a45a8ff	1227	RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR &RCC_ICSCR_MSIRANGE) >> 13);
bogdanm	0:9b334a45a8ff	1228
bogdanm	0:9b334a45a8ff	1229	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1230	/* Get the HSI48 configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1231	if((RCC->CRRCR &RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
bogdanm	0:9b334a45a8ff	1232	{
bogdanm	0:9b334a45a8ff	1233	RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
bogdanm	0:9b334a45a8ff	1234	}
bogdanm	0:9b334a45a8ff	1235	else
bogdanm	0:9b334a45a8ff	1236	{
bogdanm	0:9b334a45a8ff	1237	RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
bogdanm	0:9b334a45a8ff	1238	}
bogdanm	0:9b334a45a8ff	1239	#endif
bogdanm	0:9b334a45a8ff	1240
bogdanm	0:9b334a45a8ff	1241	/* Get the HSI configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1242	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	1243	{
bogdanm	0:9b334a45a8ff	1244	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
bogdanm	0:9b334a45a8ff	1245	}
bogdanm	0:9b334a45a8ff	1246	else
bogdanm	0:9b334a45a8ff	1247	{
bogdanm	0:9b334a45a8ff	1248	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
bogdanm	0:9b334a45a8ff	1249	}
bogdanm	0:9b334a45a8ff	1250
bogdanm	0:9b334a45a8ff	1251	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR &RCC_ICSCR_HSITRIM) >> 8);
bogdanm	0:9b334a45a8ff	1252
bogdanm	0:9b334a45a8ff	1253	/* Get the LSE configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1254	if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP)
bogdanm	0:9b334a45a8ff	1255	{
bogdanm	0:9b334a45a8ff	1256	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
bogdanm	0:9b334a45a8ff	1257	}
bogdanm	0:9b334a45a8ff	1258	else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON)
bogdanm	0:9b334a45a8ff	1259	{
bogdanm	0:9b334a45a8ff	1260	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
bogdanm	0:9b334a45a8ff	1261	}
bogdanm	0:9b334a45a8ff	1262	else
bogdanm	0:9b334a45a8ff	1263	{
bogdanm	0:9b334a45a8ff	1264	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
bogdanm	0:9b334a45a8ff	1265	}
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267	/* Get the LSI configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1268	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	1269	{
bogdanm	0:9b334a45a8ff	1270	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
bogdanm	0:9b334a45a8ff	1271	}
bogdanm	0:9b334a45a8ff	1272	else
bogdanm	0:9b334a45a8ff	1273	{
bogdanm	0:9b334a45a8ff	1274	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
bogdanm	0:9b334a45a8ff	1275	}
bogdanm	0:9b334a45a8ff	1276
bogdanm	0:9b334a45a8ff	1277	/* Get the PLL configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1278	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	1279	{
bogdanm	0:9b334a45a8ff	1280	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
bogdanm	0:9b334a45a8ff	1281	}
bogdanm	0:9b334a45a8ff	1282	else
bogdanm	0:9b334a45a8ff	1283	{
bogdanm	0:9b334a45a8ff	1284	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
bogdanm	0:9b334a45a8ff	1285	}
bogdanm	0:9b334a45a8ff	1286	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
bogdanm	0:9b334a45a8ff	1287	RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL) >> 18;
bogdanm	0:9b334a45a8ff	1288	RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV) >> 22;
bogdanm	0:9b334a45a8ff	1289
bogdanm	0:9b334a45a8ff	1290	}
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	/**
bogdanm	0:9b334a45a8ff	1293	* @brief Configures the RCC_ClkInitStruct according to the internal
bogdanm	0:9b334a45a8ff	1294	* RCC configuration registers.
bogdanm	0:9b334a45a8ff	1295	* @param RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that
bogdanm	0:9b334a45a8ff	1296	* will be configured.
bogdanm	0:9b334a45a8ff	1297	* @param pFLatency: Pointer on the Flash Latency.
bogdanm	0:9b334a45a8ff	1298	* @retval None
bogdanm	0:9b334a45a8ff	1299	*/
bogdanm	0:9b334a45a8ff	1300	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency)
bogdanm	0:9b334a45a8ff	1301	{
bogdanm	0:9b334a45a8ff	1302	/* Set all possible values for the Clock type parameter --------------------*/
bogdanm	0:9b334a45a8ff	1303	RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2;
bogdanm	0:9b334a45a8ff	1304
bogdanm	0:9b334a45a8ff	1305	/* Get the SYSCLK configuration --------------------------------------------*/
bogdanm	0:9b334a45a8ff	1306	RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
bogdanm	0:9b334a45a8ff	1307
bogdanm	0:9b334a45a8ff	1308	/* Get the HCLK configuration ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1309	RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
bogdanm	0:9b334a45a8ff	1310
bogdanm	0:9b334a45a8ff	1311	/* Get the APB1 configuration ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1312	RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
bogdanm	0:9b334a45a8ff	1313
bogdanm	0:9b334a45a8ff	1314	/* Get the APB2 configuration ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1315	RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
bogdanm	0:9b334a45a8ff	1316
bogdanm	0:9b334a45a8ff	1317	/* Get the Flash Wait State (Latency) configuration ------------------------*/
bogdanm	0:9b334a45a8ff	1318	*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
bogdanm	0:9b334a45a8ff	1319	}
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	/**
bogdanm	0:9b334a45a8ff	1322	* @brief This function handles the RCC CSS interrupt request.
bogdanm	0:9b334a45a8ff	1323	* @note This API should be called under the NMI_Handler().
bogdanm	0:9b334a45a8ff	1324	* @param None
bogdanm	0:9b334a45a8ff	1325	* @retval None
bogdanm	0:9b334a45a8ff	1326	*/
bogdanm	0:9b334a45a8ff	1327	void HAL_RCC_NMI_IRQHandler(void)
bogdanm	0:9b334a45a8ff	1328	{
bogdanm	0:9b334a45a8ff	1329	/* Check RCC CSSF flag */
bogdanm	0:9b334a45a8ff	1330	if(__HAL_RCC_GET_IT_SOURCE(RCC_IT_CSS))
bogdanm	0:9b334a45a8ff	1331	{
bogdanm	0:9b334a45a8ff	1332	/* RCC Clock Security System interrupt user callback */
bogdanm	0:9b334a45a8ff	1333	HAL_RCC_CSSCallback();
bogdanm	0:9b334a45a8ff	1334
bogdanm	0:9b334a45a8ff	1335	/* Clear RCC CSS pending bit */
bogdanm	0:9b334a45a8ff	1336	__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
bogdanm	0:9b334a45a8ff	1337	}
bogdanm	0:9b334a45a8ff	1338	}
bogdanm	0:9b334a45a8ff	1339
bogdanm	0:9b334a45a8ff	1340	/**
bogdanm	0:9b334a45a8ff	1341	* @brief RCC Clock Security System interrupt callback
bogdanm	0:9b334a45a8ff	1342	* @param none
bogdanm	0:9b334a45a8ff	1343	* @retval none
bogdanm	0:9b334a45a8ff	1344	*/
bogdanm	0:9b334a45a8ff	1345	__weak void HAL_RCC_CSSCallback(void)
bogdanm	0:9b334a45a8ff	1346	{
bogdanm	0:9b334a45a8ff	1347	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1348	the HAL_RCC_CSSCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1349	*/
bogdanm	0:9b334a45a8ff	1350	}
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	/**
bogdanm	0:9b334a45a8ff	1353	* @}
bogdanm	0:9b334a45a8ff	1354	*/
bogdanm	0:9b334a45a8ff	1355
bogdanm	0:9b334a45a8ff	1356	/**
bogdanm	0:9b334a45a8ff	1357	* @}
bogdanm	0:9b334a45a8ff	1358	*/
bogdanm	0:9b334a45a8ff	1359
bogdanm	0:9b334a45a8ff	1360	#endif /* HAL_RCC_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1361	/**
bogdanm	0:9b334a45a8ff	1362	* @}
bogdanm	0:9b334a45a8ff	1363	*/
bogdanm	0:9b334a45a8ff	1364
bogdanm	0:9b334a45a8ff	1365	/**
bogdanm	0:9b334a45a8ff	1366	* @}
bogdanm	0:9b334a45a8ff	1367	*/
bogdanm	0:9b334a45a8ff	1368
bogdanm	0:9b334a45a8ff	1369	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	1370

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c@0:9b334a45a8ff, 2015-10-01 (annotated)

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