en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
113:b3775bf36a83
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

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bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l0xx_hal_pwr.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.2.0
bogdanm 0:9b334a45a8ff 6 * @date 06-February-2015
bogdanm 0:9b334a45a8ff 7 * @brief Header file of PWR HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32L0xx_HAL_PWR_H
bogdanm 0:9b334a45a8ff 40 #define __STM32L0xx_HAL_PWR_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32l0xx_hal_def.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @defgroup PWR
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /** @defgroup PWR_Exported_Types PWR Exported Types
bogdanm 0:9b334a45a8ff 58 * @{
bogdanm 0:9b334a45a8ff 59 */
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 /**
bogdanm 0:9b334a45a8ff 62 * @brief PWR PVD configuration structure definition
bogdanm 0:9b334a45a8ff 63 */
bogdanm 0:9b334a45a8ff 64 typedef struct
bogdanm 0:9b334a45a8ff 65 {
bogdanm 0:9b334a45a8ff 66 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
bogdanm 0:9b334a45a8ff 67 This parameter can be a value of @ref PWR_PVD_detection_level */
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
bogdanm 0:9b334a45a8ff 70 This parameter can be a value of @ref PWR_PVD_Mode */
bogdanm 0:9b334a45a8ff 71 }PWR_PVDTypeDef;
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 /**
bogdanm 0:9b334a45a8ff 74 * @}
bogdanm 0:9b334a45a8ff 75 */
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 /** @defgroup PWR_Private_Defines PWR Private Defines
bogdanm 0:9b334a45a8ff 78 * @{
bogdanm 0:9b334a45a8ff 79 */
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 #define PWR_EXTI_LINE_PVD EXTI_FTSR_TR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 /**
bogdanm 0:9b334a45a8ff 84 * @}
bogdanm 0:9b334a45a8ff 85 */
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 /** @defgroup PWR_Exported_Constants PWR Exported Constants
bogdanm 0:9b334a45a8ff 88 * @{
bogdanm 0:9b334a45a8ff 89 */
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 /** @defgroup PWR_register_alias_address PWR Register alias address
bogdanm 0:9b334a45a8ff 92 * @{
bogdanm 0:9b334a45a8ff 93 */
bogdanm 0:9b334a45a8ff 94 #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1
bogdanm 0:9b334a45a8ff 95 #define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2
bogdanm 0:9b334a45a8ff 96 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
bogdanm 0:9b334a45a8ff 97 #define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3
bogdanm 0:9b334a45a8ff 98 #endif
bogdanm 0:9b334a45a8ff 99 /**
bogdanm 0:9b334a45a8ff 100 * @}
bogdanm 0:9b334a45a8ff 101 */
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /** @defgroup PWR_PVD_detection_level PVD detection level
bogdanm 0:9b334a45a8ff 104 * @{
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
bogdanm 0:9b334a45a8ff 107 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
bogdanm 0:9b334a45a8ff 108 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
bogdanm 0:9b334a45a8ff 109 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
bogdanm 0:9b334a45a8ff 110 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
bogdanm 0:9b334a45a8ff 111 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
bogdanm 0:9b334a45a8ff 112 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
bogdanm 0:9b334a45a8ff 113 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage
bogdanm 0:9b334a45a8ff 114 (Compare internally to VREFINT) */
bogdanm 0:9b334a45a8ff 115 /**
bogdanm 0:9b334a45a8ff 116 * @}
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 /** @defgroup PWR_PVD_Mode PWR PVD Mode
bogdanm 0:9b334a45a8ff 120 * @{
bogdanm 0:9b334a45a8ff 121 */
bogdanm 0:9b334a45a8ff 122 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
bogdanm 0:9b334a45a8ff 123 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
bogdanm 0:9b334a45a8ff 124 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
bogdanm 0:9b334a45a8ff 125 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
bogdanm 0:9b334a45a8ff 126 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
bogdanm 0:9b334a45a8ff 127 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
bogdanm 0:9b334a45a8ff 128 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /**
bogdanm 0:9b334a45a8ff 131 * @}
bogdanm 0:9b334a45a8ff 132 */
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
bogdanm 0:9b334a45a8ff 135 * @{
bogdanm 0:9b334a45a8ff 136 */
bogdanm 0:9b334a45a8ff 137 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 138 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 /**
bogdanm 0:9b334a45a8ff 141 * @}
bogdanm 0:9b334a45a8ff 142 */
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
bogdanm 0:9b334a45a8ff 145 * @{
bogdanm 0:9b334a45a8ff 146 */
bogdanm 0:9b334a45a8ff 147 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 148 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
bogdanm 0:9b334a45a8ff 149 /**
bogdanm 0:9b334a45a8ff 150 * @}
bogdanm 0:9b334a45a8ff 151 */
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
bogdanm 0:9b334a45a8ff 154 * @{
bogdanm 0:9b334a45a8ff 155 */
bogdanm 0:9b334a45a8ff 156 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 157 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
bogdanm 0:9b334a45a8ff 158 /**
bogdanm 0:9b334a45a8ff 159 * @}
bogdanm 0:9b334a45a8ff 160 */
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
bogdanm 0:9b334a45a8ff 163 * @{
bogdanm 0:9b334a45a8ff 164 */
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0
bogdanm 0:9b334a45a8ff 167 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1
bogdanm 0:9b334a45a8ff 168 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
bogdanm 0:9b334a45a8ff 171 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
bogdanm 0:9b334a45a8ff 172 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
bogdanm 0:9b334a45a8ff 173 /**
bogdanm 0:9b334a45a8ff 174 * @}
bogdanm 0:9b334a45a8ff 175 */
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 /** @defgroup PWR_Flag PWR Flag
bogdanm 0:9b334a45a8ff 178 * @{
bogdanm 0:9b334a45a8ff 179 */
bogdanm 0:9b334a45a8ff 180 #define PWR_FLAG_WU PWR_CSR_WUF
bogdanm 0:9b334a45a8ff 181 #define PWR_FLAG_SB PWR_CSR_SBF
bogdanm 0:9b334a45a8ff 182 #define PWR_FLAG_PVDO PWR_CSR_PVDO
bogdanm 0:9b334a45a8ff 183 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
bogdanm 0:9b334a45a8ff 184 #define PWR_FLAG_VOS PWR_CSR_VOSF
bogdanm 0:9b334a45a8ff 185 #define PWR_FLAG_REGLP PWR_CSR_REGLPF
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
bogdanm 0:9b334a45a8ff 188 ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \
bogdanm 0:9b334a45a8ff 189 ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))
bogdanm 0:9b334a45a8ff 190 /**
bogdanm 0:9b334a45a8ff 191 * @}
bogdanm 0:9b334a45a8ff 192 */
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /**
bogdanm 0:9b334a45a8ff 195 * @}
bogdanm 0:9b334a45a8ff 196 */
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 /** @defgroup PWR_Exported_Macro PWR Exported Macro
bogdanm 0:9b334a45a8ff 199 * @{
bogdanm 0:9b334a45a8ff 200 */
bogdanm 0:9b334a45a8ff 201 /** @brief macros configure the main internal regulator output voltage.
bogdanm 0:9b334a45a8ff 202 * @param __REGULATOR__: specifies the regulator output voltage to achieve
bogdanm 0:9b334a45a8ff 203 * a tradeoff between performance and power consumption when the device does
bogdanm 0:9b334a45a8ff 204 * not operate at the maximum frequency (refer to the datasheets for more details).
bogdanm 0:9b334a45a8ff 205 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 206 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
bogdanm 0:9b334a45a8ff 207 * System frequency up to 32 MHz.
bogdanm 0:9b334a45a8ff 208 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
bogdanm 0:9b334a45a8ff 209 * System frequency up to 16 MHz.
bogdanm 0:9b334a45a8ff 210 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
bogdanm 0:9b334a45a8ff 211 * System frequency up to 4.2 MHz
bogdanm 0:9b334a45a8ff 212 * @retval None
bogdanm 0:9b334a45a8ff 213 */
bogdanm 0:9b334a45a8ff 214 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /** @brief Check PWR flag is set or not.
bogdanm 0:9b334a45a8ff 217 * @param __FLAG__: specifies the flag to check.
bogdanm 0:9b334a45a8ff 218 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 219 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
bogdanm 0:9b334a45a8ff 220 * was received from the WKUP pin or from the RTC alarm (Alarm B),
bogdanm 0:9b334a45a8ff 221 * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
bogdanm 0:9b334a45a8ff 222 * An additional wakeup event is detected if the WKUP pin is enabled
bogdanm 0:9b334a45a8ff 223 * (by setting the EWUP bit) when the WKUP pin level is already high.
bogdanm 0:9b334a45a8ff 224 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
bogdanm 0:9b334a45a8ff 225 * resumed from StandBy mode.
bogdanm 0:9b334a45a8ff 226 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
bogdanm 0:9b334a45a8ff 227 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
bogdanm 0:9b334a45a8ff 228 * For this reason, this bit is equal to 0 after Standby or reset
bogdanm 0:9b334a45a8ff 229 * until the PVDE bit is set.
bogdanm 0:9b334a45a8ff 230 * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
bogdanm 0:9b334a45a8ff 231 * This bit indicates the state of the internal voltage reference, VREFINT.
bogdanm 0:9b334a45a8ff 232 * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
bogdanm 0:9b334a45a8ff 233 * the internal regulator to be ready after the voltage range is changed.
bogdanm 0:9b334a45a8ff 234 * The VOSF bit indicates that the regulator has reached the voltage level
bogdanm 0:9b334a45a8ff 235 * defined with bits VOS of PWR_CR register.
bogdanm 0:9b334a45a8ff 236 * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
bogdanm 0:9b334a45a8ff 237 * mode, this bit stays at 1 until the regulator is ready in main mode.
bogdanm 0:9b334a45a8ff 238 * A polling on this bit is recommended to wait for the regulator main mode.
bogdanm 0:9b334a45a8ff 239 * This bit is reset by hardware when the regulator is ready.
bogdanm 0:9b334a45a8ff 240 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 0:9b334a45a8ff 241 */
bogdanm 0:9b334a45a8ff 242 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 /** @brief Clear the PWR's pending flags.
bogdanm 0:9b334a45a8ff 245 * @param __FLAG__: specifies the flag to clear.
bogdanm 0:9b334a45a8ff 246 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 247 * @arg PWR_FLAG_WU: Wake Up flag
bogdanm 0:9b334a45a8ff 248 * @arg PWR_FLAG_SB: StandBy flag
bogdanm 0:9b334a45a8ff 249 */
bogdanm 0:9b334a45a8ff 250 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2)
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 /**
bogdanm 0:9b334a45a8ff 253 * @brief Enable interrupt on PVD Exti Line 16.
bogdanm 0:9b334a45a8ff 254 * @retval None.
bogdanm 0:9b334a45a8ff 255 */
bogdanm 0:9b334a45a8ff 256 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /**
bogdanm 0:9b334a45a8ff 259 * @brief Disable interrupt on PVD Exti Line 16.
bogdanm 0:9b334a45a8ff 260 * @retval None.
bogdanm 0:9b334a45a8ff 261 */
bogdanm 0:9b334a45a8ff 262 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 263
bogdanm 0:9b334a45a8ff 264 /**
bogdanm 0:9b334a45a8ff 265 * @brief Enable event on PVD Exti Line 16.
bogdanm 0:9b334a45a8ff 266 * @retval None.
bogdanm 0:9b334a45a8ff 267 */
bogdanm 0:9b334a45a8ff 268 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 /**
bogdanm 0:9b334a45a8ff 271 * @brief Disable event on PVD Exti Line 16.
bogdanm 0:9b334a45a8ff 272 * @retval None.
bogdanm 0:9b334a45a8ff 273 */
bogdanm 0:9b334a45a8ff 274 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 /**
bogdanm 0:9b334a45a8ff 278 * @brief PVD EXTI line configuration: set falling edge trigger.
bogdanm 0:9b334a45a8ff 279 * @retval None.
bogdanm 0:9b334a45a8ff 280 */
bogdanm 0:9b334a45a8ff 281 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /**
bogdanm 0:9b334a45a8ff 285 * @brief Disable the PVD Extended Interrupt Falling Trigger.
bogdanm 0:9b334a45a8ff 286 * @retval None.
bogdanm 0:9b334a45a8ff 287 */
bogdanm 0:9b334a45a8ff 288 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /**
bogdanm 0:9b334a45a8ff 292 * @brief PVD EXTI line configuration: set rising edge trigger.
bogdanm 0:9b334a45a8ff 293 * @retval None.
bogdanm 0:9b334a45a8ff 294 */
bogdanm 0:9b334a45a8ff 295 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /**
bogdanm 0:9b334a45a8ff 298 * @brief Disable the PVD Extended Interrupt Rising Trigger.
bogdanm 0:9b334a45a8ff 299 * This parameter can be:
bogdanm 0:9b334a45a8ff 300 * @retval None.
bogdanm 0:9b334a45a8ff 301 */
bogdanm 0:9b334a45a8ff 302 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 /**
bogdanm 0:9b334a45a8ff 305 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
bogdanm 0:9b334a45a8ff 306 * @retval None.
bogdanm 0:9b334a45a8ff 307 */
bogdanm 0:9b334a45a8ff 308 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 /**
bogdanm 0:9b334a45a8ff 311 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
bogdanm 0:9b334a45a8ff 312 * This parameter can be:
bogdanm 0:9b334a45a8ff 313 * @retval None.
bogdanm 0:9b334a45a8ff 314 */
bogdanm 0:9b334a45a8ff 315 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()();
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318
bogdanm 0:9b334a45a8ff 319 /**
bogdanm 0:9b334a45a8ff 320 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
bogdanm 0:9b334a45a8ff 321 * @retval EXTI PVD Line Status.
bogdanm 0:9b334a45a8ff 322 */
bogdanm 0:9b334a45a8ff 323 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 /**
bogdanm 0:9b334a45a8ff 326 * @brief Clear the PVD EXTI flag.
bogdanm 0:9b334a45a8ff 327 * @retval None.
bogdanm 0:9b334a45a8ff 328 */
bogdanm 0:9b334a45a8ff 329 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /**
bogdanm 0:9b334a45a8ff 332 * @brief Generate a Software interrupt on selected EXTI line.
bogdanm 0:9b334a45a8ff 333 * @retval None.
bogdanm 0:9b334a45a8ff 334 */
bogdanm 0:9b334a45a8ff 335 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 336 /**
bogdanm 0:9b334a45a8ff 337 * @}
bogdanm 0:9b334a45a8ff 338 */
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 /**
bogdanm 0:9b334a45a8ff 341 * @brief Generate a Software interrupt on selected EXTI line.
bogdanm 0:9b334a45a8ff 342 * @retval None.
bogdanm 0:9b334a45a8ff 343 */
bogdanm 0:9b334a45a8ff 344 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 /**
bogdanm 0:9b334a45a8ff 347 * @}
bogdanm 0:9b334a45a8ff 348 */
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350 /** @defgroup PWR_Private_Macros PWR Private Macros
bogdanm 0:9b334a45a8ff 351 * @{
bogdanm 0:9b334a45a8ff 352 */
bogdanm 0:9b334a45a8ff 353 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
bogdanm 0:9b334a45a8ff 354 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
bogdanm 0:9b334a45a8ff 355 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
bogdanm 0:9b334a45a8ff 356 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
bogdanm 0:9b334a45a8ff 359 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
bogdanm 0:9b334a45a8ff 360 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
bogdanm 0:9b334a45a8ff 361 ((MODE) == PWR_PVD_MODE_NORMAL))
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
bogdanm 0:9b334a45a8ff 364 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
bogdanm 0:9b334a45a8ff 365 ((PIN) == PWR_WAKEUP_PIN2) || \
bogdanm 0:9b334a45a8ff 366 ((PIN) == PWR_WAKEUP_PIN3))
bogdanm 0:9b334a45a8ff 367 #else
bogdanm 0:9b334a45a8ff 368 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
bogdanm 0:9b334a45a8ff 369 ((PIN) == PWR_WAKEUP_PIN2))
bogdanm 0:9b334a45a8ff 370 #endif
bogdanm 0:9b334a45a8ff 371
bogdanm 0:9b334a45a8ff 372 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
bogdanm 0:9b334a45a8ff 373 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
bogdanm 0:9b334a45a8ff 374 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378 /**
bogdanm 0:9b334a45a8ff 379 * @}
bogdanm 0:9b334a45a8ff 380 */
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /* Include PWR HAL Extension module */
bogdanm 0:9b334a45a8ff 383 #include "stm32l0xx_hal_pwr_ex.h"
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 /** @defgroup PWR_Exported_Functions PWR Exported Functions
bogdanm 0:9b334a45a8ff 386 * @{
bogdanm 0:9b334a45a8ff 387 */
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 390 * @{
bogdanm 0:9b334a45a8ff 391 */
bogdanm 0:9b334a45a8ff 392 void HAL_PWR_DeInit(void);
bogdanm 0:9b334a45a8ff 393 void HAL_PWR_EnableBkUpAccess(void);
bogdanm 0:9b334a45a8ff 394 void HAL_PWR_DisableBkUpAccess(void);
bogdanm 0:9b334a45a8ff 395 /**
bogdanm 0:9b334a45a8ff 396 * @}
bogdanm 0:9b334a45a8ff 397 */
bogdanm 0:9b334a45a8ff 398
bogdanm 0:9b334a45a8ff 399 /** @defgroup PWR_Exported_Functions_Group2 Low Power modes configuration functions
bogdanm 0:9b334a45a8ff 400 * @{
bogdanm 0:9b334a45a8ff 401 */
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 /* PVD control functions ************************************************/
bogdanm 0:9b334a45a8ff 404 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
bogdanm 0:9b334a45a8ff 405 void HAL_PWR_EnablePVD(void);
bogdanm 0:9b334a45a8ff 406 void HAL_PWR_DisablePVD(void);
bogdanm 0:9b334a45a8ff 407 void HAL_PWR_PVD_IRQHandler(void);
bogdanm 0:9b334a45a8ff 408 void HAL_PWR_PVDCallback(void);
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /* WakeUp pins configuration functions ****************************************/
bogdanm 0:9b334a45a8ff 411 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
bogdanm 0:9b334a45a8ff 412 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /* Low Power modes configuration functions ************************************/
bogdanm 0:9b334a45a8ff 415 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
bogdanm 0:9b334a45a8ff 416 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
bogdanm 0:9b334a45a8ff 417 void HAL_PWR_EnterSTANDBYMode(void);
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 void HAL_PWR_EnableSleepOnExit(void);
bogdanm 0:9b334a45a8ff 420 void HAL_PWR_DisableSleepOnExit(void);
bogdanm 0:9b334a45a8ff 421 void HAL_PWR_EnableSEVOnPend(void);
bogdanm 0:9b334a45a8ff 422 void HAL_PWR_DisableSEVOnPend(void);
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /**
bogdanm 0:9b334a45a8ff 425 * @}
bogdanm 0:9b334a45a8ff 426 */
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 /**
bogdanm 0:9b334a45a8ff 429 * @}
bogdanm 0:9b334a45a8ff 430 */
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /**
bogdanm 0:9b334a45a8ff 433 * @}
bogdanm 0:9b334a45a8ff 434 */
bogdanm 0:9b334a45a8ff 435
bogdanm 0:9b334a45a8ff 436 /**
bogdanm 0:9b334a45a8ff 437 * @}
bogdanm 0:9b334a45a8ff 438 */
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 441 }
bogdanm 0:9b334a45a8ff 442 #endif
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444
bogdanm 0:9b334a45a8ff 445 #endif /* __STM32L0xx_HAL_PWR_H */
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bogdanm 0:9b334a45a8ff 448