mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 113:b3775bf36a83

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l0xx_hal_adc.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.2.0
bogdanm	0:9b334a45a8ff	6	* @date 06-February-2015
bogdanm	0:9b334a45a8ff	7	* @brief This file contains all the functions prototypes for the ADC firmware
bogdanm	0:9b334a45a8ff	8	* library.
bogdanm	0:9b334a45a8ff	9	******************************************************************************
bogdanm	0:9b334a45a8ff	10	* @attention
bogdanm	0:9b334a45a8ff	11	*
bogdanm	0:9b334a45a8ff	12	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	13	*
bogdanm	0:9b334a45a8ff	14	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	15	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	16	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	17	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	19	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	20	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	22	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	23	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	24	*
bogdanm	0:9b334a45a8ff	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	35	*
bogdanm	0:9b334a45a8ff	36	******************************************************************************
bogdanm	0:9b334a45a8ff	37	*/
bogdanm	0:9b334a45a8ff	38
bogdanm	0:9b334a45a8ff	39	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	40	#ifndef __STM32L0xx_ADC_H
bogdanm	0:9b334a45a8ff	41	#define __STM32L0xx_ADC_H
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	44	extern "C" {
bogdanm	0:9b334a45a8ff	45	#endif
bogdanm	0:9b334a45a8ff	46
bogdanm	0:9b334a45a8ff	47	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	48	#include "stm32l0xx_hal_def.h"
bogdanm	0:9b334a45a8ff	49
bogdanm	0:9b334a45a8ff	50	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	51	* @{
bogdanm	0:9b334a45a8ff	52	*/
bogdanm	0:9b334a45a8ff	53
bogdanm	0:9b334a45a8ff	54	/** @addtogroup ADC
bogdanm	0:9b334a45a8ff	55	* @{
bogdanm	0:9b334a45a8ff	56	*/
bogdanm	0:9b334a45a8ff	57
bogdanm	0:9b334a45a8ff	58	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	59	/**
bogdanm	0:9b334a45a8ff	60	* @brief HAL State structures definition
bogdanm	0:9b334a45a8ff	61	*/
bogdanm	0:9b334a45a8ff	62	typedef enum
bogdanm	0:9b334a45a8ff	63	{
bogdanm	0:9b334a45a8ff	64	HAL_ADC_STATE_RESET = 0x00, /!< ADC not yet initialized or disabled /
bogdanm	0:9b334a45a8ff	65	HAL_ADC_STATE_READY = 0x01, /!< ADC peripheral ready for use /
bogdanm	0:9b334a45a8ff	66	HAL_ADC_STATE_BUSY = 0x02, /!< An internal process is ongoing /
bogdanm	0:9b334a45a8ff	67	HAL_ADC_STATE_BUSY_REG = 0x12, /!< Regular conversion is ongoing /
bogdanm	0:9b334a45a8ff	68	HAL_ADC_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	0:9b334a45a8ff	69	HAL_ADC_STATE_ERROR = 0x04, /!< ADC state error /
bogdanm	0:9b334a45a8ff	70	HAL_ADC_STATE_EOC = 0x05, /!< Conversion is completed /
bogdanm	0:9b334a45a8ff	71	HAL_ADC_STATE_AWD = 0x06, /!< ADC state analog watchdog /
bogdanm	0:9b334a45a8ff	72	}HAL_ADC_StateTypeDef;
bogdanm	0:9b334a45a8ff	73
bogdanm	0:9b334a45a8ff	74
bogdanm	0:9b334a45a8ff	75	/**
bogdanm	0:9b334a45a8ff	76	* @brief ADC Oversampler structure definition
bogdanm	0:9b334a45a8ff	77	*/
bogdanm	0:9b334a45a8ff	78	typedef struct
bogdanm	0:9b334a45a8ff	79	{
bogdanm	0:9b334a45a8ff	80	uint32_t Ratio; /*!< Configures the oversampling ratio.
bogdanm	0:9b334a45a8ff	81	This parameter can be a value of @ref ADC_Oversampling_Ratio */
bogdanm	0:9b334a45a8ff	82	uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
bogdanm	0:9b334a45a8ff	83	This parameter can be a value of @ref ADC_Right_Bit_Shift */
bogdanm	0:9b334a45a8ff	84	uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode
bogdanm	0:9b334a45a8ff	85	This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
bogdanm	0:9b334a45a8ff	86
bogdanm	0:9b334a45a8ff	87	}ADC_OversamplingTypeDef;
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	/**
bogdanm	0:9b334a45a8ff	90	* @brief ADC Init structure definition
bogdanm	0:9b334a45a8ff	91	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned by the ADC state.
bogdanm	0:9b334a45a8ff	92	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
bogdanm	0:9b334a45a8ff	93	* without error reporting (as it can be the expected behaviour in case of intended action to update antother parameter (which fullfills the ADC state condition) on the fly).
bogdanm	0:9b334a45a8ff	94	*/
bogdanm	0:9b334a45a8ff	95	typedef struct
bogdanm	0:9b334a45a8ff	96	{
bogdanm	0:9b334a45a8ff	97	uint32_t OversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled
bogdanm	0:9b334a45a8ff	98	This parameter can be set to ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	99	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	100	ADC_OversamplingTypeDef Oversample; /*!< Specifies the Oversampling parameters
bogdanm	0:9b334a45a8ff	101	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	102	uint32_t ClockPrescaler; /*!< Selects the ADC clock frequency.
bogdanm	0:9b334a45a8ff	103	This parameter can be a value of @ref ADC_ClockPrescaler
bogdanm	0:9b334a45a8ff	104	Note: This parameter can be modified only if ADC is disabled. */
bogdanm	0:9b334a45a8ff	105	uint32_t Resolution; /*!< Configures the ADC resolution mode.
bogdanm	0:9b334a45a8ff	106	This parameter can be a value of @ref ADC_Resolution
bogdanm	0:9b334a45a8ff	107	Note: This parameter can be modified only if ADC is disabled. */
bogdanm	0:9b334a45a8ff	108	uint32_t SamplingTime; /*!< The sample time value to be set for all channels.
bogdanm	0:9b334a45a8ff	109	This parameter can be a value of @ref ADC_sampling_times
bogdanm	0:9b334a45a8ff	110	Note: This parameter can be modified only if there is no conversion ongoing. */
bogdanm	0:9b334a45a8ff	111	uint32_t ScanConvMode; /*!< The scan sequence direction.
bogdanm	0:9b334a45a8ff	112	This parameter can be a value of @ref ADC_Scan_mode
bogdanm	0:9b334a45a8ff	113	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	114	uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
bogdanm	0:9b334a45a8ff	115	This parameter can be a value of @ref ADC_data_align
bogdanm	0:9b334a45a8ff	116	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	117	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
bogdanm	0:9b334a45a8ff	118	This parameter can be set to ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	119	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	120	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed
bogdanm	0:9b334a45a8ff	121	in Complete-sequence/Discontinuous-sequence.
bogdanm	0:9b334a45a8ff	122	Discontinuous mode can be enabled only if continuous mode is disabled.
bogdanm	0:9b334a45a8ff	123	This parameter can be set to ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	124	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	125	uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger.
bogdanm	0:9b334a45a8ff	126	This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge
bogdanm	0:9b334a45a8ff	127	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	128	uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion.
bogdanm	0:9b334a45a8ff	129	This parameter can be a value of @ref ADC_External_trigger_Source
bogdanm	0:9b334a45a8ff	130	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	131	uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
bogdanm	0:9b334a45a8ff	132	or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
bogdanm	0:9b334a45a8ff	133	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer max pointer is reached.
bogdanm	0:9b334a45a8ff	134	This parameter can be set to ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	135	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	136	uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion polling and interruption:
bogdanm	0:9b334a45a8ff	137	end of single channel conversion or end of channels conversions sequence.
bogdanm	0:9b334a45a8ff	138	This parameter can be a value of @ref ADC_EOCSelection */
bogdanm	0:9b334a45a8ff	139	uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten
bogdanm	0:9b334a45a8ff	140	This parameter has an effect on regular channels only, including in DMA mode.
bogdanm	0:9b334a45a8ff	141	This parameter can be a value of @ref ADC_Overrun
bogdanm	0:9b334a45a8ff	142	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	143	uint32_t LowPowerAutoWait; /*!< Specifies the usage of dynamic low power Auto Delay: new conversion start only
bogdanm	0:9b334a45a8ff	144	when the previous conversion (for regular channel) is completed.
bogdanm	0:9b334a45a8ff	145	This avoids risk of overrun for low frequency application.
bogdanm	0:9b334a45a8ff	146	This parameter can be set to ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	147	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	148	uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
bogdanm	0:9b334a45a8ff	149	it is mandatory to first enable the Low Frequency Mode.
bogdanm	0:9b334a45a8ff	150	This parameter can be set to ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	151	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	152	uint32_t LowPowerAutoPowerOff; /*!< When setting the AutoOff feature, the ADC is always powered off when not converting and automatically
bogdanm	0:9b334a45a8ff	153	wakes-up when a conversion is started (by software or hardware trigger).
bogdanm	0:9b334a45a8ff	154	This parameter can be set to ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	155	Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm	0:9b334a45a8ff	156	}ADC_InitTypeDef;
bogdanm	0:9b334a45a8ff	157
bogdanm	0:9b334a45a8ff	158	/**
bogdanm	0:9b334a45a8ff	159	* @brief ADC handle Structure definition
bogdanm	0:9b334a45a8ff	160	*/
bogdanm	0:9b334a45a8ff	161	typedef struct __ADC_HandleTypeDef
bogdanm	0:9b334a45a8ff	162	{
bogdanm	0:9b334a45a8ff	163	ADC_TypeDef Instance; /!< Register base address */
bogdanm	0:9b334a45a8ff	164
bogdanm	0:9b334a45a8ff	165	ADC_InitTypeDef Init; /!< ADC required parameters /
bogdanm	0:9b334a45a8ff	166
bogdanm	0:9b334a45a8ff	167	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	HAL_LockTypeDef Lock; /!< ADC locking object /
bogdanm	0:9b334a45a8ff	170
bogdanm	0:9b334a45a8ff	171	__IO HAL_ADC_StateTypeDef State; /!< ADC communication state /
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	__IO uint32_t ErrorCode; /!< ADC Error code /
bogdanm	0:9b334a45a8ff	174	}ADC_HandleTypeDef;
bogdanm	0:9b334a45a8ff	175
bogdanm	0:9b334a45a8ff	176	/**
bogdanm	0:9b334a45a8ff	177	* @brief ADC Configuration regular Channel structure definition
bogdanm	0:9b334a45a8ff	178	*/
bogdanm	0:9b334a45a8ff	179	typedef struct
bogdanm	0:9b334a45a8ff	180	{
bogdanm	0:9b334a45a8ff	181	uint32_t Channel; /*!< the ADC channel to configure
bogdanm	0:9b334a45a8ff	182	This parameter can be a value of @ref ADC_channels */
bogdanm	0:9b334a45a8ff	183	}ADC_ChannelConfTypeDef;
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	/**
bogdanm	0:9b334a45a8ff	187	* @brief ADC Configuration analog watchdog definition
bogdanm	0:9b334a45a8ff	188	*/
bogdanm	0:9b334a45a8ff	189	typedef struct
bogdanm	0:9b334a45a8ff	190	{
bogdanm	0:9b334a45a8ff	191	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels.
bogdanm	0:9b334a45a8ff	192	This parameter can be a value of @ref ADC_analog_watchdog_mode */
bogdanm	0:9b334a45a8ff	193	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
bogdanm	0:9b334a45a8ff	194	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
bogdanm	0:9b334a45a8ff	195	This parameter can be a value of @ref ADC_channels */
bogdanm	0:9b334a45a8ff	196	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
bogdanm	0:9b334a45a8ff	197	This parameter can be set to ENABLE or DISABLE */
bogdanm	0:9b334a45a8ff	198	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm	0:9b334a45a8ff	199	Depending of ADC resolution selected (12, 10, 8 or 6 bits),
bogdanm	0:9b334a45a8ff	200	this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
bogdanm	0:9b334a45a8ff	201	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm	0:9b334a45a8ff	202	Depending of ADC resolution selected (12, 10, 8 or 6 bits),
bogdanm	0:9b334a45a8ff	203	this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
bogdanm	0:9b334a45a8ff	204	}ADC_AnalogWDGConfTypeDef;
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206
bogdanm	0:9b334a45a8ff	207	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209	/** @defgroup ADC_Exported_Constants
bogdanm	0:9b334a45a8ff	210	* @{
bogdanm	0:9b334a45a8ff	211	*/
bogdanm	0:9b334a45a8ff	212
bogdanm	0:9b334a45a8ff	213	/** @defgroup ADC_Error_Code
bogdanm	0:9b334a45a8ff	214	* @{
bogdanm	0:9b334a45a8ff	215	*/
bogdanm	0:9b334a45a8ff	216	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /!< No error /
bogdanm	0:9b334a45a8ff	217	#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
bogdanm	0:9b334a45a8ff	218	enable/disable, erroneous state */
bogdanm	0:9b334a45a8ff	219	#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /!< OVR error /
bogdanm	0:9b334a45a8ff	220	#define HAL_ADC_ERROR_DMA ((uint32_t)0x03) /!< DMA transfer error /
bogdanm	0:9b334a45a8ff	221	/**
bogdanm	0:9b334a45a8ff	222	* @}
bogdanm	0:9b334a45a8ff	223	*/
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225	/** @defgroup ADC_TimeOut_Values
bogdanm	0:9b334a45a8ff	226	* @{
bogdanm	0:9b334a45a8ff	227	*/
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	/* Fixed timeout values for ADC calibration, enable settling time, disable */
bogdanm	0:9b334a45a8ff	230	/* settling time. */
bogdanm	0:9b334a45a8ff	231	/* Values defined to be higher than worst cases: low clocks freq, */
bogdanm	0:9b334a45a8ff	232	/* maximum prescalers. */
bogdanm	0:9b334a45a8ff	233	/* Unit: ms */
bogdanm	0:9b334a45a8ff	234	#define ADC_ENABLE_TIMEOUT 10
bogdanm	0:9b334a45a8ff	235	#define ADC_DISABLE_TIMEOUT 10
bogdanm	0:9b334a45a8ff	236	#define ADC_STOP_CONVERSION_TIMEOUT 10
bogdanm	0:9b334a45a8ff	237
bogdanm	0:9b334a45a8ff	238	/* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */
bogdanm	0:9b334a45a8ff	239	/* the minimum number of CPU cycles to fulfill this delay */
bogdanm	0:9b334a45a8ff	240	#define ADC_DELAY_10US_MIN_CPU_CYCLES 1800
bogdanm	0:9b334a45a8ff	241	/**
bogdanm	0:9b334a45a8ff	242	* @}
bogdanm	0:9b334a45a8ff	243	*/
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	/** @defgroup ADC_ClockPrescaler
bogdanm	0:9b334a45a8ff	246	* @{
bogdanm	0:9b334a45a8ff	247	*/
bogdanm	0:9b334a45a8ff	248	#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /!< ADC Asynchronous clock mode divided by 1 /
bogdanm	0:9b334a45a8ff	249	#define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
bogdanm	0:9b334a45a8ff	250	#define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
bogdanm	0:9b334a45a8ff	251	#define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
bogdanm	0:9b334a45a8ff	252	#define ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /!< ADC Asynchronous clock mode divided by 2 /
bogdanm	0:9b334a45a8ff	253	#define ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
bogdanm	0:9b334a45a8ff	254	#define ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
bogdanm	0:9b334a45a8ff	255	#define ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
bogdanm	0:9b334a45a8ff	256	#define ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /!< ADC Asynchronous clock mode divided by 2 /
bogdanm	0:9b334a45a8ff	257	#define ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
bogdanm	0:9b334a45a8ff	258	#define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
bogdanm	0:9b334a45a8ff	259	#define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 1
bogdanm	0:9b334a45a8ff	262	This configuration must be enabled only if PCLK has a 50%
bogdanm	0:9b334a45a8ff	263	duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
bogdanm	0:9b334a45a8ff	264	must by 50% duty cycle)*/
bogdanm	0:9b334a45a8ff	265	#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_1) /!< Synchronous clock mode divided by 2 /
bogdanm	0:9b334a45a8ff	266	#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE) /!< Synchronous clock mode divided by 4 /
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) \|\|\
bogdanm	0:9b334a45a8ff	269	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) \|\|\
bogdanm	0:9b334a45a8ff	270	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\|\
bogdanm	0:9b334a45a8ff	271	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) \|\|\
bogdanm	0:9b334a45a8ff	272	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) \|\|\
bogdanm	0:9b334a45a8ff	273	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) \|\|\
bogdanm	0:9b334a45a8ff	274	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) \|\|\
bogdanm	0:9b334a45a8ff	275	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) \|\|\
bogdanm	0:9b334a45a8ff	276	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) \|\|\
bogdanm	0:9b334a45a8ff	277	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) \|\|\
bogdanm	0:9b334a45a8ff	278	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) \|\|\
bogdanm	0:9b334a45a8ff	279	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) \|\|\
bogdanm	0:9b334a45a8ff	280	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) \|\|\
bogdanm	0:9b334a45a8ff	281	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) \|\|\
bogdanm	0:9b334a45a8ff	282	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) \|\|\
bogdanm	0:9b334a45a8ff	283	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
bogdanm	0:9b334a45a8ff	284	/**
bogdanm	0:9b334a45a8ff	285	* @}
bogdanm	0:9b334a45a8ff	286	*/
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	/** @defgroup ADC_Resolution
bogdanm	0:9b334a45a8ff	289	* @{
bogdanm	0:9b334a45a8ff	290	*/
bogdanm	0:9b334a45a8ff	291	#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /!< ADC 12-bit resolution /
bogdanm	0:9b334a45a8ff	292	#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /!< ADC 10-bit resolution /
bogdanm	0:9b334a45a8ff	293	#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /!< ADC 8-bit resolution /
bogdanm	0:9b334a45a8ff	294	#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /!< ADC 6-bit resolution /
bogdanm	0:9b334a45a8ff	295
bogdanm	0:9b334a45a8ff	296	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) \|\| \
bogdanm	0:9b334a45a8ff	297	((RESOLUTION) == ADC_RESOLUTION_10B) \|\| \
bogdanm	0:9b334a45a8ff	298	((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
bogdanm	0:9b334a45a8ff	299	((RESOLUTION) == ADC_RESOLUTION_6B))
bogdanm	0:9b334a45a8ff	300
bogdanm	0:9b334a45a8ff	301	#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
bogdanm	0:9b334a45a8ff	302	((RESOLUTION) == ADC_RESOLUTION_6B))
bogdanm	0:9b334a45a8ff	303	/**
bogdanm	0:9b334a45a8ff	304	* @}
bogdanm	0:9b334a45a8ff	305	*/
bogdanm	0:9b334a45a8ff	306
bogdanm	0:9b334a45a8ff	307	/** @defgroup ADC_data_align
bogdanm	0:9b334a45a8ff	308	* @{
bogdanm	0:9b334a45a8ff	309	*/
bogdanm	0:9b334a45a8ff	310	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	311	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
bogdanm	0:9b334a45a8ff	314	((ALIGN) == ADC_DATAALIGN_LEFT))
bogdanm	0:9b334a45a8ff	315	/**
bogdanm	0:9b334a45a8ff	316	* @}
bogdanm	0:9b334a45a8ff	317	*/
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319	/** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group
bogdanm	0:9b334a45a8ff	320	* @{
bogdanm	0:9b334a45a8ff	321	*/
bogdanm	0:9b334a45a8ff	322	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	323	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
bogdanm	0:9b334a45a8ff	324	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
bogdanm	0:9b334a45a8ff	325	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	328	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
bogdanm	0:9b334a45a8ff	329	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	330	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
bogdanm	0:9b334a45a8ff	331	/**
bogdanm	0:9b334a45a8ff	332	* @}
bogdanm	0:9b334a45a8ff	333	*/
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	/** @defgroup ADC_External_trigger_Source
bogdanm	0:9b334a45a8ff	336	* @{
bogdanm	0:9b334a45a8ff	337	*/
bogdanm	0:9b334a45a8ff	338	#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	339	#define ADC_EXTERNALTRIGCONV_T21_CC2 ADC_CFGR1_EXTSEL_0
bogdanm	0:9b334a45a8ff	340	#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_CFGR1_EXTSEL_1
bogdanm	0:9b334a45a8ff	341	#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	342	#define ADC_EXTERNALTRIGCONV_T22_TRGO ADC_CFGR1_EXTSEL_2
bogdanm	0:9b334a45a8ff	343	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_CFGR1_EXTSEL
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO ) \|\| \
bogdanm	0:9b334a45a8ff	346	((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2 ) \|\| \
bogdanm	0:9b334a45a8ff	347	((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO ) \|\| \
bogdanm	0:9b334a45a8ff	348	((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4 ) \|\| \
bogdanm	0:9b334a45a8ff	349	((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) \|\| \
bogdanm	0:9b334a45a8ff	350	((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ))
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/**
bogdanm	0:9b334a45a8ff	353	* @}
bogdanm	0:9b334a45a8ff	354	*/
bogdanm	0:9b334a45a8ff	355
bogdanm	0:9b334a45a8ff	356	/** @defgroup ADC_EOCSelection
bogdanm	0:9b334a45a8ff	357	* @{
bogdanm	0:9b334a45a8ff	358	*/
bogdanm	0:9b334a45a8ff	359	#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
bogdanm	0:9b334a45a8ff	360	#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
bogdanm	0:9b334a45a8ff	361	#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC \| ADC_ISR_EOS)) /!< reserved for future use /
bogdanm	0:9b334a45a8ff	362
bogdanm	0:9b334a45a8ff	363	#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) \|\| \
bogdanm	0:9b334a45a8ff	364	((EOC_SELECTION) == ADC_EOC_SEQ_CONV) \|\| \
bogdanm	0:9b334a45a8ff	365	((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
bogdanm	0:9b334a45a8ff	366	/**
bogdanm	0:9b334a45a8ff	367	* @}
bogdanm	0:9b334a45a8ff	368	*/
bogdanm	0:9b334a45a8ff	369
bogdanm	0:9b334a45a8ff	370	/** @defgroup ADC_Overrun
bogdanm	0:9b334a45a8ff	371	* @{
bogdanm	0:9b334a45a8ff	372	*/
bogdanm	0:9b334a45a8ff	373	#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	374	#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
bogdanm	0:9b334a45a8ff	375
bogdanm	0:9b334a45a8ff	376	#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) \|\| \
bogdanm	0:9b334a45a8ff	377	((OVR) == ADC_OVR_DATA_OVERWRITTEN))
bogdanm	0:9b334a45a8ff	378	/**
bogdanm	0:9b334a45a8ff	379	* @}
bogdanm	0:9b334a45a8ff	380	*/
bogdanm	0:9b334a45a8ff	381
bogdanm	0:9b334a45a8ff	382	/** @defgroup ADC_channels
bogdanm	0:9b334a45a8ff	383	* @{
bogdanm	0:9b334a45a8ff	384	*/
bogdanm	0:9b334a45a8ff	385	#define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0))
bogdanm	0:9b334a45a8ff	386	#define ADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) \| ADC_CFGR1_AWDCH_0)
bogdanm	0:9b334a45a8ff	387	#define ADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) \| ADC_CFGR1_AWDCH_1)
bogdanm	0:9b334a45a8ff	388	#define ADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)\| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
bogdanm	0:9b334a45a8ff	389	#define ADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)\| ADC_CFGR1_AWDCH_2)
bogdanm	0:9b334a45a8ff	390	#define ADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_0)
bogdanm	0:9b334a45a8ff	391	#define ADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1)
bogdanm	0:9b334a45a8ff	392	#define ADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
bogdanm	0:9b334a45a8ff	393	#define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)\| ADC_CFGR1_AWDCH_3)
bogdanm	0:9b334a45a8ff	394	#define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_0)
bogdanm	0:9b334a45a8ff	395	#define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_1)
bogdanm	0:9b334a45a8ff	396	#define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_1\| ADC_CFGR1_AWDCH_0)
bogdanm	0:9b334a45a8ff	397	#define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2)
bogdanm	0:9b334a45a8ff	398	#define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_0)
bogdanm	0:9b334a45a8ff	399	#define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1)
bogdanm	0:9b334a45a8ff	400	#define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1\| ADC_CFGR1_AWDCH_0)
bogdanm	0:9b334a45a8ff	401	#define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)\| ADC_CFGR1_AWDCH_4)
bogdanm	0:9b334a45a8ff	402	#define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)\| ADC_CFGR1_AWDCH_4\| ADC_CFGR1_AWDCH_0)
bogdanm	0:9b334a45a8ff	403	#define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)\| ADC_CFGR1_AWDCH_4\| ADC_CFGR1_AWDCH_1)
bogdanm	0:9b334a45a8ff	404
bogdanm	0:9b334a45a8ff	405	/* Internal channels */
bogdanm	0:9b334a45a8ff	406	#define ADC_CHANNEL_VLCD ADC_CHANNEL_16
bogdanm	0:9b334a45a8ff	407	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
bogdanm	0:9b334a45a8ff	408	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410
bogdanm	0:9b334a45a8ff	411	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
bogdanm	0:9b334a45a8ff	412	((CHANNEL) == ADC_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	413	((CHANNEL) == ADC_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	414	((CHANNEL) == ADC_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	415	((CHANNEL) == ADC_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	416	((CHANNEL) == ADC_CHANNEL_5) \|\| \
bogdanm	0:9b334a45a8ff	417	((CHANNEL) == ADC_CHANNEL_6) \|\| \
bogdanm	0:9b334a45a8ff	418	((CHANNEL) == ADC_CHANNEL_7) \|\| \
bogdanm	0:9b334a45a8ff	419	((CHANNEL) == ADC_CHANNEL_8) \|\| \
bogdanm	0:9b334a45a8ff	420	((CHANNEL) == ADC_CHANNEL_9) \|\| \
bogdanm	0:9b334a45a8ff	421	((CHANNEL) == ADC_CHANNEL_10) \|\| \
bogdanm	0:9b334a45a8ff	422	((CHANNEL) == ADC_CHANNEL_11) \|\| \
bogdanm	0:9b334a45a8ff	423	((CHANNEL) == ADC_CHANNEL_12) \|\| \
bogdanm	0:9b334a45a8ff	424	((CHANNEL) == ADC_CHANNEL_13) \|\| \
bogdanm	0:9b334a45a8ff	425	((CHANNEL) == ADC_CHANNEL_14) \|\| \
bogdanm	0:9b334a45a8ff	426	((CHANNEL) == ADC_CHANNEL_15) \|\| \
bogdanm	0:9b334a45a8ff	427	((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) \|\| \
bogdanm	0:9b334a45a8ff	428	((CHANNEL) == ADC_CHANNEL_VREFINT) \|\| \
bogdanm	0:9b334a45a8ff	429	((CHANNEL) == ADC_CHANNEL_VLCD))
bogdanm	0:9b334a45a8ff	430
bogdanm	0:9b334a45a8ff	431	/**
bogdanm	0:9b334a45a8ff	432	* @}
bogdanm	0:9b334a45a8ff	433	*/
bogdanm	0:9b334a45a8ff	434
bogdanm	0:9b334a45a8ff	435	/** @defgroup ADC_Channel_AWD_Masks
bogdanm	0:9b334a45a8ff	436	* @{
bogdanm	0:9b334a45a8ff	437	*/
bogdanm	0:9b334a45a8ff	438	#define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFF)
bogdanm	0:9b334a45a8ff	439	#define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000)
bogdanm	0:9b334a45a8ff	440	/**
bogdanm	0:9b334a45a8ff	441	* @}
bogdanm	0:9b334a45a8ff	442	*/
bogdanm	0:9b334a45a8ff	443
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	/** @defgroup ADC_sampling_times
bogdanm	0:9b334a45a8ff	446	* @{
bogdanm	0:9b334a45a8ff	447	*/
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /!< ADC sampling time 1.5 cycle /
bogdanm	0:9b334a45a8ff	450	#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /!< ADC sampling time 7.5 CYCLES /
bogdanm	0:9b334a45a8ff	451	#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /!< ADC sampling time 13.5 CYCLES /
bogdanm	0:9b334a45a8ff	452	#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 \| ADC_SMPR_SMPR_0)) /!< ADC sampling time 28.5 CYCLES /
bogdanm	0:9b334a45a8ff	453	#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /!< ADC sampling time 41.5 CYCLES /
bogdanm	0:9b334a45a8ff	454	#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 \| ADC_SMPR_SMPR_0)) /!< ADC sampling time 55.5 CYCLES /
bogdanm	0:9b334a45a8ff	455	#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 \| ADC_SMPR_SMPR_1)) /!< ADC sampling time 71.5 CYCLES /
bogdanm	0:9b334a45a8ff	456	#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /!< ADC sampling time 239.5 CYCLES /
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) \|\| \
bogdanm	0:9b334a45a8ff	459	((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) \|\| \
bogdanm	0:9b334a45a8ff	460	((TIME) == ADC_SAMPLETIME_13CYCLES_5 ) \|\| \
bogdanm	0:9b334a45a8ff	461	((TIME) == ADC_SAMPLETIME_28CYCLES_5 ) \|\| \
bogdanm	0:9b334a45a8ff	462	((TIME) == ADC_SAMPLETIME_41CYCLES_5 ) \|\| \
bogdanm	0:9b334a45a8ff	463	((TIME) == ADC_SAMPLETIME_55CYCLES_5 ) \|\| \
bogdanm	0:9b334a45a8ff	464	((TIME) == ADC_SAMPLETIME_71CYCLES_5 ) \|\| \
bogdanm	0:9b334a45a8ff	465	((TIME) == ADC_SAMPLETIME_239CYCLES_5))
bogdanm	0:9b334a45a8ff	466	/**
bogdanm	0:9b334a45a8ff	467	* @}
bogdanm	0:9b334a45a8ff	468	*/
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470
bogdanm	0:9b334a45a8ff	471	/** @defgroup ADC_Scan_mode ADC Scan mode
bogdanm	0:9b334a45a8ff	472	* @{
bogdanm	0:9b334a45a8ff	473	*/
bogdanm	0:9b334a45a8ff	474	/* Note: Scan mode values must be compatible with other STM32 devices having */
bogdanm	0:9b334a45a8ff	475	/* a configurable sequencer. */
bogdanm	0:9b334a45a8ff	476	/* Scan direction setting values are defined by taking in account */
bogdanm	0:9b334a45a8ff	477	/* already defined values for other STM32 devices: */
bogdanm	0:9b334a45a8ff	478	/* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */
bogdanm	0:9b334a45a8ff	479	/* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */
bogdanm	0:9b334a45a8ff	480	/* Scan direction forward is considered as default setting equivalent */
bogdanm	0:9b334a45a8ff	481	/* to scan enable. */
bogdanm	0:9b334a45a8ff	482	/* Scan direction backward is considered as additional setting. */
bogdanm	0:9b334a45a8ff	483	/* In case of migration from another STM32 device, the user will be */
bogdanm	0:9b334a45a8ff	484	/* warned of change of setting choices with assert check. */
bogdanm	0:9b334a45a8ff	485	#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001) /!< Scan direction forward: from channel 0 to channel 18 /
bogdanm	0:9b334a45a8ff	486	#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002) /!< Scan direction backward: from channel 18 to channel 0 /
bogdanm	0:9b334a45a8ff	487
bogdanm	0:9b334a45a8ff	488	#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
bogdanm	0:9b334a45a8ff	489
bogdanm	0:9b334a45a8ff	490	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) \|\| \
bogdanm	0:9b334a45a8ff	491	((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
bogdanm	0:9b334a45a8ff	492
bogdanm	0:9b334a45a8ff	493	/**
bogdanm	0:9b334a45a8ff	494	* @}
bogdanm	0:9b334a45a8ff	495	*/
bogdanm	0:9b334a45a8ff	496
bogdanm	0:9b334a45a8ff	497	/** @defgroup ADC_Oversampling_Ratio
bogdanm	0:9b334a45a8ff	498	* @{
bogdanm	0:9b334a45a8ff	499	*/
bogdanm	0:9b334a45a8ff	500
bogdanm	0:9b334a45a8ff	501	#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /!< ADC Oversampling ratio 2x /
bogdanm	0:9b334a45a8ff	502	#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004) /!< ADC Oversampling ratio 4x /
bogdanm	0:9b334a45a8ff	503	#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008) /!< ADC Oversampling ratio 8x /
bogdanm	0:9b334a45a8ff	504	#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000C) /!< ADC Oversampling ratio 16x /
bogdanm	0:9b334a45a8ff	505	#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010) /!< ADC Oversampling ratio 32x /
bogdanm	0:9b334a45a8ff	506	#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014) /!< ADC Oversampling ratio 64x /
bogdanm	0:9b334a45a8ff	507	#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018) /!< ADC Oversampling ratio 128x /
bogdanm	0:9b334a45a8ff	508	#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001C) /!< ADC Oversampling ratio 256x /
bogdanm	0:9b334a45a8ff	509	#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) \|\| \
bogdanm	0:9b334a45a8ff	510	((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) \|\| \
bogdanm	0:9b334a45a8ff	511	((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) \|\| \
bogdanm	0:9b334a45a8ff	512	((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) \|\| \
bogdanm	0:9b334a45a8ff	513	((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) \|\| \
bogdanm	0:9b334a45a8ff	514	((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) \|\| \
bogdanm	0:9b334a45a8ff	515	((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) \|\| \
bogdanm	0:9b334a45a8ff	516	((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
bogdanm	0:9b334a45a8ff	517	/**
bogdanm	0:9b334a45a8ff	518	* @}
bogdanm	0:9b334a45a8ff	519	*/
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	/** @defgroup ADC_Right_Bit_Shift
bogdanm	0:9b334a45a8ff	522	* @{
bogdanm	0:9b334a45a8ff	523	*/
bogdanm	0:9b334a45a8ff	524	#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /!< ADC No bit shift for oversampling /
bogdanm	0:9b334a45a8ff	525	#define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020) /!< ADC 1 bit shift for oversampling /
bogdanm	0:9b334a45a8ff	526	#define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040) /!< ADC 2 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	527	#define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060) /!< ADC 3 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	528	#define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080) /!< ADC 4 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	529	#define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0) /!< ADC 5 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	530	#define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0) /!< ADC 6 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	531	#define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0) /!< ADC 7 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	532	#define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100) /!< ADC 8 bits shift for oversampling /
bogdanm	0:9b334a45a8ff	533	#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) \|\| \
bogdanm	0:9b334a45a8ff	534	((SHIFT) == ADC_RIGHTBITSHIFT_1 ) \|\| \
bogdanm	0:9b334a45a8ff	535	((SHIFT) == ADC_RIGHTBITSHIFT_2 ) \|\| \
bogdanm	0:9b334a45a8ff	536	((SHIFT) == ADC_RIGHTBITSHIFT_3 ) \|\| \
bogdanm	0:9b334a45a8ff	537	((SHIFT) == ADC_RIGHTBITSHIFT_4 ) \|\| \
bogdanm	0:9b334a45a8ff	538	((SHIFT) == ADC_RIGHTBITSHIFT_5 ) \|\| \
bogdanm	0:9b334a45a8ff	539	((SHIFT) == ADC_RIGHTBITSHIFT_6 ) \|\| \
bogdanm	0:9b334a45a8ff	540	((SHIFT) == ADC_RIGHTBITSHIFT_7 ) \|\| \
bogdanm	0:9b334a45a8ff	541	((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
bogdanm	0:9b334a45a8ff	542	/**
bogdanm	0:9b334a45a8ff	543	* @}
bogdanm	0:9b334a45a8ff	544	*/
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	/** @defgroup ADC_Triggered_Oversampling_Mode
bogdanm	0:9b334a45a8ff	547	* @{
bogdanm	0:9b334a45a8ff	548	*/
bogdanm	0:9b334a45a8ff	549	#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /!< ADC No bit shift for oversampling /
bogdanm	0:9b334a45a8ff	550	#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200) /!< ADC No bit shift for oversampling /
bogdanm	0:9b334a45a8ff	551	#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) \|\| \
bogdanm	0:9b334a45a8ff	552	((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
bogdanm	0:9b334a45a8ff	553	/**
bogdanm	0:9b334a45a8ff	554	* @}
bogdanm	0:9b334a45a8ff	555	*/
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	/** @defgroup ADC_analog_watchdog_mode
bogdanm	0:9b334a45a8ff	558	* @{
bogdanm	0:9b334a45a8ff	559	*/
bogdanm	0:9b334a45a8ff	560	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
bogdanm	0:9b334a45a8ff	561	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL \| ADC_CFGR1_AWDEN))
bogdanm	0:9b334a45a8ff	562	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
bogdanm	0:9b334a45a8ff	563
bogdanm	0:9b334a45a8ff	564
bogdanm	0:9b334a45a8ff	565	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) \|\| \
bogdanm	0:9b334a45a8ff	566	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
bogdanm	0:9b334a45a8ff	567	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
bogdanm	0:9b334a45a8ff	568	/**
bogdanm	0:9b334a45a8ff	569	* @}
bogdanm	0:9b334a45a8ff	570	*/
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	/** @defgroup ADC_conversion_type
bogdanm	0:9b334a45a8ff	573	* @{
bogdanm	0:9b334a45a8ff	574	*/
bogdanm	0:9b334a45a8ff	575	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_EOS))
bogdanm	0:9b334a45a8ff	576	#define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
bogdanm	0:9b334a45a8ff	577	/**
bogdanm	0:9b334a45a8ff	578	* @}
bogdanm	0:9b334a45a8ff	579	*/
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	/** @defgroup ADC_Event_type
bogdanm	0:9b334a45a8ff	582	* @{
bogdanm	0:9b334a45a8ff	583	*/
bogdanm	0:9b334a45a8ff	584	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
bogdanm	0:9b334a45a8ff	585	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
bogdanm	0:9b334a45a8ff	586
bogdanm	0:9b334a45a8ff	587	#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) \|\| \
bogdanm	0:9b334a45a8ff	588	((EVENT) == ADC_OVR_EVENT))
bogdanm	0:9b334a45a8ff	589	/**
bogdanm	0:9b334a45a8ff	590	* @}
bogdanm	0:9b334a45a8ff	591	*/
bogdanm	0:9b334a45a8ff	592
bogdanm	0:9b334a45a8ff	593	/** @defgroup ADC_interrupts_definition
bogdanm	0:9b334a45a8ff	594	* @{
bogdanm	0:9b334a45a8ff	595	*/
bogdanm	0:9b334a45a8ff	596	#define ADC_IT_RDY ADC_IER_ADRDYIE /!< ADC Ready (ADRDY) interrupt source /
bogdanm	0:9b334a45a8ff	597	#define ADC_IT_EOSMP ADC_IER_EOSMPIE /!< ADC End of Sampling interrupt source /
bogdanm	0:9b334a45a8ff	598	#define ADC_IT_EOC ADC_IER_EOCIE /!< ADC End of Regular Conversion interrupt source /
bogdanm	0:9b334a45a8ff	599	#define ADC_IT_EOS ADC_IER_EOSEQIE /!< ADC End of Regular sequence of Conversions interrupt source /
bogdanm	0:9b334a45a8ff	600	#define ADC_IT_OVR ADC_IER_OVRIE /!< ADC overrun interrupt source /
bogdanm	0:9b334a45a8ff	601	#define ADC_IT_AWD ADC_IER_AWDIE /!< ADC Analog watchdog 1 interrupt source /
bogdanm	0:9b334a45a8ff	602	#define ADC_IT_EOCAL ADC_IER_EOCALIE /!< ADC End of Calibration interrupt source /
bogdanm	0:9b334a45a8ff	603
bogdanm	0:9b334a45a8ff	604	/* Check of single flag */
bogdanm	0:9b334a45a8ff	605	#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) \|\| ((IT) == ADC_IT_RDY) \|\| \
bogdanm	0:9b334a45a8ff	606	((IT) == ADC_IT_EOSMP) \|\| ((IT) == ADC_IT_EOC) \|\| \
bogdanm	0:9b334a45a8ff	607	((IT) == ADC_IT_EOS) \|\| ((IT) == ADC_IT_OVR))
bogdanm	0:9b334a45a8ff	608	/**
bogdanm	0:9b334a45a8ff	609	* @}
bogdanm	0:9b334a45a8ff	610	*/
bogdanm	0:9b334a45a8ff	611
bogdanm	0:9b334a45a8ff	612
bogdanm	0:9b334a45a8ff	613
bogdanm	0:9b334a45a8ff	614	/** @defgroup ADC_flags_definition
bogdanm	0:9b334a45a8ff	615	* @{
bogdanm	0:9b334a45a8ff	616	*/
bogdanm	0:9b334a45a8ff	617	#define ADC_FLAG_RDY ADC_ISR_ADRDY /!< ADC Ready (ADRDY) flag /
bogdanm	0:9b334a45a8ff	618	#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC End of Sampling flag /
bogdanm	0:9b334a45a8ff	619	#define ADC_FLAG_EOC ADC_ISR_EOC /!< ADC End of Regular Conversion flag /
bogdanm	0:9b334a45a8ff	620	#define ADC_FLAG_EOS ADC_ISR_EOSEQ /!< ADC End of Regular sequence of Conversions flag /
bogdanm	0:9b334a45a8ff	621	#define ADC_FLAG_OVR ADC_ISR_OVR /!< ADC overrun flag /
bogdanm	0:9b334a45a8ff	622	#define ADC_FLAG_AWD ADC_ISR_AWD /!< ADC Analog watchdog flag /
bogdanm	0:9b334a45a8ff	623	#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /!< ADC Enf Of Calibration flag /
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625
bogdanm	0:9b334a45a8ff	626	#define ADC_FLAG_ALL (ADC_FLAG_RDY \| ADC_FLAG_EOSMP \| ADC_FLAG_EOC \| ADC_FLAG_EOS \| \
bogdanm	0:9b334a45a8ff	627	ADC_FLAG_OVR \| ADC_FLAG_AWD \| ADC_FLAG_EOCAL)
bogdanm	0:9b334a45a8ff	628
bogdanm	0:9b334a45a8ff	629	/* Check of single flag */
bogdanm	0:9b334a45a8ff	630	#define IS_ADC_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) \|\| ((FLAG) == ADC_FLAG_EOSMP) \|\| \
bogdanm	0:9b334a45a8ff	631	((FLAG) == ADC_FLAG_EOC) \|\| ((FLAG) == ADC_FLAG_EOS) \|\| \
bogdanm	0:9b334a45a8ff	632	((FLAG) == ADC_FLAG_OVR) \|\| ((FLAG) == ADC_FLAG_AWD) \|\| \
bogdanm	0:9b334a45a8ff	633	((FLAG) == ADC_FLAG_EOCAL))
bogdanm	0:9b334a45a8ff	634	/**
bogdanm	0:9b334a45a8ff	635	* @}
bogdanm	0:9b334a45a8ff	636	*/
bogdanm	0:9b334a45a8ff	637
bogdanm	0:9b334a45a8ff	638
bogdanm	0:9b334a45a8ff	639	/** @defgroup ADC_range_verification
bogdanm	0:9b334a45a8ff	640	* in function of ADC resolution selected (12, 10, 8 or 6 bits)
bogdanm	0:9b334a45a8ff	641	* @{
bogdanm	0:9b334a45a8ff	642	*/
bogdanm	0:9b334a45a8ff	643	#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
bogdanm	0:9b334a45a8ff	644	((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) \|\| \
bogdanm	0:9b334a45a8ff	645	(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) \|\| \
bogdanm	0:9b334a45a8ff	646	(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) \|\| \
bogdanm	0:9b334a45a8ff	647	(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
bogdanm	0:9b334a45a8ff	648	/**
bogdanm	0:9b334a45a8ff	649	* @}
bogdanm	0:9b334a45a8ff	650	*/
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/** @defgroup ADC_regular_nb_conv_verification
bogdanm	0:9b334a45a8ff	653	* @{
bogdanm	0:9b334a45a8ff	654	*/
bogdanm	0:9b334a45a8ff	655	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
bogdanm	0:9b334a45a8ff	656	/**
bogdanm	0:9b334a45a8ff	657	* @}
bogdanm	0:9b334a45a8ff	658	*/
bogdanm	0:9b334a45a8ff	659
bogdanm	0:9b334a45a8ff	660	/**
bogdanm	0:9b334a45a8ff	661	* @}
bogdanm	0:9b334a45a8ff	662	*/
bogdanm	0:9b334a45a8ff	663	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	664
bogdanm	0:9b334a45a8ff	665	/** @defgroup ADC_Exported_Macro
bogdanm	0:9b334a45a8ff	666	* @{
bogdanm	0:9b334a45a8ff	667	*/
bogdanm	0:9b334a45a8ff	668	/** @brief Reset ADC handle state
bogdanm	0:9b334a45a8ff	669	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	670	* @retval None
bogdanm	0:9b334a45a8ff	671	*/
bogdanm	0:9b334a45a8ff	672	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
bogdanm	0:9b334a45a8ff	673
bogdanm	0:9b334a45a8ff	674	/**
bogdanm	0:9b334a45a8ff	675	* @brief Enable the ADC peripheral
bogdanm	0:9b334a45a8ff	676	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	677	* @retval None
bogdanm	0:9b334a45a8ff	678	*/
bogdanm	0:9b334a45a8ff	679	#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= ADC_CR_ADEN)
bogdanm	0:9b334a45a8ff	680
bogdanm	0:9b334a45a8ff	681	/**
bogdanm	0:9b334a45a8ff	682	* @brief Verification of hardware constraints before ADC can be enabled
bogdanm	0:9b334a45a8ff	683	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	684	* @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
bogdanm	0:9b334a45a8ff	685	*/
bogdanm	0:9b334a45a8ff	686	#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
bogdanm	0:9b334a45a8ff	687	(( ( ((__HANDLE__)->Instance->CR) & \
bogdanm	0:9b334a45a8ff	688	(ADC_CR_ADCAL \| ADC_CR_ADSTP \| ADC_CR_ADSTART \| \
bogdanm	0:9b334a45a8ff	689	ADC_CR_ADDIS \| ADC_CR_ADEN ) \
bogdanm	0:9b334a45a8ff	690	) == RESET \
bogdanm	0:9b334a45a8ff	691	) ? SET : RESET)
bogdanm	0:9b334a45a8ff	692
bogdanm	0:9b334a45a8ff	693	/**
bogdanm	0:9b334a45a8ff	694	* @brief Disable the ADC peripheral
bogdanm	0:9b334a45a8ff	695	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	696	* @retval None
bogdanm	0:9b334a45a8ff	697	*/
bogdanm	0:9b334a45a8ff	698	#define __HAL_ADC_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	699	do{ \
bogdanm	0:9b334a45a8ff	700	(__HANDLE__)->Instance->CR \|= ADC_CR_ADDIS; \
bogdanm	0:9b334a45a8ff	701	__HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP \| ADC_FLAG_RDY)); \
bogdanm	0:9b334a45a8ff	702	} while(0)
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	/**
bogdanm	0:9b334a45a8ff	705	* @brief Verification of hardware constraints before ADC can be disabled
bogdanm	0:9b334a45a8ff	706	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	707	* @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
bogdanm	0:9b334a45a8ff	708	*/
bogdanm	0:9b334a45a8ff	709	#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
bogdanm	0:9b334a45a8ff	710	(( ( ((__HANDLE__)->Instance->CR) & \
bogdanm	0:9b334a45a8ff	711	(ADC_CR_ADSTART \| ADC_CR_ADEN)) == ADC_CR_ADEN \
bogdanm	0:9b334a45a8ff	712	) ? SET : RESET)
bogdanm	0:9b334a45a8ff	713
bogdanm	0:9b334a45a8ff	714	/**
bogdanm	0:9b334a45a8ff	715	* @brief Verification of ADC state: enabled or disabled
bogdanm	0:9b334a45a8ff	716	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	717	* @retval SET (ADC enabled) or RESET (ADC disabled)
bogdanm	0:9b334a45a8ff	718	*/
bogdanm	0:9b334a45a8ff	719	#define ADC_IS_ENABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	720	(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN \| ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
bogdanm	0:9b334a45a8ff	721	((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
bogdanm	0:9b334a45a8ff	722	) ? SET : RESET)
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	/**
bogdanm	0:9b334a45a8ff	725	* @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution.
bogdanm	0:9b334a45a8ff	726	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	727	* @retval None
bogdanm	0:9b334a45a8ff	728	*/
bogdanm	0:9b334a45a8ff	729	#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731	/**
bogdanm	0:9b334a45a8ff	732	* @brief Check if no conversion is ongoing on regular groups
bogdanm	0:9b334a45a8ff	733	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	734	* @retval SET (conversion is on going) or RESET (no conversion is on going)
bogdanm	0:9b334a45a8ff	735	*/
bogdanm	0:9b334a45a8ff	736	#define ADC_IS_CONVERSION_ONGOING(__HANDLE__) \
bogdanm	0:9b334a45a8ff	737	(( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART)) == RESET ) ? RESET : SET)
bogdanm	0:9b334a45a8ff	738
bogdanm	0:9b334a45a8ff	739	/**
bogdanm	0:9b334a45a8ff	740	* @brief Enable ADC continuous conversion mode.
bogdanm	0:9b334a45a8ff	741	* @param _CONTINUOUS_MODE_: Continuous mode.
bogdanm	0:9b334a45a8ff	742	* @retval None
bogdanm	0:9b334a45a8ff	743	*/
bogdanm	0:9b334a45a8ff	744	#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13)
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	/**
bogdanm	0:9b334a45a8ff	747	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
bogdanm	0:9b334a45a8ff	748	* @param _SCAN_MODE_: Scan conversion mode.
bogdanm	0:9b334a45a8ff	749	* @retval None
bogdanm	0:9b334a45a8ff	750	*/
bogdanm	0:9b334a45a8ff	751	#define ADC_SCANDIR(_SCAN_MODE_) \
bogdanm	0:9b334a45a8ff	752	( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
bogdanm	0:9b334a45a8ff	753	)? (ADC_CFGR1_SCANDIR) : (0x00000000) \
bogdanm	0:9b334a45a8ff	754	)
bogdanm	0:9b334a45a8ff	755
bogdanm	0:9b334a45a8ff	756	/**
bogdanm	0:9b334a45a8ff	757	* @brief Configures the number of discontinuous conversions for the regular group channels.
bogdanm	0:9b334a45a8ff	758	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
bogdanm	0:9b334a45a8ff	759	* @retval None
bogdanm	0:9b334a45a8ff	760	*/
bogdanm	0:9b334a45a8ff	761	#define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 17)
bogdanm	0:9b334a45a8ff	762
bogdanm	0:9b334a45a8ff	763	/**
bogdanm	0:9b334a45a8ff	764	* @brief Enable the ADC DMA continuous request.
bogdanm	0:9b334a45a8ff	765	* @param _DMAContReq_MODE_: DMA continuous request mode.
bogdanm	0:9b334a45a8ff	766	* @retval None
bogdanm	0:9b334a45a8ff	767	*/
bogdanm	0:9b334a45a8ff	768	#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1)
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	/**
bogdanm	0:9b334a45a8ff	771	* @brief Enable the ADC Auto Delay.
bogdanm	0:9b334a45a8ff	772	* @param _AutoDelay_: Auto delay bit enable or disable.
bogdanm	0:9b334a45a8ff	773	* @retval None
bogdanm	0:9b334a45a8ff	774	*/
bogdanm	0:9b334a45a8ff	775	#define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14)
bogdanm	0:9b334a45a8ff	776
bogdanm	0:9b334a45a8ff	777	/**
bogdanm	0:9b334a45a8ff	778	* @brief Enable the ADC LowPowerAutoPowerOff.
bogdanm	0:9b334a45a8ff	779	* @param _AUTOFF_: AutoOff bit enable or disable.
bogdanm	0:9b334a45a8ff	780	* @retval None
bogdanm	0:9b334a45a8ff	781	*/
bogdanm	0:9b334a45a8ff	782	#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15)
bogdanm	0:9b334a45a8ff	783
bogdanm	0:9b334a45a8ff	784	/**
bogdanm	0:9b334a45a8ff	785	* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
bogdanm	0:9b334a45a8ff	786	* @param _Threshold_: Threshold value
bogdanm	0:9b334a45a8ff	787	* @retval None
bogdanm	0:9b334a45a8ff	788	*/
bogdanm	0:9b334a45a8ff	789	#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
bogdanm	0:9b334a45a8ff	790
bogdanm	0:9b334a45a8ff	791	/**
bogdanm	0:9b334a45a8ff	792	* @brief Enable the ADC Low Frequency mode.
bogdanm	0:9b334a45a8ff	793	* @param _LOW_FREQUENCY_MODE_: Low Frequency mode.
bogdanm	0:9b334a45a8ff	794	* @retval None
bogdanm	0:9b334a45a8ff	795	*/
bogdanm	0:9b334a45a8ff	796	#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25)
bogdanm	0:9b334a45a8ff	797
bogdanm	0:9b334a45a8ff	798	/**
bogdanm	0:9b334a45a8ff	799	* @brief Shift the offset in function of the selected ADC resolution.
bogdanm	0:9b334a45a8ff	800	* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
bogdanm	0:9b334a45a8ff	801	* If resolution 12 bits, no shift.
bogdanm	0:9b334a45a8ff	802	* If resolution 10 bits, shift of 2 ranks on the right.
bogdanm	0:9b334a45a8ff	803	* If resolution 8 bits, shift of 4 ranks on the right.
bogdanm	0:9b334a45a8ff	804	* If resolution 6 bits, shift of 6 ranks on the right.
bogdanm	0:9b334a45a8ff	805	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
bogdanm	0:9b334a45a8ff	806	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	807	* @param _Offset_: Value to be shifted
bogdanm	0:9b334a45a8ff	808	* @retval None
bogdanm	0:9b334a45a8ff	809	*/
bogdanm	0:9b334a45a8ff	810	#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
bogdanm	0:9b334a45a8ff	811	((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3)*2))
bogdanm	0:9b334a45a8ff	812
bogdanm	0:9b334a45a8ff	813	/**
bogdanm	0:9b334a45a8ff	814	* @brief Shift the AWD1 threshold in function of the selected ADC resolution.
bogdanm	0:9b334a45a8ff	815	* Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0
bogdanm	0:9b334a45a8ff	816	* If resolution 12 bits, no shift.
bogdanm	0:9b334a45a8ff	817	* If resolution 10 bits, shift of 2 ranks on the right.
bogdanm	0:9b334a45a8ff	818	* If resolution 8 bits, shift of 4 ranks on the right.
bogdanm	0:9b334a45a8ff	819	* If resolution 6 bits, shift of 6 ranks on the right.
bogdanm	0:9b334a45a8ff	820	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
bogdanm	0:9b334a45a8ff	821	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	822	* @param _Threshold_: Value to be shifted
bogdanm	0:9b334a45a8ff	823	* @retval None
bogdanm	0:9b334a45a8ff	824	*/
bogdanm	0:9b334a45a8ff	825	#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
bogdanm	0:9b334a45a8ff	826	((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2))
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	/**
bogdanm	0:9b334a45a8ff	829	* @brief Shift the value on the left, less significant are set to 0.
bogdanm	0:9b334a45a8ff	830	* @param _Value_: Value to be shifted
bogdanm	0:9b334a45a8ff	831	* @param _Shift_: Number of shift to be done
bogdanm	0:9b334a45a8ff	832	* @retval None
bogdanm	0:9b334a45a8ff	833	*/
bogdanm	0:9b334a45a8ff	834	#define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_))
bogdanm	0:9b334a45a8ff	835
bogdanm	0:9b334a45a8ff	836
bogdanm	0:9b334a45a8ff	837	/**
bogdanm	0:9b334a45a8ff	838	* @brief Enable the ADC end of conversion interrupt.
bogdanm	0:9b334a45a8ff	839	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	840	* @param __INTERRUPT__: ADC Interrupt.
bogdanm	0:9b334a45a8ff	841	* @retval None
bogdanm	0:9b334a45a8ff	842	*/
bogdanm	0:9b334a45a8ff	843	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	844
bogdanm	0:9b334a45a8ff	845	/**
bogdanm	0:9b334a45a8ff	846	* @brief Disable the ADC end of conversion interrupt.
bogdanm	0:9b334a45a8ff	847	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	848	* @param __INTERRUPT__: ADC interrupt.
bogdanm	0:9b334a45a8ff	849	* @retval None
bogdanm	0:9b334a45a8ff	850	*/
bogdanm	0:9b334a45a8ff	851	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	852
bogdanm	0:9b334a45a8ff	853	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
bogdanm	0:9b334a45a8ff	854	* @param __HANDLE__: specifies the ADC Handle.
bogdanm	0:9b334a45a8ff	855	* @param __INTERRUPT__: specifies the ADC interrupt source to check.
bogdanm	0:9b334a45a8ff	856	* @retval The new state of __IT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	857	*/
bogdanm	0:9b334a45a8ff	858	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	/**
bogdanm	0:9b334a45a8ff	861	* @brief Clear the ADC's pending flags
bogdanm	0:9b334a45a8ff	862	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	863	* @param __FLAG__: ADC flag.
bogdanm	0:9b334a45a8ff	864	* @retval None
bogdanm	0:9b334a45a8ff	865	*/
bogdanm	0:9b334a45a8ff	866	/* Note: bit cleared bit by writing 1 */
bogdanm	0:9b334a45a8ff	867	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
bogdanm	0:9b334a45a8ff	868
bogdanm	0:9b334a45a8ff	869	/**
bogdanm	0:9b334a45a8ff	870	* @brief Get the selected ADC's flag status.
bogdanm	0:9b334a45a8ff	871	* @param __HANDLE__: ADC handle.
bogdanm	0:9b334a45a8ff	872	* @param __FLAG__: ADC flag.
bogdanm	0:9b334a45a8ff	873	* @retval None
bogdanm	0:9b334a45a8ff	874	*/
bogdanm	0:9b334a45a8ff	875	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	876
bogdanm	0:9b334a45a8ff	877
bogdanm	0:9b334a45a8ff	878
bogdanm	0:9b334a45a8ff	879	/**
bogdanm	0:9b334a45a8ff	880	* @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler
bogdanm	0:9b334a45a8ff	881	* @param __HANDLE__: ADC handle
bogdanm	0:9b334a45a8ff	882	* @retval None
bogdanm	0:9b334a45a8ff	883	*/
bogdanm	0:9b334a45a8ff	884
bogdanm	0:9b334a45a8ff	885	#define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \
bogdanm	0:9b334a45a8ff	886	do{ \
bogdanm	0:9b334a45a8ff	887	if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	888	(((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	889	(((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) \
bogdanm	0:9b334a45a8ff	890	{ \
bogdanm	0:9b334a45a8ff	891	(__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
bogdanm	0:9b334a45a8ff	892	(__HANDLE__)->Instance->CFGR2 \|= (__HANDLE__)->Init.ClockPrescaler; \
bogdanm	0:9b334a45a8ff	893	} \
bogdanm	0:9b334a45a8ff	894	else \
bogdanm	0:9b334a45a8ff	895	{ \
bogdanm	0:9b334a45a8ff	896	/* CKMOD bits must be reset */ \
bogdanm	0:9b334a45a8ff	897	(__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
bogdanm	0:9b334a45a8ff	898	ADC->CCR &= ~(ADC_CCR_PRESC); \
bogdanm	0:9b334a45a8ff	899	ADC->CCR \|= (__HANDLE__)->Init.ClockPrescaler; \
bogdanm	0:9b334a45a8ff	900	} \
bogdanm	0:9b334a45a8ff	901	} while(0)
bogdanm	0:9b334a45a8ff	902
bogdanm	0:9b334a45a8ff	903	/**
bogdanm	0:9b334a45a8ff	904	* @}
bogdanm	0:9b334a45a8ff	905	*/
bogdanm	0:9b334a45a8ff	906
bogdanm	0:9b334a45a8ff	907	/* Include ADC HAL Extension module */
bogdanm	0:9b334a45a8ff	908	#include "stm32l0xx_hal_adc_ex.h"
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	911	/* Initialization and de-initialization functions **********************************/
bogdanm	0:9b334a45a8ff	912	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	913	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
bogdanm	0:9b334a45a8ff	914	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	915	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	/* IO operation functions *****************************************************/
bogdanm	0:9b334a45a8ff	918	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	919	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	920	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	921	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	922	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	923
bogdanm	0:9b334a45a8ff	924	/* Non-blocking mode: Interruption */
bogdanm	0:9b334a45a8ff	925	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	926	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	927
bogdanm	0:9b334a45a8ff	928	/* Non-blocking mode: DMA */
bogdanm	0:9b334a45a8ff	929	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
bogdanm	0:9b334a45a8ff	930	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	/* ADC retrieve conversion value intended to be used with polling or interruption */
bogdanm	0:9b334a45a8ff	933	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
bogdanm	0:9b334a45a8ff	936	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	937	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	938	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	939	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	940	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	/* Peripheral Control functions ***********************************************/
bogdanm	0:9b334a45a8ff	943	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
bogdanm	0:9b334a45a8ff	944	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
bogdanm	0:9b334a45a8ff	945
bogdanm	0:9b334a45a8ff	946	/* Peripheral State functions *************************************************/
bogdanm	0:9b334a45a8ff	947	HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	948	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950
bogdanm	0:9b334a45a8ff	951	/**
bogdanm	0:9b334a45a8ff	952	* @}
bogdanm	0:9b334a45a8ff	953	*/
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	/**
bogdanm	0:9b334a45a8ff	956	* @}
bogdanm	0:9b334a45a8ff	957	*/
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	960	}
bogdanm	0:9b334a45a8ff	961	#endif
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	#endif /__STM32L0xx_ADC_H /
bogdanm	0:9b334a45a8ff	964
bogdanm	0:9b334a45a8ff	965
bogdanm	0:9b334a45a8ff	966	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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