fix LPC812 PWM
Fork of mbed-dev by
targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 83:a036322b8637
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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bogdanm | 0:9b334a45a8ff | 1 | /** |
bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f7xx_ll_fmc.h |
bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
bogdanm | 0:9b334a45a8ff | 5 | * @version V1.0.1 |
bogdanm | 0:9b334a45a8ff | 6 | * @date 25-June-2015 |
bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file of FMC HAL module. |
bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 9 | * @attention |
bogdanm | 0:9b334a45a8ff | 10 | * |
bogdanm | 0:9b334a45a8ff | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
bogdanm | 0:9b334a45a8ff | 12 | * |
bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
bogdanm | 0:9b334a45a8ff | 23 | * |
bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 0:9b334a45a8ff | 34 | * |
bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 36 | */ |
bogdanm | 0:9b334a45a8ff | 37 | |
bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32F7xx_LL_FMC_H |
bogdanm | 0:9b334a45a8ff | 40 | #define __STM32F7xx_LL_FMC_H |
bogdanm | 0:9b334a45a8ff | 41 | |
bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
bogdanm | 0:9b334a45a8ff | 44 | #endif |
bogdanm | 0:9b334a45a8ff | 45 | |
bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 47 | #include "stm32f7xx_hal_def.h" |
bogdanm | 0:9b334a45a8ff | 48 | |
bogdanm | 0:9b334a45a8ff | 49 | /** @addtogroup STM32F7xx_HAL_Driver |
bogdanm | 0:9b334a45a8ff | 50 | * @{ |
bogdanm | 0:9b334a45a8ff | 51 | */ |
bogdanm | 0:9b334a45a8ff | 52 | |
bogdanm | 0:9b334a45a8ff | 53 | /** @addtogroup FMC_LL |
bogdanm | 0:9b334a45a8ff | 54 | * @{ |
bogdanm | 0:9b334a45a8ff | 55 | */ |
bogdanm | 0:9b334a45a8ff | 56 | |
bogdanm | 0:9b334a45a8ff | 57 | /** @addtogroup FMC_LL_Private_Macros |
bogdanm | 0:9b334a45a8ff | 58 | * @{ |
bogdanm | 0:9b334a45a8ff | 59 | */ |
bogdanm | 0:9b334a45a8ff | 60 | #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \ |
bogdanm | 0:9b334a45a8ff | 61 | ((BANK) == FMC_NORSRAM_BANK2) || \ |
bogdanm | 0:9b334a45a8ff | 62 | ((BANK) == FMC_NORSRAM_BANK3) || \ |
bogdanm | 0:9b334a45a8ff | 63 | ((BANK) == FMC_NORSRAM_BANK4)) |
bogdanm | 0:9b334a45a8ff | 64 | |
bogdanm | 0:9b334a45a8ff | 65 | #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 66 | ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) |
bogdanm | 0:9b334a45a8ff | 67 | |
bogdanm | 0:9b334a45a8ff | 68 | #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ |
bogdanm | 0:9b334a45a8ff | 69 | ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ |
bogdanm | 0:9b334a45a8ff | 70 | ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) |
bogdanm | 0:9b334a45a8ff | 71 | |
bogdanm | 0:9b334a45a8ff | 72 | #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
bogdanm | 0:9b334a45a8ff | 73 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
bogdanm | 0:9b334a45a8ff | 74 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) |
bogdanm | 0:9b334a45a8ff | 75 | |
bogdanm | 0:9b334a45a8ff | 76 | #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ |
bogdanm | 0:9b334a45a8ff | 77 | ((__MODE__) == FMC_ACCESS_MODE_B) || \ |
bogdanm | 0:9b334a45a8ff | 78 | ((__MODE__) == FMC_ACCESS_MODE_C) || \ |
bogdanm | 0:9b334a45a8ff | 79 | ((__MODE__) == FMC_ACCESS_MODE_D)) |
bogdanm | 0:9b334a45a8ff | 80 | |
bogdanm | 0:9b334a45a8ff | 81 | #define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3) |
bogdanm | 0:9b334a45a8ff | 82 | |
bogdanm | 0:9b334a45a8ff | 83 | #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 84 | ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE)) |
bogdanm | 0:9b334a45a8ff | 85 | |
bogdanm | 0:9b334a45a8ff | 86 | #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \ |
bogdanm | 0:9b334a45a8ff | 87 | ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16)) |
bogdanm | 0:9b334a45a8ff | 88 | |
bogdanm | 0:9b334a45a8ff | 89 | #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 90 | ((STATE) == FMC_NAND_ECC_ENABLE)) |
bogdanm | 0:9b334a45a8ff | 91 | |
bogdanm | 0:9b334a45a8ff | 92 | #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
bogdanm | 0:9b334a45a8ff | 93 | ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
bogdanm | 0:9b334a45a8ff | 94 | ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
bogdanm | 0:9b334a45a8ff | 95 | ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
bogdanm | 0:9b334a45a8ff | 96 | ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
bogdanm | 0:9b334a45a8ff | 97 | ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
bogdanm | 0:9b334a45a8ff | 98 | |
bogdanm | 0:9b334a45a8ff | 99 | #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ |
bogdanm | 0:9b334a45a8ff | 100 | ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ |
bogdanm | 0:9b334a45a8ff | 101 | ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32)) |
bogdanm | 0:9b334a45a8ff | 102 | |
bogdanm | 0:9b334a45a8ff | 103 | #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 104 | ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) |
bogdanm | 0:9b334a45a8ff | 105 | |
bogdanm | 0:9b334a45a8ff | 106 | #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 107 | ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ |
bogdanm | 0:9b334a45a8ff | 108 | ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) |
bogdanm | 0:9b334a45a8ff | 109 | |
bogdanm | 0:9b334a45a8ff | 110 | #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 111 | ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) |
bogdanm | 0:9b334a45a8ff | 112 | |
bogdanm | 0:9b334a45a8ff | 113 | #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ |
bogdanm | 0:9b334a45a8ff | 114 | ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ |
bogdanm | 0:9b334a45a8ff | 115 | ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) |
bogdanm | 0:9b334a45a8ff | 116 | |
bogdanm | 0:9b334a45a8ff | 117 | #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ |
bogdanm | 0:9b334a45a8ff | 118 | ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ |
bogdanm | 0:9b334a45a8ff | 119 | ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ |
bogdanm | 0:9b334a45a8ff | 120 | ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ |
bogdanm | 0:9b334a45a8ff | 121 | ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ |
bogdanm | 0:9b334a45a8ff | 122 | ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ |
bogdanm | 0:9b334a45a8ff | 123 | ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) |
bogdanm | 0:9b334a45a8ff | 124 | |
bogdanm | 0:9b334a45a8ff | 125 | #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ |
bogdanm | 0:9b334a45a8ff | 126 | ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ |
bogdanm | 0:9b334a45a8ff | 127 | ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) |
bogdanm | 0:9b334a45a8ff | 128 | |
bogdanm | 0:9b334a45a8ff | 129 | /** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time |
bogdanm | 0:9b334a45a8ff | 130 | * @{ |
bogdanm | 0:9b334a45a8ff | 131 | */ |
bogdanm | 0:9b334a45a8ff | 132 | #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) |
bogdanm | 0:9b334a45a8ff | 133 | /** |
bogdanm | 0:9b334a45a8ff | 134 | * @} |
bogdanm | 0:9b334a45a8ff | 135 | */ |
bogdanm | 0:9b334a45a8ff | 136 | |
bogdanm | 0:9b334a45a8ff | 137 | /** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time |
bogdanm | 0:9b334a45a8ff | 138 | * @{ |
bogdanm | 0:9b334a45a8ff | 139 | */ |
bogdanm | 0:9b334a45a8ff | 140 | #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255) |
bogdanm | 0:9b334a45a8ff | 141 | /** |
bogdanm | 0:9b334a45a8ff | 142 | * @} |
bogdanm | 0:9b334a45a8ff | 143 | */ |
bogdanm | 0:9b334a45a8ff | 144 | |
bogdanm | 0:9b334a45a8ff | 145 | /** @defgroup FMC_Setup_Time FMC Setup Time |
bogdanm | 0:9b334a45a8ff | 146 | * @{ |
bogdanm | 0:9b334a45a8ff | 147 | */ |
bogdanm | 0:9b334a45a8ff | 148 | #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254) |
bogdanm | 0:9b334a45a8ff | 149 | /** |
bogdanm | 0:9b334a45a8ff | 150 | * @} |
bogdanm | 0:9b334a45a8ff | 151 | */ |
bogdanm | 0:9b334a45a8ff | 152 | |
bogdanm | 0:9b334a45a8ff | 153 | /** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time |
bogdanm | 0:9b334a45a8ff | 154 | * @{ |
bogdanm | 0:9b334a45a8ff | 155 | */ |
bogdanm | 0:9b334a45a8ff | 156 | #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254) |
bogdanm | 0:9b334a45a8ff | 157 | /** |
bogdanm | 0:9b334a45a8ff | 158 | * @} |
bogdanm | 0:9b334a45a8ff | 159 | */ |
bogdanm | 0:9b334a45a8ff | 160 | |
bogdanm | 0:9b334a45a8ff | 161 | /** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time |
bogdanm | 0:9b334a45a8ff | 162 | * @{ |
bogdanm | 0:9b334a45a8ff | 163 | */ |
bogdanm | 0:9b334a45a8ff | 164 | #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254) |
bogdanm | 0:9b334a45a8ff | 165 | /** |
bogdanm | 0:9b334a45a8ff | 166 | * @} |
bogdanm | 0:9b334a45a8ff | 167 | */ |
bogdanm | 0:9b334a45a8ff | 168 | |
bogdanm | 0:9b334a45a8ff | 169 | /** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time |
bogdanm | 0:9b334a45a8ff | 170 | * @{ |
bogdanm | 0:9b334a45a8ff | 171 | */ |
bogdanm | 0:9b334a45a8ff | 172 | #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254) |
bogdanm | 0:9b334a45a8ff | 173 | /** |
bogdanm | 0:9b334a45a8ff | 174 | * @} |
bogdanm | 0:9b334a45a8ff | 175 | */ |
bogdanm | 0:9b334a45a8ff | 176 | |
bogdanm | 0:9b334a45a8ff | 177 | #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 178 | ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) |
bogdanm | 0:9b334a45a8ff | 179 | |
bogdanm | 0:9b334a45a8ff | 180 | #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
bogdanm | 0:9b334a45a8ff | 181 | ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) |
bogdanm | 0:9b334a45a8ff | 182 | |
bogdanm | 0:9b334a45a8ff | 183 | #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ |
bogdanm | 0:9b334a45a8ff | 184 | ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) |
bogdanm | 0:9b334a45a8ff | 185 | |
bogdanm | 0:9b334a45a8ff | 186 | #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 187 | ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) |
bogdanm | 0:9b334a45a8ff | 188 | |
bogdanm | 0:9b334a45a8ff | 189 | #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 190 | ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) |
bogdanm | 0:9b334a45a8ff | 191 | |
bogdanm | 0:9b334a45a8ff | 192 | #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 193 | ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) |
bogdanm | 0:9b334a45a8ff | 194 | |
bogdanm | 0:9b334a45a8ff | 195 | #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 196 | ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) |
bogdanm | 0:9b334a45a8ff | 197 | |
bogdanm | 0:9b334a45a8ff | 198 | /** @defgroup FMC_Data_Latency FMC Data Latency |
bogdanm | 0:9b334a45a8ff | 199 | * @{ |
bogdanm | 0:9b334a45a8ff | 200 | */ |
bogdanm | 0:9b334a45a8ff | 201 | #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) |
bogdanm | 0:9b334a45a8ff | 202 | /** |
bogdanm | 0:9b334a45a8ff | 203 | * @} |
bogdanm | 0:9b334a45a8ff | 204 | */ |
bogdanm | 0:9b334a45a8ff | 205 | |
bogdanm | 0:9b334a45a8ff | 206 | #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 207 | ((__BURST__) == FMC_WRITE_BURST_ENABLE)) |
bogdanm | 0:9b334a45a8ff | 208 | |
bogdanm | 0:9b334a45a8ff | 209 | #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
bogdanm | 0:9b334a45a8ff | 210 | ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
bogdanm | 0:9b334a45a8ff | 211 | |
bogdanm | 0:9b334a45a8ff | 212 | |
bogdanm | 0:9b334a45a8ff | 213 | /** @defgroup FMC_Address_Setup_Time FMC Address Setup Time |
bogdanm | 0:9b334a45a8ff | 214 | * @{ |
bogdanm | 0:9b334a45a8ff | 215 | */ |
bogdanm | 0:9b334a45a8ff | 216 | #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) |
bogdanm | 0:9b334a45a8ff | 217 | /** |
bogdanm | 0:9b334a45a8ff | 218 | * @} |
bogdanm | 0:9b334a45a8ff | 219 | */ |
bogdanm | 0:9b334a45a8ff | 220 | |
bogdanm | 0:9b334a45a8ff | 221 | /** @defgroup FMC_Address_Hold_Time FMC Address Hold Time |
bogdanm | 0:9b334a45a8ff | 222 | * @{ |
bogdanm | 0:9b334a45a8ff | 223 | */ |
bogdanm | 0:9b334a45a8ff | 224 | #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) |
bogdanm | 0:9b334a45a8ff | 225 | /** |
bogdanm | 0:9b334a45a8ff | 226 | * @} |
bogdanm | 0:9b334a45a8ff | 227 | */ |
bogdanm | 0:9b334a45a8ff | 228 | |
bogdanm | 0:9b334a45a8ff | 229 | /** @defgroup FMC_Data_Setup_Time FMC Data Setup Time |
bogdanm | 0:9b334a45a8ff | 230 | * @{ |
bogdanm | 0:9b334a45a8ff | 231 | */ |
bogdanm | 0:9b334a45a8ff | 232 | #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) |
bogdanm | 0:9b334a45a8ff | 233 | /** |
bogdanm | 0:9b334a45a8ff | 234 | * @} |
bogdanm | 0:9b334a45a8ff | 235 | */ |
bogdanm | 0:9b334a45a8ff | 236 | |
bogdanm | 0:9b334a45a8ff | 237 | /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration |
bogdanm | 0:9b334a45a8ff | 238 | * @{ |
bogdanm | 0:9b334a45a8ff | 239 | */ |
bogdanm | 0:9b334a45a8ff | 240 | #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) |
bogdanm | 0:9b334a45a8ff | 241 | /** |
bogdanm | 0:9b334a45a8ff | 242 | * @} |
bogdanm | 0:9b334a45a8ff | 243 | */ |
bogdanm | 0:9b334a45a8ff | 244 | |
bogdanm | 0:9b334a45a8ff | 245 | /** @defgroup FMC_CLK_Division FMC CLK Division |
bogdanm | 0:9b334a45a8ff | 246 | * @{ |
bogdanm | 0:9b334a45a8ff | 247 | */ |
bogdanm | 0:9b334a45a8ff | 248 | #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16)) |
bogdanm | 0:9b334a45a8ff | 249 | /** |
bogdanm | 0:9b334a45a8ff | 250 | * @} |
bogdanm | 0:9b334a45a8ff | 251 | */ |
bogdanm | 0:9b334a45a8ff | 252 | |
bogdanm | 0:9b334a45a8ff | 253 | /** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay |
bogdanm | 0:9b334a45a8ff | 254 | * @{ |
bogdanm | 0:9b334a45a8ff | 255 | */ |
bogdanm | 0:9b334a45a8ff | 256 | #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) |
bogdanm | 0:9b334a45a8ff | 257 | /** |
bogdanm | 0:9b334a45a8ff | 258 | * @} |
bogdanm | 0:9b334a45a8ff | 259 | */ |
bogdanm | 0:9b334a45a8ff | 260 | |
bogdanm | 0:9b334a45a8ff | 261 | /** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay |
bogdanm | 0:9b334a45a8ff | 262 | * @{ |
bogdanm | 0:9b334a45a8ff | 263 | */ |
bogdanm | 0:9b334a45a8ff | 264 | #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) |
bogdanm | 0:9b334a45a8ff | 265 | /** |
bogdanm | 0:9b334a45a8ff | 266 | * @} |
bogdanm | 0:9b334a45a8ff | 267 | */ |
bogdanm | 0:9b334a45a8ff | 268 | |
bogdanm | 0:9b334a45a8ff | 269 | /** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time |
bogdanm | 0:9b334a45a8ff | 270 | * @{ |
bogdanm | 0:9b334a45a8ff | 271 | */ |
bogdanm | 0:9b334a45a8ff | 272 | #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) |
bogdanm | 0:9b334a45a8ff | 273 | /** |
bogdanm | 0:9b334a45a8ff | 274 | * @} |
bogdanm | 0:9b334a45a8ff | 275 | */ |
bogdanm | 0:9b334a45a8ff | 276 | |
bogdanm | 0:9b334a45a8ff | 277 | /** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay |
bogdanm | 0:9b334a45a8ff | 278 | * @{ |
bogdanm | 0:9b334a45a8ff | 279 | */ |
bogdanm | 0:9b334a45a8ff | 280 | #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) |
bogdanm | 0:9b334a45a8ff | 281 | /** |
bogdanm | 0:9b334a45a8ff | 282 | * @} |
bogdanm | 0:9b334a45a8ff | 283 | */ |
bogdanm | 0:9b334a45a8ff | 284 | |
bogdanm | 0:9b334a45a8ff | 285 | /** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time |
bogdanm | 0:9b334a45a8ff | 286 | * @{ |
bogdanm | 0:9b334a45a8ff | 287 | */ |
bogdanm | 0:9b334a45a8ff | 288 | #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) |
bogdanm | 0:9b334a45a8ff | 289 | /** |
bogdanm | 0:9b334a45a8ff | 290 | * @} |
bogdanm | 0:9b334a45a8ff | 291 | */ |
bogdanm | 0:9b334a45a8ff | 292 | |
bogdanm | 0:9b334a45a8ff | 293 | /** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay |
bogdanm | 0:9b334a45a8ff | 294 | * @{ |
bogdanm | 0:9b334a45a8ff | 295 | */ |
bogdanm | 0:9b334a45a8ff | 296 | #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) |
bogdanm | 0:9b334a45a8ff | 297 | /** |
bogdanm | 0:9b334a45a8ff | 298 | * @} |
bogdanm | 0:9b334a45a8ff | 299 | */ |
bogdanm | 0:9b334a45a8ff | 300 | |
bogdanm | 0:9b334a45a8ff | 301 | /** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay |
bogdanm | 0:9b334a45a8ff | 302 | * @{ |
bogdanm | 0:9b334a45a8ff | 303 | */ |
bogdanm | 0:9b334a45a8ff | 304 | #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) |
bogdanm | 0:9b334a45a8ff | 305 | /** |
bogdanm | 0:9b334a45a8ff | 306 | * @} |
bogdanm | 0:9b334a45a8ff | 307 | */ |
bogdanm | 0:9b334a45a8ff | 308 | |
bogdanm | 0:9b334a45a8ff | 309 | /** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number |
bogdanm | 0:9b334a45a8ff | 310 | * @{ |
bogdanm | 0:9b334a45a8ff | 311 | */ |
bogdanm | 0:9b334a45a8ff | 312 | #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16)) |
bogdanm | 0:9b334a45a8ff | 313 | /** |
bogdanm | 0:9b334a45a8ff | 314 | * @} |
bogdanm | 0:9b334a45a8ff | 315 | */ |
bogdanm | 0:9b334a45a8ff | 316 | |
bogdanm | 0:9b334a45a8ff | 317 | /** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition |
bogdanm | 0:9b334a45a8ff | 318 | * @{ |
bogdanm | 0:9b334a45a8ff | 319 | */ |
bogdanm | 0:9b334a45a8ff | 320 | #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191) |
bogdanm | 0:9b334a45a8ff | 321 | /** |
bogdanm | 0:9b334a45a8ff | 322 | * @} |
bogdanm | 0:9b334a45a8ff | 323 | */ |
bogdanm | 0:9b334a45a8ff | 324 | |
bogdanm | 0:9b334a45a8ff | 325 | /** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate |
bogdanm | 0:9b334a45a8ff | 326 | * @{ |
bogdanm | 0:9b334a45a8ff | 327 | */ |
bogdanm | 0:9b334a45a8ff | 328 | #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191) |
bogdanm | 0:9b334a45a8ff | 329 | /** |
bogdanm | 0:9b334a45a8ff | 330 | * @} |
bogdanm | 0:9b334a45a8ff | 331 | */ |
bogdanm | 0:9b334a45a8ff | 332 | |
bogdanm | 0:9b334a45a8ff | 333 | /** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance |
bogdanm | 0:9b334a45a8ff | 334 | * @{ |
bogdanm | 0:9b334a45a8ff | 335 | */ |
bogdanm | 0:9b334a45a8ff | 336 | #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) |
bogdanm | 0:9b334a45a8ff | 337 | /** |
bogdanm | 0:9b334a45a8ff | 338 | * @} |
bogdanm | 0:9b334a45a8ff | 339 | */ |
bogdanm | 0:9b334a45a8ff | 340 | |
bogdanm | 0:9b334a45a8ff | 341 | /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance |
bogdanm | 0:9b334a45a8ff | 342 | * @{ |
bogdanm | 0:9b334a45a8ff | 343 | */ |
bogdanm | 0:9b334a45a8ff | 344 | #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) |
bogdanm | 0:9b334a45a8ff | 345 | /** |
bogdanm | 0:9b334a45a8ff | 346 | * @} |
bogdanm | 0:9b334a45a8ff | 347 | */ |
bogdanm | 0:9b334a45a8ff | 348 | |
bogdanm | 0:9b334a45a8ff | 349 | /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance |
bogdanm | 0:9b334a45a8ff | 350 | * @{ |
bogdanm | 0:9b334a45a8ff | 351 | */ |
bogdanm | 0:9b334a45a8ff | 352 | #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) |
bogdanm | 0:9b334a45a8ff | 353 | /** |
bogdanm | 0:9b334a45a8ff | 354 | * @} |
bogdanm | 0:9b334a45a8ff | 355 | */ |
bogdanm | 0:9b334a45a8ff | 356 | |
bogdanm | 0:9b334a45a8ff | 357 | /** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance |
bogdanm | 0:9b334a45a8ff | 358 | * @{ |
bogdanm | 0:9b334a45a8ff | 359 | */ |
bogdanm | 0:9b334a45a8ff | 360 | #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) |
bogdanm | 0:9b334a45a8ff | 361 | /** |
bogdanm | 0:9b334a45a8ff | 362 | * @} |
bogdanm | 0:9b334a45a8ff | 363 | */ |
bogdanm | 0:9b334a45a8ff | 364 | |
bogdanm | 0:9b334a45a8ff | 365 | #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \ |
bogdanm | 0:9b334a45a8ff | 366 | ((BANK) == FMC_SDRAM_BANK2)) |
bogdanm | 0:9b334a45a8ff | 367 | |
bogdanm | 0:9b334a45a8ff | 368 | #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ |
bogdanm | 0:9b334a45a8ff | 369 | ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ |
bogdanm | 0:9b334a45a8ff | 370 | ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ |
bogdanm | 0:9b334a45a8ff | 371 | ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11)) |
bogdanm | 0:9b334a45a8ff | 372 | |
bogdanm | 0:9b334a45a8ff | 373 | #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \ |
bogdanm | 0:9b334a45a8ff | 374 | ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \ |
bogdanm | 0:9b334a45a8ff | 375 | ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13)) |
bogdanm | 0:9b334a45a8ff | 376 | |
bogdanm | 0:9b334a45a8ff | 377 | #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ |
bogdanm | 0:9b334a45a8ff | 378 | ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4)) |
bogdanm | 0:9b334a45a8ff | 379 | |
bogdanm | 0:9b334a45a8ff | 380 | |
bogdanm | 0:9b334a45a8ff | 381 | #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \ |
bogdanm | 0:9b334a45a8ff | 382 | ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \ |
bogdanm | 0:9b334a45a8ff | 383 | ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3)) |
bogdanm | 0:9b334a45a8ff | 384 | |
bogdanm | 0:9b334a45a8ff | 385 | #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ |
bogdanm | 0:9b334a45a8ff | 386 | ((__SIZE__) == FMC_PAGE_SIZE_128) || \ |
bogdanm | 0:9b334a45a8ff | 387 | ((__SIZE__) == FMC_PAGE_SIZE_256) || \ |
bogdanm | 0:9b334a45a8ff | 388 | ((__SIZE__) == FMC_PAGE_SIZE_1024)) |
bogdanm | 0:9b334a45a8ff | 389 | |
bogdanm | 0:9b334a45a8ff | 390 | #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ |
bogdanm | 0:9b334a45a8ff | 391 | ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) |
bogdanm | 0:9b334a45a8ff | 392 | /** |
bogdanm | 0:9b334a45a8ff | 393 | * @} |
bogdanm | 0:9b334a45a8ff | 394 | */ |
bogdanm | 0:9b334a45a8ff | 395 | |
bogdanm | 0:9b334a45a8ff | 396 | /* Exported typedef ----------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 397 | /** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types |
bogdanm | 0:9b334a45a8ff | 398 | * @{ |
bogdanm | 0:9b334a45a8ff | 399 | */ |
bogdanm | 0:9b334a45a8ff | 400 | #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef |
bogdanm | 0:9b334a45a8ff | 401 | #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef |
bogdanm | 0:9b334a45a8ff | 402 | #define FMC_NAND_TypeDef FMC_Bank3_TypeDef |
bogdanm | 0:9b334a45a8ff | 403 | #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef |
bogdanm | 0:9b334a45a8ff | 404 | |
bogdanm | 0:9b334a45a8ff | 405 | #define FMC_NORSRAM_DEVICE FMC_Bank1 |
bogdanm | 0:9b334a45a8ff | 406 | #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E |
bogdanm | 0:9b334a45a8ff | 407 | #define FMC_NAND_DEVICE FMC_Bank3 |
bogdanm | 0:9b334a45a8ff | 408 | #define FMC_SDRAM_DEVICE FMC_Bank5_6 |
bogdanm | 0:9b334a45a8ff | 409 | |
bogdanm | 0:9b334a45a8ff | 410 | /** |
bogdanm | 0:9b334a45a8ff | 411 | * @brief FMC NORSRAM Configuration Structure definition |
bogdanm | 0:9b334a45a8ff | 412 | */ |
bogdanm | 0:9b334a45a8ff | 413 | typedef struct |
bogdanm | 0:9b334a45a8ff | 414 | { |
bogdanm | 0:9b334a45a8ff | 415 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
bogdanm | 0:9b334a45a8ff | 416 | This parameter can be a value of @ref FMC_NORSRAM_Bank */ |
bogdanm | 0:9b334a45a8ff | 417 | |
bogdanm | 0:9b334a45a8ff | 418 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
bogdanm | 0:9b334a45a8ff | 419 | multiplexed on the data bus or not. |
bogdanm | 0:9b334a45a8ff | 420 | This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ |
bogdanm | 0:9b334a45a8ff | 421 | |
bogdanm | 0:9b334a45a8ff | 422 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
bogdanm | 0:9b334a45a8ff | 423 | the corresponding memory device. |
bogdanm | 0:9b334a45a8ff | 424 | This parameter can be a value of @ref FMC_Memory_Type */ |
bogdanm | 0:9b334a45a8ff | 425 | |
bogdanm | 0:9b334a45a8ff | 426 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
bogdanm | 0:9b334a45a8ff | 427 | This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ |
bogdanm | 0:9b334a45a8ff | 428 | |
bogdanm | 0:9b334a45a8ff | 429 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
bogdanm | 0:9b334a45a8ff | 430 | valid only with synchronous burst Flash memories. |
bogdanm | 0:9b334a45a8ff | 431 | This parameter can be a value of @ref FMC_Burst_Access_Mode */ |
bogdanm | 0:9b334a45a8ff | 432 | |
bogdanm | 0:9b334a45a8ff | 433 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
bogdanm | 0:9b334a45a8ff | 434 | the Flash memory in burst mode. |
bogdanm | 0:9b334a45a8ff | 435 | This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ |
bogdanm | 0:9b334a45a8ff | 436 | |
bogdanm | 0:9b334a45a8ff | 437 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
bogdanm | 0:9b334a45a8ff | 438 | clock cycle before the wait state or during the wait state, |
bogdanm | 0:9b334a45a8ff | 439 | valid only when accessing memories in burst mode. |
bogdanm | 0:9b334a45a8ff | 440 | This parameter can be a value of @ref FMC_Wait_Timing */ |
bogdanm | 0:9b334a45a8ff | 441 | |
bogdanm | 0:9b334a45a8ff | 442 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. |
bogdanm | 0:9b334a45a8ff | 443 | This parameter can be a value of @ref FMC_Write_Operation */ |
bogdanm | 0:9b334a45a8ff | 444 | |
bogdanm | 0:9b334a45a8ff | 445 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
bogdanm | 0:9b334a45a8ff | 446 | signal, valid for Flash memory access in burst mode. |
bogdanm | 0:9b334a45a8ff | 447 | This parameter can be a value of @ref FMC_Wait_Signal */ |
bogdanm | 0:9b334a45a8ff | 448 | |
bogdanm | 0:9b334a45a8ff | 449 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
bogdanm | 0:9b334a45a8ff | 450 | This parameter can be a value of @ref FMC_Extended_Mode */ |
bogdanm | 0:9b334a45a8ff | 451 | |
bogdanm | 0:9b334a45a8ff | 452 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
bogdanm | 0:9b334a45a8ff | 453 | valid only with asynchronous Flash memories. |
bogdanm | 0:9b334a45a8ff | 454 | This parameter can be a value of @ref FMC_AsynchronousWait */ |
bogdanm | 0:9b334a45a8ff | 455 | |
bogdanm | 0:9b334a45a8ff | 456 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
bogdanm | 0:9b334a45a8ff | 457 | This parameter can be a value of @ref FMC_Write_Burst */ |
bogdanm | 0:9b334a45a8ff | 458 | |
bogdanm | 0:9b334a45a8ff | 459 | uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. |
bogdanm | 0:9b334a45a8ff | 460 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
bogdanm | 0:9b334a45a8ff | 461 | through FMC_BCR2..4 registers. |
bogdanm | 0:9b334a45a8ff | 462 | This parameter can be a value of @ref FMC_Continous_Clock */ |
bogdanm | 0:9b334a45a8ff | 463 | |
bogdanm | 0:9b334a45a8ff | 464 | uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. |
bogdanm | 0:9b334a45a8ff | 465 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
bogdanm | 0:9b334a45a8ff | 466 | through FMC_BCR2..4 registers. |
bogdanm | 0:9b334a45a8ff | 467 | This parameter can be a value of @ref FMC_Write_FIFO */ |
bogdanm | 0:9b334a45a8ff | 468 | |
bogdanm | 0:9b334a45a8ff | 469 | uint32_t PageSize; /*!< Specifies the memory page size. |
bogdanm | 0:9b334a45a8ff | 470 | This parameter can be a value of @ref FMC_Page_Size */ |
bogdanm | 0:9b334a45a8ff | 471 | |
bogdanm | 0:9b334a45a8ff | 472 | }FMC_NORSRAM_InitTypeDef; |
bogdanm | 0:9b334a45a8ff | 473 | |
bogdanm | 0:9b334a45a8ff | 474 | /** |
bogdanm | 0:9b334a45a8ff | 475 | * @brief FMC NORSRAM Timing parameters structure definition |
bogdanm | 0:9b334a45a8ff | 476 | */ |
bogdanm | 0:9b334a45a8ff | 477 | typedef struct |
bogdanm | 0:9b334a45a8ff | 478 | { |
bogdanm | 0:9b334a45a8ff | 479 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
bogdanm | 0:9b334a45a8ff | 480 | the duration of the address setup time. |
bogdanm | 0:9b334a45a8ff | 481 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
bogdanm | 0:9b334a45a8ff | 482 | @note This parameter is not used with synchronous NOR Flash memories. */ |
bogdanm | 0:9b334a45a8ff | 483 | |
bogdanm | 0:9b334a45a8ff | 484 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
bogdanm | 0:9b334a45a8ff | 485 | the duration of the address hold time. |
bogdanm | 0:9b334a45a8ff | 486 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
bogdanm | 0:9b334a45a8ff | 487 | @note This parameter is not used with synchronous NOR Flash memories. */ |
bogdanm | 0:9b334a45a8ff | 488 | |
bogdanm | 0:9b334a45a8ff | 489 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
bogdanm | 0:9b334a45a8ff | 490 | the duration of the data setup time. |
bogdanm | 0:9b334a45a8ff | 491 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
bogdanm | 0:9b334a45a8ff | 492 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
bogdanm | 0:9b334a45a8ff | 493 | NOR Flash memories. */ |
bogdanm | 0:9b334a45a8ff | 494 | |
bogdanm | 0:9b334a45a8ff | 495 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
bogdanm | 0:9b334a45a8ff | 496 | the duration of the bus turnaround. |
bogdanm | 0:9b334a45a8ff | 497 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
bogdanm | 0:9b334a45a8ff | 498 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
bogdanm | 0:9b334a45a8ff | 499 | |
bogdanm | 0:9b334a45a8ff | 500 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
bogdanm | 0:9b334a45a8ff | 501 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
bogdanm | 0:9b334a45a8ff | 502 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
bogdanm | 0:9b334a45a8ff | 503 | accesses. */ |
bogdanm | 0:9b334a45a8ff | 504 | |
bogdanm | 0:9b334a45a8ff | 505 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
bogdanm | 0:9b334a45a8ff | 506 | to the memory before getting the first data. |
bogdanm | 0:9b334a45a8ff | 507 | The parameter value depends on the memory type as shown below: |
bogdanm | 0:9b334a45a8ff | 508 | - It must be set to 0 in case of a CRAM |
bogdanm | 0:9b334a45a8ff | 509 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
bogdanm | 0:9b334a45a8ff | 510 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
bogdanm | 0:9b334a45a8ff | 511 | with synchronous burst mode enable */ |
bogdanm | 0:9b334a45a8ff | 512 | |
bogdanm | 0:9b334a45a8ff | 513 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
bogdanm | 0:9b334a45a8ff | 514 | This parameter can be a value of @ref FMC_Access_Mode */ |
bogdanm | 0:9b334a45a8ff | 515 | }FMC_NORSRAM_TimingTypeDef; |
bogdanm | 0:9b334a45a8ff | 516 | |
bogdanm | 0:9b334a45a8ff | 517 | /** |
bogdanm | 0:9b334a45a8ff | 518 | * @brief FMC NAND Configuration Structure definition |
bogdanm | 0:9b334a45a8ff | 519 | */ |
bogdanm | 0:9b334a45a8ff | 520 | typedef struct |
bogdanm | 0:9b334a45a8ff | 521 | { |
bogdanm | 0:9b334a45a8ff | 522 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
bogdanm | 0:9b334a45a8ff | 523 | This parameter can be a value of @ref FMC_NAND_Bank */ |
bogdanm | 0:9b334a45a8ff | 524 | |
bogdanm | 0:9b334a45a8ff | 525 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
bogdanm | 0:9b334a45a8ff | 526 | This parameter can be any value of @ref FMC_Wait_feature */ |
bogdanm | 0:9b334a45a8ff | 527 | |
bogdanm | 0:9b334a45a8ff | 528 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
bogdanm | 0:9b334a45a8ff | 529 | This parameter can be any value of @ref FMC_NAND_Data_Width */ |
bogdanm | 0:9b334a45a8ff | 530 | |
bogdanm | 0:9b334a45a8ff | 531 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
bogdanm | 0:9b334a45a8ff | 532 | This parameter can be any value of @ref FMC_ECC */ |
bogdanm | 0:9b334a45a8ff | 533 | |
bogdanm | 0:9b334a45a8ff | 534 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
bogdanm | 0:9b334a45a8ff | 535 | This parameter can be any value of @ref FMC_ECC_Page_Size */ |
bogdanm | 0:9b334a45a8ff | 536 | |
bogdanm | 0:9b334a45a8ff | 537 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
bogdanm | 0:9b334a45a8ff | 538 | delay between CLE low and RE low. |
bogdanm | 0:9b334a45a8ff | 539 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
bogdanm | 0:9b334a45a8ff | 540 | |
bogdanm | 0:9b334a45a8ff | 541 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
bogdanm | 0:9b334a45a8ff | 542 | delay between ALE low and RE low. |
bogdanm | 0:9b334a45a8ff | 543 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
bogdanm | 0:9b334a45a8ff | 544 | }FMC_NAND_InitTypeDef; |
bogdanm | 0:9b334a45a8ff | 545 | |
bogdanm | 0:9b334a45a8ff | 546 | /** |
bogdanm | 0:9b334a45a8ff | 547 | * @brief FMC NAND Timing parameters structure definition |
bogdanm | 0:9b334a45a8ff | 548 | */ |
bogdanm | 0:9b334a45a8ff | 549 | typedef struct |
bogdanm | 0:9b334a45a8ff | 550 | { |
bogdanm | 0:9b334a45a8ff | 551 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
bogdanm | 0:9b334a45a8ff | 552 | the command assertion for NAND-Flash read or write access |
bogdanm | 0:9b334a45a8ff | 553 | to common/Attribute or I/O memory space (depending on |
bogdanm | 0:9b334a45a8ff | 554 | the memory space timing to be configured). |
bogdanm | 0:9b334a45a8ff | 555 | This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ |
bogdanm | 0:9b334a45a8ff | 556 | |
bogdanm | 0:9b334a45a8ff | 557 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
bogdanm | 0:9b334a45a8ff | 558 | command for NAND-Flash read or write access to |
bogdanm | 0:9b334a45a8ff | 559 | common/Attribute or I/O memory space (depending on the |
bogdanm | 0:9b334a45a8ff | 560 | memory space timing to be configured). |
bogdanm | 0:9b334a45a8ff | 561 | This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ |
bogdanm | 0:9b334a45a8ff | 562 | |
bogdanm | 0:9b334a45a8ff | 563 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
bogdanm | 0:9b334a45a8ff | 564 | (and data for write access) after the command de-assertion |
bogdanm | 0:9b334a45a8ff | 565 | for NAND-Flash read or write access to common/Attribute |
bogdanm | 0:9b334a45a8ff | 566 | or I/O memory space (depending on the memory space timing |
bogdanm | 0:9b334a45a8ff | 567 | to be configured). |
bogdanm | 0:9b334a45a8ff | 568 | This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ |
bogdanm | 0:9b334a45a8ff | 569 | |
bogdanm | 0:9b334a45a8ff | 570 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
bogdanm | 0:9b334a45a8ff | 571 | data bus is kept in HiZ after the start of a NAND-Flash |
bogdanm | 0:9b334a45a8ff | 572 | write access to common/Attribute or I/O memory space (depending |
bogdanm | 0:9b334a45a8ff | 573 | on the memory space timing to be configured). |
bogdanm | 0:9b334a45a8ff | 574 | This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ |
bogdanm | 0:9b334a45a8ff | 575 | }FMC_NAND_PCC_TimingTypeDef; |
bogdanm | 0:9b334a45a8ff | 576 | |
bogdanm | 0:9b334a45a8ff | 577 | /** |
bogdanm | 0:9b334a45a8ff | 578 | * @brief FMC SDRAM Configuration Structure definition |
bogdanm | 0:9b334a45a8ff | 579 | */ |
bogdanm | 0:9b334a45a8ff | 580 | typedef struct |
bogdanm | 0:9b334a45a8ff | 581 | { |
bogdanm | 0:9b334a45a8ff | 582 | uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. |
bogdanm | 0:9b334a45a8ff | 583 | This parameter can be a value of @ref FMC_SDRAM_Bank */ |
bogdanm | 0:9b334a45a8ff | 584 | |
bogdanm | 0:9b334a45a8ff | 585 | uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. |
bogdanm | 0:9b334a45a8ff | 586 | This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ |
bogdanm | 0:9b334a45a8ff | 587 | |
bogdanm | 0:9b334a45a8ff | 588 | uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. |
bogdanm | 0:9b334a45a8ff | 589 | This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ |
bogdanm | 0:9b334a45a8ff | 590 | |
bogdanm | 0:9b334a45a8ff | 591 | uint32_t MemoryDataWidth; /*!< Defines the memory device width. |
bogdanm | 0:9b334a45a8ff | 592 | This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ |
bogdanm | 0:9b334a45a8ff | 593 | |
bogdanm | 0:9b334a45a8ff | 594 | uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. |
bogdanm | 0:9b334a45a8ff | 595 | This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ |
bogdanm | 0:9b334a45a8ff | 596 | |
bogdanm | 0:9b334a45a8ff | 597 | uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. |
bogdanm | 0:9b334a45a8ff | 598 | This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ |
bogdanm | 0:9b334a45a8ff | 599 | |
bogdanm | 0:9b334a45a8ff | 600 | uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. |
bogdanm | 0:9b334a45a8ff | 601 | This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ |
bogdanm | 0:9b334a45a8ff | 602 | |
bogdanm | 0:9b334a45a8ff | 603 | uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow |
bogdanm | 0:9b334a45a8ff | 604 | to disable the clock before changing frequency. |
bogdanm | 0:9b334a45a8ff | 605 | This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ |
bogdanm | 0:9b334a45a8ff | 606 | |
bogdanm | 0:9b334a45a8ff | 607 | uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read |
bogdanm | 0:9b334a45a8ff | 608 | commands during the CAS latency and stores data in the Read FIFO. |
bogdanm | 0:9b334a45a8ff | 609 | This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ |
bogdanm | 0:9b334a45a8ff | 610 | |
bogdanm | 0:9b334a45a8ff | 611 | uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. |
bogdanm | 0:9b334a45a8ff | 612 | This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ |
bogdanm | 0:9b334a45a8ff | 613 | }FMC_SDRAM_InitTypeDef; |
bogdanm | 0:9b334a45a8ff | 614 | |
bogdanm | 0:9b334a45a8ff | 615 | /** |
bogdanm | 0:9b334a45a8ff | 616 | * @brief FMC SDRAM Timing parameters structure definition |
bogdanm | 0:9b334a45a8ff | 617 | */ |
bogdanm | 0:9b334a45a8ff | 618 | typedef struct |
bogdanm | 0:9b334a45a8ff | 619 | { |
bogdanm | 0:9b334a45a8ff | 620 | uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and |
bogdanm | 0:9b334a45a8ff | 621 | an active or Refresh command in number of memory clock cycles. |
bogdanm | 0:9b334a45a8ff | 622 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ |
bogdanm | 0:9b334a45a8ff | 623 | |
bogdanm | 0:9b334a45a8ff | 624 | uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to |
bogdanm | 0:9b334a45a8ff | 625 | issuing the Activate command in number of memory clock cycles. |
bogdanm | 0:9b334a45a8ff | 626 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ |
bogdanm | 0:9b334a45a8ff | 627 | |
bogdanm | 0:9b334a45a8ff | 628 | uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock |
bogdanm | 0:9b334a45a8ff | 629 | cycles. |
bogdanm | 0:9b334a45a8ff | 630 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ |
bogdanm | 0:9b334a45a8ff | 631 | |
bogdanm | 0:9b334a45a8ff | 632 | uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command |
bogdanm | 0:9b334a45a8ff | 633 | and the delay between two consecutive Refresh commands in number of |
bogdanm | 0:9b334a45a8ff | 634 | memory clock cycles. |
bogdanm | 0:9b334a45a8ff | 635 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ |
bogdanm | 0:9b334a45a8ff | 636 | |
bogdanm | 0:9b334a45a8ff | 637 | uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. |
bogdanm | 0:9b334a45a8ff | 638 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ |
bogdanm | 0:9b334a45a8ff | 639 | |
bogdanm | 0:9b334a45a8ff | 640 | uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command |
bogdanm | 0:9b334a45a8ff | 641 | in number of memory clock cycles. |
bogdanm | 0:9b334a45a8ff | 642 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ |
bogdanm | 0:9b334a45a8ff | 643 | |
bogdanm | 0:9b334a45a8ff | 644 | uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write |
bogdanm | 0:9b334a45a8ff | 645 | command in number of memory clock cycles. |
bogdanm | 0:9b334a45a8ff | 646 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ |
bogdanm | 0:9b334a45a8ff | 647 | }FMC_SDRAM_TimingTypeDef; |
bogdanm | 0:9b334a45a8ff | 648 | |
bogdanm | 0:9b334a45a8ff | 649 | /** |
bogdanm | 0:9b334a45a8ff | 650 | * @brief SDRAM command parameters structure definition |
bogdanm | 0:9b334a45a8ff | 651 | */ |
bogdanm | 0:9b334a45a8ff | 652 | typedef struct |
bogdanm | 0:9b334a45a8ff | 653 | { |
bogdanm | 0:9b334a45a8ff | 654 | uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. |
bogdanm | 0:9b334a45a8ff | 655 | This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ |
bogdanm | 0:9b334a45a8ff | 656 | |
bogdanm | 0:9b334a45a8ff | 657 | uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. |
bogdanm | 0:9b334a45a8ff | 658 | This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ |
bogdanm | 0:9b334a45a8ff | 659 | |
bogdanm | 0:9b334a45a8ff | 660 | uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued |
bogdanm | 0:9b334a45a8ff | 661 | in auto refresh mode. |
bogdanm | 0:9b334a45a8ff | 662 | This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ |
bogdanm | 0:9b334a45a8ff | 663 | uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ |
bogdanm | 0:9b334a45a8ff | 664 | }FMC_SDRAM_CommandTypeDef; |
bogdanm | 0:9b334a45a8ff | 665 | /** |
bogdanm | 0:9b334a45a8ff | 666 | * @} |
bogdanm | 0:9b334a45a8ff | 667 | */ |
bogdanm | 0:9b334a45a8ff | 668 | |
bogdanm | 0:9b334a45a8ff | 669 | /* Exported constants --------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 670 | /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants |
bogdanm | 0:9b334a45a8ff | 671 | * @{ |
bogdanm | 0:9b334a45a8ff | 672 | */ |
bogdanm | 0:9b334a45a8ff | 673 | |
bogdanm | 0:9b334a45a8ff | 674 | /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller |
bogdanm | 0:9b334a45a8ff | 675 | * @{ |
bogdanm | 0:9b334a45a8ff | 676 | */ |
bogdanm | 0:9b334a45a8ff | 677 | |
bogdanm | 0:9b334a45a8ff | 678 | /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank |
bogdanm | 0:9b334a45a8ff | 679 | * @{ |
bogdanm | 0:9b334a45a8ff | 680 | */ |
bogdanm | 0:9b334a45a8ff | 681 | #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 682 | #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) |
bogdanm | 0:9b334a45a8ff | 683 | #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) |
bogdanm | 0:9b334a45a8ff | 684 | #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) |
bogdanm | 0:9b334a45a8ff | 685 | /** |
bogdanm | 0:9b334a45a8ff | 686 | * @} |
bogdanm | 0:9b334a45a8ff | 687 | */ |
bogdanm | 0:9b334a45a8ff | 688 | |
bogdanm | 0:9b334a45a8ff | 689 | /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing |
bogdanm | 0:9b334a45a8ff | 690 | * @{ |
bogdanm | 0:9b334a45a8ff | 691 | */ |
bogdanm | 0:9b334a45a8ff | 692 | #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 693 | #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002) |
bogdanm | 0:9b334a45a8ff | 694 | /** |
bogdanm | 0:9b334a45a8ff | 695 | * @} |
bogdanm | 0:9b334a45a8ff | 696 | */ |
bogdanm | 0:9b334a45a8ff | 697 | |
bogdanm | 0:9b334a45a8ff | 698 | /** @defgroup FMC_Memory_Type FMC Memory Type |
bogdanm | 0:9b334a45a8ff | 699 | * @{ |
bogdanm | 0:9b334a45a8ff | 700 | */ |
bogdanm | 0:9b334a45a8ff | 701 | #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 702 | #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004) |
bogdanm | 0:9b334a45a8ff | 703 | #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008) |
bogdanm | 0:9b334a45a8ff | 704 | /** |
bogdanm | 0:9b334a45a8ff | 705 | * @} |
bogdanm | 0:9b334a45a8ff | 706 | */ |
bogdanm | 0:9b334a45a8ff | 707 | |
bogdanm | 0:9b334a45a8ff | 708 | /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width |
bogdanm | 0:9b334a45a8ff | 709 | * @{ |
bogdanm | 0:9b334a45a8ff | 710 | */ |
bogdanm | 0:9b334a45a8ff | 711 | #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 712 | #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) |
bogdanm | 0:9b334a45a8ff | 713 | #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) |
bogdanm | 0:9b334a45a8ff | 714 | /** |
bogdanm | 0:9b334a45a8ff | 715 | * @} |
bogdanm | 0:9b334a45a8ff | 716 | */ |
bogdanm | 0:9b334a45a8ff | 717 | |
bogdanm | 0:9b334a45a8ff | 718 | /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access |
bogdanm | 0:9b334a45a8ff | 719 | * @{ |
bogdanm | 0:9b334a45a8ff | 720 | */ |
bogdanm | 0:9b334a45a8ff | 721 | #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040) |
bogdanm | 0:9b334a45a8ff | 722 | #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 723 | /** |
bogdanm | 0:9b334a45a8ff | 724 | * @} |
bogdanm | 0:9b334a45a8ff | 725 | */ |
bogdanm | 0:9b334a45a8ff | 726 | |
bogdanm | 0:9b334a45a8ff | 727 | /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode |
bogdanm | 0:9b334a45a8ff | 728 | * @{ |
bogdanm | 0:9b334a45a8ff | 729 | */ |
bogdanm | 0:9b334a45a8ff | 730 | #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 731 | #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100) |
bogdanm | 0:9b334a45a8ff | 732 | /** |
bogdanm | 0:9b334a45a8ff | 733 | * @} |
bogdanm | 0:9b334a45a8ff | 734 | */ |
bogdanm | 0:9b334a45a8ff | 735 | |
bogdanm | 0:9b334a45a8ff | 736 | /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity |
bogdanm | 0:9b334a45a8ff | 737 | * @{ |
bogdanm | 0:9b334a45a8ff | 738 | */ |
bogdanm | 0:9b334a45a8ff | 739 | #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 740 | #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200) |
bogdanm | 0:9b334a45a8ff | 741 | /** |
bogdanm | 0:9b334a45a8ff | 742 | * @} |
bogdanm | 0:9b334a45a8ff | 743 | */ |
bogdanm | 0:9b334a45a8ff | 744 | |
bogdanm | 0:9b334a45a8ff | 745 | /** @defgroup FMC_Wait_Timing FMC Wait Timing |
bogdanm | 0:9b334a45a8ff | 746 | * @{ |
bogdanm | 0:9b334a45a8ff | 747 | */ |
bogdanm | 0:9b334a45a8ff | 748 | #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 749 | #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800) |
bogdanm | 0:9b334a45a8ff | 750 | /** |
bogdanm | 0:9b334a45a8ff | 751 | * @} |
bogdanm | 0:9b334a45a8ff | 752 | */ |
bogdanm | 0:9b334a45a8ff | 753 | |
bogdanm | 0:9b334a45a8ff | 754 | /** @defgroup FMC_Write_Operation FMC Write Operation |
bogdanm | 0:9b334a45a8ff | 755 | * @{ |
bogdanm | 0:9b334a45a8ff | 756 | */ |
bogdanm | 0:9b334a45a8ff | 757 | #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 758 | #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000) |
bogdanm | 0:9b334a45a8ff | 759 | /** |
bogdanm | 0:9b334a45a8ff | 760 | * @} |
bogdanm | 0:9b334a45a8ff | 761 | */ |
bogdanm | 0:9b334a45a8ff | 762 | |
bogdanm | 0:9b334a45a8ff | 763 | /** @defgroup FMC_Wait_Signal FMC Wait Signal |
bogdanm | 0:9b334a45a8ff | 764 | * @{ |
bogdanm | 0:9b334a45a8ff | 765 | */ |
bogdanm | 0:9b334a45a8ff | 766 | #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 767 | #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000) |
bogdanm | 0:9b334a45a8ff | 768 | /** |
bogdanm | 0:9b334a45a8ff | 769 | * @} |
bogdanm | 0:9b334a45a8ff | 770 | */ |
bogdanm | 0:9b334a45a8ff | 771 | |
bogdanm | 0:9b334a45a8ff | 772 | /** @defgroup FMC_Extended_Mode FMC Extended Mode |
bogdanm | 0:9b334a45a8ff | 773 | * @{ |
bogdanm | 0:9b334a45a8ff | 774 | */ |
bogdanm | 0:9b334a45a8ff | 775 | #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 776 | #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000) |
bogdanm | 0:9b334a45a8ff | 777 | /** |
bogdanm | 0:9b334a45a8ff | 778 | * @} |
bogdanm | 0:9b334a45a8ff | 779 | */ |
bogdanm | 0:9b334a45a8ff | 780 | |
bogdanm | 0:9b334a45a8ff | 781 | /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait |
bogdanm | 0:9b334a45a8ff | 782 | * @{ |
bogdanm | 0:9b334a45a8ff | 783 | */ |
bogdanm | 0:9b334a45a8ff | 784 | #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 785 | #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000) |
bogdanm | 0:9b334a45a8ff | 786 | /** |
bogdanm | 0:9b334a45a8ff | 787 | * @} |
bogdanm | 0:9b334a45a8ff | 788 | */ |
bogdanm | 0:9b334a45a8ff | 789 | |
bogdanm | 0:9b334a45a8ff | 790 | /** @defgroup FMC_Page_Size FMC Page Size |
bogdanm | 0:9b334a45a8ff | 791 | * @{ |
bogdanm | 0:9b334a45a8ff | 792 | */ |
bogdanm | 0:9b334a45a8ff | 793 | #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 794 | #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0) |
bogdanm | 0:9b334a45a8ff | 795 | #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1) |
bogdanm | 0:9b334a45a8ff | 796 | #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2) |
bogdanm | 0:9b334a45a8ff | 797 | /** |
bogdanm | 0:9b334a45a8ff | 798 | * @} |
bogdanm | 0:9b334a45a8ff | 799 | */ |
bogdanm | 0:9b334a45a8ff | 800 | |
bogdanm | 0:9b334a45a8ff | 801 | /** @defgroup FMC_Write_Burst FMC Write Burst |
bogdanm | 0:9b334a45a8ff | 802 | * @{ |
bogdanm | 0:9b334a45a8ff | 803 | */ |
bogdanm | 0:9b334a45a8ff | 804 | #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 805 | #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000) |
bogdanm | 0:9b334a45a8ff | 806 | /** |
bogdanm | 0:9b334a45a8ff | 807 | * @} |
bogdanm | 0:9b334a45a8ff | 808 | */ |
bogdanm | 0:9b334a45a8ff | 809 | |
bogdanm | 0:9b334a45a8ff | 810 | /** @defgroup FMC_Continous_Clock FMC Continuous Clock |
bogdanm | 0:9b334a45a8ff | 811 | * @{ |
bogdanm | 0:9b334a45a8ff | 812 | */ |
bogdanm | 0:9b334a45a8ff | 813 | #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 814 | #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000) |
bogdanm | 0:9b334a45a8ff | 815 | /** |
bogdanm | 0:9b334a45a8ff | 816 | * @} |
bogdanm | 0:9b334a45a8ff | 817 | */ |
bogdanm | 0:9b334a45a8ff | 818 | |
bogdanm | 0:9b334a45a8ff | 819 | /** @defgroup FMC_Write_FIFO FMC Write FIFO |
bogdanm | 0:9b334a45a8ff | 820 | * @{ |
bogdanm | 0:9b334a45a8ff | 821 | */ |
bogdanm | 0:9b334a45a8ff | 822 | #define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 823 | #define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS) |
bogdanm | 0:9b334a45a8ff | 824 | /** |
bogdanm | 0:9b334a45a8ff | 825 | * @} |
bogdanm | 0:9b334a45a8ff | 826 | */ |
bogdanm | 0:9b334a45a8ff | 827 | |
bogdanm | 0:9b334a45a8ff | 828 | /** @defgroup FMC_Access_Mode FMC Access Mode |
bogdanm | 0:9b334a45a8ff | 829 | * @{ |
bogdanm | 0:9b334a45a8ff | 830 | */ |
bogdanm | 0:9b334a45a8ff | 831 | #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 832 | #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000) |
bogdanm | 0:9b334a45a8ff | 833 | #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000) |
bogdanm | 0:9b334a45a8ff | 834 | #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000) |
bogdanm | 0:9b334a45a8ff | 835 | /** |
bogdanm | 0:9b334a45a8ff | 836 | * @} |
bogdanm | 0:9b334a45a8ff | 837 | */ |
bogdanm | 0:9b334a45a8ff | 838 | |
bogdanm | 0:9b334a45a8ff | 839 | /** |
bogdanm | 0:9b334a45a8ff | 840 | * @} |
bogdanm | 0:9b334a45a8ff | 841 | */ |
bogdanm | 0:9b334a45a8ff | 842 | |
bogdanm | 0:9b334a45a8ff | 843 | /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller |
bogdanm | 0:9b334a45a8ff | 844 | * @{ |
bogdanm | 0:9b334a45a8ff | 845 | */ |
bogdanm | 0:9b334a45a8ff | 846 | /** @defgroup FMC_NAND_Bank FMC NAND Bank |
bogdanm | 0:9b334a45a8ff | 847 | * @{ |
bogdanm | 0:9b334a45a8ff | 848 | */ |
bogdanm | 0:9b334a45a8ff | 849 | #define FMC_NAND_BANK3 ((uint32_t)0x00000100) |
bogdanm | 0:9b334a45a8ff | 850 | /** |
bogdanm | 0:9b334a45a8ff | 851 | * @} |
bogdanm | 0:9b334a45a8ff | 852 | */ |
bogdanm | 0:9b334a45a8ff | 853 | |
bogdanm | 0:9b334a45a8ff | 854 | /** @defgroup FMC_Wait_feature FMC Wait feature |
bogdanm | 0:9b334a45a8ff | 855 | * @{ |
bogdanm | 0:9b334a45a8ff | 856 | */ |
bogdanm | 0:9b334a45a8ff | 857 | #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 858 | #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) |
bogdanm | 0:9b334a45a8ff | 859 | /** |
bogdanm | 0:9b334a45a8ff | 860 | * @} |
bogdanm | 0:9b334a45a8ff | 861 | */ |
bogdanm | 0:9b334a45a8ff | 862 | |
bogdanm | 0:9b334a45a8ff | 863 | /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type |
bogdanm | 0:9b334a45a8ff | 864 | * @{ |
bogdanm | 0:9b334a45a8ff | 865 | */ |
bogdanm | 0:9b334a45a8ff | 866 | #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008) |
bogdanm | 0:9b334a45a8ff | 867 | /** |
bogdanm | 0:9b334a45a8ff | 868 | * @} |
bogdanm | 0:9b334a45a8ff | 869 | */ |
bogdanm | 0:9b334a45a8ff | 870 | |
bogdanm | 0:9b334a45a8ff | 871 | /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width |
bogdanm | 0:9b334a45a8ff | 872 | * @{ |
bogdanm | 0:9b334a45a8ff | 873 | */ |
bogdanm | 0:9b334a45a8ff | 874 | #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 875 | #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) |
bogdanm | 0:9b334a45a8ff | 876 | /** |
bogdanm | 0:9b334a45a8ff | 877 | * @} |
bogdanm | 0:9b334a45a8ff | 878 | */ |
bogdanm | 0:9b334a45a8ff | 879 | |
bogdanm | 0:9b334a45a8ff | 880 | /** @defgroup FMC_ECC FMC ECC |
bogdanm | 0:9b334a45a8ff | 881 | * @{ |
bogdanm | 0:9b334a45a8ff | 882 | */ |
bogdanm | 0:9b334a45a8ff | 883 | #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 884 | #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040) |
bogdanm | 0:9b334a45a8ff | 885 | /** |
bogdanm | 0:9b334a45a8ff | 886 | * @} |
bogdanm | 0:9b334a45a8ff | 887 | */ |
bogdanm | 0:9b334a45a8ff | 888 | |
bogdanm | 0:9b334a45a8ff | 889 | /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size |
bogdanm | 0:9b334a45a8ff | 890 | * @{ |
bogdanm | 0:9b334a45a8ff | 891 | */ |
bogdanm | 0:9b334a45a8ff | 892 | #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 893 | #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000) |
bogdanm | 0:9b334a45a8ff | 894 | #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000) |
bogdanm | 0:9b334a45a8ff | 895 | #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000) |
bogdanm | 0:9b334a45a8ff | 896 | #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000) |
bogdanm | 0:9b334a45a8ff | 897 | #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000) |
bogdanm | 0:9b334a45a8ff | 898 | /** |
bogdanm | 0:9b334a45a8ff | 899 | * @} |
bogdanm | 0:9b334a45a8ff | 900 | */ |
bogdanm | 0:9b334a45a8ff | 901 | |
bogdanm | 0:9b334a45a8ff | 902 | /** |
bogdanm | 0:9b334a45a8ff | 903 | * @} |
bogdanm | 0:9b334a45a8ff | 904 | */ |
bogdanm | 0:9b334a45a8ff | 905 | |
bogdanm | 0:9b334a45a8ff | 906 | /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller |
bogdanm | 0:9b334a45a8ff | 907 | * @{ |
bogdanm | 0:9b334a45a8ff | 908 | */ |
bogdanm | 0:9b334a45a8ff | 909 | /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank |
bogdanm | 0:9b334a45a8ff | 910 | * @{ |
bogdanm | 0:9b334a45a8ff | 911 | */ |
bogdanm | 0:9b334a45a8ff | 912 | #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 913 | #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001) |
bogdanm | 0:9b334a45a8ff | 914 | /** |
bogdanm | 0:9b334a45a8ff | 915 | * @} |
bogdanm | 0:9b334a45a8ff | 916 | */ |
bogdanm | 0:9b334a45a8ff | 917 | |
bogdanm | 0:9b334a45a8ff | 918 | /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number |
bogdanm | 0:9b334a45a8ff | 919 | * @{ |
bogdanm | 0:9b334a45a8ff | 920 | */ |
bogdanm | 0:9b334a45a8ff | 921 | #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 922 | #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001) |
bogdanm | 0:9b334a45a8ff | 923 | #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002) |
bogdanm | 0:9b334a45a8ff | 924 | #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003) |
bogdanm | 0:9b334a45a8ff | 925 | /** |
bogdanm | 0:9b334a45a8ff | 926 | * @} |
bogdanm | 0:9b334a45a8ff | 927 | */ |
bogdanm | 0:9b334a45a8ff | 928 | |
bogdanm | 0:9b334a45a8ff | 929 | /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number |
bogdanm | 0:9b334a45a8ff | 930 | * @{ |
bogdanm | 0:9b334a45a8ff | 931 | */ |
bogdanm | 0:9b334a45a8ff | 932 | #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 933 | #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004) |
bogdanm | 0:9b334a45a8ff | 934 | #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008) |
bogdanm | 0:9b334a45a8ff | 935 | /** |
bogdanm | 0:9b334a45a8ff | 936 | * @} |
bogdanm | 0:9b334a45a8ff | 937 | */ |
bogdanm | 0:9b334a45a8ff | 938 | |
bogdanm | 0:9b334a45a8ff | 939 | /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width |
bogdanm | 0:9b334a45a8ff | 940 | * @{ |
bogdanm | 0:9b334a45a8ff | 941 | */ |
bogdanm | 0:9b334a45a8ff | 942 | #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 943 | #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) |
bogdanm | 0:9b334a45a8ff | 944 | #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) |
bogdanm | 0:9b334a45a8ff | 945 | /** |
bogdanm | 0:9b334a45a8ff | 946 | * @} |
bogdanm | 0:9b334a45a8ff | 947 | */ |
bogdanm | 0:9b334a45a8ff | 948 | |
bogdanm | 0:9b334a45a8ff | 949 | /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number |
bogdanm | 0:9b334a45a8ff | 950 | * @{ |
bogdanm | 0:9b334a45a8ff | 951 | */ |
bogdanm | 0:9b334a45a8ff | 952 | #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 953 | #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040) |
bogdanm | 0:9b334a45a8ff | 954 | /** |
bogdanm | 0:9b334a45a8ff | 955 | * @} |
bogdanm | 0:9b334a45a8ff | 956 | */ |
bogdanm | 0:9b334a45a8ff | 957 | |
bogdanm | 0:9b334a45a8ff | 958 | /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency |
bogdanm | 0:9b334a45a8ff | 959 | * @{ |
bogdanm | 0:9b334a45a8ff | 960 | */ |
bogdanm | 0:9b334a45a8ff | 961 | #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080) |
bogdanm | 0:9b334a45a8ff | 962 | #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100) |
bogdanm | 0:9b334a45a8ff | 963 | #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180) |
bogdanm | 0:9b334a45a8ff | 964 | /** |
bogdanm | 0:9b334a45a8ff | 965 | * @} |
bogdanm | 0:9b334a45a8ff | 966 | */ |
bogdanm | 0:9b334a45a8ff | 967 | |
bogdanm | 0:9b334a45a8ff | 968 | /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection |
bogdanm | 0:9b334a45a8ff | 969 | * @{ |
bogdanm | 0:9b334a45a8ff | 970 | */ |
bogdanm | 0:9b334a45a8ff | 971 | #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 972 | #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200) |
bogdanm | 0:9b334a45a8ff | 973 | /** |
bogdanm | 0:9b334a45a8ff | 974 | * @} |
bogdanm | 0:9b334a45a8ff | 975 | */ |
bogdanm | 0:9b334a45a8ff | 976 | |
bogdanm | 0:9b334a45a8ff | 977 | /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period |
bogdanm | 0:9b334a45a8ff | 978 | * @{ |
bogdanm | 0:9b334a45a8ff | 979 | */ |
bogdanm | 0:9b334a45a8ff | 980 | #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 981 | #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800) |
bogdanm | 0:9b334a45a8ff | 982 | #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00) |
bogdanm | 0:9b334a45a8ff | 983 | /** |
bogdanm | 0:9b334a45a8ff | 984 | * @} |
bogdanm | 0:9b334a45a8ff | 985 | */ |
bogdanm | 0:9b334a45a8ff | 986 | |
bogdanm | 0:9b334a45a8ff | 987 | /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst |
bogdanm | 0:9b334a45a8ff | 988 | * @{ |
bogdanm | 0:9b334a45a8ff | 989 | */ |
bogdanm | 0:9b334a45a8ff | 990 | #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 991 | #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000) |
bogdanm | 0:9b334a45a8ff | 992 | /** |
bogdanm | 0:9b334a45a8ff | 993 | * @} |
bogdanm | 0:9b334a45a8ff | 994 | */ |
bogdanm | 0:9b334a45a8ff | 995 | |
bogdanm | 0:9b334a45a8ff | 996 | /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay |
bogdanm | 0:9b334a45a8ff | 997 | * @{ |
bogdanm | 0:9b334a45a8ff | 998 | */ |
bogdanm | 0:9b334a45a8ff | 999 | #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 1000 | #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000) |
bogdanm | 0:9b334a45a8ff | 1001 | #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000) |
bogdanm | 0:9b334a45a8ff | 1002 | /** |
bogdanm | 0:9b334a45a8ff | 1003 | * @} |
bogdanm | 0:9b334a45a8ff | 1004 | */ |
bogdanm | 0:9b334a45a8ff | 1005 | |
bogdanm | 0:9b334a45a8ff | 1006 | /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode |
bogdanm | 0:9b334a45a8ff | 1007 | * @{ |
bogdanm | 0:9b334a45a8ff | 1008 | */ |
bogdanm | 0:9b334a45a8ff | 1009 | #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 1010 | #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001) |
bogdanm | 0:9b334a45a8ff | 1011 | #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002) |
bogdanm | 0:9b334a45a8ff | 1012 | #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003) |
bogdanm | 0:9b334a45a8ff | 1013 | #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004) |
bogdanm | 0:9b334a45a8ff | 1014 | #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005) |
bogdanm | 0:9b334a45a8ff | 1015 | #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006) |
bogdanm | 0:9b334a45a8ff | 1016 | /** |
bogdanm | 0:9b334a45a8ff | 1017 | * @} |
bogdanm | 0:9b334a45a8ff | 1018 | */ |
bogdanm | 0:9b334a45a8ff | 1019 | |
bogdanm | 0:9b334a45a8ff | 1020 | /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target |
bogdanm | 0:9b334a45a8ff | 1021 | * @{ |
bogdanm | 0:9b334a45a8ff | 1022 | */ |
bogdanm | 0:9b334a45a8ff | 1023 | #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 |
bogdanm | 0:9b334a45a8ff | 1024 | #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 |
bogdanm | 0:9b334a45a8ff | 1025 | #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018) |
bogdanm | 0:9b334a45a8ff | 1026 | /** |
bogdanm | 0:9b334a45a8ff | 1027 | * @} |
bogdanm | 0:9b334a45a8ff | 1028 | */ |
bogdanm | 0:9b334a45a8ff | 1029 | |
bogdanm | 0:9b334a45a8ff | 1030 | /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status |
bogdanm | 0:9b334a45a8ff | 1031 | * @{ |
bogdanm | 0:9b334a45a8ff | 1032 | */ |
bogdanm | 0:9b334a45a8ff | 1033 | #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000) |
bogdanm | 0:9b334a45a8ff | 1034 | #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 |
bogdanm | 0:9b334a45a8ff | 1035 | #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 |
bogdanm | 0:9b334a45a8ff | 1036 | /** |
bogdanm | 0:9b334a45a8ff | 1037 | * @} |
bogdanm | 0:9b334a45a8ff | 1038 | */ |
bogdanm | 0:9b334a45a8ff | 1039 | |
bogdanm | 0:9b334a45a8ff | 1040 | /** |
bogdanm | 0:9b334a45a8ff | 1041 | * @} |
bogdanm | 0:9b334a45a8ff | 1042 | */ |
bogdanm | 0:9b334a45a8ff | 1043 | |
bogdanm | 0:9b334a45a8ff | 1044 | /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition |
bogdanm | 0:9b334a45a8ff | 1045 | * @{ |
bogdanm | 0:9b334a45a8ff | 1046 | */ |
bogdanm | 0:9b334a45a8ff | 1047 | #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008) |
bogdanm | 0:9b334a45a8ff | 1048 | #define FMC_IT_LEVEL ((uint32_t)0x00000010) |
bogdanm | 0:9b334a45a8ff | 1049 | #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020) |
bogdanm | 0:9b334a45a8ff | 1050 | #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000) |
bogdanm | 0:9b334a45a8ff | 1051 | /** |
bogdanm | 0:9b334a45a8ff | 1052 | * @} |
bogdanm | 0:9b334a45a8ff | 1053 | */ |
bogdanm | 0:9b334a45a8ff | 1054 | |
bogdanm | 0:9b334a45a8ff | 1055 | /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition |
bogdanm | 0:9b334a45a8ff | 1056 | * @{ |
bogdanm | 0:9b334a45a8ff | 1057 | */ |
bogdanm | 0:9b334a45a8ff | 1058 | #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001) |
bogdanm | 0:9b334a45a8ff | 1059 | #define FMC_FLAG_LEVEL ((uint32_t)0x00000002) |
bogdanm | 0:9b334a45a8ff | 1060 | #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004) |
bogdanm | 0:9b334a45a8ff | 1061 | #define FMC_FLAG_FEMPT ((uint32_t)0x00000040) |
bogdanm | 0:9b334a45a8ff | 1062 | #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE |
bogdanm | 0:9b334a45a8ff | 1063 | #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY |
bogdanm | 0:9b334a45a8ff | 1064 | #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE |
bogdanm | 0:9b334a45a8ff | 1065 | /** |
bogdanm | 0:9b334a45a8ff | 1066 | * @} |
bogdanm | 0:9b334a45a8ff | 1067 | */ |
bogdanm | 0:9b334a45a8ff | 1068 | /** |
bogdanm | 0:9b334a45a8ff | 1069 | * @} |
bogdanm | 0:9b334a45a8ff | 1070 | */ |
bogdanm | 0:9b334a45a8ff | 1071 | |
bogdanm | 0:9b334a45a8ff | 1072 | /** |
bogdanm | 0:9b334a45a8ff | 1073 | * @} |
bogdanm | 0:9b334a45a8ff | 1074 | */ |
bogdanm | 0:9b334a45a8ff | 1075 | |
bogdanm | 0:9b334a45a8ff | 1076 | /* Private macro -------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1077 | /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros |
bogdanm | 0:9b334a45a8ff | 1078 | * @{ |
bogdanm | 0:9b334a45a8ff | 1079 | */ |
bogdanm | 0:9b334a45a8ff | 1080 | |
bogdanm | 0:9b334a45a8ff | 1081 | /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros |
bogdanm | 0:9b334a45a8ff | 1082 | * @brief macros to handle NOR device enable/disable and read/write operations |
bogdanm | 0:9b334a45a8ff | 1083 | * @{ |
bogdanm | 0:9b334a45a8ff | 1084 | */ |
bogdanm | 0:9b334a45a8ff | 1085 | |
bogdanm | 0:9b334a45a8ff | 1086 | /** |
bogdanm | 0:9b334a45a8ff | 1087 | * @brief Enable the NORSRAM device access. |
bogdanm | 0:9b334a45a8ff | 1088 | * @param __INSTANCE__: FMC_NORSRAM Instance |
bogdanm | 0:9b334a45a8ff | 1089 | * @param __BANK__: FMC_NORSRAM Bank |
bogdanm | 0:9b334a45a8ff | 1090 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1091 | */ |
bogdanm | 0:9b334a45a8ff | 1092 | #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN) |
bogdanm | 0:9b334a45a8ff | 1093 | |
bogdanm | 0:9b334a45a8ff | 1094 | /** |
bogdanm | 0:9b334a45a8ff | 1095 | * @brief Disable the NORSRAM device access. |
bogdanm | 0:9b334a45a8ff | 1096 | * @param __INSTANCE__: FMC_NORSRAM Instance |
bogdanm | 0:9b334a45a8ff | 1097 | * @param __BANK__: FMC_NORSRAM Bank |
bogdanm | 0:9b334a45a8ff | 1098 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1099 | */ |
bogdanm | 0:9b334a45a8ff | 1100 | #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) |
bogdanm | 0:9b334a45a8ff | 1101 | |
bogdanm | 0:9b334a45a8ff | 1102 | /** |
bogdanm | 0:9b334a45a8ff | 1103 | * @} |
bogdanm | 0:9b334a45a8ff | 1104 | */ |
bogdanm | 0:9b334a45a8ff | 1105 | |
bogdanm | 0:9b334a45a8ff | 1106 | /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros |
bogdanm | 0:9b334a45a8ff | 1107 | * @brief macros to handle NAND device enable/disable |
bogdanm | 0:9b334a45a8ff | 1108 | * @{ |
bogdanm | 0:9b334a45a8ff | 1109 | */ |
bogdanm | 0:9b334a45a8ff | 1110 | |
bogdanm | 0:9b334a45a8ff | 1111 | /** |
bogdanm | 0:9b334a45a8ff | 1112 | * @brief Enable the NAND device access. |
bogdanm | 0:9b334a45a8ff | 1113 | * @param __INSTANCE__: FMC_NAND Instance |
bogdanm | 0:9b334a45a8ff | 1114 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1115 | */ |
bogdanm | 0:9b334a45a8ff | 1116 | #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) |
bogdanm | 0:9b334a45a8ff | 1117 | |
bogdanm | 0:9b334a45a8ff | 1118 | /** |
bogdanm | 0:9b334a45a8ff | 1119 | * @brief Disable the NAND device access. |
bogdanm | 0:9b334a45a8ff | 1120 | * @param __INSTANCE__: FMC_NAND Instance |
bogdanm | 0:9b334a45a8ff | 1121 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1122 | */ |
bogdanm | 0:9b334a45a8ff | 1123 | #define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) |
bogdanm | 0:9b334a45a8ff | 1124 | |
bogdanm | 0:9b334a45a8ff | 1125 | /** |
bogdanm | 0:9b334a45a8ff | 1126 | * @} |
bogdanm | 0:9b334a45a8ff | 1127 | */ |
bogdanm | 0:9b334a45a8ff | 1128 | |
bogdanm | 0:9b334a45a8ff | 1129 | /** @defgroup FMC_Interrupt FMC Interrupt |
bogdanm | 0:9b334a45a8ff | 1130 | * @brief macros to handle FMC interrupts |
bogdanm | 0:9b334a45a8ff | 1131 | * @{ |
bogdanm | 0:9b334a45a8ff | 1132 | */ |
bogdanm | 0:9b334a45a8ff | 1133 | |
bogdanm | 0:9b334a45a8ff | 1134 | /** |
bogdanm | 0:9b334a45a8ff | 1135 | * @brief Enable the NAND device interrupt. |
bogdanm | 0:9b334a45a8ff | 1136 | * @param __INSTANCE__: FMC_NAND instance |
bogdanm | 0:9b334a45a8ff | 1137 | * @param __INTERRUPT__: FMC_NAND interrupt |
bogdanm | 0:9b334a45a8ff | 1138 | * This parameter can be any combination of the following values: |
bogdanm | 0:9b334a45a8ff | 1139 | * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. |
bogdanm | 0:9b334a45a8ff | 1140 | * @arg FMC_IT_LEVEL: Interrupt level. |
bogdanm | 0:9b334a45a8ff | 1141 | * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. |
bogdanm | 0:9b334a45a8ff | 1142 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1143 | */ |
bogdanm | 0:9b334a45a8ff | 1144 | #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) |
bogdanm | 0:9b334a45a8ff | 1145 | |
bogdanm | 0:9b334a45a8ff | 1146 | /** |
bogdanm | 0:9b334a45a8ff | 1147 | * @brief Disable the NAND device interrupt. |
bogdanm | 0:9b334a45a8ff | 1148 | * @param __INSTANCE__: FMC_NAND Instance |
bogdanm | 0:9b334a45a8ff | 1149 | * @param __INTERRUPT__: FMC_NAND interrupt |
bogdanm | 0:9b334a45a8ff | 1150 | * This parameter can be any combination of the following values: |
bogdanm | 0:9b334a45a8ff | 1151 | * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. |
bogdanm | 0:9b334a45a8ff | 1152 | * @arg FMC_IT_LEVEL: Interrupt level. |
bogdanm | 0:9b334a45a8ff | 1153 | * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. |
bogdanm | 0:9b334a45a8ff | 1154 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1155 | */ |
bogdanm | 0:9b334a45a8ff | 1156 | #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) |
bogdanm | 0:9b334a45a8ff | 1157 | |
bogdanm | 0:9b334a45a8ff | 1158 | /** |
bogdanm | 0:9b334a45a8ff | 1159 | * @brief Get flag status of the NAND device. |
bogdanm | 0:9b334a45a8ff | 1160 | * @param __INSTANCE__: FMC_NAND Instance |
bogdanm | 0:9b334a45a8ff | 1161 | * @param __BANK__: FMC_NAND Bank |
bogdanm | 0:9b334a45a8ff | 1162 | * @param __FLAG__: FMC_NAND flag |
bogdanm | 0:9b334a45a8ff | 1163 | * This parameter can be any combination of the following values: |
bogdanm | 0:9b334a45a8ff | 1164 | * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
bogdanm | 0:9b334a45a8ff | 1165 | * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. |
bogdanm | 0:9b334a45a8ff | 1166 | * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
bogdanm | 0:9b334a45a8ff | 1167 | * @arg FMC_FLAG_FEMPT: FIFO empty flag. |
bogdanm | 0:9b334a45a8ff | 1168 | * @retval The state of FLAG (SET or RESET). |
bogdanm | 0:9b334a45a8ff | 1169 | */ |
bogdanm | 0:9b334a45a8ff | 1170 | #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) |
bogdanm | 0:9b334a45a8ff | 1171 | |
bogdanm | 0:9b334a45a8ff | 1172 | /** |
bogdanm | 0:9b334a45a8ff | 1173 | * @brief Clear flag status of the NAND device. |
bogdanm | 0:9b334a45a8ff | 1174 | * @param __INSTANCE__: FMC_NAND Instance |
bogdanm | 0:9b334a45a8ff | 1175 | * @param __FLAG__: FMC_NAND flag |
bogdanm | 0:9b334a45a8ff | 1176 | * This parameter can be any combination of the following values: |
bogdanm | 0:9b334a45a8ff | 1177 | * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
bogdanm | 0:9b334a45a8ff | 1178 | * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. |
bogdanm | 0:9b334a45a8ff | 1179 | * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
bogdanm | 0:9b334a45a8ff | 1180 | * @arg FMC_FLAG_FEMPT: FIFO empty flag. |
bogdanm | 0:9b334a45a8ff | 1181 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1182 | */ |
bogdanm | 0:9b334a45a8ff | 1183 | #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) |
bogdanm | 0:9b334a45a8ff | 1184 | |
bogdanm | 0:9b334a45a8ff | 1185 | /** |
bogdanm | 0:9b334a45a8ff | 1186 | * @brief Enable the SDRAM device interrupt. |
bogdanm | 0:9b334a45a8ff | 1187 | * @param __INSTANCE__: FMC_SDRAM instance |
bogdanm | 0:9b334a45a8ff | 1188 | * @param __INTERRUPT__: FMC_SDRAM interrupt |
bogdanm | 0:9b334a45a8ff | 1189 | * This parameter can be any combination of the following values: |
bogdanm | 0:9b334a45a8ff | 1190 | * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error |
bogdanm | 0:9b334a45a8ff | 1191 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1192 | */ |
bogdanm | 0:9b334a45a8ff | 1193 | #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) |
bogdanm | 0:9b334a45a8ff | 1194 | |
bogdanm | 0:9b334a45a8ff | 1195 | /** |
bogdanm | 0:9b334a45a8ff | 1196 | * @brief Disable the SDRAM device interrupt. |
bogdanm | 0:9b334a45a8ff | 1197 | * @param __INSTANCE__: FMC_SDRAM instance |
bogdanm | 0:9b334a45a8ff | 1198 | * @param __INTERRUPT__: FMC_SDRAM interrupt |
bogdanm | 0:9b334a45a8ff | 1199 | * This parameter can be any combination of the following values: |
bogdanm | 0:9b334a45a8ff | 1200 | * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error |
bogdanm | 0:9b334a45a8ff | 1201 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1202 | */ |
bogdanm | 0:9b334a45a8ff | 1203 | #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) |
bogdanm | 0:9b334a45a8ff | 1204 | |
bogdanm | 0:9b334a45a8ff | 1205 | /** |
bogdanm | 0:9b334a45a8ff | 1206 | * @brief Get flag status of the SDRAM device. |
bogdanm | 0:9b334a45a8ff | 1207 | * @param __INSTANCE__: FMC_SDRAM instance |
bogdanm | 0:9b334a45a8ff | 1208 | * @param __FLAG__: FMC_SDRAM flag |
bogdanm | 0:9b334a45a8ff | 1209 | * This parameter can be any combination of the following values: |
bogdanm | 0:9b334a45a8ff | 1210 | * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. |
bogdanm | 0:9b334a45a8ff | 1211 | * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. |
bogdanm | 0:9b334a45a8ff | 1212 | * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. |
bogdanm | 0:9b334a45a8ff | 1213 | * @retval The state of FLAG (SET or RESET). |
bogdanm | 0:9b334a45a8ff | 1214 | */ |
bogdanm | 0:9b334a45a8ff | 1215 | #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) |
bogdanm | 0:9b334a45a8ff | 1216 | |
bogdanm | 0:9b334a45a8ff | 1217 | /** |
bogdanm | 0:9b334a45a8ff | 1218 | * @brief Clear flag status of the SDRAM device. |
bogdanm | 0:9b334a45a8ff | 1219 | * @param __INSTANCE__: FMC_SDRAM instance |
bogdanm | 0:9b334a45a8ff | 1220 | * @param __FLAG__: FMC_SDRAM flag |
bogdanm | 0:9b334a45a8ff | 1221 | * This parameter can be any combination of the following values: |
bogdanm | 0:9b334a45a8ff | 1222 | * @arg FMC_SDRAM_FLAG_REFRESH_ERROR |
bogdanm | 0:9b334a45a8ff | 1223 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1224 | */ |
bogdanm | 0:9b334a45a8ff | 1225 | #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) |
bogdanm | 0:9b334a45a8ff | 1226 | /** |
bogdanm | 0:9b334a45a8ff | 1227 | * @} |
bogdanm | 0:9b334a45a8ff | 1228 | */ |
bogdanm | 0:9b334a45a8ff | 1229 | |
bogdanm | 0:9b334a45a8ff | 1230 | /** |
bogdanm | 0:9b334a45a8ff | 1231 | * @} |
bogdanm | 0:9b334a45a8ff | 1232 | */ |
bogdanm | 0:9b334a45a8ff | 1233 | |
bogdanm | 0:9b334a45a8ff | 1234 | /* Private functions ---------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 1235 | /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions |
bogdanm | 0:9b334a45a8ff | 1236 | * @{ |
bogdanm | 0:9b334a45a8ff | 1237 | */ |
bogdanm | 0:9b334a45a8ff | 1238 | |
bogdanm | 0:9b334a45a8ff | 1239 | /** @defgroup FMC_LL_NORSRAM NOR SRAM |
bogdanm | 0:9b334a45a8ff | 1240 | * @{ |
bogdanm | 0:9b334a45a8ff | 1241 | */ |
bogdanm | 0:9b334a45a8ff | 1242 | /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions |
bogdanm | 0:9b334a45a8ff | 1243 | * @{ |
bogdanm | 0:9b334a45a8ff | 1244 | */ |
bogdanm | 0:9b334a45a8ff | 1245 | HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); |
bogdanm | 0:9b334a45a8ff | 1246 | HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1247 | HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
bogdanm | 0:9b334a45a8ff | 1248 | HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1249 | /** |
bogdanm | 0:9b334a45a8ff | 1250 | * @} |
bogdanm | 0:9b334a45a8ff | 1251 | */ |
bogdanm | 0:9b334a45a8ff | 1252 | |
bogdanm | 0:9b334a45a8ff | 1253 | /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions |
bogdanm | 0:9b334a45a8ff | 1254 | * @{ |
bogdanm | 0:9b334a45a8ff | 1255 | */ |
bogdanm | 0:9b334a45a8ff | 1256 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1257 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1258 | /** |
bogdanm | 0:9b334a45a8ff | 1259 | * @} |
bogdanm | 0:9b334a45a8ff | 1260 | */ |
bogdanm | 0:9b334a45a8ff | 1261 | /** |
bogdanm | 0:9b334a45a8ff | 1262 | * @} |
bogdanm | 0:9b334a45a8ff | 1263 | */ |
bogdanm | 0:9b334a45a8ff | 1264 | |
bogdanm | 0:9b334a45a8ff | 1265 | /** @defgroup FMC_LL_NAND NAND |
bogdanm | 0:9b334a45a8ff | 1266 | * @{ |
bogdanm | 0:9b334a45a8ff | 1267 | */ |
bogdanm | 0:9b334a45a8ff | 1268 | /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions |
bogdanm | 0:9b334a45a8ff | 1269 | * @{ |
bogdanm | 0:9b334a45a8ff | 1270 | */ |
bogdanm | 0:9b334a45a8ff | 1271 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); |
bogdanm | 0:9b334a45a8ff | 1272 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1273 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1274 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1275 | /** |
bogdanm | 0:9b334a45a8ff | 1276 | * @} |
bogdanm | 0:9b334a45a8ff | 1277 | */ |
bogdanm | 0:9b334a45a8ff | 1278 | |
bogdanm | 0:9b334a45a8ff | 1279 | /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions |
bogdanm | 0:9b334a45a8ff | 1280 | * @{ |
bogdanm | 0:9b334a45a8ff | 1281 | */ |
bogdanm | 0:9b334a45a8ff | 1282 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1283 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1284 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); |
bogdanm | 0:9b334a45a8ff | 1285 | /** |
bogdanm | 0:9b334a45a8ff | 1286 | * @} |
bogdanm | 0:9b334a45a8ff | 1287 | */ |
bogdanm | 0:9b334a45a8ff | 1288 | |
bogdanm | 0:9b334a45a8ff | 1289 | /** @defgroup FMC_LL_SDRAM SDRAM |
bogdanm | 0:9b334a45a8ff | 1290 | * @{ |
bogdanm | 0:9b334a45a8ff | 1291 | */ |
bogdanm | 0:9b334a45a8ff | 1292 | /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions |
bogdanm | 0:9b334a45a8ff | 1293 | * @{ |
bogdanm | 0:9b334a45a8ff | 1294 | */ |
bogdanm | 0:9b334a45a8ff | 1295 | HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); |
bogdanm | 0:9b334a45a8ff | 1296 | HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1297 | HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1298 | |
bogdanm | 0:9b334a45a8ff | 1299 | /** |
bogdanm | 0:9b334a45a8ff | 1300 | * @} |
bogdanm | 0:9b334a45a8ff | 1301 | */ |
bogdanm | 0:9b334a45a8ff | 1302 | |
bogdanm | 0:9b334a45a8ff | 1303 | /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions |
bogdanm | 0:9b334a45a8ff | 1304 | * @{ |
bogdanm | 0:9b334a45a8ff | 1305 | */ |
bogdanm | 0:9b334a45a8ff | 1306 | HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1307 | HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1308 | HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); |
bogdanm | 0:9b334a45a8ff | 1309 | HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); |
bogdanm | 0:9b334a45a8ff | 1310 | HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); |
bogdanm | 0:9b334a45a8ff | 1311 | uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); |
bogdanm | 0:9b334a45a8ff | 1312 | /** |
bogdanm | 0:9b334a45a8ff | 1313 | * @} |
bogdanm | 0:9b334a45a8ff | 1314 | */ |
bogdanm | 0:9b334a45a8ff | 1315 | |
bogdanm | 0:9b334a45a8ff | 1316 | /** |
bogdanm | 0:9b334a45a8ff | 1317 | * @} |
bogdanm | 0:9b334a45a8ff | 1318 | */ |
bogdanm | 0:9b334a45a8ff | 1319 | |
bogdanm | 0:9b334a45a8ff | 1320 | /** |
bogdanm | 0:9b334a45a8ff | 1321 | * @} |
bogdanm | 0:9b334a45a8ff | 1322 | */ |
bogdanm | 0:9b334a45a8ff | 1323 | |
bogdanm | 0:9b334a45a8ff | 1324 | /** |
bogdanm | 0:9b334a45a8ff | 1325 | * @} |
bogdanm | 0:9b334a45a8ff | 1326 | */ |
bogdanm | 0:9b334a45a8ff | 1327 | |
bogdanm | 0:9b334a45a8ff | 1328 | /** |
bogdanm | 0:9b334a45a8ff | 1329 | * @} |
bogdanm | 0:9b334a45a8ff | 1330 | */ |
bogdanm | 0:9b334a45a8ff | 1331 | #ifdef __cplusplus |
bogdanm | 0:9b334a45a8ff | 1332 | } |
bogdanm | 0:9b334a45a8ff | 1333 | #endif |
bogdanm | 0:9b334a45a8ff | 1334 | |
bogdanm | 0:9b334a45a8ff | 1335 | #endif /* __STM32F7xx_LL_FMC_H */ |
bogdanm | 0:9b334a45a8ff | 1336 | |
bogdanm | 0:9b334a45a8ff | 1337 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |