en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
83:a036322b8637
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f7xx_hal_sram.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.1
bogdanm 0:9b334a45a8ff 6 * @date 25-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief SRAM HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides a generic firmware to drive SRAM memories
bogdanm 0:9b334a45a8ff 9 * mounted as external device.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 @verbatim
bogdanm 0:9b334a45a8ff 12 ==============================================================================
bogdanm 0:9b334a45a8ff 13 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 [..]
bogdanm 0:9b334a45a8ff 16 This driver is a generic layered driver which contains a set of APIs used to
bogdanm 0:9b334a45a8ff 17 control SRAM memories. It uses the FMC layer functions to interface
bogdanm 0:9b334a45a8ff 18 with SRAM devices.
bogdanm 0:9b334a45a8ff 19 The following sequence should be followed to configure the FMC to interface
bogdanm 0:9b334a45a8ff 20 with SRAM/PSRAM memories:
bogdanm 0:9b334a45a8ff 21
bogdanm 0:9b334a45a8ff 22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
bogdanm 0:9b334a45a8ff 23 SRAM_HandleTypeDef hsram; and:
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
bogdanm 0:9b334a45a8ff 26 values of the structure member.
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
bogdanm 0:9b334a45a8ff 29 base register instance for NOR or SRAM device
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
bogdanm 0:9b334a45a8ff 32 base register instance for NOR or SRAM extended mode
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
bogdanm 0:9b334a45a8ff 35 mode timings; for example:
bogdanm 0:9b334a45a8ff 36 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
bogdanm 0:9b334a45a8ff 37 and fill its fields with the allowed values of the structure member.
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
bogdanm 0:9b334a45a8ff 40 performs the following sequence:
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
bogdanm 0:9b334a45a8ff 43 (##) Control register configuration using the FMC NORSRAM interface function
bogdanm 0:9b334a45a8ff 44 FMC_NORSRAM_Init()
bogdanm 0:9b334a45a8ff 45 (##) Timing register configuration using the FMC NORSRAM interface function
bogdanm 0:9b334a45a8ff 46 FMC_NORSRAM_Timing_Init()
bogdanm 0:9b334a45a8ff 47 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
bogdanm 0:9b334a45a8ff 48 FMC_NORSRAM_Extended_Timing_Init()
bogdanm 0:9b334a45a8ff 49 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 (#) At this stage you can perform read/write accesses from/to the memory connected
bogdanm 0:9b334a45a8ff 52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
bogdanm 0:9b334a45a8ff 53 following APIs:
bogdanm 0:9b334a45a8ff 54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
bogdanm 0:9b334a45a8ff 55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
bogdanm 0:9b334a45a8ff 58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 (#) You can continuously monitor the SRAM device HAL state by calling the function
bogdanm 0:9b334a45a8ff 61 HAL_SRAM_GetState()
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 @endverbatim
bogdanm 0:9b334a45a8ff 64 ******************************************************************************
bogdanm 0:9b334a45a8ff 65 * @attention
bogdanm 0:9b334a45a8ff 66 *
bogdanm 0:9b334a45a8ff 67 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 68 *
bogdanm 0:9b334a45a8ff 69 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 70 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 71 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 72 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 73 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 74 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 75 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 77 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 78 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 79 *
bogdanm 0:9b334a45a8ff 80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 90 *
bogdanm 0:9b334a45a8ff 91 ******************************************************************************
bogdanm 0:9b334a45a8ff 92 */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 95 #include "stm32f7xx_hal.h"
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /** @addtogroup STM32F7xx_HAL_Driver
bogdanm 0:9b334a45a8ff 98 * @{
bogdanm 0:9b334a45a8ff 99 */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /** @defgroup SRAM SRAM
bogdanm 0:9b334a45a8ff 102 * @brief SRAM driver modules
bogdanm 0:9b334a45a8ff 103 * @{
bogdanm 0:9b334a45a8ff 104 */
bogdanm 0:9b334a45a8ff 105 #ifdef HAL_SRAM_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 106 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 107 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 108 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 109 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 110 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 111 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
bogdanm 0:9b334a45a8ff 114 * @{
bogdanm 0:9b334a45a8ff 115 */
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 118 * @brief Initialization and Configuration functions.
bogdanm 0:9b334a45a8ff 119 *
bogdanm 0:9b334a45a8ff 120 @verbatim
bogdanm 0:9b334a45a8ff 121 ==============================================================================
bogdanm 0:9b334a45a8ff 122 ##### SRAM Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 123 ==============================================================================
bogdanm 0:9b334a45a8ff 124 [..] This section provides functions allowing to initialize/de-initialize
bogdanm 0:9b334a45a8ff 125 the SRAM memory
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 @endverbatim
bogdanm 0:9b334a45a8ff 128 * @{
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /**
bogdanm 0:9b334a45a8ff 132 * @brief Performs the SRAM device initialization sequence
bogdanm 0:9b334a45a8ff 133 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 134 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 135 * @param Timing: Pointer to SRAM control timing structure
bogdanm 0:9b334a45a8ff 136 * @param ExtTiming: Pointer to SRAM extended mode timing structure
bogdanm 0:9b334a45a8ff 137 * @retval HAL status
bogdanm 0:9b334a45a8ff 138 */
bogdanm 0:9b334a45a8ff 139 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
bogdanm 0:9b334a45a8ff 140 {
bogdanm 0:9b334a45a8ff 141 /* Check the SRAM handle parameter */
bogdanm 0:9b334a45a8ff 142 if(hsram == NULL)
bogdanm 0:9b334a45a8ff 143 {
bogdanm 0:9b334a45a8ff 144 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 145 }
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 if(hsram->State == HAL_SRAM_STATE_RESET)
bogdanm 0:9b334a45a8ff 148 {
bogdanm 0:9b334a45a8ff 149 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 150 hsram->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 151 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 152 HAL_SRAM_MspInit(hsram);
bogdanm 0:9b334a45a8ff 153 }
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 /* Initialize SRAM control Interface */
bogdanm 0:9b334a45a8ff 156 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 /* Initialize SRAM timing Interface */
bogdanm 0:9b334a45a8ff 159 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /* Initialize SRAM extended mode timing Interface */
bogdanm 0:9b334a45a8ff 162 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 /* Enable the NORSRAM device */
bogdanm 0:9b334a45a8ff 165 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 return HAL_OK;
bogdanm 0:9b334a45a8ff 168 }
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /**
bogdanm 0:9b334a45a8ff 171 * @brief Performs the SRAM device De-initialization sequence.
bogdanm 0:9b334a45a8ff 172 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 173 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 174 * @retval HAL status
bogdanm 0:9b334a45a8ff 175 */
bogdanm 0:9b334a45a8ff 176 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
bogdanm 0:9b334a45a8ff 177 {
bogdanm 0:9b334a45a8ff 178 /* De-Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 179 HAL_SRAM_MspDeInit(hsram);
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 /* Configure the SRAM registers with their reset values */
bogdanm 0:9b334a45a8ff 182 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 hsram->State = HAL_SRAM_STATE_RESET;
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 /* Release Lock */
bogdanm 0:9b334a45a8ff 187 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 return HAL_OK;
bogdanm 0:9b334a45a8ff 190 }
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 /**
bogdanm 0:9b334a45a8ff 193 * @brief SRAM MSP Init.
bogdanm 0:9b334a45a8ff 194 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 195 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 196 * @retval None
bogdanm 0:9b334a45a8ff 197 */
bogdanm 0:9b334a45a8ff 198 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
bogdanm 0:9b334a45a8ff 199 {
bogdanm 0:9b334a45a8ff 200 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 201 the HAL_SRAM_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 202 */
bogdanm 0:9b334a45a8ff 203 }
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 /**
bogdanm 0:9b334a45a8ff 206 * @brief SRAM MSP DeInit.
bogdanm 0:9b334a45a8ff 207 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 208 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 209 * @retval None
bogdanm 0:9b334a45a8ff 210 */
bogdanm 0:9b334a45a8ff 211 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
bogdanm 0:9b334a45a8ff 212 {
bogdanm 0:9b334a45a8ff 213 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 214 the HAL_SRAM_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 215 */
bogdanm 0:9b334a45a8ff 216 }
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /**
bogdanm 0:9b334a45a8ff 219 * @brief DMA transfer complete callback.
bogdanm 0:9b334a45a8ff 220 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 221 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 222 * @retval None
bogdanm 0:9b334a45a8ff 223 */
bogdanm 0:9b334a45a8ff 224 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 225 {
bogdanm 0:9b334a45a8ff 226 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 227 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 228 */
bogdanm 0:9b334a45a8ff 229 }
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 /**
bogdanm 0:9b334a45a8ff 232 * @brief DMA transfer complete error callback.
bogdanm 0:9b334a45a8ff 233 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 234 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 235 * @retval None
bogdanm 0:9b334a45a8ff 236 */
bogdanm 0:9b334a45a8ff 237 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 238 {
bogdanm 0:9b334a45a8ff 239 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 240 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 241 */
bogdanm 0:9b334a45a8ff 242 }
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 /**
bogdanm 0:9b334a45a8ff 245 * @}
bogdanm 0:9b334a45a8ff 246 */
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
bogdanm 0:9b334a45a8ff 249 * @brief Input Output and memory control functions
bogdanm 0:9b334a45a8ff 250 *
bogdanm 0:9b334a45a8ff 251 @verbatim
bogdanm 0:9b334a45a8ff 252 ==============================================================================
bogdanm 0:9b334a45a8ff 253 ##### SRAM Input and Output functions #####
bogdanm 0:9b334a45a8ff 254 ==============================================================================
bogdanm 0:9b334a45a8ff 255 [..]
bogdanm 0:9b334a45a8ff 256 This section provides functions allowing to use and control the SRAM memory
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 @endverbatim
bogdanm 0:9b334a45a8ff 259 * @{
bogdanm 0:9b334a45a8ff 260 */
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /**
bogdanm 0:9b334a45a8ff 263 * @brief Reads 8-bit buffer from SRAM memory.
bogdanm 0:9b334a45a8ff 264 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 265 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 266 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 267 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 268 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 269 * @retval HAL status
bogdanm 0:9b334a45a8ff 270 */
bogdanm 0:9b334a45a8ff 271 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 272 {
bogdanm 0:9b334a45a8ff 273 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 /* Process Locked */
bogdanm 0:9b334a45a8ff 276 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 279 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 280
bogdanm 0:9b334a45a8ff 281 /* Read data from memory */
bogdanm 0:9b334a45a8ff 282 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 283 {
bogdanm 0:9b334a45a8ff 284 *pDstBuffer = *(__IO uint8_t *)psramaddress;
bogdanm 0:9b334a45a8ff 285 pDstBuffer++;
bogdanm 0:9b334a45a8ff 286 psramaddress++;
bogdanm 0:9b334a45a8ff 287 }
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 290 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 /* Process unlocked */
bogdanm 0:9b334a45a8ff 293 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 return HAL_OK;
bogdanm 0:9b334a45a8ff 296 }
bogdanm 0:9b334a45a8ff 297
bogdanm 0:9b334a45a8ff 298 /**
bogdanm 0:9b334a45a8ff 299 * @brief Writes 8-bit buffer to SRAM memory.
bogdanm 0:9b334a45a8ff 300 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 301 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 302 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 303 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 304 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 305 * @retval HAL status
bogdanm 0:9b334a45a8ff 306 */
bogdanm 0:9b334a45a8ff 307 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 308 {
bogdanm 0:9b334a45a8ff 309 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /* Check the SRAM controller state */
bogdanm 0:9b334a45a8ff 312 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
bogdanm 0:9b334a45a8ff 313 {
bogdanm 0:9b334a45a8ff 314 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 315 }
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 /* Process Locked */
bogdanm 0:9b334a45a8ff 318 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 321 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 /* Write data to memory */
bogdanm 0:9b334a45a8ff 324 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 325 {
bogdanm 0:9b334a45a8ff 326 *(__IO uint8_t *)psramaddress = *pSrcBuffer;
bogdanm 0:9b334a45a8ff 327 pSrcBuffer++;
bogdanm 0:9b334a45a8ff 328 psramaddress++;
bogdanm 0:9b334a45a8ff 329 }
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 332 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 /* Process unlocked */
bogdanm 0:9b334a45a8ff 335 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 return HAL_OK;
bogdanm 0:9b334a45a8ff 338 }
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 /**
bogdanm 0:9b334a45a8ff 341 * @brief Reads 16-bit buffer from SRAM memory.
bogdanm 0:9b334a45a8ff 342 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 343 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 344 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 345 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 346 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 347 * @retval HAL status
bogdanm 0:9b334a45a8ff 348 */
bogdanm 0:9b334a45a8ff 349 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 350 {
bogdanm 0:9b334a45a8ff 351 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 /* Process Locked */
bogdanm 0:9b334a45a8ff 354 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 357 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /* Read data from memory */
bogdanm 0:9b334a45a8ff 360 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 361 {
bogdanm 0:9b334a45a8ff 362 *pDstBuffer = *(__IO uint16_t *)psramaddress;
bogdanm 0:9b334a45a8ff 363 pDstBuffer++;
bogdanm 0:9b334a45a8ff 364 psramaddress++;
bogdanm 0:9b334a45a8ff 365 }
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 368 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /* Process unlocked */
bogdanm 0:9b334a45a8ff 371 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 return HAL_OK;
bogdanm 0:9b334a45a8ff 374 }
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /**
bogdanm 0:9b334a45a8ff 377 * @brief Writes 16-bit buffer to SRAM memory.
bogdanm 0:9b334a45a8ff 378 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 379 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 380 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 381 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 382 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 383 * @retval HAL status
bogdanm 0:9b334a45a8ff 384 */
bogdanm 0:9b334a45a8ff 385 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 386 {
bogdanm 0:9b334a45a8ff 387 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 /* Check the SRAM controller state */
bogdanm 0:9b334a45a8ff 390 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
bogdanm 0:9b334a45a8ff 391 {
bogdanm 0:9b334a45a8ff 392 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 393 }
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 /* Process Locked */
bogdanm 0:9b334a45a8ff 396 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 399 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /* Write data to memory */
bogdanm 0:9b334a45a8ff 402 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 403 {
bogdanm 0:9b334a45a8ff 404 *(__IO uint16_t *)psramaddress = *pSrcBuffer;
bogdanm 0:9b334a45a8ff 405 pSrcBuffer++;
bogdanm 0:9b334a45a8ff 406 psramaddress++;
bogdanm 0:9b334a45a8ff 407 }
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 410 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 411
bogdanm 0:9b334a45a8ff 412 /* Process unlocked */
bogdanm 0:9b334a45a8ff 413 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 414
bogdanm 0:9b334a45a8ff 415 return HAL_OK;
bogdanm 0:9b334a45a8ff 416 }
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 /**
bogdanm 0:9b334a45a8ff 419 * @brief Reads 32-bit buffer from SRAM memory.
bogdanm 0:9b334a45a8ff 420 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 421 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 422 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 423 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 424 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 425 * @retval HAL status
bogdanm 0:9b334a45a8ff 426 */
bogdanm 0:9b334a45a8ff 427 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 428 {
bogdanm 0:9b334a45a8ff 429 /* Process Locked */
bogdanm 0:9b334a45a8ff 430 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 433 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 /* Read data from memory */
bogdanm 0:9b334a45a8ff 436 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 437 {
bogdanm 0:9b334a45a8ff 438 *pDstBuffer = *(__IO uint32_t *)pAddress;
bogdanm 0:9b334a45a8ff 439 pDstBuffer++;
bogdanm 0:9b334a45a8ff 440 pAddress++;
bogdanm 0:9b334a45a8ff 441 }
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 444 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /* Process unlocked */
bogdanm 0:9b334a45a8ff 447 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 return HAL_OK;
bogdanm 0:9b334a45a8ff 450 }
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 /**
bogdanm 0:9b334a45a8ff 453 * @brief Writes 32-bit buffer to SRAM memory.
bogdanm 0:9b334a45a8ff 454 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 455 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 456 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 457 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 458 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 459 * @retval HAL status
bogdanm 0:9b334a45a8ff 460 */
bogdanm 0:9b334a45a8ff 461 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 462 {
bogdanm 0:9b334a45a8ff 463 /* Check the SRAM controller state */
bogdanm 0:9b334a45a8ff 464 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
bogdanm 0:9b334a45a8ff 465 {
bogdanm 0:9b334a45a8ff 466 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 467 }
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /* Process Locked */
bogdanm 0:9b334a45a8ff 470 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 473 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 474
bogdanm 0:9b334a45a8ff 475 /* Write data to memory */
bogdanm 0:9b334a45a8ff 476 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 477 {
bogdanm 0:9b334a45a8ff 478 *(__IO uint32_t *)pAddress = *pSrcBuffer;
bogdanm 0:9b334a45a8ff 479 pSrcBuffer++;
bogdanm 0:9b334a45a8ff 480 pAddress++;
bogdanm 0:9b334a45a8ff 481 }
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 484 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 /* Process unlocked */
bogdanm 0:9b334a45a8ff 487 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 return HAL_OK;
bogdanm 0:9b334a45a8ff 490 }
bogdanm 0:9b334a45a8ff 491
bogdanm 0:9b334a45a8ff 492 /**
bogdanm 0:9b334a45a8ff 493 * @brief Reads a Words data from the SRAM memory using DMA transfer.
bogdanm 0:9b334a45a8ff 494 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 495 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 496 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 497 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 498 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 499 * @retval HAL status
bogdanm 0:9b334a45a8ff 500 */
bogdanm 0:9b334a45a8ff 501 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 502 {
bogdanm 0:9b334a45a8ff 503 /* Process Locked */
bogdanm 0:9b334a45a8ff 504 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 507 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 508
bogdanm 0:9b334a45a8ff 509 /* Configure DMA user callbacks */
bogdanm 0:9b334a45a8ff 510 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
bogdanm 0:9b334a45a8ff 511 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 514 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 517 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 518
bogdanm 0:9b334a45a8ff 519 /* Process unlocked */
bogdanm 0:9b334a45a8ff 520 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 return HAL_OK;
bogdanm 0:9b334a45a8ff 523 }
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 /**
bogdanm 0:9b334a45a8ff 526 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
bogdanm 0:9b334a45a8ff 527 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 528 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 529 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 530 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 531 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 532 * @retval HAL status
bogdanm 0:9b334a45a8ff 533 */
bogdanm 0:9b334a45a8ff 534 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 535 {
bogdanm 0:9b334a45a8ff 536 /* Check the SRAM controller state */
bogdanm 0:9b334a45a8ff 537 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
bogdanm 0:9b334a45a8ff 538 {
bogdanm 0:9b334a45a8ff 539 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 540 }
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /* Process Locked */
bogdanm 0:9b334a45a8ff 543 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 546 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 /* Configure DMA user callbacks */
bogdanm 0:9b334a45a8ff 549 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
bogdanm 0:9b334a45a8ff 550 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
bogdanm 0:9b334a45a8ff 551
bogdanm 0:9b334a45a8ff 552 /* Enable the DMA Stream */
bogdanm 0:9b334a45a8ff 553 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
bogdanm 0:9b334a45a8ff 554
bogdanm 0:9b334a45a8ff 555 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 556 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558 /* Process unlocked */
bogdanm 0:9b334a45a8ff 559 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 return HAL_OK;
bogdanm 0:9b334a45a8ff 562 }
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 /**
bogdanm 0:9b334a45a8ff 565 * @}
bogdanm 0:9b334a45a8ff 566 */
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
bogdanm 0:9b334a45a8ff 569 * @brief Control functions
bogdanm 0:9b334a45a8ff 570 *
bogdanm 0:9b334a45a8ff 571 @verbatim
bogdanm 0:9b334a45a8ff 572 ==============================================================================
bogdanm 0:9b334a45a8ff 573 ##### SRAM Control functions #####
bogdanm 0:9b334a45a8ff 574 ==============================================================================
bogdanm 0:9b334a45a8ff 575 [..]
bogdanm 0:9b334a45a8ff 576 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 577 the SRAM interface.
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 @endverbatim
bogdanm 0:9b334a45a8ff 580 * @{
bogdanm 0:9b334a45a8ff 581 */
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 /**
bogdanm 0:9b334a45a8ff 584 * @brief Enables dynamically SRAM write operation.
bogdanm 0:9b334a45a8ff 585 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 586 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 587 * @retval HAL status
bogdanm 0:9b334a45a8ff 588 */
bogdanm 0:9b334a45a8ff 589 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
bogdanm 0:9b334a45a8ff 590 {
bogdanm 0:9b334a45a8ff 591 /* Process Locked */
bogdanm 0:9b334a45a8ff 592 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 593
bogdanm 0:9b334a45a8ff 594 /* Enable write operation */
bogdanm 0:9b334a45a8ff 595 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 598 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 /* Process unlocked */
bogdanm 0:9b334a45a8ff 601 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 602
bogdanm 0:9b334a45a8ff 603 return HAL_OK;
bogdanm 0:9b334a45a8ff 604 }
bogdanm 0:9b334a45a8ff 605
bogdanm 0:9b334a45a8ff 606 /**
bogdanm 0:9b334a45a8ff 607 * @brief Disables dynamically SRAM write operation.
bogdanm 0:9b334a45a8ff 608 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 609 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 610 * @retval HAL status
bogdanm 0:9b334a45a8ff 611 */
bogdanm 0:9b334a45a8ff 612 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
bogdanm 0:9b334a45a8ff 613 {
bogdanm 0:9b334a45a8ff 614 /* Process Locked */
bogdanm 0:9b334a45a8ff 615 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 618 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 619
bogdanm 0:9b334a45a8ff 620 /* Disable write operation */
bogdanm 0:9b334a45a8ff 621 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 624 hsram->State = HAL_SRAM_STATE_PROTECTED;
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 /* Process unlocked */
bogdanm 0:9b334a45a8ff 627 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 628
bogdanm 0:9b334a45a8ff 629 return HAL_OK;
bogdanm 0:9b334a45a8ff 630 }
bogdanm 0:9b334a45a8ff 631
bogdanm 0:9b334a45a8ff 632 /**
bogdanm 0:9b334a45a8ff 633 * @}
bogdanm 0:9b334a45a8ff 634 */
bogdanm 0:9b334a45a8ff 635
bogdanm 0:9b334a45a8ff 636 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
bogdanm 0:9b334a45a8ff 637 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 638 *
bogdanm 0:9b334a45a8ff 639 @verbatim
bogdanm 0:9b334a45a8ff 640 ==============================================================================
bogdanm 0:9b334a45a8ff 641 ##### SRAM State functions #####
bogdanm 0:9b334a45a8ff 642 ==============================================================================
bogdanm 0:9b334a45a8ff 643 [..]
bogdanm 0:9b334a45a8ff 644 This subsection permits to get in run-time the status of the SRAM controller
bogdanm 0:9b334a45a8ff 645 and the data flow.
bogdanm 0:9b334a45a8ff 646
bogdanm 0:9b334a45a8ff 647 @endverbatim
bogdanm 0:9b334a45a8ff 648 * @{
bogdanm 0:9b334a45a8ff 649 */
bogdanm 0:9b334a45a8ff 650
bogdanm 0:9b334a45a8ff 651 /**
bogdanm 0:9b334a45a8ff 652 * @brief Returns the SRAM controller state
bogdanm 0:9b334a45a8ff 653 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 654 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 655 * @retval HAL state
bogdanm 0:9b334a45a8ff 656 */
bogdanm 0:9b334a45a8ff 657 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
bogdanm 0:9b334a45a8ff 658 {
bogdanm 0:9b334a45a8ff 659 return hsram->State;
bogdanm 0:9b334a45a8ff 660 }
bogdanm 0:9b334a45a8ff 661
bogdanm 0:9b334a45a8ff 662 /**
bogdanm 0:9b334a45a8ff 663 * @}
bogdanm 0:9b334a45a8ff 664 */
bogdanm 0:9b334a45a8ff 665
bogdanm 0:9b334a45a8ff 666 /**
bogdanm 0:9b334a45a8ff 667 * @}
bogdanm 0:9b334a45a8ff 668 */
bogdanm 0:9b334a45a8ff 669 #endif /* HAL_SRAM_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 670 /**
bogdanm 0:9b334a45a8ff 671 * @}
bogdanm 0:9b334a45a8ff 672 */
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 /**
bogdanm 0:9b334a45a8ff 675 * @}
bogdanm 0:9b334a45a8ff 676 */
bogdanm 0:9b334a45a8ff 677
bogdanm 0:9b334a45a8ff 678 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/