en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
83:a036322b8637
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f7xx_hal_pwr.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.1
bogdanm 0:9b334a45a8ff 6 * @date 25-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief PWR HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Power Controller (PWR) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 ******************************************************************************
bogdanm 0:9b334a45a8ff 14 * @attention
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 17 *
bogdanm 0:9b334a45a8ff 18 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 19 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 20 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 21 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 23 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 24 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 26 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 27 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 28 *
bogdanm 0:9b334a45a8ff 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 39 *
bogdanm 0:9b334a45a8ff 40 ******************************************************************************
bogdanm 0:9b334a45a8ff 41 */
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 44 #include "stm32f7xx_hal.h"
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /** @addtogroup STM32F7xx_HAL_Driver
bogdanm 0:9b334a45a8ff 47 * @{
bogdanm 0:9b334a45a8ff 48 */
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 /** @defgroup PWR PWR
bogdanm 0:9b334a45a8ff 51 * @brief PWR HAL module driver
bogdanm 0:9b334a45a8ff 52 * @{
bogdanm 0:9b334a45a8ff 53 */
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 #ifdef HAL_PWR_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 59 /** @addtogroup PWR_Private_Constants
bogdanm 0:9b334a45a8ff 60 * @{
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
bogdanm 0:9b334a45a8ff 64 * @{
bogdanm 0:9b334a45a8ff 65 */
bogdanm 0:9b334a45a8ff 66 #define PVD_MODE_IT ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 67 #define PVD_MODE_EVT ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 68 #define PVD_RISING_EDGE ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 69 #define PVD_FALLING_EDGE ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 70 /**
bogdanm 0:9b334a45a8ff 71 * @}
bogdanm 0:9b334a45a8ff 72 */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
bogdanm 0:9b334a45a8ff 75 * @{
bogdanm 0:9b334a45a8ff 76 */
bogdanm 0:9b334a45a8ff 77 #define PWR_EWUP_MASK ((uint32_t)0x00003F00)
bogdanm 0:9b334a45a8ff 78 /**
bogdanm 0:9b334a45a8ff 79 * @}
bogdanm 0:9b334a45a8ff 80 */
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 /**
bogdanm 0:9b334a45a8ff 83 * @}
bogdanm 0:9b334a45a8ff 84 */
bogdanm 0:9b334a45a8ff 85 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 86 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 87 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 88 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /** @defgroup PWR_Exported_Functions PWR Exported Functions
bogdanm 0:9b334a45a8ff 91 * @{
bogdanm 0:9b334a45a8ff 92 */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 95 * @brief Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 96 *
bogdanm 0:9b334a45a8ff 97 @verbatim
bogdanm 0:9b334a45a8ff 98 ===============================================================================
bogdanm 0:9b334a45a8ff 99 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 100 ===============================================================================
bogdanm 0:9b334a45a8ff 101 [..]
bogdanm 0:9b334a45a8ff 102 After reset, the backup domain (RTC registers, RTC backup data
bogdanm 0:9b334a45a8ff 103 registers and backup SRAM) is protected against possible unwanted
bogdanm 0:9b334a45a8ff 104 write accesses.
bogdanm 0:9b334a45a8ff 105 To enable access to the RTC Domain and RTC registers, proceed as follows:
bogdanm 0:9b334a45a8ff 106 (+) Enable the Power Controller (PWR) APB1 interface clock using the
bogdanm 0:9b334a45a8ff 107 __HAL_RCC_PWR_CLK_ENABLE() macro.
bogdanm 0:9b334a45a8ff 108 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 @endverbatim
bogdanm 0:9b334a45a8ff 111 * @{
bogdanm 0:9b334a45a8ff 112 */
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /**
bogdanm 0:9b334a45a8ff 115 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
bogdanm 0:9b334a45a8ff 116 * @retval None
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118 void HAL_PWR_DeInit(void)
bogdanm 0:9b334a45a8ff 119 {
bogdanm 0:9b334a45a8ff 120 __HAL_RCC_PWR_FORCE_RESET();
bogdanm 0:9b334a45a8ff 121 __HAL_RCC_PWR_RELEASE_RESET();
bogdanm 0:9b334a45a8ff 122 }
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 /**
bogdanm 0:9b334a45a8ff 125 * @brief Enables access to the backup domain (RTC registers, RTC
bogdanm 0:9b334a45a8ff 126 * backup data registers and backup SRAM).
bogdanm 0:9b334a45a8ff 127 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
bogdanm 0:9b334a45a8ff 128 * Backup Domain Access should be kept enabled.
bogdanm 0:9b334a45a8ff 129 * @retval None
bogdanm 0:9b334a45a8ff 130 */
bogdanm 0:9b334a45a8ff 131 void HAL_PWR_EnableBkUpAccess(void)
bogdanm 0:9b334a45a8ff 132 {
bogdanm 0:9b334a45a8ff 133 /* Enable access to RTC and backup registers */
bogdanm 0:9b334a45a8ff 134 SET_BIT(PWR->CR1, PWR_CR1_DBP);
bogdanm 0:9b334a45a8ff 135 }
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /**
bogdanm 0:9b334a45a8ff 138 * @brief Disables access to the backup domain (RTC registers, RTC
bogdanm 0:9b334a45a8ff 139 * backup data registers and backup SRAM).
bogdanm 0:9b334a45a8ff 140 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
bogdanm 0:9b334a45a8ff 141 * Backup Domain Access should be kept enabled.
bogdanm 0:9b334a45a8ff 142 * @retval None
bogdanm 0:9b334a45a8ff 143 */
bogdanm 0:9b334a45a8ff 144 void HAL_PWR_DisableBkUpAccess(void)
bogdanm 0:9b334a45a8ff 145 {
bogdanm 0:9b334a45a8ff 146 /* Disable access to RTC and backup registers */
bogdanm 0:9b334a45a8ff 147 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
bogdanm 0:9b334a45a8ff 148 }
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 /**
bogdanm 0:9b334a45a8ff 151 * @}
bogdanm 0:9b334a45a8ff 152 */
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
bogdanm 0:9b334a45a8ff 155 * @brief Low Power modes configuration functions
bogdanm 0:9b334a45a8ff 156 *
bogdanm 0:9b334a45a8ff 157 @verbatim
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 ===============================================================================
bogdanm 0:9b334a45a8ff 160 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 161 ===============================================================================
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 *** PVD configuration ***
bogdanm 0:9b334a45a8ff 164 =========================
bogdanm 0:9b334a45a8ff 165 [..]
bogdanm 0:9b334a45a8ff 166 (+) The PVD is used to monitor the VDD power supply by comparing it to a
bogdanm 0:9b334a45a8ff 167 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
bogdanm 0:9b334a45a8ff 168 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
bogdanm 0:9b334a45a8ff 169 than the PVD threshold. This event is internally connected to the EXTI
bogdanm 0:9b334a45a8ff 170 line16 and can generate an interrupt if enabled. This is done through
bogdanm 0:9b334a45a8ff 171 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
bogdanm 0:9b334a45a8ff 172 (+) The PVD is stopped in Standby mode.
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 *** Wake-up pin configuration ***
bogdanm 0:9b334a45a8ff 175 ================================
bogdanm 0:9b334a45a8ff 176 [..]
bogdanm 0:9b334a45a8ff 177 (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
bogdanm 0:9b334a45a8ff 178 forced in input pull-down configuration and is active on rising edges.
bogdanm 0:9b334a45a8ff 179 (+) There are to 6 Wake-up pin in the STM32F7 devices family
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 *** Low Power modes configuration ***
bogdanm 0:9b334a45a8ff 182 =====================================
bogdanm 0:9b334a45a8ff 183 [..]
bogdanm 0:9b334a45a8ff 184 The devices feature 3 low-power modes:
bogdanm 0:9b334a45a8ff 185 (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.
bogdanm 0:9b334a45a8ff 186 (+) Stop mode: all clocks are stopped, regulator running, regulator
bogdanm 0:9b334a45a8ff 187 in low power mode
bogdanm 0:9b334a45a8ff 188 (+) Standby mode: 1.2V domain powered off.
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 *** Sleep mode ***
bogdanm 0:9b334a45a8ff 191 ==================
bogdanm 0:9b334a45a8ff 192 [..]
bogdanm 0:9b334a45a8ff 193 (+) Entry:
bogdanm 0:9b334a45a8ff 194 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
bogdanm 0:9b334a45a8ff 195 functions with
bogdanm 0:9b334a45a8ff 196 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
bogdanm 0:9b334a45a8ff 197 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 -@@- The Regulator parameter is not used for the STM32F7 family
bogdanm 0:9b334a45a8ff 200 and is kept as parameter just to maintain compatibility with the
bogdanm 0:9b334a45a8ff 201 lower power families (STM32L).
bogdanm 0:9b334a45a8ff 202 (+) Exit:
bogdanm 0:9b334a45a8ff 203 Any peripheral interrupt acknowledged by the nested vectored interrupt
bogdanm 0:9b334a45a8ff 204 controller (NVIC) can wake up the device from Sleep mode.
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 *** Stop mode ***
bogdanm 0:9b334a45a8ff 207 =================
bogdanm 0:9b334a45a8ff 208 [..]
bogdanm 0:9b334a45a8ff 209 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
bogdanm 0:9b334a45a8ff 210 and the HSE RC oscillators are disabled. Internal SRAM and register contents
bogdanm 0:9b334a45a8ff 211 are preserved.
bogdanm 0:9b334a45a8ff 212 The voltage regulator can be configured either in normal or low-power mode.
bogdanm 0:9b334a45a8ff 213 To minimize the consumption In Stop mode, FLASH can be powered off before
bogdanm 0:9b334a45a8ff 214 entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
bogdanm 0:9b334a45a8ff 215 It can be switched on again by software after exiting the Stop mode using
bogdanm 0:9b334a45a8ff 216 the HAL_PWREx_DisableFlashPowerDown() function.
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 (+) Entry:
bogdanm 0:9b334a45a8ff 219 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
bogdanm 0:9b334a45a8ff 220 function with:
bogdanm 0:9b334a45a8ff 221 (++) Main regulator ON.
bogdanm 0:9b334a45a8ff 222 (++) Low Power regulator ON.
bogdanm 0:9b334a45a8ff 223 (+) Exit:
bogdanm 0:9b334a45a8ff 224 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 *** Standby mode ***
bogdanm 0:9b334a45a8ff 227 ====================
bogdanm 0:9b334a45a8ff 228 [..]
bogdanm 0:9b334a45a8ff 229 (+)
bogdanm 0:9b334a45a8ff 230 The Standby mode allows to achieve the lowest power consumption. It is based
bogdanm 0:9b334a45a8ff 231 on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
bogdanm 0:9b334a45a8ff 232 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
bogdanm 0:9b334a45a8ff 233 the HSE oscillator are also switched off. SRAM and register contents are lost
bogdanm 0:9b334a45a8ff 234 except for the RTC registers, RTC backup registers, backup SRAM and Standby
bogdanm 0:9b334a45a8ff 235 circuitry.
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 The voltage regulator is OFF.
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 (++) Entry:
bogdanm 0:9b334a45a8ff 240 (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
bogdanm 0:9b334a45a8ff 241 (++) Exit:
bogdanm 0:9b334a45a8ff 242 (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
bogdanm 0:9b334a45a8ff 243 wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 *** Auto-wakeup (AWU) from low-power mode ***
bogdanm 0:9b334a45a8ff 246 =============================================
bogdanm 0:9b334a45a8ff 247 [..]
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
bogdanm 0:9b334a45a8ff 250 Wakeup event, a tamper event or a time-stamp event, without depending on
bogdanm 0:9b334a45a8ff 251 an external interrupt (Auto-wakeup mode).
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
bogdanm 0:9b334a45a8ff 256 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
bogdanm 0:9b334a45a8ff 259 is necessary to configure the RTC to detect the tamper or time stamp event using the
bogdanm 0:9b334a45a8ff 260 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
bogdanm 0:9b334a45a8ff 263 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 @endverbatim
bogdanm 0:9b334a45a8ff 266 * @{
bogdanm 0:9b334a45a8ff 267 */
bogdanm 0:9b334a45a8ff 268
bogdanm 0:9b334a45a8ff 269 /**
bogdanm 0:9b334a45a8ff 270 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
bogdanm 0:9b334a45a8ff 271 * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
bogdanm 0:9b334a45a8ff 272 * information for the PVD.
bogdanm 0:9b334a45a8ff 273 * @note Refer to the electrical characteristics of your device datasheet for
bogdanm 0:9b334a45a8ff 274 * more details about the voltage threshold corresponding to each
bogdanm 0:9b334a45a8ff 275 * detection level.
bogdanm 0:9b334a45a8ff 276 * @retval None
bogdanm 0:9b334a45a8ff 277 */
bogdanm 0:9b334a45a8ff 278 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
bogdanm 0:9b334a45a8ff 279 {
bogdanm 0:9b334a45a8ff 280 /* Check the parameters */
bogdanm 0:9b334a45a8ff 281 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
bogdanm 0:9b334a45a8ff 282 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /* Set PLS[7:5] bits according to PVDLevel value */
bogdanm 0:9b334a45a8ff 285 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
bogdanm 0:9b334a45a8ff 288 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
bogdanm 0:9b334a45a8ff 289 __HAL_PWR_PVD_EXTI_DISABLE_IT();
bogdanm 0:9b334a45a8ff 290 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 291 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 /* Configure interrupt mode */
bogdanm 0:9b334a45a8ff 294 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
bogdanm 0:9b334a45a8ff 295 {
bogdanm 0:9b334a45a8ff 296 __HAL_PWR_PVD_EXTI_ENABLE_IT();
bogdanm 0:9b334a45a8ff 297 }
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 /* Configure event mode */
bogdanm 0:9b334a45a8ff 300 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
bogdanm 0:9b334a45a8ff 301 {
bogdanm 0:9b334a45a8ff 302 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
bogdanm 0:9b334a45a8ff 303 }
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 /* Configure the edge */
bogdanm 0:9b334a45a8ff 306 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
bogdanm 0:9b334a45a8ff 307 {
bogdanm 0:9b334a45a8ff 308 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
bogdanm 0:9b334a45a8ff 309 }
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
bogdanm 0:9b334a45a8ff 312 {
bogdanm 0:9b334a45a8ff 313 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 314 }
bogdanm 0:9b334a45a8ff 315 }
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 /**
bogdanm 0:9b334a45a8ff 318 * @brief Enables the Power Voltage Detector(PVD).
bogdanm 0:9b334a45a8ff 319 * @retval None
bogdanm 0:9b334a45a8ff 320 */
bogdanm 0:9b334a45a8ff 321 void HAL_PWR_EnablePVD(void)
bogdanm 0:9b334a45a8ff 322 {
bogdanm 0:9b334a45a8ff 323 /* Enable the power voltage detector */
bogdanm 0:9b334a45a8ff 324 SET_BIT(PWR->CR1, PWR_CR1_PVDE);
bogdanm 0:9b334a45a8ff 325 }
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 /**
bogdanm 0:9b334a45a8ff 328 * @brief Disables the Power Voltage Detector(PVD).
bogdanm 0:9b334a45a8ff 329 * @retval None
bogdanm 0:9b334a45a8ff 330 */
bogdanm 0:9b334a45a8ff 331 void HAL_PWR_DisablePVD(void)
bogdanm 0:9b334a45a8ff 332 {
bogdanm 0:9b334a45a8ff 333 /* Disable the power voltage detector */
bogdanm 0:9b334a45a8ff 334 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
bogdanm 0:9b334a45a8ff 335 }
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 /**
bogdanm 0:9b334a45a8ff 338 * @brief Enable the WakeUp PINx functionality.
bogdanm 0:9b334a45a8ff 339 * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
bogdanm 0:9b334a45a8ff 340 * This parameter can be one of the following legacy values, which sets the default polarity:
bogdanm 0:9b334a45a8ff 341 * detection on high level (rising edge):
bogdanm 0:9b334a45a8ff 342 * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6
bogdanm 0:9b334a45a8ff 343 * or one of the following value where the user can explicitly states the enabled pin and
bogdanm 0:9b334a45a8ff 344 * the chosen polarity
bogdanm 0:9b334a45a8ff 345 * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
bogdanm 0:9b334a45a8ff 346 * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
bogdanm 0:9b334a45a8ff 347 * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
bogdanm 0:9b334a45a8ff 348 * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
bogdanm 0:9b334a45a8ff 349 * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
bogdanm 0:9b334a45a8ff 350 * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
bogdanm 0:9b334a45a8ff 351 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
bogdanm 0:9b334a45a8ff 352 * @retval None
bogdanm 0:9b334a45a8ff 353 */
bogdanm 0:9b334a45a8ff 354 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
bogdanm 0:9b334a45a8ff 355 {
bogdanm 0:9b334a45a8ff 356 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358 /* Enable wake-up pin */
bogdanm 0:9b334a45a8ff 359 SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /* Specifies the Wake-Up pin polarity for the event detection
bogdanm 0:9b334a45a8ff 362 (rising or falling edge) */
bogdanm 0:9b334a45a8ff 363 MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));
bogdanm 0:9b334a45a8ff 364 }
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 /**
bogdanm 0:9b334a45a8ff 367 * @brief Disables the WakeUp PINx functionality.
bogdanm 0:9b334a45a8ff 368 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
bogdanm 0:9b334a45a8ff 369 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 370 * @arg PWR_WAKEUP_PIN1
bogdanm 0:9b334a45a8ff 371 * @arg PWR_WAKEUP_PIN2
bogdanm 0:9b334a45a8ff 372 * @arg PWR_WAKEUP_PIN3
bogdanm 0:9b334a45a8ff 373 * @arg PWR_WAKEUP_PIN4
bogdanm 0:9b334a45a8ff 374 * @arg PWR_WAKEUP_PIN5
bogdanm 0:9b334a45a8ff 375 * @arg PWR_WAKEUP_PIN6
bogdanm 0:9b334a45a8ff 376 * @retval None
bogdanm 0:9b334a45a8ff 377 */
bogdanm 0:9b334a45a8ff 378 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
bogdanm 0:9b334a45a8ff 379 {
bogdanm 0:9b334a45a8ff 380 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 CLEAR_BIT(PWR->CSR2, WakeUpPinx);
bogdanm 0:9b334a45a8ff 383 }
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 /**
bogdanm 0:9b334a45a8ff 386 * @brief Enters Sleep mode.
bogdanm 0:9b334a45a8ff 387 *
bogdanm 0:9b334a45a8ff 388 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 389 *
bogdanm 0:9b334a45a8ff 390 * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
bogdanm 0:9b334a45a8ff 391 * systick interrupt when used as time base for Timeout
bogdanm 0:9b334a45a8ff 392 *
bogdanm 0:9b334a45a8ff 393 * @param Regulator: Specifies the regulator state in SLEEP mode.
bogdanm 0:9b334a45a8ff 394 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 395 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
bogdanm 0:9b334a45a8ff 396 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
bogdanm 0:9b334a45a8ff 397 * @note This parameter is not used for the STM32F7 family and is kept as parameter
bogdanm 0:9b334a45a8ff 398 * just to maintain compatibility with the lower power families.
bogdanm 0:9b334a45a8ff 399 * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 400 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 401 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
bogdanm 0:9b334a45a8ff 402 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
bogdanm 0:9b334a45a8ff 403 * @retval None
bogdanm 0:9b334a45a8ff 404 */
bogdanm 0:9b334a45a8ff 405 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
bogdanm 0:9b334a45a8ff 406 {
bogdanm 0:9b334a45a8ff 407 /* Check the parameters */
bogdanm 0:9b334a45a8ff 408 assert_param(IS_PWR_REGULATOR(Regulator));
bogdanm 0:9b334a45a8ff 409 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 /* Clear SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 412 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /* Select SLEEP mode entry -------------------------------------------------*/
bogdanm 0:9b334a45a8ff 415 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
bogdanm 0:9b334a45a8ff 416 {
bogdanm 0:9b334a45a8ff 417 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 418 __WFI();
bogdanm 0:9b334a45a8ff 419 }
bogdanm 0:9b334a45a8ff 420 else
bogdanm 0:9b334a45a8ff 421 {
bogdanm 0:9b334a45a8ff 422 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 423 __SEV();
bogdanm 0:9b334a45a8ff 424 __WFE();
bogdanm 0:9b334a45a8ff 425 __WFE();
bogdanm 0:9b334a45a8ff 426 }
bogdanm 0:9b334a45a8ff 427 }
bogdanm 0:9b334a45a8ff 428
bogdanm 0:9b334a45a8ff 429 /**
bogdanm 0:9b334a45a8ff 430 * @brief Enters Stop mode.
bogdanm 0:9b334a45a8ff 431 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 432 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
bogdanm 0:9b334a45a8ff 433 * the HSI RC oscillator is selected as system clock.
bogdanm 0:9b334a45a8ff 434 * @note When the voltage regulator operates in low power mode, an additional
bogdanm 0:9b334a45a8ff 435 * startup delay is incurred when waking up from Stop mode.
bogdanm 0:9b334a45a8ff 436 * By keeping the internal regulator ON during Stop mode, the consumption
bogdanm 0:9b334a45a8ff 437 * is higher although the startup time is reduced.
bogdanm 0:9b334a45a8ff 438 * @param Regulator: Specifies the regulator state in Stop mode.
bogdanm 0:9b334a45a8ff 439 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 440 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
bogdanm 0:9b334a45a8ff 441 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
bogdanm 0:9b334a45a8ff 442 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 443 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 444 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
bogdanm 0:9b334a45a8ff 445 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
bogdanm 0:9b334a45a8ff 446 * @retval None
bogdanm 0:9b334a45a8ff 447 */
bogdanm 0:9b334a45a8ff 448 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
bogdanm 0:9b334a45a8ff 449 {
bogdanm 0:9b334a45a8ff 450 uint32_t tmpreg = 0;
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 /* Check the parameters */
bogdanm 0:9b334a45a8ff 453 assert_param(IS_PWR_REGULATOR(Regulator));
bogdanm 0:9b334a45a8ff 454 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 /* Select the regulator state in Stop mode ---------------------------------*/
bogdanm 0:9b334a45a8ff 457 tmpreg = PWR->CR1;
bogdanm 0:9b334a45a8ff 458 /* Clear PDDS and LPDS bits */
bogdanm 0:9b334a45a8ff 459 tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
bogdanm 0:9b334a45a8ff 462 tmpreg |= Regulator;
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /* Store the new value */
bogdanm 0:9b334a45a8ff 465 PWR->CR1 = tmpreg;
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 468 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /* Select Stop mode entry --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 471 if(STOPEntry == PWR_STOPENTRY_WFI)
bogdanm 0:9b334a45a8ff 472 {
bogdanm 0:9b334a45a8ff 473 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 474 __WFI();
bogdanm 0:9b334a45a8ff 475 }
bogdanm 0:9b334a45a8ff 476 else
bogdanm 0:9b334a45a8ff 477 {
bogdanm 0:9b334a45a8ff 478 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 479 __SEV();
bogdanm 0:9b334a45a8ff 480 __WFE();
bogdanm 0:9b334a45a8ff 481 __WFE();
bogdanm 0:9b334a45a8ff 482 }
bogdanm 0:9b334a45a8ff 483 /* Reset SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 484 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
bogdanm 0:9b334a45a8ff 485 }
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 /**
bogdanm 0:9b334a45a8ff 488 * @brief Enters Standby mode.
bogdanm 0:9b334a45a8ff 489 * @note In Standby mode, all I/O pins are high impedance except for:
bogdanm 0:9b334a45a8ff 490 * - Reset pad (still available)
bogdanm 0:9b334a45a8ff 491 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
bogdanm 0:9b334a45a8ff 492 * Alarm out, or RTC clock calibration out.
bogdanm 0:9b334a45a8ff 493 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
bogdanm 0:9b334a45a8ff 494 * - WKUP pins if enabled.
bogdanm 0:9b334a45a8ff 495 * @retval None
bogdanm 0:9b334a45a8ff 496 */
bogdanm 0:9b334a45a8ff 497 void HAL_PWR_EnterSTANDBYMode(void)
bogdanm 0:9b334a45a8ff 498 {
bogdanm 0:9b334a45a8ff 499 /* Select Standby mode */
bogdanm 0:9b334a45a8ff 500 PWR->CR1 |= PWR_CR1_PDDS;
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 503 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 /* This option is used to ensure that store operations are completed */
bogdanm 0:9b334a45a8ff 506 #if defined ( __CC_ARM)
bogdanm 0:9b334a45a8ff 507 __force_stores();
bogdanm 0:9b334a45a8ff 508 #endif
bogdanm 0:9b334a45a8ff 509 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 510 __WFI();
bogdanm 0:9b334a45a8ff 511 }
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 /**
bogdanm 0:9b334a45a8ff 514 * @brief This function handles the PWR PVD interrupt request.
bogdanm 0:9b334a45a8ff 515 * @note This API should be called under the PVD_IRQHandler().
bogdanm 0:9b334a45a8ff 516 * @retval None
bogdanm 0:9b334a45a8ff 517 */
bogdanm 0:9b334a45a8ff 518 void HAL_PWR_PVD_IRQHandler(void)
bogdanm 0:9b334a45a8ff 519 {
bogdanm 0:9b334a45a8ff 520 /* Check PWR Exti flag */
bogdanm 0:9b334a45a8ff 521 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
bogdanm 0:9b334a45a8ff 522 {
bogdanm 0:9b334a45a8ff 523 /* PWR PVD interrupt user callback */
bogdanm 0:9b334a45a8ff 524 HAL_PWR_PVDCallback();
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 /* Clear PWR Exti pending bit */
bogdanm 0:9b334a45a8ff 527 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
bogdanm 0:9b334a45a8ff 528 }
bogdanm 0:9b334a45a8ff 529 }
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 /**
bogdanm 0:9b334a45a8ff 532 * @brief PWR PVD interrupt callback
bogdanm 0:9b334a45a8ff 533 * @retval None
bogdanm 0:9b334a45a8ff 534 */
bogdanm 0:9b334a45a8ff 535 __weak void HAL_PWR_PVDCallback(void)
bogdanm 0:9b334a45a8ff 536 {
bogdanm 0:9b334a45a8ff 537 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 538 the HAL_PWR_PVDCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 539 */
bogdanm 0:9b334a45a8ff 540 }
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /**
bogdanm 0:9b334a45a8ff 543 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
bogdanm 0:9b334a45a8ff 544 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
bogdanm 0:9b334a45a8ff 545 * re-enters SLEEP mode when an interruption handling is over.
bogdanm 0:9b334a45a8ff 546 * Setting this bit is useful when the processor is expected to run only on
bogdanm 0:9b334a45a8ff 547 * interruptions handling.
bogdanm 0:9b334a45a8ff 548 * @retval None
bogdanm 0:9b334a45a8ff 549 */
bogdanm 0:9b334a45a8ff 550 void HAL_PWR_EnableSleepOnExit(void)
bogdanm 0:9b334a45a8ff 551 {
bogdanm 0:9b334a45a8ff 552 /* Set SLEEPONEXIT bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 553 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
bogdanm 0:9b334a45a8ff 554 }
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556 /**
bogdanm 0:9b334a45a8ff 557 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
bogdanm 0:9b334a45a8ff 558 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
bogdanm 0:9b334a45a8ff 559 * re-enters SLEEP mode when an interruption handling is over.
bogdanm 0:9b334a45a8ff 560 * @retval None
bogdanm 0:9b334a45a8ff 561 */
bogdanm 0:9b334a45a8ff 562 void HAL_PWR_DisableSleepOnExit(void)
bogdanm 0:9b334a45a8ff 563 {
bogdanm 0:9b334a45a8ff 564 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 565 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
bogdanm 0:9b334a45a8ff 566 }
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568 /**
bogdanm 0:9b334a45a8ff 569 * @brief Enables CORTEX M4 SEVONPEND bit.
bogdanm 0:9b334a45a8ff 570 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
bogdanm 0:9b334a45a8ff 571 * WFE to wake up when an interrupt moves from inactive to pended.
bogdanm 0:9b334a45a8ff 572 * @retval None
bogdanm 0:9b334a45a8ff 573 */
bogdanm 0:9b334a45a8ff 574 void HAL_PWR_EnableSEVOnPend(void)
bogdanm 0:9b334a45a8ff 575 {
bogdanm 0:9b334a45a8ff 576 /* Set SEVONPEND bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 577 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
bogdanm 0:9b334a45a8ff 578 }
bogdanm 0:9b334a45a8ff 579
bogdanm 0:9b334a45a8ff 580 /**
bogdanm 0:9b334a45a8ff 581 * @brief Disables CORTEX M4 SEVONPEND bit.
bogdanm 0:9b334a45a8ff 582 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
bogdanm 0:9b334a45a8ff 583 * WFE to wake up when an interrupt moves from inactive to pended.
bogdanm 0:9b334a45a8ff 584 * @retval None
bogdanm 0:9b334a45a8ff 585 */
bogdanm 0:9b334a45a8ff 586 void HAL_PWR_DisableSEVOnPend(void)
bogdanm 0:9b334a45a8ff 587 {
bogdanm 0:9b334a45a8ff 588 /* Clear SEVONPEND bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 589 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
bogdanm 0:9b334a45a8ff 590 }
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592 /**
bogdanm 0:9b334a45a8ff 593 * @}
bogdanm 0:9b334a45a8ff 594 */
bogdanm 0:9b334a45a8ff 595
bogdanm 0:9b334a45a8ff 596 /**
bogdanm 0:9b334a45a8ff 597 * @}
bogdanm 0:9b334a45a8ff 598 */
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 #endif /* HAL_PWR_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 601 /**
bogdanm 0:9b334a45a8ff 602 * @}
bogdanm 0:9b334a45a8ff 603 */
bogdanm 0:9b334a45a8ff 604
bogdanm 0:9b334a45a8ff 605 /**
bogdanm 0:9b334a45a8ff 606 * @}
bogdanm 0:9b334a45a8ff 607 */
bogdanm 0:9b334a45a8ff 608
bogdanm 0:9b334a45a8ff 609 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/