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fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
83:a036322b8637
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f7xx_hal_nor.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.1
bogdanm 0:9b334a45a8ff 6 * @date 25-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief NOR HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides a generic firmware to drive NOR memories mounted
bogdanm 0:9b334a45a8ff 9 * as external device.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 @verbatim
bogdanm 0:9b334a45a8ff 12 ==============================================================================
bogdanm 0:9b334a45a8ff 13 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 [..]
bogdanm 0:9b334a45a8ff 16 This driver is a generic layered driver which contains a set of APIs used to
bogdanm 0:9b334a45a8ff 17 control NOR flash memories. It uses the FMC layer functions to interface
bogdanm 0:9b334a45a8ff 18 with NOR devices. This driver is used as follows:
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
bogdanm 0:9b334a45a8ff 21 with control and timing parameters for both normal and extended mode.
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 (+) Read NOR flash memory manufacturer code and device IDs using the function
bogdanm 0:9b334a45a8ff 24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
bogdanm 0:9b334a45a8ff 25 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 (+) Access NOR flash memory by read/write data unit operations using the functions
bogdanm 0:9b334a45a8ff 28 HAL_NOR_Read(), HAL_NOR_Program().
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 (+) Perform NOR flash erase block/chip operations using the functions
bogdanm 0:9b334a45a8ff 31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
bogdanm 0:9b334a45a8ff 34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
bogdanm 0:9b334a45a8ff 35 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
bogdanm 0:9b334a45a8ff 38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 (+) You can monitor the NOR device HAL state by calling the function
bogdanm 0:9b334a45a8ff 41 HAL_NOR_GetState()
bogdanm 0:9b334a45a8ff 42 [..]
bogdanm 0:9b334a45a8ff 43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
bogdanm 0:9b334a45a8ff 44 If a NOR flash device contains different operations and/or implementations,
bogdanm 0:9b334a45a8ff 45 it should be implemented separately.
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 *** NOR HAL driver macros list ***
bogdanm 0:9b334a45a8ff 48 =============================================
bogdanm 0:9b334a45a8ff 49 [..]
bogdanm 0:9b334a45a8ff 50 Below the list of most used macros in NOR HAL driver.
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 (+) NOR_WRITE : NOR memory write data to specified address
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 @endverbatim
bogdanm 0:9b334a45a8ff 55 ******************************************************************************
bogdanm 0:9b334a45a8ff 56 * @attention
bogdanm 0:9b334a45a8ff 57 *
bogdanm 0:9b334a45a8ff 58 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 59 *
bogdanm 0:9b334a45a8ff 60 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 61 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 62 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 63 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 65 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 66 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 68 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 69 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 81 *
bogdanm 0:9b334a45a8ff 82 ******************************************************************************
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 86 #include "stm32f7xx_hal.h"
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 /** @addtogroup STM32F7xx_HAL_Driver
bogdanm 0:9b334a45a8ff 89 * @{
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 /** @defgroup NOR NOR
bogdanm 0:9b334a45a8ff 93 * @brief NOR driver modules
bogdanm 0:9b334a45a8ff 94 * @{
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96 #ifdef HAL_NOR_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 99 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /** @defgroup NOR_Private_Defines NOR Private Defines
bogdanm 0:9b334a45a8ff 102 * @{
bogdanm 0:9b334a45a8ff 103 */
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 /* Constants to define address to set to write a command */
bogdanm 0:9b334a45a8ff 106 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 107 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 108 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
bogdanm 0:9b334a45a8ff 109 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 110 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 111 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
bogdanm 0:9b334a45a8ff 112 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /* Constants to define data to program a command */
bogdanm 0:9b334a45a8ff 115 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
bogdanm 0:9b334a45a8ff 116 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
bogdanm 0:9b334a45a8ff 117 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 118 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
bogdanm 0:9b334a45a8ff 119 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
bogdanm 0:9b334a45a8ff 120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
bogdanm 0:9b334a45a8ff 121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
bogdanm 0:9b334a45a8ff 122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
bogdanm 0:9b334a45a8ff 123 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
bogdanm 0:9b334a45a8ff 124 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
bogdanm 0:9b334a45a8ff 127 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
bogdanm 0:9b334a45a8ff 128 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /* Mask on NOR STATUS REGISTER */
bogdanm 0:9b334a45a8ff 131 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
bogdanm 0:9b334a45a8ff 132 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /**
bogdanm 0:9b334a45a8ff 135 * @}
bogdanm 0:9b334a45a8ff 136 */
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 139 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 140 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 141 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 142 /** @defgroup NOR_Exported_Functions NOR Exported Functions
bogdanm 0:9b334a45a8ff 143 * @{
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 147 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 148 *
bogdanm 0:9b334a45a8ff 149 @verbatim
bogdanm 0:9b334a45a8ff 150 ==============================================================================
bogdanm 0:9b334a45a8ff 151 ##### NOR Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 152 ==============================================================================
bogdanm 0:9b334a45a8ff 153 [..]
bogdanm 0:9b334a45a8ff 154 This section provides functions allowing to initialize/de-initialize
bogdanm 0:9b334a45a8ff 155 the NOR memory
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 @endverbatim
bogdanm 0:9b334a45a8ff 158 * @{
bogdanm 0:9b334a45a8ff 159 */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /**
bogdanm 0:9b334a45a8ff 162 * @brief Perform the NOR memory Initialization sequence
bogdanm 0:9b334a45a8ff 163 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 164 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 165 * @param Timing: pointer to NOR control timing structure
bogdanm 0:9b334a45a8ff 166 * @param ExtTiming: pointer to NOR extended mode timing structure
bogdanm 0:9b334a45a8ff 167 * @retval HAL status
bogdanm 0:9b334a45a8ff 168 */
bogdanm 0:9b334a45a8ff 169 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
bogdanm 0:9b334a45a8ff 170 {
bogdanm 0:9b334a45a8ff 171 /* Check the NOR handle parameter */
bogdanm 0:9b334a45a8ff 172 if(hnor == NULL)
bogdanm 0:9b334a45a8ff 173 {
bogdanm 0:9b334a45a8ff 174 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 175 }
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 if(hnor->State == HAL_NOR_STATE_RESET)
bogdanm 0:9b334a45a8ff 178 {
bogdanm 0:9b334a45a8ff 179 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 180 hnor->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 181 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 182 HAL_NOR_MspInit(hnor);
bogdanm 0:9b334a45a8ff 183 }
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /* Initialize NOR control Interface */
bogdanm 0:9b334a45a8ff 186 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 /* Initialize NOR timing Interface */
bogdanm 0:9b334a45a8ff 189 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 /* Initialize NOR extended mode timing Interface */
bogdanm 0:9b334a45a8ff 192 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /* Enable the NORSRAM device */
bogdanm 0:9b334a45a8ff 195 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 198 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 return HAL_OK;
bogdanm 0:9b334a45a8ff 201 }
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 /**
bogdanm 0:9b334a45a8ff 204 * @brief Perform NOR memory De-Initialization sequence
bogdanm 0:9b334a45a8ff 205 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 206 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 207 * @retval HAL status
bogdanm 0:9b334a45a8ff 208 */
bogdanm 0:9b334a45a8ff 209 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 210 {
bogdanm 0:9b334a45a8ff 211 /* De-Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 212 HAL_NOR_MspDeInit(hnor);
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 /* Configure the NOR registers with their reset values */
bogdanm 0:9b334a45a8ff 215 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 218 hnor->State = HAL_NOR_STATE_RESET;
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 /* Release Lock */
bogdanm 0:9b334a45a8ff 221 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 return HAL_OK;
bogdanm 0:9b334a45a8ff 224 }
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /**
bogdanm 0:9b334a45a8ff 227 * @brief NOR MSP Init
bogdanm 0:9b334a45a8ff 228 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 229 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 230 * @retval None
bogdanm 0:9b334a45a8ff 231 */
bogdanm 0:9b334a45a8ff 232 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 233 {
bogdanm 0:9b334a45a8ff 234 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 235 the HAL_NOR_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 236 */
bogdanm 0:9b334a45a8ff 237 }
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 /**
bogdanm 0:9b334a45a8ff 240 * @brief NOR MSP DeInit
bogdanm 0:9b334a45a8ff 241 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 242 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 243 * @retval None
bogdanm 0:9b334a45a8ff 244 */
bogdanm 0:9b334a45a8ff 245 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 246 {
bogdanm 0:9b334a45a8ff 247 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 248 the HAL_NOR_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 249 */
bogdanm 0:9b334a45a8ff 250 }
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 /**
bogdanm 0:9b334a45a8ff 253 * @brief NOR MSP Wait for Ready/Busy signal
bogdanm 0:9b334a45a8ff 254 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 255 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 256 * @param Timeout: Maximum timeout value
bogdanm 0:9b334a45a8ff 257 * @retval None
bogdanm 0:9b334a45a8ff 258 */
bogdanm 0:9b334a45a8ff 259 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 260 {
bogdanm 0:9b334a45a8ff 261 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 262 the HAL_NOR_MspWait could be implemented in the user file
bogdanm 0:9b334a45a8ff 263 */
bogdanm 0:9b334a45a8ff 264 }
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 /**
bogdanm 0:9b334a45a8ff 267 * @}
bogdanm 0:9b334a45a8ff 268 */
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
bogdanm 0:9b334a45a8ff 271 * @brief Input Output and memory control functions
bogdanm 0:9b334a45a8ff 272 *
bogdanm 0:9b334a45a8ff 273 @verbatim
bogdanm 0:9b334a45a8ff 274 ==============================================================================
bogdanm 0:9b334a45a8ff 275 ##### NOR Input and Output functions #####
bogdanm 0:9b334a45a8ff 276 ==============================================================================
bogdanm 0:9b334a45a8ff 277 [..]
bogdanm 0:9b334a45a8ff 278 This section provides functions allowing to use and control the NOR memory
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 @endverbatim
bogdanm 0:9b334a45a8ff 281 * @{
bogdanm 0:9b334a45a8ff 282 */
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /**
bogdanm 0:9b334a45a8ff 285 * @brief Read NOR flash IDs
bogdanm 0:9b334a45a8ff 286 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 287 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 288 * @param pNOR_ID : pointer to NOR ID structure
bogdanm 0:9b334a45a8ff 289 * @retval HAL status
bogdanm 0:9b334a45a8ff 290 */
bogdanm 0:9b334a45a8ff 291 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
bogdanm 0:9b334a45a8ff 292 {
bogdanm 0:9b334a45a8ff 293 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 /* Process Locked */
bogdanm 0:9b334a45a8ff 296 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 297
bogdanm 0:9b334a45a8ff 298 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 299 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 300 {
bogdanm 0:9b334a45a8ff 301 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 302 }
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 305 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 306 {
bogdanm 0:9b334a45a8ff 307 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 308 }
bogdanm 0:9b334a45a8ff 309 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 310 {
bogdanm 0:9b334a45a8ff 311 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 312 }
bogdanm 0:9b334a45a8ff 313 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 314 {
bogdanm 0:9b334a45a8ff 315 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 316 }
bogdanm 0:9b334a45a8ff 317 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 318 {
bogdanm 0:9b334a45a8ff 319 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 320 }
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 323 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 /* Send read ID command */
bogdanm 0:9b334a45a8ff 326 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 327 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 328 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 /* Read the NOR IDs */
bogdanm 0:9b334a45a8ff 331 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);
bogdanm 0:9b334a45a8ff 332 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
bogdanm 0:9b334a45a8ff 333 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
bogdanm 0:9b334a45a8ff 334 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 337 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 /* Process unlocked */
bogdanm 0:9b334a45a8ff 340 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 return HAL_OK;
bogdanm 0:9b334a45a8ff 343 }
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 /**
bogdanm 0:9b334a45a8ff 346 * @brief Returns the NOR memory to Read mode.
bogdanm 0:9b334a45a8ff 347 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 348 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 349 * @retval HAL status
bogdanm 0:9b334a45a8ff 350 */
bogdanm 0:9b334a45a8ff 351 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 352 {
bogdanm 0:9b334a45a8ff 353 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /* Process Locked */
bogdanm 0:9b334a45a8ff 356 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 359 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 360 {
bogdanm 0:9b334a45a8ff 361 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 362 }
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 365 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 366 {
bogdanm 0:9b334a45a8ff 367 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 368 }
bogdanm 0:9b334a45a8ff 369 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 370 {
bogdanm 0:9b334a45a8ff 371 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 372 }
bogdanm 0:9b334a45a8ff 373 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 374 {
bogdanm 0:9b334a45a8ff 375 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 376 }
bogdanm 0:9b334a45a8ff 377 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 378 {
bogdanm 0:9b334a45a8ff 379 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 380 }
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 383
bogdanm 0:9b334a45a8ff 384 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 385 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 /* Process unlocked */
bogdanm 0:9b334a45a8ff 388 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 return HAL_OK;
bogdanm 0:9b334a45a8ff 391 }
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 /**
bogdanm 0:9b334a45a8ff 394 * @brief Read data from NOR memory
bogdanm 0:9b334a45a8ff 395 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 396 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 397 * @param pAddress: pointer to Device address
bogdanm 0:9b334a45a8ff 398 * @param pData : pointer to read data
bogdanm 0:9b334a45a8ff 399 * @retval HAL status
bogdanm 0:9b334a45a8ff 400 */
bogdanm 0:9b334a45a8ff 401 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
bogdanm 0:9b334a45a8ff 402 {
bogdanm 0:9b334a45a8ff 403 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 404
bogdanm 0:9b334a45a8ff 405 /* Process Locked */
bogdanm 0:9b334a45a8ff 406 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 407
bogdanm 0:9b334a45a8ff 408 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 409 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 410 {
bogdanm 0:9b334a45a8ff 411 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 412 }
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 415 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 416 {
bogdanm 0:9b334a45a8ff 417 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 418 }
bogdanm 0:9b334a45a8ff 419 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 420 {
bogdanm 0:9b334a45a8ff 421 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 422 }
bogdanm 0:9b334a45a8ff 423 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 424 {
bogdanm 0:9b334a45a8ff 425 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 426 }
bogdanm 0:9b334a45a8ff 427 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 428 {
bogdanm 0:9b334a45a8ff 429 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 430 }
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 433 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 /* Send read data command */
bogdanm 0:9b334a45a8ff 436 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 437 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 438 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 /* Read the data */
bogdanm 0:9b334a45a8ff 441 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 444 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /* Process unlocked */
bogdanm 0:9b334a45a8ff 447 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 return HAL_OK;
bogdanm 0:9b334a45a8ff 450 }
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 /**
bogdanm 0:9b334a45a8ff 453 * @brief Program data to NOR memory
bogdanm 0:9b334a45a8ff 454 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 455 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 456 * @param pAddress: Device address
bogdanm 0:9b334a45a8ff 457 * @param pData : pointer to the data to write
bogdanm 0:9b334a45a8ff 458 * @retval HAL status
bogdanm 0:9b334a45a8ff 459 */
bogdanm 0:9b334a45a8ff 460 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
bogdanm 0:9b334a45a8ff 461 {
bogdanm 0:9b334a45a8ff 462 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /* Process Locked */
bogdanm 0:9b334a45a8ff 465 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 468 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 469 {
bogdanm 0:9b334a45a8ff 470 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 471 }
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 474 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 475 {
bogdanm 0:9b334a45a8ff 476 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 477 }
bogdanm 0:9b334a45a8ff 478 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 479 {
bogdanm 0:9b334a45a8ff 480 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 481 }
bogdanm 0:9b334a45a8ff 482 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 483 {
bogdanm 0:9b334a45a8ff 484 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 485 }
bogdanm 0:9b334a45a8ff 486 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 487 {
bogdanm 0:9b334a45a8ff 488 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 489 }
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 492 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 /* Send program data command */
bogdanm 0:9b334a45a8ff 495 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 496 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 497 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
bogdanm 0:9b334a45a8ff 498
bogdanm 0:9b334a45a8ff 499 /* Write the data */
bogdanm 0:9b334a45a8ff 500 NOR_WRITE(pAddress, *pData);
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 503 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 /* Process unlocked */
bogdanm 0:9b334a45a8ff 506 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 return HAL_OK;
bogdanm 0:9b334a45a8ff 509 }
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 /**
bogdanm 0:9b334a45a8ff 512 * @brief Reads a half-word buffer from the NOR memory.
bogdanm 0:9b334a45a8ff 513 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 514 * @param uwAddress: NOR memory internal address to read from.
bogdanm 0:9b334a45a8ff 515 * @param pData: pointer to the buffer that receives the data read from the
bogdanm 0:9b334a45a8ff 516 * NOR memory.
bogdanm 0:9b334a45a8ff 517 * @param uwBufferSize : number of Half word to read.
bogdanm 0:9b334a45a8ff 518 * @retval HAL status
bogdanm 0:9b334a45a8ff 519 */
bogdanm 0:9b334a45a8ff 520 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
bogdanm 0:9b334a45a8ff 521 {
bogdanm 0:9b334a45a8ff 522 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /* Process Locked */
bogdanm 0:9b334a45a8ff 525 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 526
bogdanm 0:9b334a45a8ff 527 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 528 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 529 {
bogdanm 0:9b334a45a8ff 530 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 531 }
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 534 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 535 {
bogdanm 0:9b334a45a8ff 536 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 537 }
bogdanm 0:9b334a45a8ff 538 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 539 {
bogdanm 0:9b334a45a8ff 540 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 541 }
bogdanm 0:9b334a45a8ff 542 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 543 {
bogdanm 0:9b334a45a8ff 544 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 545 }
bogdanm 0:9b334a45a8ff 546 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 547 {
bogdanm 0:9b334a45a8ff 548 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 549 }
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 552 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 553
bogdanm 0:9b334a45a8ff 554 /* Send read data command */
bogdanm 0:9b334a45a8ff 555 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 556 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 557 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /* Read buffer */
bogdanm 0:9b334a45a8ff 560 while( uwBufferSize > 0)
bogdanm 0:9b334a45a8ff 561 {
bogdanm 0:9b334a45a8ff 562 *pData++ = *(__IO uint16_t *)uwAddress;
bogdanm 0:9b334a45a8ff 563 uwAddress += 2;
bogdanm 0:9b334a45a8ff 564 uwBufferSize--;
bogdanm 0:9b334a45a8ff 565 }
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 568 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 569
bogdanm 0:9b334a45a8ff 570 /* Process unlocked */
bogdanm 0:9b334a45a8ff 571 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573 return HAL_OK;
bogdanm 0:9b334a45a8ff 574 }
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 /**
bogdanm 0:9b334a45a8ff 577 * @brief Writes a half-word buffer to the NOR memory. This function must be used
bogdanm 0:9b334a45a8ff 578 only with S29GL128P NOR memory.
bogdanm 0:9b334a45a8ff 579 * @param hnor: pointer to the NOR handle
bogdanm 0:9b334a45a8ff 580 * @param uwAddress: NOR memory internal start write address
bogdanm 0:9b334a45a8ff 581 * @param pData: pointer to source data buffer.
bogdanm 0:9b334a45a8ff 582 * @param uwBufferSize: Size of the buffer to write
bogdanm 0:9b334a45a8ff 583 * @retval HAL status
bogdanm 0:9b334a45a8ff 584 */
bogdanm 0:9b334a45a8ff 585 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
bogdanm 0:9b334a45a8ff 586 {
bogdanm 0:9b334a45a8ff 587 uint16_t * p_currentaddress = (uint16_t *)NULL;
bogdanm 0:9b334a45a8ff 588 uint16_t * p_endaddress = (uint16_t *)NULL;
bogdanm 0:9b334a45a8ff 589 uint32_t lastloadedaddress = 0, deviceaddress = 0;
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 /* Process Locked */
bogdanm 0:9b334a45a8ff 592 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 593
bogdanm 0:9b334a45a8ff 594 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 595 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 596 {
bogdanm 0:9b334a45a8ff 597 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 598 }
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 601 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 602 {
bogdanm 0:9b334a45a8ff 603 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 604 }
bogdanm 0:9b334a45a8ff 605 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 606 {
bogdanm 0:9b334a45a8ff 607 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 608 }
bogdanm 0:9b334a45a8ff 609 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 610 {
bogdanm 0:9b334a45a8ff 611 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 612 }
bogdanm 0:9b334a45a8ff 613 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 614 {
bogdanm 0:9b334a45a8ff 615 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 616 }
bogdanm 0:9b334a45a8ff 617
bogdanm 0:9b334a45a8ff 618 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 619 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 620
bogdanm 0:9b334a45a8ff 621 /* Initialize variables */
bogdanm 0:9b334a45a8ff 622 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
bogdanm 0:9b334a45a8ff 623 p_endaddress = p_currentaddress + (uwBufferSize-1);
bogdanm 0:9b334a45a8ff 624 lastloadedaddress = (uint32_t)(uwAddress);
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 /* Issue unlock command sequence */
bogdanm 0:9b334a45a8ff 627 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 628 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 629
bogdanm 0:9b334a45a8ff 630 /* Write Buffer Load Command */
bogdanm 0:9b334a45a8ff 631 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
bogdanm 0:9b334a45a8ff 632 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
bogdanm 0:9b334a45a8ff 633
bogdanm 0:9b334a45a8ff 634 /* Load Data into NOR Buffer */
bogdanm 0:9b334a45a8ff 635 while(p_currentaddress <= p_endaddress)
bogdanm 0:9b334a45a8ff 636 {
bogdanm 0:9b334a45a8ff 637 /* Store last loaded address & data value (for polling) */
bogdanm 0:9b334a45a8ff 638 lastloadedaddress = (uint32_t)p_currentaddress;
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 NOR_WRITE(p_currentaddress, *pData++);
bogdanm 0:9b334a45a8ff 641
bogdanm 0:9b334a45a8ff 642 p_currentaddress ++;
bogdanm 0:9b334a45a8ff 643 }
bogdanm 0:9b334a45a8ff 644
bogdanm 0:9b334a45a8ff 645 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
bogdanm 0:9b334a45a8ff 646
bogdanm 0:9b334a45a8ff 647 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 648 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 649
bogdanm 0:9b334a45a8ff 650 /* Process unlocked */
bogdanm 0:9b334a45a8ff 651 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 652
bogdanm 0:9b334a45a8ff 653 return HAL_OK;
bogdanm 0:9b334a45a8ff 654
bogdanm 0:9b334a45a8ff 655 }
bogdanm 0:9b334a45a8ff 656
bogdanm 0:9b334a45a8ff 657 /**
bogdanm 0:9b334a45a8ff 658 * @brief Erase the specified block of the NOR memory
bogdanm 0:9b334a45a8ff 659 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 660 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 661 * @param BlockAddress : Block to erase address
bogdanm 0:9b334a45a8ff 662 * @param Address: Device address
bogdanm 0:9b334a45a8ff 663 * @retval HAL status
bogdanm 0:9b334a45a8ff 664 */
bogdanm 0:9b334a45a8ff 665 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
bogdanm 0:9b334a45a8ff 666 {
bogdanm 0:9b334a45a8ff 667 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 668
bogdanm 0:9b334a45a8ff 669 /* Process Locked */
bogdanm 0:9b334a45a8ff 670 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 673 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 674 {
bogdanm 0:9b334a45a8ff 675 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 676 }
bogdanm 0:9b334a45a8ff 677
bogdanm 0:9b334a45a8ff 678 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 679 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 680 {
bogdanm 0:9b334a45a8ff 681 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 682 }
bogdanm 0:9b334a45a8ff 683 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 684 {
bogdanm 0:9b334a45a8ff 685 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 686 }
bogdanm 0:9b334a45a8ff 687 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 688 {
bogdanm 0:9b334a45a8ff 689 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 690 }
bogdanm 0:9b334a45a8ff 691 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 692 {
bogdanm 0:9b334a45a8ff 693 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 694 }
bogdanm 0:9b334a45a8ff 695
bogdanm 0:9b334a45a8ff 696 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 697 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 698
bogdanm 0:9b334a45a8ff 699 /* Send block erase command sequence */
bogdanm 0:9b334a45a8ff 700 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 701 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 702 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
bogdanm 0:9b334a45a8ff 703 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
bogdanm 0:9b334a45a8ff 704 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
bogdanm 0:9b334a45a8ff 705 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
bogdanm 0:9b334a45a8ff 706
bogdanm 0:9b334a45a8ff 707 /* Check the NOR memory status and update the controller state */
bogdanm 0:9b334a45a8ff 708 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 709
bogdanm 0:9b334a45a8ff 710 /* Process unlocked */
bogdanm 0:9b334a45a8ff 711 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 return HAL_OK;
bogdanm 0:9b334a45a8ff 714
bogdanm 0:9b334a45a8ff 715 }
bogdanm 0:9b334a45a8ff 716
bogdanm 0:9b334a45a8ff 717 /**
bogdanm 0:9b334a45a8ff 718 * @brief Erase the entire NOR chip.
bogdanm 0:9b334a45a8ff 719 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 720 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 721 * @param Address : Device address
bogdanm 0:9b334a45a8ff 722 * @retval HAL status
bogdanm 0:9b334a45a8ff 723 */
bogdanm 0:9b334a45a8ff 724 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
bogdanm 0:9b334a45a8ff 725 {
bogdanm 0:9b334a45a8ff 726 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 727
bogdanm 0:9b334a45a8ff 728 /* Process Locked */
bogdanm 0:9b334a45a8ff 729 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 730
bogdanm 0:9b334a45a8ff 731 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 732 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 733 {
bogdanm 0:9b334a45a8ff 734 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 735 }
bogdanm 0:9b334a45a8ff 736
bogdanm 0:9b334a45a8ff 737 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 738 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 739 {
bogdanm 0:9b334a45a8ff 740 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 741 }
bogdanm 0:9b334a45a8ff 742 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 743 {
bogdanm 0:9b334a45a8ff 744 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 745 }
bogdanm 0:9b334a45a8ff 746 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 747 {
bogdanm 0:9b334a45a8ff 748 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 749 }
bogdanm 0:9b334a45a8ff 750 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 751 {
bogdanm 0:9b334a45a8ff 752 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 753 }
bogdanm 0:9b334a45a8ff 754
bogdanm 0:9b334a45a8ff 755 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 756 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 757
bogdanm 0:9b334a45a8ff 758 /* Send NOR chip erase command sequence */
bogdanm 0:9b334a45a8ff 759 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
bogdanm 0:9b334a45a8ff 760 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
bogdanm 0:9b334a45a8ff 761 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
bogdanm 0:9b334a45a8ff 762 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
bogdanm 0:9b334a45a8ff 763 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
bogdanm 0:9b334a45a8ff 764 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
bogdanm 0:9b334a45a8ff 765
bogdanm 0:9b334a45a8ff 766 /* Check the NOR memory status and update the controller state */
bogdanm 0:9b334a45a8ff 767 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 768
bogdanm 0:9b334a45a8ff 769 /* Process unlocked */
bogdanm 0:9b334a45a8ff 770 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 771
bogdanm 0:9b334a45a8ff 772 return HAL_OK;
bogdanm 0:9b334a45a8ff 773 }
bogdanm 0:9b334a45a8ff 774
bogdanm 0:9b334a45a8ff 775 /**
bogdanm 0:9b334a45a8ff 776 * @brief Read NOR flash CFI IDs
bogdanm 0:9b334a45a8ff 777 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 778 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 779 * @param pNOR_CFI : pointer to NOR CFI IDs structure
bogdanm 0:9b334a45a8ff 780 * @retval HAL status
bogdanm 0:9b334a45a8ff 781 */
bogdanm 0:9b334a45a8ff 782 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
bogdanm 0:9b334a45a8ff 783 {
bogdanm 0:9b334a45a8ff 784 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 785
bogdanm 0:9b334a45a8ff 786 /* Process Locked */
bogdanm 0:9b334a45a8ff 787 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 788
bogdanm 0:9b334a45a8ff 789 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 790 if(hnor->State == HAL_NOR_STATE_BUSY)
bogdanm 0:9b334a45a8ff 791 {
bogdanm 0:9b334a45a8ff 792 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 793 }
bogdanm 0:9b334a45a8ff 794
bogdanm 0:9b334a45a8ff 795 /* Select the NOR device address */
bogdanm 0:9b334a45a8ff 796 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 797 {
bogdanm 0:9b334a45a8ff 798 deviceaddress = NOR_MEMORY_ADRESS1;
bogdanm 0:9b334a45a8ff 799 }
bogdanm 0:9b334a45a8ff 800 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
bogdanm 0:9b334a45a8ff 801 {
bogdanm 0:9b334a45a8ff 802 deviceaddress = NOR_MEMORY_ADRESS2;
bogdanm 0:9b334a45a8ff 803 }
bogdanm 0:9b334a45a8ff 804 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
bogdanm 0:9b334a45a8ff 805 {
bogdanm 0:9b334a45a8ff 806 deviceaddress = NOR_MEMORY_ADRESS3;
bogdanm 0:9b334a45a8ff 807 }
bogdanm 0:9b334a45a8ff 808 else /* FMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 809 {
bogdanm 0:9b334a45a8ff 810 deviceaddress = NOR_MEMORY_ADRESS4;
bogdanm 0:9b334a45a8ff 811 }
bogdanm 0:9b334a45a8ff 812
bogdanm 0:9b334a45a8ff 813 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 814 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 815
bogdanm 0:9b334a45a8ff 816 /* Send read CFI query command */
bogdanm 0:9b334a45a8ff 817 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
bogdanm 0:9b334a45a8ff 818
bogdanm 0:9b334a45a8ff 819 /* read the NOR CFI information */
bogdanm 0:9b334a45a8ff 820 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);
bogdanm 0:9b334a45a8ff 821 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);
bogdanm 0:9b334a45a8ff 822 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);
bogdanm 0:9b334a45a8ff 823 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);
bogdanm 0:9b334a45a8ff 824
bogdanm 0:9b334a45a8ff 825 /* Check the NOR controller state */
bogdanm 0:9b334a45a8ff 826 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 827
bogdanm 0:9b334a45a8ff 828 /* Process unlocked */
bogdanm 0:9b334a45a8ff 829 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 830
bogdanm 0:9b334a45a8ff 831 return HAL_OK;
bogdanm 0:9b334a45a8ff 832 }
bogdanm 0:9b334a45a8ff 833
bogdanm 0:9b334a45a8ff 834 /**
bogdanm 0:9b334a45a8ff 835 * @}
bogdanm 0:9b334a45a8ff 836 */
bogdanm 0:9b334a45a8ff 837
bogdanm 0:9b334a45a8ff 838 /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
bogdanm 0:9b334a45a8ff 839 * @brief management functions
bogdanm 0:9b334a45a8ff 840 *
bogdanm 0:9b334a45a8ff 841 @verbatim
bogdanm 0:9b334a45a8ff 842 ==============================================================================
bogdanm 0:9b334a45a8ff 843 ##### NOR Control functions #####
bogdanm 0:9b334a45a8ff 844 ==============================================================================
bogdanm 0:9b334a45a8ff 845 [..]
bogdanm 0:9b334a45a8ff 846 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 847 the NOR interface.
bogdanm 0:9b334a45a8ff 848
bogdanm 0:9b334a45a8ff 849 @endverbatim
bogdanm 0:9b334a45a8ff 850 * @{
bogdanm 0:9b334a45a8ff 851 */
bogdanm 0:9b334a45a8ff 852
bogdanm 0:9b334a45a8ff 853 /**
bogdanm 0:9b334a45a8ff 854 * @brief Enables dynamically NOR write operation.
bogdanm 0:9b334a45a8ff 855 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 856 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 857 * @retval HAL status
bogdanm 0:9b334a45a8ff 858 */
bogdanm 0:9b334a45a8ff 859 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 860 {
bogdanm 0:9b334a45a8ff 861 /* Process Locked */
bogdanm 0:9b334a45a8ff 862 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 863
bogdanm 0:9b334a45a8ff 864 /* Enable write operation */
bogdanm 0:9b334a45a8ff 865 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 866
bogdanm 0:9b334a45a8ff 867 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 868 hnor->State = HAL_NOR_STATE_READY;
bogdanm 0:9b334a45a8ff 869
bogdanm 0:9b334a45a8ff 870 /* Process unlocked */
bogdanm 0:9b334a45a8ff 871 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 872
bogdanm 0:9b334a45a8ff 873 return HAL_OK;
bogdanm 0:9b334a45a8ff 874 }
bogdanm 0:9b334a45a8ff 875
bogdanm 0:9b334a45a8ff 876 /**
bogdanm 0:9b334a45a8ff 877 * @brief Disables dynamically NOR write operation.
bogdanm 0:9b334a45a8ff 878 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 879 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 880 * @retval HAL status
bogdanm 0:9b334a45a8ff 881 */
bogdanm 0:9b334a45a8ff 882 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 883 {
bogdanm 0:9b334a45a8ff 884 /* Process Locked */
bogdanm 0:9b334a45a8ff 885 __HAL_LOCK(hnor);
bogdanm 0:9b334a45a8ff 886
bogdanm 0:9b334a45a8ff 887 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 888 hnor->State = HAL_NOR_STATE_BUSY;
bogdanm 0:9b334a45a8ff 889
bogdanm 0:9b334a45a8ff 890 /* Disable write operation */
bogdanm 0:9b334a45a8ff 891 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
bogdanm 0:9b334a45a8ff 892
bogdanm 0:9b334a45a8ff 893 /* Update the NOR controller state */
bogdanm 0:9b334a45a8ff 894 hnor->State = HAL_NOR_STATE_PROTECTED;
bogdanm 0:9b334a45a8ff 895
bogdanm 0:9b334a45a8ff 896 /* Process unlocked */
bogdanm 0:9b334a45a8ff 897 __HAL_UNLOCK(hnor);
bogdanm 0:9b334a45a8ff 898
bogdanm 0:9b334a45a8ff 899 return HAL_OK;
bogdanm 0:9b334a45a8ff 900 }
bogdanm 0:9b334a45a8ff 901
bogdanm 0:9b334a45a8ff 902 /**
bogdanm 0:9b334a45a8ff 903 * @}
bogdanm 0:9b334a45a8ff 904 */
bogdanm 0:9b334a45a8ff 905
bogdanm 0:9b334a45a8ff 906 /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
bogdanm 0:9b334a45a8ff 907 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 908 *
bogdanm 0:9b334a45a8ff 909 @verbatim
bogdanm 0:9b334a45a8ff 910 ==============================================================================
bogdanm 0:9b334a45a8ff 911 ##### NOR State functions #####
bogdanm 0:9b334a45a8ff 912 ==============================================================================
bogdanm 0:9b334a45a8ff 913 [..]
bogdanm 0:9b334a45a8ff 914 This subsection permits to get in run-time the status of the NOR controller
bogdanm 0:9b334a45a8ff 915 and the data flow.
bogdanm 0:9b334a45a8ff 916
bogdanm 0:9b334a45a8ff 917 @endverbatim
bogdanm 0:9b334a45a8ff 918 * @{
bogdanm 0:9b334a45a8ff 919 */
bogdanm 0:9b334a45a8ff 920
bogdanm 0:9b334a45a8ff 921 /**
bogdanm 0:9b334a45a8ff 922 * @brief return the NOR controller state
bogdanm 0:9b334a45a8ff 923 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 924 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 925 * @retval NOR controller state
bogdanm 0:9b334a45a8ff 926 */
bogdanm 0:9b334a45a8ff 927 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
bogdanm 0:9b334a45a8ff 928 {
bogdanm 0:9b334a45a8ff 929 return hnor->State;
bogdanm 0:9b334a45a8ff 930 }
bogdanm 0:9b334a45a8ff 931
bogdanm 0:9b334a45a8ff 932 /**
bogdanm 0:9b334a45a8ff 933 * @brief Returns the NOR operation status.
bogdanm 0:9b334a45a8ff 934 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 935 * the configuration information for NOR module.
bogdanm 0:9b334a45a8ff 936 * @param Address: Device address
bogdanm 0:9b334a45a8ff 937 * @param Timeout: NOR programming Timeout
bogdanm 0:9b334a45a8ff 938 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
bogdanm 0:9b334a45a8ff 939 * or HAL_NOR_STATUS_TIMEOUT
bogdanm 0:9b334a45a8ff 940 */
bogdanm 0:9b334a45a8ff 941 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 942 {
bogdanm 0:9b334a45a8ff 943 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
bogdanm 0:9b334a45a8ff 944 uint16_t tmpSR1 = 0, tmpSR2 = 0;
bogdanm 0:9b334a45a8ff 945 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 946
bogdanm 0:9b334a45a8ff 947 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
bogdanm 0:9b334a45a8ff 948 HAL_NOR_MspWait(hnor, Timeout);
bogdanm 0:9b334a45a8ff 949
bogdanm 0:9b334a45a8ff 950 /* Get the NOR memory operation status -------------------------------------*/
bogdanm 0:9b334a45a8ff 951
bogdanm 0:9b334a45a8ff 952 /* Get tick */
bogdanm 0:9b334a45a8ff 953 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 954 while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
bogdanm 0:9b334a45a8ff 955 {
bogdanm 0:9b334a45a8ff 956 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 957 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 958 {
bogdanm 0:9b334a45a8ff 959 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 960 {
bogdanm 0:9b334a45a8ff 961 status = HAL_NOR_STATUS_TIMEOUT;
bogdanm 0:9b334a45a8ff 962 }
bogdanm 0:9b334a45a8ff 963 }
bogdanm 0:9b334a45a8ff 964
bogdanm 0:9b334a45a8ff 965 /* Read NOR status register (DQ6 and DQ5) */
bogdanm 0:9b334a45a8ff 966 tmpSR1 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 967 tmpSR2 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 968
bogdanm 0:9b334a45a8ff 969 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
bogdanm 0:9b334a45a8ff 970 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
bogdanm 0:9b334a45a8ff 971 {
bogdanm 0:9b334a45a8ff 972 return HAL_NOR_STATUS_SUCCESS ;
bogdanm 0:9b334a45a8ff 973 }
bogdanm 0:9b334a45a8ff 974
bogdanm 0:9b334a45a8ff 975 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
bogdanm 0:9b334a45a8ff 976 {
bogdanm 0:9b334a45a8ff 977 status = HAL_NOR_STATUS_ONGOING;
bogdanm 0:9b334a45a8ff 978 }
bogdanm 0:9b334a45a8ff 979
bogdanm 0:9b334a45a8ff 980 tmpSR1 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 981 tmpSR2 = *(__IO uint16_t *)Address;
bogdanm 0:9b334a45a8ff 982
bogdanm 0:9b334a45a8ff 983 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
bogdanm 0:9b334a45a8ff 984 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
bogdanm 0:9b334a45a8ff 985 {
bogdanm 0:9b334a45a8ff 986 return HAL_NOR_STATUS_SUCCESS;
bogdanm 0:9b334a45a8ff 987 }
bogdanm 0:9b334a45a8ff 988 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
bogdanm 0:9b334a45a8ff 989 {
bogdanm 0:9b334a45a8ff 990 return HAL_NOR_STATUS_ERROR;
bogdanm 0:9b334a45a8ff 991 }
bogdanm 0:9b334a45a8ff 992 }
bogdanm 0:9b334a45a8ff 993
bogdanm 0:9b334a45a8ff 994 /* Return the operation status */
bogdanm 0:9b334a45a8ff 995 return status;
bogdanm 0:9b334a45a8ff 996 }
bogdanm 0:9b334a45a8ff 997
bogdanm 0:9b334a45a8ff 998 /**
bogdanm 0:9b334a45a8ff 999 * @}
bogdanm 0:9b334a45a8ff 1000 */
bogdanm 0:9b334a45a8ff 1001
bogdanm 0:9b334a45a8ff 1002 /**
bogdanm 0:9b334a45a8ff 1003 * @}
bogdanm 0:9b334a45a8ff 1004 */
bogdanm 0:9b334a45a8ff 1005 #endif /* HAL_NOR_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1006 /**
bogdanm 0:9b334a45a8ff 1007 * @}
bogdanm 0:9b334a45a8ff 1008 */
bogdanm 0:9b334a45a8ff 1009
bogdanm 0:9b334a45a8ff 1010 /**
bogdanm 0:9b334a45a8ff 1011 * @}
bogdanm 0:9b334a45a8ff 1012 */
bogdanm 0:9b334a45a8ff 1013
bogdanm 0:9b334a45a8ff 1014 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/