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fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
19:112740acecfa
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

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bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_hal_spi.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.3.2
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief Header file of SPI HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32F4xx_HAL_SPI_H
bogdanm 0:9b334a45a8ff 40 #define __STM32F4xx_HAL_SPI_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32f4xx_hal_def.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @addtogroup SPI
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Exported types ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58 /** @defgroup SPI_Exported_Types SPI Exported Types
bogdanm 0:9b334a45a8ff 59 * @{
bogdanm 0:9b334a45a8ff 60 */
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 /**
bogdanm 0:9b334a45a8ff 63 * @brief SPI Configuration Structure definition
bogdanm 0:9b334a45a8ff 64 */
bogdanm 0:9b334a45a8ff 65 typedef struct
bogdanm 0:9b334a45a8ff 66 {
bogdanm 0:9b334a45a8ff 67 uint32_t Mode; /*!< Specifies the SPI operating mode.
bogdanm 0:9b334a45a8ff 68 This parameter can be a value of @ref SPI_mode */
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 uint32_t Direction; /*!< Specifies the SPI Directional mode state.
bogdanm 0:9b334a45a8ff 71 This parameter can be a value of @ref SPI_Direction_mode */
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 uint32_t DataSize; /*!< Specifies the SPI data size.
bogdanm 0:9b334a45a8ff 74 This parameter can be a value of @ref SPI_data_size */
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
bogdanm 0:9b334a45a8ff 77 This parameter can be a value of @ref SPI_Clock_Polarity */
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
bogdanm 0:9b334a45a8ff 80 This parameter can be a value of @ref SPI_Clock_Phase */
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
bogdanm 0:9b334a45a8ff 83 hardware (NSS pin) or by software using the SSI bit.
bogdanm 0:9b334a45a8ff 84 This parameter can be a value of @ref SPI_Slave_Select_management */
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
bogdanm 0:9b334a45a8ff 87 used to configure the transmit and receive SCK clock.
bogdanm 0:9b334a45a8ff 88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
bogdanm 0:9b334a45a8ff 89 @note The communication clock is derived from the master
bogdanm 0:9b334a45a8ff 90 clock. The slave clock does not need to be set */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
bogdanm 0:9b334a45a8ff 93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
bogdanm 0:9b334a45a8ff 96 This parameter can be a value of @ref SPI_TI_mode */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
bogdanm 0:9b334a45a8ff 99 This parameter can be a value of @ref SPI_CRC_Calculation */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
bogdanm 0:9b334a45a8ff 102 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 }SPI_InitTypeDef;
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /**
bogdanm 0:9b334a45a8ff 107 * @brief HAL SPI State structure definition
bogdanm 0:9b334a45a8ff 108 */
bogdanm 0:9b334a45a8ff 109 typedef enum
bogdanm 0:9b334a45a8ff 110 {
bogdanm 0:9b334a45a8ff 111 HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
bogdanm 0:9b334a45a8ff 112 HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
bogdanm 0:9b334a45a8ff 113 HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
bogdanm 0:9b334a45a8ff 114 HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
bogdanm 0:9b334a45a8ff 115 HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
bogdanm 0:9b334a45a8ff 116 HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
bogdanm 0:9b334a45a8ff 117 HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 }HAL_SPI_StateTypeDef;
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 /**
bogdanm 0:9b334a45a8ff 122 * @brief SPI handle Structure definition
bogdanm 0:9b334a45a8ff 123 */
bogdanm 0:9b334a45a8ff 124 typedef struct __SPI_HandleTypeDef
bogdanm 0:9b334a45a8ff 125 {
bogdanm 0:9b334a45a8ff 126 SPI_TypeDef *Instance; /* SPI registers base address */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 SPI_InitTypeDef Init; /* SPI communication parameters */
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 uint16_t TxXferSize; /* SPI Tx transfer size */
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 uint16_t TxXferCount; /* SPI Tx Transfer Counter */
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 uint16_t RxXferSize; /* SPI Rx transfer size */
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 uint16_t RxXferCount; /* SPI Rx Transfer Counter */
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 HAL_LockTypeDef Lock; /* SPI locking object */
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 __IO uint32_t ErrorCode; /* SPI Error code */
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 }SPI_HandleTypeDef;
bogdanm 0:9b334a45a8ff 157 /**
bogdanm 0:9b334a45a8ff 158 * @}
bogdanm 0:9b334a45a8ff 159 */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 162 /** @defgroup SPI_Exported_Constants SPI Exported Constants
bogdanm 0:9b334a45a8ff 163 * @{
bogdanm 0:9b334a45a8ff 164 */
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 /** @defgroup SPI_Error_Code SPI Error Code
bogdanm 0:9b334a45a8ff 167 * @brief SPI Error Code
bogdanm 0:9b334a45a8ff 168 * @{
bogdanm 0:9b334a45a8ff 169 */
bogdanm 0:9b334a45a8ff 170 #define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 0:9b334a45a8ff 171 #define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001) /*!< MODF error */
bogdanm 0:9b334a45a8ff 172 #define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002) /*!< CRC error */
bogdanm 0:9b334a45a8ff 173 #define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004) /*!< OVR error */
bogdanm 0:9b334a45a8ff 174 #define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008) /*!< FRE error */
bogdanm 0:9b334a45a8ff 175 #define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
bogdanm 0:9b334a45a8ff 176 #define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020) /*!< Flag: RXNE,TXE, BSY */
bogdanm 0:9b334a45a8ff 177 /**
bogdanm 0:9b334a45a8ff 178 * @}
bogdanm 0:9b334a45a8ff 179 */
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 /** @defgroup SPI_mode SPI Mode
bogdanm 0:9b334a45a8ff 182 * @{
bogdanm 0:9b334a45a8ff 183 */
bogdanm 0:9b334a45a8ff 184 #define SPI_MODE_SLAVE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 185 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
bogdanm 0:9b334a45a8ff 186 /**
bogdanm 0:9b334a45a8ff 187 * @}
bogdanm 0:9b334a45a8ff 188 */
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /** @defgroup SPI_Direction_mode SPI Direction Mode
bogdanm 0:9b334a45a8ff 191 * @{
bogdanm 0:9b334a45a8ff 192 */
bogdanm 0:9b334a45a8ff 193 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 194 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
bogdanm 0:9b334a45a8ff 195 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
bogdanm 0:9b334a45a8ff 196 /**
bogdanm 0:9b334a45a8ff 197 * @}
bogdanm 0:9b334a45a8ff 198 */
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 /** @defgroup SPI_data_size SPI Data Size
bogdanm 0:9b334a45a8ff 201 * @{
bogdanm 0:9b334a45a8ff 202 */
bogdanm 0:9b334a45a8ff 203 #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 204 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
bogdanm 0:9b334a45a8ff 205 /**
bogdanm 0:9b334a45a8ff 206 * @}
bogdanm 0:9b334a45a8ff 207 */
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
bogdanm 0:9b334a45a8ff 210 * @{
bogdanm 0:9b334a45a8ff 211 */
bogdanm 0:9b334a45a8ff 212 #define SPI_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 213 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
bogdanm 0:9b334a45a8ff 214 /**
bogdanm 0:9b334a45a8ff 215 * @}
bogdanm 0:9b334a45a8ff 216 */
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /** @defgroup SPI_Clock_Phase SPI Clock Phase
bogdanm 0:9b334a45a8ff 219 * @{
bogdanm 0:9b334a45a8ff 220 */
bogdanm 0:9b334a45a8ff 221 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 222 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
bogdanm 0:9b334a45a8ff 223 /**
bogdanm 0:9b334a45a8ff 224 * @}
bogdanm 0:9b334a45a8ff 225 */
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
bogdanm 0:9b334a45a8ff 228 * @{
bogdanm 0:9b334a45a8ff 229 */
bogdanm 0:9b334a45a8ff 230 #define SPI_NSS_SOFT SPI_CR1_SSM
bogdanm 0:9b334a45a8ff 231 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 232 #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 233 /**
bogdanm 0:9b334a45a8ff 234 * @}
bogdanm 0:9b334a45a8ff 235 */
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
bogdanm 0:9b334a45a8ff 238 * @{
bogdanm 0:9b334a45a8ff 239 */
bogdanm 0:9b334a45a8ff 240 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 241 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 242 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 243 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
bogdanm 0:9b334a45a8ff 244 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 245 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
bogdanm 0:9b334a45a8ff 246 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 247 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
bogdanm 0:9b334a45a8ff 248 /**
bogdanm 0:9b334a45a8ff 249 * @}
bogdanm 0:9b334a45a8ff 250 */
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transsmission
bogdanm 0:9b334a45a8ff 253 * @{
bogdanm 0:9b334a45a8ff 254 */
bogdanm 0:9b334a45a8ff 255 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 256 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
bogdanm 0:9b334a45a8ff 257 /**
bogdanm 0:9b334a45a8ff 258 * @}
bogdanm 0:9b334a45a8ff 259 */
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 /** @defgroup SPI_TI_mode SPI TI Mode
bogdanm 0:9b334a45a8ff 262 * @{
bogdanm 0:9b334a45a8ff 263 */
bogdanm 0:9b334a45a8ff 264 #define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 265 #define SPI_TIMODE_ENABLE SPI_CR2_FRF
bogdanm 0:9b334a45a8ff 266 /**
bogdanm 0:9b334a45a8ff 267 * @}
bogdanm 0:9b334a45a8ff 268 */
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
bogdanm 0:9b334a45a8ff 271 * @{
bogdanm 0:9b334a45a8ff 272 */
bogdanm 0:9b334a45a8ff 273 #define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 274 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
bogdanm 0:9b334a45a8ff 275 /**
bogdanm 0:9b334a45a8ff 276 * @}
bogdanm 0:9b334a45a8ff 277 */
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
bogdanm 0:9b334a45a8ff 280 * @{
bogdanm 0:9b334a45a8ff 281 */
bogdanm 0:9b334a45a8ff 282 #define SPI_IT_TXE SPI_CR2_TXEIE
bogdanm 0:9b334a45a8ff 283 #define SPI_IT_RXNE SPI_CR2_RXNEIE
bogdanm 0:9b334a45a8ff 284 #define SPI_IT_ERR SPI_CR2_ERRIE
bogdanm 0:9b334a45a8ff 285 /**
bogdanm 0:9b334a45a8ff 286 * @}
bogdanm 0:9b334a45a8ff 287 */
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 /** @defgroup SPI_Flags_definition SPI Flags Definition
bogdanm 0:9b334a45a8ff 290 * @{
bogdanm 0:9b334a45a8ff 291 */
bogdanm 0:9b334a45a8ff 292 #define SPI_FLAG_RXNE SPI_SR_RXNE
bogdanm 0:9b334a45a8ff 293 #define SPI_FLAG_TXE SPI_SR_TXE
bogdanm 0:9b334a45a8ff 294 #define SPI_FLAG_CRCERR SPI_SR_CRCERR
bogdanm 0:9b334a45a8ff 295 #define SPI_FLAG_MODF SPI_SR_MODF
bogdanm 0:9b334a45a8ff 296 #define SPI_FLAG_OVR SPI_SR_OVR
bogdanm 0:9b334a45a8ff 297 #define SPI_FLAG_BSY SPI_SR_BSY
bogdanm 0:9b334a45a8ff 298 #define SPI_FLAG_FRE SPI_SR_FRE
bogdanm 0:9b334a45a8ff 299 /**
bogdanm 0:9b334a45a8ff 300 * @}
bogdanm 0:9b334a45a8ff 301 */
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 /**
bogdanm 0:9b334a45a8ff 304 * @}
bogdanm 0:9b334a45a8ff 305 */
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 /* Exported macro ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 308 /** @defgroup SPI_Exported_Macros SPI Exported Macros
bogdanm 0:9b334a45a8ff 309 * @{
bogdanm 0:9b334a45a8ff 310 */
bogdanm 0:9b334a45a8ff 311 /** @brief Reset SPI handle state
bogdanm 0:9b334a45a8ff 312 * @param __HANDLE__: specifies the SPI handle.
bogdanm 0:9b334a45a8ff 313 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 314 * @retval None
bogdanm 0:9b334a45a8ff 315 */
bogdanm 0:9b334a45a8ff 316 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 /** @brief Enable or disable the specified SPI interrupts.
bogdanm 0:9b334a45a8ff 319 * @param __HANDLE__: specifies the SPI handle.
bogdanm 0:9b334a45a8ff 320 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 321 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 0:9b334a45a8ff 322 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 323 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm 0:9b334a45a8ff 324 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 0:9b334a45a8ff 325 * @arg SPI_IT_ERR: Error interrupt enable
bogdanm 0:9b334a45a8ff 326 * @retval None
bogdanm 0:9b334a45a8ff 327 */
bogdanm 0:9b334a45a8ff 328 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 329 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /** @brief Check if the specified SPI interrupt source is enabled or disabled.
bogdanm 0:9b334a45a8ff 332 * @param __HANDLE__: specifies the SPI handle.
bogdanm 0:9b334a45a8ff 333 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 334 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
bogdanm 0:9b334a45a8ff 335 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 336 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm 0:9b334a45a8ff 337 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 0:9b334a45a8ff 338 * @arg SPI_IT_ERR: Error interrupt enable
bogdanm 0:9b334a45a8ff 339 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 0:9b334a45a8ff 340 */
bogdanm 0:9b334a45a8ff 341 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 /** @brief Check whether the specified SPI flag is set or not.
bogdanm 0:9b334a45a8ff 344 * @param __HANDLE__: specifies the SPI handle.
bogdanm 0:9b334a45a8ff 345 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 346 * @param __FLAG__: specifies the flag to check.
bogdanm 0:9b334a45a8ff 347 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 348 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
bogdanm 0:9b334a45a8ff 349 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
bogdanm 0:9b334a45a8ff 350 * @arg SPI_FLAG_CRCERR: CRC error flag
bogdanm 0:9b334a45a8ff 351 * @arg SPI_FLAG_MODF: Mode fault flag
bogdanm 0:9b334a45a8ff 352 * @arg SPI_FLAG_OVR: Overrun flag
bogdanm 0:9b334a45a8ff 353 * @arg SPI_FLAG_BSY: Busy flag
bogdanm 0:9b334a45a8ff 354 * @arg SPI_FLAG_FRE: Frame format error flag
bogdanm 0:9b334a45a8ff 355 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 0:9b334a45a8ff 356 */
bogdanm 0:9b334a45a8ff 357 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /** @brief Clear the SPI CRCERR pending flag.
bogdanm 0:9b334a45a8ff 360 * @param __HANDLE__: specifies the SPI handle.
bogdanm 0:9b334a45a8ff 361 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 362 * @retval None
bogdanm 0:9b334a45a8ff 363 */
bogdanm 0:9b334a45a8ff 364 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 /** @brief Clear the SPI MODF pending flag.
bogdanm 0:9b334a45a8ff 367 * @param __HANDLE__: specifies the SPI handle.
bogdanm 0:9b334a45a8ff 368 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 369 * @retval None
bogdanm 0:9b334a45a8ff 370 */
bogdanm 0:9b334a45a8ff 371 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
bogdanm 0:9b334a45a8ff 372 do{ \
bogdanm 0:9b334a45a8ff 373 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 374 tmpreg = (__HANDLE__)->Instance->SR; \
bogdanm 0:9b334a45a8ff 375 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
bogdanm 0:9b334a45a8ff 376 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 377 } while(0)
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 /** @brief Clear the SPI OVR pending flag.
bogdanm 0:9b334a45a8ff 380 * @param __HANDLE__: specifies the SPI handle.
bogdanm 0:9b334a45a8ff 381 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 382 * @retval None
bogdanm 0:9b334a45a8ff 383 */
bogdanm 0:9b334a45a8ff 384 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
bogdanm 0:9b334a45a8ff 385 do{ \
bogdanm 0:9b334a45a8ff 386 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 387 tmpreg = (__HANDLE__)->Instance->DR; \
bogdanm 0:9b334a45a8ff 388 tmpreg = (__HANDLE__)->Instance->SR; \
bogdanm 0:9b334a45a8ff 389 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 390 } while(0)
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 /** @brief Clear the SPI FRE pending flag.
bogdanm 0:9b334a45a8ff 393 * @param __HANDLE__: specifies the SPI handle.
bogdanm 0:9b334a45a8ff 394 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 0:9b334a45a8ff 395 * @retval None
bogdanm 0:9b334a45a8ff 396 */
bogdanm 0:9b334a45a8ff 397 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
bogdanm 0:9b334a45a8ff 398 do{ \
bogdanm 0:9b334a45a8ff 399 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 400 tmpreg = (__HANDLE__)->Instance->SR; \
bogdanm 0:9b334a45a8ff 401 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 402 }while(0)
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 /** @brief Enable SPI
bogdanm 0:9b334a45a8ff 405 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 0:9b334a45a8ff 406 * @retval None
bogdanm 0:9b334a45a8ff 407 */
bogdanm 0:9b334a45a8ff 408 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /** @brief Disable SPI
bogdanm 0:9b334a45a8ff 411 * @param __HANDLE__: specifies the SPI Handle.
bogdanm 0:9b334a45a8ff 412 * @retval None
bogdanm 0:9b334a45a8ff 413 */
bogdanm 0:9b334a45a8ff 414 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
bogdanm 0:9b334a45a8ff 415 /**
bogdanm 0:9b334a45a8ff 416 * @}
bogdanm 0:9b334a45a8ff 417 */
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 420 /** @addtogroup SPI_Exported_Functions
bogdanm 0:9b334a45a8ff 421 * @{
bogdanm 0:9b334a45a8ff 422 */
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /** @addtogroup SPI_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 425 * @{
bogdanm 0:9b334a45a8ff 426 */
bogdanm 0:9b334a45a8ff 427 /* Initialization/de-initialization functions **********************************/
bogdanm 0:9b334a45a8ff 428 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 429 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 430 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 431 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 432 /**
bogdanm 0:9b334a45a8ff 433 * @}
bogdanm 0:9b334a45a8ff 434 */
bogdanm 0:9b334a45a8ff 435
bogdanm 0:9b334a45a8ff 436 /** @addtogroup SPI_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 437 * @{
bogdanm 0:9b334a45a8ff 438 */
bogdanm 0:9b334a45a8ff 439 /* I/O operation functions *****************************************************/
bogdanm 0:9b334a45a8ff 440 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 441 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 442 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 443 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 0:9b334a45a8ff 444 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 0:9b334a45a8ff 445 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm 0:9b334a45a8ff 446 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 0:9b334a45a8ff 447 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 0:9b334a45a8ff 448 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm 0:9b334a45a8ff 449 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 450 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 451 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 454 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 455 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 456 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 457 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 458 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 459 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 460 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 461 /**
bogdanm 0:9b334a45a8ff 462 * @}
bogdanm 0:9b334a45a8ff 463 */
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 /** @addtogroup SPI_Exported_Functions_Group3
bogdanm 0:9b334a45a8ff 466 * @{
bogdanm 0:9b334a45a8ff 467 */
bogdanm 0:9b334a45a8ff 468 /* Peripheral State and Control functions **************************************/
bogdanm 0:9b334a45a8ff 469 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 470 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 /**
bogdanm 0:9b334a45a8ff 473 * @}
bogdanm 0:9b334a45a8ff 474 */
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /**
bogdanm 0:9b334a45a8ff 477 * @}
bogdanm 0:9b334a45a8ff 478 */
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 /* Private types -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 481 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 482 /* Private constants ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 483 /** @defgroup SPI_Private_Constants SPI Private Constants
bogdanm 0:9b334a45a8ff 484 * @{
bogdanm 0:9b334a45a8ff 485 */
bogdanm 0:9b334a45a8ff 486 /**
bogdanm 0:9b334a45a8ff 487 * @}
bogdanm 0:9b334a45a8ff 488 */
bogdanm 0:9b334a45a8ff 489
bogdanm 0:9b334a45a8ff 490 /* Private macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 491 /** @defgroup SPI_Private_Macros SPI Private Macros
bogdanm 0:9b334a45a8ff 492 * @{
bogdanm 0:9b334a45a8ff 493 */
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
bogdanm 0:9b334a45a8ff 496 ((MODE) == SPI_MODE_MASTER))
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498
bogdanm 0:9b334a45a8ff 499 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
bogdanm 0:9b334a45a8ff 500 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
bogdanm 0:9b334a45a8ff 501 ((MODE) == SPI_DIRECTION_1LINE))
bogdanm 0:9b334a45a8ff 502
bogdanm 0:9b334a45a8ff 503 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
bogdanm 0:9b334a45a8ff 504 ((MODE) == SPI_DIRECTION_1LINE))
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
bogdanm 0:9b334a45a8ff 509 ((DATASIZE) == SPI_DATASIZE_8BIT))
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
bogdanm 0:9b334a45a8ff 512 ((CPOL) == SPI_POLARITY_HIGH))
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
bogdanm 0:9b334a45a8ff 515 ((CPHA) == SPI_PHASE_2EDGE))
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
bogdanm 0:9b334a45a8ff 518 ((NSS) == SPI_NSS_HARD_INPUT) || \
bogdanm 0:9b334a45a8ff 519 ((NSS) == SPI_NSS_HARD_OUTPUT))
bogdanm 0:9b334a45a8ff 520
bogdanm 0:9b334a45a8ff 521 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
bogdanm 0:9b334a45a8ff 522 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
bogdanm 0:9b334a45a8ff 523 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
bogdanm 0:9b334a45a8ff 524 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
bogdanm 0:9b334a45a8ff 525 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
bogdanm 0:9b334a45a8ff 526 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
bogdanm 0:9b334a45a8ff 527 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
bogdanm 0:9b334a45a8ff 528 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
bogdanm 0:9b334a45a8ff 531 ((BIT) == SPI_FIRSTBIT_LSB))
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
bogdanm 0:9b334a45a8ff 534 ((MODE) == SPI_TIMODE_ENABLE))
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
bogdanm 0:9b334a45a8ff 537 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
bogdanm 0:9b334a45a8ff 542
bogdanm 0:9b334a45a8ff 543 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
bogdanm 0:9b334a45a8ff 546 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
bogdanm 0:9b334a45a8ff 547 /**
bogdanm 0:9b334a45a8ff 548 * @}
bogdanm 0:9b334a45a8ff 549 */
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 552 /** @defgroup SPI_Private_Functions SPI Private Functions
bogdanm 0:9b334a45a8ff 553 * @{
bogdanm 0:9b334a45a8ff 554 */
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556 /**
bogdanm 0:9b334a45a8ff 557 * @}
bogdanm 0:9b334a45a8ff 558 */
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 /**
bogdanm 0:9b334a45a8ff 561 * @}
bogdanm 0:9b334a45a8ff 562 */
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 /**
bogdanm 0:9b334a45a8ff 565 * @}
bogdanm 0:9b334a45a8ff 566 */
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568
bogdanm 0:9b334a45a8ff 569 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 570 }
bogdanm 0:9b334a45a8ff 571 #endif
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573 #endif /* __STM32F4xx_HAL_SPI_H */
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/