mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 19:112740acecfa

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f4xx_hal_rcc_ex.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.3.2
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of RCC HAL Extension module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F4xx_HAL_RCC_EX_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32f4xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup RCCEx
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62	/**
bogdanm	0:9b334a45a8ff	63	* @brief RCC PLL configuration structure definition
bogdanm	0:9b334a45a8ff	64	*/
bogdanm	0:9b334a45a8ff	65	typedef struct
bogdanm	0:9b334a45a8ff	66	{
bogdanm	0:9b334a45a8ff	67	uint32_t PLLState; /*!< The new state of the PLL.
bogdanm	0:9b334a45a8ff	68	This parameter can be a value of @ref RCC_PLL_Config */
bogdanm	0:9b334a45a8ff	69
bogdanm	0:9b334a45a8ff	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
bogdanm	0:9b334a45a8ff	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
bogdanm	0:9b334a45a8ff	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
bogdanm	0:9b334a45a8ff	75
bogdanm	0:9b334a45a8ff	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
bogdanm	0:9b334a45a8ff	77	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
bogdanm	0:9b334a45a8ff	78
bogdanm	0:9b334a45a8ff	79	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
bogdanm	0:9b334a45a8ff	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
bogdanm	0:9b334a45a8ff	81
bogdanm	0:9b334a45a8ff	82	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
bogdanm	0:9b334a45a8ff	83	This parameter must be a number between Min_Data = 4 and Max_Data = 15 */
bogdanm	0:9b334a45a8ff	84	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	85	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
bogdanm	0:9b334a45a8ff	86	This parameter is only available in STM32F446xx devices.
bogdanm	0:9b334a45a8ff	87	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
bogdanm	0:9b334a45a8ff	88	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	89	}RCC_PLLInitTypeDef;
bogdanm	0:9b334a45a8ff	90
bogdanm	0:9b334a45a8ff	91	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	92	/**
bogdanm	0:9b334a45a8ff	93	* @brief PLLI2S Clock structure definition
bogdanm	0:9b334a45a8ff	94	*/
bogdanm	0:9b334a45a8ff	95	typedef struct
bogdanm	0:9b334a45a8ff	96	{
bogdanm	0:9b334a45a8ff	97	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
bogdanm	0:9b334a45a8ff	98	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
bogdanm	0:9b334a45a8ff	99
bogdanm	0:9b334a45a8ff	100	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	0:9b334a45a8ff	101	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
bogdanm	0:9b334a45a8ff	102
bogdanm	0:9b334a45a8ff	103	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
bogdanm	0:9b334a45a8ff	104	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
bogdanm	0:9b334a45a8ff	105
bogdanm	0:9b334a45a8ff	106	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
bogdanm	0:9b334a45a8ff	107	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	108	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm	0:9b334a45a8ff	109
bogdanm	0:9b334a45a8ff	110	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	0:9b334a45a8ff	111	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	112	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
bogdanm	0:9b334a45a8ff	113	}RCC_PLLI2SInitTypeDef;
bogdanm	0:9b334a45a8ff	114
bogdanm	0:9b334a45a8ff	115	/**
bogdanm	0:9b334a45a8ff	116	* @brief PLLSAI Clock structure definition
bogdanm	0:9b334a45a8ff	117	*/
bogdanm	0:9b334a45a8ff	118	typedef struct
bogdanm	0:9b334a45a8ff	119	{
bogdanm	0:9b334a45a8ff	120	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
bogdanm	0:9b334a45a8ff	121	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
bogdanm	0:9b334a45a8ff	122
bogdanm	0:9b334a45a8ff	123	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	0:9b334a45a8ff	124	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
bogdanm	0:9b334a45a8ff	125
bogdanm	0:9b334a45a8ff	126	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
bogdanm	0:9b334a45a8ff	127	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
bogdanm	0:9b334a45a8ff	128
bogdanm	0:9b334a45a8ff	129	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
bogdanm	0:9b334a45a8ff	130	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	131	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
bogdanm	0:9b334a45a8ff	132	}RCC_PLLSAIInitTypeDef;
bogdanm	0:9b334a45a8ff	133	/**
bogdanm	0:9b334a45a8ff	134	* @brief RCC extended clocks structure definition
bogdanm	0:9b334a45a8ff	135	*/
bogdanm	0:9b334a45a8ff	136	typedef struct
bogdanm	0:9b334a45a8ff	137	{
bogdanm	0:9b334a45a8ff	138	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	139	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	140
bogdanm	0:9b334a45a8ff	141	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm	0:9b334a45a8ff	142	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	0:9b334a45a8ff	143
bogdanm	0:9b334a45a8ff	144	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
bogdanm	0:9b334a45a8ff	145	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm	0:9b334a45a8ff	148	This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm	0:9b334a45a8ff	149	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm	0:9b334a45a8ff	152	This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm	0:9b334a45a8ff	153	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
bogdanm	0:9b334a45a8ff	156	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
bogdanm	0:9b334a45a8ff	157
bogdanm	0:9b334a45a8ff	158	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
bogdanm	0:9b334a45a8ff	159	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
bogdanm	0:9b334a45a8ff	160
bogdanm	0:9b334a45a8ff	161	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
bogdanm	0:9b334a45a8ff	162	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
bogdanm	0:9b334a45a8ff	163
bogdanm	0:9b334a45a8ff	164	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
bogdanm	0:9b334a45a8ff	165	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
bogdanm	0:9b334a45a8ff	166
bogdanm	0:9b334a45a8ff	167	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
bogdanm	0:9b334a45a8ff	168	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	169
bogdanm	0:9b334a45a8ff	170	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
bogdanm	0:9b334a45a8ff	171	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
bogdanm	0:9b334a45a8ff	174	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	0:9b334a45a8ff	175
bogdanm	0:9b334a45a8ff	176	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
bogdanm	0:9b334a45a8ff	177	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	178
bogdanm	0:9b334a45a8ff	179	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
bogdanm	0:9b334a45a8ff	180	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
bogdanm	0:9b334a45a8ff	181
bogdanm	0:9b334a45a8ff	182	uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
bogdanm	0:9b334a45a8ff	183	This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
bogdanm	0:9b334a45a8ff	186	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
bogdanm	0:9b334a45a8ff	187	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	188	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	189
bogdanm	0:9b334a45a8ff	190	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	191
bogdanm	0:9b334a45a8ff	192	/**
bogdanm	0:9b334a45a8ff	193	* @brief PLLI2S Clock structure definition
bogdanm	0:9b334a45a8ff	194	*/
bogdanm	0:9b334a45a8ff	195	typedef struct
bogdanm	0:9b334a45a8ff	196	{
bogdanm	0:9b334a45a8ff	197	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	0:9b334a45a8ff	198	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	199	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	0:9b334a45a8ff	202	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	203	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	0:9b334a45a8ff	204
bogdanm	0:9b334a45a8ff	205	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	0:9b334a45a8ff	206	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	207	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm	0:9b334a45a8ff	208	}RCC_PLLI2SInitTypeDef;
bogdanm	0:9b334a45a8ff	209
bogdanm	0:9b334a45a8ff	210	/**
bogdanm	0:9b334a45a8ff	211	* @brief PLLSAI Clock structure definition
bogdanm	0:9b334a45a8ff	212	*/
bogdanm	0:9b334a45a8ff	213	typedef struct
bogdanm	0:9b334a45a8ff	214	{
bogdanm	0:9b334a45a8ff	215	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	0:9b334a45a8ff	216	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	217	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	0:9b334a45a8ff	220	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	221	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
bogdanm	0:9b334a45a8ff	224	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	225	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227	}RCC_PLLSAIInitTypeDef;
bogdanm	0:9b334a45a8ff	228	/**
bogdanm	0:9b334a45a8ff	229	* @brief RCC extended clocks structure definition
bogdanm	0:9b334a45a8ff	230	*/
bogdanm	0:9b334a45a8ff	231	typedef struct
bogdanm	0:9b334a45a8ff	232	{
bogdanm	0:9b334a45a8ff	233	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	234	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	235
bogdanm	0:9b334a45a8ff	236	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm	0:9b334a45a8ff	237	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	0:9b334a45a8ff	238
bogdanm	0:9b334a45a8ff	239	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
bogdanm	0:9b334a45a8ff	240	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm	0:9b334a45a8ff	243	This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm	0:9b334a45a8ff	244	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm	0:9b334a45a8ff	247	This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm	0:9b334a45a8ff	248	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
bogdanm	0:9b334a45a8ff	251	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
bogdanm	0:9b334a45a8ff	252
bogdanm	0:9b334a45a8ff	253	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
bogdanm	0:9b334a45a8ff	254	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
bogdanm	0:9b334a45a8ff	257	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
bogdanm	0:9b334a45a8ff	258
bogdanm	0:9b334a45a8ff	259	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	260	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	261
bogdanm	0:9b334a45a8ff	262	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
bogdanm	0:9b334a45a8ff	263	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	264	/**
bogdanm	0:9b334a45a8ff	265	* @brief PLLI2S Clock structure definition
bogdanm	0:9b334a45a8ff	266	*/
bogdanm	0:9b334a45a8ff	267	typedef struct
bogdanm	0:9b334a45a8ff	268	{
bogdanm	0:9b334a45a8ff	269	#if defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	270	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
bogdanm	0:9b334a45a8ff	271	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
bogdanm	0:9b334a45a8ff	272	#endif /* STM32F411xE */
bogdanm	0:9b334a45a8ff	273
bogdanm	0:9b334a45a8ff	274	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	0:9b334a45a8ff	275	This parameter must be a number between Min_Data = 192 and Max_Data = 432
bogdanm	0:9b334a45a8ff	276	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	0:9b334a45a8ff	279	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	280	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282	}RCC_PLLI2SInitTypeDef;
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	/**
bogdanm	0:9b334a45a8ff	286	* @brief RCC extended clocks structure definition
bogdanm	0:9b334a45a8ff	287	*/
bogdanm	0:9b334a45a8ff	288	typedef struct
bogdanm	0:9b334a45a8ff	289	{
bogdanm	0:9b334a45a8ff	290	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	291	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	292
bogdanm	0:9b334a45a8ff	293	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm	0:9b334a45a8ff	294	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	0:9b334a45a8ff	295
bogdanm	0:9b334a45a8ff	296	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
bogdanm	0:9b334a45a8ff	297	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	298
bogdanm	0:9b334a45a8ff	299	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	300	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
bogdanm	0:9b334a45a8ff	301	/**
bogdanm	0:9b334a45a8ff	302	* @}
bogdanm	0:9b334a45a8ff	303	*/
bogdanm	0:9b334a45a8ff	304
bogdanm	0:9b334a45a8ff	305	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	306	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
bogdanm	0:9b334a45a8ff	307	* @{
bogdanm	0:9b334a45a8ff	308	*/
bogdanm	0:9b334a45a8ff	309
bogdanm	0:9b334a45a8ff	310	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
bogdanm	0:9b334a45a8ff	311	* @{
bogdanm	0:9b334a45a8ff	312	*/
bogdanm	0:9b334a45a8ff	313	/------------------------------- Peripheral Clock source for STM32F446xx -----------------------------/
bogdanm	0:9b334a45a8ff	314	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	315	#define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	316	#define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	317	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	318	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	319	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	320	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	321	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	322	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	323	#define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	324	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	325	#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	326	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	327	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	328	/-----------------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/--------------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------------/
bogdanm	0:9b334a45a8ff	331	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	332	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	333	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	334	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	335	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	336	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	337	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	338	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	339	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	340	/-----------------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	/------------------------ Peripheral Clock source for STM32F40xxx/STM32F41xxx ------------------------/
bogdanm	0:9b334a45a8ff	343	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
bogdanm	0:9b334a45a8ff	344	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	345	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	346	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	347	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	348	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
bogdanm	0:9b334a45a8ff	349	/-----------------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	350	/**
bogdanm	0:9b334a45a8ff	351	* @}
bogdanm	0:9b334a45a8ff	352	*/
bogdanm	0:9b334a45a8ff	353
bogdanm	0:9b334a45a8ff	354	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
bogdanm	0:9b334a45a8ff	355	* @{
bogdanm	0:9b334a45a8ff	356	*/
bogdanm	0:9b334a45a8ff	357	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	358	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	359	#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	360	#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	361	#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
bogdanm	0:9b334a45a8ff	362	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
bogdanm	0:9b334a45a8ff	363	/**
bogdanm	0:9b334a45a8ff	364	* @}
bogdanm	0:9b334a45a8ff	365	*/
bogdanm	0:9b334a45a8ff	366
bogdanm	0:9b334a45a8ff	367	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
bogdanm	0:9b334a45a8ff	368	* @{
bogdanm	0:9b334a45a8ff	369	*/
bogdanm	0:9b334a45a8ff	370	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	371	#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	372	#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	373	#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006)
bogdanm	0:9b334a45a8ff	374	#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	375	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	376	/**
bogdanm	0:9b334a45a8ff	377	* @}
bogdanm	0:9b334a45a8ff	378	*/
bogdanm	0:9b334a45a8ff	379
bogdanm	0:9b334a45a8ff	380	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
bogdanm	0:9b334a45a8ff	381	* @{
bogdanm	0:9b334a45a8ff	382	*/
bogdanm	0:9b334a45a8ff	383	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	384	#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	385	#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	386	#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006)
bogdanm	0:9b334a45a8ff	387	#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	388	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	389	/**
bogdanm	0:9b334a45a8ff	390	* @}
bogdanm	0:9b334a45a8ff	391	*/
bogdanm	0:9b334a45a8ff	392
bogdanm	0:9b334a45a8ff	393	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	394	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
bogdanm	0:9b334a45a8ff	395	* @{
bogdanm	0:9b334a45a8ff	396	*/
bogdanm	0:9b334a45a8ff	397	#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	398	#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	399	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	400	/**
bogdanm	0:9b334a45a8ff	401	* @}
bogdanm	0:9b334a45a8ff	402	*/
bogdanm	0:9b334a45a8ff	403
bogdanm	0:9b334a45a8ff	404	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
bogdanm	0:9b334a45a8ff	405	* @{
bogdanm	0:9b334a45a8ff	406	*/
bogdanm	0:9b334a45a8ff	407	#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	408	#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	409	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	410	/**
bogdanm	0:9b334a45a8ff	411	* @}
bogdanm	0:9b334a45a8ff	412	*/
bogdanm	0:9b334a45a8ff	413	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	416	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
bogdanm	0:9b334a45a8ff	417	* @{
bogdanm	0:9b334a45a8ff	418	*/
bogdanm	0:9b334a45a8ff	419	#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	420	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
bogdanm	0:9b334a45a8ff	421	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
bogdanm	0:9b334a45a8ff	422	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
bogdanm	0:9b334a45a8ff	423	/**
bogdanm	0:9b334a45a8ff	424	* @}
bogdanm	0:9b334a45a8ff	425	*/
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
bogdanm	0:9b334a45a8ff	428	* @{
bogdanm	0:9b334a45a8ff	429	*/
bogdanm	0:9b334a45a8ff	430	#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	431	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
bogdanm	0:9b334a45a8ff	432	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
bogdanm	0:9b334a45a8ff	433	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
bogdanm	0:9b334a45a8ff	434	/**
bogdanm	0:9b334a45a8ff	435	* @}
bogdanm	0:9b334a45a8ff	436	*/
bogdanm	0:9b334a45a8ff	437
bogdanm	0:9b334a45a8ff	438	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
bogdanm	0:9b334a45a8ff	439	* @{
bogdanm	0:9b334a45a8ff	440	*/
bogdanm	0:9b334a45a8ff	441	#define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	442	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
bogdanm	0:9b334a45a8ff	443	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
bogdanm	0:9b334a45a8ff	444	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
bogdanm	0:9b334a45a8ff	445	/**
bogdanm	0:9b334a45a8ff	446	* @}
bogdanm	0:9b334a45a8ff	447	*/
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
bogdanm	0:9b334a45a8ff	450	* @{
bogdanm	0:9b334a45a8ff	451	*/
bogdanm	0:9b334a45a8ff	452	#define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	453	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
bogdanm	0:9b334a45a8ff	454	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
bogdanm	0:9b334a45a8ff	455	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
bogdanm	0:9b334a45a8ff	456	/**
bogdanm	0:9b334a45a8ff	457	* @}
bogdanm	0:9b334a45a8ff	458	*/
bogdanm	0:9b334a45a8ff	459
bogdanm	0:9b334a45a8ff	460	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
bogdanm	0:9b334a45a8ff	461	* @{
bogdanm	0:9b334a45a8ff	462	*/
bogdanm	0:9b334a45a8ff	463	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	464	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
bogdanm	0:9b334a45a8ff	465	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
bogdanm	0:9b334a45a8ff	466	/**
bogdanm	0:9b334a45a8ff	467	* @}
bogdanm	0:9b334a45a8ff	468	*/
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
bogdanm	0:9b334a45a8ff	471	* @{
bogdanm	0:9b334a45a8ff	472	*/
bogdanm	0:9b334a45a8ff	473	#define RCC_CECCLKSOURCE_HSI ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	474	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
bogdanm	0:9b334a45a8ff	475	/**
bogdanm	0:9b334a45a8ff	476	* @}
bogdanm	0:9b334a45a8ff	477	*/
bogdanm	0:9b334a45a8ff	478
bogdanm	0:9b334a45a8ff	479	/** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source
bogdanm	0:9b334a45a8ff	480	* @{
bogdanm	0:9b334a45a8ff	481	*/
bogdanm	0:9b334a45a8ff	482	#define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	483	#define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
bogdanm	0:9b334a45a8ff	484	/**
bogdanm	0:9b334a45a8ff	485	* @}
bogdanm	0:9b334a45a8ff	486	*/
bogdanm	0:9b334a45a8ff	487
bogdanm	0:9b334a45a8ff	488	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
bogdanm	0:9b334a45a8ff	489	* @{
bogdanm	0:9b334a45a8ff	490	*/
bogdanm	0:9b334a45a8ff	491	#define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	492	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
bogdanm	0:9b334a45a8ff	493	/**
bogdanm	0:9b334a45a8ff	494	* @}
bogdanm	0:9b334a45a8ff	495	*/
bogdanm	0:9b334a45a8ff	496
bogdanm	0:9b334a45a8ff	497	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
bogdanm	0:9b334a45a8ff	498	* @{
bogdanm	0:9b334a45a8ff	499	*/
bogdanm	0:9b334a45a8ff	500	#define RCC_SPDIFRXCLKSOURCE_PLLR ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	501	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
bogdanm	0:9b334a45a8ff	502	/**
bogdanm	0:9b334a45a8ff	503	* @}
bogdanm	0:9b334a45a8ff	504	*/
bogdanm	0:9b334a45a8ff	505
bogdanm	0:9b334a45a8ff	506	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	507
bogdanm	0:9b334a45a8ff	508	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
bogdanm	0:9b334a45a8ff	509	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	510	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
bogdanm	0:9b334a45a8ff	511	* @{
bogdanm	0:9b334a45a8ff	512	*/
bogdanm	0:9b334a45a8ff	513	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	514	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	515	/**
bogdanm	0:9b334a45a8ff	516	* @}
bogdanm	0:9b334a45a8ff	517	*/
bogdanm	0:9b334a45a8ff	518	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx */
bogdanm	0:9b334a45a8ff	519
bogdanm	0:9b334a45a8ff	520	#if defined(STM32F411xE) \|\| defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	521	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
bogdanm	0:9b334a45a8ff	522	* @{
bogdanm	0:9b334a45a8ff	523	*/
bogdanm	0:9b334a45a8ff	524	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	525	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	526	/**
bogdanm	0:9b334a45a8ff	527	* @}
bogdanm	0:9b334a45a8ff	528	*/
bogdanm	0:9b334a45a8ff	529	#endif /* STM32F411xE \|\| STM32F446xx */
bogdanm	0:9b334a45a8ff	530
bogdanm	0:9b334a45a8ff	531	/**
bogdanm	0:9b334a45a8ff	532	* @}
bogdanm	0:9b334a45a8ff	533	*/
bogdanm	0:9b334a45a8ff	534
bogdanm	0:9b334a45a8ff	535	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	536	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
bogdanm	0:9b334a45a8ff	537	* @{
bogdanm	0:9b334a45a8ff	538	*/
bogdanm	0:9b334a45a8ff	539	/------------------------------- STM32F42xxx/STM32F43xxx ----------------------------------/
bogdanm	0:9b334a45a8ff	540	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	541	/** @brief Enables or disables the AHB1 peripheral clock.
bogdanm	0:9b334a45a8ff	542	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	543	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	544	* using it.
bogdanm	0:9b334a45a8ff	545	*/
bogdanm	0:9b334a45a8ff	546	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	547	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	548	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
bogdanm	0:9b334a45a8ff	549	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	550	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
bogdanm	0:9b334a45a8ff	551	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	552	} while(0)
bogdanm	0:9b334a45a8ff	553	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	554	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	555	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
bogdanm	0:9b334a45a8ff	556	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	557	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
bogdanm	0:9b334a45a8ff	558	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	559	} while(0)
bogdanm	0:9b334a45a8ff	560	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	561	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	562	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
bogdanm	0:9b334a45a8ff	563	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	564	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
bogdanm	0:9b334a45a8ff	565	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	566	} while(0)
bogdanm	0:9b334a45a8ff	567	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	568	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	569	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
bogdanm	0:9b334a45a8ff	570	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	571	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
bogdanm	0:9b334a45a8ff	572	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	573	} while(0)
bogdanm	0:9b334a45a8ff	574	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	575	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	576	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
bogdanm	0:9b334a45a8ff	577	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	578	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
bogdanm	0:9b334a45a8ff	579	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	580	} while(0)
bogdanm	0:9b334a45a8ff	581	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	582	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	583	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
bogdanm	0:9b334a45a8ff	584	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	585	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
bogdanm	0:9b334a45a8ff	586	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	587	} while(0)
bogdanm	0:9b334a45a8ff	588	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	589	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	590	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
bogdanm	0:9b334a45a8ff	591	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	592	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
bogdanm	0:9b334a45a8ff	593	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	594	} while(0)
bogdanm	0:9b334a45a8ff	595	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	596	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	597	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
bogdanm	0:9b334a45a8ff	598	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	599	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
bogdanm	0:9b334a45a8ff	600	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	601	} while(0)
bogdanm	0:9b334a45a8ff	602	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	603	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	604	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
bogdanm	0:9b334a45a8ff	605	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	606	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
bogdanm	0:9b334a45a8ff	607	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	608	} while(0)
bogdanm	0:9b334a45a8ff	609	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	610	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	611	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
bogdanm	0:9b334a45a8ff	612	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	613	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
bogdanm	0:9b334a45a8ff	614	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	615	} while(0)
bogdanm	0:9b334a45a8ff	616	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	617	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	618	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
bogdanm	0:9b334a45a8ff	619	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	620	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
bogdanm	0:9b334a45a8ff	621	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	622	} while(0)
bogdanm	0:9b334a45a8ff	623	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	624	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	625	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
bogdanm	0:9b334a45a8ff	626	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	627	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
bogdanm	0:9b334a45a8ff	628	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	629	} while(0)
bogdanm	0:9b334a45a8ff	630
bogdanm	0:9b334a45a8ff	631	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
bogdanm	0:9b334a45a8ff	632	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
bogdanm	0:9b334a45a8ff	633	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
bogdanm	0:9b334a45a8ff	634	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
bogdanm	0:9b334a45a8ff	635	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
bogdanm	0:9b334a45a8ff	636	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
bogdanm	0:9b334a45a8ff	637	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
bogdanm	0:9b334a45a8ff	638	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
bogdanm	0:9b334a45a8ff	639	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
bogdanm	0:9b334a45a8ff	640	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
bogdanm	0:9b334a45a8ff	641	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
bogdanm	0:9b334a45a8ff	642	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	/**
bogdanm	0:9b334a45a8ff	645	* @brief Enable ETHERNET clock.
bogdanm	0:9b334a45a8ff	646	*/
bogdanm	0:9b334a45a8ff	647	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	648	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
bogdanm	0:9b334a45a8ff	649	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
bogdanm	0:9b334a45a8ff	650	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
bogdanm	0:9b334a45a8ff	651	} while(0)
bogdanm	0:9b334a45a8ff	652	/**
bogdanm	0:9b334a45a8ff	653	* @brief Disable ETHERNET clock.
bogdanm	0:9b334a45a8ff	654	*/
bogdanm	0:9b334a45a8ff	655	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
bogdanm	0:9b334a45a8ff	656	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
bogdanm	0:9b334a45a8ff	657	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
bogdanm	0:9b334a45a8ff	658	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
bogdanm	0:9b334a45a8ff	659	} while(0)
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	/** @brief Enable or disable the AHB2 peripheral clock.
bogdanm	0:9b334a45a8ff	662	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	663	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	664	* using it.
bogdanm	0:9b334a45a8ff	665	*/
bogdanm	0:9b334a45a8ff	666
bogdanm	0:9b334a45a8ff	667	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	668	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	669	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
bogdanm	0:9b334a45a8ff	670	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	671	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
bogdanm	0:9b334a45a8ff	672	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	673	} while(0)
bogdanm	0:9b334a45a8ff	674	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm	0:9b334a45a8ff	675
bogdanm	0:9b334a45a8ff	676	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	677	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	678	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	679	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
bogdanm	0:9b334a45a8ff	680	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	681	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
bogdanm	0:9b334a45a8ff	682	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	683	} while(0)
bogdanm	0:9b334a45a8ff	684	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	685	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	686	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
bogdanm	0:9b334a45a8ff	687	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	688	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
bogdanm	0:9b334a45a8ff	689	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	690	} while(0)
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
bogdanm	0:9b334a45a8ff	693	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
bogdanm	0:9b334a45a8ff	694	#endif /* STM32F437xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	/** @brief Enables or disables the AHB3 peripheral clock.
bogdanm	0:9b334a45a8ff	697	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	698	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	699	* using it.
bogdanm	0:9b334a45a8ff	700	*/
bogdanm	0:9b334a45a8ff	701	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	702	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	703	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
bogdanm	0:9b334a45a8ff	704	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	705	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
bogdanm	0:9b334a45a8ff	706	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	707	} while(0)
bogdanm	0:9b334a45a8ff	708	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
bogdanm	0:9b334a45a8ff	709
bogdanm	0:9b334a45a8ff	710	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	0:9b334a45a8ff	711	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	712	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	713	* using it.
bogdanm	0:9b334a45a8ff	714	*/
bogdanm	0:9b334a45a8ff	715	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	716	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	717	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
bogdanm	0:9b334a45a8ff	718	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	719	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
bogdanm	0:9b334a45a8ff	720	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	721	} while(0)
bogdanm	0:9b334a45a8ff	722	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	723	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	724	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
bogdanm	0:9b334a45a8ff	725	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	726	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
bogdanm	0:9b334a45a8ff	727	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	728	} while(0)
bogdanm	0:9b334a45a8ff	729	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	730	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	731	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
bogdanm	0:9b334a45a8ff	732	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	733	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
bogdanm	0:9b334a45a8ff	734	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	735	} while(0)
bogdanm	0:9b334a45a8ff	736	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	737	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	738	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
bogdanm	0:9b334a45a8ff	739	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	740	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
bogdanm	0:9b334a45a8ff	741	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	742	} while(0)
bogdanm	0:9b334a45a8ff	743	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	744	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	745	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
bogdanm	0:9b334a45a8ff	746	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	747	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
bogdanm	0:9b334a45a8ff	748	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	749	} while(0)
bogdanm	0:9b334a45a8ff	750	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	751	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	752	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
bogdanm	0:9b334a45a8ff	753	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	754	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
bogdanm	0:9b334a45a8ff	755	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	756	} while(0)
bogdanm	0:9b334a45a8ff	757	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	758	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	759	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
bogdanm	0:9b334a45a8ff	760	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	761	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
bogdanm	0:9b334a45a8ff	762	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	763	} while(0)
bogdanm	0:9b334a45a8ff	764	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	765	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	766	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
bogdanm	0:9b334a45a8ff	767	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	768	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
bogdanm	0:9b334a45a8ff	769	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	770	} while(0)
bogdanm	0:9b334a45a8ff	771	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	772	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	773	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
bogdanm	0:9b334a45a8ff	774	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	775	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
bogdanm	0:9b334a45a8ff	776	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	777	} while(0)
bogdanm	0:9b334a45a8ff	778	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	779	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	780	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
bogdanm	0:9b334a45a8ff	781	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	782	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
bogdanm	0:9b334a45a8ff	783	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	784	} while(0)
bogdanm	0:9b334a45a8ff	785	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	786	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	787	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
bogdanm	0:9b334a45a8ff	788	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	789	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
bogdanm	0:9b334a45a8ff	790	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	791	} while(0)
bogdanm	0:9b334a45a8ff	792	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	793	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	794	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
bogdanm	0:9b334a45a8ff	795	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	796	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
bogdanm	0:9b334a45a8ff	797	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	798	} while(0)
bogdanm	0:9b334a45a8ff	799	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	800	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	801	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
bogdanm	0:9b334a45a8ff	802	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	803	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
bogdanm	0:9b334a45a8ff	804	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	805	} while(0)
bogdanm	0:9b334a45a8ff	806	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	807	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	808	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
bogdanm	0:9b334a45a8ff	809	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	810	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
bogdanm	0:9b334a45a8ff	811	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	812	} while(0)
bogdanm	0:9b334a45a8ff	813
bogdanm	0:9b334a45a8ff	814	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm	0:9b334a45a8ff	815	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm	0:9b334a45a8ff	816	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
bogdanm	0:9b334a45a8ff	817	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
bogdanm	0:9b334a45a8ff	818	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm	0:9b334a45a8ff	819	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm	0:9b334a45a8ff	820	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
bogdanm	0:9b334a45a8ff	821	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
bogdanm	0:9b334a45a8ff	822	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
bogdanm	0:9b334a45a8ff	823	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
bogdanm	0:9b334a45a8ff	824	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm	0:9b334a45a8ff	825	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
bogdanm	0:9b334a45a8ff	826	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	0:9b334a45a8ff	829	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	830	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	831	* using it.
bogdanm	0:9b334a45a8ff	832	*/
bogdanm	0:9b334a45a8ff	833	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	834	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	835	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
bogdanm	0:9b334a45a8ff	836	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	837	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
bogdanm	0:9b334a45a8ff	838	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	839	} while(0)
bogdanm	0:9b334a45a8ff	840	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	841	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	842	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
bogdanm	0:9b334a45a8ff	843	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	844	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
bogdanm	0:9b334a45a8ff	845	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	846	} while(0)
bogdanm	0:9b334a45a8ff	847	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	848	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	849	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
bogdanm	0:9b334a45a8ff	850	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	851	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
bogdanm	0:9b334a45a8ff	852	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	853	} while(0)
bogdanm	0:9b334a45a8ff	854	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	855	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	856	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
bogdanm	0:9b334a45a8ff	857	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	858	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
bogdanm	0:9b334a45a8ff	859	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	860	} while(0)
bogdanm	0:9b334a45a8ff	861	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	862	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	863	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
bogdanm	0:9b334a45a8ff	864	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	865	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
bogdanm	0:9b334a45a8ff	866	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	867	} while(0)
bogdanm	0:9b334a45a8ff	868	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	869	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	870	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
bogdanm	0:9b334a45a8ff	871	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	872	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
bogdanm	0:9b334a45a8ff	873	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	874	} while(0)
bogdanm	0:9b334a45a8ff	875
bogdanm	0:9b334a45a8ff	876	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
bogdanm	0:9b334a45a8ff	877	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
bogdanm	0:9b334a45a8ff	878	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
bogdanm	0:9b334a45a8ff	879	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
bogdanm	0:9b334a45a8ff	880	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
bogdanm	0:9b334a45a8ff	881	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
bogdanm	0:9b334a45a8ff	882
bogdanm	0:9b334a45a8ff	883	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	884	#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_LTDCEN))
bogdanm	0:9b334a45a8ff	885
bogdanm	0:9b334a45a8ff	886	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
bogdanm	0:9b334a45a8ff	887	#endif /* STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	888
bogdanm	0:9b334a45a8ff	889	/** @brief Force or release AHB1 peripheral reset.
bogdanm	0:9b334a45a8ff	890	*/
bogdanm	0:9b334a45a8ff	891	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
bogdanm	0:9b334a45a8ff	892	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
bogdanm	0:9b334a45a8ff	893	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
bogdanm	0:9b334a45a8ff	894	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
bogdanm	0:9b334a45a8ff	895	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
bogdanm	0:9b334a45a8ff	896	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
bogdanm	0:9b334a45a8ff	897	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
bogdanm	0:9b334a45a8ff	898	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
bogdanm	0:9b334a45a8ff	899
bogdanm	0:9b334a45a8ff	900	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm	0:9b334a45a8ff	901	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm	0:9b334a45a8ff	902	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
bogdanm	0:9b334a45a8ff	903	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
bogdanm	0:9b334a45a8ff	904	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
bogdanm	0:9b334a45a8ff	905	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
bogdanm	0:9b334a45a8ff	906	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
bogdanm	0:9b334a45a8ff	907	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
bogdanm	0:9b334a45a8ff	908
bogdanm	0:9b334a45a8ff	909	/** @brief Force or release AHB2 peripheral reset.
bogdanm	0:9b334a45a8ff	910	*/
bogdanm	0:9b334a45a8ff	911	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
bogdanm	0:9b334a45a8ff	912	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm	0:9b334a45a8ff	913
bogdanm	0:9b334a45a8ff	914	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	915	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
bogdanm	0:9b334a45a8ff	916	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
bogdanm	0:9b334a45a8ff	919	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
bogdanm	0:9b334a45a8ff	920	#endif /* STM32F437xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	921
bogdanm	0:9b334a45a8ff	922	/** @brief Force or release AHB3 peripheral reset
bogdanm	0:9b334a45a8ff	923	*/
bogdanm	0:9b334a45a8ff	924	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
bogdanm	0:9b334a45a8ff	925	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
bogdanm	0:9b334a45a8ff	926
bogdanm	0:9b334a45a8ff	927	/** @brief Force or release APB1 peripheral reset.
bogdanm	0:9b334a45a8ff	928	*/
bogdanm	0:9b334a45a8ff	929	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	930	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
bogdanm	0:9b334a45a8ff	931	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
bogdanm	0:9b334a45a8ff	932	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
bogdanm	0:9b334a45a8ff	933	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
bogdanm	0:9b334a45a8ff	934	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
bogdanm	0:9b334a45a8ff	935	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
bogdanm	0:9b334a45a8ff	936	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
bogdanm	0:9b334a45a8ff	937	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
bogdanm	0:9b334a45a8ff	938	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
bogdanm	0:9b334a45a8ff	939	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	940	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
bogdanm	0:9b334a45a8ff	941	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
bogdanm	0:9b334a45a8ff	942
bogdanm	0:9b334a45a8ff	943	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	944	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm	0:9b334a45a8ff	945	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
bogdanm	0:9b334a45a8ff	946	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
bogdanm	0:9b334a45a8ff	947	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm	0:9b334a45a8ff	948	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm	0:9b334a45a8ff	949	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
bogdanm	0:9b334a45a8ff	950	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
bogdanm	0:9b334a45a8ff	951	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
bogdanm	0:9b334a45a8ff	952	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
bogdanm	0:9b334a45a8ff	953	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	954	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
bogdanm	0:9b334a45a8ff	955	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
bogdanm	0:9b334a45a8ff	956
bogdanm	0:9b334a45a8ff	957	/** @brief Force or release APB2 peripheral reset.
bogdanm	0:9b334a45a8ff	958	*/
bogdanm	0:9b334a45a8ff	959	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
bogdanm	0:9b334a45a8ff	960	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
bogdanm	0:9b334a45a8ff	961	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
bogdanm	0:9b334a45a8ff	962	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
bogdanm	0:9b334a45a8ff	963
bogdanm	0:9b334a45a8ff	964	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
bogdanm	0:9b334a45a8ff	965	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
bogdanm	0:9b334a45a8ff	966	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
bogdanm	0:9b334a45a8ff	967	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	970	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
bogdanm	0:9b334a45a8ff	971	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
bogdanm	0:9b334a45a8ff	972	#endif /* STM32F429xx\|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	973
bogdanm	0:9b334a45a8ff	974	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	975	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	976	* power consumption.
bogdanm	0:9b334a45a8ff	977	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	978	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	979	*/
bogdanm	0:9b334a45a8ff	980	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
bogdanm	0:9b334a45a8ff	981	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
bogdanm	0:9b334a45a8ff	982	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
bogdanm	0:9b334a45a8ff	983	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
bogdanm	0:9b334a45a8ff	984	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
bogdanm	0:9b334a45a8ff	985	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm	0:9b334a45a8ff	986	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm	0:9b334a45a8ff	987	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm	0:9b334a45a8ff	988	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
bogdanm	0:9b334a45a8ff	989	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm	0:9b334a45a8ff	990	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
bogdanm	0:9b334a45a8ff	991	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
bogdanm	0:9b334a45a8ff	992	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
bogdanm	0:9b334a45a8ff	993	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
bogdanm	0:9b334a45a8ff	996	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
bogdanm	0:9b334a45a8ff	997	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
bogdanm	0:9b334a45a8ff	998	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
bogdanm	0:9b334a45a8ff	999	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
bogdanm	0:9b334a45a8ff	1000	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm	0:9b334a45a8ff	1001	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm	0:9b334a45a8ff	1002	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm	0:9b334a45a8ff	1003	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
bogdanm	0:9b334a45a8ff	1004	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm	0:9b334a45a8ff	1005	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
bogdanm	0:9b334a45a8ff	1006	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
bogdanm	0:9b334a45a8ff	1007	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
bogdanm	0:9b334a45a8ff	1008
bogdanm	0:9b334a45a8ff	1009	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1010	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1011	* power consumption.
bogdanm	0:9b334a45a8ff	1012	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1013	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1014	*/
bogdanm	0:9b334a45a8ff	1015	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
bogdanm	0:9b334a45a8ff	1016	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	1019	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
bogdanm	0:9b334a45a8ff	1020	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
bogdanm	0:9b334a45a8ff	1021
bogdanm	0:9b334a45a8ff	1022	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
bogdanm	0:9b334a45a8ff	1023	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
bogdanm	0:9b334a45a8ff	1024	#endif /* STM32F437xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1027	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1028	* power consumption.
bogdanm	0:9b334a45a8ff	1029	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1030	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1031	*/
bogdanm	0:9b334a45a8ff	1032	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
bogdanm	0:9b334a45a8ff	1033	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1036	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1037	* power consumption.
bogdanm	0:9b334a45a8ff	1038	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1039	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1040	*/
bogdanm	0:9b334a45a8ff	1041	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
bogdanm	0:9b334a45a8ff	1042	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
bogdanm	0:9b334a45a8ff	1043	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
bogdanm	0:9b334a45a8ff	1044	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
bogdanm	0:9b334a45a8ff	1045	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
bogdanm	0:9b334a45a8ff	1046	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
bogdanm	0:9b334a45a8ff	1047	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
bogdanm	0:9b334a45a8ff	1048	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
bogdanm	0:9b334a45a8ff	1049	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
bogdanm	0:9b334a45a8ff	1050	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
bogdanm	0:9b334a45a8ff	1051	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
bogdanm	0:9b334a45a8ff	1052	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
bogdanm	0:9b334a45a8ff	1053	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
bogdanm	0:9b334a45a8ff	1054
bogdanm	0:9b334a45a8ff	1055	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
bogdanm	0:9b334a45a8ff	1056	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
bogdanm	0:9b334a45a8ff	1057	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
bogdanm	0:9b334a45a8ff	1058	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
bogdanm	0:9b334a45a8ff	1059	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
bogdanm	0:9b334a45a8ff	1060	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
bogdanm	0:9b334a45a8ff	1061	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
bogdanm	0:9b334a45a8ff	1062	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
bogdanm	0:9b334a45a8ff	1063	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
bogdanm	0:9b334a45a8ff	1064	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
bogdanm	0:9b334a45a8ff	1065	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
bogdanm	0:9b334a45a8ff	1066	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
bogdanm	0:9b334a45a8ff	1067	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
bogdanm	0:9b334a45a8ff	1068
bogdanm	0:9b334a45a8ff	1069	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1070	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1071	* power consumption.
bogdanm	0:9b334a45a8ff	1072	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1073	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1074	*/
bogdanm	0:9b334a45a8ff	1075	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
bogdanm	0:9b334a45a8ff	1076	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
bogdanm	0:9b334a45a8ff	1077	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
bogdanm	0:9b334a45a8ff	1078	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
bogdanm	0:9b334a45a8ff	1079	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
bogdanm	0:9b334a45a8ff	1080	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
bogdanm	0:9b334a45a8ff	1081
bogdanm	0:9b334a45a8ff	1082	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
bogdanm	0:9b334a45a8ff	1083	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
bogdanm	0:9b334a45a8ff	1084	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
bogdanm	0:9b334a45a8ff	1085	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
bogdanm	0:9b334a45a8ff	1086	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
bogdanm	0:9b334a45a8ff	1087	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
bogdanm	0:9b334a45a8ff	1088
bogdanm	0:9b334a45a8ff	1089	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	1090	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
bogdanm	0:9b334a45a8ff	1091
bogdanm	0:9b334a45a8ff	1092	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
bogdanm	0:9b334a45a8ff	1093	#endif /* STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	1094
bogdanm	0:9b334a45a8ff	1095	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	1096	/---------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	1097
bogdanm	0:9b334a45a8ff	1098	/----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------/
bogdanm	0:9b334a45a8ff	1099	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
bogdanm	0:9b334a45a8ff	1100	/** @brief Enables or disables the AHB1 peripheral clock.
bogdanm	0:9b334a45a8ff	1101	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1102	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1103	* using it.
bogdanm	0:9b334a45a8ff	1104	*/
bogdanm	0:9b334a45a8ff	1105	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1106	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1107	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
bogdanm	0:9b334a45a8ff	1108	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1109	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
bogdanm	0:9b334a45a8ff	1110	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1111	} while(0)
bogdanm	0:9b334a45a8ff	1112	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1113	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1114	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
bogdanm	0:9b334a45a8ff	1115	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1116	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
bogdanm	0:9b334a45a8ff	1117	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1118	} while(0)
bogdanm	0:9b334a45a8ff	1119	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1120	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1121	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
bogdanm	0:9b334a45a8ff	1122	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1123	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
bogdanm	0:9b334a45a8ff	1124	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1125	} while(0)
bogdanm	0:9b334a45a8ff	1126	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1127	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1128	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
bogdanm	0:9b334a45a8ff	1129	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1130	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
bogdanm	0:9b334a45a8ff	1131	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1132	} while(0)
bogdanm	0:9b334a45a8ff	1133	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1134	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1135	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
bogdanm	0:9b334a45a8ff	1136	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1137	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
bogdanm	0:9b334a45a8ff	1138	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1139	} while(0)
bogdanm	0:9b334a45a8ff	1140
bogdanm	0:9b334a45a8ff	1141	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
bogdanm	0:9b334a45a8ff	1142	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
bogdanm	0:9b334a45a8ff	1143	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
bogdanm	0:9b334a45a8ff	1144	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
bogdanm	0:9b334a45a8ff	1145	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
bogdanm	0:9b334a45a8ff	1146
bogdanm	0:9b334a45a8ff	1147	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
bogdanm	0:9b334a45a8ff	1148	/**
bogdanm	0:9b334a45a8ff	1149	* @brief Enable ETHERNET clock.
bogdanm	0:9b334a45a8ff	1150	*/
bogdanm	0:9b334a45a8ff	1151	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1152	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1153	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
bogdanm	0:9b334a45a8ff	1154	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1155	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
bogdanm	0:9b334a45a8ff	1156	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1157	} while(0)
bogdanm	0:9b334a45a8ff	1158	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1159	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1160	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
bogdanm	0:9b334a45a8ff	1161	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1162	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
bogdanm	0:9b334a45a8ff	1163	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1164	} while(0)
bogdanm	0:9b334a45a8ff	1165	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1166	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1167	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
bogdanm	0:9b334a45a8ff	1168	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1169	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
bogdanm	0:9b334a45a8ff	1170	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1171	} while(0)
bogdanm	0:9b334a45a8ff	1172	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1173	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1174	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
bogdanm	0:9b334a45a8ff	1175	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1176	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
bogdanm	0:9b334a45a8ff	1177	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1178	} while(0)
bogdanm	0:9b334a45a8ff	1179	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1180	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
bogdanm	0:9b334a45a8ff	1181	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
bogdanm	0:9b334a45a8ff	1182	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
bogdanm	0:9b334a45a8ff	1183	} while(0)
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	/**
bogdanm	0:9b334a45a8ff	1186	* @brief Disable ETHERNET clock.
bogdanm	0:9b334a45a8ff	1187	*/
bogdanm	0:9b334a45a8ff	1188	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
bogdanm	0:9b334a45a8ff	1189	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
bogdanm	0:9b334a45a8ff	1190	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
bogdanm	0:9b334a45a8ff	1191	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
bogdanm	0:9b334a45a8ff	1192	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
bogdanm	0:9b334a45a8ff	1193	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
bogdanm	0:9b334a45a8ff	1194	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
bogdanm	0:9b334a45a8ff	1195	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
bogdanm	0:9b334a45a8ff	1196	} while(0)
bogdanm	0:9b334a45a8ff	1197	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	0:9b334a45a8ff	1198
bogdanm	0:9b334a45a8ff	1199	/** @brief Enable or disable the AHB2 peripheral clock.
bogdanm	0:9b334a45a8ff	1200	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1201	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1202	* using it.
bogdanm	0:9b334a45a8ff	1203	*/
bogdanm	0:9b334a45a8ff	1204	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
bogdanm	0:9b334a45a8ff	1205	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1206	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1207	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
bogdanm	0:9b334a45a8ff	1208	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1209	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
bogdanm	0:9b334a45a8ff	1210	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1211	} while(0)
bogdanm	0:9b334a45a8ff	1212	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm	0:9b334a45a8ff	1213	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	0:9b334a45a8ff	1214
bogdanm	0:9b334a45a8ff	1215	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
bogdanm	0:9b334a45a8ff	1216	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1217	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1218	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
bogdanm	0:9b334a45a8ff	1219	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1220	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
bogdanm	0:9b334a45a8ff	1221	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1222	} while(0)
bogdanm	0:9b334a45a8ff	1223	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1224	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1225	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
bogdanm	0:9b334a45a8ff	1226	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1227	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
bogdanm	0:9b334a45a8ff	1228	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1229	} while(0)
bogdanm	0:9b334a45a8ff	1230	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
bogdanm	0:9b334a45a8ff	1231	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
bogdanm	0:9b334a45a8ff	1232	#endif /* STM32F415xx \|\| STM32F417xx */
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	/** @brief Enables or disables the AHB3 peripheral clock.
bogdanm	0:9b334a45a8ff	1235	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1236	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1237	* using it.
bogdanm	0:9b334a45a8ff	1238	*/
bogdanm	0:9b334a45a8ff	1239	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1240	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1241	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
bogdanm	0:9b334a45a8ff	1242	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1243	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
bogdanm	0:9b334a45a8ff	1244	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1245	} while(0)
bogdanm	0:9b334a45a8ff	1246	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
bogdanm	0:9b334a45a8ff	1247
bogdanm	0:9b334a45a8ff	1248	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	0:9b334a45a8ff	1249	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1250	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1251	* using it.
bogdanm	0:9b334a45a8ff	1252	*/
bogdanm	0:9b334a45a8ff	1253	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1254	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1255	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
bogdanm	0:9b334a45a8ff	1256	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1257	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
bogdanm	0:9b334a45a8ff	1258	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1259	} while(0)
bogdanm	0:9b334a45a8ff	1260	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1261	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1262	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
bogdanm	0:9b334a45a8ff	1263	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1264	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
bogdanm	0:9b334a45a8ff	1265	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1266	} while(0)
bogdanm	0:9b334a45a8ff	1267	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1268	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1269	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
bogdanm	0:9b334a45a8ff	1270	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1271	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
bogdanm	0:9b334a45a8ff	1272	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1273	} while(0)
bogdanm	0:9b334a45a8ff	1274	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1275	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1276	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
bogdanm	0:9b334a45a8ff	1277	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1278	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
bogdanm	0:9b334a45a8ff	1279	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1280	} while(0)
bogdanm	0:9b334a45a8ff	1281	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1282	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1283	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
bogdanm	0:9b334a45a8ff	1284	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1285	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
bogdanm	0:9b334a45a8ff	1286	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1287	} while(0)
bogdanm	0:9b334a45a8ff	1288	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1289	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1290	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
bogdanm	0:9b334a45a8ff	1291	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1292	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
bogdanm	0:9b334a45a8ff	1293	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1294	} while(0)
bogdanm	0:9b334a45a8ff	1295	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1296	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1297	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
bogdanm	0:9b334a45a8ff	1298	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1299	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
bogdanm	0:9b334a45a8ff	1300	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1301	} while(0)
bogdanm	0:9b334a45a8ff	1302	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1303	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1304	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
bogdanm	0:9b334a45a8ff	1305	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1306	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
bogdanm	0:9b334a45a8ff	1307	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1308	} while(0)
bogdanm	0:9b334a45a8ff	1309	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1310	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1311	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
bogdanm	0:9b334a45a8ff	1312	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1313	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
bogdanm	0:9b334a45a8ff	1314	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1315	} while(0)
bogdanm	0:9b334a45a8ff	1316	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1317	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1318	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
bogdanm	0:9b334a45a8ff	1319	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1320	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
bogdanm	0:9b334a45a8ff	1321	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1322	} while(0)
bogdanm	0:9b334a45a8ff	1323	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1324	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1325	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
bogdanm	0:9b334a45a8ff	1326	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1327	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
bogdanm	0:9b334a45a8ff	1328	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1329	} while(0)
bogdanm	0:9b334a45a8ff	1330
bogdanm	0:9b334a45a8ff	1331	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm	0:9b334a45a8ff	1332	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm	0:9b334a45a8ff	1333	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
bogdanm	0:9b334a45a8ff	1334	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
bogdanm	0:9b334a45a8ff	1335	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm	0:9b334a45a8ff	1336	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm	0:9b334a45a8ff	1337	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
bogdanm	0:9b334a45a8ff	1338	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
bogdanm	0:9b334a45a8ff	1339	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
bogdanm	0:9b334a45a8ff	1340	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
bogdanm	0:9b334a45a8ff	1341	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm	0:9b334a45a8ff	1342
bogdanm	0:9b334a45a8ff	1343	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	0:9b334a45a8ff	1344	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1345	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1346	* using it.
bogdanm	0:9b334a45a8ff	1347	*/
bogdanm	0:9b334a45a8ff	1348	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1349	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1350	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
bogdanm	0:9b334a45a8ff	1351	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1352	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
bogdanm	0:9b334a45a8ff	1353	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1354	} while(0)
bogdanm	0:9b334a45a8ff	1355	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1356	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1357	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
bogdanm	0:9b334a45a8ff	1358	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1359	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
bogdanm	0:9b334a45a8ff	1360	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1361	} while(0)
bogdanm	0:9b334a45a8ff	1362	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1363	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1364	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
bogdanm	0:9b334a45a8ff	1365	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1366	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
bogdanm	0:9b334a45a8ff	1367	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1368	} while(0)
bogdanm	0:9b334a45a8ff	1369
bogdanm	0:9b334a45a8ff	1370	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
bogdanm	0:9b334a45a8ff	1371	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
bogdanm	0:9b334a45a8ff	1372	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
bogdanm	0:9b334a45a8ff	1373
bogdanm	0:9b334a45a8ff	1374	/** @brief Force or release AHB1 peripheral reset.
bogdanm	0:9b334a45a8ff	1375	*/
bogdanm	0:9b334a45a8ff	1376	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
bogdanm	0:9b334a45a8ff	1377	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
bogdanm	0:9b334a45a8ff	1378	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
bogdanm	0:9b334a45a8ff	1379	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
bogdanm	0:9b334a45a8ff	1380	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
bogdanm	0:9b334a45a8ff	1381
bogdanm	0:9b334a45a8ff	1382	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm	0:9b334a45a8ff	1383	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm	0:9b334a45a8ff	1384	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
bogdanm	0:9b334a45a8ff	1385	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
bogdanm	0:9b334a45a8ff	1386	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
bogdanm	0:9b334a45a8ff	1387
bogdanm	0:9b334a45a8ff	1388	/** @brief Force or release AHB2 peripheral reset.
bogdanm	0:9b334a45a8ff	1389	*/
bogdanm	0:9b334a45a8ff	1390	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
bogdanm	0:9b334a45a8ff	1391	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
bogdanm	0:9b334a45a8ff	1392	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm	0:9b334a45a8ff	1393	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	0:9b334a45a8ff	1394
bogdanm	0:9b334a45a8ff	1395	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
bogdanm	0:9b334a45a8ff	1396	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
bogdanm	0:9b334a45a8ff	1397	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
bogdanm	0:9b334a45a8ff	1398
bogdanm	0:9b334a45a8ff	1399	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
bogdanm	0:9b334a45a8ff	1400	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
bogdanm	0:9b334a45a8ff	1401
bogdanm	0:9b334a45a8ff	1402	#endif /* STM32F415xx \|\| STM32F417xx */
bogdanm	0:9b334a45a8ff	1403
bogdanm	0:9b334a45a8ff	1404	/** @brief Force or release AHB3 peripheral reset
bogdanm	0:9b334a45a8ff	1405	*/
bogdanm	0:9b334a45a8ff	1406	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
bogdanm	0:9b334a45a8ff	1407	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	/** @brief Force or release APB1 peripheral reset.
bogdanm	0:9b334a45a8ff	1410	*/
bogdanm	0:9b334a45a8ff	1411	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	1412	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
bogdanm	0:9b334a45a8ff	1413	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
bogdanm	0:9b334a45a8ff	1414	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
bogdanm	0:9b334a45a8ff	1415	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
bogdanm	0:9b334a45a8ff	1416	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
bogdanm	0:9b334a45a8ff	1417	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
bogdanm	0:9b334a45a8ff	1418	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
bogdanm	0:9b334a45a8ff	1419	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
bogdanm	0:9b334a45a8ff	1420	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
bogdanm	0:9b334a45a8ff	1421	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	1422
bogdanm	0:9b334a45a8ff	1423	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	1424	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm	0:9b334a45a8ff	1425	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
bogdanm	0:9b334a45a8ff	1426	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
bogdanm	0:9b334a45a8ff	1427	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm	0:9b334a45a8ff	1428	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm	0:9b334a45a8ff	1429	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
bogdanm	0:9b334a45a8ff	1430	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
bogdanm	0:9b334a45a8ff	1431	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
bogdanm	0:9b334a45a8ff	1432	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
bogdanm	0:9b334a45a8ff	1433	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	/** @brief Force or release APB2 peripheral reset.
bogdanm	0:9b334a45a8ff	1436	*/
bogdanm	0:9b334a45a8ff	1437	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
bogdanm	0:9b334a45a8ff	1438	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
bogdanm	0:9b334a45a8ff	1439
bogdanm	0:9b334a45a8ff	1440	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1441	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1442	* power consumption.
bogdanm	0:9b334a45a8ff	1443	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1444	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1445	*/
bogdanm	0:9b334a45a8ff	1446	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
bogdanm	0:9b334a45a8ff	1447	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
bogdanm	0:9b334a45a8ff	1448	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
bogdanm	0:9b334a45a8ff	1449	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
bogdanm	0:9b334a45a8ff	1450	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
bogdanm	0:9b334a45a8ff	1451	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm	0:9b334a45a8ff	1452	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm	0:9b334a45a8ff	1453	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm	0:9b334a45a8ff	1454	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
bogdanm	0:9b334a45a8ff	1455	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm	0:9b334a45a8ff	1456
bogdanm	0:9b334a45a8ff	1457	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
bogdanm	0:9b334a45a8ff	1458	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
bogdanm	0:9b334a45a8ff	1459	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
bogdanm	0:9b334a45a8ff	1460	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
bogdanm	0:9b334a45a8ff	1461	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
bogdanm	0:9b334a45a8ff	1462	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm	0:9b334a45a8ff	1463	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm	0:9b334a45a8ff	1464	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm	0:9b334a45a8ff	1465	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
bogdanm	0:9b334a45a8ff	1466	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm	0:9b334a45a8ff	1467
bogdanm	0:9b334a45a8ff	1468	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1469	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1470	* power consumption.
bogdanm	0:9b334a45a8ff	1471	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1472	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1473	*/
bogdanm	0:9b334a45a8ff	1474	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
bogdanm	0:9b334a45a8ff	1475	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
bogdanm	0:9b334a45a8ff	1476	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
bogdanm	0:9b334a45a8ff	1477	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	0:9b334a45a8ff	1478
bogdanm	0:9b334a45a8ff	1479	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
bogdanm	0:9b334a45a8ff	1480	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
bogdanm	0:9b334a45a8ff	1481	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
bogdanm	0:9b334a45a8ff	1482
bogdanm	0:9b334a45a8ff	1483	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
bogdanm	0:9b334a45a8ff	1484	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
bogdanm	0:9b334a45a8ff	1485	#endif /* STM32F415xx \|\| STM32F417xx */
bogdanm	0:9b334a45a8ff	1486
bogdanm	0:9b334a45a8ff	1487	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1488	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1489	* power consumption.
bogdanm	0:9b334a45a8ff	1490	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1491	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1492	*/
bogdanm	0:9b334a45a8ff	1493	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
bogdanm	0:9b334a45a8ff	1494	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
bogdanm	0:9b334a45a8ff	1495
bogdanm	0:9b334a45a8ff	1496	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1497	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1498	* power consumption.
bogdanm	0:9b334a45a8ff	1499	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1500	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1501	*/
bogdanm	0:9b334a45a8ff	1502	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
bogdanm	0:9b334a45a8ff	1503	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
bogdanm	0:9b334a45a8ff	1504	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
bogdanm	0:9b334a45a8ff	1505	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
bogdanm	0:9b334a45a8ff	1506	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
bogdanm	0:9b334a45a8ff	1507	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
bogdanm	0:9b334a45a8ff	1508	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
bogdanm	0:9b334a45a8ff	1509	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
bogdanm	0:9b334a45a8ff	1510	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
bogdanm	0:9b334a45a8ff	1511	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
bogdanm	0:9b334a45a8ff	1512	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
bogdanm	0:9b334a45a8ff	1513
bogdanm	0:9b334a45a8ff	1514	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
bogdanm	0:9b334a45a8ff	1515	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
bogdanm	0:9b334a45a8ff	1516	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
bogdanm	0:9b334a45a8ff	1517	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
bogdanm	0:9b334a45a8ff	1518	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
bogdanm	0:9b334a45a8ff	1519	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
bogdanm	0:9b334a45a8ff	1520	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
bogdanm	0:9b334a45a8ff	1521	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
bogdanm	0:9b334a45a8ff	1522	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
bogdanm	0:9b334a45a8ff	1523	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
bogdanm	0:9b334a45a8ff	1524	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
bogdanm	0:9b334a45a8ff	1525
bogdanm	0:9b334a45a8ff	1526	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1527	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1528	* power consumption.
bogdanm	0:9b334a45a8ff	1529	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1530	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1531	*/
bogdanm	0:9b334a45a8ff	1532	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
bogdanm	0:9b334a45a8ff	1533	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
bogdanm	0:9b334a45a8ff	1534	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
bogdanm	0:9b334a45a8ff	1535
bogdanm	0:9b334a45a8ff	1536	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
bogdanm	0:9b334a45a8ff	1537	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
bogdanm	0:9b334a45a8ff	1538	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
bogdanm	0:9b334a45a8ff	1539	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
bogdanm	0:9b334a45a8ff	1540	/---------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	1541
bogdanm	0:9b334a45a8ff	1542	/------------------------------------------ STM32F411xx --------------------------------------/
bogdanm	0:9b334a45a8ff	1543	#if defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	1544	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	0:9b334a45a8ff	1545	*/
bogdanm	0:9b334a45a8ff	1546	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1547	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1548	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
bogdanm	0:9b334a45a8ff	1549	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1550	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
bogdanm	0:9b334a45a8ff	1551	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1552	} while(0)
bogdanm	0:9b334a45a8ff	1553	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
bogdanm	0:9b334a45a8ff	1554
bogdanm	0:9b334a45a8ff	1555	/** @brief Force or release APB2 peripheral reset.
bogdanm	0:9b334a45a8ff	1556	*/
bogdanm	0:9b334a45a8ff	1557	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
bogdanm	0:9b334a45a8ff	1558	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
bogdanm	0:9b334a45a8ff	1559
bogdanm	0:9b334a45a8ff	1560	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1561	*/
bogdanm	0:9b334a45a8ff	1562	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
bogdanm	0:9b334a45a8ff	1563	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
bogdanm	0:9b334a45a8ff	1564
bogdanm	0:9b334a45a8ff	1565	#endif /* STM32F411xE */
bogdanm	0:9b334a45a8ff	1566	/---------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	1567
bogdanm	0:9b334a45a8ff	1568	/----------------------------------------- STM32F446xx ---------------------------------------/
bogdanm	0:9b334a45a8ff	1569	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	1570	/** @brief Enables or disables the AHB1 peripheral clock.
bogdanm	0:9b334a45a8ff	1571	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1572	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1573	* using it.
bogdanm	0:9b334a45a8ff	1574	*/
bogdanm	0:9b334a45a8ff	1575	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1576	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1577	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
bogdanm	0:9b334a45a8ff	1578	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1579	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
bogdanm	0:9b334a45a8ff	1580	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1581	} while(0)
bogdanm	0:9b334a45a8ff	1582	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1583	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1584	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
bogdanm	0:9b334a45a8ff	1585	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1586	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
bogdanm	0:9b334a45a8ff	1587	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1588	} while(0)
bogdanm	0:9b334a45a8ff	1589	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1590	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1591	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
bogdanm	0:9b334a45a8ff	1592	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1593	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
bogdanm	0:9b334a45a8ff	1594	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1595	} while(0)
bogdanm	0:9b334a45a8ff	1596	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1597	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1598	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
bogdanm	0:9b334a45a8ff	1599	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1600	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
bogdanm	0:9b334a45a8ff	1601	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1602	} while(0)
bogdanm	0:9b334a45a8ff	1603
bogdanm	0:9b334a45a8ff	1604	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
bogdanm	0:9b334a45a8ff	1605	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
bogdanm	0:9b334a45a8ff	1606	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
bogdanm	0:9b334a45a8ff	1607	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	/** @brief Enable or disable the AHB2 peripheral clock.
bogdanm	0:9b334a45a8ff	1610	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1611	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1612	* using it.
bogdanm	0:9b334a45a8ff	1613	*/
bogdanm	0:9b334a45a8ff	1614	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1615	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1616	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
bogdanm	0:9b334a45a8ff	1617	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1618	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
bogdanm	0:9b334a45a8ff	1619	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1620	} while(0)
bogdanm	0:9b334a45a8ff	1621	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm	0:9b334a45a8ff	1622
bogdanm	0:9b334a45a8ff	1623	/** @brief Enables or disables the AHB3 peripheral clock.
bogdanm	0:9b334a45a8ff	1624	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1625	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1626	* using it.
bogdanm	0:9b334a45a8ff	1627	*/
bogdanm	0:9b334a45a8ff	1628	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1629	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1630	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
bogdanm	0:9b334a45a8ff	1631	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1632	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
bogdanm	0:9b334a45a8ff	1633	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1634	} while(0)
bogdanm	0:9b334a45a8ff	1635	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1636	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1637	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
bogdanm	0:9b334a45a8ff	1638	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1639	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
bogdanm	0:9b334a45a8ff	1640	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1641	} while(0)
bogdanm	0:9b334a45a8ff	1642
bogdanm	0:9b334a45a8ff	1643	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
bogdanm	0:9b334a45a8ff	1644	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
bogdanm	0:9b334a45a8ff	1645
bogdanm	0:9b334a45a8ff	1646	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	0:9b334a45a8ff	1647	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1648	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1649	* using it.
bogdanm	0:9b334a45a8ff	1650	*/
bogdanm	0:9b334a45a8ff	1651	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1652	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1653	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
bogdanm	0:9b334a45a8ff	1654	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1655	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
bogdanm	0:9b334a45a8ff	1656	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1657	} while(0)
bogdanm	0:9b334a45a8ff	1658	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1659	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1660	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
bogdanm	0:9b334a45a8ff	1661	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1662	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
bogdanm	0:9b334a45a8ff	1663	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1664	} while(0)
bogdanm	0:9b334a45a8ff	1665	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1666	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1667	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
bogdanm	0:9b334a45a8ff	1668	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1669	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
bogdanm	0:9b334a45a8ff	1670	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1671	} while(0)
bogdanm	0:9b334a45a8ff	1672	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1673	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1674	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
bogdanm	0:9b334a45a8ff	1675	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1676	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
bogdanm	0:9b334a45a8ff	1677	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1678	} while(0)
bogdanm	0:9b334a45a8ff	1679	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1680	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1681	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
bogdanm	0:9b334a45a8ff	1682	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1683	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
bogdanm	0:9b334a45a8ff	1684	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1685	} while(0)
bogdanm	0:9b334a45a8ff	1686	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1687	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1688	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
bogdanm	0:9b334a45a8ff	1689	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1690	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
bogdanm	0:9b334a45a8ff	1691	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1692	} while(0)
bogdanm	0:9b334a45a8ff	1693	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1694	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1695	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
bogdanm	0:9b334a45a8ff	1696	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1697	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
bogdanm	0:9b334a45a8ff	1698	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1699	} while(0)
bogdanm	0:9b334a45a8ff	1700	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1701	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1702	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
bogdanm	0:9b334a45a8ff	1703	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1704	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
bogdanm	0:9b334a45a8ff	1705	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1706	} while(0)
bogdanm	0:9b334a45a8ff	1707	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1708	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1709	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
bogdanm	0:9b334a45a8ff	1710	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1711	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
bogdanm	0:9b334a45a8ff	1712	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1713	} while(0)
bogdanm	0:9b334a45a8ff	1714	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1715	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1716	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
bogdanm	0:9b334a45a8ff	1717	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1718	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
bogdanm	0:9b334a45a8ff	1719	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1720	} while(0)
bogdanm	0:9b334a45a8ff	1721	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1722	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1723	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
bogdanm	0:9b334a45a8ff	1724	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1725	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
bogdanm	0:9b334a45a8ff	1726	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1727	} while(0)
bogdanm	0:9b334a45a8ff	1728	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1729	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1730	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
bogdanm	0:9b334a45a8ff	1731	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1732	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
bogdanm	0:9b334a45a8ff	1733	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1734	} while(0)
bogdanm	0:9b334a45a8ff	1735	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1736	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1737	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
bogdanm	0:9b334a45a8ff	1738	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1739	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
bogdanm	0:9b334a45a8ff	1740	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1741	} while(0)
bogdanm	0:9b334a45a8ff	1742	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1743	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1744	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
bogdanm	0:9b334a45a8ff	1745	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1746	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
bogdanm	0:9b334a45a8ff	1747	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1748	} while(0)
bogdanm	0:9b334a45a8ff	1749
bogdanm	0:9b334a45a8ff	1750	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm	0:9b334a45a8ff	1751	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm	0:9b334a45a8ff	1752	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
bogdanm	0:9b334a45a8ff	1753	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
bogdanm	0:9b334a45a8ff	1754	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm	0:9b334a45a8ff	1755	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
bogdanm	0:9b334a45a8ff	1756	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm	0:9b334a45a8ff	1757	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
bogdanm	0:9b334a45a8ff	1758	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
bogdanm	0:9b334a45a8ff	1759	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
bogdanm	0:9b334a45a8ff	1760	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
bogdanm	0:9b334a45a8ff	1761	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
bogdanm	0:9b334a45a8ff	1762	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
bogdanm	0:9b334a45a8ff	1763	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm	0:9b334a45a8ff	1764
bogdanm	0:9b334a45a8ff	1765	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	0:9b334a45a8ff	1766	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1767	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1768	* using it.
bogdanm	0:9b334a45a8ff	1769	*/
bogdanm	0:9b334a45a8ff	1770	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1771	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1772	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
bogdanm	0:9b334a45a8ff	1773	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1774	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
bogdanm	0:9b334a45a8ff	1775	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1776	} while(0)
bogdanm	0:9b334a45a8ff	1777	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1778	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1779	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
bogdanm	0:9b334a45a8ff	1780	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1781	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
bogdanm	0:9b334a45a8ff	1782	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1783	} while(0)
bogdanm	0:9b334a45a8ff	1784	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1785	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1786	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
bogdanm	0:9b334a45a8ff	1787	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1788	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
bogdanm	0:9b334a45a8ff	1789	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1790	} while(0)
bogdanm	0:9b334a45a8ff	1791	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1792	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1793	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
bogdanm	0:9b334a45a8ff	1794	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1795	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
bogdanm	0:9b334a45a8ff	1796	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1797	} while(0)
bogdanm	0:9b334a45a8ff	1798	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1799	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1800	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
bogdanm	0:9b334a45a8ff	1801	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1802	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
bogdanm	0:9b334a45a8ff	1803	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1804	} while(0)
bogdanm	0:9b334a45a8ff	1805
bogdanm	0:9b334a45a8ff	1806	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
bogdanm	0:9b334a45a8ff	1807	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
bogdanm	0:9b334a45a8ff	1808	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
bogdanm	0:9b334a45a8ff	1809	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
bogdanm	0:9b334a45a8ff	1810	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
bogdanm	0:9b334a45a8ff	1811
bogdanm	0:9b334a45a8ff	1812	/** @brief Force or release AHB1 peripheral reset.
bogdanm	0:9b334a45a8ff	1813	*/
bogdanm	0:9b334a45a8ff	1814	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
bogdanm	0:9b334a45a8ff	1815	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
bogdanm	0:9b334a45a8ff	1816	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
bogdanm	0:9b334a45a8ff	1817
bogdanm	0:9b334a45a8ff	1818	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm	0:9b334a45a8ff	1819	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm	0:9b334a45a8ff	1820	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
bogdanm	0:9b334a45a8ff	1821
bogdanm	0:9b334a45a8ff	1822	/** @brief Force or release AHB2 peripheral reset.
bogdanm	0:9b334a45a8ff	1823	*/
bogdanm	0:9b334a45a8ff	1824	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
bogdanm	0:9b334a45a8ff	1825	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm	0:9b334a45a8ff	1826
bogdanm	0:9b334a45a8ff	1827	/** @brief Force or release AHB3 peripheral reset
bogdanm	0:9b334a45a8ff	1828	*/
bogdanm	0:9b334a45a8ff	1829	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
bogdanm	0:9b334a45a8ff	1830	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
bogdanm	0:9b334a45a8ff	1831
bogdanm	0:9b334a45a8ff	1832	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
bogdanm	0:9b334a45a8ff	1833	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
bogdanm	0:9b334a45a8ff	1834
bogdanm	0:9b334a45a8ff	1835	/** @brief Force or release APB1 peripheral reset.
bogdanm	0:9b334a45a8ff	1836	*/
bogdanm	0:9b334a45a8ff	1837	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	1838	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
bogdanm	0:9b334a45a8ff	1839	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
bogdanm	0:9b334a45a8ff	1840	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
bogdanm	0:9b334a45a8ff	1841	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
bogdanm	0:9b334a45a8ff	1842	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
bogdanm	0:9b334a45a8ff	1843	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
bogdanm	0:9b334a45a8ff	1844	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
bogdanm	0:9b334a45a8ff	1845	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
bogdanm	0:9b334a45a8ff	1846	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
bogdanm	0:9b334a45a8ff	1847	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
bogdanm	0:9b334a45a8ff	1848	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
bogdanm	0:9b334a45a8ff	1849	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
bogdanm	0:9b334a45a8ff	1850	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	1851
bogdanm	0:9b334a45a8ff	1852	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	1853	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm	0:9b334a45a8ff	1854	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
bogdanm	0:9b334a45a8ff	1855	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
bogdanm	0:9b334a45a8ff	1856	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm	0:9b334a45a8ff	1857	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
bogdanm	0:9b334a45a8ff	1858	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm	0:9b334a45a8ff	1859	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
bogdanm	0:9b334a45a8ff	1860	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
bogdanm	0:9b334a45a8ff	1861	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
bogdanm	0:9b334a45a8ff	1862	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
bogdanm	0:9b334a45a8ff	1863	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
bogdanm	0:9b334a45a8ff	1864	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
bogdanm	0:9b334a45a8ff	1865	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	1866
bogdanm	0:9b334a45a8ff	1867	/** @brief Force or release APB2 peripheral reset.
bogdanm	0:9b334a45a8ff	1868	*/
bogdanm	0:9b334a45a8ff	1869	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
bogdanm	0:9b334a45a8ff	1870	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
bogdanm	0:9b334a45a8ff	1871	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
bogdanm	0:9b334a45a8ff	1872
bogdanm	0:9b334a45a8ff	1873	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
bogdanm	0:9b334a45a8ff	1874	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
bogdanm	0:9b334a45a8ff	1875	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
bogdanm	0:9b334a45a8ff	1876
bogdanm	0:9b334a45a8ff	1877	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1878	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1879	* power consumption.
bogdanm	0:9b334a45a8ff	1880	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1881	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1882	*/
bogdanm	0:9b334a45a8ff	1883	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
bogdanm	0:9b334a45a8ff	1884	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
bogdanm	0:9b334a45a8ff	1885	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
bogdanm	0:9b334a45a8ff	1886	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
bogdanm	0:9b334a45a8ff	1887	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm	0:9b334a45a8ff	1888
bogdanm	0:9b334a45a8ff	1889	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
bogdanm	0:9b334a45a8ff	1890	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
bogdanm	0:9b334a45a8ff	1891	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
bogdanm	0:9b334a45a8ff	1892	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
bogdanm	0:9b334a45a8ff	1893	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm	0:9b334a45a8ff	1894	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1895	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1896	* power consumption.
bogdanm	0:9b334a45a8ff	1897	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1898	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1899	*/
bogdanm	0:9b334a45a8ff	1900	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
bogdanm	0:9b334a45a8ff	1901	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
bogdanm	0:9b334a45a8ff	1902
bogdanm	0:9b334a45a8ff	1903	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1904	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1905	* power consumption.
bogdanm	0:9b334a45a8ff	1906	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1907	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1908	*/
bogdanm	0:9b334a45a8ff	1909	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
bogdanm	0:9b334a45a8ff	1910	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
bogdanm	0:9b334a45a8ff	1911
bogdanm	0:9b334a45a8ff	1912	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
bogdanm	0:9b334a45a8ff	1913	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
bogdanm	0:9b334a45a8ff	1914
bogdanm	0:9b334a45a8ff	1915	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1916	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1917	* power consumption.
bogdanm	0:9b334a45a8ff	1918	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1919	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1920	*/
bogdanm	0:9b334a45a8ff	1921	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
bogdanm	0:9b334a45a8ff	1922	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
bogdanm	0:9b334a45a8ff	1923	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
bogdanm	0:9b334a45a8ff	1924	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
bogdanm	0:9b334a45a8ff	1925	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
bogdanm	0:9b334a45a8ff	1926	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
bogdanm	0:9b334a45a8ff	1927	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
bogdanm	0:9b334a45a8ff	1928	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
bogdanm	0:9b334a45a8ff	1929	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
bogdanm	0:9b334a45a8ff	1930	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
bogdanm	0:9b334a45a8ff	1931	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
bogdanm	0:9b334a45a8ff	1932	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
bogdanm	0:9b334a45a8ff	1933	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
bogdanm	0:9b334a45a8ff	1934	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
bogdanm	0:9b334a45a8ff	1935
bogdanm	0:9b334a45a8ff	1936	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
bogdanm	0:9b334a45a8ff	1937	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
bogdanm	0:9b334a45a8ff	1938	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
bogdanm	0:9b334a45a8ff	1939	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
bogdanm	0:9b334a45a8ff	1940	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
bogdanm	0:9b334a45a8ff	1941	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
bogdanm	0:9b334a45a8ff	1942	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
bogdanm	0:9b334a45a8ff	1943	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
bogdanm	0:9b334a45a8ff	1944	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
bogdanm	0:9b334a45a8ff	1945	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
bogdanm	0:9b334a45a8ff	1946	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
bogdanm	0:9b334a45a8ff	1947	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
bogdanm	0:9b334a45a8ff	1948	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
bogdanm	0:9b334a45a8ff	1949	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
bogdanm	0:9b334a45a8ff	1950
bogdanm	0:9b334a45a8ff	1951	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1952	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1953	* power consumption.
bogdanm	0:9b334a45a8ff	1954	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1955	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1956	*/
bogdanm	0:9b334a45a8ff	1957	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
bogdanm	0:9b334a45a8ff	1958	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
bogdanm	0:9b334a45a8ff	1959	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
bogdanm	0:9b334a45a8ff	1960	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
bogdanm	0:9b334a45a8ff	1961	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
bogdanm	0:9b334a45a8ff	1962
bogdanm	0:9b334a45a8ff	1963	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
bogdanm	0:9b334a45a8ff	1964	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
bogdanm	0:9b334a45a8ff	1965	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
bogdanm	0:9b334a45a8ff	1966	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
bogdanm	0:9b334a45a8ff	1967	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
bogdanm	0:9b334a45a8ff	1968
bogdanm	0:9b334a45a8ff	1969	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	1970	/------------------------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	1971
bogdanm	0:9b334a45a8ff	1972	/------------------------------------------------- PLL Configuration ----------------------------------------/
bogdanm	0:9b334a45a8ff	1973	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	1974	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
bogdanm	0:9b334a45a8ff	1975	* @note This function must be used only when the main PLL is disabled.
bogdanm	0:9b334a45a8ff	1976	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
bogdanm	0:9b334a45a8ff	1977	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1978	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	1979	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	1980	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
bogdanm	0:9b334a45a8ff	1981	* @param __PLLM__: specifies the division factor for PLL VCO input clock
bogdanm	0:9b334a45a8ff	1982	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm	0:9b334a45a8ff	1983	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
bogdanm	0:9b334a45a8ff	1984	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm	0:9b334a45a8ff	1985	* of 2 MHz to limit PLL jitter.
bogdanm	0:9b334a45a8ff	1986	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
bogdanm	0:9b334a45a8ff	1987	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	1988	* @note You have to set the PLLN parameter correctly to ensure that the VCO
bogdanm	0:9b334a45a8ff	1989	* output frequency is between 192 and 432 MHz.
bogdanm	0:9b334a45a8ff	1990	*
bogdanm	0:9b334a45a8ff	1991	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
bogdanm	0:9b334a45a8ff	1992	* This parameter must be a number in the range {2, 4, 6, or 8}.
bogdanm	0:9b334a45a8ff	1993	*
bogdanm	0:9b334a45a8ff	1994	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
bogdanm	0:9b334a45a8ff	1995	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	1996	* @note If the USB OTG FS is used in your application, you have to set the
bogdanm	0:9b334a45a8ff	1997	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
bogdanm	0:9b334a45a8ff	1998	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
bogdanm	0:9b334a45a8ff	1999	* correctly.
bogdanm	0:9b334a45a8ff	2000	*
bogdanm	0:9b334a45a8ff	2001	* @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
bogdanm	0:9b334a45a8ff	2002	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	2003	* @note This parameter is only available in STM32F446xx devices.
bogdanm	0:9b334a45a8ff	2004	*
bogdanm	0:9b334a45a8ff	2005	*/
bogdanm	0:9b334a45a8ff	2006	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
bogdanm	0:9b334a45a8ff	2007	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
bogdanm	0:9b334a45a8ff	2008	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
bogdanm	0:9b334a45a8ff	2009	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
bogdanm	0:9b334a45a8ff	2010	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
bogdanm	0:9b334a45a8ff	2011	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
bogdanm	0:9b334a45a8ff	2012	#else
bogdanm	0:9b334a45a8ff	2013	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
bogdanm	0:9b334a45a8ff	2014	* @note This function must be used only when the main PLL is disabled.
bogdanm	0:9b334a45a8ff	2015	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
bogdanm	0:9b334a45a8ff	2016	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2017	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	2018	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	2019	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
bogdanm	0:9b334a45a8ff	2020	* @param __PLLM__: specifies the division factor for PLL VCO input clock
bogdanm	0:9b334a45a8ff	2021	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm	0:9b334a45a8ff	2022	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
bogdanm	0:9b334a45a8ff	2023	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm	0:9b334a45a8ff	2024	* of 2 MHz to limit PLL jitter.
bogdanm	0:9b334a45a8ff	2025	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
bogdanm	0:9b334a45a8ff	2026	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	2027	* @note You have to set the PLLN parameter correctly to ensure that the VCO
bogdanm	0:9b334a45a8ff	2028	* output frequency is between 192 and 432 MHz.
bogdanm	0:9b334a45a8ff	2029	*
bogdanm	0:9b334a45a8ff	2030	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
bogdanm	0:9b334a45a8ff	2031	* This parameter must be a number in the range {2, 4, 6, or 8}.
bogdanm	0:9b334a45a8ff	2032	*
bogdanm	0:9b334a45a8ff	2033	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
bogdanm	0:9b334a45a8ff	2034	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	2035	* @note If the USB OTG FS is used in your application, you have to set the
bogdanm	0:9b334a45a8ff	2036	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
bogdanm	0:9b334a45a8ff	2037	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
bogdanm	0:9b334a45a8ff	2038	* correctly.
bogdanm	0:9b334a45a8ff	2039	*
bogdanm	0:9b334a45a8ff	2040	*/
bogdanm	0:9b334a45a8ff	2041	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
bogdanm	0:9b334a45a8ff	2042	(RCC->PLLCFGR = (0x20000000 \| (__RCC_PLLSource__) \| (__PLLM__)\| \
bogdanm	0:9b334a45a8ff	2043	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
bogdanm	0:9b334a45a8ff	2044	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
bogdanm	0:9b334a45a8ff	2045	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
bogdanm	0:9b334a45a8ff	2046	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	2047	/-------------------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	2048
bogdanm	0:9b334a45a8ff	2049	/------------------------------------------- PLLI2S Configuration --------------------------------------/
bogdanm	0:9b334a45a8ff	2050	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2051	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
bogdanm	0:9b334a45a8ff	2052	* @note This macro must be used only when the PLLI2S is disabled.
bogdanm	0:9b334a45a8ff	2053	* @note PLLI2S clock source is common with the main PLL (configured in
bogdanm	0:9b334a45a8ff	2054	* HAL_RCC_ClockConfig() API).
bogdanm	0:9b334a45a8ff	2055	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
bogdanm	0:9b334a45a8ff	2056	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm	0:9b334a45a8ff	2057	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
bogdanm	0:9b334a45a8ff	2058	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm	0:9b334a45a8ff	2059	* of 1 MHz to limit PLLI2S jitter.
bogdanm	0:9b334a45a8ff	2060	* @note The PLLI2SM parameter is only used with STM32F411xE and STM32F446xx Devices
bogdanm	0:9b334a45a8ff	2061	*
bogdanm	0:9b334a45a8ff	2062	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
bogdanm	0:9b334a45a8ff	2063	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	2064	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
bogdanm	0:9b334a45a8ff	2065	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm	0:9b334a45a8ff	2066	*
bogdanm	0:9b334a45a8ff	2067	* @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
bogdanm	0:9b334a45a8ff	2068	* This parameter must be a number in the range {2, 4, 6, or 8}.
bogdanm	0:9b334a45a8ff	2069	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
bogdanm	0:9b334a45a8ff	2070	*
bogdanm	0:9b334a45a8ff	2071	* @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm	0:9b334a45a8ff	2072	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	2073	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
bogdanm	0:9b334a45a8ff	2074	* on the I2S clock frequency.
bogdanm	0:9b334a45a8ff	2075	*
bogdanm	0:9b334a45a8ff	2076	* @param __PLLI2SQ__: specifies the division factor for SAI clock
bogdanm	0:9b334a45a8ff	2077	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	2078	* @note the PLLI2SQ parameter is only available with STM32F427/437/429x/439xx Devices
bogdanm	0:9b334a45a8ff	2079	*
bogdanm	0:9b334a45a8ff	2080	*/
bogdanm	0:9b334a45a8ff	2081	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
bogdanm	0:9b334a45a8ff	2082	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
bogdanm	0:9b334a45a8ff	2083	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
bogdanm	0:9b334a45a8ff	2084	((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
bogdanm	0:9b334a45a8ff	2085	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
bogdanm	0:9b334a45a8ff	2086	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
bogdanm	0:9b334a45a8ff	2087	#else
bogdanm	0:9b334a45a8ff	2088	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
bogdanm	0:9b334a45a8ff	2089	* @note This macro must be used only when the PLLI2S is disabled.
bogdanm	0:9b334a45a8ff	2090	* @note PLLI2S clock source is common with the main PLL (configured in
bogdanm	0:9b334a45a8ff	2091	* HAL_RCC_ClockConfig() API).
bogdanm	0:9b334a45a8ff	2092	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
bogdanm	0:9b334a45a8ff	2093	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	2094	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
bogdanm	0:9b334a45a8ff	2095	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm	0:9b334a45a8ff	2096	* @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm	0:9b334a45a8ff	2097	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	2098	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
bogdanm	0:9b334a45a8ff	2099	* on the I2S clock frequency.
bogdanm	0:9b334a45a8ff	2100	*
bogdanm	0:9b334a45a8ff	2101	*/
bogdanm	0:9b334a45a8ff	2102	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
bogdanm	0:9b334a45a8ff	2103	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \| \
bogdanm	0:9b334a45a8ff	2104	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
bogdanm	0:9b334a45a8ff	2105	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	2106
bogdanm	0:9b334a45a8ff	2107	#if defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	2108
bogdanm	0:9b334a45a8ff	2109	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
bogdanm	0:9b334a45a8ff	2110	* @note This macro must be used only when the PLLI2S is disabled.
bogdanm	0:9b334a45a8ff	2111	* @note This macro must be used only when the PLLI2S is disabled.
bogdanm	0:9b334a45a8ff	2112	* @note PLLI2S clock source is common with the main PLL (configured in
bogdanm	0:9b334a45a8ff	2113	* HAL_RCC_ClockConfig() API).
bogdanm	0:9b334a45a8ff	2114	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
bogdanm	0:9b334a45a8ff	2115	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm	0:9b334a45a8ff	2116	* @note The PLLI2SM parameter is only used with STM32F411xE Devices
bogdanm	0:9b334a45a8ff	2117	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
bogdanm	0:9b334a45a8ff	2118	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm	0:9b334a45a8ff	2119	* of 2 MHz to limit PLLI2S jitter.
bogdanm	0:9b334a45a8ff	2120	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
bogdanm	0:9b334a45a8ff	2121	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	2122	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
bogdanm	0:9b334a45a8ff	2123	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm	0:9b334a45a8ff	2124	* @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm	0:9b334a45a8ff	2125	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	2126	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
bogdanm	0:9b334a45a8ff	2127	* on the I2S clock frequency.
bogdanm	0:9b334a45a8ff	2128	*/
bogdanm	0:9b334a45a8ff	2129	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
bogdanm	0:9b334a45a8ff	2130	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
bogdanm	0:9b334a45a8ff	2131	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
bogdanm	0:9b334a45a8ff	2132	#endif /* STM32F411xE */
bogdanm	0:9b334a45a8ff	2133
bogdanm	0:9b334a45a8ff	2134	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	2135	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
bogdanm	0:9b334a45a8ff	2136	* @note This macro must be used only when the PLLI2S is disabled.
bogdanm	0:9b334a45a8ff	2137	* @note PLLI2S clock source is common with the main PLL (configured in
bogdanm	0:9b334a45a8ff	2138	* HAL_RCC_ClockConfig() API)
bogdanm	0:9b334a45a8ff	2139	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm	0:9b334a45a8ff	2140	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	2141	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
bogdanm	0:9b334a45a8ff	2142	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm	0:9b334a45a8ff	2143	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
bogdanm	0:9b334a45a8ff	2144	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	2145	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx Devices
bogdanm	0:9b334a45a8ff	2146	* and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
bogdanm	0:9b334a45a8ff	2147	* @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm	0:9b334a45a8ff	2148	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	2149	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
bogdanm	0:9b334a45a8ff	2150	* on the I2S clock frequency.
bogdanm	0:9b334a45a8ff	2151	*/
bogdanm	0:9b334a45a8ff	2152	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) \|\
bogdanm	0:9b334a45a8ff	2153	((__PLLI2SQ__) << 24) \|\
bogdanm	0:9b334a45a8ff	2154	((__PLLI2SR__) << 28))
bogdanm	0:9b334a45a8ff	2155	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	2156	/----------------------------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	2157
bogdanm	0:9b334a45a8ff	2158	/--------------------------------------------------- PLLSAI Configuration ---------------------------------------/
bogdanm	0:9b334a45a8ff	2159	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2160	/** @brief Macros to Enable or Disable the PLLISAI.
bogdanm	0:9b334a45a8ff	2161	* @note The PLLSAI is only available with STM32F429x/439x Devices.
bogdanm	0:9b334a45a8ff	2162	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	2163	*/
bogdanm	0:9b334a45a8ff	2164	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
bogdanm	0:9b334a45a8ff	2165	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
bogdanm	0:9b334a45a8ff	2166
bogdanm	0:9b334a45a8ff	2167	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2168	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
bogdanm	0:9b334a45a8ff	2169	*
bogdanm	0:9b334a45a8ff	2170	* @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
bogdanm	0:9b334a45a8ff	2171	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm	0:9b334a45a8ff	2172	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
bogdanm	0:9b334a45a8ff	2173	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm	0:9b334a45a8ff	2174	* of 1 MHz to limit PLLI2S jitter.
bogdanm	0:9b334a45a8ff	2175	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
bogdanm	0:9b334a45a8ff	2176	*
bogdanm	0:9b334a45a8ff	2177	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
bogdanm	0:9b334a45a8ff	2178	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	2179	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
bogdanm	0:9b334a45a8ff	2180	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm	0:9b334a45a8ff	2181	*
bogdanm	0:9b334a45a8ff	2182	* @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
bogdanm	0:9b334a45a8ff	2183	* This parameter must be a number in the range {2, 4, 6, or 8}.
bogdanm	0:9b334a45a8ff	2184	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
bogdanm	0:9b334a45a8ff	2185	*
bogdanm	0:9b334a45a8ff	2186	* @param __PLLSAIQ__: specifies the division factor for SAI clock
bogdanm	0:9b334a45a8ff	2187	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	2188	*
bogdanm	0:9b334a45a8ff	2189	* @param __PLLSAIR__: specifies the division factor for LTDC clock
bogdanm	0:9b334a45a8ff	2190	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	2191	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
bogdanm	0:9b334a45a8ff	2192	*/
bogdanm	0:9b334a45a8ff	2193	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
bogdanm	0:9b334a45a8ff	2194	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
bogdanm	0:9b334a45a8ff	2195	((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
bogdanm	0:9b334a45a8ff	2196	((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \| \
bogdanm	0:9b334a45a8ff	2197	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
bogdanm	0:9b334a45a8ff	2198	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	2199
bogdanm	0:9b334a45a8ff	2200	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	2201	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
bogdanm	0:9b334a45a8ff	2202	*
bogdanm	0:9b334a45a8ff	2203	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
bogdanm	0:9b334a45a8ff	2204	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	0:9b334a45a8ff	2205	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
bogdanm	0:9b334a45a8ff	2206	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm	0:9b334a45a8ff	2207	*
bogdanm	0:9b334a45a8ff	2208	* @param __PLLSAIQ__: specifies the division factor for SAI clock
bogdanm	0:9b334a45a8ff	2209	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	2210	*
bogdanm	0:9b334a45a8ff	2211	* @param __PLLSAIR__: specifies the division factor for LTDC clock
bogdanm	0:9b334a45a8ff	2212	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	0:9b334a45a8ff	2213	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
bogdanm	0:9b334a45a8ff	2214	*/
bogdanm	0:9b334a45a8ff	2215	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
bogdanm	0:9b334a45a8ff	2216	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
bogdanm	0:9b334a45a8ff	2217	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \| \
bogdanm	0:9b334a45a8ff	2218	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
bogdanm	0:9b334a45a8ff	2219	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	2220
bogdanm	0:9b334a45a8ff	2221	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
bogdanm	0:9b334a45a8ff	2222	/----------------------------------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	2223
bogdanm	0:9b334a45a8ff	2224	/----------------------------------------- PLLSAI/PLLI2S Dividers Configuration ---------------------------------------/
bogdanm	0:9b334a45a8ff	2225	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2226	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
bogdanm	0:9b334a45a8ff	2227	* @note This function must be called before enabling the PLLI2S.
bogdanm	0:9b334a45a8ff	2228	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
bogdanm	0:9b334a45a8ff	2229	* This parameter must be a number between 1 and 32.
bogdanm	0:9b334a45a8ff	2230	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
bogdanm	0:9b334a45a8ff	2231	*/
bogdanm	0:9b334a45a8ff	2232	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
bogdanm	0:9b334a45a8ff	2233
bogdanm	0:9b334a45a8ff	2234	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
bogdanm	0:9b334a45a8ff	2235	* @note This function must be called before enabling the PLLSAI.
bogdanm	0:9b334a45a8ff	2236	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
bogdanm	0:9b334a45a8ff	2237	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
bogdanm	0:9b334a45a8ff	2238	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
bogdanm	0:9b334a45a8ff	2239	*/
bogdanm	0:9b334a45a8ff	2240	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
bogdanm	0:9b334a45a8ff	2241	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
bogdanm	0:9b334a45a8ff	2242
bogdanm	0:9b334a45a8ff	2243	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	2244	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
bogdanm	0:9b334a45a8ff	2245	*
bogdanm	0:9b334a45a8ff	2246	* @note The LTDC peripheral is only available with STM32F427/437/429/439xx Devices.
bogdanm	0:9b334a45a8ff	2247	* @note This function must be called before enabling the PLLSAI.
bogdanm	0:9b334a45a8ff	2248	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
bogdanm	0:9b334a45a8ff	2249	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
bogdanm	0:9b334a45a8ff	2250	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
bogdanm	0:9b334a45a8ff	2251	*/
bogdanm	0:9b334a45a8ff	2252	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
bogdanm	0:9b334a45a8ff	2253	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	2254	/-----------------------------------------------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	2255
bogdanm	0:9b334a45a8ff	2256	/-------------------------------------------------- Peripheral Clock selection -----------------------------------------------------/
bogdanm	0:9b334a45a8ff	2257	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
bogdanm	0:9b334a45a8ff	2258	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
bogdanm	0:9b334a45a8ff	2259	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	2260	/** @brief Macro to configure the I2S clock source (I2SCLK).
bogdanm	0:9b334a45a8ff	2261	* @note This function must be called before enabling the I2S APB clock.
bogdanm	0:9b334a45a8ff	2262	* @param __SOURCE__: specifies the I2S clock source.
bogdanm	0:9b334a45a8ff	2263	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2264	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
bogdanm	0:9b334a45a8ff	2265	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm	0:9b334a45a8ff	2266	* used as I2S clock source.
bogdanm	0:9b334a45a8ff	2267	*/
bogdanm	0:9b334a45a8ff	2268	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
bogdanm	0:9b334a45a8ff	2269	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx */
bogdanm	0:9b334a45a8ff	2270
bogdanm	0:9b334a45a8ff	2271	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	2272
bogdanm	0:9b334a45a8ff	2273	/** @brief Macro to configure SAI1BlockA clock source selection.
bogdanm	0:9b334a45a8ff	2274	* @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices.
bogdanm	0:9b334a45a8ff	2275	* @note This function must be called before enabling PLLSAI, PLLI2S and
bogdanm	0:9b334a45a8ff	2276	* the SAI clock.
bogdanm	0:9b334a45a8ff	2277	* @param __SOURCE__: specifies the SAI Block A clock source.
bogdanm	0:9b334a45a8ff	2278	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2279	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
bogdanm	0:9b334a45a8ff	2280	* as SAI1 Block A clock.
bogdanm	0:9b334a45a8ff	2281	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
bogdanm	0:9b334a45a8ff	2282	* as SAI1 Block A clock.
bogdanm	0:9b334a45a8ff	2283	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
bogdanm	0:9b334a45a8ff	2284	* used as SAI1 Block A clock.
bogdanm	0:9b334a45a8ff	2285	*/
bogdanm	0:9b334a45a8ff	2286	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
bogdanm	0:9b334a45a8ff	2287
bogdanm	0:9b334a45a8ff	2288	/** @brief Macro to configure SAI1BlockB clock source selection.
bogdanm	0:9b334a45a8ff	2289	* @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices.
bogdanm	0:9b334a45a8ff	2290	* @note This function must be called before enabling PLLSAI, PLLI2S and
bogdanm	0:9b334a45a8ff	2291	* the SAI clock.
bogdanm	0:9b334a45a8ff	2292	* @param __SOURCE__: specifies the SAI Block B clock source.
bogdanm	0:9b334a45a8ff	2293	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2294	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
bogdanm	0:9b334a45a8ff	2295	* as SAI1 Block B clock.
bogdanm	0:9b334a45a8ff	2296	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
bogdanm	0:9b334a45a8ff	2297	* as SAI1 Block B clock.
bogdanm	0:9b334a45a8ff	2298	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
bogdanm	0:9b334a45a8ff	2299	* used as SAI1 Block B clock.
bogdanm	0:9b334a45a8ff	2300	*/
bogdanm	0:9b334a45a8ff	2301	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
bogdanm	0:9b334a45a8ff	2302	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	2303
bogdanm	0:9b334a45a8ff	2304	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2305	/** @brief Macro to configure SAI1 clock source selection.
bogdanm	0:9b334a45a8ff	2306	* @note This configuration is only available with STM32F446xx Devices.
bogdanm	0:9b334a45a8ff	2307	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
bogdanm	0:9b334a45a8ff	2308	* the SAI clock.
bogdanm	0:9b334a45a8ff	2309	* @param __SOURCE__: specifies the SAI1 clock source.
bogdanm	0:9b334a45a8ff	2310	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2311	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2312	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2313	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2314	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2315	*/
bogdanm	0:9b334a45a8ff	2316	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
bogdanm	0:9b334a45a8ff	2317
bogdanm	0:9b334a45a8ff	2318	/** @brief Macro to Get SAI1 clock source selection.
bogdanm	0:9b334a45a8ff	2319	* @note This configuration is only available with STM32F446xx Devices.
bogdanm	0:9b334a45a8ff	2320	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2321	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2322	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2323	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2324	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2325	*/
bogdanm	0:9b334a45a8ff	2326	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
bogdanm	0:9b334a45a8ff	2327
bogdanm	0:9b334a45a8ff	2328	/** @brief Macro to configure SAI2 clock source selection.
bogdanm	0:9b334a45a8ff	2329	* @note This configuration is only available with STM32F446xx Devices.
bogdanm	0:9b334a45a8ff	2330	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
bogdanm	0:9b334a45a8ff	2331	* the SAI clock.
bogdanm	0:9b334a45a8ff	2332	* @param __SOURCE__: specifies the SAI2 clock source.
bogdanm	0:9b334a45a8ff	2333	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2334	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
bogdanm	0:9b334a45a8ff	2335	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
bogdanm	0:9b334a45a8ff	2336	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
bogdanm	0:9b334a45a8ff	2337	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
bogdanm	0:9b334a45a8ff	2338	*/
bogdanm	0:9b334a45a8ff	2339	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
bogdanm	0:9b334a45a8ff	2340
bogdanm	0:9b334a45a8ff	2341	/** @brief Macro to Get SAI2 clock source selection.
bogdanm	0:9b334a45a8ff	2342	* @note This configuration is only available with STM32F446xx Devices.
bogdanm	0:9b334a45a8ff	2343	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2344	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
bogdanm	0:9b334a45a8ff	2345	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
bogdanm	0:9b334a45a8ff	2346	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
bogdanm	0:9b334a45a8ff	2347	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
bogdanm	0:9b334a45a8ff	2348	*/
bogdanm	0:9b334a45a8ff	2349	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
bogdanm	0:9b334a45a8ff	2350
bogdanm	0:9b334a45a8ff	2351	/** @brief Macro to configure I2S APB1 clock source selection.
bogdanm	0:9b334a45a8ff	2352	* @note This configuration is only available with STM32F446xx Devices.
bogdanm	0:9b334a45a8ff	2353	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
bogdanm	0:9b334a45a8ff	2354	* @param __SOURCE__: specifies the I2S APB1 clock source.
bogdanm	0:9b334a45a8ff	2355	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2356	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
bogdanm	0:9b334a45a8ff	2357	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2358	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2359	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
bogdanm	0:9b334a45a8ff	2360	*/
bogdanm	0:9b334a45a8ff	2361	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
bogdanm	0:9b334a45a8ff	2362
bogdanm	0:9b334a45a8ff	2363	/** @brief Macro to Get I2S APB1 clock source selection.
bogdanm	0:9b334a45a8ff	2364	* @note This configuration is only available with STM32F446xx Devices.
bogdanm	0:9b334a45a8ff	2365	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2366	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
bogdanm	0:9b334a45a8ff	2367	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2368	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2369	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
bogdanm	0:9b334a45a8ff	2370	*/
bogdanm	0:9b334a45a8ff	2371	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
bogdanm	0:9b334a45a8ff	2372
bogdanm	0:9b334a45a8ff	2373	/** @brief Macro to configure I2S APB2 clock source selection.
bogdanm	0:9b334a45a8ff	2374	* @note This configuration is only available with STM32F446xx Devices.
bogdanm	0:9b334a45a8ff	2375	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
bogdanm	0:9b334a45a8ff	2376	* @param __SOURCE__: specifies the SAI Block A clock source.
bogdanm	0:9b334a45a8ff	2377	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2378	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
bogdanm	0:9b334a45a8ff	2379	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2380	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2381	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
bogdanm	0:9b334a45a8ff	2382	*/
bogdanm	0:9b334a45a8ff	2383	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
bogdanm	0:9b334a45a8ff	2384
bogdanm	0:9b334a45a8ff	2385	/** @brief Macro to Get I2S APB2 clock source selection.
bogdanm	0:9b334a45a8ff	2386	* @note This configuration is only available with STM32F446xx Devices.
bogdanm	0:9b334a45a8ff	2387	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2388	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
bogdanm	0:9b334a45a8ff	2389	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2390	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
bogdanm	0:9b334a45a8ff	2391	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
bogdanm	0:9b334a45a8ff	2392	*/
bogdanm	0:9b334a45a8ff	2393	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
bogdanm	0:9b334a45a8ff	2394
bogdanm	0:9b334a45a8ff	2395	/** @brief Macro to configure the CEC clock.
bogdanm	0:9b334a45a8ff	2396	* @param __SOURCE__: specifies the CEC clock source.
bogdanm	0:9b334a45a8ff	2397	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2398	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	0:9b334a45a8ff	2399	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	0:9b334a45a8ff	2400	*/
bogdanm	0:9b334a45a8ff	2401	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
bogdanm	0:9b334a45a8ff	2402
bogdanm	0:9b334a45a8ff	2403	/** @brief Macro to Get the CEC clock.
bogdanm	0:9b334a45a8ff	2404	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2405	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
bogdanm	0:9b334a45a8ff	2406	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	0:9b334a45a8ff	2407	*/
bogdanm	0:9b334a45a8ff	2408	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
bogdanm	0:9b334a45a8ff	2409
bogdanm	0:9b334a45a8ff	2410	/** @brief Macro to configure the FMPI2C1 clock.
bogdanm	0:9b334a45a8ff	2411	* @param __SOURCE__: specifies the FMPI2C1 clock source.
bogdanm	0:9b334a45a8ff	2412	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2413	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock
bogdanm	0:9b334a45a8ff	2414	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock
bogdanm	0:9b334a45a8ff	2415	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	0:9b334a45a8ff	2416	*/
bogdanm	0:9b334a45a8ff	2417	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
bogdanm	0:9b334a45a8ff	2418
bogdanm	0:9b334a45a8ff	2419	/** @brief Macro to Get the FMPI2C1 clock.
bogdanm	0:9b334a45a8ff	2420	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2421	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock
bogdanm	0:9b334a45a8ff	2422	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock
bogdanm	0:9b334a45a8ff	2423	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	0:9b334a45a8ff	2424	*/
bogdanm	0:9b334a45a8ff	2425	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
bogdanm	0:9b334a45a8ff	2426
bogdanm	0:9b334a45a8ff	2427	/** @brief Macro to configure the CLK48 clock.
bogdanm	0:9b334a45a8ff	2428	* @param __SOURCE__: specifies the CK48 clock source.
bogdanm	0:9b334a45a8ff	2429	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2430	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
bogdanm	0:9b334a45a8ff	2431	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
bogdanm	0:9b334a45a8ff	2432	*/
bogdanm	0:9b334a45a8ff	2433	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
bogdanm	0:9b334a45a8ff	2434
bogdanm	0:9b334a45a8ff	2435	/** @brief Macro to Get the CLK48 clock.
bogdanm	0:9b334a45a8ff	2436	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2437	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
bogdanm	0:9b334a45a8ff	2438	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
bogdanm	0:9b334a45a8ff	2439	*/
bogdanm	0:9b334a45a8ff	2440	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
bogdanm	0:9b334a45a8ff	2441
bogdanm	0:9b334a45a8ff	2442	/** @brief Macro to configure the SDIO clock.
bogdanm	0:9b334a45a8ff	2443	* @param __SOURCE__: specifies the SDIO clock source.
bogdanm	0:9b334a45a8ff	2444	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2445	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
bogdanm	0:9b334a45a8ff	2446	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
bogdanm	0:9b334a45a8ff	2447	*/
bogdanm	0:9b334a45a8ff	2448	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
bogdanm	0:9b334a45a8ff	2449
bogdanm	0:9b334a45a8ff	2450	/** @brief Macro to Get the SDIO clock.
bogdanm	0:9b334a45a8ff	2451	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2452	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
bogdanm	0:9b334a45a8ff	2453	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
bogdanm	0:9b334a45a8ff	2454	*/
bogdanm	0:9b334a45a8ff	2455	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
bogdanm	0:9b334a45a8ff	2456
bogdanm	0:9b334a45a8ff	2457	/** @brief Macro to configure the SPDIFRX clock.
bogdanm	0:9b334a45a8ff	2458	* @param __SOURCE__: specifies the SPDIFRX clock source.
bogdanm	0:9b334a45a8ff	2459	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2460	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
bogdanm	0:9b334a45a8ff	2461	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
bogdanm	0:9b334a45a8ff	2462	*/
bogdanm	0:9b334a45a8ff	2463	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
bogdanm	0:9b334a45a8ff	2464
bogdanm	0:9b334a45a8ff	2465	/** @brief Macro to Get the SPDIFRX clock.
bogdanm	0:9b334a45a8ff	2466	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	2467	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
bogdanm	0:9b334a45a8ff	2468	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
bogdanm	0:9b334a45a8ff	2469	*/
bogdanm	0:9b334a45a8ff	2470	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
bogdanm	0:9b334a45a8ff	2471	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	2472
bogdanm	0:9b334a45a8ff	2473	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
bogdanm	0:9b334a45a8ff	2474	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2475
bogdanm	0:9b334a45a8ff	2476	/** @brief Macro to configure the Timers clocks prescalers
bogdanm	0:9b334a45a8ff	2477	* @note This feature is only available with STM32F429x/439x Devices.
bogdanm	0:9b334a45a8ff	2478	* @param __PRESC__ : specifies the Timers clocks prescalers selection
bogdanm	0:9b334a45a8ff	2479	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2480	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
bogdanm	0:9b334a45a8ff	2481	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
bogdanm	0:9b334a45a8ff	2482	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
bogdanm	0:9b334a45a8ff	2483	* division by 4 or more.
bogdanm	0:9b334a45a8ff	2484	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
bogdanm	0:9b334a45a8ff	2485	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
bogdanm	0:9b334a45a8ff	2486	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
bogdanm	0:9b334a45a8ff	2487	* to division by 8 or more.
bogdanm	0:9b334a45a8ff	2488	*/
bogdanm	0:9b334a45a8ff	2489	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
bogdanm	0:9b334a45a8ff	2490
bogdanm	0:9b334a45a8ff	2491	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx */
bogdanm	0:9b334a45a8ff	2492
bogdanm	0:9b334a45a8ff	2493	/-------------------------------------------------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	2494
bogdanm	0:9b334a45a8ff	2495	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2496	/** @brief Enable PLLSAI_RDY interrupt.
bogdanm	0:9b334a45a8ff	2497	*/
bogdanm	0:9b334a45a8ff	2498	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
bogdanm	0:9b334a45a8ff	2499
bogdanm	0:9b334a45a8ff	2500	/** @brief Disable PLLSAI_RDY interrupt.
bogdanm	0:9b334a45a8ff	2501	*/
bogdanm	0:9b334a45a8ff	2502	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
bogdanm	0:9b334a45a8ff	2503
bogdanm	0:9b334a45a8ff	2504	/** @brief Clear the PLLSAI RDY interrupt pending bits.
bogdanm	0:9b334a45a8ff	2505	*/
bogdanm	0:9b334a45a8ff	2506	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
bogdanm	0:9b334a45a8ff	2507
bogdanm	0:9b334a45a8ff	2508	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	2509	* @retval The new state (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	2510	*/
bogdanm	0:9b334a45a8ff	2511	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
bogdanm	0:9b334a45a8ff	2512
bogdanm	0:9b334a45a8ff	2513	/** @brief Check PLLSAI RDY flag is set or not.
bogdanm	0:9b334a45a8ff	2514	* @retval The new state (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	2515	*/
bogdanm	0:9b334a45a8ff	2516	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
bogdanm	0:9b334a45a8ff	2517
bogdanm	0:9b334a45a8ff	2518	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
bogdanm	0:9b334a45a8ff	2519
bogdanm	0:9b334a45a8ff	2520	/**
bogdanm	0:9b334a45a8ff	2521	* @}
bogdanm	0:9b334a45a8ff	2522	*/
bogdanm	0:9b334a45a8ff	2523
bogdanm	0:9b334a45a8ff	2524	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2525	/** @addtogroup RCCEx_Exported_Functions
bogdanm	0:9b334a45a8ff	2526	* @{
bogdanm	0:9b334a45a8ff	2527	*/
bogdanm	0:9b334a45a8ff	2528
bogdanm	0:9b334a45a8ff	2529	/** @addtogroup RCCEx_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	2530	* @{
bogdanm	0:9b334a45a8ff	2531	*/
bogdanm	0:9b334a45a8ff	2532	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	0:9b334a45a8ff	2533	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	0:9b334a45a8ff	2534
bogdanm	0:9b334a45a8ff	2535	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2536	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
bogdanm	0:9b334a45a8ff	2537	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	2538
bogdanm	0:9b334a45a8ff	2539	#if defined(STM32F411xE) \|\| defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2540	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
bogdanm	0:9b334a45a8ff	2541	#endif /* STM32F411xE \|\| STM32F446xx */
bogdanm	0:9b334a45a8ff	2542	/**
bogdanm	0:9b334a45a8ff	2543	* @}
bogdanm	0:9b334a45a8ff	2544	*/
bogdanm	0:9b334a45a8ff	2545
bogdanm	0:9b334a45a8ff	2546	/**
bogdanm	0:9b334a45a8ff	2547	* @}
bogdanm	0:9b334a45a8ff	2548	*/
bogdanm	0:9b334a45a8ff	2549	/* Private types -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2550	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2551	/* Private constants ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2552	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
bogdanm	0:9b334a45a8ff	2553	* @{
bogdanm	0:9b334a45a8ff	2554	*/
bogdanm	0:9b334a45a8ff	2555
bogdanm	0:9b334a45a8ff	2556	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
bogdanm	0:9b334a45a8ff	2557	* @brief RCC registers bit address in the alias region
bogdanm	0:9b334a45a8ff	2558	* @{
bogdanm	0:9b334a45a8ff	2559	*/
bogdanm	0:9b334a45a8ff	2560	/* --- CR Register ---*/
bogdanm	0:9b334a45a8ff	2561	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2562	/* Alias word address of PLLSAION bit */
bogdanm	0:9b334a45a8ff	2563	#define RCC_PLLSAION_BIT_NUMBER 0x1C
bogdanm	0:9b334a45a8ff	2564	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
bogdanm	0:9b334a45a8ff	2565
bogdanm	0:9b334a45a8ff	2566	/* --- DCKCFGR Register ---*/
bogdanm	0:9b334a45a8ff	2567	/* Alias word address of TIMPRE bit */
bogdanm	0:9b334a45a8ff	2568	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
bogdanm	0:9b334a45a8ff	2569	#define RCC_TIMPRE_BIT_NUMBER 0x18
bogdanm	0:9b334a45a8ff	2570	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
bogdanm	0:9b334a45a8ff	2571	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx */
bogdanm	0:9b334a45a8ff	2572
bogdanm	0:9b334a45a8ff	2573	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	2574
bogdanm	0:9b334a45a8ff	2575	/**
bogdanm	0:9b334a45a8ff	2576	* @}
bogdanm	0:9b334a45a8ff	2577	*/
bogdanm	0:9b334a45a8ff	2578
bogdanm	0:9b334a45a8ff	2579	/**
bogdanm	0:9b334a45a8ff	2580	* @}
bogdanm	0:9b334a45a8ff	2581	*/
bogdanm	0:9b334a45a8ff	2582
bogdanm	0:9b334a45a8ff	2583	/* Private macros ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2584	/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
bogdanm	0:9b334a45a8ff	2585	* @{
bogdanm	0:9b334a45a8ff	2586	*/
bogdanm	0:9b334a45a8ff	2587	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
bogdanm	0:9b334a45a8ff	2588	* @{
bogdanm	0:9b334a45a8ff	2589	*/
bogdanm	0:9b334a45a8ff	2590
bogdanm	0:9b334a45a8ff	2591	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	2592	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
bogdanm	0:9b334a45a8ff	2593	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	2594
bogdanm	0:9b334a45a8ff	2595	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
bogdanm	0:9b334a45a8ff	2596	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	2597	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
bogdanm	0:9b334a45a8ff	2598	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
bogdanm	0:9b334a45a8ff	2599
bogdanm	0:9b334a45a8ff	2600	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2601	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000007FF))
bogdanm	0:9b334a45a8ff	2602	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	2603
bogdanm	0:9b334a45a8ff	2604	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
bogdanm	0:9b334a45a8ff	2605	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
bogdanm	0:9b334a45a8ff	2606
bogdanm	0:9b334a45a8ff	2607
bogdanm	0:9b334a45a8ff	2608	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2609	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
bogdanm	0:9b334a45a8ff	2610
bogdanm	0:9b334a45a8ff	2611	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
bogdanm	0:9b334a45a8ff	2612
bogdanm	0:9b334a45a8ff	2613	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
bogdanm	0:9b334a45a8ff	2614
bogdanm	0:9b334a45a8ff	2615	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
bogdanm	0:9b334a45a8ff	2616
bogdanm	0:9b334a45a8ff	2617	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
bogdanm	0:9b334a45a8ff	2618
bogdanm	0:9b334a45a8ff	2619	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
bogdanm	0:9b334a45a8ff	2620
bogdanm	0:9b334a45a8ff	2621	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
bogdanm	0:9b334a45a8ff	2622	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
bogdanm	0:9b334a45a8ff	2623	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
bogdanm	0:9b334a45a8ff	2624	((VALUE) == RCC_PLLSAIDIVR_16))
bogdanm	0:9b334a45a8ff	2625	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	2626
bogdanm	0:9b334a45a8ff	2627	#if defined(STM32F446xx) \|\| defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	2628	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
bogdanm	0:9b334a45a8ff	2629
bogdanm	0:9b334a45a8ff	2630	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
bogdanm	0:9b334a45a8ff	2631	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
bogdanm	0:9b334a45a8ff	2632	#endif /* STM32F446xx \|\| STM32F411xE */
bogdanm	0:9b334a45a8ff	2633
bogdanm	0:9b334a45a8ff	2634	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2635	#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
bogdanm	0:9b334a45a8ff	2636
bogdanm	0:9b334a45a8ff	2637	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
bogdanm	0:9b334a45a8ff	2638	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
bogdanm	0:9b334a45a8ff	2639	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
bogdanm	0:9b334a45a8ff	2640	((VALUE) == RCC_PLLI2SP_DIV8))
bogdanm	0:9b334a45a8ff	2641
bogdanm	0:9b334a45a8ff	2642	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
bogdanm	0:9b334a45a8ff	2643
bogdanm	0:9b334a45a8ff	2644	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
bogdanm	0:9b334a45a8ff	2645	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
bogdanm	0:9b334a45a8ff	2646	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
bogdanm	0:9b334a45a8ff	2647	((VALUE) == RCC_PLLSAIP_DIV8))
bogdanm	0:9b334a45a8ff	2648
bogdanm	0:9b334a45a8ff	2649	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
bogdanm	0:9b334a45a8ff	2650	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
bogdanm	0:9b334a45a8ff	2651	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
bogdanm	0:9b334a45a8ff	2652	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
bogdanm	0:9b334a45a8ff	2653
bogdanm	0:9b334a45a8ff	2654	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
bogdanm	0:9b334a45a8ff	2655	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
bogdanm	0:9b334a45a8ff	2656	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
bogdanm	0:9b334a45a8ff	2657	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
bogdanm	0:9b334a45a8ff	2658
bogdanm	0:9b334a45a8ff	2659	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
bogdanm	0:9b334a45a8ff	2660	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
bogdanm	0:9b334a45a8ff	2661	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
bogdanm	0:9b334a45a8ff	2662	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
bogdanm	0:9b334a45a8ff	2663
bogdanm	0:9b334a45a8ff	2664	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
bogdanm	0:9b334a45a8ff	2665	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
bogdanm	0:9b334a45a8ff	2666	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
bogdanm	0:9b334a45a8ff	2667	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
bogdanm	0:9b334a45a8ff	2668
bogdanm	0:9b334a45a8ff	2669	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
bogdanm	0:9b334a45a8ff	2670	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
bogdanm	0:9b334a45a8ff	2671	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	2672
bogdanm	0:9b334a45a8ff	2673	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
bogdanm	0:9b334a45a8ff	2674	((SOURCE) == RCC_CECCLKSOURCE_LSE))
bogdanm	0:9b334a45a8ff	2675
bogdanm	0:9b334a45a8ff	2676	#define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) \|\|\
bogdanm	0:9b334a45a8ff	2677	((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
bogdanm	0:9b334a45a8ff	2678
bogdanm	0:9b334a45a8ff	2679	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) \|\|\
bogdanm	0:9b334a45a8ff	2680	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
bogdanm	0:9b334a45a8ff	2681
bogdanm	0:9b334a45a8ff	2682	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
bogdanm	0:9b334a45a8ff	2683	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
bogdanm	0:9b334a45a8ff	2684	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	2685
bogdanm	0:9b334a45a8ff	2686	/**
bogdanm	0:9b334a45a8ff	2687	* @}
bogdanm	0:9b334a45a8ff	2688	*/
bogdanm	0:9b334a45a8ff	2689
bogdanm	0:9b334a45a8ff	2690	/**
bogdanm	0:9b334a45a8ff	2691	* @}
bogdanm	0:9b334a45a8ff	2692	*/
bogdanm	0:9b334a45a8ff	2693
bogdanm	0:9b334a45a8ff	2694	/**
bogdanm	0:9b334a45a8ff	2695	* @}
bogdanm	0:9b334a45a8ff	2696	*/
bogdanm	0:9b334a45a8ff	2697
bogdanm	0:9b334a45a8ff	2698	/**
bogdanm	0:9b334a45a8ff	2699	* @}
bogdanm	0:9b334a45a8ff	2700	*/
bogdanm	0:9b334a45a8ff	2701	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	2702	}
bogdanm	0:9b334a45a8ff	2703	#endif
bogdanm	0:9b334a45a8ff	2704
bogdanm	0:9b334a45a8ff	2705	#endif /* __STM32F4xx_HAL_RCC_EX_H */
bogdanm	0:9b334a45a8ff	2706
bogdanm	0:9b334a45a8ff	2707	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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