mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 19:112740acecfa

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f4xx_hal_eth.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.3.2
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of ETH HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F4xx_HAL_ETH_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F4xx_HAL_ETH_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	#if defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	47	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	48	#include "stm32f4xx_hal_def.h"
bogdanm	0:9b334a45a8ff	49
bogdanm	0:9b334a45a8ff	50	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	51	* @{
bogdanm	0:9b334a45a8ff	52	*/
bogdanm	0:9b334a45a8ff	53
bogdanm	0:9b334a45a8ff	54	/** @addtogroup ETH
bogdanm	0:9b334a45a8ff	55	* @{
bogdanm	0:9b334a45a8ff	56	*/
bogdanm	0:9b334a45a8ff	57
bogdanm	0:9b334a45a8ff	58	/** @addtogroup ETH_Private_Macros
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
bogdanm	0:9b334a45a8ff	62	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	63	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
bogdanm	0:9b334a45a8ff	64	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
bogdanm	0:9b334a45a8ff	65	((SPEED) == ETH_SPEED_100M))
bogdanm	0:9b334a45a8ff	66	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
bogdanm	0:9b334a45a8ff	67	((MODE) == ETH_MODE_HALFDUPLEX))
bogdanm	0:9b334a45a8ff	68	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
bogdanm	0:9b334a45a8ff	69	((MODE) == ETH_RXINTERRUPT_MODE))
bogdanm	0:9b334a45a8ff	70	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
bogdanm	0:9b334a45a8ff	71	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
bogdanm	0:9b334a45a8ff	72	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
bogdanm	0:9b334a45a8ff	73	((MODE) == ETH_MEDIA_INTERFACE_RMII))
bogdanm	0:9b334a45a8ff	74	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	75	((CMD) == ETH_WATCHDOG_DISABLE))
bogdanm	0:9b334a45a8ff	76	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	77	((CMD) == ETH_JABBER_DISABLE))
bogdanm	0:9b334a45a8ff	78	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
bogdanm	0:9b334a45a8ff	79	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
bogdanm	0:9b334a45a8ff	80	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
bogdanm	0:9b334a45a8ff	81	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
bogdanm	0:9b334a45a8ff	82	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
bogdanm	0:9b334a45a8ff	83	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
bogdanm	0:9b334a45a8ff	84	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
bogdanm	0:9b334a45a8ff	85	((GAP) == ETH_INTERFRAMEGAP_40BIT))
bogdanm	0:9b334a45a8ff	86	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	87	((CMD) == ETH_CARRIERSENCE_DISABLE))
bogdanm	0:9b334a45a8ff	88	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	89	((CMD) == ETH_RECEIVEOWN_DISABLE))
bogdanm	0:9b334a45a8ff	90	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	91	((CMD) == ETH_LOOPBACKMODE_DISABLE))
bogdanm	0:9b334a45a8ff	92	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	93	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
bogdanm	0:9b334a45a8ff	94	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	95	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
bogdanm	0:9b334a45a8ff	96	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	97	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
bogdanm	0:9b334a45a8ff	98	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
bogdanm	0:9b334a45a8ff	99	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
bogdanm	0:9b334a45a8ff	100	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
bogdanm	0:9b334a45a8ff	101	((LIMIT) == ETH_BACKOFFLIMIT_1))
bogdanm	0:9b334a45a8ff	102	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	103	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
bogdanm	0:9b334a45a8ff	104	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	105	((CMD) == ETH_RECEIVEAll_DISABLE))
bogdanm	0:9b334a45a8ff	106	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	107	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	108	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
bogdanm	0:9b334a45a8ff	109	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
bogdanm	0:9b334a45a8ff	110	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
bogdanm	0:9b334a45a8ff	111	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
bogdanm	0:9b334a45a8ff	112	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	113	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
bogdanm	0:9b334a45a8ff	114	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
bogdanm	0:9b334a45a8ff	115	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
bogdanm	0:9b334a45a8ff	116	#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	117	((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
bogdanm	0:9b334a45a8ff	118	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
bogdanm	0:9b334a45a8ff	119	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
bogdanm	0:9b334a45a8ff	120	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
bogdanm	0:9b334a45a8ff	121	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
bogdanm	0:9b334a45a8ff	122	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
bogdanm	0:9b334a45a8ff	123	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
bogdanm	0:9b334a45a8ff	124	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
bogdanm	0:9b334a45a8ff	125	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
bogdanm	0:9b334a45a8ff	126	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	127	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
bogdanm	0:9b334a45a8ff	128	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
bogdanm	0:9b334a45a8ff	129	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
bogdanm	0:9b334a45a8ff	130	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
bogdanm	0:9b334a45a8ff	131	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
bogdanm	0:9b334a45a8ff	132	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	133	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
bogdanm	0:9b334a45a8ff	134	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	135	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
bogdanm	0:9b334a45a8ff	136	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	137	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
bogdanm	0:9b334a45a8ff	138	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
bogdanm	0:9b334a45a8ff	139	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
bogdanm	0:9b334a45a8ff	140	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
bogdanm	0:9b334a45a8ff	141	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
bogdanm	0:9b334a45a8ff	142	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
bogdanm	0:9b334a45a8ff	143	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
bogdanm	0:9b334a45a8ff	144	((ADDRESS) == ETH_MAC_ADDRESS3))
bogdanm	0:9b334a45a8ff	145	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
bogdanm	0:9b334a45a8ff	146	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
bogdanm	0:9b334a45a8ff	147	((ADDRESS) == ETH_MAC_ADDRESS3))
bogdanm	0:9b334a45a8ff	148	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
bogdanm	0:9b334a45a8ff	149	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
bogdanm	0:9b334a45a8ff	150	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
bogdanm	0:9b334a45a8ff	151	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
bogdanm	0:9b334a45a8ff	152	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
bogdanm	0:9b334a45a8ff	153	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
bogdanm	0:9b334a45a8ff	154	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
bogdanm	0:9b334a45a8ff	155	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
bogdanm	0:9b334a45a8ff	156	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	157	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
bogdanm	0:9b334a45a8ff	158	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	159	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
bogdanm	0:9b334a45a8ff	160	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	161	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
bogdanm	0:9b334a45a8ff	162	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	163	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
bogdanm	0:9b334a45a8ff	164	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
bogdanm	0:9b334a45a8ff	165	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
bogdanm	0:9b334a45a8ff	166	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
bogdanm	0:9b334a45a8ff	167	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
bogdanm	0:9b334a45a8ff	168	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
bogdanm	0:9b334a45a8ff	169	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
bogdanm	0:9b334a45a8ff	170	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
bogdanm	0:9b334a45a8ff	171	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
bogdanm	0:9b334a45a8ff	172	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	173	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
bogdanm	0:9b334a45a8ff	174	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	175	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
bogdanm	0:9b334a45a8ff	176	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
bogdanm	0:9b334a45a8ff	177	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
bogdanm	0:9b334a45a8ff	178	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
bogdanm	0:9b334a45a8ff	179	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
bogdanm	0:9b334a45a8ff	180	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	181	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
bogdanm	0:9b334a45a8ff	182	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	183	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
bogdanm	0:9b334a45a8ff	184	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	185	((CMD) == ETH_FIXEDBURST_DISABLE))
bogdanm	0:9b334a45a8ff	186	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
bogdanm	0:9b334a45a8ff	187	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
bogdanm	0:9b334a45a8ff	188	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
bogdanm	0:9b334a45a8ff	189	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
bogdanm	0:9b334a45a8ff	190	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
bogdanm	0:9b334a45a8ff	191	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
bogdanm	0:9b334a45a8ff	192	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
bogdanm	0:9b334a45a8ff	193	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
bogdanm	0:9b334a45a8ff	194	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
bogdanm	0:9b334a45a8ff	195	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
bogdanm	0:9b334a45a8ff	196	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
bogdanm	0:9b334a45a8ff	197	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
bogdanm	0:9b334a45a8ff	198	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
bogdanm	0:9b334a45a8ff	199	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
bogdanm	0:9b334a45a8ff	200	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
bogdanm	0:9b334a45a8ff	201	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
bogdanm	0:9b334a45a8ff	202	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
bogdanm	0:9b334a45a8ff	203	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
bogdanm	0:9b334a45a8ff	204	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
bogdanm	0:9b334a45a8ff	205	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
bogdanm	0:9b334a45a8ff	206	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
bogdanm	0:9b334a45a8ff	207	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
bogdanm	0:9b334a45a8ff	208	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
bogdanm	0:9b334a45a8ff	209	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
bogdanm	0:9b334a45a8ff	210	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
bogdanm	0:9b334a45a8ff	211	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
bogdanm	0:9b334a45a8ff	212	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
bogdanm	0:9b334a45a8ff	213	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
bogdanm	0:9b334a45a8ff	214	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
bogdanm	0:9b334a45a8ff	215	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
bogdanm	0:9b334a45a8ff	216	#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) \|\| \
bogdanm	0:9b334a45a8ff	217	((FLAG) == ETH_DMATXDESC_IC) \|\| \
bogdanm	0:9b334a45a8ff	218	((FLAG) == ETH_DMATXDESC_LS) \|\| \
bogdanm	0:9b334a45a8ff	219	((FLAG) == ETH_DMATXDESC_FS) \|\| \
bogdanm	0:9b334a45a8ff	220	((FLAG) == ETH_DMATXDESC_DC) \|\| \
bogdanm	0:9b334a45a8ff	221	((FLAG) == ETH_DMATXDESC_DP) \|\| \
bogdanm	0:9b334a45a8ff	222	((FLAG) == ETH_DMATXDESC_TTSE) \|\| \
bogdanm	0:9b334a45a8ff	223	((FLAG) == ETH_DMATXDESC_TER) \|\| \
bogdanm	0:9b334a45a8ff	224	((FLAG) == ETH_DMATXDESC_TCH) \|\| \
bogdanm	0:9b334a45a8ff	225	((FLAG) == ETH_DMATXDESC_TTSS) \|\| \
bogdanm	0:9b334a45a8ff	226	((FLAG) == ETH_DMATXDESC_IHE) \|\| \
bogdanm	0:9b334a45a8ff	227	((FLAG) == ETH_DMATXDESC_ES) \|\| \
bogdanm	0:9b334a45a8ff	228	((FLAG) == ETH_DMATXDESC_JT) \|\| \
bogdanm	0:9b334a45a8ff	229	((FLAG) == ETH_DMATXDESC_FF) \|\| \
bogdanm	0:9b334a45a8ff	230	((FLAG) == ETH_DMATXDESC_PCE) \|\| \
bogdanm	0:9b334a45a8ff	231	((FLAG) == ETH_DMATXDESC_LCA) \|\| \
bogdanm	0:9b334a45a8ff	232	((FLAG) == ETH_DMATXDESC_NC) \|\| \
bogdanm	0:9b334a45a8ff	233	((FLAG) == ETH_DMATXDESC_LCO) \|\| \
bogdanm	0:9b334a45a8ff	234	((FLAG) == ETH_DMATXDESC_EC) \|\| \
bogdanm	0:9b334a45a8ff	235	((FLAG) == ETH_DMATXDESC_VF) \|\| \
bogdanm	0:9b334a45a8ff	236	((FLAG) == ETH_DMATXDESC_CC) \|\| \
bogdanm	0:9b334a45a8ff	237	((FLAG) == ETH_DMATXDESC_ED) \|\| \
bogdanm	0:9b334a45a8ff	238	((FLAG) == ETH_DMATXDESC_UF) \|\| \
bogdanm	0:9b334a45a8ff	239	((FLAG) == ETH_DMATXDESC_DB))
bogdanm	0:9b334a45a8ff	240	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
bogdanm	0:9b334a45a8ff	241	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
bogdanm	0:9b334a45a8ff	242	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
bogdanm	0:9b334a45a8ff	243	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
bogdanm	0:9b334a45a8ff	244	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
bogdanm	0:9b334a45a8ff	245	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
bogdanm	0:9b334a45a8ff	246	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
bogdanm	0:9b334a45a8ff	247	#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) \|\| \
bogdanm	0:9b334a45a8ff	248	((FLAG) == ETH_DMARXDESC_AFM) \|\| \
bogdanm	0:9b334a45a8ff	249	((FLAG) == ETH_DMARXDESC_ES) \|\| \
bogdanm	0:9b334a45a8ff	250	((FLAG) == ETH_DMARXDESC_DE) \|\| \
bogdanm	0:9b334a45a8ff	251	((FLAG) == ETH_DMARXDESC_SAF) \|\| \
bogdanm	0:9b334a45a8ff	252	((FLAG) == ETH_DMARXDESC_LE) \|\| \
bogdanm	0:9b334a45a8ff	253	((FLAG) == ETH_DMARXDESC_OE) \|\| \
bogdanm	0:9b334a45a8ff	254	((FLAG) == ETH_DMARXDESC_VLAN) \|\| \
bogdanm	0:9b334a45a8ff	255	((FLAG) == ETH_DMARXDESC_FS) \|\| \
bogdanm	0:9b334a45a8ff	256	((FLAG) == ETH_DMARXDESC_LS) \|\| \
bogdanm	0:9b334a45a8ff	257	((FLAG) == ETH_DMARXDESC_IPV4HCE) \|\| \
bogdanm	0:9b334a45a8ff	258	((FLAG) == ETH_DMARXDESC_LC) \|\| \
bogdanm	0:9b334a45a8ff	259	((FLAG) == ETH_DMARXDESC_FT) \|\| \
bogdanm	0:9b334a45a8ff	260	((FLAG) == ETH_DMARXDESC_RWT) \|\| \
bogdanm	0:9b334a45a8ff	261	((FLAG) == ETH_DMARXDESC_RE) \|\| \
bogdanm	0:9b334a45a8ff	262	((FLAG) == ETH_DMARXDESC_DBE) \|\| \
bogdanm	0:9b334a45a8ff	263	((FLAG) == ETH_DMARXDESC_CE) \|\| \
bogdanm	0:9b334a45a8ff	264	((FLAG) == ETH_DMARXDESC_MAMPCE))
bogdanm	0:9b334a45a8ff	265	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
bogdanm	0:9b334a45a8ff	266	((BUFFER) == ETH_DMARXDESC_BUFFER2))
bogdanm	0:9b334a45a8ff	267	#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) \|\| \
bogdanm	0:9b334a45a8ff	268	((FLAG) == ETH_PMT_FLAG_MPR))
bogdanm	0:9b334a45a8ff	269	#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
bogdanm	0:9b334a45a8ff	270	#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) \|\| ((FLAG) == ETH_DMA_FLAG_PMT) \|\| \
bogdanm	0:9b334a45a8ff	271	((FLAG) == ETH_DMA_FLAG_MMC) \|\| ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) \|\| \
bogdanm	0:9b334a45a8ff	272	((FLAG) == ETH_DMA_FLAG_READWRITEERROR) \|\| ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) \|\| \
bogdanm	0:9b334a45a8ff	273	((FLAG) == ETH_DMA_FLAG_NIS) \|\| ((FLAG) == ETH_DMA_FLAG_AIS) \|\| \
bogdanm	0:9b334a45a8ff	274	((FLAG) == ETH_DMA_FLAG_ER) \|\| ((FLAG) == ETH_DMA_FLAG_FBE) \|\| \
bogdanm	0:9b334a45a8ff	275	((FLAG) == ETH_DMA_FLAG_ET) \|\| ((FLAG) == ETH_DMA_FLAG_RWT) \|\| \
bogdanm	0:9b334a45a8ff	276	((FLAG) == ETH_DMA_FLAG_RPS) \|\| ((FLAG) == ETH_DMA_FLAG_RBU) \|\| \
bogdanm	0:9b334a45a8ff	277	((FLAG) == ETH_DMA_FLAG_R) \|\| ((FLAG) == ETH_DMA_FLAG_TU) \|\| \
bogdanm	0:9b334a45a8ff	278	((FLAG) == ETH_DMA_FLAG_RO) \|\| ((FLAG) == ETH_DMA_FLAG_TJT) \|\| \
bogdanm	0:9b334a45a8ff	279	((FLAG) == ETH_DMA_FLAG_TBU) \|\| ((FLAG) == ETH_DMA_FLAG_TPS) \|\| \
bogdanm	0:9b334a45a8ff	280	((FLAG) == ETH_DMA_FLAG_T))
bogdanm	0:9b334a45a8ff	281	#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
bogdanm	0:9b334a45a8ff	282	#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) \|\| ((IT) == ETH_MAC_IT_MMCT) \|\| \
bogdanm	0:9b334a45a8ff	283	((IT) == ETH_MAC_IT_MMCR) \|\| ((IT) == ETH_MAC_IT_MMC) \|\| \
bogdanm	0:9b334a45a8ff	284	((IT) == ETH_MAC_IT_PMT))
bogdanm	0:9b334a45a8ff	285	#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) \|\| ((FLAG) == ETH_MAC_FLAG_MMCT) \|\| \
bogdanm	0:9b334a45a8ff	286	((FLAG) == ETH_MAC_FLAG_MMCR) \|\| ((FLAG) == ETH_MAC_FLAG_MMC) \|\| \
bogdanm	0:9b334a45a8ff	287	((FLAG) == ETH_MAC_FLAG_PMT))
bogdanm	0:9b334a45a8ff	288	#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
bogdanm	0:9b334a45a8ff	289	#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) \|\| ((IT) == ETH_DMA_IT_PMT) \|\| \
bogdanm	0:9b334a45a8ff	290	((IT) == ETH_DMA_IT_MMC) \|\| ((IT) == ETH_DMA_IT_NIS) \|\| \
bogdanm	0:9b334a45a8ff	291	((IT) == ETH_DMA_IT_AIS) \|\| ((IT) == ETH_DMA_IT_ER) \|\| \
bogdanm	0:9b334a45a8ff	292	((IT) == ETH_DMA_IT_FBE) \|\| ((IT) == ETH_DMA_IT_ET) \|\| \
bogdanm	0:9b334a45a8ff	293	((IT) == ETH_DMA_IT_RWT) \|\| ((IT) == ETH_DMA_IT_RPS) \|\| \
bogdanm	0:9b334a45a8ff	294	((IT) == ETH_DMA_IT_RBU) \|\| ((IT) == ETH_DMA_IT_R) \|\| \
bogdanm	0:9b334a45a8ff	295	((IT) == ETH_DMA_IT_TU) \|\| ((IT) == ETH_DMA_IT_RO) \|\| \
bogdanm	0:9b334a45a8ff	296	((IT) == ETH_DMA_IT_TJT) \|\| ((IT) == ETH_DMA_IT_TBU) \|\| \
bogdanm	0:9b334a45a8ff	297	((IT) == ETH_DMA_IT_TPS) \|\| ((IT) == ETH_DMA_IT_T))
bogdanm	0:9b334a45a8ff	298	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
bogdanm	0:9b334a45a8ff	299	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
bogdanm	0:9b334a45a8ff	300	#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) \|\| (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
bogdanm	0:9b334a45a8ff	301	((IT) != 0x00))
bogdanm	0:9b334a45a8ff	302	#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) \|\| ((IT) == ETH_MMC_IT_TGFMSC) \|\| \
bogdanm	0:9b334a45a8ff	303	((IT) == ETH_MMC_IT_TGFSC) \|\| ((IT) == ETH_MMC_IT_RGUF) \|\| \
bogdanm	0:9b334a45a8ff	304	((IT) == ETH_MMC_IT_RFAE) \|\| ((IT) == ETH_MMC_IT_RFCE))
bogdanm	0:9b334a45a8ff	305	#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	306	((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
bogdanm	0:9b334a45a8ff	307
bogdanm	0:9b334a45a8ff	308
bogdanm	0:9b334a45a8ff	309	/**
bogdanm	0:9b334a45a8ff	310	* @}
bogdanm	0:9b334a45a8ff	311	*/
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	/** @addtogroup ETH_Private_Defines
bogdanm	0:9b334a45a8ff	314	* @{
bogdanm	0:9b334a45a8ff	315	*/
bogdanm	0:9b334a45a8ff	316	/* Delay to wait when writing to some Ethernet registers */
bogdanm	0:9b334a45a8ff	317	#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319	/* ETHERNET Errors */
bogdanm	0:9b334a45a8ff	320	#define ETH_SUCCESS ((uint32_t)0)
bogdanm	0:9b334a45a8ff	321	#define ETH_ERROR ((uint32_t)1)
bogdanm	0:9b334a45a8ff	322
bogdanm	0:9b334a45a8ff	323	/* ETHERNET DMA Tx descriptors Collision Count Shift */
bogdanm	0:9b334a45a8ff	324	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
bogdanm	0:9b334a45a8ff	325
bogdanm	0:9b334a45a8ff	326	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
bogdanm	0:9b334a45a8ff	327	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	/* ETHERNET DMA Rx descriptors Frame Length Shift */
bogdanm	0:9b334a45a8ff	330	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
bogdanm	0:9b334a45a8ff	333	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	/* ETHERNET DMA Rx descriptors Frame length Shift */
bogdanm	0:9b334a45a8ff	336	#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	/* ETHERNET MAC address offsets */
bogdanm	0:9b334a45a8ff	339	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
bogdanm	0:9b334a45a8ff	340	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	/* ETHERNET MACMIIAR register Mask */
bogdanm	0:9b334a45a8ff	343	#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	/* ETHERNET MACCR register Mask */
bogdanm	0:9b334a45a8ff	346	#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	/* ETHERNET MACFCR register Mask */
bogdanm	0:9b334a45a8ff	349	#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	/* ETHERNET DMAOMR register Mask */
bogdanm	0:9b334a45a8ff	352	#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
bogdanm	0:9b334a45a8ff	353
bogdanm	0:9b334a45a8ff	354	/* ETHERNET Remote Wake-up frame register length */
bogdanm	0:9b334a45a8ff	355	#define ETH_WAKEUP_REGISTER_LENGTH 8
bogdanm	0:9b334a45a8ff	356
bogdanm	0:9b334a45a8ff	357	/* ETHERNET Missed frames counter Shift */
bogdanm	0:9b334a45a8ff	358	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
bogdanm	0:9b334a45a8ff	359	/**
bogdanm	0:9b334a45a8ff	360	* @}
bogdanm	0:9b334a45a8ff	361	*/
bogdanm	0:9b334a45a8ff	362
bogdanm	0:9b334a45a8ff	363	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	364	/** @defgroup ETH_Exported_Types ETH Exported Types
bogdanm	0:9b334a45a8ff	365	* @{
bogdanm	0:9b334a45a8ff	366	*/
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/**
bogdanm	0:9b334a45a8ff	369	* @brief HAL State structures definition
bogdanm	0:9b334a45a8ff	370	*/
bogdanm	0:9b334a45a8ff	371	typedef enum
bogdanm	0:9b334a45a8ff	372	{
bogdanm	0:9b334a45a8ff	373	HAL_ETH_STATE_RESET = 0x00, /!< Peripheral not yet Initialized or disabled /
bogdanm	0:9b334a45a8ff	374	HAL_ETH_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	0:9b334a45a8ff	375	HAL_ETH_STATE_BUSY = 0x02, /!< an internal process is ongoing /
bogdanm	0:9b334a45a8ff	376	HAL_ETH_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
bogdanm	0:9b334a45a8ff	377	HAL_ETH_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
bogdanm	0:9b334a45a8ff	378	HAL_ETH_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
bogdanm	0:9b334a45a8ff	379	HAL_ETH_STATE_BUSY_WR = 0x42, /!< Write process is ongoing /
bogdanm	0:9b334a45a8ff	380	HAL_ETH_STATE_BUSY_RD = 0x82, /!< Read process is ongoing /
bogdanm	0:9b334a45a8ff	381	HAL_ETH_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	0:9b334a45a8ff	382	HAL_ETH_STATE_ERROR = 0x04 /!< Reception process is ongoing /
bogdanm	0:9b334a45a8ff	383	}HAL_ETH_StateTypeDef;
bogdanm	0:9b334a45a8ff	384
bogdanm	0:9b334a45a8ff	385	/**
bogdanm	0:9b334a45a8ff	386	* @brief ETH Init Structure definition
bogdanm	0:9b334a45a8ff	387	*/
bogdanm	0:9b334a45a8ff	388
bogdanm	0:9b334a45a8ff	389	typedef struct
bogdanm	0:9b334a45a8ff	390	{
bogdanm	0:9b334a45a8ff	391	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
bogdanm	0:9b334a45a8ff	392	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
bogdanm	0:9b334a45a8ff	393	and the mode (half/full-duplex).
bogdanm	0:9b334a45a8ff	394	This parameter can be a value of @ref ETH_AutoNegotiation */
bogdanm	0:9b334a45a8ff	395
bogdanm	0:9b334a45a8ff	396	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
bogdanm	0:9b334a45a8ff	397	This parameter can be a value of @ref ETH_Speed */
bogdanm	0:9b334a45a8ff	398
bogdanm	0:9b334a45a8ff	399	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
bogdanm	0:9b334a45a8ff	400	This parameter can be a value of @ref ETH_Duplex_Mode */
bogdanm	0:9b334a45a8ff	401
bogdanm	0:9b334a45a8ff	402	uint16_t PhyAddress; /*!< Ethernet PHY address.
bogdanm	0:9b334a45a8ff	403	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
bogdanm	0:9b334a45a8ff	404
bogdanm	0:9b334a45a8ff	405	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
bogdanm	0:9b334a45a8ff	406
bogdanm	0:9b334a45a8ff	407	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
bogdanm	0:9b334a45a8ff	408	This parameter can be a value of @ref ETH_Rx_Mode */
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
bogdanm	0:9b334a45a8ff	411	This parameter can be a value of @ref ETH_Checksum_Mode */
bogdanm	0:9b334a45a8ff	412
bogdanm	0:9b334a45a8ff	413	uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
bogdanm	0:9b334a45a8ff	414	This parameter can be a value of @ref ETH_Media_Interface */
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416	} ETH_InitTypeDef;
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418
bogdanm	0:9b334a45a8ff	419	/**
bogdanm	0:9b334a45a8ff	420	* @brief ETH MAC Configuration Structure definition
bogdanm	0:9b334a45a8ff	421	*/
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	typedef struct
bogdanm	0:9b334a45a8ff	424	{
bogdanm	0:9b334a45a8ff	425	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
bogdanm	0:9b334a45a8ff	426	When enabled, the MAC allows no more then 2048 bytes to be received.
bogdanm	0:9b334a45a8ff	427	When disabled, the MAC can receive up to 16384 bytes.
bogdanm	0:9b334a45a8ff	428	This parameter can be a value of @ref ETH_Watchdog */
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	uint32_t Jabber; /*!< Selects or not Jabber timer
bogdanm	0:9b334a45a8ff	431	When enabled, the MAC allows no more then 2048 bytes to be sent.
bogdanm	0:9b334a45a8ff	432	When disabled, the MAC can send up to 16384 bytes.
bogdanm	0:9b334a45a8ff	433	This parameter can be a value of @ref ETH_Jabber */
bogdanm	0:9b334a45a8ff	434
bogdanm	0:9b334a45a8ff	435	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
bogdanm	0:9b334a45a8ff	436	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
bogdanm	0:9b334a45a8ff	437
bogdanm	0:9b334a45a8ff	438	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
bogdanm	0:9b334a45a8ff	439	This parameter can be a value of @ref ETH_Carrier_Sense */
bogdanm	0:9b334a45a8ff	440
bogdanm	0:9b334a45a8ff	441	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
bogdanm	0:9b334a45a8ff	442	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
bogdanm	0:9b334a45a8ff	443	in Half-Duplex mode.
bogdanm	0:9b334a45a8ff	444	This parameter can be a value of @ref ETH_Receive_Own */
bogdanm	0:9b334a45a8ff	445
bogdanm	0:9b334a45a8ff	446	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
bogdanm	0:9b334a45a8ff	447	This parameter can be a value of @ref ETH_Loop_Back_Mode */
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
bogdanm	0:9b334a45a8ff	450	This parameter can be a value of @ref ETH_Checksum_Offload */
bogdanm	0:9b334a45a8ff	451
bogdanm	0:9b334a45a8ff	452	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
bogdanm	0:9b334a45a8ff	453	when a collision occurs (Half-Duplex mode).
bogdanm	0:9b334a45a8ff	454	This parameter can be a value of @ref ETH_Retry_Transmission */
bogdanm	0:9b334a45a8ff	455
bogdanm	0:9b334a45a8ff	456	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
bogdanm	0:9b334a45a8ff	457	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
bogdanm	0:9b334a45a8ff	460	This parameter can be a value of @ref ETH_Back_Off_Limit */
bogdanm	0:9b334a45a8ff	461
bogdanm	0:9b334a45a8ff	462	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
bogdanm	0:9b334a45a8ff	463	This parameter can be a value of @ref ETH_Deferral_Check */
bogdanm	0:9b334a45a8ff	464
bogdanm	0:9b334a45a8ff	465	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
bogdanm	0:9b334a45a8ff	466	This parameter can be a value of @ref ETH_Receive_All */
bogdanm	0:9b334a45a8ff	467
bogdanm	0:9b334a45a8ff	468	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
bogdanm	0:9b334a45a8ff	469	This parameter can be a value of @ref ETH_Source_Addr_Filter */
bogdanm	0:9b334a45a8ff	470
bogdanm	0:9b334a45a8ff	471	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
bogdanm	0:9b334a45a8ff	472	This parameter can be a value of @ref ETH_Pass_Control_Frames */
bogdanm	0:9b334a45a8ff	473
bogdanm	0:9b334a45a8ff	474	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
bogdanm	0:9b334a45a8ff	475	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
bogdanm	0:9b334a45a8ff	476
bogdanm	0:9b334a45a8ff	477	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
bogdanm	0:9b334a45a8ff	478	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
bogdanm	0:9b334a45a8ff	479
bogdanm	0:9b334a45a8ff	480	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
bogdanm	0:9b334a45a8ff	481	This parameter can be a value of @ref ETH_Promiscuous_Mode */
bogdanm	0:9b334a45a8ff	482
bogdanm	0:9b334a45a8ff	483	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
bogdanm	0:9b334a45a8ff	484	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
bogdanm	0:9b334a45a8ff	485
bogdanm	0:9b334a45a8ff	486	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
bogdanm	0:9b334a45a8ff	487	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
bogdanm	0:9b334a45a8ff	488
bogdanm	0:9b334a45a8ff	489	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
bogdanm	0:9b334a45a8ff	490	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
bogdanm	0:9b334a45a8ff	491
bogdanm	0:9b334a45a8ff	492	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
bogdanm	0:9b334a45a8ff	493	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
bogdanm	0:9b334a45a8ff	496	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	497
bogdanm	0:9b334a45a8ff	498	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
bogdanm	0:9b334a45a8ff	499	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
bogdanm	0:9b334a45a8ff	500
bogdanm	0:9b334a45a8ff	501	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
bogdanm	0:9b334a45a8ff	502	automatic retransmission of PAUSE Frame.
bogdanm	0:9b334a45a8ff	503	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
bogdanm	0:9b334a45a8ff	504
bogdanm	0:9b334a45a8ff	505	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
bogdanm	0:9b334a45a8ff	506	unicast address and unique multicast address).
bogdanm	0:9b334a45a8ff	507	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
bogdanm	0:9b334a45a8ff	508
bogdanm	0:9b334a45a8ff	509	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
bogdanm	0:9b334a45a8ff	510	disable its transmitter for a specified time (Pause Time)
bogdanm	0:9b334a45a8ff	511	This parameter can be a value of @ref ETH_Receive_Flow_Control */
bogdanm	0:9b334a45a8ff	512
bogdanm	0:9b334a45a8ff	513	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
bogdanm	0:9b334a45a8ff	514	or the MAC back-pressure operation (Half-Duplex mode)
bogdanm	0:9b334a45a8ff	515	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
bogdanm	0:9b334a45a8ff	518	comparison and filtering.
bogdanm	0:9b334a45a8ff	519	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	} ETH_MACInitTypeDef;
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	/**
bogdanm	0:9b334a45a8ff	527	* @brief ETH DMA Configuration Structure definition
bogdanm	0:9b334a45a8ff	528	*/
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	typedef struct
bogdanm	0:9b334a45a8ff	531	{
bogdanm	0:9b334a45a8ff	532	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
bogdanm	0:9b334a45a8ff	533	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
bogdanm	0:9b334a45a8ff	534
bogdanm	0:9b334a45a8ff	535	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
bogdanm	0:9b334a45a8ff	536	This parameter can be a value of @ref ETH_Receive_Store_Forward */
bogdanm	0:9b334a45a8ff	537
bogdanm	0:9b334a45a8ff	538	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
bogdanm	0:9b334a45a8ff	539	This parameter can be a value of @ref ETH_Flush_Received_Frame */
bogdanm	0:9b334a45a8ff	540
bogdanm	0:9b334a45a8ff	541	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
bogdanm	0:9b334a45a8ff	542	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
bogdanm	0:9b334a45a8ff	545	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
bogdanm	0:9b334a45a8ff	546
bogdanm	0:9b334a45a8ff	547	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
bogdanm	0:9b334a45a8ff	548	This parameter can be a value of @ref ETH_Forward_Error_Frames */
bogdanm	0:9b334a45a8ff	549
bogdanm	0:9b334a45a8ff	550	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
bogdanm	0:9b334a45a8ff	551	and length less than 64 bytes) including pad-bytes and CRC)
bogdanm	0:9b334a45a8ff	552	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
bogdanm	0:9b334a45a8ff	555	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
bogdanm	0:9b334a45a8ff	558	frame of Transmit data even before obtaining the status for the first frame.
bogdanm	0:9b334a45a8ff	559	This parameter can be a value of @ref ETH_Second_Frame_Operate */
bogdanm	0:9b334a45a8ff	560
bogdanm	0:9b334a45a8ff	561	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
bogdanm	0:9b334a45a8ff	562	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
bogdanm	0:9b334a45a8ff	563
bogdanm	0:9b334a45a8ff	564	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
bogdanm	0:9b334a45a8ff	565	This parameter can be a value of @ref ETH_Fixed_Burst */
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
bogdanm	0:9b334a45a8ff	568	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
bogdanm	0:9b334a45a8ff	569
bogdanm	0:9b334a45a8ff	570	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
bogdanm	0:9b334a45a8ff	571	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
bogdanm	0:9b334a45a8ff	572
bogdanm	0:9b334a45a8ff	573	uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
bogdanm	0:9b334a45a8ff	574	This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
bogdanm	0:9b334a45a8ff	575
bogdanm	0:9b334a45a8ff	576	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
bogdanm	0:9b334a45a8ff	577	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
bogdanm	0:9b334a45a8ff	578
bogdanm	0:9b334a45a8ff	579	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
bogdanm	0:9b334a45a8ff	580	This parameter can be a value of @ref ETH_DMA_Arbitration */
bogdanm	0:9b334a45a8ff	581	} ETH_DMAInitTypeDef;
bogdanm	0:9b334a45a8ff	582
bogdanm	0:9b334a45a8ff	583
bogdanm	0:9b334a45a8ff	584	/**
bogdanm	0:9b334a45a8ff	585	* @brief ETH DMA Descriptors data structure definition
bogdanm	0:9b334a45a8ff	586	*/
bogdanm	0:9b334a45a8ff	587
bogdanm	0:9b334a45a8ff	588	typedef struct
bogdanm	0:9b334a45a8ff	589	{
bogdanm	0:9b334a45a8ff	590	__IO uint32_t Status; /!< Status /
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
bogdanm	0:9b334a45a8ff	593
bogdanm	0:9b334a45a8ff	594	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
bogdanm	0:9b334a45a8ff	595
bogdanm	0:9b334a45a8ff	596	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
bogdanm	0:9b334a45a8ff	597
bogdanm	0:9b334a45a8ff	598	/!< Enhanced ETHERNET DMA PTP Descriptors /
bogdanm	0:9b334a45a8ff	599	uint32_t ExtendedStatus; /!< Extended status for PTP receive descriptor /
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	uint32_t Reserved1; /!< Reserved /
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	uint32_t TimeStampLow; /!< Time Stamp Low value for transmit and receive /
bogdanm	0:9b334a45a8ff	604
bogdanm	0:9b334a45a8ff	605	uint32_t TimeStampHigh; /!< Time Stamp High value for transmit and receive /
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	} ETH_DMADescTypeDef;
bogdanm	0:9b334a45a8ff	608
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	/**
bogdanm	0:9b334a45a8ff	611	* @brief Received Frame Informations structure definition
bogdanm	0:9b334a45a8ff	612	*/
bogdanm	0:9b334a45a8ff	613	typedef struct
bogdanm	0:9b334a45a8ff	614	{
bogdanm	0:9b334a45a8ff	615	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
bogdanm	0:9b334a45a8ff	618
bogdanm	0:9b334a45a8ff	619	uint32_t SegCount; /!< Segment count /
bogdanm	0:9b334a45a8ff	620
bogdanm	0:9b334a45a8ff	621	uint32_t length; /!< Frame length /
bogdanm	0:9b334a45a8ff	622
bogdanm	0:9b334a45a8ff	623	uint32_t buffer; /!< Frame buffer /
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625	} ETH_DMARxFrameInfos;
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627
bogdanm	0:9b334a45a8ff	628	/**
bogdanm	0:9b334a45a8ff	629	* @brief ETH Handle Structure definition
bogdanm	0:9b334a45a8ff	630	*/
bogdanm	0:9b334a45a8ff	631
bogdanm	0:9b334a45a8ff	632	typedef struct
bogdanm	0:9b334a45a8ff	633	{
bogdanm	0:9b334a45a8ff	634	ETH_TypeDef Instance; /!< Register base address */
bogdanm	0:9b334a45a8ff	635
bogdanm	0:9b334a45a8ff	636	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
bogdanm	0:9b334a45a8ff	637
bogdanm	0:9b334a45a8ff	638	uint32_t LinkStatus; /!< Ethernet link status /
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
bogdanm	0:9b334a45a8ff	641
bogdanm	0:9b334a45a8ff	642	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
bogdanm	0:9b334a45a8ff	645
bogdanm	0:9b334a45a8ff	646	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	HAL_LockTypeDef Lock; /!< ETH Lock /
bogdanm	0:9b334a45a8ff	649
bogdanm	0:9b334a45a8ff	650	} ETH_HandleTypeDef;
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/**
bogdanm	0:9b334a45a8ff	653	* @}
bogdanm	0:9b334a45a8ff	654	*/
bogdanm	0:9b334a45a8ff	655
bogdanm	0:9b334a45a8ff	656	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	657	/** @defgroup ETH_Exported_Constants ETH Exported Constants
bogdanm	0:9b334a45a8ff	658	* @{
bogdanm	0:9b334a45a8ff	659	*/
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	/** @defgroup ETH_Buffers_setting ETH Buffers setting
bogdanm	0:9b334a45a8ff	662	* @{
bogdanm	0:9b334a45a8ff	663	*/
bogdanm	0:9b334a45a8ff	664	#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC /
bogdanm	0:9b334a45a8ff	665	#define ETH_HEADER ((uint32_t)14) /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
bogdanm	0:9b334a45a8ff	666	#define ETH_CRC ((uint32_t)4) /!< Ethernet CRC /
bogdanm	0:9b334a45a8ff	667	#define ETH_EXTRA ((uint32_t)2) /!< Extra bytes in some cases /
bogdanm	0:9b334a45a8ff	668	#define ETH_VLAN_TAG ((uint32_t)4) /!< optional 802.1q VLAN Tag /
bogdanm	0:9b334a45a8ff	669	#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /!< Minimum Ethernet payload size /
bogdanm	0:9b334a45a8ff	670	#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /!< Maximum Ethernet payload size /
bogdanm	0:9b334a45a8ff	671	#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /!< Jumbo frame payload size /
bogdanm	0:9b334a45a8ff	672
bogdanm	0:9b334a45a8ff	673	/* Ethernet driver receive buffers are organized in a chained linked-list, when
bogdanm	0:9b334a45a8ff	674	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
bogdanm	0:9b334a45a8ff	675	to the driver receive buffers memory.
bogdanm	0:9b334a45a8ff	676
bogdanm	0:9b334a45a8ff	677	Depending on the size of the received ethernet packet and the size of
bogdanm	0:9b334a45a8ff	678	each ethernet driver receive buffer, the received packet can take one or more
bogdanm	0:9b334a45a8ff	679	ethernet driver receive buffer.
bogdanm	0:9b334a45a8ff	680
bogdanm	0:9b334a45a8ff	681	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
bogdanm	0:9b334a45a8ff	682	and the total count of the driver receive buffers ETH_RXBUFNB.
bogdanm	0:9b334a45a8ff	683
bogdanm	0:9b334a45a8ff	684	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
bogdanm	0:9b334a45a8ff	685	example, they can be reconfigured in the application layer to fit the application
bogdanm	0:9b334a45a8ff	686	needs */
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
bogdanm	0:9b334a45a8ff	689	packet */
bogdanm	0:9b334a45a8ff	690	#ifndef ETH_RX_BUF_SIZE
bogdanm	0:9b334a45a8ff	691	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
bogdanm	0:9b334a45a8ff	692	#endif
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
bogdanm	0:9b334a45a8ff	695	#ifndef ETH_RXBUFNB
bogdanm	0:9b334a45a8ff	696	#define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
bogdanm	0:9b334a45a8ff	697	#endif
bogdanm	0:9b334a45a8ff	698
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
bogdanm	0:9b334a45a8ff	701	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
bogdanm	0:9b334a45a8ff	702	driver transmit buffers memory to the TxFIFO.
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	Depending on the size of the Ethernet packet to be transmitted and the size of
bogdanm	0:9b334a45a8ff	705	each ethernet driver transmit buffer, the packet to be transmitted can take
bogdanm	0:9b334a45a8ff	706	one or more ethernet driver transmit buffer.
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
bogdanm	0:9b334a45a8ff	709	and the total count of the driver transmit buffers ETH_TXBUFNB.
bogdanm	0:9b334a45a8ff	710
bogdanm	0:9b334a45a8ff	711	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
bogdanm	0:9b334a45a8ff	712	example, they can be reconfigured in the application layer to fit the application
bogdanm	0:9b334a45a8ff	713	needs */
bogdanm	0:9b334a45a8ff	714
bogdanm	0:9b334a45a8ff	715	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
bogdanm	0:9b334a45a8ff	716	packet */
bogdanm	0:9b334a45a8ff	717	#ifndef ETH_TX_BUF_SIZE
bogdanm	0:9b334a45a8ff	718	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
bogdanm	0:9b334a45a8ff	719	#endif
bogdanm	0:9b334a45a8ff	720
bogdanm	0:9b334a45a8ff	721	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
bogdanm	0:9b334a45a8ff	722	#ifndef ETH_TXBUFNB
bogdanm	0:9b334a45a8ff	723	#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
bogdanm	0:9b334a45a8ff	724	#endif
bogdanm	0:9b334a45a8ff	725
bogdanm	0:9b334a45a8ff	726	/**
bogdanm	0:9b334a45a8ff	727	* @}
bogdanm	0:9b334a45a8ff	728	*/
bogdanm	0:9b334a45a8ff	729
bogdanm	0:9b334a45a8ff	730	/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
bogdanm	0:9b334a45a8ff	731	* @{
bogdanm	0:9b334a45a8ff	732	*/
bogdanm	0:9b334a45a8ff	733
bogdanm	0:9b334a45a8ff	734	/*
bogdanm	0:9b334a45a8ff	735	DMA Tx Descriptor
bogdanm	0:9b334a45a8ff	736	-----------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	737	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
bogdanm	0:9b334a45a8ff	738	-----------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	739	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
bogdanm	0:9b334a45a8ff	740	-----------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	741	TDES2 \| Buffer1 Address [31:0] \|
bogdanm	0:9b334a45a8ff	742	-----------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	743	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
bogdanm	0:9b334a45a8ff	744	-----------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	745	*/
bogdanm	0:9b334a45a8ff	746
bogdanm	0:9b334a45a8ff	747	/**
bogdanm	0:9b334a45a8ff	748	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
bogdanm	0:9b334a45a8ff	749	*/
bogdanm	0:9b334a45a8ff	750	#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
bogdanm	0:9b334a45a8ff	751	#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /!< Interrupt on Completion /
bogdanm	0:9b334a45a8ff	752	#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /!< Last Segment /
bogdanm	0:9b334a45a8ff	753	#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /!< First Segment /
bogdanm	0:9b334a45a8ff	754	#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /!< Disable CRC /
bogdanm	0:9b334a45a8ff	755	#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /!< Disable Padding /
bogdanm	0:9b334a45a8ff	756	#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /!< Transmit Time Stamp Enable /
bogdanm	0:9b334a45a8ff	757	#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /!< Checksum Insertion Control: 4 cases /
bogdanm	0:9b334a45a8ff	758	#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /!< Do Nothing: Checksum Engine is bypassed /
bogdanm	0:9b334a45a8ff	759	#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /!< IPV4 header Checksum Insertion /
bogdanm	0:9b334a45a8ff	760	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
bogdanm	0:9b334a45a8ff	761	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
bogdanm	0:9b334a45a8ff	762	#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /!< Transmit End of Ring /
bogdanm	0:9b334a45a8ff	763	#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /!< Second Address Chained /
bogdanm	0:9b334a45a8ff	764	#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /!< Tx Time Stamp Status /
bogdanm	0:9b334a45a8ff	765	#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /!< IP Header Error /
bogdanm	0:9b334a45a8ff	766	#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
bogdanm	0:9b334a45a8ff	767	#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /!< Jabber Timeout /
bogdanm	0:9b334a45a8ff	768	#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
bogdanm	0:9b334a45a8ff	769	#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /!< Payload Checksum Error /
bogdanm	0:9b334a45a8ff	770	#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /!< Loss of Carrier: carrier lost during transmission /
bogdanm	0:9b334a45a8ff	771	#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /!< No Carrier: no carrier signal from the transceiver /
bogdanm	0:9b334a45a8ff	772	#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /!< Late Collision: transmission aborted due to collision /
bogdanm	0:9b334a45a8ff	773	#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /!< Excessive Collision: transmission aborted after 16 collisions /
bogdanm	0:9b334a45a8ff	774	#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /!< VLAN Frame /
bogdanm	0:9b334a45a8ff	775	#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /!< Collision Count /
bogdanm	0:9b334a45a8ff	776	#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /!< Excessive Deferral /
bogdanm	0:9b334a45a8ff	777	#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /!< Underflow Error: late data arrival from the memory /
bogdanm	0:9b334a45a8ff	778	#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /!< Deferred Bit /
bogdanm	0:9b334a45a8ff	779
bogdanm	0:9b334a45a8ff	780	/**
bogdanm	0:9b334a45a8ff	781	* @brief Bit definition of TDES1 register
bogdanm	0:9b334a45a8ff	782	*/
bogdanm	0:9b334a45a8ff	783	#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /!< Transmit Buffer2 Size /
bogdanm	0:9b334a45a8ff	784	#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /!< Transmit Buffer1 Size /
bogdanm	0:9b334a45a8ff	785
bogdanm	0:9b334a45a8ff	786	/**
bogdanm	0:9b334a45a8ff	787	* @brief Bit definition of TDES2 register
bogdanm	0:9b334a45a8ff	788	*/
bogdanm	0:9b334a45a8ff	789	#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
bogdanm	0:9b334a45a8ff	790
bogdanm	0:9b334a45a8ff	791	/**
bogdanm	0:9b334a45a8ff	792	* @brief Bit definition of TDES3 register
bogdanm	0:9b334a45a8ff	793	*/
bogdanm	0:9b334a45a8ff	794	#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
bogdanm	0:9b334a45a8ff	795
bogdanm	0:9b334a45a8ff	796	/*---------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	797	TDES6 \| Transmit Time Stamp Low [31:0] \|
bogdanm	0:9b334a45a8ff	798	-----------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	799	TDES7 \| Transmit Time Stamp High [31:0] \|
bogdanm	0:9b334a45a8ff	800	----------------------------------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	801
bogdanm	0:9b334a45a8ff	802	/* Bit definition of TDES6 register */
bogdanm	0:9b334a45a8ff	803	#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
bogdanm	0:9b334a45a8ff	804
bogdanm	0:9b334a45a8ff	805	/* Bit definition of TDES7 register */
bogdanm	0:9b334a45a8ff	806	#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
bogdanm	0:9b334a45a8ff	807
bogdanm	0:9b334a45a8ff	808	/**
bogdanm	0:9b334a45a8ff	809	* @}
bogdanm	0:9b334a45a8ff	810	*/
bogdanm	0:9b334a45a8ff	811	/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
bogdanm	0:9b334a45a8ff	812	* @{
bogdanm	0:9b334a45a8ff	813	*/
bogdanm	0:9b334a45a8ff	814
bogdanm	0:9b334a45a8ff	815	/*
bogdanm	0:9b334a45a8ff	816	DMA Rx Descriptor
bogdanm	0:9b334a45a8ff	817	--------------------------------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	818	RDES0 \| OWN(31) \| Status [30:0] \|
bogdanm	0:9b334a45a8ff	819	---------------------------------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	820	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
bogdanm	0:9b334a45a8ff	821	---------------------------------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	822	RDES2 \| Buffer1 Address [31:0] \|
bogdanm	0:9b334a45a8ff	823	---------------------------------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	824	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
bogdanm	0:9b334a45a8ff	825	---------------------------------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	826	*/
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	/**
bogdanm	0:9b334a45a8ff	829	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
bogdanm	0:9b334a45a8ff	830	*/
bogdanm	0:9b334a45a8ff	831	#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
bogdanm	0:9b334a45a8ff	832	#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /!< DA Filter Fail for the rx frame /
bogdanm	0:9b334a45a8ff	833	#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /!< Receive descriptor frame length /
bogdanm	0:9b334a45a8ff	834	#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
bogdanm	0:9b334a45a8ff	835	#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /!< Descriptor error: no more descriptors for receive frame /
bogdanm	0:9b334a45a8ff	836	#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /!< SA Filter Fail for the received frame /
bogdanm	0:9b334a45a8ff	837	#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /!< Frame size not matching with length field /
bogdanm	0:9b334a45a8ff	838	#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /!< Overflow Error: Frame was damaged due to buffer overflow /
bogdanm	0:9b334a45a8ff	839	#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /!< VLAN Tag: received frame is a VLAN frame /
bogdanm	0:9b334a45a8ff	840	#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /!< First descriptor of the frame /
bogdanm	0:9b334a45a8ff	841	#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /!< Last descriptor of the frame /
bogdanm	0:9b334a45a8ff	842	#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /!< IPC Checksum Error: Rx Ipv4 header checksum error /
bogdanm	0:9b334a45a8ff	843	#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /!< Late collision occurred during reception /
bogdanm	0:9b334a45a8ff	844	#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /!< Frame type - Ethernet, otherwise 802.3 /
bogdanm	0:9b334a45a8ff	845	#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /!< Receive Watchdog Timeout: watchdog timer expired during reception /
bogdanm	0:9b334a45a8ff	846	#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /!< Receive error: error reported by MII interface /
bogdanm	0:9b334a45a8ff	847	#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /!< Dribble bit error: frame contains non int multiple of 8 bits /
bogdanm	0:9b334a45a8ff	848	#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /!< CRC error /
bogdanm	0:9b334a45a8ff	849	#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
bogdanm	0:9b334a45a8ff	850
bogdanm	0:9b334a45a8ff	851	/**
bogdanm	0:9b334a45a8ff	852	* @brief Bit definition of RDES1 register
bogdanm	0:9b334a45a8ff	853	*/
bogdanm	0:9b334a45a8ff	854	#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /!< Disable Interrupt on Completion /
bogdanm	0:9b334a45a8ff	855	#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /!< Receive Buffer2 Size /
bogdanm	0:9b334a45a8ff	856	#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /!< Receive End of Ring /
bogdanm	0:9b334a45a8ff	857	#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /!< Second Address Chained /
bogdanm	0:9b334a45a8ff	858	#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /!< Receive Buffer1 Size /
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	/**
bogdanm	0:9b334a45a8ff	861	* @brief Bit definition of RDES2 register
bogdanm	0:9b334a45a8ff	862	*/
bogdanm	0:9b334a45a8ff	863	#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	/**
bogdanm	0:9b334a45a8ff	866	* @brief Bit definition of RDES3 register
bogdanm	0:9b334a45a8ff	867	*/
bogdanm	0:9b334a45a8ff	868	#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
bogdanm	0:9b334a45a8ff	869
bogdanm	0:9b334a45a8ff	870	/*---------------------------------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	871	RDES4 \| Reserved[31:15] \| Extended Status [14:0] \|
bogdanm	0:9b334a45a8ff	872	---------------------------------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	873	RDES5 \| Reserved[31:0] \|
bogdanm	0:9b334a45a8ff	874	---------------------------------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	875	RDES6 \| Receive Time Stamp Low [31:0] \|
bogdanm	0:9b334a45a8ff	876	---------------------------------------------------------------------------------------------------------------------
bogdanm	0:9b334a45a8ff	877	RDES7 \| Receive Time Stamp High [31:0] \|
bogdanm	0:9b334a45a8ff	878	--------------------------------------------------------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	879
bogdanm	0:9b334a45a8ff	880	/* Bit definition of RDES4 register */
bogdanm	0:9b334a45a8ff	881	#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
bogdanm	0:9b334a45a8ff	882	#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
bogdanm	0:9b334a45a8ff	883	#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
bogdanm	0:9b334a45a8ff	884	#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
bogdanm	0:9b334a45a8ff	885	#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
bogdanm	0:9b334a45a8ff	886	#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
bogdanm	0:9b334a45a8ff	887	#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
bogdanm	0:9b334a45a8ff	888	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
bogdanm	0:9b334a45a8ff	889	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
bogdanm	0:9b334a45a8ff	890	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
bogdanm	0:9b334a45a8ff	891	#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
bogdanm	0:9b334a45a8ff	892	#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
bogdanm	0:9b334a45a8ff	893	#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
bogdanm	0:9b334a45a8ff	894	#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
bogdanm	0:9b334a45a8ff	895	#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
bogdanm	0:9b334a45a8ff	896	#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
bogdanm	0:9b334a45a8ff	897	#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
bogdanm	0:9b334a45a8ff	898	#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
bogdanm	0:9b334a45a8ff	899	#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
bogdanm	0:9b334a45a8ff	900
bogdanm	0:9b334a45a8ff	901	/* Bit definition of RDES6 register */
bogdanm	0:9b334a45a8ff	902	#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	/* Bit definition of RDES7 register */
bogdanm	0:9b334a45a8ff	905	#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
bogdanm	0:9b334a45a8ff	906	/**
bogdanm	0:9b334a45a8ff	907	* @}
bogdanm	0:9b334a45a8ff	908	*/
bogdanm	0:9b334a45a8ff	909	/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
bogdanm	0:9b334a45a8ff	910	* @{
bogdanm	0:9b334a45a8ff	911	*/
bogdanm	0:9b334a45a8ff	912	#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	913	#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	914
bogdanm	0:9b334a45a8ff	915	/**
bogdanm	0:9b334a45a8ff	916	* @}
bogdanm	0:9b334a45a8ff	917	*/
bogdanm	0:9b334a45a8ff	918	/** @defgroup ETH_Speed ETH Speed
bogdanm	0:9b334a45a8ff	919	* @{
bogdanm	0:9b334a45a8ff	920	*/
bogdanm	0:9b334a45a8ff	921	#define ETH_SPEED_10M ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	922	#define ETH_SPEED_100M ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	923
bogdanm	0:9b334a45a8ff	924	/**
bogdanm	0:9b334a45a8ff	925	* @}
bogdanm	0:9b334a45a8ff	926	*/
bogdanm	0:9b334a45a8ff	927	/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
bogdanm	0:9b334a45a8ff	928	* @{
bogdanm	0:9b334a45a8ff	929	*/
bogdanm	0:9b334a45a8ff	930	#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	931	#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	932	/**
bogdanm	0:9b334a45a8ff	933	* @}
bogdanm	0:9b334a45a8ff	934	*/
bogdanm	0:9b334a45a8ff	935	/** @defgroup ETH_Rx_Mode ETH Rx Mode
bogdanm	0:9b334a45a8ff	936	* @{
bogdanm	0:9b334a45a8ff	937	*/
bogdanm	0:9b334a45a8ff	938	#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	939	#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	940	/**
bogdanm	0:9b334a45a8ff	941	* @}
bogdanm	0:9b334a45a8ff	942	*/
bogdanm	0:9b334a45a8ff	943
bogdanm	0:9b334a45a8ff	944	/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
bogdanm	0:9b334a45a8ff	945	* @{
bogdanm	0:9b334a45a8ff	946	*/
bogdanm	0:9b334a45a8ff	947	#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	948	#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	949	/**
bogdanm	0:9b334a45a8ff	950	* @}
bogdanm	0:9b334a45a8ff	951	*/
bogdanm	0:9b334a45a8ff	952
bogdanm	0:9b334a45a8ff	953	/** @defgroup ETH_Media_Interface ETH Media Interface
bogdanm	0:9b334a45a8ff	954	* @{
bogdanm	0:9b334a45a8ff	955	*/
bogdanm	0:9b334a45a8ff	956	#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	957	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
bogdanm	0:9b334a45a8ff	958	/**
bogdanm	0:9b334a45a8ff	959	* @}
bogdanm	0:9b334a45a8ff	960	*/
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	/** @defgroup ETH_Watchdog ETH Watchdog
bogdanm	0:9b334a45a8ff	963	* @{
bogdanm	0:9b334a45a8ff	964	*/
bogdanm	0:9b334a45a8ff	965	#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	966	#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	967	/**
bogdanm	0:9b334a45a8ff	968	* @}
bogdanm	0:9b334a45a8ff	969	*/
bogdanm	0:9b334a45a8ff	970
bogdanm	0:9b334a45a8ff	971	/** @defgroup ETH_Jabber ETH Jabber
bogdanm	0:9b334a45a8ff	972	* @{
bogdanm	0:9b334a45a8ff	973	*/
bogdanm	0:9b334a45a8ff	974	#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	975	#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	976	/**
bogdanm	0:9b334a45a8ff	977	* @}
bogdanm	0:9b334a45a8ff	978	*/
bogdanm	0:9b334a45a8ff	979
bogdanm	0:9b334a45a8ff	980	/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
bogdanm	0:9b334a45a8ff	981	* @{
bogdanm	0:9b334a45a8ff	982	*/
bogdanm	0:9b334a45a8ff	983	#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /!< minimum IFG between frames during transmission is 96Bit /
bogdanm	0:9b334a45a8ff	984	#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /!< minimum IFG between frames during transmission is 88Bit /
bogdanm	0:9b334a45a8ff	985	#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /!< minimum IFG between frames during transmission is 80Bit /
bogdanm	0:9b334a45a8ff	986	#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /!< minimum IFG between frames during transmission is 72Bit /
bogdanm	0:9b334a45a8ff	987	#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /!< minimum IFG between frames during transmission is 64Bit /
bogdanm	0:9b334a45a8ff	988	#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /!< minimum IFG between frames during transmission is 56Bit /
bogdanm	0:9b334a45a8ff	989	#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /!< minimum IFG between frames during transmission is 48Bit /
bogdanm	0:9b334a45a8ff	990	#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /!< minimum IFG between frames during transmission is 40Bit /
bogdanm	0:9b334a45a8ff	991	/**
bogdanm	0:9b334a45a8ff	992	* @}
bogdanm	0:9b334a45a8ff	993	*/
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995	/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
bogdanm	0:9b334a45a8ff	996	* @{
bogdanm	0:9b334a45a8ff	997	*/
bogdanm	0:9b334a45a8ff	998	#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	999	#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	1000	/**
bogdanm	0:9b334a45a8ff	1001	* @}
bogdanm	0:9b334a45a8ff	1002	*/
bogdanm	0:9b334a45a8ff	1003
bogdanm	0:9b334a45a8ff	1004	/** @defgroup ETH_Receive_Own ETH Receive Own
bogdanm	0:9b334a45a8ff	1005	* @{
bogdanm	0:9b334a45a8ff	1006	*/
bogdanm	0:9b334a45a8ff	1007	#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1008	#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	1009	/**
bogdanm	0:9b334a45a8ff	1010	* @}
bogdanm	0:9b334a45a8ff	1011	*/
bogdanm	0:9b334a45a8ff	1012
bogdanm	0:9b334a45a8ff	1013	/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
bogdanm	0:9b334a45a8ff	1014	* @{
bogdanm	0:9b334a45a8ff	1015	*/
bogdanm	0:9b334a45a8ff	1016	#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	1017	#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1018	/**
bogdanm	0:9b334a45a8ff	1019	* @}
bogdanm	0:9b334a45a8ff	1020	*/
bogdanm	0:9b334a45a8ff	1021
bogdanm	0:9b334a45a8ff	1022	/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
bogdanm	0:9b334a45a8ff	1023	* @{
bogdanm	0:9b334a45a8ff	1024	*/
bogdanm	0:9b334a45a8ff	1025	#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	1026	#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1027	/**
bogdanm	0:9b334a45a8ff	1028	* @}
bogdanm	0:9b334a45a8ff	1029	*/
bogdanm	0:9b334a45a8ff	1030
bogdanm	0:9b334a45a8ff	1031	/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
bogdanm	0:9b334a45a8ff	1032	* @{
bogdanm	0:9b334a45a8ff	1033	*/
bogdanm	0:9b334a45a8ff	1034	#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1035	#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1036	/**
bogdanm	0:9b334a45a8ff	1037	* @}
bogdanm	0:9b334a45a8ff	1038	*/
bogdanm	0:9b334a45a8ff	1039
bogdanm	0:9b334a45a8ff	1040	/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
bogdanm	0:9b334a45a8ff	1041	* @{
bogdanm	0:9b334a45a8ff	1042	*/
bogdanm	0:9b334a45a8ff	1043	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1044	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1045	/**
bogdanm	0:9b334a45a8ff	1046	* @}
bogdanm	0:9b334a45a8ff	1047	*/
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
bogdanm	0:9b334a45a8ff	1050	* @{
bogdanm	0:9b334a45a8ff	1051	*/
bogdanm	0:9b334a45a8ff	1052	#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1053	#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1054	#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1055	#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
bogdanm	0:9b334a45a8ff	1056	/**
bogdanm	0:9b334a45a8ff	1057	* @}
bogdanm	0:9b334a45a8ff	1058	*/
bogdanm	0:9b334a45a8ff	1059
bogdanm	0:9b334a45a8ff	1060	/** @defgroup ETH_Deferral_Check ETH Deferral Check
bogdanm	0:9b334a45a8ff	1061	* @{
bogdanm	0:9b334a45a8ff	1062	*/
bogdanm	0:9b334a45a8ff	1063	#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1064	#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1065	/**
bogdanm	0:9b334a45a8ff	1066	* @}
bogdanm	0:9b334a45a8ff	1067	*/
bogdanm	0:9b334a45a8ff	1068
bogdanm	0:9b334a45a8ff	1069	/** @defgroup ETH_Receive_All ETH Receive All
bogdanm	0:9b334a45a8ff	1070	* @{
bogdanm	0:9b334a45a8ff	1071	*/
bogdanm	0:9b334a45a8ff	1072	#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	1073	#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1074	/**
bogdanm	0:9b334a45a8ff	1075	* @}
bogdanm	0:9b334a45a8ff	1076	*/
bogdanm	0:9b334a45a8ff	1077
bogdanm	0:9b334a45a8ff	1078	/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
bogdanm	0:9b334a45a8ff	1079	* @{
bogdanm	0:9b334a45a8ff	1080	*/
bogdanm	0:9b334a45a8ff	1081	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	1082	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	1083	#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1084	/**
bogdanm	0:9b334a45a8ff	1085	* @}
bogdanm	0:9b334a45a8ff	1086	*/
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088	/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
bogdanm	0:9b334a45a8ff	1089	* @{
bogdanm	0:9b334a45a8ff	1090	*/
bogdanm	0:9b334a45a8ff	1091	#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /!< MAC filters all control frames from reaching the application /
bogdanm	0:9b334a45a8ff	1092	#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /!< MAC forwards all control frames to application even if they fail the Address Filter /
bogdanm	0:9b334a45a8ff	1093	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /!< MAC forwards control frames that pass the Address Filter. /
bogdanm	0:9b334a45a8ff	1094	/**
bogdanm	0:9b334a45a8ff	1095	* @}
bogdanm	0:9b334a45a8ff	1096	*/
bogdanm	0:9b334a45a8ff	1097
bogdanm	0:9b334a45a8ff	1098	/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
bogdanm	0:9b334a45a8ff	1099	* @{
bogdanm	0:9b334a45a8ff	1100	*/
bogdanm	0:9b334a45a8ff	1101	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1102	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	1103	/**
bogdanm	0:9b334a45a8ff	1104	* @}
bogdanm	0:9b334a45a8ff	1105	*/
bogdanm	0:9b334a45a8ff	1106
bogdanm	0:9b334a45a8ff	1107	/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
bogdanm	0:9b334a45a8ff	1108	* @{
bogdanm	0:9b334a45a8ff	1109	*/
bogdanm	0:9b334a45a8ff	1110	#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1111	#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1112	/**
bogdanm	0:9b334a45a8ff	1113	* @}
bogdanm	0:9b334a45a8ff	1114	*/
bogdanm	0:9b334a45a8ff	1115
bogdanm	0:9b334a45a8ff	1116	/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
bogdanm	0:9b334a45a8ff	1117	* @{
bogdanm	0:9b334a45a8ff	1118	*/
bogdanm	0:9b334a45a8ff	1119	#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	1120	#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1121	/**
bogdanm	0:9b334a45a8ff	1122	* @}
bogdanm	0:9b334a45a8ff	1123	*/
bogdanm	0:9b334a45a8ff	1124
bogdanm	0:9b334a45a8ff	1125	/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
bogdanm	0:9b334a45a8ff	1126	* @{
bogdanm	0:9b334a45a8ff	1127	*/
bogdanm	0:9b334a45a8ff	1128	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
bogdanm	0:9b334a45a8ff	1129	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1130	#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1131	#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1132	/**
bogdanm	0:9b334a45a8ff	1133	* @}
bogdanm	0:9b334a45a8ff	1134	*/
bogdanm	0:9b334a45a8ff	1135
bogdanm	0:9b334a45a8ff	1136	/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
bogdanm	0:9b334a45a8ff	1137	* @{
bogdanm	0:9b334a45a8ff	1138	*/
bogdanm	0:9b334a45a8ff	1139	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
bogdanm	0:9b334a45a8ff	1140	#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1141	#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1142	/**
bogdanm	0:9b334a45a8ff	1143	* @}
bogdanm	0:9b334a45a8ff	1144	*/
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146	/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
bogdanm	0:9b334a45a8ff	1147	* @{
bogdanm	0:9b334a45a8ff	1148	*/
bogdanm	0:9b334a45a8ff	1149	#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1150	#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1151	/**
bogdanm	0:9b334a45a8ff	1152	* @}
bogdanm	0:9b334a45a8ff	1153	*/
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
bogdanm	0:9b334a45a8ff	1156	* @{
bogdanm	0:9b334a45a8ff	1157	*/
bogdanm	0:9b334a45a8ff	1158	#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /!< Pause time minus 4 slot times /
bogdanm	0:9b334a45a8ff	1159	#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /!< Pause time minus 28 slot times /
bogdanm	0:9b334a45a8ff	1160	#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /!< Pause time minus 144 slot times /
bogdanm	0:9b334a45a8ff	1161	#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /!< Pause time minus 256 slot times /
bogdanm	0:9b334a45a8ff	1162	/**
bogdanm	0:9b334a45a8ff	1163	* @}
bogdanm	0:9b334a45a8ff	1164	*/
bogdanm	0:9b334a45a8ff	1165
bogdanm	0:9b334a45a8ff	1166	/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
bogdanm	0:9b334a45a8ff	1167	* @{
bogdanm	0:9b334a45a8ff	1168	*/
bogdanm	0:9b334a45a8ff	1169	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1170	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1171	/**
bogdanm	0:9b334a45a8ff	1172	* @}
bogdanm	0:9b334a45a8ff	1173	*/
bogdanm	0:9b334a45a8ff	1174
bogdanm	0:9b334a45a8ff	1175	/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
bogdanm	0:9b334a45a8ff	1176	* @{
bogdanm	0:9b334a45a8ff	1177	*/
bogdanm	0:9b334a45a8ff	1178	#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1179	#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1180	/**
bogdanm	0:9b334a45a8ff	1181	* @}
bogdanm	0:9b334a45a8ff	1182	*/
bogdanm	0:9b334a45a8ff	1183
bogdanm	0:9b334a45a8ff	1184	/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
bogdanm	0:9b334a45a8ff	1185	* @{
bogdanm	0:9b334a45a8ff	1186	*/
bogdanm	0:9b334a45a8ff	1187	#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1188	#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1189	/**
bogdanm	0:9b334a45a8ff	1190	* @}
bogdanm	0:9b334a45a8ff	1191	*/
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
bogdanm	0:9b334a45a8ff	1194	* @{
bogdanm	0:9b334a45a8ff	1195	*/
bogdanm	0:9b334a45a8ff	1196	#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	1197	#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1198	/**
bogdanm	0:9b334a45a8ff	1199	* @}
bogdanm	0:9b334a45a8ff	1200	*/
bogdanm	0:9b334a45a8ff	1201
bogdanm	0:9b334a45a8ff	1202	/** @defgroup ETH_MAC_addresses ETH MAC addresses
bogdanm	0:9b334a45a8ff	1203	* @{
bogdanm	0:9b334a45a8ff	1204	*/
bogdanm	0:9b334a45a8ff	1205	#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1206	#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1207	#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	1208	#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
bogdanm	0:9b334a45a8ff	1209	/**
bogdanm	0:9b334a45a8ff	1210	* @}
bogdanm	0:9b334a45a8ff	1211	*/
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
bogdanm	0:9b334a45a8ff	1214	* @{
bogdanm	0:9b334a45a8ff	1215	*/
bogdanm	0:9b334a45a8ff	1216	#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1217	#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	1218	/**
bogdanm	0:9b334a45a8ff	1219	* @}
bogdanm	0:9b334a45a8ff	1220	*/
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
bogdanm	0:9b334a45a8ff	1223	* @{
bogdanm	0:9b334a45a8ff	1224	*/
bogdanm	0:9b334a45a8ff	1225	#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /!< Mask MAC Address high reg bits [15:8] /
bogdanm	0:9b334a45a8ff	1226	#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /!< Mask MAC Address high reg bits [7:0] /
bogdanm	0:9b334a45a8ff	1227	#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /!< Mask MAC Address low reg bits [31:24] /
bogdanm	0:9b334a45a8ff	1228	#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /!< Mask MAC Address low reg bits [23:16] /
bogdanm	0:9b334a45a8ff	1229	#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /!< Mask MAC Address low reg bits [15:8] /
bogdanm	0:9b334a45a8ff	1230	#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /!< Mask MAC Address low reg bits [70] /
bogdanm	0:9b334a45a8ff	1231	/**
bogdanm	0:9b334a45a8ff	1232	* @}
bogdanm	0:9b334a45a8ff	1233	*/
bogdanm	0:9b334a45a8ff	1234
bogdanm	0:9b334a45a8ff	1235	/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
bogdanm	0:9b334a45a8ff	1236	* @{
bogdanm	0:9b334a45a8ff	1237	*/
bogdanm	0:9b334a45a8ff	1238	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
bogdanm	0:9b334a45a8ff	1239	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
bogdanm	0:9b334a45a8ff	1240	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
bogdanm	0:9b334a45a8ff	1241	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
bogdanm	0:9b334a45a8ff	1242	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
bogdanm	0:9b334a45a8ff	1243	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
bogdanm	0:9b334a45a8ff	1244	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
bogdanm	0:9b334a45a8ff	1245	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
bogdanm	0:9b334a45a8ff	1246	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
bogdanm	0:9b334a45a8ff	1247	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
bogdanm	0:9b334a45a8ff	1248	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
bogdanm	0:9b334a45a8ff	1249	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
bogdanm	0:9b334a45a8ff	1250	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
bogdanm	0:9b334a45a8ff	1251	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
bogdanm	0:9b334a45a8ff	1252	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
bogdanm	0:9b334a45a8ff	1253	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
bogdanm	0:9b334a45a8ff	1254	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
bogdanm	0:9b334a45a8ff	1255	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
bogdanm	0:9b334a45a8ff	1256	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
bogdanm	0:9b334a45a8ff	1257	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
bogdanm	0:9b334a45a8ff	1258	#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
bogdanm	0:9b334a45a8ff	1259	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
bogdanm	0:9b334a45a8ff	1260	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
bogdanm	0:9b334a45a8ff	1261	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
bogdanm	0:9b334a45a8ff	1262	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
bogdanm	0:9b334a45a8ff	1263	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
bogdanm	0:9b334a45a8ff	1264	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
bogdanm	0:9b334a45a8ff	1265	/**
bogdanm	0:9b334a45a8ff	1266	* @}
bogdanm	0:9b334a45a8ff	1267	*/
bogdanm	0:9b334a45a8ff	1268
bogdanm	0:9b334a45a8ff	1269	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
bogdanm	0:9b334a45a8ff	1270	* @{
bogdanm	0:9b334a45a8ff	1271	*/
bogdanm	0:9b334a45a8ff	1272	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1273	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	1274	/**
bogdanm	0:9b334a45a8ff	1275	* @}
bogdanm	0:9b334a45a8ff	1276	*/
bogdanm	0:9b334a45a8ff	1277
bogdanm	0:9b334a45a8ff	1278	/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
bogdanm	0:9b334a45a8ff	1279	* @{
bogdanm	0:9b334a45a8ff	1280	*/
bogdanm	0:9b334a45a8ff	1281	#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	1282	#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1283	/**
bogdanm	0:9b334a45a8ff	1284	* @}
bogdanm	0:9b334a45a8ff	1285	*/
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
bogdanm	0:9b334a45a8ff	1288	* @{
bogdanm	0:9b334a45a8ff	1289	*/
bogdanm	0:9b334a45a8ff	1290	#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1291	#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	1292	/**
bogdanm	0:9b334a45a8ff	1293	* @}
bogdanm	0:9b334a45a8ff	1294	*/
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
bogdanm	0:9b334a45a8ff	1297	* @{
bogdanm	0:9b334a45a8ff	1298	*/
bogdanm	0:9b334a45a8ff	1299	#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	1300	#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1301	/**
bogdanm	0:9b334a45a8ff	1302	* @}
bogdanm	0:9b334a45a8ff	1303	*/
bogdanm	0:9b334a45a8ff	1304
bogdanm	0:9b334a45a8ff	1305	/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
bogdanm	0:9b334a45a8ff	1306	* @{
bogdanm	0:9b334a45a8ff	1307	*/
bogdanm	0:9b334a45a8ff	1308	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
bogdanm	0:9b334a45a8ff	1309	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
bogdanm	0:9b334a45a8ff	1310	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
bogdanm	0:9b334a45a8ff	1311	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
bogdanm	0:9b334a45a8ff	1312	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
bogdanm	0:9b334a45a8ff	1313	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
bogdanm	0:9b334a45a8ff	1314	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
bogdanm	0:9b334a45a8ff	1315	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
bogdanm	0:9b334a45a8ff	1316	/**
bogdanm	0:9b334a45a8ff	1317	* @}
bogdanm	0:9b334a45a8ff	1318	*/
bogdanm	0:9b334a45a8ff	1319
bogdanm	0:9b334a45a8ff	1320	/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
bogdanm	0:9b334a45a8ff	1321	* @{
bogdanm	0:9b334a45a8ff	1322	*/
bogdanm	0:9b334a45a8ff	1323	#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1324	#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1325	/**
bogdanm	0:9b334a45a8ff	1326	* @}
bogdanm	0:9b334a45a8ff	1327	*/
bogdanm	0:9b334a45a8ff	1328
bogdanm	0:9b334a45a8ff	1329	/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
bogdanm	0:9b334a45a8ff	1330	* @{
bogdanm	0:9b334a45a8ff	1331	*/
bogdanm	0:9b334a45a8ff	1332	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	1333	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1334	/**
bogdanm	0:9b334a45a8ff	1335	* @}
bogdanm	0:9b334a45a8ff	1336	*/
bogdanm	0:9b334a45a8ff	1337
bogdanm	0:9b334a45a8ff	1338	/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
bogdanm	0:9b334a45a8ff	1339	* @{
bogdanm	0:9b334a45a8ff	1340	*/
bogdanm	0:9b334a45a8ff	1341	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Receive FIFO is 64 Bytes /
bogdanm	0:9b334a45a8ff	1342	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /!< threshold level of the MTL Receive FIFO is 32 Bytes /
bogdanm	0:9b334a45a8ff	1343	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /!< threshold level of the MTL Receive FIFO is 96 Bytes /
bogdanm	0:9b334a45a8ff	1344	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /!< threshold level of the MTL Receive FIFO is 128 Bytes /
bogdanm	0:9b334a45a8ff	1345	/**
bogdanm	0:9b334a45a8ff	1346	* @}
bogdanm	0:9b334a45a8ff	1347	*/
bogdanm	0:9b334a45a8ff	1348
bogdanm	0:9b334a45a8ff	1349	/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
bogdanm	0:9b334a45a8ff	1350	* @{
bogdanm	0:9b334a45a8ff	1351	*/
bogdanm	0:9b334a45a8ff	1352	#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	1353	#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1354	/**
bogdanm	0:9b334a45a8ff	1355	* @}
bogdanm	0:9b334a45a8ff	1356	*/
bogdanm	0:9b334a45a8ff	1357
bogdanm	0:9b334a45a8ff	1358	/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
bogdanm	0:9b334a45a8ff	1359	* @{
bogdanm	0:9b334a45a8ff	1360	*/
bogdanm	0:9b334a45a8ff	1361	#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	1362	#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1363	/**
bogdanm	0:9b334a45a8ff	1364	* @}
bogdanm	0:9b334a45a8ff	1365	*/
bogdanm	0:9b334a45a8ff	1366
bogdanm	0:9b334a45a8ff	1367	/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
bogdanm	0:9b334a45a8ff	1368	* @{
bogdanm	0:9b334a45a8ff	1369	*/
bogdanm	0:9b334a45a8ff	1370	#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	1371	#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1372	/**
bogdanm	0:9b334a45a8ff	1373	* @}
bogdanm	0:9b334a45a8ff	1374	*/
bogdanm	0:9b334a45a8ff	1375
bogdanm	0:9b334a45a8ff	1376	/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
bogdanm	0:9b334a45a8ff	1377	* @{
bogdanm	0:9b334a45a8ff	1378	*/
bogdanm	0:9b334a45a8ff	1379	#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
bogdanm	0:9b334a45a8ff	1380	#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
bogdanm	0:9b334a45a8ff	1381	#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
bogdanm	0:9b334a45a8ff	1382	#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
bogdanm	0:9b334a45a8ff	1383	#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
bogdanm	0:9b334a45a8ff	1384	#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
bogdanm	0:9b334a45a8ff	1385	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
bogdanm	0:9b334a45a8ff	1386	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
bogdanm	0:9b334a45a8ff	1387	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
bogdanm	0:9b334a45a8ff	1388	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
bogdanm	0:9b334a45a8ff	1389	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
bogdanm	0:9b334a45a8ff	1390	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
bogdanm	0:9b334a45a8ff	1391	/**
bogdanm	0:9b334a45a8ff	1392	* @}
bogdanm	0:9b334a45a8ff	1393	*/
bogdanm	0:9b334a45a8ff	1394
bogdanm	0:9b334a45a8ff	1395	/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
bogdanm	0:9b334a45a8ff	1396	* @{
bogdanm	0:9b334a45a8ff	1397	*/
bogdanm	0:9b334a45a8ff	1398	#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
bogdanm	0:9b334a45a8ff	1399	#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
bogdanm	0:9b334a45a8ff	1400	#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
bogdanm	0:9b334a45a8ff	1401	#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
bogdanm	0:9b334a45a8ff	1402	#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
bogdanm	0:9b334a45a8ff	1403	#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
bogdanm	0:9b334a45a8ff	1404	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
bogdanm	0:9b334a45a8ff	1405	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
bogdanm	0:9b334a45a8ff	1406	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
bogdanm	0:9b334a45a8ff	1407	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
bogdanm	0:9b334a45a8ff	1408	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
bogdanm	0:9b334a45a8ff	1409	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
bogdanm	0:9b334a45a8ff	1410	/**
bogdanm	0:9b334a45a8ff	1411	* @}
bogdanm	0:9b334a45a8ff	1412	*/
bogdanm	0:9b334a45a8ff	1413
bogdanm	0:9b334a45a8ff	1414	/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
bogdanm	0:9b334a45a8ff	1415	* @{
bogdanm	0:9b334a45a8ff	1416	*/
bogdanm	0:9b334a45a8ff	1417	#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	1418	#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1419	/**
bogdanm	0:9b334a45a8ff	1420	* @}
bogdanm	0:9b334a45a8ff	1421	*/
bogdanm	0:9b334a45a8ff	1422
bogdanm	0:9b334a45a8ff	1423	/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
bogdanm	0:9b334a45a8ff	1424	* @{
bogdanm	0:9b334a45a8ff	1425	*/
bogdanm	0:9b334a45a8ff	1426	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	1427	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	1428	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	1429	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
bogdanm	0:9b334a45a8ff	1430	#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	1431	/**
bogdanm	0:9b334a45a8ff	1432	* @}
bogdanm	0:9b334a45a8ff	1433	*/
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
bogdanm	0:9b334a45a8ff	1436	* @{
bogdanm	0:9b334a45a8ff	1437	*/
bogdanm	0:9b334a45a8ff	1438	#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /!< Last Segment /
bogdanm	0:9b334a45a8ff	1439	#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /!< First Segment /
bogdanm	0:9b334a45a8ff	1440	/**
bogdanm	0:9b334a45a8ff	1441	* @}
bogdanm	0:9b334a45a8ff	1442	*/
bogdanm	0:9b334a45a8ff	1443
bogdanm	0:9b334a45a8ff	1444	/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
bogdanm	0:9b334a45a8ff	1445	* @{
bogdanm	0:9b334a45a8ff	1446	*/
bogdanm	0:9b334a45a8ff	1447	#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /!< Checksum engine bypass /
bogdanm	0:9b334a45a8ff	1448	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /!< IPv4 header checksum insertion /
bogdanm	0:9b334a45a8ff	1449	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
bogdanm	0:9b334a45a8ff	1450	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
bogdanm	0:9b334a45a8ff	1451	/**
bogdanm	0:9b334a45a8ff	1452	* @}
bogdanm	0:9b334a45a8ff	1453	*/
bogdanm	0:9b334a45a8ff	1454
bogdanm	0:9b334a45a8ff	1455	/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
bogdanm	0:9b334a45a8ff	1456	* @{
bogdanm	0:9b334a45a8ff	1457	*/
bogdanm	0:9b334a45a8ff	1458	#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /!< DMA Rx Desc Buffer1 /
bogdanm	0:9b334a45a8ff	1459	#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /!< DMA Rx Desc Buffer2 /
bogdanm	0:9b334a45a8ff	1460	/**
bogdanm	0:9b334a45a8ff	1461	* @}
bogdanm	0:9b334a45a8ff	1462	*/
bogdanm	0:9b334a45a8ff	1463
bogdanm	0:9b334a45a8ff	1464	/** @defgroup ETH_PMT_Flags ETH PMT Flags
bogdanm	0:9b334a45a8ff	1465	* @{
bogdanm	0:9b334a45a8ff	1466	*/
bogdanm	0:9b334a45a8ff	1467	#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /!< Wake-Up Frame Filter Register Pointer Reset /
bogdanm	0:9b334a45a8ff	1468	#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /!< Wake-Up Frame Received /
bogdanm	0:9b334a45a8ff	1469	#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /!< Magic Packet Received /
bogdanm	0:9b334a45a8ff	1470	/**
bogdanm	0:9b334a45a8ff	1471	* @}
bogdanm	0:9b334a45a8ff	1472	*/
bogdanm	0:9b334a45a8ff	1473
bogdanm	0:9b334a45a8ff	1474	/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
bogdanm	0:9b334a45a8ff	1475	* @{
bogdanm	0:9b334a45a8ff	1476	*/
bogdanm	0:9b334a45a8ff	1477	#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /!< When Tx good frame counter reaches half the maximum value /
bogdanm	0:9b334a45a8ff	1478	#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /!< When Tx good multi col counter reaches half the maximum value /
bogdanm	0:9b334a45a8ff	1479	#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /!< When Tx good single col counter reaches half the maximum value /
bogdanm	0:9b334a45a8ff	1480	/**
bogdanm	0:9b334a45a8ff	1481	* @}
bogdanm	0:9b334a45a8ff	1482	*/
bogdanm	0:9b334a45a8ff	1483
bogdanm	0:9b334a45a8ff	1484	/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
bogdanm	0:9b334a45a8ff	1485	* @{
bogdanm	0:9b334a45a8ff	1486	*/
bogdanm	0:9b334a45a8ff	1487	#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /!< When Rx good unicast frames counter reaches half the maximum value /
bogdanm	0:9b334a45a8ff	1488	#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /!< When Rx alignment error counter reaches half the maximum value /
bogdanm	0:9b334a45a8ff	1489	#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /!< When Rx crc error counter reaches half the maximum value /
bogdanm	0:9b334a45a8ff	1490	/**
bogdanm	0:9b334a45a8ff	1491	* @}
bogdanm	0:9b334a45a8ff	1492	*/
bogdanm	0:9b334a45a8ff	1493
bogdanm	0:9b334a45a8ff	1494	/** @defgroup ETH_MAC_Flags ETH MAC Flags
bogdanm	0:9b334a45a8ff	1495	* @{
bogdanm	0:9b334a45a8ff	1496	*/
bogdanm	0:9b334a45a8ff	1497	#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /!< Time stamp trigger flag (on MAC) /
bogdanm	0:9b334a45a8ff	1498	#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /!< MMC transmit flag /
bogdanm	0:9b334a45a8ff	1499	#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /!< MMC receive flag /
bogdanm	0:9b334a45a8ff	1500	#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /!< MMC flag (on MAC) /
bogdanm	0:9b334a45a8ff	1501	#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /!< PMT flag (on MAC) /
bogdanm	0:9b334a45a8ff	1502	/**
bogdanm	0:9b334a45a8ff	1503	* @}
bogdanm	0:9b334a45a8ff	1504	*/
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	/** @defgroup ETH_DMA_Flags ETH DMA Flags
bogdanm	0:9b334a45a8ff	1507	* @{
bogdanm	0:9b334a45a8ff	1508	*/
bogdanm	0:9b334a45a8ff	1509	#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
bogdanm	0:9b334a45a8ff	1510	#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
bogdanm	0:9b334a45a8ff	1511	#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
bogdanm	0:9b334a45a8ff	1512	#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /!< Error bits 0-Rx DMA, 1-Tx DMA /
bogdanm	0:9b334a45a8ff	1513	#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /!< Error bits 0-write transfer, 1-read transfer /
bogdanm	0:9b334a45a8ff	1514	#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /!< Error bits 0-data buffer, 1-desc. access /
bogdanm	0:9b334a45a8ff	1515	#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary flag /
bogdanm	0:9b334a45a8ff	1516	#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary flag /
bogdanm	0:9b334a45a8ff	1517	#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /!< Early receive flag /
bogdanm	0:9b334a45a8ff	1518	#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /!< Fatal bus error flag /
bogdanm	0:9b334a45a8ff	1519	#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /!< Early transmit flag /
bogdanm	0:9b334a45a8ff	1520	#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout flag /
bogdanm	0:9b334a45a8ff	1521	#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /!< Receive process stopped flag /
bogdanm	0:9b334a45a8ff	1522	#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable flag /
bogdanm	0:9b334a45a8ff	1523	#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /!< Receive flag /
bogdanm	0:9b334a45a8ff	1524	#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /!< Underflow flag /
bogdanm	0:9b334a45a8ff	1525	#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /!< Overflow flag /
bogdanm	0:9b334a45a8ff	1526	#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout flag /
bogdanm	0:9b334a45a8ff	1527	#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable flag /
bogdanm	0:9b334a45a8ff	1528	#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /!< Transmit process stopped flag /
bogdanm	0:9b334a45a8ff	1529	#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /!< Transmit flag /
bogdanm	0:9b334a45a8ff	1530	/**
bogdanm	0:9b334a45a8ff	1531	* @}
bogdanm	0:9b334a45a8ff	1532	*/
bogdanm	0:9b334a45a8ff	1533
bogdanm	0:9b334a45a8ff	1534	/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
bogdanm	0:9b334a45a8ff	1535	* @{
bogdanm	0:9b334a45a8ff	1536	*/
bogdanm	0:9b334a45a8ff	1537	#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /!< Time stamp trigger interrupt (on MAC) /
bogdanm	0:9b334a45a8ff	1538	#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /!< MMC transmit interrupt /
bogdanm	0:9b334a45a8ff	1539	#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /!< MMC receive interrupt /
bogdanm	0:9b334a45a8ff	1540	#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /!< MMC interrupt (on MAC) /
bogdanm	0:9b334a45a8ff	1541	#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /!< PMT interrupt (on MAC) /
bogdanm	0:9b334a45a8ff	1542	/**
bogdanm	0:9b334a45a8ff	1543	* @}
bogdanm	0:9b334a45a8ff	1544	*/
bogdanm	0:9b334a45a8ff	1545
bogdanm	0:9b334a45a8ff	1546	/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
bogdanm	0:9b334a45a8ff	1547	* @{
bogdanm	0:9b334a45a8ff	1548	*/
bogdanm	0:9b334a45a8ff	1549	#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
bogdanm	0:9b334a45a8ff	1550	#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
bogdanm	0:9b334a45a8ff	1551	#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
bogdanm	0:9b334a45a8ff	1552	#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary /
bogdanm	0:9b334a45a8ff	1553	#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary /
bogdanm	0:9b334a45a8ff	1554	#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /!< Early receive interrupt /
bogdanm	0:9b334a45a8ff	1555	#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /!< Fatal bus error interrupt /
bogdanm	0:9b334a45a8ff	1556	#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /!< Early transmit interrupt /
bogdanm	0:9b334a45a8ff	1557	#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout interrupt /
bogdanm	0:9b334a45a8ff	1558	#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /!< Receive process stopped interrupt /
bogdanm	0:9b334a45a8ff	1559	#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable interrupt /
bogdanm	0:9b334a45a8ff	1560	#define ETH_DMA_IT_R ((uint32_t)0x00000040) /!< Receive interrupt /
bogdanm	0:9b334a45a8ff	1561	#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /!< Underflow interrupt /
bogdanm	0:9b334a45a8ff	1562	#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /!< Overflow interrupt /
bogdanm	0:9b334a45a8ff	1563	#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout interrupt /
bogdanm	0:9b334a45a8ff	1564	#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable interrupt /
bogdanm	0:9b334a45a8ff	1565	#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /!< Transmit process stopped interrupt /
bogdanm	0:9b334a45a8ff	1566	#define ETH_DMA_IT_T ((uint32_t)0x00000001) /!< Transmit interrupt /
bogdanm	0:9b334a45a8ff	1567	/**
bogdanm	0:9b334a45a8ff	1568	* @}
bogdanm	0:9b334a45a8ff	1569	*/
bogdanm	0:9b334a45a8ff	1570
bogdanm	0:9b334a45a8ff	1571	/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
bogdanm	0:9b334a45a8ff	1572	* @{
bogdanm	0:9b334a45a8ff	1573	*/
bogdanm	0:9b334a45a8ff	1574	#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Tx Command issued /
bogdanm	0:9b334a45a8ff	1575	#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /!< Running - fetching the Tx descriptor /
bogdanm	0:9b334a45a8ff	1576	#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /!< Running - waiting for status /
bogdanm	0:9b334a45a8ff	1577	#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /!< Running - reading the data from host memory /
bogdanm	0:9b334a45a8ff	1578	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /!< Suspended - Tx Descriptor unavailable /
bogdanm	0:9b334a45a8ff	1579	#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /!< Running - closing Rx descriptor /
bogdanm	0:9b334a45a8ff	1580
bogdanm	0:9b334a45a8ff	1581	/**
bogdanm	0:9b334a45a8ff	1582	* @}
bogdanm	0:9b334a45a8ff	1583	*/
bogdanm	0:9b334a45a8ff	1584
bogdanm	0:9b334a45a8ff	1585
bogdanm	0:9b334a45a8ff	1586	/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
bogdanm	0:9b334a45a8ff	1587	* @{
bogdanm	0:9b334a45a8ff	1588	*/
bogdanm	0:9b334a45a8ff	1589	#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Rx Command issued /
bogdanm	0:9b334a45a8ff	1590	#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /!< Running - fetching the Rx descriptor /
bogdanm	0:9b334a45a8ff	1591	#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /!< Running - waiting for packet /
bogdanm	0:9b334a45a8ff	1592	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /!< Suspended - Rx Descriptor unavailable /
bogdanm	0:9b334a45a8ff	1593	#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /!< Running - closing descriptor /
bogdanm	0:9b334a45a8ff	1594	#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /!< Running - queuing the receive frame into host memory /
bogdanm	0:9b334a45a8ff	1595
bogdanm	0:9b334a45a8ff	1596	/**
bogdanm	0:9b334a45a8ff	1597	* @}
bogdanm	0:9b334a45a8ff	1598	*/
bogdanm	0:9b334a45a8ff	1599
bogdanm	0:9b334a45a8ff	1600	/** @defgroup ETH_DMA_overflow ETH DMA overflow
bogdanm	0:9b334a45a8ff	1601	* @{
bogdanm	0:9b334a45a8ff	1602	*/
bogdanm	0:9b334a45a8ff	1603	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /!< Overflow bit for FIFO overflow counter /
bogdanm	0:9b334a45a8ff	1604	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /!< Overflow bit for missed frame counter /
bogdanm	0:9b334a45a8ff	1605	/**
bogdanm	0:9b334a45a8ff	1606	* @}
bogdanm	0:9b334a45a8ff	1607	*/
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
bogdanm	0:9b334a45a8ff	1610	* @{
bogdanm	0:9b334a45a8ff	1611	*/
bogdanm	0:9b334a45a8ff	1612	#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /!< External interrupt line 19 Connected to the ETH EXTI Line /
bogdanm	0:9b334a45a8ff	1613
bogdanm	0:9b334a45a8ff	1614	/**
bogdanm	0:9b334a45a8ff	1615	* @}
bogdanm	0:9b334a45a8ff	1616	*/
bogdanm	0:9b334a45a8ff	1617
bogdanm	0:9b334a45a8ff	1618	/**
bogdanm	0:9b334a45a8ff	1619	* @}
bogdanm	0:9b334a45a8ff	1620	*/
bogdanm	0:9b334a45a8ff	1621
bogdanm	0:9b334a45a8ff	1622	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1623	/** @defgroup ETH_Exported_Macros ETH Exported Macros
bogdanm	0:9b334a45a8ff	1624	* @brief macros to handle interrupts and specific clock configurations
bogdanm	0:9b334a45a8ff	1625	* @{
bogdanm	0:9b334a45a8ff	1626	*/
bogdanm	0:9b334a45a8ff	1627
bogdanm	0:9b334a45a8ff	1628	/** @brief Reset ETH handle state
bogdanm	0:9b334a45a8ff	1629	* @param __HANDLE__: specifies the ETH handle.
bogdanm	0:9b334a45a8ff	1630	* @retval None
bogdanm	0:9b334a45a8ff	1631	*/
bogdanm	0:9b334a45a8ff	1632	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
bogdanm	0:9b334a45a8ff	1633
bogdanm	0:9b334a45a8ff	1634	/**
bogdanm	0:9b334a45a8ff	1635	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
bogdanm	0:9b334a45a8ff	1636	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1637	* @param __FLAG__: specifies the flag of TDES0 to check.
bogdanm	0:9b334a45a8ff	1638	* @retval the ETH_DMATxDescFlag (SET or RESET).
bogdanm	0:9b334a45a8ff	1639	*/
bogdanm	0:9b334a45a8ff	1640	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
bogdanm	0:9b334a45a8ff	1641
bogdanm	0:9b334a45a8ff	1642	/**
bogdanm	0:9b334a45a8ff	1643	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
bogdanm	0:9b334a45a8ff	1644	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1645	* @param __FLAG__: specifies the flag of RDES0 to check.
bogdanm	0:9b334a45a8ff	1646	* @retval the ETH_DMATxDescFlag (SET or RESET).
bogdanm	0:9b334a45a8ff	1647	*/
bogdanm	0:9b334a45a8ff	1648	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
bogdanm	0:9b334a45a8ff	1649
bogdanm	0:9b334a45a8ff	1650	/**
bogdanm	0:9b334a45a8ff	1651	* @brief Enables the specified DMA Rx Desc receive interrupt.
bogdanm	0:9b334a45a8ff	1652	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1653	* @retval None
bogdanm	0:9b334a45a8ff	1654	*/
bogdanm	0:9b334a45a8ff	1655	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
bogdanm	0:9b334a45a8ff	1656
bogdanm	0:9b334a45a8ff	1657	/**
bogdanm	0:9b334a45a8ff	1658	* @brief Disables the specified DMA Rx Desc receive interrupt.
bogdanm	0:9b334a45a8ff	1659	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1660	* @retval None
bogdanm	0:9b334a45a8ff	1661	*/
bogdanm	0:9b334a45a8ff	1662	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
bogdanm	0:9b334a45a8ff	1663
bogdanm	0:9b334a45a8ff	1664	/**
bogdanm	0:9b334a45a8ff	1665	* @brief Set the specified DMA Rx Desc Own bit.
bogdanm	0:9b334a45a8ff	1666	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1667	* @retval None
bogdanm	0:9b334a45a8ff	1668	*/
bogdanm	0:9b334a45a8ff	1669	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
bogdanm	0:9b334a45a8ff	1670
bogdanm	0:9b334a45a8ff	1671	/**
bogdanm	0:9b334a45a8ff	1672	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
bogdanm	0:9b334a45a8ff	1673	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1674	* @retval The Transmit descriptor collision counter value.
bogdanm	0:9b334a45a8ff	1675	*/
bogdanm	0:9b334a45a8ff	1676	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
bogdanm	0:9b334a45a8ff	1677
bogdanm	0:9b334a45a8ff	1678	/**
bogdanm	0:9b334a45a8ff	1679	* @brief Set the specified DMA Tx Desc Own bit.
bogdanm	0:9b334a45a8ff	1680	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1681	* @retval None
bogdanm	0:9b334a45a8ff	1682	*/
bogdanm	0:9b334a45a8ff	1683	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
bogdanm	0:9b334a45a8ff	1684
bogdanm	0:9b334a45a8ff	1685	/**
bogdanm	0:9b334a45a8ff	1686	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
bogdanm	0:9b334a45a8ff	1687	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1688	* @retval None
bogdanm	0:9b334a45a8ff	1689	*/
bogdanm	0:9b334a45a8ff	1690	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
bogdanm	0:9b334a45a8ff	1691
bogdanm	0:9b334a45a8ff	1692	/**
bogdanm	0:9b334a45a8ff	1693	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
bogdanm	0:9b334a45a8ff	1694	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1695	* @retval None
bogdanm	0:9b334a45a8ff	1696	*/
bogdanm	0:9b334a45a8ff	1697	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
bogdanm	0:9b334a45a8ff	1698
bogdanm	0:9b334a45a8ff	1699	/**
bogdanm	0:9b334a45a8ff	1700	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
bogdanm	0:9b334a45a8ff	1701	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1702	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
bogdanm	0:9b334a45a8ff	1703	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1704	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
bogdanm	0:9b334a45a8ff	1705	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
bogdanm	0:9b334a45a8ff	1706	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
bogdanm	0:9b334a45a8ff	1707	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
bogdanm	0:9b334a45a8ff	1708	* @retval None
bogdanm	0:9b334a45a8ff	1709	*/
bogdanm	0:9b334a45a8ff	1710	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
bogdanm	0:9b334a45a8ff	1711
bogdanm	0:9b334a45a8ff	1712	/**
bogdanm	0:9b334a45a8ff	1713	* @brief Enables the DMA Tx Desc CRC.
bogdanm	0:9b334a45a8ff	1714	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1715	* @retval None
bogdanm	0:9b334a45a8ff	1716	*/
bogdanm	0:9b334a45a8ff	1717	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
bogdanm	0:9b334a45a8ff	1718
bogdanm	0:9b334a45a8ff	1719	/**
bogdanm	0:9b334a45a8ff	1720	* @brief Disables the DMA Tx Desc CRC.
bogdanm	0:9b334a45a8ff	1721	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1722	* @retval None
bogdanm	0:9b334a45a8ff	1723	*/
bogdanm	0:9b334a45a8ff	1724	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
bogdanm	0:9b334a45a8ff	1725
bogdanm	0:9b334a45a8ff	1726	/**
bogdanm	0:9b334a45a8ff	1727	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
bogdanm	0:9b334a45a8ff	1728	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1729	* @retval None
bogdanm	0:9b334a45a8ff	1730	*/
bogdanm	0:9b334a45a8ff	1731	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
bogdanm	0:9b334a45a8ff	1732
bogdanm	0:9b334a45a8ff	1733	/**
bogdanm	0:9b334a45a8ff	1734	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
bogdanm	0:9b334a45a8ff	1735	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1736	* @retval None
bogdanm	0:9b334a45a8ff	1737	*/
bogdanm	0:9b334a45a8ff	1738	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
bogdanm	0:9b334a45a8ff	1739
bogdanm	0:9b334a45a8ff	1740	/**
bogdanm	0:9b334a45a8ff	1741	* @brief Enables the specified ETHERNET MAC interrupts.
bogdanm	0:9b334a45a8ff	1742	* @param __HANDLE__ : ETH Handle
bogdanm	0:9b334a45a8ff	1743	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
bogdanm	0:9b334a45a8ff	1744	* enabled or disabled.
bogdanm	0:9b334a45a8ff	1745	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1746	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
bogdanm	0:9b334a45a8ff	1747	* @arg ETH_MAC_IT_PMT : PMT interrupt
bogdanm	0:9b334a45a8ff	1748	* @retval None
bogdanm	0:9b334a45a8ff	1749	*/
bogdanm	0:9b334a45a8ff	1750	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1751
bogdanm	0:9b334a45a8ff	1752	/**
bogdanm	0:9b334a45a8ff	1753	* @brief Disables the specified ETHERNET MAC interrupts.
bogdanm	0:9b334a45a8ff	1754	* @param __HANDLE__ : ETH Handle
bogdanm	0:9b334a45a8ff	1755	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
bogdanm	0:9b334a45a8ff	1756	* enabled or disabled.
bogdanm	0:9b334a45a8ff	1757	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1758	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
bogdanm	0:9b334a45a8ff	1759	* @arg ETH_MAC_IT_PMT : PMT interrupt
bogdanm	0:9b334a45a8ff	1760	* @retval None
bogdanm	0:9b334a45a8ff	1761	*/
bogdanm	0:9b334a45a8ff	1762	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1763
bogdanm	0:9b334a45a8ff	1764	/**
bogdanm	0:9b334a45a8ff	1765	* @brief Initiate a Pause Control Frame (Full-duplex only).
bogdanm	0:9b334a45a8ff	1766	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1767	* @retval None
bogdanm	0:9b334a45a8ff	1768	*/
bogdanm	0:9b334a45a8ff	1769	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
bogdanm	0:9b334a45a8ff	1770
bogdanm	0:9b334a45a8ff	1771	/**
bogdanm	0:9b334a45a8ff	1772	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
bogdanm	0:9b334a45a8ff	1773	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1774	* @retval The new state of flow control busy status bit (SET or RESET).
bogdanm	0:9b334a45a8ff	1775	*/
bogdanm	0:9b334a45a8ff	1776	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
bogdanm	0:9b334a45a8ff	1777
bogdanm	0:9b334a45a8ff	1778	/**
bogdanm	0:9b334a45a8ff	1779	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
bogdanm	0:9b334a45a8ff	1780	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1781	* @retval None
bogdanm	0:9b334a45a8ff	1782	*/
bogdanm	0:9b334a45a8ff	1783	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
bogdanm	0:9b334a45a8ff	1784
bogdanm	0:9b334a45a8ff	1785	/**
bogdanm	0:9b334a45a8ff	1786	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
bogdanm	0:9b334a45a8ff	1787	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1788	* @retval None
bogdanm	0:9b334a45a8ff	1789	*/
bogdanm	0:9b334a45a8ff	1790	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
bogdanm	0:9b334a45a8ff	1791
bogdanm	0:9b334a45a8ff	1792	/**
bogdanm	0:9b334a45a8ff	1793	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
bogdanm	0:9b334a45a8ff	1794	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1795	* @param __FLAG__: specifies the flag to check.
bogdanm	0:9b334a45a8ff	1796	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1797	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
bogdanm	0:9b334a45a8ff	1798	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
bogdanm	0:9b334a45a8ff	1799	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
bogdanm	0:9b334a45a8ff	1800	* @arg ETH_MAC_FLAG_MMC : MMC flag
bogdanm	0:9b334a45a8ff	1801	* @arg ETH_MAC_FLAG_PMT : PMT flag
bogdanm	0:9b334a45a8ff	1802	* @retval The state of ETHERNET MAC flag.
bogdanm	0:9b334a45a8ff	1803	*/
bogdanm	0:9b334a45a8ff	1804	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
bogdanm	0:9b334a45a8ff	1805
bogdanm	0:9b334a45a8ff	1806	/**
bogdanm	0:9b334a45a8ff	1807	* @brief Enables the specified ETHERNET DMA interrupts.
bogdanm	0:9b334a45a8ff	1808	* @param __HANDLE__ : ETH Handle
bogdanm	0:9b334a45a8ff	1809	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
bogdanm	0:9b334a45a8ff	1810	* enabled @ref ETH_DMA_Interrupts
bogdanm	0:9b334a45a8ff	1811	* @retval None
bogdanm	0:9b334a45a8ff	1812	*/
bogdanm	0:9b334a45a8ff	1813	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1814
bogdanm	0:9b334a45a8ff	1815	/**
bogdanm	0:9b334a45a8ff	1816	* @brief Disables the specified ETHERNET DMA interrupts.
bogdanm	0:9b334a45a8ff	1817	* @param __HANDLE__ : ETH Handle
bogdanm	0:9b334a45a8ff	1818	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
bogdanm	0:9b334a45a8ff	1819	* disabled. @ref ETH_DMA_Interrupts
bogdanm	0:9b334a45a8ff	1820	* @retval None
bogdanm	0:9b334a45a8ff	1821	*/
bogdanm	0:9b334a45a8ff	1822	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1823
bogdanm	0:9b334a45a8ff	1824	/**
bogdanm	0:9b334a45a8ff	1825	* @brief Clears the ETHERNET DMA IT pending bit.
bogdanm	0:9b334a45a8ff	1826	* @param __HANDLE__ : ETH Handle
bogdanm	0:9b334a45a8ff	1827	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
bogdanm	0:9b334a45a8ff	1828	* @retval None
bogdanm	0:9b334a45a8ff	1829	*/
bogdanm	0:9b334a45a8ff	1830	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1831
bogdanm	0:9b334a45a8ff	1832	/**
bogdanm	0:9b334a45a8ff	1833	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
bogdanm	0:9b334a45a8ff	1834	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1835	* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
bogdanm	0:9b334a45a8ff	1836	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
bogdanm	0:9b334a45a8ff	1837	*/
bogdanm	0:9b334a45a8ff	1838	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
bogdanm	0:9b334a45a8ff	1839
bogdanm	0:9b334a45a8ff	1840	/**
bogdanm	0:9b334a45a8ff	1841	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
bogdanm	0:9b334a45a8ff	1842	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1843	* @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
bogdanm	0:9b334a45a8ff	1844	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
bogdanm	0:9b334a45a8ff	1845	*/
bogdanm	0:9b334a45a8ff	1846	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
bogdanm	0:9b334a45a8ff	1847
bogdanm	0:9b334a45a8ff	1848	/**
bogdanm	0:9b334a45a8ff	1849	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
bogdanm	0:9b334a45a8ff	1850	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1851	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
bogdanm	0:9b334a45a8ff	1852	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1853	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
bogdanm	0:9b334a45a8ff	1854	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
bogdanm	0:9b334a45a8ff	1855	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
bogdanm	0:9b334a45a8ff	1856	*/
bogdanm	0:9b334a45a8ff	1857	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
bogdanm	0:9b334a45a8ff	1858
bogdanm	0:9b334a45a8ff	1859	/**
bogdanm	0:9b334a45a8ff	1860	* @brief Set the DMA Receive status watchdog timer register value
bogdanm	0:9b334a45a8ff	1861	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1862	* @param __VALUE__: DMA Receive status watchdog timer register value
bogdanm	0:9b334a45a8ff	1863	* @retval None
bogdanm	0:9b334a45a8ff	1864	*/
bogdanm	0:9b334a45a8ff	1865	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
bogdanm	0:9b334a45a8ff	1866
bogdanm	0:9b334a45a8ff	1867	/**
bogdanm	0:9b334a45a8ff	1868	* @brief Enables any unicast packet filtered by the MAC address
bogdanm	0:9b334a45a8ff	1869	* recognition to be a wake-up frame.
bogdanm	0:9b334a45a8ff	1870	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1871	* @retval None
bogdanm	0:9b334a45a8ff	1872	*/
bogdanm	0:9b334a45a8ff	1873	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
bogdanm	0:9b334a45a8ff	1874
bogdanm	0:9b334a45a8ff	1875	/**
bogdanm	0:9b334a45a8ff	1876	* @brief Disables any unicast packet filtered by the MAC address
bogdanm	0:9b334a45a8ff	1877	* recognition to be a wake-up frame.
bogdanm	0:9b334a45a8ff	1878	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1879	* @retval None
bogdanm	0:9b334a45a8ff	1880	*/
bogdanm	0:9b334a45a8ff	1881	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
bogdanm	0:9b334a45a8ff	1882
bogdanm	0:9b334a45a8ff	1883	/**
bogdanm	0:9b334a45a8ff	1884	* @brief Enables the MAC Wake-Up Frame Detection.
bogdanm	0:9b334a45a8ff	1885	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1886	* @retval None
bogdanm	0:9b334a45a8ff	1887	*/
bogdanm	0:9b334a45a8ff	1888	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
bogdanm	0:9b334a45a8ff	1889
bogdanm	0:9b334a45a8ff	1890	/**
bogdanm	0:9b334a45a8ff	1891	* @brief Disables the MAC Wake-Up Frame Detection.
bogdanm	0:9b334a45a8ff	1892	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1893	* @retval None
bogdanm	0:9b334a45a8ff	1894	*/
bogdanm	0:9b334a45a8ff	1895	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
bogdanm	0:9b334a45a8ff	1896
bogdanm	0:9b334a45a8ff	1897	/**
bogdanm	0:9b334a45a8ff	1898	* @brief Enables the MAC Magic Packet Detection.
bogdanm	0:9b334a45a8ff	1899	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1900	* @retval None
bogdanm	0:9b334a45a8ff	1901	*/
bogdanm	0:9b334a45a8ff	1902	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
bogdanm	0:9b334a45a8ff	1903
bogdanm	0:9b334a45a8ff	1904	/**
bogdanm	0:9b334a45a8ff	1905	* @brief Disables the MAC Magic Packet Detection.
bogdanm	0:9b334a45a8ff	1906	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1907	* @retval None
bogdanm	0:9b334a45a8ff	1908	*/
bogdanm	0:9b334a45a8ff	1909	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
bogdanm	0:9b334a45a8ff	1910
bogdanm	0:9b334a45a8ff	1911	/**
bogdanm	0:9b334a45a8ff	1912	* @brief Enables the MAC Power Down.
bogdanm	0:9b334a45a8ff	1913	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1914	* @retval None
bogdanm	0:9b334a45a8ff	1915	*/
bogdanm	0:9b334a45a8ff	1916	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
bogdanm	0:9b334a45a8ff	1917
bogdanm	0:9b334a45a8ff	1918	/**
bogdanm	0:9b334a45a8ff	1919	* @brief Disables the MAC Power Down.
bogdanm	0:9b334a45a8ff	1920	* @param __HANDLE__: ETH Handle
bogdanm	0:9b334a45a8ff	1921	* @retval None
bogdanm	0:9b334a45a8ff	1922	*/
bogdanm	0:9b334a45a8ff	1923	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
bogdanm	0:9b334a45a8ff	1924
bogdanm	0:9b334a45a8ff	1925	/**
bogdanm	0:9b334a45a8ff	1926	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
bogdanm	0:9b334a45a8ff	1927	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1928	* @param __FLAG__: specifies the flag to check.
bogdanm	0:9b334a45a8ff	1929	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1930	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
bogdanm	0:9b334a45a8ff	1931	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
bogdanm	0:9b334a45a8ff	1932	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
bogdanm	0:9b334a45a8ff	1933	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
bogdanm	0:9b334a45a8ff	1934	*/
bogdanm	0:9b334a45a8ff	1935	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
bogdanm	0:9b334a45a8ff	1936
bogdanm	0:9b334a45a8ff	1937	/**
bogdanm	0:9b334a45a8ff	1938	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
bogdanm	0:9b334a45a8ff	1939	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1940	* @retval None
bogdanm	0:9b334a45a8ff	1941	*/
bogdanm	0:9b334a45a8ff	1942	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
bogdanm	0:9b334a45a8ff	1943
bogdanm	0:9b334a45a8ff	1944	/**
bogdanm	0:9b334a45a8ff	1945	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
bogdanm	0:9b334a45a8ff	1946	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1947	* @retval None
bogdanm	0:9b334a45a8ff	1948	*/
bogdanm	0:9b334a45a8ff	1949	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
bogdanm	0:9b334a45a8ff	1950	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
bogdanm	0:9b334a45a8ff	1951
bogdanm	0:9b334a45a8ff	1952	/**
bogdanm	0:9b334a45a8ff	1953	* @brief Enables the MMC Counter Freeze.
bogdanm	0:9b334a45a8ff	1954	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1955	* @retval None
bogdanm	0:9b334a45a8ff	1956	*/
bogdanm	0:9b334a45a8ff	1957	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
bogdanm	0:9b334a45a8ff	1958
bogdanm	0:9b334a45a8ff	1959	/**
bogdanm	0:9b334a45a8ff	1960	* @brief Disables the MMC Counter Freeze.
bogdanm	0:9b334a45a8ff	1961	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1962	* @retval None
bogdanm	0:9b334a45a8ff	1963	*/
bogdanm	0:9b334a45a8ff	1964	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
bogdanm	0:9b334a45a8ff	1965
bogdanm	0:9b334a45a8ff	1966	/**
bogdanm	0:9b334a45a8ff	1967	* @brief Enables the MMC Reset On Read.
bogdanm	0:9b334a45a8ff	1968	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1969	* @retval None
bogdanm	0:9b334a45a8ff	1970	*/
bogdanm	0:9b334a45a8ff	1971	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
bogdanm	0:9b334a45a8ff	1972
bogdanm	0:9b334a45a8ff	1973	/**
bogdanm	0:9b334a45a8ff	1974	* @brief Disables the MMC Reset On Read.
bogdanm	0:9b334a45a8ff	1975	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1976	* @retval None
bogdanm	0:9b334a45a8ff	1977	*/
bogdanm	0:9b334a45a8ff	1978	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
bogdanm	0:9b334a45a8ff	1979
bogdanm	0:9b334a45a8ff	1980	/**
bogdanm	0:9b334a45a8ff	1981	* @brief Enables the MMC Counter Stop Rollover.
bogdanm	0:9b334a45a8ff	1982	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1983	* @retval None
bogdanm	0:9b334a45a8ff	1984	*/
bogdanm	0:9b334a45a8ff	1985	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
bogdanm	0:9b334a45a8ff	1986
bogdanm	0:9b334a45a8ff	1987	/**
bogdanm	0:9b334a45a8ff	1988	* @brief Disables the MMC Counter Stop Rollover.
bogdanm	0:9b334a45a8ff	1989	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1990	* @retval None
bogdanm	0:9b334a45a8ff	1991	*/
bogdanm	0:9b334a45a8ff	1992	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
bogdanm	0:9b334a45a8ff	1993
bogdanm	0:9b334a45a8ff	1994	/**
bogdanm	0:9b334a45a8ff	1995	* @brief Resets the MMC Counters.
bogdanm	0:9b334a45a8ff	1996	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	1997	* @retval None
bogdanm	0:9b334a45a8ff	1998	*/
bogdanm	0:9b334a45a8ff	1999	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
bogdanm	0:9b334a45a8ff	2000
bogdanm	0:9b334a45a8ff	2001	/**
bogdanm	0:9b334a45a8ff	2002	* @brief Enables the specified ETHERNET MMC Rx interrupts.
bogdanm	0:9b334a45a8ff	2003	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	2004	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm	0:9b334a45a8ff	2005	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2006	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
bogdanm	0:9b334a45a8ff	2007	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
bogdanm	0:9b334a45a8ff	2008	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
bogdanm	0:9b334a45a8ff	2009	* @retval None
bogdanm	0:9b334a45a8ff	2010	*/
bogdanm	0:9b334a45a8ff	2011	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
bogdanm	0:9b334a45a8ff	2012	/**
bogdanm	0:9b334a45a8ff	2013	* @brief Disables the specified ETHERNET MMC Rx interrupts.
bogdanm	0:9b334a45a8ff	2014	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	2015	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm	0:9b334a45a8ff	2016	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2017	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
bogdanm	0:9b334a45a8ff	2018	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
bogdanm	0:9b334a45a8ff	2019	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
bogdanm	0:9b334a45a8ff	2020	* @retval None
bogdanm	0:9b334a45a8ff	2021	*/
bogdanm	0:9b334a45a8ff	2022	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFF)
bogdanm	0:9b334a45a8ff	2023	/**
bogdanm	0:9b334a45a8ff	2024	* @brief Enables the specified ETHERNET MMC Tx interrupts.
bogdanm	0:9b334a45a8ff	2025	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	2026	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm	0:9b334a45a8ff	2027	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2028	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
bogdanm	0:9b334a45a8ff	2029	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
bogdanm	0:9b334a45a8ff	2030	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
bogdanm	0:9b334a45a8ff	2031	* @retval None
bogdanm	0:9b334a45a8ff	2032	*/
bogdanm	0:9b334a45a8ff	2033	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2034
bogdanm	0:9b334a45a8ff	2035	/**
bogdanm	0:9b334a45a8ff	2036	* @brief Disables the specified ETHERNET MMC Tx interrupts.
bogdanm	0:9b334a45a8ff	2037	* @param __HANDLE__: ETH Handle.
bogdanm	0:9b334a45a8ff	2038	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm	0:9b334a45a8ff	2039	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2040	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
bogdanm	0:9b334a45a8ff	2041	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
bogdanm	0:9b334a45a8ff	2042	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
bogdanm	0:9b334a45a8ff	2043	* @retval None
bogdanm	0:9b334a45a8ff	2044	*/
bogdanm	0:9b334a45a8ff	2045	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2046
bogdanm	0:9b334a45a8ff	2047	/**
bogdanm	0:9b334a45a8ff	2048	* @brief Enables the ETH External interrupt line.
bogdanm	0:9b334a45a8ff	2049	* @retval None
bogdanm	0:9b334a45a8ff	2050	*/
bogdanm	0:9b334a45a8ff	2051	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
bogdanm	0:9b334a45a8ff	2052
bogdanm	0:9b334a45a8ff	2053	/**
bogdanm	0:9b334a45a8ff	2054	* @brief Disables the ETH External interrupt line.
bogdanm	0:9b334a45a8ff	2055	* @retval None
bogdanm	0:9b334a45a8ff	2056	*/
bogdanm	0:9b334a45a8ff	2057	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
bogdanm	0:9b334a45a8ff	2058
bogdanm	0:9b334a45a8ff	2059	/**
bogdanm	0:9b334a45a8ff	2060	* @brief Enable event on ETH External event line.
bogdanm	0:9b334a45a8ff	2061	* @retval None.
bogdanm	0:9b334a45a8ff	2062	*/
bogdanm	0:9b334a45a8ff	2063	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR \|= (ETH_EXTI_LINE_WAKEUP)
bogdanm	0:9b334a45a8ff	2064
bogdanm	0:9b334a45a8ff	2065	/**
bogdanm	0:9b334a45a8ff	2066	* @brief Disable event on ETH External event line
bogdanm	0:9b334a45a8ff	2067	* @retval None.
bogdanm	0:9b334a45a8ff	2068	*/
bogdanm	0:9b334a45a8ff	2069	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
bogdanm	0:9b334a45a8ff	2070
bogdanm	0:9b334a45a8ff	2071	/**
bogdanm	0:9b334a45a8ff	2072	* @brief Get flag of the ETH External interrupt line.
bogdanm	0:9b334a45a8ff	2073	* @retval None
bogdanm	0:9b334a45a8ff	2074	*/
bogdanm	0:9b334a45a8ff	2075	#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
bogdanm	0:9b334a45a8ff	2076
bogdanm	0:9b334a45a8ff	2077	/**
bogdanm	0:9b334a45a8ff	2078	* @brief Clear flag of the ETH External interrupt line.
bogdanm	0:9b334a45a8ff	2079	* @retval None
bogdanm	0:9b334a45a8ff	2080	*/
bogdanm	0:9b334a45a8ff	2081	#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
bogdanm	0:9b334a45a8ff	2082
bogdanm	0:9b334a45a8ff	2083	/**
bogdanm	0:9b334a45a8ff	2084	* @brief Enables rising edge trigger to the ETH External interrupt line.
bogdanm	0:9b334a45a8ff	2085	* @retval None
bogdanm	0:9b334a45a8ff	2086	*/
bogdanm	0:9b334a45a8ff	2087	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
bogdanm	0:9b334a45a8ff	2088
bogdanm	0:9b334a45a8ff	2089	/**
bogdanm	0:9b334a45a8ff	2090	* @brief Disables the rising edge trigger to the ETH External interrupt line.
bogdanm	0:9b334a45a8ff	2091	* @retval None
bogdanm	0:9b334a45a8ff	2092	*/
bogdanm	0:9b334a45a8ff	2093	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
bogdanm	0:9b334a45a8ff	2094
bogdanm	0:9b334a45a8ff	2095	/**
bogdanm	0:9b334a45a8ff	2096	* @brief Enables falling edge trigger to the ETH External interrupt line.
bogdanm	0:9b334a45a8ff	2097	* @retval None
bogdanm	0:9b334a45a8ff	2098	*/
bogdanm	0:9b334a45a8ff	2099	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP)
bogdanm	0:9b334a45a8ff	2100
bogdanm	0:9b334a45a8ff	2101	/**
bogdanm	0:9b334a45a8ff	2102	* @brief Disables falling edge trigger to the ETH External interrupt line.
bogdanm	0:9b334a45a8ff	2103	* @retval None
bogdanm	0:9b334a45a8ff	2104	*/
bogdanm	0:9b334a45a8ff	2105	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
bogdanm	0:9b334a45a8ff	2106
bogdanm	0:9b334a45a8ff	2107	/**
bogdanm	0:9b334a45a8ff	2108	* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
bogdanm	0:9b334a45a8ff	2109	* @retval None
bogdanm	0:9b334a45a8ff	2110	*/
bogdanm	0:9b334a45a8ff	2111	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP;\
bogdanm	0:9b334a45a8ff	2112	EXTI->FTSR \|= ETH_EXTI_LINE_WAKEUP
bogdanm	0:9b334a45a8ff	2113
bogdanm	0:9b334a45a8ff	2114	/**
bogdanm	0:9b334a45a8ff	2115	* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
bogdanm	0:9b334a45a8ff	2116	* @retval None
bogdanm	0:9b334a45a8ff	2117	*/
bogdanm	0:9b334a45a8ff	2118	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
bogdanm	0:9b334a45a8ff	2119	EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
bogdanm	0:9b334a45a8ff	2120
bogdanm	0:9b334a45a8ff	2121	/**
bogdanm	0:9b334a45a8ff	2122	* @brief Generate a Software interrupt on selected EXTI line.
bogdanm	0:9b334a45a8ff	2123	* @retval None.
bogdanm	0:9b334a45a8ff	2124	*/
bogdanm	0:9b334a45a8ff	2125	#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER\|= ETH_EXTI_LINE_WAKEUP
bogdanm	0:9b334a45a8ff	2126
bogdanm	0:9b334a45a8ff	2127	/**
bogdanm	0:9b334a45a8ff	2128	* @}
bogdanm	0:9b334a45a8ff	2129	*/
bogdanm	0:9b334a45a8ff	2130	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2131
bogdanm	0:9b334a45a8ff	2132	/** @addtogroup ETH_Exported_Functions
bogdanm	0:9b334a45a8ff	2133	* @{
bogdanm	0:9b334a45a8ff	2134	*/
bogdanm	0:9b334a45a8ff	2135
bogdanm	0:9b334a45a8ff	2136	/* Initialization and de-initialization functions ****************************/
bogdanm	0:9b334a45a8ff	2137
bogdanm	0:9b334a45a8ff	2138	/** @addtogroup ETH_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	2139	* @{
bogdanm	0:9b334a45a8ff	2140	*/
bogdanm	0:9b334a45a8ff	2141	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2142	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2143	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2144	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2145	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
bogdanm	0:9b334a45a8ff	2146	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
bogdanm	0:9b334a45a8ff	2147
bogdanm	0:9b334a45a8ff	2148	/**
bogdanm	0:9b334a45a8ff	2149	* @}
bogdanm	0:9b334a45a8ff	2150	*/
bogdanm	0:9b334a45a8ff	2151	/* IO operation functions ****************************************************/
bogdanm	0:9b334a45a8ff	2152
bogdanm	0:9b334a45a8ff	2153	/** @addtogroup ETH_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	2154	* @{
bogdanm	0:9b334a45a8ff	2155	*/
bogdanm	0:9b334a45a8ff	2156	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
bogdanm	0:9b334a45a8ff	2157	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2158	/* Communication with PHY functions*/
bogdanm	0:9b334a45a8ff	2159	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
bogdanm	0:9b334a45a8ff	2160	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
bogdanm	0:9b334a45a8ff	2161	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	2162	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2163	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2164	/* Callback in non blocking modes (Interrupt) */
bogdanm	0:9b334a45a8ff	2165	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2166	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2167	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2168	/**
bogdanm	0:9b334a45a8ff	2169	* @}
bogdanm	0:9b334a45a8ff	2170	*/
bogdanm	0:9b334a45a8ff	2171
bogdanm	0:9b334a45a8ff	2172	/* Peripheral Control functions **********************************************/
bogdanm	0:9b334a45a8ff	2173
bogdanm	0:9b334a45a8ff	2174	/** @addtogroup ETH_Exported_Functions_Group3
bogdanm	0:9b334a45a8ff	2175	* @{
bogdanm	0:9b334a45a8ff	2176	*/
bogdanm	0:9b334a45a8ff	2177
bogdanm	0:9b334a45a8ff	2178	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2179	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2180	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
bogdanm	0:9b334a45a8ff	2181	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
bogdanm	0:9b334a45a8ff	2182	/**
bogdanm	0:9b334a45a8ff	2183	* @}
bogdanm	0:9b334a45a8ff	2184	*/
bogdanm	0:9b334a45a8ff	2185
bogdanm	0:9b334a45a8ff	2186	/* Peripheral State functions ************************************************/
bogdanm	0:9b334a45a8ff	2187
bogdanm	0:9b334a45a8ff	2188	/** @addtogroup ETH_Exported_Functions_Group4
bogdanm	0:9b334a45a8ff	2189	* @{
bogdanm	0:9b334a45a8ff	2190	*/
bogdanm	0:9b334a45a8ff	2191	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	2192	/**
bogdanm	0:9b334a45a8ff	2193	* @}
bogdanm	0:9b334a45a8ff	2194	*/
bogdanm	0:9b334a45a8ff	2195
bogdanm	0:9b334a45a8ff	2196	/**
bogdanm	0:9b334a45a8ff	2197	* @}
bogdanm	0:9b334a45a8ff	2198	*/
bogdanm	0:9b334a45a8ff	2199
bogdanm	0:9b334a45a8ff	2200	/**
bogdanm	0:9b334a45a8ff	2201	* @}
bogdanm	0:9b334a45a8ff	2202	*/
bogdanm	0:9b334a45a8ff	2203
bogdanm	0:9b334a45a8ff	2204	/**
bogdanm	0:9b334a45a8ff	2205	* @}
bogdanm	0:9b334a45a8ff	2206	*/
bogdanm	0:9b334a45a8ff	2207
bogdanm	0:9b334a45a8ff	2208	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	2209
bogdanm	0:9b334a45a8ff	2210	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	2211	}
bogdanm	0:9b334a45a8ff	2212	#endif
bogdanm	0:9b334a45a8ff	2213
bogdanm	0:9b334a45a8ff	2214	#endif /* __STM32F4xx_HAL_ETH_H */
bogdanm	0:9b334a45a8ff	2215
bogdanm	0:9b334a45a8ff	2216
bogdanm	0:9b334a45a8ff	2217	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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