en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
19:112740acecfa
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_hal_eth.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.3.2
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief ETH HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Ethernet (ETH) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + IO operation functions
bogdanm 0:9b334a45a8ff 12 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 13 * + Peripheral State and Errors functions
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 @verbatim
bogdanm 0:9b334a45a8ff 16 ==============================================================================
bogdanm 0:9b334a45a8ff 17 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 18 ==============================================================================
bogdanm 0:9b334a45a8ff 19 [..]
bogdanm 0:9b334a45a8ff 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
bogdanm 0:9b334a45a8ff 21 ETH_HandleTypeDef heth;
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 (#)Fill parameters of Init structure in heth handle
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
bogdanm 0:9b334a45a8ff 28 (##) Enable the Ethernet interface clock using
bogdanm 0:9b334a45a8ff 29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 (##) Initialize the related GPIO clocks
bogdanm 0:9b334a45a8ff 34 (##) Configure Ethernet pin-out
bogdanm 0:9b334a45a8ff 35 (##) Configure Ethernet NVIC interrupt (IT mode)
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
bogdanm 0:9b334a45a8ff 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
bogdanm 0:9b334a45a8ff 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 (#)Enable MAC and DMA transmission and reception:
bogdanm 0:9b334a45a8ff 42 (##) HAL_ETH_Start();
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
bogdanm 0:9b334a45a8ff 45 the frame to MAC TX FIFO:
bogdanm 0:9b334a45a8ff 46 (##) HAL_ETH_TransmitFrame();
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
bogdanm 0:9b334a45a8ff 49 frame parameters
bogdanm 0:9b334a45a8ff 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 (#) Get a received frame when an ETH RX interrupt occurs:
bogdanm 0:9b334a45a8ff 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 (#) Communicate with external PHY device:
bogdanm 0:9b334a45a8ff 56 (##) Read a specific register from the PHY
bogdanm 0:9b334a45a8ff 57 HAL_ETH_ReadPHYRegister();
bogdanm 0:9b334a45a8ff 58 (##) Write data to a specific RHY register:
bogdanm 0:9b334a45a8ff 59 HAL_ETH_WritePHYRegister();
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
bogdanm 0:9b334a45a8ff 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
bogdanm 0:9b334a45a8ff 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 -@- The PTP protocol and the DMA descriptors ring mode are not supported
bogdanm 0:9b334a45a8ff 68 in this driver
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 @endverbatim
bogdanm 0:9b334a45a8ff 71 ******************************************************************************
bogdanm 0:9b334a45a8ff 72 * @attention
bogdanm 0:9b334a45a8ff 73 *
bogdanm 0:9b334a45a8ff 74 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 75 *
bogdanm 0:9b334a45a8ff 76 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 77 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 78 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 79 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 80 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 81 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 82 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 84 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 85 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 86 *
bogdanm 0:9b334a45a8ff 87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 97 *
bogdanm 0:9b334a45a8ff 98 ******************************************************************************
bogdanm 0:9b334a45a8ff 99 */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 102 #include "stm32f4xx_hal.h"
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 105 * @{
bogdanm 0:9b334a45a8ff 106 */
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 /** @defgroup ETH ETH
bogdanm 0:9b334a45a8ff 109 * @brief ETH HAL module driver
bogdanm 0:9b334a45a8ff 110 * @{
bogdanm 0:9b334a45a8ff 111 */
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 #ifdef HAL_ETH_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 118 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 119 /** @defgroup ETH_Private_Constants ETH Private Constants
bogdanm 0:9b334a45a8ff 120 * @{
bogdanm 0:9b334a45a8ff 121 */
bogdanm 0:9b334a45a8ff 122 #define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
bogdanm 0:9b334a45a8ff 123 #define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 /**
bogdanm 0:9b334a45a8ff 126 * @}
bogdanm 0:9b334a45a8ff 127 */
bogdanm 0:9b334a45a8ff 128 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 129 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 130 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 131 /** @defgroup ETH_Private_Functions ETH Private Functions
bogdanm 0:9b334a45a8ff 132 * @{
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
bogdanm 0:9b334a45a8ff 135 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
bogdanm 0:9b334a45a8ff 136 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 137 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 138 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 139 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 140 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 141 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 142 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 143 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 144 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /**
bogdanm 0:9b334a45a8ff 147 * @}
bogdanm 0:9b334a45a8ff 148 */
bogdanm 0:9b334a45a8ff 149 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /** @defgroup ETH_Exported_Functions ETH Exported Functions
bogdanm 0:9b334a45a8ff 152 * @{
bogdanm 0:9b334a45a8ff 153 */
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 156 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 157 *
bogdanm 0:9b334a45a8ff 158 @verbatim
bogdanm 0:9b334a45a8ff 159 ===============================================================================
bogdanm 0:9b334a45a8ff 160 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 161 ===============================================================================
bogdanm 0:9b334a45a8ff 162 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 163 (+) Initialize and configure the Ethernet peripheral
bogdanm 0:9b334a45a8ff 164 (+) De-initialize the Ethernet peripheral
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 @endverbatim
bogdanm 0:9b334a45a8ff 167 * @{
bogdanm 0:9b334a45a8ff 168 */
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /**
bogdanm 0:9b334a45a8ff 171 * @brief Initializes the Ethernet MAC and DMA according to default
bogdanm 0:9b334a45a8ff 172 * parameters.
bogdanm 0:9b334a45a8ff 173 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 174 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 175 * @retval HAL status
bogdanm 0:9b334a45a8ff 176 */
bogdanm 0:9b334a45a8ff 177 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 178 {
bogdanm 0:9b334a45a8ff 179 uint32_t tmpreg1 = 0, phyreg = 0;
bogdanm 0:9b334a45a8ff 180 uint32_t hclk = 60000000;
bogdanm 0:9b334a45a8ff 181 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 182 uint32_t err = ETH_SUCCESS;
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 /* Check the ETH peripheral state */
bogdanm 0:9b334a45a8ff 185 if(heth == NULL)
bogdanm 0:9b334a45a8ff 186 {
bogdanm 0:9b334a45a8ff 187 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 188 }
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /* Check parameters */
bogdanm 0:9b334a45a8ff 191 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
bogdanm 0:9b334a45a8ff 192 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
bogdanm 0:9b334a45a8ff 193 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
bogdanm 0:9b334a45a8ff 194 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 if(heth->State == HAL_ETH_STATE_RESET)
bogdanm 0:9b334a45a8ff 197 {
bogdanm 0:9b334a45a8ff 198 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 199 heth->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 200 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
bogdanm 0:9b334a45a8ff 201 HAL_ETH_MspInit(heth);
bogdanm 0:9b334a45a8ff 202 }
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 /* Enable SYSCFG Clock */
bogdanm 0:9b334a45a8ff 205 __HAL_RCC_SYSCFG_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 /* Select MII or RMII Mode*/
bogdanm 0:9b334a45a8ff 208 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
bogdanm 0:9b334a45a8ff 209 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 /* Ethernet Software reset */
bogdanm 0:9b334a45a8ff 212 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
bogdanm 0:9b334a45a8ff 213 /* After reset all the registers holds their respective reset values */
bogdanm 0:9b334a45a8ff 214 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /* Wait for software reset */
bogdanm 0:9b334a45a8ff 217 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 218 {
bogdanm 0:9b334a45a8ff 219 }
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 /*-------------------------------- MAC Initialization ----------------------*/
bogdanm 0:9b334a45a8ff 222 /* Get the ETHERNET MACMIIAR value */
bogdanm 0:9b334a45a8ff 223 tmpreg1 = (heth->Instance)->MACMIIAR;
bogdanm 0:9b334a45a8ff 224 /* Clear CSR Clock Range CR[2:0] bits */
bogdanm 0:9b334a45a8ff 225 tmpreg1 &= ETH_MACMIIAR_CR_MASK;
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /* Get hclk frequency value */
bogdanm 0:9b334a45a8ff 228 hclk = HAL_RCC_GetHCLKFreq();
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /* Set CR bits depending on hclk value */
bogdanm 0:9b334a45a8ff 231 if((hclk >= 20000000)&&(hclk < 35000000))
bogdanm 0:9b334a45a8ff 232 {
bogdanm 0:9b334a45a8ff 233 /* CSR Clock Range between 20-35 MHz */
bogdanm 0:9b334a45a8ff 234 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
bogdanm 0:9b334a45a8ff 235 }
bogdanm 0:9b334a45a8ff 236 else if((hclk >= 35000000)&&(hclk < 60000000))
bogdanm 0:9b334a45a8ff 237 {
bogdanm 0:9b334a45a8ff 238 /* CSR Clock Range between 35-60 MHz */
bogdanm 0:9b334a45a8ff 239 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
bogdanm 0:9b334a45a8ff 240 }
bogdanm 0:9b334a45a8ff 241 else if((hclk >= 60000000)&&(hclk < 100000000))
bogdanm 0:9b334a45a8ff 242 {
bogdanm 0:9b334a45a8ff 243 /* CSR Clock Range between 60-100 MHz */
bogdanm 0:9b334a45a8ff 244 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
bogdanm 0:9b334a45a8ff 245 }
bogdanm 0:9b334a45a8ff 246 else if((hclk >= 100000000)&&(hclk < 150000000))
bogdanm 0:9b334a45a8ff 247 {
bogdanm 0:9b334a45a8ff 248 /* CSR Clock Range between 100-150 MHz */
bogdanm 0:9b334a45a8ff 249 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
bogdanm 0:9b334a45a8ff 250 }
bogdanm 0:9b334a45a8ff 251 else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
bogdanm 0:9b334a45a8ff 252 {
bogdanm 0:9b334a45a8ff 253 /* CSR Clock Range between 150-168 MHz */
bogdanm 0:9b334a45a8ff 254 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
bogdanm 0:9b334a45a8ff 255 }
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
bogdanm 0:9b334a45a8ff 258 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /*-------------------- PHY initialization and configuration ----------------*/
bogdanm 0:9b334a45a8ff 261 /* Put the PHY in reset mode */
bogdanm 0:9b334a45a8ff 262 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
bogdanm 0:9b334a45a8ff 263 {
bogdanm 0:9b334a45a8ff 264 /* In case of write timeout */
bogdanm 0:9b334a45a8ff 265 err = ETH_ERROR;
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 268 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 /* Set the ETH peripheral state to READY */
bogdanm 0:9b334a45a8ff 271 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 /* Return HAL_ERROR */
bogdanm 0:9b334a45a8ff 274 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 275 }
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 /* Delay to assure PHY reset */
bogdanm 0:9b334a45a8ff 278 HAL_Delay(PHY_RESET_DELAY);
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
bogdanm 0:9b334a45a8ff 281 {
bogdanm 0:9b334a45a8ff 282 /* Get tick */
bogdanm 0:9b334a45a8ff 283 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 /* We wait for linked status */
bogdanm 0:9b334a45a8ff 286 do
bogdanm 0:9b334a45a8ff 287 {
bogdanm 0:9b334a45a8ff 288 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 291 if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 292 {
bogdanm 0:9b334a45a8ff 293 /* In case of write timeout */
bogdanm 0:9b334a45a8ff 294 err = ETH_ERROR;
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 297 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 302 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 305 }
bogdanm 0:9b334a45a8ff 306 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /* Enable Auto-Negotiation */
bogdanm 0:9b334a45a8ff 310 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
bogdanm 0:9b334a45a8ff 311 {
bogdanm 0:9b334a45a8ff 312 /* In case of write timeout */
bogdanm 0:9b334a45a8ff 313 err = ETH_ERROR;
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 316 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 /* Set the ETH peripheral state to READY */
bogdanm 0:9b334a45a8ff 319 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321 /* Return HAL_ERROR */
bogdanm 0:9b334a45a8ff 322 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 323 }
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 /* Get tick */
bogdanm 0:9b334a45a8ff 326 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 327
bogdanm 0:9b334a45a8ff 328 /* Wait until the auto-negotiation will be completed */
bogdanm 0:9b334a45a8ff 329 do
bogdanm 0:9b334a45a8ff 330 {
bogdanm 0:9b334a45a8ff 331 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 334 if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 335 {
bogdanm 0:9b334a45a8ff 336 /* In case of write timeout */
bogdanm 0:9b334a45a8ff 337 err = ETH_ERROR;
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 340 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 345 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 348 }
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 /* Read the result of the auto-negotiation */
bogdanm 0:9b334a45a8ff 353 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
bogdanm 0:9b334a45a8ff 354 {
bogdanm 0:9b334a45a8ff 355 /* In case of write timeout */
bogdanm 0:9b334a45a8ff 356 err = ETH_ERROR;
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 359 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /* Set the ETH peripheral state to READY */
bogdanm 0:9b334a45a8ff 362 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 /* Return HAL_ERROR */
bogdanm 0:9b334a45a8ff 365 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 366 }
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
bogdanm 0:9b334a45a8ff 369 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 370 {
bogdanm 0:9b334a45a8ff 371 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
bogdanm 0:9b334a45a8ff 372 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
bogdanm 0:9b334a45a8ff 373 }
bogdanm 0:9b334a45a8ff 374 else
bogdanm 0:9b334a45a8ff 375 {
bogdanm 0:9b334a45a8ff 376 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
bogdanm 0:9b334a45a8ff 377 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
bogdanm 0:9b334a45a8ff 378 }
bogdanm 0:9b334a45a8ff 379 /* Configure the MAC with the speed fixed by the auto-negotiation process */
bogdanm 0:9b334a45a8ff 380 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
bogdanm 0:9b334a45a8ff 381 {
bogdanm 0:9b334a45a8ff 382 /* Set Ethernet speed to 10M following the auto-negotiation */
bogdanm 0:9b334a45a8ff 383 (heth->Init).Speed = ETH_SPEED_10M;
bogdanm 0:9b334a45a8ff 384 }
bogdanm 0:9b334a45a8ff 385 else
bogdanm 0:9b334a45a8ff 386 {
bogdanm 0:9b334a45a8ff 387 /* Set Ethernet speed to 100M following the auto-negotiation */
bogdanm 0:9b334a45a8ff 388 (heth->Init).Speed = ETH_SPEED_100M;
bogdanm 0:9b334a45a8ff 389 }
bogdanm 0:9b334a45a8ff 390 }
bogdanm 0:9b334a45a8ff 391 else /* AutoNegotiation Disable */
bogdanm 0:9b334a45a8ff 392 {
bogdanm 0:9b334a45a8ff 393 /* Check parameters */
bogdanm 0:9b334a45a8ff 394 assert_param(IS_ETH_SPEED(heth->Init.Speed));
bogdanm 0:9b334a45a8ff 395 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 /* Set MAC Speed and Duplex Mode */
bogdanm 0:9b334a45a8ff 398 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
bogdanm 0:9b334a45a8ff 399 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
bogdanm 0:9b334a45a8ff 400 {
bogdanm 0:9b334a45a8ff 401 /* In case of write timeout */
bogdanm 0:9b334a45a8ff 402 err = ETH_ERROR;
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 405 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /* Set the ETH peripheral state to READY */
bogdanm 0:9b334a45a8ff 408 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /* Return HAL_ERROR */
bogdanm 0:9b334a45a8ff 411 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 412 }
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /* Delay to assure PHY configuration */
bogdanm 0:9b334a45a8ff 415 HAL_Delay(PHY_CONFIG_DELAY);
bogdanm 0:9b334a45a8ff 416 }
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 /* Config MAC and DMA */
bogdanm 0:9b334a45a8ff 419 ETH_MACDMAConfig(heth, err);
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 /* Set ETH HAL State to Ready */
bogdanm 0:9b334a45a8ff 422 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /* Return function status */
bogdanm 0:9b334a45a8ff 425 return HAL_OK;
bogdanm 0:9b334a45a8ff 426 }
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 /**
bogdanm 0:9b334a45a8ff 429 * @brief De-Initializes the ETH peripheral.
bogdanm 0:9b334a45a8ff 430 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 431 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 432 * @retval HAL status
bogdanm 0:9b334a45a8ff 433 */
bogdanm 0:9b334a45a8ff 434 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 435 {
bogdanm 0:9b334a45a8ff 436 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 437 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 438
bogdanm 0:9b334a45a8ff 439 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
bogdanm 0:9b334a45a8ff 440 HAL_ETH_MspDeInit(heth);
bogdanm 0:9b334a45a8ff 441
bogdanm 0:9b334a45a8ff 442 /* Set ETH HAL state to Disabled */
bogdanm 0:9b334a45a8ff 443 heth->State= HAL_ETH_STATE_RESET;
bogdanm 0:9b334a45a8ff 444
bogdanm 0:9b334a45a8ff 445 /* Release Lock */
bogdanm 0:9b334a45a8ff 446 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 447
bogdanm 0:9b334a45a8ff 448 /* Return function status */
bogdanm 0:9b334a45a8ff 449 return HAL_OK;
bogdanm 0:9b334a45a8ff 450 }
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 /**
bogdanm 0:9b334a45a8ff 453 * @brief Initializes the DMA Tx descriptors in chain mode.
bogdanm 0:9b334a45a8ff 454 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 455 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 456 * @param DMATxDescTab: Pointer to the first Tx desc list
bogdanm 0:9b334a45a8ff 457 * @param TxBuff: Pointer to the first TxBuffer list
bogdanm 0:9b334a45a8ff 458 * @param TxBuffCount: Number of the used Tx desc in the list
bogdanm 0:9b334a45a8ff 459 * @retval HAL status
bogdanm 0:9b334a45a8ff 460 */
bogdanm 0:9b334a45a8ff 461 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
bogdanm 0:9b334a45a8ff 462 {
bogdanm 0:9b334a45a8ff 463 uint32_t i = 0;
bogdanm 0:9b334a45a8ff 464 ETH_DMADescTypeDef *dmatxdesc;
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /* Process Locked */
bogdanm 0:9b334a45a8ff 467 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 470 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
bogdanm 0:9b334a45a8ff 473 heth->TxDesc = DMATxDescTab;
bogdanm 0:9b334a45a8ff 474
bogdanm 0:9b334a45a8ff 475 /* Fill each DMATxDesc descriptor with the right values */
bogdanm 0:9b334a45a8ff 476 for(i=0; i < TxBuffCount; i++)
bogdanm 0:9b334a45a8ff 477 {
bogdanm 0:9b334a45a8ff 478 /* Get the pointer on the ith member of the Tx Desc list */
bogdanm 0:9b334a45a8ff 479 dmatxdesc = DMATxDescTab + i;
bogdanm 0:9b334a45a8ff 480
bogdanm 0:9b334a45a8ff 481 /* Set Second Address Chained bit */
bogdanm 0:9b334a45a8ff 482 dmatxdesc->Status = ETH_DMATXDESC_TCH;
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /* Set Buffer1 address pointer */
bogdanm 0:9b334a45a8ff 485 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
bogdanm 0:9b334a45a8ff 488 {
bogdanm 0:9b334a45a8ff 489 /* Set the DMA Tx descriptors checksum insertion */
bogdanm 0:9b334a45a8ff 490 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
bogdanm 0:9b334a45a8ff 491 }
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
bogdanm 0:9b334a45a8ff 494 if(i < (TxBuffCount-1))
bogdanm 0:9b334a45a8ff 495 {
bogdanm 0:9b334a45a8ff 496 /* Set next descriptor address register with next descriptor base address */
bogdanm 0:9b334a45a8ff 497 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
bogdanm 0:9b334a45a8ff 498 }
bogdanm 0:9b334a45a8ff 499 else
bogdanm 0:9b334a45a8ff 500 {
bogdanm 0:9b334a45a8ff 501 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
bogdanm 0:9b334a45a8ff 502 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
bogdanm 0:9b334a45a8ff 503 }
bogdanm 0:9b334a45a8ff 504 }
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 /* Set Transmit Descriptor List Address Register */
bogdanm 0:9b334a45a8ff 507 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
bogdanm 0:9b334a45a8ff 508
bogdanm 0:9b334a45a8ff 509 /* Set ETH HAL State to Ready */
bogdanm 0:9b334a45a8ff 510 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 511
bogdanm 0:9b334a45a8ff 512 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 513 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 514
bogdanm 0:9b334a45a8ff 515 /* Return function status */
bogdanm 0:9b334a45a8ff 516 return HAL_OK;
bogdanm 0:9b334a45a8ff 517 }
bogdanm 0:9b334a45a8ff 518
bogdanm 0:9b334a45a8ff 519 /**
bogdanm 0:9b334a45a8ff 520 * @brief Initializes the DMA Rx descriptors in chain mode.
bogdanm 0:9b334a45a8ff 521 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 522 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 523 * @param DMARxDescTab: Pointer to the first Rx desc list
bogdanm 0:9b334a45a8ff 524 * @param RxBuff: Pointer to the first RxBuffer list
bogdanm 0:9b334a45a8ff 525 * @param RxBuffCount: Number of the used Rx desc in the list
bogdanm 0:9b334a45a8ff 526 * @retval HAL status
bogdanm 0:9b334a45a8ff 527 */
bogdanm 0:9b334a45a8ff 528 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
bogdanm 0:9b334a45a8ff 529 {
bogdanm 0:9b334a45a8ff 530 uint32_t i = 0;
bogdanm 0:9b334a45a8ff 531 ETH_DMADescTypeDef *DMARxDesc;
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 /* Process Locked */
bogdanm 0:9b334a45a8ff 534 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 537 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
bogdanm 0:9b334a45a8ff 540 heth->RxDesc = DMARxDescTab;
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /* Fill each DMARxDesc descriptor with the right values */
bogdanm 0:9b334a45a8ff 543 for(i=0; i < RxBuffCount; i++)
bogdanm 0:9b334a45a8ff 544 {
bogdanm 0:9b334a45a8ff 545 /* Get the pointer on the ith member of the Rx Desc list */
bogdanm 0:9b334a45a8ff 546 DMARxDesc = DMARxDescTab+i;
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 /* Set Own bit of the Rx descriptor Status */
bogdanm 0:9b334a45a8ff 549 DMARxDesc->Status = ETH_DMARXDESC_OWN;
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /* Set Buffer1 size and Second Address Chained bit */
bogdanm 0:9b334a45a8ff 552 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
bogdanm 0:9b334a45a8ff 553
bogdanm 0:9b334a45a8ff 554 /* Set Buffer1 address pointer */
bogdanm 0:9b334a45a8ff 555 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
bogdanm 0:9b334a45a8ff 558 {
bogdanm 0:9b334a45a8ff 559 /* Enable Ethernet DMA Rx Descriptor interrupt */
bogdanm 0:9b334a45a8ff 560 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
bogdanm 0:9b334a45a8ff 561 }
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
bogdanm 0:9b334a45a8ff 564 if(i < (RxBuffCount-1))
bogdanm 0:9b334a45a8ff 565 {
bogdanm 0:9b334a45a8ff 566 /* Set next descriptor address register with next descriptor base address */
bogdanm 0:9b334a45a8ff 567 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
bogdanm 0:9b334a45a8ff 568 }
bogdanm 0:9b334a45a8ff 569 else
bogdanm 0:9b334a45a8ff 570 {
bogdanm 0:9b334a45a8ff 571 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
bogdanm 0:9b334a45a8ff 572 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
bogdanm 0:9b334a45a8ff 573 }
bogdanm 0:9b334a45a8ff 574 }
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 /* Set Receive Descriptor List Address Register */
bogdanm 0:9b334a45a8ff 577 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /* Set ETH HAL State to Ready */
bogdanm 0:9b334a45a8ff 580 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 581
bogdanm 0:9b334a45a8ff 582 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 583 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 /* Return function status */
bogdanm 0:9b334a45a8ff 586 return HAL_OK;
bogdanm 0:9b334a45a8ff 587 }
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589 /**
bogdanm 0:9b334a45a8ff 590 * @brief Initializes the ETH MSP.
bogdanm 0:9b334a45a8ff 591 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 592 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 593 * @retval None
bogdanm 0:9b334a45a8ff 594 */
bogdanm 0:9b334a45a8ff 595 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 596 {
bogdanm 0:9b334a45a8ff 597 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 598 the HAL_ETH_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 599 */
bogdanm 0:9b334a45a8ff 600 }
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 /**
bogdanm 0:9b334a45a8ff 603 * @brief DeInitializes ETH MSP.
bogdanm 0:9b334a45a8ff 604 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 605 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 606 * @retval None
bogdanm 0:9b334a45a8ff 607 */
bogdanm 0:9b334a45a8ff 608 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 609 {
bogdanm 0:9b334a45a8ff 610 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 611 the HAL_ETH_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 612 */
bogdanm 0:9b334a45a8ff 613 }
bogdanm 0:9b334a45a8ff 614
bogdanm 0:9b334a45a8ff 615 /**
bogdanm 0:9b334a45a8ff 616 * @}
bogdanm 0:9b334a45a8ff 617 */
bogdanm 0:9b334a45a8ff 618
bogdanm 0:9b334a45a8ff 619 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
bogdanm 0:9b334a45a8ff 620 * @brief Data transfers functions
bogdanm 0:9b334a45a8ff 621 *
bogdanm 0:9b334a45a8ff 622 @verbatim
bogdanm 0:9b334a45a8ff 623 ==============================================================================
bogdanm 0:9b334a45a8ff 624 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 625 ==============================================================================
bogdanm 0:9b334a45a8ff 626 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 627 (+) Transmit a frame
bogdanm 0:9b334a45a8ff 628 HAL_ETH_TransmitFrame();
bogdanm 0:9b334a45a8ff 629 (+) Receive a frame
bogdanm 0:9b334a45a8ff 630 HAL_ETH_GetReceivedFrame();
bogdanm 0:9b334a45a8ff 631 HAL_ETH_GetReceivedFrame_IT();
bogdanm 0:9b334a45a8ff 632 (+) Read from an External PHY register
bogdanm 0:9b334a45a8ff 633 HAL_ETH_ReadPHYRegister();
bogdanm 0:9b334a45a8ff 634 (+) Write to an External PHY register
bogdanm 0:9b334a45a8ff 635 HAL_ETH_WritePHYRegister();
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 @endverbatim
bogdanm 0:9b334a45a8ff 638
bogdanm 0:9b334a45a8ff 639 * @{
bogdanm 0:9b334a45a8ff 640 */
bogdanm 0:9b334a45a8ff 641
bogdanm 0:9b334a45a8ff 642 /**
bogdanm 0:9b334a45a8ff 643 * @brief Sends an Ethernet frame.
bogdanm 0:9b334a45a8ff 644 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 645 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 646 * @param FrameLength: Amount of data to be sent
bogdanm 0:9b334a45a8ff 647 * @retval HAL status
bogdanm 0:9b334a45a8ff 648 */
bogdanm 0:9b334a45a8ff 649 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
bogdanm 0:9b334a45a8ff 650 {
bogdanm 0:9b334a45a8ff 651 uint32_t bufcount = 0, size = 0, i = 0;
bogdanm 0:9b334a45a8ff 652
bogdanm 0:9b334a45a8ff 653 /* Process Locked */
bogdanm 0:9b334a45a8ff 654 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 655
bogdanm 0:9b334a45a8ff 656 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 657 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 if (FrameLength == 0)
bogdanm 0:9b334a45a8ff 660 {
bogdanm 0:9b334a45a8ff 661 /* Set ETH HAL state to READY */
bogdanm 0:9b334a45a8ff 662 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 663
bogdanm 0:9b334a45a8ff 664 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 665 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 666
bogdanm 0:9b334a45a8ff 667 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 668 }
bogdanm 0:9b334a45a8ff 669
bogdanm 0:9b334a45a8ff 670 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
bogdanm 0:9b334a45a8ff 671 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 672 {
bogdanm 0:9b334a45a8ff 673 /* OWN bit set */
bogdanm 0:9b334a45a8ff 674 heth->State = HAL_ETH_STATE_BUSY_TX;
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 677 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 678
bogdanm 0:9b334a45a8ff 679 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 680 }
bogdanm 0:9b334a45a8ff 681
bogdanm 0:9b334a45a8ff 682 /* Get the number of needed Tx buffers for the current frame */
bogdanm 0:9b334a45a8ff 683 if (FrameLength > ETH_TX_BUF_SIZE)
bogdanm 0:9b334a45a8ff 684 {
bogdanm 0:9b334a45a8ff 685 bufcount = FrameLength/ETH_TX_BUF_SIZE;
bogdanm 0:9b334a45a8ff 686 if (FrameLength % ETH_TX_BUF_SIZE)
bogdanm 0:9b334a45a8ff 687 {
bogdanm 0:9b334a45a8ff 688 bufcount++;
bogdanm 0:9b334a45a8ff 689 }
bogdanm 0:9b334a45a8ff 690 }
bogdanm 0:9b334a45a8ff 691 else
bogdanm 0:9b334a45a8ff 692 {
bogdanm 0:9b334a45a8ff 693 bufcount = 1;
bogdanm 0:9b334a45a8ff 694 }
bogdanm 0:9b334a45a8ff 695 if (bufcount == 1)
bogdanm 0:9b334a45a8ff 696 {
bogdanm 0:9b334a45a8ff 697 /* Set LAST and FIRST segment */
bogdanm 0:9b334a45a8ff 698 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
bogdanm 0:9b334a45a8ff 699 /* Set frame size */
bogdanm 0:9b334a45a8ff 700 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
bogdanm 0:9b334a45a8ff 701 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
bogdanm 0:9b334a45a8ff 702 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
bogdanm 0:9b334a45a8ff 703 /* Point to next descriptor */
bogdanm 0:9b334a45a8ff 704 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 705 }
bogdanm 0:9b334a45a8ff 706 else
bogdanm 0:9b334a45a8ff 707 {
bogdanm 0:9b334a45a8ff 708 for (i=0; i< bufcount; i++)
bogdanm 0:9b334a45a8ff 709 {
bogdanm 0:9b334a45a8ff 710 /* Clear FIRST and LAST segment bits */
bogdanm 0:9b334a45a8ff 711 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 if (i == 0)
bogdanm 0:9b334a45a8ff 714 {
bogdanm 0:9b334a45a8ff 715 /* Setting the first segment bit */
bogdanm 0:9b334a45a8ff 716 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
bogdanm 0:9b334a45a8ff 717 }
bogdanm 0:9b334a45a8ff 718
bogdanm 0:9b334a45a8ff 719 /* Program size */
bogdanm 0:9b334a45a8ff 720 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
bogdanm 0:9b334a45a8ff 721
bogdanm 0:9b334a45a8ff 722 if (i == (bufcount-1))
bogdanm 0:9b334a45a8ff 723 {
bogdanm 0:9b334a45a8ff 724 /* Setting the last segment bit */
bogdanm 0:9b334a45a8ff 725 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
bogdanm 0:9b334a45a8ff 726 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
bogdanm 0:9b334a45a8ff 727 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
bogdanm 0:9b334a45a8ff 728 }
bogdanm 0:9b334a45a8ff 729
bogdanm 0:9b334a45a8ff 730 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
bogdanm 0:9b334a45a8ff 731 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
bogdanm 0:9b334a45a8ff 732 /* point to next descriptor */
bogdanm 0:9b334a45a8ff 733 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 734 }
bogdanm 0:9b334a45a8ff 735 }
bogdanm 0:9b334a45a8ff 736
bogdanm 0:9b334a45a8ff 737 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
bogdanm 0:9b334a45a8ff 738 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 739 {
bogdanm 0:9b334a45a8ff 740 /* Clear TBUS ETHERNET DMA flag */
bogdanm 0:9b334a45a8ff 741 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
bogdanm 0:9b334a45a8ff 742 /* Resume DMA transmission*/
bogdanm 0:9b334a45a8ff 743 (heth->Instance)->DMATPDR = 0;
bogdanm 0:9b334a45a8ff 744 }
bogdanm 0:9b334a45a8ff 745
bogdanm 0:9b334a45a8ff 746 /* Set ETH HAL State to Ready */
bogdanm 0:9b334a45a8ff 747 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 748
bogdanm 0:9b334a45a8ff 749 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 750 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 /* Return function status */
bogdanm 0:9b334a45a8ff 753 return HAL_OK;
bogdanm 0:9b334a45a8ff 754 }
bogdanm 0:9b334a45a8ff 755
bogdanm 0:9b334a45a8ff 756 /**
bogdanm 0:9b334a45a8ff 757 * @brief Checks for received frames.
bogdanm 0:9b334a45a8ff 758 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 759 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 760 * @retval HAL status
bogdanm 0:9b334a45a8ff 761 */
bogdanm 0:9b334a45a8ff 762 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 763 {
bogdanm 0:9b334a45a8ff 764 uint32_t framelength = 0;
bogdanm 0:9b334a45a8ff 765
bogdanm 0:9b334a45a8ff 766 /* Process Locked */
bogdanm 0:9b334a45a8ff 767 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 768
bogdanm 0:9b334a45a8ff 769 /* Check the ETH state to BUSY */
bogdanm 0:9b334a45a8ff 770 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 771
bogdanm 0:9b334a45a8ff 772 /* Check if segment is not owned by DMA */
bogdanm 0:9b334a45a8ff 773 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
bogdanm 0:9b334a45a8ff 774 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
bogdanm 0:9b334a45a8ff 775 {
bogdanm 0:9b334a45a8ff 776 /* Check if last segment */
bogdanm 0:9b334a45a8ff 777 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
bogdanm 0:9b334a45a8ff 778 {
bogdanm 0:9b334a45a8ff 779 /* increment segment count */
bogdanm 0:9b334a45a8ff 780 (heth->RxFrameInfos).SegCount++;
bogdanm 0:9b334a45a8ff 781
bogdanm 0:9b334a45a8ff 782 /* Check if last segment is first segment: one segment contains the frame */
bogdanm 0:9b334a45a8ff 783 if ((heth->RxFrameInfos).SegCount == 1)
bogdanm 0:9b334a45a8ff 784 {
bogdanm 0:9b334a45a8ff 785 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
bogdanm 0:9b334a45a8ff 786 }
bogdanm 0:9b334a45a8ff 787
bogdanm 0:9b334a45a8ff 788 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
bogdanm 0:9b334a45a8ff 789
bogdanm 0:9b334a45a8ff 790 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
bogdanm 0:9b334a45a8ff 791 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
bogdanm 0:9b334a45a8ff 792 heth->RxFrameInfos.length = framelength;
bogdanm 0:9b334a45a8ff 793
bogdanm 0:9b334a45a8ff 794 /* Get the address of the buffer start address */
bogdanm 0:9b334a45a8ff 795 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
bogdanm 0:9b334a45a8ff 796 /* point to next descriptor */
bogdanm 0:9b334a45a8ff 797 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 798
bogdanm 0:9b334a45a8ff 799 /* Set HAL State to Ready */
bogdanm 0:9b334a45a8ff 800 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 801
bogdanm 0:9b334a45a8ff 802 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 803 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 804
bogdanm 0:9b334a45a8ff 805 /* Return function status */
bogdanm 0:9b334a45a8ff 806 return HAL_OK;
bogdanm 0:9b334a45a8ff 807 }
bogdanm 0:9b334a45a8ff 808 /* Check if first segment */
bogdanm 0:9b334a45a8ff 809 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 810 {
bogdanm 0:9b334a45a8ff 811 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
bogdanm 0:9b334a45a8ff 812 (heth->RxFrameInfos).LSRxDesc = NULL;
bogdanm 0:9b334a45a8ff 813 (heth->RxFrameInfos).SegCount = 1;
bogdanm 0:9b334a45a8ff 814 /* Point to next descriptor */
bogdanm 0:9b334a45a8ff 815 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 816 }
bogdanm 0:9b334a45a8ff 817 /* Check if intermediate segment */
bogdanm 0:9b334a45a8ff 818 else
bogdanm 0:9b334a45a8ff 819 {
bogdanm 0:9b334a45a8ff 820 (heth->RxFrameInfos).SegCount++;
bogdanm 0:9b334a45a8ff 821 /* Point to next descriptor */
bogdanm 0:9b334a45a8ff 822 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 823 }
bogdanm 0:9b334a45a8ff 824 }
bogdanm 0:9b334a45a8ff 825
bogdanm 0:9b334a45a8ff 826 /* Set ETH HAL State to Ready */
bogdanm 0:9b334a45a8ff 827 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 828
bogdanm 0:9b334a45a8ff 829 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 830 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 /* Return function status */
bogdanm 0:9b334a45a8ff 833 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 834 }
bogdanm 0:9b334a45a8ff 835
bogdanm 0:9b334a45a8ff 836 /**
bogdanm 0:9b334a45a8ff 837 * @brief Gets the Received frame in interrupt mode.
bogdanm 0:9b334a45a8ff 838 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 839 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 840 * @retval HAL status
bogdanm 0:9b334a45a8ff 841 */
bogdanm 0:9b334a45a8ff 842 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 843 {
bogdanm 0:9b334a45a8ff 844 uint32_t descriptorscancounter = 0;
bogdanm 0:9b334a45a8ff 845
bogdanm 0:9b334a45a8ff 846 /* Process Locked */
bogdanm 0:9b334a45a8ff 847 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 848
bogdanm 0:9b334a45a8ff 849 /* Set ETH HAL State to BUSY */
bogdanm 0:9b334a45a8ff 850 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 851
bogdanm 0:9b334a45a8ff 852 /* Scan descriptors owned by CPU */
bogdanm 0:9b334a45a8ff 853 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
bogdanm 0:9b334a45a8ff 854 {
bogdanm 0:9b334a45a8ff 855 /* Just for security */
bogdanm 0:9b334a45a8ff 856 descriptorscancounter++;
bogdanm 0:9b334a45a8ff 857
bogdanm 0:9b334a45a8ff 858 /* Check if first segment in frame */
bogdanm 0:9b334a45a8ff 859 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
bogdanm 0:9b334a45a8ff 860 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
bogdanm 0:9b334a45a8ff 861 {
bogdanm 0:9b334a45a8ff 862 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
bogdanm 0:9b334a45a8ff 863 heth->RxFrameInfos.SegCount = 1;
bogdanm 0:9b334a45a8ff 864 /* Point to next descriptor */
bogdanm 0:9b334a45a8ff 865 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 866 }
bogdanm 0:9b334a45a8ff 867 /* Check if intermediate segment */
bogdanm 0:9b334a45a8ff 868 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
bogdanm 0:9b334a45a8ff 869 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 870 {
bogdanm 0:9b334a45a8ff 871 /* Increment segment count */
bogdanm 0:9b334a45a8ff 872 (heth->RxFrameInfos.SegCount)++;
bogdanm 0:9b334a45a8ff 873 /* Point to next descriptor */
bogdanm 0:9b334a45a8ff 874 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 875 }
bogdanm 0:9b334a45a8ff 876 /* Should be last segment */
bogdanm 0:9b334a45a8ff 877 else
bogdanm 0:9b334a45a8ff 878 {
bogdanm 0:9b334a45a8ff 879 /* Last segment */
bogdanm 0:9b334a45a8ff 880 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
bogdanm 0:9b334a45a8ff 881
bogdanm 0:9b334a45a8ff 882 /* Increment segment count */
bogdanm 0:9b334a45a8ff 883 (heth->RxFrameInfos.SegCount)++;
bogdanm 0:9b334a45a8ff 884
bogdanm 0:9b334a45a8ff 885 /* Check if last segment is first segment: one segment contains the frame */
bogdanm 0:9b334a45a8ff 886 if ((heth->RxFrameInfos.SegCount) == 1)
bogdanm 0:9b334a45a8ff 887 {
bogdanm 0:9b334a45a8ff 888 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
bogdanm 0:9b334a45a8ff 889 }
bogdanm 0:9b334a45a8ff 890
bogdanm 0:9b334a45a8ff 891 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
bogdanm 0:9b334a45a8ff 892 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 /* Get the address of the buffer start address */
bogdanm 0:9b334a45a8ff 895 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
bogdanm 0:9b334a45a8ff 896
bogdanm 0:9b334a45a8ff 897 /* Point to next descriptor */
bogdanm 0:9b334a45a8ff 898 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm 0:9b334a45a8ff 899
bogdanm 0:9b334a45a8ff 900 /* Set HAL State to Ready */
bogdanm 0:9b334a45a8ff 901 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 902
bogdanm 0:9b334a45a8ff 903 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 904 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 905
bogdanm 0:9b334a45a8ff 906 /* Return function status */
bogdanm 0:9b334a45a8ff 907 return HAL_OK;
bogdanm 0:9b334a45a8ff 908 }
bogdanm 0:9b334a45a8ff 909 }
bogdanm 0:9b334a45a8ff 910
bogdanm 0:9b334a45a8ff 911 /* Set HAL State to Ready */
bogdanm 0:9b334a45a8ff 912 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 913
bogdanm 0:9b334a45a8ff 914 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 915 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 916
bogdanm 0:9b334a45a8ff 917 /* Return function status */
bogdanm 0:9b334a45a8ff 918 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 919 }
bogdanm 0:9b334a45a8ff 920
bogdanm 0:9b334a45a8ff 921 /**
bogdanm 0:9b334a45a8ff 922 * @brief This function handles ETH interrupt request.
bogdanm 0:9b334a45a8ff 923 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 924 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 925 * @retval HAL status
bogdanm 0:9b334a45a8ff 926 */
bogdanm 0:9b334a45a8ff 927 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 928 {
bogdanm 0:9b334a45a8ff 929 /* Frame received */
bogdanm 0:9b334a45a8ff 930 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
bogdanm 0:9b334a45a8ff 931 {
bogdanm 0:9b334a45a8ff 932 /* Receive complete callback */
bogdanm 0:9b334a45a8ff 933 HAL_ETH_RxCpltCallback(heth);
bogdanm 0:9b334a45a8ff 934
bogdanm 0:9b334a45a8ff 935 /* Clear the Eth DMA Rx IT pending bits */
bogdanm 0:9b334a45a8ff 936 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
bogdanm 0:9b334a45a8ff 937
bogdanm 0:9b334a45a8ff 938 /* Set HAL State to Ready */
bogdanm 0:9b334a45a8ff 939 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 940
bogdanm 0:9b334a45a8ff 941 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 942 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 943
bogdanm 0:9b334a45a8ff 944 }
bogdanm 0:9b334a45a8ff 945 /* Frame transmitted */
bogdanm 0:9b334a45a8ff 946 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
bogdanm 0:9b334a45a8ff 947 {
bogdanm 0:9b334a45a8ff 948 /* Transfer complete callback */
bogdanm 0:9b334a45a8ff 949 HAL_ETH_TxCpltCallback(heth);
bogdanm 0:9b334a45a8ff 950
bogdanm 0:9b334a45a8ff 951 /* Clear the Eth DMA Tx IT pending bits */
bogdanm 0:9b334a45a8ff 952 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
bogdanm 0:9b334a45a8ff 953
bogdanm 0:9b334a45a8ff 954 /* Set HAL State to Ready */
bogdanm 0:9b334a45a8ff 955 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 956
bogdanm 0:9b334a45a8ff 957 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 958 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 959 }
bogdanm 0:9b334a45a8ff 960
bogdanm 0:9b334a45a8ff 961 /* Clear the interrupt flags */
bogdanm 0:9b334a45a8ff 962 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
bogdanm 0:9b334a45a8ff 963
bogdanm 0:9b334a45a8ff 964 /* ETH DMA Error */
bogdanm 0:9b334a45a8ff 965 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
bogdanm 0:9b334a45a8ff 966 {
bogdanm 0:9b334a45a8ff 967 /* Ethernet Error callback */
bogdanm 0:9b334a45a8ff 968 HAL_ETH_ErrorCallback(heth);
bogdanm 0:9b334a45a8ff 969
bogdanm 0:9b334a45a8ff 970 /* Clear the interrupt flags */
bogdanm 0:9b334a45a8ff 971 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
bogdanm 0:9b334a45a8ff 972
bogdanm 0:9b334a45a8ff 973 /* Set HAL State to Ready */
bogdanm 0:9b334a45a8ff 974 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 975
bogdanm 0:9b334a45a8ff 976 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 977 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 978 }
bogdanm 0:9b334a45a8ff 979 }
bogdanm 0:9b334a45a8ff 980
bogdanm 0:9b334a45a8ff 981 /**
bogdanm 0:9b334a45a8ff 982 * @brief Tx Transfer completed callbacks.
bogdanm 0:9b334a45a8ff 983 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 984 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 985 * @retval None
bogdanm 0:9b334a45a8ff 986 */
bogdanm 0:9b334a45a8ff 987 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 988 {
bogdanm 0:9b334a45a8ff 989 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 990 the HAL_ETH_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 991 */
bogdanm 0:9b334a45a8ff 992 }
bogdanm 0:9b334a45a8ff 993
bogdanm 0:9b334a45a8ff 994 /**
bogdanm 0:9b334a45a8ff 995 * @brief Rx Transfer completed callbacks.
bogdanm 0:9b334a45a8ff 996 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 997 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 998 * @retval None
bogdanm 0:9b334a45a8ff 999 */
bogdanm 0:9b334a45a8ff 1000 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1001 {
bogdanm 0:9b334a45a8ff 1002 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1003 the HAL_ETH_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1004 */
bogdanm 0:9b334a45a8ff 1005 }
bogdanm 0:9b334a45a8ff 1006
bogdanm 0:9b334a45a8ff 1007 /**
bogdanm 0:9b334a45a8ff 1008 * @brief Ethernet transfer error callbacks
bogdanm 0:9b334a45a8ff 1009 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1010 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1011 * @retval None
bogdanm 0:9b334a45a8ff 1012 */
bogdanm 0:9b334a45a8ff 1013 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1014 {
bogdanm 0:9b334a45a8ff 1015 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1016 the HAL_ETH_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1017 */
bogdanm 0:9b334a45a8ff 1018 }
bogdanm 0:9b334a45a8ff 1019
bogdanm 0:9b334a45a8ff 1020 /**
bogdanm 0:9b334a45a8ff 1021 * @brief Reads a PHY register
bogdanm 0:9b334a45a8ff 1022 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1023 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1024 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
bogdanm 0:9b334a45a8ff 1025 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1026 * PHY_BCR: Transceiver Basic Control Register,
bogdanm 0:9b334a45a8ff 1027 * PHY_BSR: Transceiver Basic Status Register.
bogdanm 0:9b334a45a8ff 1028 * More PHY register could be read depending on the used PHY
bogdanm 0:9b334a45a8ff 1029 * @param RegValue: PHY register value
bogdanm 0:9b334a45a8ff 1030 * @retval HAL status
bogdanm 0:9b334a45a8ff 1031 */
bogdanm 0:9b334a45a8ff 1032 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
bogdanm 0:9b334a45a8ff 1033 {
bogdanm 0:9b334a45a8ff 1034 uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1035 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 1036
bogdanm 0:9b334a45a8ff 1037 /* Check parameters */
bogdanm 0:9b334a45a8ff 1038 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
bogdanm 0:9b334a45a8ff 1039
bogdanm 0:9b334a45a8ff 1040 /* Check the ETH peripheral state */
bogdanm 0:9b334a45a8ff 1041 if(heth->State == HAL_ETH_STATE_BUSY_RD)
bogdanm 0:9b334a45a8ff 1042 {
bogdanm 0:9b334a45a8ff 1043 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1044 }
bogdanm 0:9b334a45a8ff 1045 /* Set ETH HAL State to BUSY_RD */
bogdanm 0:9b334a45a8ff 1046 heth->State = HAL_ETH_STATE_BUSY_RD;
bogdanm 0:9b334a45a8ff 1047
bogdanm 0:9b334a45a8ff 1048 /* Get the ETHERNET MACMIIAR value */
bogdanm 0:9b334a45a8ff 1049 tmpreg1 = heth->Instance->MACMIIAR;
bogdanm 0:9b334a45a8ff 1050
bogdanm 0:9b334a45a8ff 1051 /* Keep only the CSR Clock Range CR[2:0] bits value */
bogdanm 0:9b334a45a8ff 1052 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
bogdanm 0:9b334a45a8ff 1053
bogdanm 0:9b334a45a8ff 1054 /* Prepare the MII address register value */
bogdanm 0:9b334a45a8ff 1055 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
bogdanm 0:9b334a45a8ff 1056 tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
bogdanm 0:9b334a45a8ff 1057 tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
bogdanm 0:9b334a45a8ff 1058 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
bogdanm 0:9b334a45a8ff 1059
bogdanm 0:9b334a45a8ff 1060 /* Write the result value into the MII Address register */
bogdanm 0:9b334a45a8ff 1061 heth->Instance->MACMIIAR = tmpreg1;
bogdanm 0:9b334a45a8ff 1062
bogdanm 0:9b334a45a8ff 1063 /* Get tick */
bogdanm 0:9b334a45a8ff 1064 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1065
bogdanm 0:9b334a45a8ff 1066 /* Check for the Busy flag */
bogdanm 0:9b334a45a8ff 1067 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
bogdanm 0:9b334a45a8ff 1068 {
bogdanm 0:9b334a45a8ff 1069 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 1070 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
bogdanm 0:9b334a45a8ff 1071 {
bogdanm 0:9b334a45a8ff 1072 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1073
bogdanm 0:9b334a45a8ff 1074 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1075 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 1076
bogdanm 0:9b334a45a8ff 1077 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1078 }
bogdanm 0:9b334a45a8ff 1079
bogdanm 0:9b334a45a8ff 1080 tmpreg1 = heth->Instance->MACMIIAR;
bogdanm 0:9b334a45a8ff 1081 }
bogdanm 0:9b334a45a8ff 1082
bogdanm 0:9b334a45a8ff 1083 /* Get MACMIIDR value */
bogdanm 0:9b334a45a8ff 1084 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
bogdanm 0:9b334a45a8ff 1085
bogdanm 0:9b334a45a8ff 1086 /* Set ETH HAL State to READY */
bogdanm 0:9b334a45a8ff 1087 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1088
bogdanm 0:9b334a45a8ff 1089 /* Return function status */
bogdanm 0:9b334a45a8ff 1090 return HAL_OK;
bogdanm 0:9b334a45a8ff 1091 }
bogdanm 0:9b334a45a8ff 1092
bogdanm 0:9b334a45a8ff 1093 /**
bogdanm 0:9b334a45a8ff 1094 * @brief Writes to a PHY register.
bogdanm 0:9b334a45a8ff 1095 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1096 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1097 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
bogdanm 0:9b334a45a8ff 1098 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1099 * PHY_BCR: Transceiver Control Register.
bogdanm 0:9b334a45a8ff 1100 * More PHY register could be written depending on the used PHY
bogdanm 0:9b334a45a8ff 1101 * @param RegValue: the value to write
bogdanm 0:9b334a45a8ff 1102 * @retval HAL status
bogdanm 0:9b334a45a8ff 1103 */
bogdanm 0:9b334a45a8ff 1104 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
bogdanm 0:9b334a45a8ff 1105 {
bogdanm 0:9b334a45a8ff 1106 uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1107 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 1108
bogdanm 0:9b334a45a8ff 1109 /* Check parameters */
bogdanm 0:9b334a45a8ff 1110 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
bogdanm 0:9b334a45a8ff 1111
bogdanm 0:9b334a45a8ff 1112 /* Check the ETH peripheral state */
bogdanm 0:9b334a45a8ff 1113 if(heth->State == HAL_ETH_STATE_BUSY_WR)
bogdanm 0:9b334a45a8ff 1114 {
bogdanm 0:9b334a45a8ff 1115 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1116 }
bogdanm 0:9b334a45a8ff 1117 /* Set ETH HAL State to BUSY_WR */
bogdanm 0:9b334a45a8ff 1118 heth->State = HAL_ETH_STATE_BUSY_WR;
bogdanm 0:9b334a45a8ff 1119
bogdanm 0:9b334a45a8ff 1120 /* Get the ETHERNET MACMIIAR value */
bogdanm 0:9b334a45a8ff 1121 tmpreg1 = heth->Instance->MACMIIAR;
bogdanm 0:9b334a45a8ff 1122
bogdanm 0:9b334a45a8ff 1123 /* Keep only the CSR Clock Range CR[2:0] bits value */
bogdanm 0:9b334a45a8ff 1124 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
bogdanm 0:9b334a45a8ff 1125
bogdanm 0:9b334a45a8ff 1126 /* Prepare the MII register address value */
bogdanm 0:9b334a45a8ff 1127 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
bogdanm 0:9b334a45a8ff 1128 tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
bogdanm 0:9b334a45a8ff 1129 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
bogdanm 0:9b334a45a8ff 1130 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
bogdanm 0:9b334a45a8ff 1131
bogdanm 0:9b334a45a8ff 1132 /* Give the value to the MII data register */
bogdanm 0:9b334a45a8ff 1133 heth->Instance->MACMIIDR = (uint16_t)RegValue;
bogdanm 0:9b334a45a8ff 1134
bogdanm 0:9b334a45a8ff 1135 /* Write the result value into the MII Address register */
bogdanm 0:9b334a45a8ff 1136 heth->Instance->MACMIIAR = tmpreg1;
bogdanm 0:9b334a45a8ff 1137
bogdanm 0:9b334a45a8ff 1138 /* Get tick */
bogdanm 0:9b334a45a8ff 1139 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1140
bogdanm 0:9b334a45a8ff 1141 /* Check for the Busy flag */
bogdanm 0:9b334a45a8ff 1142 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
bogdanm 0:9b334a45a8ff 1143 {
bogdanm 0:9b334a45a8ff 1144 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 1145 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
bogdanm 0:9b334a45a8ff 1146 {
bogdanm 0:9b334a45a8ff 1147 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1148
bogdanm 0:9b334a45a8ff 1149 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1150 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 1151
bogdanm 0:9b334a45a8ff 1152 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1153 }
bogdanm 0:9b334a45a8ff 1154
bogdanm 0:9b334a45a8ff 1155 tmpreg1 = heth->Instance->MACMIIAR;
bogdanm 0:9b334a45a8ff 1156 }
bogdanm 0:9b334a45a8ff 1157
bogdanm 0:9b334a45a8ff 1158 /* Set ETH HAL State to READY */
bogdanm 0:9b334a45a8ff 1159 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1160
bogdanm 0:9b334a45a8ff 1161 /* Return function status */
bogdanm 0:9b334a45a8ff 1162 return HAL_OK;
bogdanm 0:9b334a45a8ff 1163 }
bogdanm 0:9b334a45a8ff 1164
bogdanm 0:9b334a45a8ff 1165 /**
bogdanm 0:9b334a45a8ff 1166 * @}
bogdanm 0:9b334a45a8ff 1167 */
bogdanm 0:9b334a45a8ff 1168
bogdanm 0:9b334a45a8ff 1169 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
bogdanm 0:9b334a45a8ff 1170 * @brief Peripheral Control functions
bogdanm 0:9b334a45a8ff 1171 *
bogdanm 0:9b334a45a8ff 1172 @verbatim
bogdanm 0:9b334a45a8ff 1173 ===============================================================================
bogdanm 0:9b334a45a8ff 1174 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 1175 ===============================================================================
bogdanm 0:9b334a45a8ff 1176 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 1177 (+) Enable MAC and DMA transmission and reception.
bogdanm 0:9b334a45a8ff 1178 HAL_ETH_Start();
bogdanm 0:9b334a45a8ff 1179 (+) Disable MAC and DMA transmission and reception.
bogdanm 0:9b334a45a8ff 1180 HAL_ETH_Stop();
bogdanm 0:9b334a45a8ff 1181 (+) Set the MAC configuration in runtime mode
bogdanm 0:9b334a45a8ff 1182 HAL_ETH_ConfigMAC();
bogdanm 0:9b334a45a8ff 1183 (+) Set the DMA configuration in runtime mode
bogdanm 0:9b334a45a8ff 1184 HAL_ETH_ConfigDMA();
bogdanm 0:9b334a45a8ff 1185
bogdanm 0:9b334a45a8ff 1186 @endverbatim
bogdanm 0:9b334a45a8ff 1187 * @{
bogdanm 0:9b334a45a8ff 1188 */
bogdanm 0:9b334a45a8ff 1189
bogdanm 0:9b334a45a8ff 1190 /**
bogdanm 0:9b334a45a8ff 1191 * @brief Enables Ethernet MAC and DMA reception/transmission
bogdanm 0:9b334a45a8ff 1192 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1193 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1194 * @retval HAL status
bogdanm 0:9b334a45a8ff 1195 */
bogdanm 0:9b334a45a8ff 1196 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1197 {
bogdanm 0:9b334a45a8ff 1198 /* Process Locked */
bogdanm 0:9b334a45a8ff 1199 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 1200
bogdanm 0:9b334a45a8ff 1201 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 1202 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1203
bogdanm 0:9b334a45a8ff 1204 /* Enable transmit state machine of the MAC for transmission on the MII */
bogdanm 0:9b334a45a8ff 1205 ETH_MACTransmissionEnable(heth);
bogdanm 0:9b334a45a8ff 1206
bogdanm 0:9b334a45a8ff 1207 /* Enable receive state machine of the MAC for reception from the MII */
bogdanm 0:9b334a45a8ff 1208 ETH_MACReceptionEnable(heth);
bogdanm 0:9b334a45a8ff 1209
bogdanm 0:9b334a45a8ff 1210 /* Flush Transmit FIFO */
bogdanm 0:9b334a45a8ff 1211 ETH_FlushTransmitFIFO(heth);
bogdanm 0:9b334a45a8ff 1212
bogdanm 0:9b334a45a8ff 1213 /* Start DMA transmission */
bogdanm 0:9b334a45a8ff 1214 ETH_DMATransmissionEnable(heth);
bogdanm 0:9b334a45a8ff 1215
bogdanm 0:9b334a45a8ff 1216 /* Start DMA reception */
bogdanm 0:9b334a45a8ff 1217 ETH_DMAReceptionEnable(heth);
bogdanm 0:9b334a45a8ff 1218
bogdanm 0:9b334a45a8ff 1219 /* Set the ETH state to READY*/
bogdanm 0:9b334a45a8ff 1220 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1221
bogdanm 0:9b334a45a8ff 1222 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1223 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 1224
bogdanm 0:9b334a45a8ff 1225 /* Return function status */
bogdanm 0:9b334a45a8ff 1226 return HAL_OK;
bogdanm 0:9b334a45a8ff 1227 }
bogdanm 0:9b334a45a8ff 1228
bogdanm 0:9b334a45a8ff 1229 /**
bogdanm 0:9b334a45a8ff 1230 * @brief Stop Ethernet MAC and DMA reception/transmission
bogdanm 0:9b334a45a8ff 1231 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1232 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1233 * @retval HAL status
bogdanm 0:9b334a45a8ff 1234 */
bogdanm 0:9b334a45a8ff 1235 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1236 {
bogdanm 0:9b334a45a8ff 1237 /* Process Locked */
bogdanm 0:9b334a45a8ff 1238 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 1239
bogdanm 0:9b334a45a8ff 1240 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 1241 heth->State = HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1242
bogdanm 0:9b334a45a8ff 1243 /* Stop DMA transmission */
bogdanm 0:9b334a45a8ff 1244 ETH_DMATransmissionDisable(heth);
bogdanm 0:9b334a45a8ff 1245
bogdanm 0:9b334a45a8ff 1246 /* Stop DMA reception */
bogdanm 0:9b334a45a8ff 1247 ETH_DMAReceptionDisable(heth);
bogdanm 0:9b334a45a8ff 1248
bogdanm 0:9b334a45a8ff 1249 /* Disable receive state machine of the MAC for reception from the MII */
bogdanm 0:9b334a45a8ff 1250 ETH_MACReceptionDisable(heth);
bogdanm 0:9b334a45a8ff 1251
bogdanm 0:9b334a45a8ff 1252 /* Flush Transmit FIFO */
bogdanm 0:9b334a45a8ff 1253 ETH_FlushTransmitFIFO(heth);
bogdanm 0:9b334a45a8ff 1254
bogdanm 0:9b334a45a8ff 1255 /* Disable transmit state machine of the MAC for transmission on the MII */
bogdanm 0:9b334a45a8ff 1256 ETH_MACTransmissionDisable(heth);
bogdanm 0:9b334a45a8ff 1257
bogdanm 0:9b334a45a8ff 1258 /* Set the ETH state*/
bogdanm 0:9b334a45a8ff 1259 heth->State = HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1260
bogdanm 0:9b334a45a8ff 1261 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1262 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 1263
bogdanm 0:9b334a45a8ff 1264 /* Return function status */
bogdanm 0:9b334a45a8ff 1265 return HAL_OK;
bogdanm 0:9b334a45a8ff 1266 }
bogdanm 0:9b334a45a8ff 1267
bogdanm 0:9b334a45a8ff 1268 /**
bogdanm 0:9b334a45a8ff 1269 * @brief Set ETH MAC Configuration.
bogdanm 0:9b334a45a8ff 1270 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1271 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1272 * @param macconf: MAC Configuration structure
bogdanm 0:9b334a45a8ff 1273 * @retval HAL status
bogdanm 0:9b334a45a8ff 1274 */
bogdanm 0:9b334a45a8ff 1275 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
bogdanm 0:9b334a45a8ff 1276 {
bogdanm 0:9b334a45a8ff 1277 uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1278
bogdanm 0:9b334a45a8ff 1279 /* Process Locked */
bogdanm 0:9b334a45a8ff 1280 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 1281
bogdanm 0:9b334a45a8ff 1282 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 1283 heth->State= HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1284
bogdanm 0:9b334a45a8ff 1285 assert_param(IS_ETH_SPEED(heth->Init.Speed));
bogdanm 0:9b334a45a8ff 1286 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
bogdanm 0:9b334a45a8ff 1287
bogdanm 0:9b334a45a8ff 1288 if (macconf != NULL)
bogdanm 0:9b334a45a8ff 1289 {
bogdanm 0:9b334a45a8ff 1290 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1291 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
bogdanm 0:9b334a45a8ff 1292 assert_param(IS_ETH_JABBER(macconf->Jabber));
bogdanm 0:9b334a45a8ff 1293 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
bogdanm 0:9b334a45a8ff 1294 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
bogdanm 0:9b334a45a8ff 1295 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
bogdanm 0:9b334a45a8ff 1296 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
bogdanm 0:9b334a45a8ff 1297 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
bogdanm 0:9b334a45a8ff 1298 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
bogdanm 0:9b334a45a8ff 1299 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
bogdanm 0:9b334a45a8ff 1300 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
bogdanm 0:9b334a45a8ff 1301 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
bogdanm 0:9b334a45a8ff 1302 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
bogdanm 0:9b334a45a8ff 1303 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
bogdanm 0:9b334a45a8ff 1304 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
bogdanm 0:9b334a45a8ff 1305 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
bogdanm 0:9b334a45a8ff 1306 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
bogdanm 0:9b334a45a8ff 1307 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
bogdanm 0:9b334a45a8ff 1308 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
bogdanm 0:9b334a45a8ff 1309 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
bogdanm 0:9b334a45a8ff 1310 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
bogdanm 0:9b334a45a8ff 1311 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
bogdanm 0:9b334a45a8ff 1312 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
bogdanm 0:9b334a45a8ff 1313 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
bogdanm 0:9b334a45a8ff 1314 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
bogdanm 0:9b334a45a8ff 1315 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
bogdanm 0:9b334a45a8ff 1316 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
bogdanm 0:9b334a45a8ff 1317 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
bogdanm 0:9b334a45a8ff 1318
bogdanm 0:9b334a45a8ff 1319 /*------------------------ ETHERNET MACCR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1320 /* Get the ETHERNET MACCR value */
bogdanm 0:9b334a45a8ff 1321 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1322 /* Clear WD, PCE, PS, TE and RE bits */
bogdanm 0:9b334a45a8ff 1323 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 1324
bogdanm 0:9b334a45a8ff 1325 tmpreg1 |= (uint32_t)(macconf->Watchdog |
bogdanm 0:9b334a45a8ff 1326 macconf->Jabber |
bogdanm 0:9b334a45a8ff 1327 macconf->InterFrameGap |
bogdanm 0:9b334a45a8ff 1328 macconf->CarrierSense |
bogdanm 0:9b334a45a8ff 1329 (heth->Init).Speed |
bogdanm 0:9b334a45a8ff 1330 macconf->ReceiveOwn |
bogdanm 0:9b334a45a8ff 1331 macconf->LoopbackMode |
bogdanm 0:9b334a45a8ff 1332 (heth->Init).DuplexMode |
bogdanm 0:9b334a45a8ff 1333 macconf->ChecksumOffload |
bogdanm 0:9b334a45a8ff 1334 macconf->RetryTransmission |
bogdanm 0:9b334a45a8ff 1335 macconf->AutomaticPadCRCStrip |
bogdanm 0:9b334a45a8ff 1336 macconf->BackOffLimit |
bogdanm 0:9b334a45a8ff 1337 macconf->DeferralCheck);
bogdanm 0:9b334a45a8ff 1338
bogdanm 0:9b334a45a8ff 1339 /* Write to ETHERNET MACCR */
bogdanm 0:9b334a45a8ff 1340 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1341
bogdanm 0:9b334a45a8ff 1342 /* Wait until the write operation will be taken into account :
bogdanm 0:9b334a45a8ff 1343 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1344 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1345 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1346 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1347
bogdanm 0:9b334a45a8ff 1348 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1349 /* Write to ETHERNET MACFFR */
bogdanm 0:9b334a45a8ff 1350 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
bogdanm 0:9b334a45a8ff 1351 macconf->SourceAddrFilter |
bogdanm 0:9b334a45a8ff 1352 macconf->PassControlFrames |
bogdanm 0:9b334a45a8ff 1353 macconf->BroadcastFramesReception |
bogdanm 0:9b334a45a8ff 1354 macconf->DestinationAddrFilter |
bogdanm 0:9b334a45a8ff 1355 macconf->PromiscuousMode |
bogdanm 0:9b334a45a8ff 1356 macconf->MulticastFramesFilter |
bogdanm 0:9b334a45a8ff 1357 macconf->UnicastFramesFilter);
bogdanm 0:9b334a45a8ff 1358
bogdanm 0:9b334a45a8ff 1359 /* Wait until the write operation will be taken into account :
bogdanm 0:9b334a45a8ff 1360 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1361 tmpreg1 = (heth->Instance)->MACFFR;
bogdanm 0:9b334a45a8ff 1362 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1363 (heth->Instance)->MACFFR = tmpreg1;
bogdanm 0:9b334a45a8ff 1364
bogdanm 0:9b334a45a8ff 1365 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
bogdanm 0:9b334a45a8ff 1366 /* Write to ETHERNET MACHTHR */
bogdanm 0:9b334a45a8ff 1367 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
bogdanm 0:9b334a45a8ff 1368
bogdanm 0:9b334a45a8ff 1369 /* Write to ETHERNET MACHTLR */
bogdanm 0:9b334a45a8ff 1370 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
bogdanm 0:9b334a45a8ff 1371 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1372
bogdanm 0:9b334a45a8ff 1373 /* Get the ETHERNET MACFCR value */
bogdanm 0:9b334a45a8ff 1374 tmpreg1 = (heth->Instance)->MACFCR;
bogdanm 0:9b334a45a8ff 1375 /* Clear xx bits */
bogdanm 0:9b334a45a8ff 1376 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 1377
bogdanm 0:9b334a45a8ff 1378 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16) |
bogdanm 0:9b334a45a8ff 1379 macconf->ZeroQuantaPause |
bogdanm 0:9b334a45a8ff 1380 macconf->PauseLowThreshold |
bogdanm 0:9b334a45a8ff 1381 macconf->UnicastPauseFrameDetect |
bogdanm 0:9b334a45a8ff 1382 macconf->ReceiveFlowControl |
bogdanm 0:9b334a45a8ff 1383 macconf->TransmitFlowControl);
bogdanm 0:9b334a45a8ff 1384
bogdanm 0:9b334a45a8ff 1385 /* Write to ETHERNET MACFCR */
bogdanm 0:9b334a45a8ff 1386 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1387
bogdanm 0:9b334a45a8ff 1388 /* Wait until the write operation will be taken into account :
bogdanm 0:9b334a45a8ff 1389 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1390 tmpreg1 = (heth->Instance)->MACFCR;
bogdanm 0:9b334a45a8ff 1391 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1392 (heth->Instance)->MACFCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1393
bogdanm 0:9b334a45a8ff 1394 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
bogdanm 0:9b334a45a8ff 1395 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
bogdanm 0:9b334a45a8ff 1396 macconf->VLANTagIdentifier);
bogdanm 0:9b334a45a8ff 1397
bogdanm 0:9b334a45a8ff 1398 /* Wait until the write operation will be taken into account :
bogdanm 0:9b334a45a8ff 1399 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1400 tmpreg1 = (heth->Instance)->MACVLANTR;
bogdanm 0:9b334a45a8ff 1401 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1402 (heth->Instance)->MACVLANTR = tmpreg1;
bogdanm 0:9b334a45a8ff 1403 }
bogdanm 0:9b334a45a8ff 1404 else /* macconf == NULL : here we just configure Speed and Duplex mode */
bogdanm 0:9b334a45a8ff 1405 {
bogdanm 0:9b334a45a8ff 1406 /*------------------------ ETHERNET MACCR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1407 /* Get the ETHERNET MACCR value */
bogdanm 0:9b334a45a8ff 1408 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1409
bogdanm 0:9b334a45a8ff 1410 /* Clear FES and DM bits */
bogdanm 0:9b334a45a8ff 1411 tmpreg1 &= ~((uint32_t)0x00004800);
bogdanm 0:9b334a45a8ff 1412
bogdanm 0:9b334a45a8ff 1413 tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
bogdanm 0:9b334a45a8ff 1414
bogdanm 0:9b334a45a8ff 1415 /* Write to ETHERNET MACCR */
bogdanm 0:9b334a45a8ff 1416 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1417
bogdanm 0:9b334a45a8ff 1418 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1419 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1420 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1421 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1422 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1423 }
bogdanm 0:9b334a45a8ff 1424
bogdanm 0:9b334a45a8ff 1425 /* Set the ETH state to Ready */
bogdanm 0:9b334a45a8ff 1426 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1427
bogdanm 0:9b334a45a8ff 1428 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1429 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 1430
bogdanm 0:9b334a45a8ff 1431 /* Return function status */
bogdanm 0:9b334a45a8ff 1432 return HAL_OK;
bogdanm 0:9b334a45a8ff 1433 }
bogdanm 0:9b334a45a8ff 1434
bogdanm 0:9b334a45a8ff 1435 /**
bogdanm 0:9b334a45a8ff 1436 * @brief Sets ETH DMA Configuration.
bogdanm 0:9b334a45a8ff 1437 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1438 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1439 * @param dmaconf: DMA Configuration structure
bogdanm 0:9b334a45a8ff 1440 * @retval HAL status
bogdanm 0:9b334a45a8ff 1441 */
bogdanm 0:9b334a45a8ff 1442 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
bogdanm 0:9b334a45a8ff 1443 {
bogdanm 0:9b334a45a8ff 1444 uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1445
bogdanm 0:9b334a45a8ff 1446 /* Process Locked */
bogdanm 0:9b334a45a8ff 1447 __HAL_LOCK(heth);
bogdanm 0:9b334a45a8ff 1448
bogdanm 0:9b334a45a8ff 1449 /* Set the ETH peripheral state to BUSY */
bogdanm 0:9b334a45a8ff 1450 heth->State= HAL_ETH_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1451
bogdanm 0:9b334a45a8ff 1452 /* Check parameters */
bogdanm 0:9b334a45a8ff 1453 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
bogdanm 0:9b334a45a8ff 1454 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
bogdanm 0:9b334a45a8ff 1455 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
bogdanm 0:9b334a45a8ff 1456 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
bogdanm 0:9b334a45a8ff 1457 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
bogdanm 0:9b334a45a8ff 1458 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
bogdanm 0:9b334a45a8ff 1459 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
bogdanm 0:9b334a45a8ff 1460 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
bogdanm 0:9b334a45a8ff 1461 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
bogdanm 0:9b334a45a8ff 1462 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
bogdanm 0:9b334a45a8ff 1463 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
bogdanm 0:9b334a45a8ff 1464 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
bogdanm 0:9b334a45a8ff 1465 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
bogdanm 0:9b334a45a8ff 1466 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
bogdanm 0:9b334a45a8ff 1467 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
bogdanm 0:9b334a45a8ff 1468 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
bogdanm 0:9b334a45a8ff 1469
bogdanm 0:9b334a45a8ff 1470 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1471 /* Get the ETHERNET DMAOMR value */
bogdanm 0:9b334a45a8ff 1472 tmpreg1 = (heth->Instance)->DMAOMR;
bogdanm 0:9b334a45a8ff 1473 /* Clear xx bits */
bogdanm 0:9b334a45a8ff 1474 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 1475
bogdanm 0:9b334a45a8ff 1476 tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
bogdanm 0:9b334a45a8ff 1477 dmaconf->ReceiveStoreForward |
bogdanm 0:9b334a45a8ff 1478 dmaconf->FlushReceivedFrame |
bogdanm 0:9b334a45a8ff 1479 dmaconf->TransmitStoreForward |
bogdanm 0:9b334a45a8ff 1480 dmaconf->TransmitThresholdControl |
bogdanm 0:9b334a45a8ff 1481 dmaconf->ForwardErrorFrames |
bogdanm 0:9b334a45a8ff 1482 dmaconf->ForwardUndersizedGoodFrames |
bogdanm 0:9b334a45a8ff 1483 dmaconf->ReceiveThresholdControl |
bogdanm 0:9b334a45a8ff 1484 dmaconf->SecondFrameOperate);
bogdanm 0:9b334a45a8ff 1485
bogdanm 0:9b334a45a8ff 1486 /* Write to ETHERNET DMAOMR */
bogdanm 0:9b334a45a8ff 1487 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1488
bogdanm 0:9b334a45a8ff 1489 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1490 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1491 tmpreg1 = (heth->Instance)->DMAOMR;
bogdanm 0:9b334a45a8ff 1492 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1493 (heth->Instance)->DMAOMR = tmpreg1;
bogdanm 0:9b334a45a8ff 1494
bogdanm 0:9b334a45a8ff 1495 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1496 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
bogdanm 0:9b334a45a8ff 1497 dmaconf->FixedBurst |
bogdanm 0:9b334a45a8ff 1498 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
bogdanm 0:9b334a45a8ff 1499 dmaconf->TxDMABurstLength |
bogdanm 0:9b334a45a8ff 1500 dmaconf->EnhancedDescriptorFormat |
bogdanm 0:9b334a45a8ff 1501 (dmaconf->DescriptorSkipLength << 2) |
bogdanm 0:9b334a45a8ff 1502 dmaconf->DMAArbitration |
bogdanm 0:9b334a45a8ff 1503 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
bogdanm 0:9b334a45a8ff 1504
bogdanm 0:9b334a45a8ff 1505 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1506 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1507 tmpreg1 = (heth->Instance)->DMABMR;
bogdanm 0:9b334a45a8ff 1508 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1509 (heth->Instance)->DMABMR = tmpreg1;
bogdanm 0:9b334a45a8ff 1510
bogdanm 0:9b334a45a8ff 1511 /* Set the ETH state to Ready */
bogdanm 0:9b334a45a8ff 1512 heth->State= HAL_ETH_STATE_READY;
bogdanm 0:9b334a45a8ff 1513
bogdanm 0:9b334a45a8ff 1514 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1515 __HAL_UNLOCK(heth);
bogdanm 0:9b334a45a8ff 1516
bogdanm 0:9b334a45a8ff 1517 /* Return function status */
bogdanm 0:9b334a45a8ff 1518 return HAL_OK;
bogdanm 0:9b334a45a8ff 1519 }
bogdanm 0:9b334a45a8ff 1520
bogdanm 0:9b334a45a8ff 1521 /**
bogdanm 0:9b334a45a8ff 1522 * @}
bogdanm 0:9b334a45a8ff 1523 */
bogdanm 0:9b334a45a8ff 1524
bogdanm 0:9b334a45a8ff 1525 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
bogdanm 0:9b334a45a8ff 1526 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 1527 *
bogdanm 0:9b334a45a8ff 1528 @verbatim
bogdanm 0:9b334a45a8ff 1529 ===============================================================================
bogdanm 0:9b334a45a8ff 1530 ##### Peripheral State functions #####
bogdanm 0:9b334a45a8ff 1531 ===============================================================================
bogdanm 0:9b334a45a8ff 1532 [..]
bogdanm 0:9b334a45a8ff 1533 This subsection permits to get in run-time the status of the peripheral
bogdanm 0:9b334a45a8ff 1534 and the data flow.
bogdanm 0:9b334a45a8ff 1535 (+) Get the ETH handle state:
bogdanm 0:9b334a45a8ff 1536 HAL_ETH_GetState();
bogdanm 0:9b334a45a8ff 1537
bogdanm 0:9b334a45a8ff 1538
bogdanm 0:9b334a45a8ff 1539 @endverbatim
bogdanm 0:9b334a45a8ff 1540 * @{
bogdanm 0:9b334a45a8ff 1541 */
bogdanm 0:9b334a45a8ff 1542
bogdanm 0:9b334a45a8ff 1543 /**
bogdanm 0:9b334a45a8ff 1544 * @brief Return the ETH HAL state
bogdanm 0:9b334a45a8ff 1545 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1546 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1547 * @retval HAL state
bogdanm 0:9b334a45a8ff 1548 */
bogdanm 0:9b334a45a8ff 1549 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1550 {
bogdanm 0:9b334a45a8ff 1551 /* Return ETH state */
bogdanm 0:9b334a45a8ff 1552 return heth->State;
bogdanm 0:9b334a45a8ff 1553 }
bogdanm 0:9b334a45a8ff 1554
bogdanm 0:9b334a45a8ff 1555 /**
bogdanm 0:9b334a45a8ff 1556 * @}
bogdanm 0:9b334a45a8ff 1557 */
bogdanm 0:9b334a45a8ff 1558
bogdanm 0:9b334a45a8ff 1559 /**
bogdanm 0:9b334a45a8ff 1560 * @}
bogdanm 0:9b334a45a8ff 1561 */
bogdanm 0:9b334a45a8ff 1562
bogdanm 0:9b334a45a8ff 1563 /** @addtogroup ETH_Private_Functions
bogdanm 0:9b334a45a8ff 1564 * @{
bogdanm 0:9b334a45a8ff 1565 */
bogdanm 0:9b334a45a8ff 1566
bogdanm 0:9b334a45a8ff 1567 /**
bogdanm 0:9b334a45a8ff 1568 * @brief Configures Ethernet MAC and DMA with default parameters.
bogdanm 0:9b334a45a8ff 1569 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1570 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1571 * @param err: Ethernet Init error
bogdanm 0:9b334a45a8ff 1572 * @retval HAL status
bogdanm 0:9b334a45a8ff 1573 */
bogdanm 0:9b334a45a8ff 1574 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
bogdanm 0:9b334a45a8ff 1575 {
bogdanm 0:9b334a45a8ff 1576 ETH_MACInitTypeDef macinit;
bogdanm 0:9b334a45a8ff 1577 ETH_DMAInitTypeDef dmainit;
bogdanm 0:9b334a45a8ff 1578 uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1579
bogdanm 0:9b334a45a8ff 1580 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
bogdanm 0:9b334a45a8ff 1581 {
bogdanm 0:9b334a45a8ff 1582 /* Set Ethernet duplex mode to Full-duplex */
bogdanm 0:9b334a45a8ff 1583 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
bogdanm 0:9b334a45a8ff 1584
bogdanm 0:9b334a45a8ff 1585 /* Set Ethernet speed to 100M */
bogdanm 0:9b334a45a8ff 1586 (heth->Init).Speed = ETH_SPEED_100M;
bogdanm 0:9b334a45a8ff 1587 }
bogdanm 0:9b334a45a8ff 1588
bogdanm 0:9b334a45a8ff 1589 /* Ethernet MAC default initialization **************************************/
bogdanm 0:9b334a45a8ff 1590 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
bogdanm 0:9b334a45a8ff 1591 macinit.Jabber = ETH_JABBER_ENABLE;
bogdanm 0:9b334a45a8ff 1592 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
bogdanm 0:9b334a45a8ff 1593 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
bogdanm 0:9b334a45a8ff 1594 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
bogdanm 0:9b334a45a8ff 1595 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
bogdanm 0:9b334a45a8ff 1596 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
bogdanm 0:9b334a45a8ff 1597 {
bogdanm 0:9b334a45a8ff 1598 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
bogdanm 0:9b334a45a8ff 1599 }
bogdanm 0:9b334a45a8ff 1600 else
bogdanm 0:9b334a45a8ff 1601 {
bogdanm 0:9b334a45a8ff 1602 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
bogdanm 0:9b334a45a8ff 1603 }
bogdanm 0:9b334a45a8ff 1604 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
bogdanm 0:9b334a45a8ff 1605 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
bogdanm 0:9b334a45a8ff 1606 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
bogdanm 0:9b334a45a8ff 1607 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
bogdanm 0:9b334a45a8ff 1608 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
bogdanm 0:9b334a45a8ff 1609 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
bogdanm 0:9b334a45a8ff 1610 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
bogdanm 0:9b334a45a8ff 1611 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
bogdanm 0:9b334a45a8ff 1612 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
bogdanm 0:9b334a45a8ff 1613 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
bogdanm 0:9b334a45a8ff 1614 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
bogdanm 0:9b334a45a8ff 1615 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
bogdanm 0:9b334a45a8ff 1616 macinit.HashTableHigh = 0x0;
bogdanm 0:9b334a45a8ff 1617 macinit.HashTableLow = 0x0;
bogdanm 0:9b334a45a8ff 1618 macinit.PauseTime = 0x0;
bogdanm 0:9b334a45a8ff 1619 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
bogdanm 0:9b334a45a8ff 1620 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
bogdanm 0:9b334a45a8ff 1621 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
bogdanm 0:9b334a45a8ff 1622 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
bogdanm 0:9b334a45a8ff 1623 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
bogdanm 0:9b334a45a8ff 1624 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
bogdanm 0:9b334a45a8ff 1625 macinit.VLANTagIdentifier = 0x0;
bogdanm 0:9b334a45a8ff 1626
bogdanm 0:9b334a45a8ff 1627 /*------------------------ ETHERNET MACCR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1628 /* Get the ETHERNET MACCR value */
bogdanm 0:9b334a45a8ff 1629 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1630 /* Clear WD, PCE, PS, TE and RE bits */
bogdanm 0:9b334a45a8ff 1631 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 1632 /* Set the WD bit according to ETH Watchdog value */
bogdanm 0:9b334a45a8ff 1633 /* Set the JD: bit according to ETH Jabber value */
bogdanm 0:9b334a45a8ff 1634 /* Set the IFG bit according to ETH InterFrameGap value */
bogdanm 0:9b334a45a8ff 1635 /* Set the DCRS bit according to ETH CarrierSense value */
bogdanm 0:9b334a45a8ff 1636 /* Set the FES bit according to ETH Speed value */
bogdanm 0:9b334a45a8ff 1637 /* Set the DO bit according to ETH ReceiveOwn value */
bogdanm 0:9b334a45a8ff 1638 /* Set the LM bit according to ETH LoopbackMode value */
bogdanm 0:9b334a45a8ff 1639 /* Set the DM bit according to ETH Mode value */
bogdanm 0:9b334a45a8ff 1640 /* Set the IPCO bit according to ETH ChecksumOffload value */
bogdanm 0:9b334a45a8ff 1641 /* Set the DR bit according to ETH RetryTransmission value */
bogdanm 0:9b334a45a8ff 1642 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
bogdanm 0:9b334a45a8ff 1643 /* Set the BL bit according to ETH BackOffLimit value */
bogdanm 0:9b334a45a8ff 1644 /* Set the DC bit according to ETH DeferralCheck value */
bogdanm 0:9b334a45a8ff 1645 tmpreg1 |= (uint32_t)(macinit.Watchdog |
bogdanm 0:9b334a45a8ff 1646 macinit.Jabber |
bogdanm 0:9b334a45a8ff 1647 macinit.InterFrameGap |
bogdanm 0:9b334a45a8ff 1648 macinit.CarrierSense |
bogdanm 0:9b334a45a8ff 1649 (heth->Init).Speed |
bogdanm 0:9b334a45a8ff 1650 macinit.ReceiveOwn |
bogdanm 0:9b334a45a8ff 1651 macinit.LoopbackMode |
bogdanm 0:9b334a45a8ff 1652 (heth->Init).DuplexMode |
bogdanm 0:9b334a45a8ff 1653 macinit.ChecksumOffload |
bogdanm 0:9b334a45a8ff 1654 macinit.RetryTransmission |
bogdanm 0:9b334a45a8ff 1655 macinit.AutomaticPadCRCStrip |
bogdanm 0:9b334a45a8ff 1656 macinit.BackOffLimit |
bogdanm 0:9b334a45a8ff 1657 macinit.DeferralCheck);
bogdanm 0:9b334a45a8ff 1658
bogdanm 0:9b334a45a8ff 1659 /* Write to ETHERNET MACCR */
bogdanm 0:9b334a45a8ff 1660 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1661
bogdanm 0:9b334a45a8ff 1662 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1663 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1664 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1665 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1666 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1667
bogdanm 0:9b334a45a8ff 1668 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
bogdanm 0:9b334a45a8ff 1669 /* Set the RA bit according to ETH ReceiveAll value */
bogdanm 0:9b334a45a8ff 1670 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
bogdanm 0:9b334a45a8ff 1671 /* Set the PCF bit according to ETH PassControlFrames value */
bogdanm 0:9b334a45a8ff 1672 /* Set the DBF bit according to ETH BroadcastFramesReception value */
bogdanm 0:9b334a45a8ff 1673 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
bogdanm 0:9b334a45a8ff 1674 /* Set the PR bit according to ETH PromiscuousMode value */
bogdanm 0:9b334a45a8ff 1675 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
bogdanm 0:9b334a45a8ff 1676 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
bogdanm 0:9b334a45a8ff 1677 /* Write to ETHERNET MACFFR */
bogdanm 0:9b334a45a8ff 1678 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
bogdanm 0:9b334a45a8ff 1679 macinit.SourceAddrFilter |
bogdanm 0:9b334a45a8ff 1680 macinit.PassControlFrames |
bogdanm 0:9b334a45a8ff 1681 macinit.BroadcastFramesReception |
bogdanm 0:9b334a45a8ff 1682 macinit.DestinationAddrFilter |
bogdanm 0:9b334a45a8ff 1683 macinit.PromiscuousMode |
bogdanm 0:9b334a45a8ff 1684 macinit.MulticastFramesFilter |
bogdanm 0:9b334a45a8ff 1685 macinit.UnicastFramesFilter);
bogdanm 0:9b334a45a8ff 1686
bogdanm 0:9b334a45a8ff 1687 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1688 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1689 tmpreg1 = (heth->Instance)->MACFFR;
bogdanm 0:9b334a45a8ff 1690 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1691 (heth->Instance)->MACFFR = tmpreg1;
bogdanm 0:9b334a45a8ff 1692
bogdanm 0:9b334a45a8ff 1693 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
bogdanm 0:9b334a45a8ff 1694 /* Write to ETHERNET MACHTHR */
bogdanm 0:9b334a45a8ff 1695 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
bogdanm 0:9b334a45a8ff 1696
bogdanm 0:9b334a45a8ff 1697 /* Write to ETHERNET MACHTLR */
bogdanm 0:9b334a45a8ff 1698 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
bogdanm 0:9b334a45a8ff 1699 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
bogdanm 0:9b334a45a8ff 1700
bogdanm 0:9b334a45a8ff 1701 /* Get the ETHERNET MACFCR value */
bogdanm 0:9b334a45a8ff 1702 tmpreg1 = (heth->Instance)->MACFCR;
bogdanm 0:9b334a45a8ff 1703 /* Clear xx bits */
bogdanm 0:9b334a45a8ff 1704 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 1705
bogdanm 0:9b334a45a8ff 1706 /* Set the PT bit according to ETH PauseTime value */
bogdanm 0:9b334a45a8ff 1707 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
bogdanm 0:9b334a45a8ff 1708 /* Set the PLT bit according to ETH PauseLowThreshold value */
bogdanm 0:9b334a45a8ff 1709 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
bogdanm 0:9b334a45a8ff 1710 /* Set the RFE bit according to ETH ReceiveFlowControl value */
bogdanm 0:9b334a45a8ff 1711 /* Set the TFE bit according to ETH TransmitFlowControl value */
bogdanm 0:9b334a45a8ff 1712 tmpreg1 |= (uint32_t)((macinit.PauseTime << 16) |
bogdanm 0:9b334a45a8ff 1713 macinit.ZeroQuantaPause |
bogdanm 0:9b334a45a8ff 1714 macinit.PauseLowThreshold |
bogdanm 0:9b334a45a8ff 1715 macinit.UnicastPauseFrameDetect |
bogdanm 0:9b334a45a8ff 1716 macinit.ReceiveFlowControl |
bogdanm 0:9b334a45a8ff 1717 macinit.TransmitFlowControl);
bogdanm 0:9b334a45a8ff 1718
bogdanm 0:9b334a45a8ff 1719 /* Write to ETHERNET MACFCR */
bogdanm 0:9b334a45a8ff 1720 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1721
bogdanm 0:9b334a45a8ff 1722 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1723 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1724 tmpreg1 = (heth->Instance)->MACFCR;
bogdanm 0:9b334a45a8ff 1725 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1726 (heth->Instance)->MACFCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1727
bogdanm 0:9b334a45a8ff 1728 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
bogdanm 0:9b334a45a8ff 1729 /* Set the ETV bit according to ETH VLANTagComparison value */
bogdanm 0:9b334a45a8ff 1730 /* Set the VL bit according to ETH VLANTagIdentifier value */
bogdanm 0:9b334a45a8ff 1731 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
bogdanm 0:9b334a45a8ff 1732 macinit.VLANTagIdentifier);
bogdanm 0:9b334a45a8ff 1733
bogdanm 0:9b334a45a8ff 1734 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1735 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1736 tmpreg1 = (heth->Instance)->MACVLANTR;
bogdanm 0:9b334a45a8ff 1737 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1738 (heth->Instance)->MACVLANTR = tmpreg1;
bogdanm 0:9b334a45a8ff 1739
bogdanm 0:9b334a45a8ff 1740 /* Ethernet DMA default initialization ************************************/
bogdanm 0:9b334a45a8ff 1741 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
bogdanm 0:9b334a45a8ff 1742 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
bogdanm 0:9b334a45a8ff 1743 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
bogdanm 0:9b334a45a8ff 1744 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
bogdanm 0:9b334a45a8ff 1745 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
bogdanm 0:9b334a45a8ff 1746 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
bogdanm 0:9b334a45a8ff 1747 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
bogdanm 0:9b334a45a8ff 1748 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
bogdanm 0:9b334a45a8ff 1749 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
bogdanm 0:9b334a45a8ff 1750 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
bogdanm 0:9b334a45a8ff 1751 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
bogdanm 0:9b334a45a8ff 1752 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
bogdanm 0:9b334a45a8ff 1753 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
bogdanm 0:9b334a45a8ff 1754 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
bogdanm 0:9b334a45a8ff 1755 dmainit.DescriptorSkipLength = 0x0;
bogdanm 0:9b334a45a8ff 1756 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
bogdanm 0:9b334a45a8ff 1757
bogdanm 0:9b334a45a8ff 1758 /* Get the ETHERNET DMAOMR value */
bogdanm 0:9b334a45a8ff 1759 tmpreg1 = (heth->Instance)->DMAOMR;
bogdanm 0:9b334a45a8ff 1760 /* Clear xx bits */
bogdanm 0:9b334a45a8ff 1761 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
bogdanm 0:9b334a45a8ff 1762
bogdanm 0:9b334a45a8ff 1763 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
bogdanm 0:9b334a45a8ff 1764 /* Set the RSF bit according to ETH ReceiveStoreForward value */
bogdanm 0:9b334a45a8ff 1765 /* Set the DFF bit according to ETH FlushReceivedFrame value */
bogdanm 0:9b334a45a8ff 1766 /* Set the TSF bit according to ETH TransmitStoreForward value */
bogdanm 0:9b334a45a8ff 1767 /* Set the TTC bit according to ETH TransmitThresholdControl value */
bogdanm 0:9b334a45a8ff 1768 /* Set the FEF bit according to ETH ForwardErrorFrames value */
bogdanm 0:9b334a45a8ff 1769 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
bogdanm 0:9b334a45a8ff 1770 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
bogdanm 0:9b334a45a8ff 1771 /* Set the OSF bit according to ETH SecondFrameOperate value */
bogdanm 0:9b334a45a8ff 1772 tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
bogdanm 0:9b334a45a8ff 1773 dmainit.ReceiveStoreForward |
bogdanm 0:9b334a45a8ff 1774 dmainit.FlushReceivedFrame |
bogdanm 0:9b334a45a8ff 1775 dmainit.TransmitStoreForward |
bogdanm 0:9b334a45a8ff 1776 dmainit.TransmitThresholdControl |
bogdanm 0:9b334a45a8ff 1777 dmainit.ForwardErrorFrames |
bogdanm 0:9b334a45a8ff 1778 dmainit.ForwardUndersizedGoodFrames |
bogdanm 0:9b334a45a8ff 1779 dmainit.ReceiveThresholdControl |
bogdanm 0:9b334a45a8ff 1780 dmainit.SecondFrameOperate);
bogdanm 0:9b334a45a8ff 1781
bogdanm 0:9b334a45a8ff 1782 /* Write to ETHERNET DMAOMR */
bogdanm 0:9b334a45a8ff 1783 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
bogdanm 0:9b334a45a8ff 1784
bogdanm 0:9b334a45a8ff 1785 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1786 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1787 tmpreg1 = (heth->Instance)->DMAOMR;
bogdanm 0:9b334a45a8ff 1788 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1789 (heth->Instance)->DMAOMR = tmpreg1;
bogdanm 0:9b334a45a8ff 1790
bogdanm 0:9b334a45a8ff 1791 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
bogdanm 0:9b334a45a8ff 1792 /* Set the AAL bit according to ETH AddressAlignedBeats value */
bogdanm 0:9b334a45a8ff 1793 /* Set the FB bit according to ETH FixedBurst value */
bogdanm 0:9b334a45a8ff 1794 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
bogdanm 0:9b334a45a8ff 1795 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
bogdanm 0:9b334a45a8ff 1796 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
bogdanm 0:9b334a45a8ff 1797 /* Set the DSL bit according to ETH DesciptorSkipLength value */
bogdanm 0:9b334a45a8ff 1798 /* Set the PR and DA bits according to ETH DMAArbitration value */
bogdanm 0:9b334a45a8ff 1799 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
bogdanm 0:9b334a45a8ff 1800 dmainit.FixedBurst |
bogdanm 0:9b334a45a8ff 1801 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
bogdanm 0:9b334a45a8ff 1802 dmainit.TxDMABurstLength |
bogdanm 0:9b334a45a8ff 1803 dmainit.EnhancedDescriptorFormat |
bogdanm 0:9b334a45a8ff 1804 (dmainit.DescriptorSkipLength << 2) |
bogdanm 0:9b334a45a8ff 1805 dmainit.DMAArbitration |
bogdanm 0:9b334a45a8ff 1806 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
bogdanm 0:9b334a45a8ff 1807
bogdanm 0:9b334a45a8ff 1808 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1809 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1810 tmpreg1 = (heth->Instance)->DMABMR;
bogdanm 0:9b334a45a8ff 1811 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1812 (heth->Instance)->DMABMR = tmpreg1;
bogdanm 0:9b334a45a8ff 1813
bogdanm 0:9b334a45a8ff 1814 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
bogdanm 0:9b334a45a8ff 1815 {
bogdanm 0:9b334a45a8ff 1816 /* Enable the Ethernet Rx Interrupt */
bogdanm 0:9b334a45a8ff 1817 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
bogdanm 0:9b334a45a8ff 1818 }
bogdanm 0:9b334a45a8ff 1819
bogdanm 0:9b334a45a8ff 1820 /* Initialize MAC address in ethernet MAC */
bogdanm 0:9b334a45a8ff 1821 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
bogdanm 0:9b334a45a8ff 1822 }
bogdanm 0:9b334a45a8ff 1823
bogdanm 0:9b334a45a8ff 1824 /**
bogdanm 0:9b334a45a8ff 1825 * @brief Configures the selected MAC address.
bogdanm 0:9b334a45a8ff 1826 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1827 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1828 * @param MacAddr: The MAC address to configure
bogdanm 0:9b334a45a8ff 1829 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1830 * @arg ETH_MAC_Address0: MAC Address0
bogdanm 0:9b334a45a8ff 1831 * @arg ETH_MAC_Address1: MAC Address1
bogdanm 0:9b334a45a8ff 1832 * @arg ETH_MAC_Address2: MAC Address2
bogdanm 0:9b334a45a8ff 1833 * @arg ETH_MAC_Address3: MAC Address3
bogdanm 0:9b334a45a8ff 1834 * @param Addr: Pointer to MAC address buffer data (6 bytes)
bogdanm 0:9b334a45a8ff 1835 * @retval HAL status
bogdanm 0:9b334a45a8ff 1836 */
bogdanm 0:9b334a45a8ff 1837 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
bogdanm 0:9b334a45a8ff 1838 {
bogdanm 0:9b334a45a8ff 1839 uint32_t tmpreg1;
bogdanm 0:9b334a45a8ff 1840
bogdanm 0:9b334a45a8ff 1841 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1842 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
bogdanm 0:9b334a45a8ff 1843
bogdanm 0:9b334a45a8ff 1844 /* Calculate the selected MAC address high register */
bogdanm 0:9b334a45a8ff 1845 tmpreg1 = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
bogdanm 0:9b334a45a8ff 1846 /* Load the selected MAC address high register */
bogdanm 0:9b334a45a8ff 1847 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
bogdanm 0:9b334a45a8ff 1848 /* Calculate the selected MAC address low register */
bogdanm 0:9b334a45a8ff 1849 tmpreg1 = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
bogdanm 0:9b334a45a8ff 1850
bogdanm 0:9b334a45a8ff 1851 /* Load the selected MAC address low register */
bogdanm 0:9b334a45a8ff 1852 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
bogdanm 0:9b334a45a8ff 1853 }
bogdanm 0:9b334a45a8ff 1854
bogdanm 0:9b334a45a8ff 1855 /**
bogdanm 0:9b334a45a8ff 1856 * @brief Enables the MAC transmission.
bogdanm 0:9b334a45a8ff 1857 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1858 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1859 * @retval None
bogdanm 0:9b334a45a8ff 1860 */
bogdanm 0:9b334a45a8ff 1861 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1862 {
bogdanm 0:9b334a45a8ff 1863 __IO uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1864
bogdanm 0:9b334a45a8ff 1865 /* Enable the MAC transmission */
bogdanm 0:9b334a45a8ff 1866 (heth->Instance)->MACCR |= ETH_MACCR_TE;
bogdanm 0:9b334a45a8ff 1867
bogdanm 0:9b334a45a8ff 1868 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1869 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1870 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1871 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1872 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1873 }
bogdanm 0:9b334a45a8ff 1874
bogdanm 0:9b334a45a8ff 1875 /**
bogdanm 0:9b334a45a8ff 1876 * @brief Disables the MAC transmission.
bogdanm 0:9b334a45a8ff 1877 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1878 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1879 * @retval None
bogdanm 0:9b334a45a8ff 1880 */
bogdanm 0:9b334a45a8ff 1881 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1882 {
bogdanm 0:9b334a45a8ff 1883 __IO uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1884
bogdanm 0:9b334a45a8ff 1885 /* Disable the MAC transmission */
bogdanm 0:9b334a45a8ff 1886 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
bogdanm 0:9b334a45a8ff 1887
bogdanm 0:9b334a45a8ff 1888 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1889 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1890 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1891 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1892 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1893 }
bogdanm 0:9b334a45a8ff 1894
bogdanm 0:9b334a45a8ff 1895 /**
bogdanm 0:9b334a45a8ff 1896 * @brief Enables the MAC reception.
bogdanm 0:9b334a45a8ff 1897 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1898 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1899 * @retval None
bogdanm 0:9b334a45a8ff 1900 */
bogdanm 0:9b334a45a8ff 1901 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1902 {
bogdanm 0:9b334a45a8ff 1903 __IO uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1904
bogdanm 0:9b334a45a8ff 1905 /* Enable the MAC reception */
bogdanm 0:9b334a45a8ff 1906 (heth->Instance)->MACCR |= ETH_MACCR_RE;
bogdanm 0:9b334a45a8ff 1907
bogdanm 0:9b334a45a8ff 1908 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1909 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1910 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1911 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1912 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1913 }
bogdanm 0:9b334a45a8ff 1914
bogdanm 0:9b334a45a8ff 1915 /**
bogdanm 0:9b334a45a8ff 1916 * @brief Disables the MAC reception.
bogdanm 0:9b334a45a8ff 1917 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1918 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1919 * @retval None
bogdanm 0:9b334a45a8ff 1920 */
bogdanm 0:9b334a45a8ff 1921 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1922 {
bogdanm 0:9b334a45a8ff 1923 __IO uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1924
bogdanm 0:9b334a45a8ff 1925 /* Disable the MAC reception */
bogdanm 0:9b334a45a8ff 1926 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
bogdanm 0:9b334a45a8ff 1927
bogdanm 0:9b334a45a8ff 1928 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1929 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1930 tmpreg1 = (heth->Instance)->MACCR;
bogdanm 0:9b334a45a8ff 1931 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 1932 (heth->Instance)->MACCR = tmpreg1;
bogdanm 0:9b334a45a8ff 1933 }
bogdanm 0:9b334a45a8ff 1934
bogdanm 0:9b334a45a8ff 1935 /**
bogdanm 0:9b334a45a8ff 1936 * @brief Enables the DMA transmission.
bogdanm 0:9b334a45a8ff 1937 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1938 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1939 * @retval None
bogdanm 0:9b334a45a8ff 1940 */
bogdanm 0:9b334a45a8ff 1941 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1942 {
bogdanm 0:9b334a45a8ff 1943 /* Enable the DMA transmission */
bogdanm 0:9b334a45a8ff 1944 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
bogdanm 0:9b334a45a8ff 1945 }
bogdanm 0:9b334a45a8ff 1946
bogdanm 0:9b334a45a8ff 1947 /**
bogdanm 0:9b334a45a8ff 1948 * @brief Disables the DMA transmission.
bogdanm 0:9b334a45a8ff 1949 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1950 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1951 * @retval None
bogdanm 0:9b334a45a8ff 1952 */
bogdanm 0:9b334a45a8ff 1953 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1954 {
bogdanm 0:9b334a45a8ff 1955 /* Disable the DMA transmission */
bogdanm 0:9b334a45a8ff 1956 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
bogdanm 0:9b334a45a8ff 1957 }
bogdanm 0:9b334a45a8ff 1958
bogdanm 0:9b334a45a8ff 1959 /**
bogdanm 0:9b334a45a8ff 1960 * @brief Enables the DMA reception.
bogdanm 0:9b334a45a8ff 1961 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1962 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1963 * @retval None
bogdanm 0:9b334a45a8ff 1964 */
bogdanm 0:9b334a45a8ff 1965 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1966 {
bogdanm 0:9b334a45a8ff 1967 /* Enable the DMA reception */
bogdanm 0:9b334a45a8ff 1968 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
bogdanm 0:9b334a45a8ff 1969 }
bogdanm 0:9b334a45a8ff 1970
bogdanm 0:9b334a45a8ff 1971 /**
bogdanm 0:9b334a45a8ff 1972 * @brief Disables the DMA reception.
bogdanm 0:9b334a45a8ff 1973 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1974 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1975 * @retval None
bogdanm 0:9b334a45a8ff 1976 */
bogdanm 0:9b334a45a8ff 1977 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1978 {
bogdanm 0:9b334a45a8ff 1979 /* Disable the DMA reception */
bogdanm 0:9b334a45a8ff 1980 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
bogdanm 0:9b334a45a8ff 1981 }
bogdanm 0:9b334a45a8ff 1982
bogdanm 0:9b334a45a8ff 1983 /**
bogdanm 0:9b334a45a8ff 1984 * @brief Clears the ETHERNET transmit FIFO.
bogdanm 0:9b334a45a8ff 1985 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1986 * the configuration information for ETHERNET module
bogdanm 0:9b334a45a8ff 1987 * @retval None
bogdanm 0:9b334a45a8ff 1988 */
bogdanm 0:9b334a45a8ff 1989 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
bogdanm 0:9b334a45a8ff 1990 {
bogdanm 0:9b334a45a8ff 1991 __IO uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 1992
bogdanm 0:9b334a45a8ff 1993 /* Set the Flush Transmit FIFO bit */
bogdanm 0:9b334a45a8ff 1994 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
bogdanm 0:9b334a45a8ff 1995
bogdanm 0:9b334a45a8ff 1996 /* Wait until the write operation will be taken into account:
bogdanm 0:9b334a45a8ff 1997 at least four TX_CLK/RX_CLK clock cycles */
bogdanm 0:9b334a45a8ff 1998 tmpreg1 = (heth->Instance)->DMAOMR;
bogdanm 0:9b334a45a8ff 1999 HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm 0:9b334a45a8ff 2000 (heth->Instance)->DMAOMR = tmpreg1;
bogdanm 0:9b334a45a8ff 2001 }
bogdanm 0:9b334a45a8ff 2002
bogdanm 0:9b334a45a8ff 2003 /**
bogdanm 0:9b334a45a8ff 2004 * @}
bogdanm 0:9b334a45a8ff 2005 */
bogdanm 0:9b334a45a8ff 2006
bogdanm 0:9b334a45a8ff 2007 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 2008 #endif /* HAL_ETH_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 2009 /**
bogdanm 0:9b334a45a8ff 2010 * @}
bogdanm 0:9b334a45a8ff 2011 */
bogdanm 0:9b334a45a8ff 2012
bogdanm 0:9b334a45a8ff 2013 /**
bogdanm 0:9b334a45a8ff 2014 * @}
bogdanm 0:9b334a45a8ff 2015 */
bogdanm 0:9b334a45a8ff 2016
bogdanm 0:9b334a45a8ff 2017 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/