mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f3xx_hal_tim_ex.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.1.0
bogdanm	0:9b334a45a8ff	6	* @date 12-Sept-2014
bogdanm	0:9b334a45a8ff	7	* @brief Header file of TIM HAL Extended module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F3xx_HAL_TIM_EX_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F3xx_HAL_TIM_EX_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32f3xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32F3xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup TIMEx
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62	/**
bogdanm	0:9b334a45a8ff	63	* @brief TIM Hall sensor Configuration Structure definition
bogdanm	0:9b334a45a8ff	64	*/
bogdanm	0:9b334a45a8ff	65
bogdanm	0:9b334a45a8ff	66	typedef struct
bogdanm	0:9b334a45a8ff	67	{
bogdanm	0:9b334a45a8ff	68
bogdanm	0:9b334a45a8ff	69	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	70	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	73	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	74
bogdanm	0:9b334a45a8ff	75	uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	76	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	77	uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	78	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	79	} TIM_HallSensor_InitTypeDef;
bogdanm	0:9b334a45a8ff	80
bogdanm	0:9b334a45a8ff	81	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	0:9b334a45a8ff	82	/**
bogdanm	0:9b334a45a8ff	83	* @brief TIM Master configuration Structure definition
bogdanm	0:9b334a45a8ff	84	* @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO
bogdanm	0:9b334a45a8ff	85	* output
bogdanm	0:9b334a45a8ff	86	*/
bogdanm	0:9b334a45a8ff	87	typedef struct {
bogdanm	0:9b334a45a8ff	88	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
bogdanm	0:9b334a45a8ff	89	This parameter can be a value of @ref TIM_Master_Mode_Selection */
bogdanm	0:9b334a45a8ff	90	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
bogdanm	0:9b334a45a8ff	91	This parameter can be a value of @ref TIM_Master_Slave_Mode */
bogdanm	0:9b334a45a8ff	92	}TIM_MasterConfigTypeDef;
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	/**
bogdanm	0:9b334a45a8ff	95	* @brief TIM Break and Dead time configuration Structure definition
bogdanm	0:9b334a45a8ff	96	* @note STM32F373xC and STM32F378xx: single break input with configurable polarity.
bogdanm	0:9b334a45a8ff	97	*/
bogdanm	0:9b334a45a8ff	98	typedef struct
bogdanm	0:9b334a45a8ff	99	{
bogdanm	0:9b334a45a8ff	100	uint32_t OffStateRunMode; /*!< TIM off state in run mode
bogdanm	0:9b334a45a8ff	101	This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
bogdanm	0:9b334a45a8ff	102	uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
bogdanm	0:9b334a45a8ff	103	This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
bogdanm	0:9b334a45a8ff	104	uint32_t LockLevel; /*!< TIM Lock level
bogdanm	0:9b334a45a8ff	105	This parameter can be a value of @ref TIM_Lock_level */
bogdanm	0:9b334a45a8ff	106	uint32_t DeadTime; /*!< TIM dead Time
bogdanm	0:9b334a45a8ff	107	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
bogdanm	0:9b334a45a8ff	108	uint32_t BreakState; /*!< TIM Break State
bogdanm	0:9b334a45a8ff	109	This parameter can be a value of @ref TIM_Break_Input_enable_disable */
bogdanm	0:9b334a45a8ff	110	uint32_t BreakPolarity; /*!< TIM Break input polarity
bogdanm	0:9b334a45a8ff	111	This parameter can be a value of @ref TIM_Break_Polarity */
bogdanm	0:9b334a45a8ff	112	uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
bogdanm	0:9b334a45a8ff	113	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
bogdanm	0:9b334a45a8ff	114	} TIM_BreakDeadTimeConfigTypeDef;
bogdanm	0:9b334a45a8ff	115
bogdanm	0:9b334a45a8ff	116	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	0:9b334a45a8ff	117
bogdanm	0:9b334a45a8ff	118	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	119	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	0:9b334a45a8ff	120	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	121	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	122	/**
bogdanm	0:9b334a45a8ff	123	* @brief TIM Break input(s) and Dead time configuration Structure definition
bogdanm	0:9b334a45a8ff	124	* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
bogdanm	0:9b334a45a8ff	125	* filter and polarity.
bogdanm	0:9b334a45a8ff	126	*/
bogdanm	0:9b334a45a8ff	127	typedef struct
bogdanm	0:9b334a45a8ff	128	{
bogdanm	0:9b334a45a8ff	129	uint32_t OffStateRunMode; /*!< TIM off state in run mode
bogdanm	0:9b334a45a8ff	130	This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
bogdanm	0:9b334a45a8ff	131	uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
bogdanm	0:9b334a45a8ff	132	This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
bogdanm	0:9b334a45a8ff	133	uint32_t LockLevel; /*!< TIM Lock level
bogdanm	0:9b334a45a8ff	134	This parameter can be a value of @ref TIM_Lock_level */
bogdanm	0:9b334a45a8ff	135	uint32_t DeadTime; /*!< TIM dead Time
bogdanm	0:9b334a45a8ff	136	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
bogdanm	0:9b334a45a8ff	137	uint32_t BreakState; /*!< TIM Break State
bogdanm	0:9b334a45a8ff	138	This parameter can be a value of @ref TIM_Break_Input_enable_disable */
bogdanm	0:9b334a45a8ff	139	uint32_t BreakPolarity; /*!< TIM Break input polarity
bogdanm	0:9b334a45a8ff	140	This parameter can be a value of @ref TIM_Break_Polarity */
bogdanm	0:9b334a45a8ff	141	uint32_t BreakFilter; /*!< Specifies the brek input filter.
bogdanm	0:9b334a45a8ff	142	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	143	uint32_t Break2State; /*!< TIM Break2 State
bogdanm	0:9b334a45a8ff	144	This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
bogdanm	0:9b334a45a8ff	145	uint32_t Break2Polarity; /*!< TIM Break2 input polarity
bogdanm	0:9b334a45a8ff	146	This parameter can be a value of @ref TIMEx_Break2_Polarity */
bogdanm	0:9b334a45a8ff	147	uint32_t Break2Filter; /*!< TIM break2 input filter.
bogdanm	0:9b334a45a8ff	148	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	149	uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
bogdanm	0:9b334a45a8ff	150	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
bogdanm	0:9b334a45a8ff	151	} TIM_BreakDeadTimeConfigTypeDef;
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	/**
bogdanm	0:9b334a45a8ff	154	* @brief TIM Master configuration Structure definition
bogdanm	0:9b334a45a8ff	155	* @note Advanced timers provide TRGO2 internal line which is redirected
bogdanm	0:9b334a45a8ff	156	* to the ADC
bogdanm	0:9b334a45a8ff	157	*/
bogdanm	0:9b334a45a8ff	158	typedef struct {
bogdanm	0:9b334a45a8ff	159	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
bogdanm	0:9b334a45a8ff	160	This parameter can be a value of @ref TIM_Master_Mode_Selection */
bogdanm	0:9b334a45a8ff	161	uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
bogdanm	0:9b334a45a8ff	162	This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
bogdanm	0:9b334a45a8ff	163	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
bogdanm	0:9b334a45a8ff	164	This parameter can be a value of @ref TIM_Master_Slave_Mode */
bogdanm	0:9b334a45a8ff	165	}TIM_MasterConfigTypeDef;
bogdanm	0:9b334a45a8ff	166	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	167	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	168	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	169	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	0:9b334a45a8ff	170	/**
bogdanm	0:9b334a45a8ff	171	* @}
bogdanm	0:9b334a45a8ff	172	*/
bogdanm	0:9b334a45a8ff	173
bogdanm	0:9b334a45a8ff	174	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	175	/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
bogdanm	0:9b334a45a8ff	176	* @{
bogdanm	0:9b334a45a8ff	177	*/
bogdanm	0:9b334a45a8ff	178
bogdanm	0:9b334a45a8ff	179	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	0:9b334a45a8ff	180	/** @defgroup TIMEx_Channel TIM Extended Channel
bogdanm	0:9b334a45a8ff	181	* @{
bogdanm	0:9b334a45a8ff	182	*/
bogdanm	0:9b334a45a8ff	183	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	184	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	185	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm	0:9b334a45a8ff	186	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm	0:9b334a45a8ff	187	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm	0:9b334a45a8ff	188
bogdanm	0:9b334a45a8ff	189	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	190	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	191	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	192	((CHANNEL) == TIM_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	193	((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm	0:9b334a45a8ff	194
bogdanm	0:9b334a45a8ff	195	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	196	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	197
bogdanm	0:9b334a45a8ff	198	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	199	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	202	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	203	((CHANNEL) == TIM_CHANNEL_3))
bogdanm	0:9b334a45a8ff	204	/**
bogdanm	0:9b334a45a8ff	205	* @}
bogdanm	0:9b334a45a8ff	206	*/
bogdanm	0:9b334a45a8ff	207
bogdanm	0:9b334a45a8ff	208	/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Extended Output Compare and PWM Modes
bogdanm	0:9b334a45a8ff	209	* @{
bogdanm	0:9b334a45a8ff	210	*/
bogdanm	0:9b334a45a8ff	211
bogdanm	0:9b334a45a8ff	212	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	213	#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	214	#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	215	#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	216	#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	217	#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
bogdanm	0:9b334a45a8ff	218	#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	219	#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	220
bogdanm	0:9b334a45a8ff	221	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
bogdanm	0:9b334a45a8ff	222	((MODE) == TIM_OCMODE_PWM2))
bogdanm	0:9b334a45a8ff	223
bogdanm	0:9b334a45a8ff	224	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
bogdanm	0:9b334a45a8ff	225	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	226	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	227	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
bogdanm	0:9b334a45a8ff	228	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	229	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
bogdanm	0:9b334a45a8ff	230	/**
bogdanm	0:9b334a45a8ff	231	* @}
bogdanm	0:9b334a45a8ff	232	*/
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	/** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source
bogdanm	0:9b334a45a8ff	235	* @{
bogdanm	0:9b334a45a8ff	236	*/
bogdanm	0:9b334a45a8ff	237	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	238	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	239
bogdanm	0:9b334a45a8ff	240	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	241	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
bogdanm	0:9b334a45a8ff	242	/**
bogdanm	0:9b334a45a8ff	243	* @}
bogdanm	0:9b334a45a8ff	244	*/
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	/** @defgroup TIMEx_Slave_Mode TIM Extended Slave Mode
bogdanm	0:9b334a45a8ff	247	* @{
bogdanm	0:9b334a45a8ff	248	*/
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	251	#define TIM_SLAVEMODE_RESET ((uint16_t)0x0004)
bogdanm	0:9b334a45a8ff	252	#define TIM_SLAVEMODE_GATED ((uint16_t)0x0005)
bogdanm	0:9b334a45a8ff	253	#define TIM_SLAVEMODE_TRIGGER ((uint16_t)0x0006)
bogdanm	0:9b334a45a8ff	254	#define TIM_SLAVEMODE_EXTERNAL1 ((uint16_t)0x0007)
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	257	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
bogdanm	0:9b334a45a8ff	258	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
bogdanm	0:9b334a45a8ff	259	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
bogdanm	0:9b334a45a8ff	260	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm	0:9b334a45a8ff	261	/**
bogdanm	0:9b334a45a8ff	262	* @}
bogdanm	0:9b334a45a8ff	263	*/
bogdanm	0:9b334a45a8ff	264
bogdanm	0:9b334a45a8ff	265	/** @defgroup TIMEx_Event_Source TIM Extended Event Source
bogdanm	0:9b334a45a8ff	266	* @{
bogdanm	0:9b334a45a8ff	267	*/
bogdanm	0:9b334a45a8ff	268
bogdanm	0:9b334a45a8ff	269	#define TIM_EventSource_Update TIM_EGR_UG /!< Reinitialize the counter and generates an update of the registers /
bogdanm	0:9b334a45a8ff	270	#define TIM_EventSource_CC1 TIM_EGR_CC1G /!< A capture/compare event is generated on channel 1 /
bogdanm	0:9b334a45a8ff	271	#define TIM_EventSource_CC2 TIM_EGR_CC2G /!< A capture/compare event is generated on channel 2 /
bogdanm	0:9b334a45a8ff	272	#define TIM_EventSource_CC3 TIM_EGR_CC3G /!< A capture/compare event is generated on channel 3 /
bogdanm	0:9b334a45a8ff	273	#define TIM_EventSource_CC4 TIM_EGR_CC4G /!< A capture/compare event is generated on channel 4 /
bogdanm	0:9b334a45a8ff	274	#define TIM_EventSource_COM TIM_EGR_COMG /!< A commutation event is generated /
bogdanm	0:9b334a45a8ff	275	#define TIM_EventSource_Trigger TIM_EGR_TG /!< A trigger event is generated /
bogdanm	0:9b334a45a8ff	276	#define TIM_EventSource_Break TIM_EGR_BG /!< A break event is generated /
bogdanm	0:9b334a45a8ff	277	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	0:9b334a45a8ff	278
bogdanm	0:9b334a45a8ff	279	/**
bogdanm	0:9b334a45a8ff	280	* @}
bogdanm	0:9b334a45a8ff	281	*/
bogdanm	0:9b334a45a8ff	282
bogdanm	0:9b334a45a8ff	283	/** @defgroup TIMEx_DMA_Base_address TIM Extended DMA BAse Address
bogdanm	0:9b334a45a8ff	284	* @{
bogdanm	0:9b334a45a8ff	285	*/
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287	#define TIM_DMABase_CR1 (0x00000000)
bogdanm	0:9b334a45a8ff	288	#define TIM_DMABase_CR2 (0x00000001)
bogdanm	0:9b334a45a8ff	289	#define TIM_DMABase_SMCR (0x00000002)
bogdanm	0:9b334a45a8ff	290	#define TIM_DMABase_DIER (0x00000003)
bogdanm	0:9b334a45a8ff	291	#define TIM_DMABase_SR (0x00000004)
bogdanm	0:9b334a45a8ff	292	#define TIM_DMABase_EGR (0x00000005)
bogdanm	0:9b334a45a8ff	293	#define TIM_DMABase_CCMR1 (0x00000006)
bogdanm	0:9b334a45a8ff	294	#define TIM_DMABase_CCMR2 (0x00000007)
bogdanm	0:9b334a45a8ff	295	#define TIM_DMABase_CCER (0x00000008)
bogdanm	0:9b334a45a8ff	296	#define TIM_DMABase_CNT (0x00000009)
bogdanm	0:9b334a45a8ff	297	#define TIM_DMABase_PSC (0x0000000A)
bogdanm	0:9b334a45a8ff	298	#define TIM_DMABase_ARR (0x0000000B)
bogdanm	0:9b334a45a8ff	299	#define TIM_DMABase_RCR (0x0000000C)
bogdanm	0:9b334a45a8ff	300	#define TIM_DMABase_CCR1 (0x0000000D)
bogdanm	0:9b334a45a8ff	301	#define TIM_DMABase_CCR2 (0x0000000E)
bogdanm	0:9b334a45a8ff	302	#define TIM_DMABase_CCR3 (0x0000000F)
bogdanm	0:9b334a45a8ff	303	#define TIM_DMABase_CCR4 (0x00000010)
bogdanm	0:9b334a45a8ff	304	#define TIM_DMABase_BDTR (0x00000011)
bogdanm	0:9b334a45a8ff	305	#define TIM_DMABase_DCR (0x00000012)
bogdanm	0:9b334a45a8ff	306	#define TIM_DMABase_OR (0x00000013)
bogdanm	0:9b334a45a8ff	307	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
bogdanm	0:9b334a45a8ff	308	((BASE) == TIM_DMABase_CR2) \|\| \
bogdanm	0:9b334a45a8ff	309	((BASE) == TIM_DMABase_SMCR) \|\| \
bogdanm	0:9b334a45a8ff	310	((BASE) == TIM_DMABase_DIER) \|\| \
bogdanm	0:9b334a45a8ff	311	((BASE) == TIM_DMABase_SR) \|\| \
bogdanm	0:9b334a45a8ff	312	((BASE) == TIM_DMABase_EGR) \|\| \
bogdanm	0:9b334a45a8ff	313	((BASE) == TIM_DMABase_CCMR1) \|\| \
bogdanm	0:9b334a45a8ff	314	((BASE) == TIM_DMABase_CCMR2) \|\| \
bogdanm	0:9b334a45a8ff	315	((BASE) == TIM_DMABase_CCER) \|\| \
bogdanm	0:9b334a45a8ff	316	((BASE) == TIM_DMABase_CNT) \|\| \
bogdanm	0:9b334a45a8ff	317	((BASE) == TIM_DMABase_PSC) \|\| \
bogdanm	0:9b334a45a8ff	318	((BASE) == TIM_DMABase_ARR) \|\| \
bogdanm	0:9b334a45a8ff	319	((BASE) == TIM_DMABase_RCR) \|\| \
bogdanm	0:9b334a45a8ff	320	((BASE) == TIM_DMABase_CCR1) \|\| \
bogdanm	0:9b334a45a8ff	321	((BASE) == TIM_DMABase_CCR2) \|\| \
bogdanm	0:9b334a45a8ff	322	((BASE) == TIM_DMABase_CCR3) \|\| \
bogdanm	0:9b334a45a8ff	323	((BASE) == TIM_DMABase_CCR4) \|\| \
bogdanm	0:9b334a45a8ff	324	((BASE) == TIM_DMABase_BDTR) \|\| \
bogdanm	0:9b334a45a8ff	325	((BASE) == TIM_DMABase_DCR) \|\| \
bogdanm	0:9b334a45a8ff	326	((BASE) == TIM_DMABase_OR))
bogdanm	0:9b334a45a8ff	327	/**
bogdanm	0:9b334a45a8ff	328	* @}
bogdanm	0:9b334a45a8ff	329	*/
bogdanm	0:9b334a45a8ff	330	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	333	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	0:9b334a45a8ff	334	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	335	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	336	/** @defgroup TIMEx_Channel TIM Extended Channel
bogdanm	0:9b334a45a8ff	337	* @{
bogdanm	0:9b334a45a8ff	338	*/
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	341	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	342	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm	0:9b334a45a8ff	343	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm	0:9b334a45a8ff	344	#define TIM_CHANNEL_5 ((uint32_t)0x0010)
bogdanm	0:9b334a45a8ff	345	#define TIM_CHANNEL_6 ((uint32_t)0x0014)
bogdanm	0:9b334a45a8ff	346	#define TIM_CHANNEL_ALL ((uint32_t)0x003C)
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	349	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	350	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	351	((CHANNEL) == TIM_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	352	((CHANNEL) == TIM_CHANNEL_5) \|\| \
bogdanm	0:9b334a45a8ff	353	((CHANNEL) == TIM_CHANNEL_6) \|\| \
bogdanm	0:9b334a45a8ff	354	((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm	0:9b334a45a8ff	355
bogdanm	0:9b334a45a8ff	356	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	357	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	360	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	361
bogdanm	0:9b334a45a8ff	362	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	363	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	364	((CHANNEL) == TIM_CHANNEL_3))
bogdanm	0:9b334a45a8ff	365	/**
bogdanm	0:9b334a45a8ff	366	* @}
bogdanm	0:9b334a45a8ff	367	*/
bogdanm	0:9b334a45a8ff	368
bogdanm	0:9b334a45a8ff	369	/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Extended Output Compare and PWM Modes
bogdanm	0:9b334a45a8ff	370	* @{
bogdanm	0:9b334a45a8ff	371	*/
bogdanm	0:9b334a45a8ff	372	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	373	#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	374	#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	375	#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	376	#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	377	#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	378	#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	379	#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
bogdanm	0:9b334a45a8ff	382	#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	383	#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	384	#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	385	#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	386	#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M)
bogdanm	0:9b334a45a8ff	387
bogdanm	0:9b334a45a8ff	388	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
bogdanm	0:9b334a45a8ff	389	((MODE) == TIM_OCMODE_PWM2) \|\| \
bogdanm	0:9b334a45a8ff	390	((MODE) == TIM_OCMODE_COMBINED_PWM1) \|\| \
bogdanm	0:9b334a45a8ff	391	((MODE) == TIM_OCMODE_COMBINED_PWM2) \|\| \
bogdanm	0:9b334a45a8ff	392	((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) \|\| \
bogdanm	0:9b334a45a8ff	393	((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
bogdanm	0:9b334a45a8ff	394
bogdanm	0:9b334a45a8ff	395	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
bogdanm	0:9b334a45a8ff	396	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	397	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	398	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
bogdanm	0:9b334a45a8ff	399	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	400	((MODE) == TIM_OCMODE_FORCED_INACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	401	((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) \|\| \
bogdanm	0:9b334a45a8ff	402	((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
bogdanm	0:9b334a45a8ff	403	/**
bogdanm	0:9b334a45a8ff	404	* @}
bogdanm	0:9b334a45a8ff	405	*/
bogdanm	0:9b334a45a8ff	406
bogdanm	0:9b334a45a8ff	407	/** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source
bogdanm	0:9b334a45a8ff	408	* @{
bogdanm	0:9b334a45a8ff	409	*/
bogdanm	0:9b334a45a8ff	410	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	411	#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
bogdanm	0:9b334a45a8ff	412	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414	#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
bogdanm	0:9b334a45a8ff	415	((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) \|\| \
bogdanm	0:9b334a45a8ff	416	((MODE) == TIM_CLEARINPUTSOURCE_NONE))
bogdanm	0:9b334a45a8ff	417	/**
bogdanm	0:9b334a45a8ff	418	* @}
bogdanm	0:9b334a45a8ff	419	*/
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	/** @defgroup TIMEx_BreakInput_Filter TIM Extended Break Input Filter
bogdanm	0:9b334a45a8ff	422	* @{
bogdanm	0:9b334a45a8ff	423	*/
bogdanm	0:9b334a45a8ff	424
bogdanm	0:9b334a45a8ff	425	#define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	426	/**
bogdanm	0:9b334a45a8ff	427	* @}
bogdanm	0:9b334a45a8ff	428	*/
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	/** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
bogdanm	0:9b334a45a8ff	431	* @{
bogdanm	0:9b334a45a8ff	432	*/
bogdanm	0:9b334a45a8ff	433	#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	434	#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
bogdanm	0:9b334a45a8ff	435
bogdanm	0:9b334a45a8ff	436	#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	437	((STATE) == TIM_BREAK2_DISABLE))
bogdanm	0:9b334a45a8ff	438	/**
bogdanm	0:9b334a45a8ff	439	* @}
bogdanm	0:9b334a45a8ff	440	*/
bogdanm	0:9b334a45a8ff	441	/** @defgroup TIMEx_Break2_Polarity TIM Extended Break Input 2 Polarity
bogdanm	0:9b334a45a8ff	442	* @{
bogdanm	0:9b334a45a8ff	443	*/
bogdanm	0:9b334a45a8ff	444	#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	445	#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
bogdanm	0:9b334a45a8ff	446
bogdanm	0:9b334a45a8ff	447	#define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) \|\| \
bogdanm	0:9b334a45a8ff	448	((POLARITY) == TIM_BREAK2POLARITY_HIGH))
bogdanm	0:9b334a45a8ff	449	/**
bogdanm	0:9b334a45a8ff	450	* @}
bogdanm	0:9b334a45a8ff	451	*/
bogdanm	0:9b334a45a8ff	452
bogdanm	0:9b334a45a8ff	453	/** @defgroup TIMEx_Master_Mode_Selection_2 TIM Extended Master Mode Selection 2 (TRGO2)
bogdanm	0:9b334a45a8ff	454	* @{
bogdanm	0:9b334a45a8ff	455	*/
bogdanm	0:9b334a45a8ff	456	#define TIM_TRGO2_RESET ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	457	#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	458	#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
bogdanm	0:9b334a45a8ff	459	#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	460	#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
bogdanm	0:9b334a45a8ff	461	#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	462	#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1))
bogdanm	0:9b334a45a8ff	463	#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	464	#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
bogdanm	0:9b334a45a8ff	465	#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	466	#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1))
bogdanm	0:9b334a45a8ff	467	#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	468	#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2))
bogdanm	0:9b334a45a8ff	469	#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	470	#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1))
bogdanm	0:9b334a45a8ff	471	#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
bogdanm	0:9b334a45a8ff	472
bogdanm	0:9b334a45a8ff	473	#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) \|\| \
bogdanm	0:9b334a45a8ff	474	((SOURCE) == TIM_TRGO2_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	475	((SOURCE) == TIM_TRGO2_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	476	((SOURCE) == TIM_TRGO2_OC1) \|\| \
bogdanm	0:9b334a45a8ff	477	((SOURCE) == TIM_TRGO2_OC1REF) \|\| \
bogdanm	0:9b334a45a8ff	478	((SOURCE) == TIM_TRGO2_OC2REF) \|\| \
bogdanm	0:9b334a45a8ff	479	((SOURCE) == TIM_TRGO2_OC3REF) \|\| \
bogdanm	0:9b334a45a8ff	480	((SOURCE) == TIM_TRGO2_OC3REF) \|\| \
bogdanm	0:9b334a45a8ff	481	((SOURCE) == TIM_TRGO2_OC4REF) \|\| \
bogdanm	0:9b334a45a8ff	482	((SOURCE) == TIM_TRGO2_OC5REF) \|\| \
bogdanm	0:9b334a45a8ff	483	((SOURCE) == TIM_TRGO2_OC6REF) \|\| \
bogdanm	0:9b334a45a8ff	484	((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) \|\| \
bogdanm	0:9b334a45a8ff	485	((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) \|\| \
bogdanm	0:9b334a45a8ff	486	((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) \|\| \
bogdanm	0:9b334a45a8ff	487	((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	488	((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) \|\| \
bogdanm	0:9b334a45a8ff	489	((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
bogdanm	0:9b334a45a8ff	490	/**
bogdanm	0:9b334a45a8ff	491	* @}
bogdanm	0:9b334a45a8ff	492	*/
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	/** @defgroup TIMEx_Slave_Mode TIM Extended Slave mode
bogdanm	0:9b334a45a8ff	495	* @{
bogdanm	0:9b334a45a8ff	496	*/
bogdanm	0:9b334a45a8ff	497	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	498	#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
bogdanm	0:9b334a45a8ff	499	#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0))
bogdanm	0:9b334a45a8ff	500	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1))
bogdanm	0:9b334a45a8ff	501	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0))
bogdanm	0:9b334a45a8ff	502	#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
bogdanm	0:9b334a45a8ff	503
bogdanm	0:9b334a45a8ff	504	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	505	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
bogdanm	0:9b334a45a8ff	506	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
bogdanm	0:9b334a45a8ff	507	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
bogdanm	0:9b334a45a8ff	508	((MODE) == TIM_SLAVEMODE_EXTERNAL1) \|\| \
bogdanm	0:9b334a45a8ff	509	((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
bogdanm	0:9b334a45a8ff	510	/**
bogdanm	0:9b334a45a8ff	511	* @}
bogdanm	0:9b334a45a8ff	512	*/
bogdanm	0:9b334a45a8ff	513
bogdanm	0:9b334a45a8ff	514	/** @defgroup TIM_Event_Source TIM Extended Event Source
bogdanm	0:9b334a45a8ff	515	* @{
bogdanm	0:9b334a45a8ff	516	*/
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	#define TIM_EventSource_Update TIM_EGR_UG /!< Reinitialize the counter and generates an update of the registers /
bogdanm	0:9b334a45a8ff	519	#define TIM_EventSource_CC1 TIM_EGR_CC1G /!< A capture/compare event is generated on channel 1 /
bogdanm	0:9b334a45a8ff	520	#define TIM_EventSource_CC2 TIM_EGR_CC2G /!< A capture/compare event is generated on channel 2 /
bogdanm	0:9b334a45a8ff	521	#define TIM_EventSource_CC3 TIM_EGR_CC3G /!< A capture/compare event is generated on channel 3 /
bogdanm	0:9b334a45a8ff	522	#define TIM_EventSource_CC4 TIM_EGR_CC4G /!< A capture/compare event is generated on channel 4 /
bogdanm	0:9b334a45a8ff	523	#define TIM_EventSource_COM TIM_EGR_COMG /!< A commutation event is generated /
bogdanm	0:9b334a45a8ff	524	#define TIM_EventSource_Trigger TIM_EGR_TG /!< A trigger event is generated /
bogdanm	0:9b334a45a8ff	525	#define TIM_EventSource_Break TIM_EGR_BG /!< A break event is generated /
bogdanm	0:9b334a45a8ff	526	#define TIM_EventSource_Break2 TIM_EGR_B2G /!< A break 2 event is generated /
bogdanm	0:9b334a45a8ff	527	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529	/**
bogdanm	0:9b334a45a8ff	530	* @}
bogdanm	0:9b334a45a8ff	531	*/
bogdanm	0:9b334a45a8ff	532
bogdanm	0:9b334a45a8ff	533	/** @defgroup TIM_DMA_Base_address TIM Extended DMA Base Address
bogdanm	0:9b334a45a8ff	534	* @{
bogdanm	0:9b334a45a8ff	535	*/
bogdanm	0:9b334a45a8ff	536
bogdanm	0:9b334a45a8ff	537	#define TIM_DMABase_CR1 (0x00000000)
bogdanm	0:9b334a45a8ff	538	#define TIM_DMABase_CR2 (0x00000001)
bogdanm	0:9b334a45a8ff	539	#define TIM_DMABase_SMCR (0x00000002)
bogdanm	0:9b334a45a8ff	540	#define TIM_DMABase_DIER (0x00000003)
bogdanm	0:9b334a45a8ff	541	#define TIM_DMABase_SR (0x00000004)
bogdanm	0:9b334a45a8ff	542	#define TIM_DMABase_EGR (0x00000005)
bogdanm	0:9b334a45a8ff	543	#define TIM_DMABase_CCMR1 (0x00000006)
bogdanm	0:9b334a45a8ff	544	#define TIM_DMABase_CCMR2 (0x00000007)
bogdanm	0:9b334a45a8ff	545	#define TIM_DMABase_CCER (0x00000008)
bogdanm	0:9b334a45a8ff	546	#define TIM_DMABase_CNT (0x00000009)
bogdanm	0:9b334a45a8ff	547	#define TIM_DMABase_PSC (0x0000000A)
bogdanm	0:9b334a45a8ff	548	#define TIM_DMABase_ARR (0x0000000B)
bogdanm	0:9b334a45a8ff	549	#define TIM_DMABase_RCR (0x0000000C)
bogdanm	0:9b334a45a8ff	550	#define TIM_DMABase_CCR1 (0x0000000D)
bogdanm	0:9b334a45a8ff	551	#define TIM_DMABase_CCR2 (0x0000000E)
bogdanm	0:9b334a45a8ff	552	#define TIM_DMABase_CCR3 (0x0000000F)
bogdanm	0:9b334a45a8ff	553	#define TIM_DMABase_CCR4 (0x00000010)
bogdanm	0:9b334a45a8ff	554	#define TIM_DMABase_BDTR (0x00000011)
bogdanm	0:9b334a45a8ff	555	#define TIM_DMABase_DCR (0x00000012)
bogdanm	0:9b334a45a8ff	556	#define TIM_DMABase_CCMR3 (0x00000015)
bogdanm	0:9b334a45a8ff	557	#define TIM_DMABase_CCR5 (0x00000016)
bogdanm	0:9b334a45a8ff	558	#define TIM_DMABase_CCR6 (0x00000017)
bogdanm	0:9b334a45a8ff	559	#define TIM_DMABase_OR (0x00000018)
bogdanm	0:9b334a45a8ff	560	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
bogdanm	0:9b334a45a8ff	561	((BASE) == TIM_DMABase_CR2) \|\| \
bogdanm	0:9b334a45a8ff	562	((BASE) == TIM_DMABase_SMCR) \|\| \
bogdanm	0:9b334a45a8ff	563	((BASE) == TIM_DMABase_DIER) \|\| \
bogdanm	0:9b334a45a8ff	564	((BASE) == TIM_DMABase_SR) \|\| \
bogdanm	0:9b334a45a8ff	565	((BASE) == TIM_DMABase_EGR) \|\| \
bogdanm	0:9b334a45a8ff	566	((BASE) == TIM_DMABase_CCMR1) \|\| \
bogdanm	0:9b334a45a8ff	567	((BASE) == TIM_DMABase_CCMR2) \|\| \
bogdanm	0:9b334a45a8ff	568	((BASE) == TIM_DMABase_CCER) \|\| \
bogdanm	0:9b334a45a8ff	569	((BASE) == TIM_DMABase_CNT) \|\| \
bogdanm	0:9b334a45a8ff	570	((BASE) == TIM_DMABase_PSC) \|\| \
bogdanm	0:9b334a45a8ff	571	((BASE) == TIM_DMABase_ARR) \|\| \
bogdanm	0:9b334a45a8ff	572	((BASE) == TIM_DMABase_RCR) \|\| \
bogdanm	0:9b334a45a8ff	573	((BASE) == TIM_DMABase_CCR1) \|\| \
bogdanm	0:9b334a45a8ff	574	((BASE) == TIM_DMABase_CCR2) \|\| \
bogdanm	0:9b334a45a8ff	575	((BASE) == TIM_DMABase_CCR3) \|\| \
bogdanm	0:9b334a45a8ff	576	((BASE) == TIM_DMABase_CCR4) \|\| \
bogdanm	0:9b334a45a8ff	577	((BASE) == TIM_DMABase_BDTR) \|\| \
bogdanm	0:9b334a45a8ff	578	((BASE) == TIM_DMABase_CCMR3) \|\| \
bogdanm	0:9b334a45a8ff	579	((BASE) == TIM_DMABase_CCR5) \|\| \
bogdanm	0:9b334a45a8ff	580	((BASE) == TIM_DMABase_CCR6) \|\| \
bogdanm	0:9b334a45a8ff	581	((BASE) == TIM_DMABase_OR))
bogdanm	0:9b334a45a8ff	582	/**
bogdanm	0:9b334a45a8ff	583	* @}
bogdanm	0:9b334a45a8ff	584	*/
bogdanm	0:9b334a45a8ff	585	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	586	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	587	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	588	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	0:9b334a45a8ff	589
bogdanm	0:9b334a45a8ff	590	#if defined(STM32F302xE) \|\| \
bogdanm	0:9b334a45a8ff	591	defined(STM32F302xC) \|\| \
bogdanm	0:9b334a45a8ff	592	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	593	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	594	/** @defgroup TIMEx_Remap TIM Extended Remapping
bogdanm	0:9b334a45a8ff	595	* @{
bogdanm	0:9b334a45a8ff	596	*/
bogdanm	0:9b334a45a8ff	597	#define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
bogdanm	0:9b334a45a8ff	598	#define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
bogdanm	0:9b334a45a8ff	599	#define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
bogdanm	0:9b334a45a8ff	600	#define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
bogdanm	0:9b334a45a8ff	601	#define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
bogdanm	0:9b334a45a8ff	602	#define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
bogdanm	0:9b334a45a8ff	603	#define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
bogdanm	0:9b334a45a8ff	604	#define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
bogdanm	0:9b334a45a8ff	605
bogdanm	0:9b334a45a8ff	606	#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) \|\|\
bogdanm	0:9b334a45a8ff	607	((REMAP) == TIM_TIM1_ADC1_AWD1) \|\|\
bogdanm	0:9b334a45a8ff	608	((REMAP) == TIM_TIM1_ADC1_AWD2) \|\|\
bogdanm	0:9b334a45a8ff	609	((REMAP) == TIM_TIM1_ADC1_AWD3) \|\|\
bogdanm	0:9b334a45a8ff	610	((REMAP) == TIM_TIM16_GPIO) \|\|\
bogdanm	0:9b334a45a8ff	611	((REMAP) == TIM_TIM16_RTC) \|\|\
bogdanm	0:9b334a45a8ff	612	((REMAP) == TIM_TIM16_HSE) \|\|\
bogdanm	0:9b334a45a8ff	613	((REMAP) == TIM_TIM16_MCO))
bogdanm	0:9b334a45a8ff	614	/**
bogdanm	0:9b334a45a8ff	615	* @}
bogdanm	0:9b334a45a8ff	616	*/
bogdanm	0:9b334a45a8ff	617	#endif /* STM32F302xE \|\| */
bogdanm	0:9b334a45a8ff	618	/* STM32F302xC \|\| */
bogdanm	0:9b334a45a8ff	619	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	620	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| */
bogdanm	0:9b334a45a8ff	621
bogdanm	0:9b334a45a8ff	622	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	0:9b334a45a8ff	623	/** @defgroup TIMEx_Remap TIM Extended Remapping 1
bogdanm	0:9b334a45a8ff	624	* @{
bogdanm	0:9b334a45a8ff	625	*/
bogdanm	0:9b334a45a8ff	626	#define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
bogdanm	0:9b334a45a8ff	627	#define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
bogdanm	0:9b334a45a8ff	628	#define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
bogdanm	0:9b334a45a8ff	629	#define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
bogdanm	0:9b334a45a8ff	630	#define TIM_TIM8_ADC2_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
bogdanm	0:9b334a45a8ff	631	#define TIM_TIM8_ADC2_AWD1 (0x00000001) /* !< TIM8_ETR is connected to ADC2 AWD1 */
bogdanm	0:9b334a45a8ff	632	#define TIM_TIM8_ADC2_AWD2 (0x00000002) /* !< TIM8_ETR is connected to ADC2 AWD2 */
bogdanm	0:9b334a45a8ff	633	#define TIM_TIM8_ADC2_AWD3 (0x00000003) /* !< TIM8_ETR is connected to ADC2 AWD3 */
bogdanm	0:9b334a45a8ff	634	#define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
bogdanm	0:9b334a45a8ff	635	#define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
bogdanm	0:9b334a45a8ff	636	#define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
bogdanm	0:9b334a45a8ff	637	#define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
bogdanm	0:9b334a45a8ff	638
bogdanm	0:9b334a45a8ff	639	#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) \|\|\
bogdanm	0:9b334a45a8ff	640	((REMAP1) == TIM_TIM1_ADC1_AWD1) \|\|\
bogdanm	0:9b334a45a8ff	641	((REMAP1) == TIM_TIM1_ADC1_AWD2) \|\|\
bogdanm	0:9b334a45a8ff	642	((REMAP1) == TIM_TIM1_ADC1_AWD3) \|\|\
bogdanm	0:9b334a45a8ff	643	((REMAP1) == TIM_TIM8_ADC2_NONE) \|\|\
bogdanm	0:9b334a45a8ff	644	((REMAP1) == TIM_TIM8_ADC2_AWD1) \|\|\
bogdanm	0:9b334a45a8ff	645	((REMAP1) == TIM_TIM8_ADC2_AWD2) \|\|\
bogdanm	0:9b334a45a8ff	646	((REMAP1) == TIM_TIM8_ADC2_AWD3) \|\|\
bogdanm	0:9b334a45a8ff	647	((REMAP1) == TIM_TIM16_GPIO) \|\|\
bogdanm	0:9b334a45a8ff	648	((REMAP1) == TIM_TIM16_RTC) \|\|\
bogdanm	0:9b334a45a8ff	649	((REMAP1) == TIM_TIM16_HSE) \|\|\
bogdanm	0:9b334a45a8ff	650	((REMAP1) == TIM_TIM16_MCO))
bogdanm	0:9b334a45a8ff	651	/**
bogdanm	0:9b334a45a8ff	652	* @}
bogdanm	0:9b334a45a8ff	653	*/
bogdanm	0:9b334a45a8ff	654
bogdanm	0:9b334a45a8ff	655	/** @defgroup TIMEx_Remap2 TIM Extended Remapping 2
bogdanm	0:9b334a45a8ff	656	* @{
bogdanm	0:9b334a45a8ff	657	*/
bogdanm	0:9b334a45a8ff	658	#define TIM_TIM1_ADC4_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
bogdanm	0:9b334a45a8ff	659	#define TIM_TIM1_ADC4_AWD1 (0x00000004) /* !< TIM1_ETR is connected to ADC4 AWD1 */
bogdanm	0:9b334a45a8ff	660	#define TIM_TIM1_ADC4_AWD2 (0x00000008) /* !< TIM1_ETR is connected to ADC4 AWD2 */
bogdanm	0:9b334a45a8ff	661	#define TIM_TIM1_ADC4_AWD3 (0x0000000C) /* !< TIM1_ETR is connected to ADC4 AWD3 */
bogdanm	0:9b334a45a8ff	662	#define TIM_TIM8_ADC3_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
bogdanm	0:9b334a45a8ff	663	#define TIM_TIM8_ADC3_AWD1 (0x00000004) /* !< TIM8_ETR is connected to ADC3 AWD1 */
bogdanm	0:9b334a45a8ff	664	#define TIM_TIM8_ADC3_AWD2 (0x00000008) /* !< TIM8_ETR is connected to ADC3 AWD2 */
bogdanm	0:9b334a45a8ff	665	#define TIM_TIM8_ADC3_AWD3 (0x0000000C) /* !< TIM8_ETR is connected to ADC3 AWD3 */
bogdanm	0:9b334a45a8ff	666	#define TIM_TIM16_NONE (0x00000000) /* !< Non significant value for TIM16 */
bogdanm	0:9b334a45a8ff	667
bogdanm	0:9b334a45a8ff	668	#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) \|\|\
bogdanm	0:9b334a45a8ff	669	((REMAP2) == TIM_TIM1_ADC4_AWD1) \|\|\
bogdanm	0:9b334a45a8ff	670	((REMAP2) == TIM_TIM1_ADC4_AWD2) \|\|\
bogdanm	0:9b334a45a8ff	671	((REMAP2) == TIM_TIM1_ADC4_AWD3) \|\|\
bogdanm	0:9b334a45a8ff	672	((REMAP2) == TIM_TIM8_ADC3_NONE) \|\|\
bogdanm	0:9b334a45a8ff	673	((REMAP2) == TIM_TIM8_ADC3_AWD1) \|\|\
bogdanm	0:9b334a45a8ff	674	((REMAP2) == TIM_TIM8_ADC3_AWD2) \|\|\
bogdanm	0:9b334a45a8ff	675	((REMAP2) == TIM_TIM8_ADC3_AWD3) \|\|\
bogdanm	0:9b334a45a8ff	676	((REMAP2) == TIM_TIM16_NONE))
bogdanm	0:9b334a45a8ff	677	/**
bogdanm	0:9b334a45a8ff	678	* @}
bogdanm	0:9b334a45a8ff	679	*/
bogdanm	0:9b334a45a8ff	680	#endif /* STM32F303xC \|\| STM32F358xx */
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	0:9b334a45a8ff	683	/** @defgroup TIMEx_Remap TIM Extended Remapping 1
bogdanm	0:9b334a45a8ff	684	* @{
bogdanm	0:9b334a45a8ff	685	*/
bogdanm	0:9b334a45a8ff	686	#define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
bogdanm	0:9b334a45a8ff	687	#define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
bogdanm	0:9b334a45a8ff	688	#define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
bogdanm	0:9b334a45a8ff	689	#define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
bogdanm	0:9b334a45a8ff	690	#define TIM_TIM8_ADC2_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
bogdanm	0:9b334a45a8ff	691	#define TIM_TIM8_ADC2_AWD1 (0x00000001) /* !< TIM8_ETR is connected to ADC2 AWD1 */
bogdanm	0:9b334a45a8ff	692	#define TIM_TIM8_ADC2_AWD2 (0x00000002) /* !< TIM8_ETR is connected to ADC2 AWD2 */
bogdanm	0:9b334a45a8ff	693	#define TIM_TIM8_ADC2_AWD3 (0x00000003) /* !< TIM8_ETR is connected to ADC2 AWD3 */
bogdanm	0:9b334a45a8ff	694	#define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
bogdanm	0:9b334a45a8ff	695	#define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
bogdanm	0:9b334a45a8ff	696	#define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
bogdanm	0:9b334a45a8ff	697	#define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
bogdanm	0:9b334a45a8ff	698	#define TIM_TIM20_ADC3_NONE (0x00000000) /* !< TIM20_ETR is not connected to any AWD (analog watchdog) */
bogdanm	0:9b334a45a8ff	699	#define TIM_TIM20_ADC3_AWD1 (0x00000001) /* !< TIM20_ETR is connected to ADC3 AWD1 */
bogdanm	0:9b334a45a8ff	700	#define TIM_TIM20_ADC3_AWD2 (0x00000002) /* !< TIM20_ETR is connected to ADC3 AWD2 */
bogdanm	0:9b334a45a8ff	701	#define TIM_TIM20_ADC3_AWD3 (0x00000003) /* !< TIM20_ETR is connected to ADC3 AWD3 */
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703	#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) \|\|\
bogdanm	0:9b334a45a8ff	704	((REMAP1) == TIM_TIM1_ADC1_AWD1) \|\|\
bogdanm	0:9b334a45a8ff	705	((REMAP1) == TIM_TIM1_ADC1_AWD2) \|\|\
bogdanm	0:9b334a45a8ff	706	((REMAP1) == TIM_TIM1_ADC1_AWD3) \|\|\
bogdanm	0:9b334a45a8ff	707	((REMAP1) == TIM_TIM8_ADC2_NONE) \|\|\
bogdanm	0:9b334a45a8ff	708	((REMAP1) == TIM_TIM8_ADC2_AWD1) \|\|\
bogdanm	0:9b334a45a8ff	709	((REMAP1) == TIM_TIM8_ADC2_AWD2) \|\|\
bogdanm	0:9b334a45a8ff	710	((REMAP1) == TIM_TIM8_ADC2_AWD3) \|\|\
bogdanm	0:9b334a45a8ff	711	((REMAP1) == TIM_TIM16_GPIO) \|\|\
bogdanm	0:9b334a45a8ff	712	((REMAP1) == TIM_TIM16_RTC) \|\|\
bogdanm	0:9b334a45a8ff	713	((REMAP1) == TIM_TIM16_HSE) \|\|\
bogdanm	0:9b334a45a8ff	714	((REMAP1) == TIM_TIM16_MCO) \|\|\
bogdanm	0:9b334a45a8ff	715	((REMAP1) == TIM_TIM20_ADC3_NONE) \|\|\
bogdanm	0:9b334a45a8ff	716	((REMAP1) == TIM_TIM20_ADC3_AWD1) \|\|\
bogdanm	0:9b334a45a8ff	717	((REMAP1) == TIM_TIM20_ADC3_AWD2) \|\|\
bogdanm	0:9b334a45a8ff	718	((REMAP1) == TIM_TIM20_ADC3_AWD3))
bogdanm	0:9b334a45a8ff	719	/**
bogdanm	0:9b334a45a8ff	720	* @}
bogdanm	0:9b334a45a8ff	721	*/
bogdanm	0:9b334a45a8ff	722
bogdanm	0:9b334a45a8ff	723	/** @defgroup TIMEx_Remap2 TIM Extended Remapping 2
bogdanm	0:9b334a45a8ff	724	* @{
bogdanm	0:9b334a45a8ff	725	*/
bogdanm	0:9b334a45a8ff	726	#define TIM_TIM1_ADC4_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
bogdanm	0:9b334a45a8ff	727	#define TIM_TIM1_ADC4_AWD1 (0x00000004) /* !< TIM1_ETR is connected to ADC4 AWD1 */
bogdanm	0:9b334a45a8ff	728	#define TIM_TIM1_ADC4_AWD2 (0x00000008) /* !< TIM1_ETR is connected to ADC4 AWD2 */
bogdanm	0:9b334a45a8ff	729	#define TIM_TIM1_ADC4_AWD3 (0x0000000C) /* !< TIM1_ETR is connected to ADC4 AWD3 */
bogdanm	0:9b334a45a8ff	730	#define TIM_TIM8_ADC3_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
bogdanm	0:9b334a45a8ff	731	#define TIM_TIM8_ADC3_AWD1 (0x00000004) /* !< TIM8_ETR is connected to ADC3 AWD1 */
bogdanm	0:9b334a45a8ff	732	#define TIM_TIM8_ADC3_AWD2 (0x00000008) /* !< TIM8_ETR is connected to ADC3 AWD2 */
bogdanm	0:9b334a45a8ff	733	#define TIM_TIM8_ADC3_AWD3 (0x0000000C) /* !< TIM8_ETR is connected to ADC3 AWD3 */
bogdanm	0:9b334a45a8ff	734	#define TIM_TIM16_NONE (0x00000000) /* !< Non significant value for TIM16 */
bogdanm	0:9b334a45a8ff	735	#define TIM_TIM20_ADC4_NONE (0x00000000) /* !< TIM20_ETR is not connected to any AWD (analog watchdog) */
bogdanm	0:9b334a45a8ff	736	#define TIM_TIM20_ADC4_AWD1 (0x00000004) /* !< TIM20_ETR is connected to ADC4 AWD1 */
bogdanm	0:9b334a45a8ff	737	#define TIM_TIM20_ADC4_AWD2 (0x00000008) /* !< TIM20_ETR is connected to ADC4 AWD2 */
bogdanm	0:9b334a45a8ff	738	#define TIM_TIM20_ADC4_AWD3 (0x0000000C) /* !< TIM20_ETR is connected to ADC4 AWD3 */
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) \|\|\
bogdanm	0:9b334a45a8ff	741	((REMAP2) == TIM_TIM1_ADC4_AWD1) \|\|\
bogdanm	0:9b334a45a8ff	742	((REMAP2) == TIM_TIM1_ADC4_AWD2) \|\|\
bogdanm	0:9b334a45a8ff	743	((REMAP2) == TIM_TIM1_ADC4_AWD3) \|\|\
bogdanm	0:9b334a45a8ff	744	((REMAP2) == TIM_TIM8_ADC3_NONE) \|\|\
bogdanm	0:9b334a45a8ff	745	((REMAP2) == TIM_TIM8_ADC3_AWD1) \|\|\
bogdanm	0:9b334a45a8ff	746	((REMAP2) == TIM_TIM8_ADC3_AWD2) \|\|\
bogdanm	0:9b334a45a8ff	747	((REMAP2) == TIM_TIM8_ADC3_AWD3) \|\|\
bogdanm	0:9b334a45a8ff	748	((REMAP2) == TIM_TIM16_NONE) \|\|\
bogdanm	0:9b334a45a8ff	749	((REMAP2) == TIM_TIM20_ADC4_NONE) \|\|\
bogdanm	0:9b334a45a8ff	750	((REMAP2) == TIM_TIM20_ADC4_AWD1) \|\|\
bogdanm	0:9b334a45a8ff	751	((REMAP2) == TIM_TIM20_ADC4_AWD2) \|\|\
bogdanm	0:9b334a45a8ff	752	((REMAP2) == TIM_TIM20_ADC4_AWD3))
bogdanm	0:9b334a45a8ff	753	/**
bogdanm	0:9b334a45a8ff	754	* @}
bogdanm	0:9b334a45a8ff	755	*/
bogdanm	0:9b334a45a8ff	756	#endif /* STM32F303xE \|\| STM32F398xx */
bogdanm	0:9b334a45a8ff	757
bogdanm	0:9b334a45a8ff	758
bogdanm	0:9b334a45a8ff	759	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	0:9b334a45a8ff	760	/** @defgroup TIMEx_Remap TIM Extended remapping
bogdanm	0:9b334a45a8ff	761	* @{
bogdanm	0:9b334a45a8ff	762	*/
bogdanm	0:9b334a45a8ff	763
bogdanm	0:9b334a45a8ff	764	#define TIM_TIM2_TIM8_TRGO (0x00000000) /!< TIM8 TRGOUT is connected to TIM2_ITR1 /
bogdanm	0:9b334a45a8ff	765	#define TIM_TIM2_ETH_PTP (0x00000400) /!< PTP trigger output is connected to TIM2_ITR1 /
bogdanm	0:9b334a45a8ff	766	#define TIM_TIM2_USBFS_SOF (0x00000800) /!< OTG FS SOF is connected to the TIM2_ITR1 input /
bogdanm	0:9b334a45a8ff	767	#define TIM_TIM2_USBHS_SOF (0x00000C00) /!< OTG HS SOF is connected to the TIM2_ITR1 input /
bogdanm	0:9b334a45a8ff	768	#define TIM_TIM14_GPIO (0x00000000) /* !< TIM14 TI1 is connected to GPIO */
bogdanm	0:9b334a45a8ff	769	#define TIM_TIM14_RTC (0x00000001) /* !< TIM14 TI1 is connected to RTC_clock */
bogdanm	0:9b334a45a8ff	770	#define TIM_TIM14_HSE (0x00000002) /* !< TIM14 TI1 is connected to HSE/32 */
bogdanm	0:9b334a45a8ff	771	#define TIM_TIM14_MCO (0x00000003) /* !< TIM14 TI1 is connected to MCO */
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773	#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) \|\|\
bogdanm	0:9b334a45a8ff	774	((REMAP) == TIM_TIM2_ETH_PTP) \|\|\
bogdanm	0:9b334a45a8ff	775	((REMAP) == TIM_TIM2_USBFS_SOF) \|\|\
bogdanm	0:9b334a45a8ff	776	((REMAP) == TIM_TIM2_USBHS_SOF) \|\|\
bogdanm	0:9b334a45a8ff	777	((REMAP) == TIM_TIM14_GPIO) \|\|\
bogdanm	0:9b334a45a8ff	778	((REMAP) == TIM_TIM14_RTC) \|\|\
bogdanm	0:9b334a45a8ff	779	((REMAP) == TIM_TIM14_HSE) \|\|\
bogdanm	0:9b334a45a8ff	780	((REMAP) == TIM_TIM14_MCO))
bogdanm	0:9b334a45a8ff	781
bogdanm	0:9b334a45a8ff	782	/**
bogdanm	0:9b334a45a8ff	783	* @}
bogdanm	0:9b334a45a8ff	784	*/
bogdanm	0:9b334a45a8ff	785	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	0:9b334a45a8ff	786
bogdanm	0:9b334a45a8ff	787	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	788	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	0:9b334a45a8ff	789	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	790	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	791	/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
bogdanm	0:9b334a45a8ff	792	* @{
bogdanm	0:9b334a45a8ff	793	*/
bogdanm	0:9b334a45a8ff	794	#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
bogdanm	0:9b334a45a8ff	795	#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
bogdanm	0:9b334a45a8ff	796	#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
bogdanm	0:9b334a45a8ff	797	#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
bogdanm	0:9b334a45a8ff	798
bogdanm	0:9b334a45a8ff	799	#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
bogdanm	0:9b334a45a8ff	800	/**
bogdanm	0:9b334a45a8ff	801	* @}
bogdanm	0:9b334a45a8ff	802	*/
bogdanm	0:9b334a45a8ff	803	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	804	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	805	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	806	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	0:9b334a45a8ff	807
bogdanm	0:9b334a45a8ff	808	/** @defgroup TIM_Clock_Filter TIM Clock Filter
bogdanm	0:9b334a45a8ff	809	* @{
bogdanm	0:9b334a45a8ff	810	*/
bogdanm	0:9b334a45a8ff	811	#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
bogdanm	0:9b334a45a8ff	812	/**
bogdanm	0:9b334a45a8ff	813	* @}
bogdanm	0:9b334a45a8ff	814	*/
bogdanm	0:9b334a45a8ff	815
bogdanm	0:9b334a45a8ff	816	/**
bogdanm	0:9b334a45a8ff	817	* @}
bogdanm	0:9b334a45a8ff	818	*/
bogdanm	0:9b334a45a8ff	819
bogdanm	0:9b334a45a8ff	820	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	821	/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
bogdanm	0:9b334a45a8ff	822	* @{
bogdanm	0:9b334a45a8ff	823	*/
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	0:9b334a45a8ff	826	/**
bogdanm	0:9b334a45a8ff	827	* @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm	0:9b334a45a8ff	828	* calling another time ConfigChannel function.
bogdanm	0:9b334a45a8ff	829	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	830	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	831	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	832	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	833	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	834	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	835	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	836	* @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm	0:9b334a45a8ff	837	* @retval None
bogdanm	0:9b334a45a8ff	838	*/
bogdanm	0:9b334a45a8ff	839	#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm	0:9b334a45a8ff	840	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm	0:9b334a45a8ff	841
bogdanm	0:9b334a45a8ff	842	/**
bogdanm	0:9b334a45a8ff	843	* @brief Gets the TIM Capture Compare Register value on runtime
bogdanm	0:9b334a45a8ff	844	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	845	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm	0:9b334a45a8ff	846	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	847	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm	0:9b334a45a8ff	848	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm	0:9b334a45a8ff	849	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm	0:9b334a45a8ff	850	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm	0:9b334a45a8ff	851	* @retval None
bogdanm	0:9b334a45a8ff	852	*/
bogdanm	0:9b334a45a8ff	853	#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	854	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm	0:9b334a45a8ff	855	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	858	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	0:9b334a45a8ff	859	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	860	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	861	/**
bogdanm	0:9b334a45a8ff	862	* @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm	0:9b334a45a8ff	863	* calling another time ConfigChannel function.
bogdanm	0:9b334a45a8ff	864	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	865	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	866	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	867	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	868	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	869	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	870	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	871	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
bogdanm	0:9b334a45a8ff	872	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
bogdanm	0:9b334a45a8ff	873	* @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm	0:9b334a45a8ff	874	* @retval None
bogdanm	0:9b334a45a8ff	875	*/
bogdanm	0:9b334a45a8ff	876	#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm	0:9b334a45a8ff	877	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	878	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	879	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	880	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	881	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	882	((__HANDLE__)->Instance->CCR6 \|= (__COMPARE__)))
bogdanm	0:9b334a45a8ff	883
bogdanm	0:9b334a45a8ff	884	/**
bogdanm	0:9b334a45a8ff	885	* @brief Gets the TIM Capture Compare Register value on runtime
bogdanm	0:9b334a45a8ff	886	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	887	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm	0:9b334a45a8ff	888	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	889	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm	0:9b334a45a8ff	890	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm	0:9b334a45a8ff	891	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm	0:9b334a45a8ff	892	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm	0:9b334a45a8ff	893	* @arg TIM_CHANNEL_5: get capture/compare 5 register value
bogdanm	0:9b334a45a8ff	894	* @arg TIM_CHANNEL_6: get capture/compare 6 register value
bogdanm	0:9b334a45a8ff	895	* @retval None
bogdanm	0:9b334a45a8ff	896	*/
bogdanm	0:9b334a45a8ff	897	#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	898	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
bogdanm	0:9b334a45a8ff	899	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
bogdanm	0:9b334a45a8ff	900	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
bogdanm	0:9b334a45a8ff	901	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
bogdanm	0:9b334a45a8ff	902	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
bogdanm	0:9b334a45a8ff	903	((__HANDLE__)->Instance->CCR6))
bogdanm	0:9b334a45a8ff	904	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	905	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	906	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	907	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	0:9b334a45a8ff	908	/**
bogdanm	0:9b334a45a8ff	909	* @}
bogdanm	0:9b334a45a8ff	910	*/
bogdanm	0:9b334a45a8ff	911
bogdanm	0:9b334a45a8ff	912	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	913	/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
bogdanm	0:9b334a45a8ff	914	* @{
bogdanm	0:9b334a45a8ff	915	*/
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
bogdanm	0:9b334a45a8ff	918	* @brief Timer Hall Sensor functions
bogdanm	0:9b334a45a8ff	919	* @{
bogdanm	0:9b334a45a8ff	920	*/
bogdanm	0:9b334a45a8ff	921	/* Timer Hall Sensor functions **********************************************/
bogdanm	0:9b334a45a8ff	922	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef htim, TIM_HallSensor_InitTypeDef sConfig);
bogdanm	0:9b334a45a8ff	923	HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	924
bogdanm	0:9b334a45a8ff	925	void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	926	void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	927
bogdanm	0:9b334a45a8ff	928	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	929	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	930	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	931	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	932	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	933	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	934	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	935	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	936	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	937	/**
bogdanm	0:9b334a45a8ff	938	* @}
bogdanm	0:9b334a45a8ff	939	*/
bogdanm	0:9b334a45a8ff	940
bogdanm	0:9b334a45a8ff	941	/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
bogdanm	0:9b334a45a8ff	942	* @brief Timer Complementary Output Compare functions
bogdanm	0:9b334a45a8ff	943	* @{
bogdanm	0:9b334a45a8ff	944	*/
bogdanm	0:9b334a45a8ff	945	/* Timer Complementary Output Compare functions *****************************/
bogdanm	0:9b334a45a8ff	946	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	947	HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	948	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	951	HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	952	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	953
bogdanm	0:9b334a45a8ff	954	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	955	HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	956	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	957	/**
bogdanm	0:9b334a45a8ff	958	* @}
bogdanm	0:9b334a45a8ff	959	*/
bogdanm	0:9b334a45a8ff	960
bogdanm	0:9b334a45a8ff	961	/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
bogdanm	0:9b334a45a8ff	962	* @brief Timer Complementary PWM functions
bogdanm	0:9b334a45a8ff	963	* @{
bogdanm	0:9b334a45a8ff	964	*/
bogdanm	0:9b334a45a8ff	965	/* Timer Complementary PWM functions ****************************************/
bogdanm	0:9b334a45a8ff	966	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	967	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	968	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	969
bogdanm	0:9b334a45a8ff	970	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	971	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	972	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	973	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	974	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	975	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	976	/**
bogdanm	0:9b334a45a8ff	977	* @}
bogdanm	0:9b334a45a8ff	978	*/
bogdanm	0:9b334a45a8ff	979
bogdanm	0:9b334a45a8ff	980	/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
bogdanm	0:9b334a45a8ff	981	* @brief Timer Complementary One Pulse functions
bogdanm	0:9b334a45a8ff	982	* @{
bogdanm	0:9b334a45a8ff	983	*/
bogdanm	0:9b334a45a8ff	984	/* Timer Complementary One Pulse functions **********************************/
bogdanm	0:9b334a45a8ff	985	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	986	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	987	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	990	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	991	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	992	/**
bogdanm	0:9b334a45a8ff	993	* @}
bogdanm	0:9b334a45a8ff	994	*/
bogdanm	0:9b334a45a8ff	995
bogdanm	0:9b334a45a8ff	996	/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	997	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	998	* @{
bogdanm	0:9b334a45a8ff	999	*/
bogdanm	0:9b334a45a8ff	1000	/* Extended Control functions ************************************************/
bogdanm	0:9b334a45a8ff	1001	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
bogdanm	0:9b334a45a8ff	1002	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
bogdanm	0:9b334a45a8ff	1003	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
bogdanm	0:9b334a45a8ff	1004	HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef htim, TIM_MasterConfigTypeDef sMasterConfig);
bogdanm	0:9b334a45a8ff	1005	HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef htim, TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig);
bogdanm	0:9b334a45a8ff	1006
bogdanm	0:9b334a45a8ff	1007	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	1008	defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	0:9b334a45a8ff	1009	HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
bogdanm	0:9b334a45a8ff	1010	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	1011	/* STM32F303xC \|\| STM32F358xx */
bogdanm	0:9b334a45a8ff	1012
bogdanm	0:9b334a45a8ff	1013	#if defined(STM32F302xE) \|\| \
bogdanm	0:9b334a45a8ff	1014	defined(STM32F302xC) \|\| \
bogdanm	0:9b334a45a8ff	1015	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	1016	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
bogdanm	0:9b334a45a8ff	1017	defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	0:9b334a45a8ff	1018	HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
bogdanm	0:9b334a45a8ff	1019	#endif /* STM32F302xE \|\| */
bogdanm	0:9b334a45a8ff	1020	/* STM32F302xC \|\| */
bogdanm	0:9b334a45a8ff	1021	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	1022	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| */
bogdanm	0:9b334a45a8ff	1023	/* STM32F373xC \|\| STM32F378xx */
bogdanm	0:9b334a45a8ff	1024
bogdanm	0:9b334a45a8ff	1025	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	1026	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	0:9b334a45a8ff	1027	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	0:9b334a45a8ff	1028	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	0:9b334a45a8ff	1029	HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
bogdanm	0:9b334a45a8ff	1030	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	1031	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	1032	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	0:9b334a45a8ff	1033	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	0:9b334a45a8ff	1034	/**
bogdanm	0:9b334a45a8ff	1035	* @}
bogdanm	0:9b334a45a8ff	1036	*/
bogdanm	0:9b334a45a8ff	1037
bogdanm	0:9b334a45a8ff	1038	/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
bogdanm	0:9b334a45a8ff	1039	* @brief Extended Callbacks functions
bogdanm	0:9b334a45a8ff	1040	* @{
bogdanm	0:9b334a45a8ff	1041	*/
bogdanm	0:9b334a45a8ff	1042	/* Extended Callback *********************************************************/
bogdanm	0:9b334a45a8ff	1043	void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1044	void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1045	void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1046	/**
bogdanm	0:9b334a45a8ff	1047	* @}
bogdanm	0:9b334a45a8ff	1048	*/
bogdanm	0:9b334a45a8ff	1049
bogdanm	0:9b334a45a8ff	1050	/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
bogdanm	0:9b334a45a8ff	1051	* @brief Extended Peripheral State functions
bogdanm	0:9b334a45a8ff	1052	* @{
bogdanm	0:9b334a45a8ff	1053	*/
bogdanm	0:9b334a45a8ff	1054	/* Extended Peripheral State functions **************************************/
bogdanm	0:9b334a45a8ff	1055	HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1056	/**
bogdanm	0:9b334a45a8ff	1057	* @}
bogdanm	0:9b334a45a8ff	1058	*/
bogdanm	0:9b334a45a8ff	1059
bogdanm	0:9b334a45a8ff	1060	/**
bogdanm	0:9b334a45a8ff	1061	* @}
bogdanm	0:9b334a45a8ff	1062	*/
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	/**
bogdanm	0:9b334a45a8ff	1065	* @}
bogdanm	0:9b334a45a8ff	1066	*/
bogdanm	0:9b334a45a8ff	1067
bogdanm	0:9b334a45a8ff	1068	/**
bogdanm	0:9b334a45a8ff	1069	* @}
bogdanm	0:9b334a45a8ff	1070	*/
bogdanm	0:9b334a45a8ff	1071
bogdanm	0:9b334a45a8ff	1072	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1073	}
bogdanm	0:9b334a45a8ff	1074	#endif
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077	#endif /* __STM32F3xx_HAL_TIM_EX_H */
bogdanm	0:9b334a45a8ff	1078
bogdanm	0:9b334a45a8ff	1079	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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