mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f3xx_hal_tim.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.1.0
bogdanm	0:9b334a45a8ff	6	* @date 12-Sept-2014
bogdanm	0:9b334a45a8ff	7	* @brief Header file of TIM HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F3xx_HAL_TIM_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F3xx_HAL_TIM_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32f3xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32F3xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup TIM
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup TIM_Exported_Types TIM Exported Types
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62	/**
bogdanm	0:9b334a45a8ff	63	* @brief TIM Time base Configuration Structure definition
bogdanm	0:9b334a45a8ff	64	*/
bogdanm	0:9b334a45a8ff	65	typedef struct
bogdanm	0:9b334a45a8ff	66	{
bogdanm	0:9b334a45a8ff	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm	0:9b334a45a8ff	68	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	69
bogdanm	0:9b334a45a8ff	70	uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm	0:9b334a45a8ff	71	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm	0:9b334a45a8ff	74	Auto-Reload Register at the next update event.
bogdanm	0:9b334a45a8ff	75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm	0:9b334a45a8ff	76
bogdanm	0:9b334a45a8ff	77	uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm	0:9b334a45a8ff	78	This parameter can be a value of @ref TIM_ClockDivision */
bogdanm	0:9b334a45a8ff	79
bogdanm	0:9b334a45a8ff	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm	0:9b334a45a8ff	81	reaches zero, an update event is generated and counting restarts
bogdanm	0:9b334a45a8ff	82	from the RCR value (N).
bogdanm	0:9b334a45a8ff	83	This means in PWM mode that (N+1) corresponds to:
bogdanm	0:9b334a45a8ff	84	- the number of PWM periods in edge-aligned mode
bogdanm	0:9b334a45a8ff	85	- the number of half PWM period in center-aligned mode
bogdanm	0:9b334a45a8ff	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
bogdanm	0:9b334a45a8ff	87	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	88	} TIM_Base_InitTypeDef;
bogdanm	0:9b334a45a8ff	89
bogdanm	0:9b334a45a8ff	90	/**
bogdanm	0:9b334a45a8ff	91	* @brief TIM Output Compare Configuration Structure definition
bogdanm	0:9b334a45a8ff	92	*/
bogdanm	0:9b334a45a8ff	93	typedef struct
bogdanm	0:9b334a45a8ff	94	{
bogdanm	0:9b334a45a8ff	95	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	0:9b334a45a8ff	96	This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	99	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	0:9b334a45a8ff	102	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	0:9b334a45a8ff	105	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	0:9b334a45a8ff	106	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	107
bogdanm	0:9b334a45a8ff	108	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm	0:9b334a45a8ff	109	This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm	0:9b334a45a8ff	110	@note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm	0:9b334a45a8ff	111
bogdanm	0:9b334a45a8ff	112
bogdanm	0:9b334a45a8ff	113	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	114	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	0:9b334a45a8ff	115	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	118	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	0:9b334a45a8ff	119	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	120	} TIM_OC_InitTypeDef;
bogdanm	0:9b334a45a8ff	121
bogdanm	0:9b334a45a8ff	122	/**
bogdanm	0:9b334a45a8ff	123	* @brief TIM One Pulse Mode Configuration Structure definition
bogdanm	0:9b334a45a8ff	124	*/
bogdanm	0:9b334a45a8ff	125	typedef struct
bogdanm	0:9b334a45a8ff	126	{
bogdanm	0:9b334a45a8ff	127	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	0:9b334a45a8ff	128	This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
bogdanm	0:9b334a45a8ff	129
bogdanm	0:9b334a45a8ff	130	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	131	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	0:9b334a45a8ff	134	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	0:9b334a45a8ff	135
bogdanm	0:9b334a45a8ff	136	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	0:9b334a45a8ff	137	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	0:9b334a45a8ff	138	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	141	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	0:9b334a45a8ff	142	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	143
bogdanm	0:9b334a45a8ff	144	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	145	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	0:9b334a45a8ff	146	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	147
bogdanm	0:9b334a45a8ff	148	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	149	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	152	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	153
bogdanm	0:9b334a45a8ff	154	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	155	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	156	} TIM_OnePulse_InitTypeDef;
bogdanm	0:9b334a45a8ff	157
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	/**
bogdanm	0:9b334a45a8ff	160	* @brief TIM Input Capture Configuration Structure definition
bogdanm	0:9b334a45a8ff	161	*/
bogdanm	0:9b334a45a8ff	162	typedef struct
bogdanm	0:9b334a45a8ff	163	{
bogdanm	0:9b334a45a8ff	164	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	165	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	166
bogdanm	0:9b334a45a8ff	167	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	168	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	169
bogdanm	0:9b334a45a8ff	170	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	171	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	174	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	175	} TIM_IC_InitTypeDef;
bogdanm	0:9b334a45a8ff	176
bogdanm	0:9b334a45a8ff	177	/**
bogdanm	0:9b334a45a8ff	178	* @brief TIM Encoder Configuration Structure definition
bogdanm	0:9b334a45a8ff	179	*/
bogdanm	0:9b334a45a8ff	180	typedef struct
bogdanm	0:9b334a45a8ff	181	{
bogdanm	0:9b334a45a8ff	182	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	183	This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	186	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	187
bogdanm	0:9b334a45a8ff	188	uint32_t IC1Selection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	189	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	190
bogdanm	0:9b334a45a8ff	191	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	192	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	193
bogdanm	0:9b334a45a8ff	194	uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	195	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	198	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200	uint32_t IC2Selection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	201	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	204	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	208	} TIM_Encoder_InitTypeDef;
bogdanm	0:9b334a45a8ff	209
bogdanm	0:9b334a45a8ff	210
bogdanm	0:9b334a45a8ff	211	/**
bogdanm	0:9b334a45a8ff	212	* @brief Clock Configuration Handle Structure definition
bogdanm	0:9b334a45a8ff	213	*/
bogdanm	0:9b334a45a8ff	214	typedef struct
bogdanm	0:9b334a45a8ff	215	{
bogdanm	0:9b334a45a8ff	216	uint32_t ClockSource; /*!< TIM clock sources
bogdanm	0:9b334a45a8ff	217	This parameter can be a value of @ref TIM_Clock_Source */
bogdanm	0:9b334a45a8ff	218	uint32_t ClockPolarity; /*!< TIM clock polarity
bogdanm	0:9b334a45a8ff	219	This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm	0:9b334a45a8ff	220	uint32_t ClockPrescaler; /*!< TIM clock prescaler
bogdanm	0:9b334a45a8ff	221	This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm	0:9b334a45a8ff	222	uint32_t ClockFilter; /*!< TIM clock filter
bogdanm	0:9b334a45a8ff	223	This parameter can be a value of @ref TIM_Clock_Filter */
bogdanm	0:9b334a45a8ff	224	}TIM_ClockConfigTypeDef;
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	/**
bogdanm	0:9b334a45a8ff	227	* @brief Clear Input Configuration Handle Structure definition
bogdanm	0:9b334a45a8ff	228	*/
bogdanm	0:9b334a45a8ff	229	typedef struct
bogdanm	0:9b334a45a8ff	230	{
bogdanm	0:9b334a45a8ff	231	uint32_t ClearInputState; /*!< TIM clear Input state
bogdanm	0:9b334a45a8ff	232	This parameter can be ENABLE or DISABLE */
bogdanm	0:9b334a45a8ff	233	uint32_t ClearInputSource; /*!< TIM clear Input sources
bogdanm	0:9b334a45a8ff	234	This parameter can be a value of @ref TIMEx_ClearInput_Source */
bogdanm	0:9b334a45a8ff	235	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
bogdanm	0:9b334a45a8ff	236	This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm	0:9b334a45a8ff	237	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
bogdanm	0:9b334a45a8ff	238	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm	0:9b334a45a8ff	239	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
bogdanm	0:9b334a45a8ff	240	This parameter can be a value of @ref TIM_ClearInput_Filter */
bogdanm	0:9b334a45a8ff	241	}TIM_ClearInputConfigTypeDef;
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	/**
bogdanm	0:9b334a45a8ff	244	* @brief TIM Slave configuration Structure definition
bogdanm	0:9b334a45a8ff	245	*/
bogdanm	0:9b334a45a8ff	246	typedef struct {
bogdanm	0:9b334a45a8ff	247	uint32_t SlaveMode; /*!< Slave mode selection
bogdanm	0:9b334a45a8ff	248	This parameter can be a value of @ref TIMEx_Slave_Mode */
bogdanm	0:9b334a45a8ff	249	uint32_t InputTrigger; /*!< Input Trigger source
bogdanm	0:9b334a45a8ff	250	This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm	0:9b334a45a8ff	251	uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm	0:9b334a45a8ff	252	This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm	0:9b334a45a8ff	253	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm	0:9b334a45a8ff	254	This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm	0:9b334a45a8ff	255	uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm	0:9b334a45a8ff	256	This parameter can be a value of @ref TIM_Trigger_Filter */
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	}TIM_SlaveConfigTypeDef;
bogdanm	0:9b334a45a8ff	259
bogdanm	0:9b334a45a8ff	260	/**
bogdanm	0:9b334a45a8ff	261	* @brief HAL State structures definition
bogdanm	0:9b334a45a8ff	262	*/
bogdanm	0:9b334a45a8ff	263	typedef enum
bogdanm	0:9b334a45a8ff	264	{
bogdanm	0:9b334a45a8ff	265	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
bogdanm	0:9b334a45a8ff	266	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	0:9b334a45a8ff	267	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
bogdanm	0:9b334a45a8ff	268	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	0:9b334a45a8ff	269	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
bogdanm	0:9b334a45a8ff	270	}HAL_TIM_StateTypeDef;
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	/**
bogdanm	0:9b334a45a8ff	273	* @brief HAL Active channel structures definition
bogdanm	0:9b334a45a8ff	274	*/
bogdanm	0:9b334a45a8ff	275	typedef enum
bogdanm	0:9b334a45a8ff	276	{
bogdanm	0:9b334a45a8ff	277	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
bogdanm	0:9b334a45a8ff	278	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
bogdanm	0:9b334a45a8ff	279	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
bogdanm	0:9b334a45a8ff	280	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
bogdanm	0:9b334a45a8ff	281	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
bogdanm	0:9b334a45a8ff	282	}HAL_TIM_ActiveChannel;
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	/**
bogdanm	0:9b334a45a8ff	285	* @brief TIM Time Base Handle Structure definition
bogdanm	0:9b334a45a8ff	286	*/
bogdanm	0:9b334a45a8ff	287	typedef struct
bogdanm	0:9b334a45a8ff	288	{
bogdanm	0:9b334a45a8ff	289	TIM_TypeDef Instance; /!< Register base address */
bogdanm	0:9b334a45a8ff	290	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
bogdanm	0:9b334a45a8ff	291	HAL_TIM_ActiveChannel Channel; /!< Active channel /
bogdanm	0:9b334a45a8ff	292	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
bogdanm	0:9b334a45a8ff	293	This array is accessed by a @ref DMA_Handle_index */
bogdanm	0:9b334a45a8ff	294	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	0:9b334a45a8ff	295	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
bogdanm	0:9b334a45a8ff	296	}TIM_HandleTypeDef;
bogdanm	0:9b334a45a8ff	297
bogdanm	0:9b334a45a8ff	298	/**
bogdanm	0:9b334a45a8ff	299	* @}
bogdanm	0:9b334a45a8ff	300	*/
bogdanm	0:9b334a45a8ff	301
bogdanm	0:9b334a45a8ff	302	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	303	/** @defgroup TIM_Exported_Constants TIM Exported Constants
bogdanm	0:9b334a45a8ff	304	* @{
bogdanm	0:9b334a45a8ff	305	*/
bogdanm	0:9b334a45a8ff	306
bogdanm	0:9b334a45a8ff	307	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
bogdanm	0:9b334a45a8ff	308	* @{
bogdanm	0:9b334a45a8ff	309	*/
bogdanm	0:9b334a45a8ff	310	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	311	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	312	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	313	/**
bogdanm	0:9b334a45a8ff	314	* @}
bogdanm	0:9b334a45a8ff	315	*/
bogdanm	0:9b334a45a8ff	316
bogdanm	0:9b334a45a8ff	317	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
bogdanm	0:9b334a45a8ff	318	* @{
bogdanm	0:9b334a45a8ff	319	*/
bogdanm	0:9b334a45a8ff	320	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
bogdanm	0:9b334a45a8ff	321	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
bogdanm	0:9b334a45a8ff	322	/**
bogdanm	0:9b334a45a8ff	323	* @}
bogdanm	0:9b334a45a8ff	324	*/
bogdanm	0:9b334a45a8ff	325
bogdanm	0:9b334a45a8ff	326	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
bogdanm	0:9b334a45a8ff	327	* @{
bogdanm	0:9b334a45a8ff	328	*/
bogdanm	0:9b334a45a8ff	329	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	330	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
bogdanm	0:9b334a45a8ff	331	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
bogdanm	0:9b334a45a8ff	332	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
bogdanm	0:9b334a45a8ff	333	/**
bogdanm	0:9b334a45a8ff	334	* @}
bogdanm	0:9b334a45a8ff	335	*/
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	/** @defgroup TIM_Counter_Mode TIM Counter Mode
bogdanm	0:9b334a45a8ff	338	* @{
bogdanm	0:9b334a45a8ff	339	*/
bogdanm	0:9b334a45a8ff	340
bogdanm	0:9b334a45a8ff	341	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm	0:9b334a45a8ff	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm	0:9b334a45a8ff	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm	0:9b334a45a8ff	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm	0:9b334a45a8ff	346
bogdanm	0:9b334a45a8ff	347	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
bogdanm	0:9b334a45a8ff	348	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
bogdanm	0:9b334a45a8ff	349	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
bogdanm	0:9b334a45a8ff	350	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
bogdanm	0:9b334a45a8ff	351	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm	0:9b334a45a8ff	352	/**
bogdanm	0:9b334a45a8ff	353	* @}
bogdanm	0:9b334a45a8ff	354	*/
bogdanm	0:9b334a45a8ff	355
bogdanm	0:9b334a45a8ff	356	/** @defgroup TIM_ClockDivision TIM Clock Division
bogdanm	0:9b334a45a8ff	357	* @{
bogdanm	0:9b334a45a8ff	358	*/
bogdanm	0:9b334a45a8ff	359
bogdanm	0:9b334a45a8ff	360	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	361	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm	0:9b334a45a8ff	362	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm	0:9b334a45a8ff	363
bogdanm	0:9b334a45a8ff	364	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	365	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	366	((DIV) == TIM_CLOCKDIVISION_DIV4))
bogdanm	0:9b334a45a8ff	367	/**
bogdanm	0:9b334a45a8ff	368	* @}
bogdanm	0:9b334a45a8ff	369	*/
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
bogdanm	0:9b334a45a8ff	372	* @{
bogdanm	0:9b334a45a8ff	373	*/
bogdanm	0:9b334a45a8ff	374
bogdanm	0:9b334a45a8ff	375	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	376	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm	0:9b334a45a8ff	377
bogdanm	0:9b334a45a8ff	378	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	379	((STATE) == TIM_OUTPUTSTATE_ENABLE))
bogdanm	0:9b334a45a8ff	380	/**
bogdanm	0:9b334a45a8ff	381	* @}
bogdanm	0:9b334a45a8ff	382	*/
bogdanm	0:9b334a45a8ff	383	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
bogdanm	0:9b334a45a8ff	384	* @{
bogdanm	0:9b334a45a8ff	385	*/
bogdanm	0:9b334a45a8ff	386	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	387	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm	0:9b334a45a8ff	388
bogdanm	0:9b334a45a8ff	389	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	390	((STATE) == TIM_OCFAST_ENABLE))
bogdanm	0:9b334a45a8ff	391	/**
bogdanm	0:9b334a45a8ff	392	* @}
bogdanm	0:9b334a45a8ff	393	*/
bogdanm	0:9b334a45a8ff	394	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
bogdanm	0:9b334a45a8ff	395	* @{
bogdanm	0:9b334a45a8ff	396	*/
bogdanm	0:9b334a45a8ff	397
bogdanm	0:9b334a45a8ff	398	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	399	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm	0:9b334a45a8ff	400
bogdanm	0:9b334a45a8ff	401	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	402	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
bogdanm	0:9b334a45a8ff	403	/**
bogdanm	0:9b334a45a8ff	404	* @}
bogdanm	0:9b334a45a8ff	405	*/
bogdanm	0:9b334a45a8ff	406
bogdanm	0:9b334a45a8ff	407	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
bogdanm	0:9b334a45a8ff	408	* @{
bogdanm	0:9b334a45a8ff	409	*/
bogdanm	0:9b334a45a8ff	410
bogdanm	0:9b334a45a8ff	411	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	412	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	415	((POLARITY) == TIM_OCPOLARITY_LOW))
bogdanm	0:9b334a45a8ff	416	/**
bogdanm	0:9b334a45a8ff	417	* @}
bogdanm	0:9b334a45a8ff	418	*/
bogdanm	0:9b334a45a8ff	419
bogdanm	0:9b334a45a8ff	420	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
bogdanm	0:9b334a45a8ff	421	* @{
bogdanm	0:9b334a45a8ff	422	*/
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	425	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	428	((POLARITY) == TIM_OCNPOLARITY_LOW))
bogdanm	0:9b334a45a8ff	429	/**
bogdanm	0:9b334a45a8ff	430	* @}
bogdanm	0:9b334a45a8ff	431	*/
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
bogdanm	0:9b334a45a8ff	434	* @{
bogdanm	0:9b334a45a8ff	435	*/
bogdanm	0:9b334a45a8ff	436
bogdanm	0:9b334a45a8ff	437	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
bogdanm	0:9b334a45a8ff	438	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	439	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
bogdanm	0:9b334a45a8ff	440	((STATE) == TIM_OCIDLESTATE_RESET))
bogdanm	0:9b334a45a8ff	441	/**
bogdanm	0:9b334a45a8ff	442	* @}
bogdanm	0:9b334a45a8ff	443	*/
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
bogdanm	0:9b334a45a8ff	446	* @{
bogdanm	0:9b334a45a8ff	447	*/
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
bogdanm	0:9b334a45a8ff	450	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	451	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
bogdanm	0:9b334a45a8ff	452	((STATE) == TIM_OCNIDLESTATE_RESET))
bogdanm	0:9b334a45a8ff	453	/**
bogdanm	0:9b334a45a8ff	454	* @}
bogdanm	0:9b334a45a8ff	455	*/
bogdanm	0:9b334a45a8ff	456
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
bogdanm	0:9b334a45a8ff	460	* @{
bogdanm	0:9b334a45a8ff	461	*/
bogdanm	0:9b334a45a8ff	462
bogdanm	0:9b334a45a8ff	463	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm	0:9b334a45a8ff	464	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm	0:9b334a45a8ff	465	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm	0:9b334a45a8ff	466
bogdanm	0:9b334a45a8ff	467	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	468	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	469	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm	0:9b334a45a8ff	470	/**
bogdanm	0:9b334a45a8ff	471	* @}
bogdanm	0:9b334a45a8ff	472	*/
bogdanm	0:9b334a45a8ff	473
bogdanm	0:9b334a45a8ff	474	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
bogdanm	0:9b334a45a8ff	475	* @{
bogdanm	0:9b334a45a8ff	476	*/
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	0:9b334a45a8ff	479	connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm	0:9b334a45a8ff	480	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	0:9b334a45a8ff	481	connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm	0:9b334a45a8ff	482	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
bogdanm	0:9b334a45a8ff	485	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
bogdanm	0:9b334a45a8ff	486	((SELECTION) == TIM_ICSELECTION_TRC))
bogdanm	0:9b334a45a8ff	487	/**
bogdanm	0:9b334a45a8ff	488	* @}
bogdanm	0:9b334a45a8ff	489	*/
bogdanm	0:9b334a45a8ff	490
bogdanm	0:9b334a45a8ff	491	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
bogdanm	0:9b334a45a8ff	492	* @{
bogdanm	0:9b334a45a8ff	493	*/
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
bogdanm	0:9b334a45a8ff	496	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
bogdanm	0:9b334a45a8ff	497	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
bogdanm	0:9b334a45a8ff	498	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
bogdanm	0:9b334a45a8ff	499
bogdanm	0:9b334a45a8ff	500	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	501	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	502	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	503	((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm	0:9b334a45a8ff	504	/**
bogdanm	0:9b334a45a8ff	505	* @}
bogdanm	0:9b334a45a8ff	506	*/
bogdanm	0:9b334a45a8ff	507
bogdanm	0:9b334a45a8ff	508	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
bogdanm	0:9b334a45a8ff	509	* @{
bogdanm	0:9b334a45a8ff	510	*/
bogdanm	0:9b334a45a8ff	511
bogdanm	0:9b334a45a8ff	512	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm	0:9b334a45a8ff	513	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	514	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
bogdanm	0:9b334a45a8ff	515	((MODE) == TIM_OPMODE_REPETITIVE))
bogdanm	0:9b334a45a8ff	516	/**
bogdanm	0:9b334a45a8ff	517	* @}
bogdanm	0:9b334a45a8ff	518	*/
bogdanm	0:9b334a45a8ff	519	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
bogdanm	0:9b334a45a8ff	520	* @{
bogdanm	0:9b334a45a8ff	521	*/
bogdanm	0:9b334a45a8ff	522	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm	0:9b334a45a8ff	523	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm	0:9b334a45a8ff	524	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
bogdanm	0:9b334a45a8ff	525	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
bogdanm	0:9b334a45a8ff	526	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
bogdanm	0:9b334a45a8ff	527	((MODE) == TIM_ENCODERMODE_TI12))
bogdanm	0:9b334a45a8ff	528	/**
bogdanm	0:9b334a45a8ff	529	* @}
bogdanm	0:9b334a45a8ff	530	*/
bogdanm	0:9b334a45a8ff	531	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
bogdanm	0:9b334a45a8ff	532	* @{
bogdanm	0:9b334a45a8ff	533	*/
bogdanm	0:9b334a45a8ff	534	#define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm	0:9b334a45a8ff	535	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm	0:9b334a45a8ff	536	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm	0:9b334a45a8ff	537	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm	0:9b334a45a8ff	538	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm	0:9b334a45a8ff	539	#define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm	0:9b334a45a8ff	540	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm	0:9b334a45a8ff	541	#define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543	#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
bogdanm	0:9b334a45a8ff	544
bogdanm	0:9b334a45a8ff	545	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	546	((IT) == TIM_IT_CC1) \|\| \
bogdanm	0:9b334a45a8ff	547	((IT) == TIM_IT_CC2) \|\| \
bogdanm	0:9b334a45a8ff	548	((IT) == TIM_IT_CC3) \|\| \
bogdanm	0:9b334a45a8ff	549	((IT) == TIM_IT_CC4) \|\| \
bogdanm	0:9b334a45a8ff	550	((IT) == TIM_IT_COM) \|\| \
bogdanm	0:9b334a45a8ff	551	((IT) == TIM_IT_TRIGGER) \|\| \
bogdanm	0:9b334a45a8ff	552	((IT) == TIM_IT_BREAK))
bogdanm	0:9b334a45a8ff	553	/**
bogdanm	0:9b334a45a8ff	554	* @}
bogdanm	0:9b334a45a8ff	555	*/
bogdanm	0:9b334a45a8ff	556	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
bogdanm	0:9b334a45a8ff	557	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	558
bogdanm	0:9b334a45a8ff	559	/** @defgroup TIM_DMA_sources TIM DMA Sources
bogdanm	0:9b334a45a8ff	560	* @{
bogdanm	0:9b334a45a8ff	561	*/
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm	0:9b334a45a8ff	564	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm	0:9b334a45a8ff	565	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm	0:9b334a45a8ff	566	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm	0:9b334a45a8ff	567	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm	0:9b334a45a8ff	568	#define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm	0:9b334a45a8ff	569	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm	0:9b334a45a8ff	570	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	/**
bogdanm	0:9b334a45a8ff	573	* @}
bogdanm	0:9b334a45a8ff	574	*/
bogdanm	0:9b334a45a8ff	575
bogdanm	0:9b334a45a8ff	576	/** @defgroup TIM_Flag_definition TIM Flag Definition
bogdanm	0:9b334a45a8ff	577	* @{
bogdanm	0:9b334a45a8ff	578	*/
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm	0:9b334a45a8ff	581	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm	0:9b334a45a8ff	582	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm	0:9b334a45a8ff	583	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm	0:9b334a45a8ff	584	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm	0:9b334a45a8ff	585	#define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm	0:9b334a45a8ff	586	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm	0:9b334a45a8ff	587	#define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm	0:9b334a45a8ff	588	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm	0:9b334a45a8ff	589	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm	0:9b334a45a8ff	590	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm	0:9b334a45a8ff	591	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm	0:9b334a45a8ff	592
bogdanm	0:9b334a45a8ff	593	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	594	((FLAG) == TIM_FLAG_CC1) \|\| \
bogdanm	0:9b334a45a8ff	595	((FLAG) == TIM_FLAG_CC2) \|\| \
bogdanm	0:9b334a45a8ff	596	((FLAG) == TIM_FLAG_CC3) \|\| \
bogdanm	0:9b334a45a8ff	597	((FLAG) == TIM_FLAG_CC4) \|\| \
bogdanm	0:9b334a45a8ff	598	((FLAG) == TIM_FLAG_COM) \|\| \
bogdanm	0:9b334a45a8ff	599	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
bogdanm	0:9b334a45a8ff	600	((FLAG) == TIM_FLAG_BREAK) \|\| \
bogdanm	0:9b334a45a8ff	601	((FLAG) == TIM_FLAG_CC1OF) \|\| \
bogdanm	0:9b334a45a8ff	602	((FLAG) == TIM_FLAG_CC2OF) \|\| \
bogdanm	0:9b334a45a8ff	603	((FLAG) == TIM_FLAG_CC3OF) \|\| \
bogdanm	0:9b334a45a8ff	604	((FLAG) == TIM_FLAG_CC4OF))
bogdanm	0:9b334a45a8ff	605	/**
bogdanm	0:9b334a45a8ff	606	* @}
bogdanm	0:9b334a45a8ff	607	*/
bogdanm	0:9b334a45a8ff	608
bogdanm	0:9b334a45a8ff	609	/** @defgroup TIM_Clock_Source TIM Clock Source
bogdanm	0:9b334a45a8ff	610	* @{
bogdanm	0:9b334a45a8ff	611	*/
bogdanm	0:9b334a45a8ff	612	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm	0:9b334a45a8ff	613	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm	0:9b334a45a8ff	614	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	615	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm	0:9b334a45a8ff	616	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm	0:9b334a45a8ff	617	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
bogdanm	0:9b334a45a8ff	618	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	619	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	620	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	621	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm	0:9b334a45a8ff	622
bogdanm	0:9b334a45a8ff	623	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
bogdanm	0:9b334a45a8ff	624	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
bogdanm	0:9b334a45a8ff	625	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	626	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	627	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	628	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	629	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
bogdanm	0:9b334a45a8ff	630	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
bogdanm	0:9b334a45a8ff	631	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
bogdanm	0:9b334a45a8ff	632	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm	0:9b334a45a8ff	633	/**
bogdanm	0:9b334a45a8ff	634	* @}
bogdanm	0:9b334a45a8ff	635	*/
bogdanm	0:9b334a45a8ff	636
bogdanm	0:9b334a45a8ff	637	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
bogdanm	0:9b334a45a8ff	638	* @{
bogdanm	0:9b334a45a8ff	639	*/
bogdanm	0:9b334a45a8ff	640	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
bogdanm	0:9b334a45a8ff	641	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
bogdanm	0:9b334a45a8ff	642	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	643	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	644	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	645
bogdanm	0:9b334a45a8ff	646	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
bogdanm	0:9b334a45a8ff	647	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
bogdanm	0:9b334a45a8ff	648	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	649	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	650	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm	0:9b334a45a8ff	651	/**
bogdanm	0:9b334a45a8ff	652	* @}
bogdanm	0:9b334a45a8ff	653	*/
bogdanm	0:9b334a45a8ff	654	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
bogdanm	0:9b334a45a8ff	655	* @{
bogdanm	0:9b334a45a8ff	656	*/
bogdanm	0:9b334a45a8ff	657	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	658	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	659	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	660	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	661
bogdanm	0:9b334a45a8ff	662	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	663	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	664	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	665	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	666	/**
bogdanm	0:9b334a45a8ff	667	* @}
bogdanm	0:9b334a45a8ff	668	*/
bogdanm	0:9b334a45a8ff	669	/** @defgroup TIM_Clock_Filter TIM Clock Filter
bogdanm	0:9b334a45a8ff	670	* @{
bogdanm	0:9b334a45a8ff	671	*/
bogdanm	0:9b334a45a8ff	672
bogdanm	0:9b334a45a8ff	673	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	674	/**
bogdanm	0:9b334a45a8ff	675	* @}
bogdanm	0:9b334a45a8ff	676	*/
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
bogdanm	0:9b334a45a8ff	679	* @{
bogdanm	0:9b334a45a8ff	680	*/
bogdanm	0:9b334a45a8ff	681	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
bogdanm	0:9b334a45a8ff	682	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
bogdanm	0:9b334a45a8ff	683
bogdanm	0:9b334a45a8ff	684
bogdanm	0:9b334a45a8ff	685	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
bogdanm	0:9b334a45a8ff	686	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm	0:9b334a45a8ff	687	/**
bogdanm	0:9b334a45a8ff	688	* @}
bogdanm	0:9b334a45a8ff	689	*/
bogdanm	0:9b334a45a8ff	690
bogdanm	0:9b334a45a8ff	691	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
bogdanm	0:9b334a45a8ff	692	* @{
bogdanm	0:9b334a45a8ff	693	*/
bogdanm	0:9b334a45a8ff	694	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	695	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	696	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	697	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	698	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	699	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	700	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	701	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	702	/**
bogdanm	0:9b334a45a8ff	703	* @}
bogdanm	0:9b334a45a8ff	704	*/
bogdanm	0:9b334a45a8ff	705
bogdanm	0:9b334a45a8ff	706	/** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter
bogdanm	0:9b334a45a8ff	707	* @{
bogdanm	0:9b334a45a8ff	708	*/
bogdanm	0:9b334a45a8ff	709
bogdanm	0:9b334a45a8ff	710	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	711	/**
bogdanm	0:9b334a45a8ff	712	* @}
bogdanm	0:9b334a45a8ff	713	*/
bogdanm	0:9b334a45a8ff	714
bogdanm	0:9b334a45a8ff	715	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
bogdanm	0:9b334a45a8ff	716	* @{
bogdanm	0:9b334a45a8ff	717	*/
bogdanm	0:9b334a45a8ff	718	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
bogdanm	0:9b334a45a8ff	719	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	720
bogdanm	0:9b334a45a8ff	721	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	722	((STATE) == TIM_OSSR_DISABLE))
bogdanm	0:9b334a45a8ff	723	/**
bogdanm	0:9b334a45a8ff	724	* @}
bogdanm	0:9b334a45a8ff	725	*/
bogdanm	0:9b334a45a8ff	726
bogdanm	0:9b334a45a8ff	727	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
bogdanm	0:9b334a45a8ff	728	* @{
bogdanm	0:9b334a45a8ff	729	*/
bogdanm	0:9b334a45a8ff	730	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm	0:9b334a45a8ff	731	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	732
bogdanm	0:9b334a45a8ff	733	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	734	((STATE) == TIM_OSSI_DISABLE))
bogdanm	0:9b334a45a8ff	735	/**
bogdanm	0:9b334a45a8ff	736	* @}
bogdanm	0:9b334a45a8ff	737	*/
bogdanm	0:9b334a45a8ff	738	/** @defgroup TIM_Lock_level TIM Lock Configuration
bogdanm	0:9b334a45a8ff	739	* @{
bogdanm	0:9b334a45a8ff	740	*/
bogdanm	0:9b334a45a8ff	741	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	742	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm	0:9b334a45a8ff	743	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm	0:9b334a45a8ff	744	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
bogdanm	0:9b334a45a8ff	747	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
bogdanm	0:9b334a45a8ff	748	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
bogdanm	0:9b334a45a8ff	749	((LEVEL) == TIM_LOCKLEVEL_3))
bogdanm	0:9b334a45a8ff	750	/**
bogdanm	0:9b334a45a8ff	751	* @}
bogdanm	0:9b334a45a8ff	752	*/
bogdanm	0:9b334a45a8ff	753	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
bogdanm	0:9b334a45a8ff	754	* @{
bogdanm	0:9b334a45a8ff	755	*/
bogdanm	0:9b334a45a8ff	756	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
bogdanm	0:9b334a45a8ff	757	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	758
bogdanm	0:9b334a45a8ff	759	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	760	((STATE) == TIM_BREAK_DISABLE))
bogdanm	0:9b334a45a8ff	761	/**
bogdanm	0:9b334a45a8ff	762	* @}
bogdanm	0:9b334a45a8ff	763	*/
bogdanm	0:9b334a45a8ff	764	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
bogdanm	0:9b334a45a8ff	765	* @{
bogdanm	0:9b334a45a8ff	766	*/
bogdanm	0:9b334a45a8ff	767	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	768	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
bogdanm	0:9b334a45a8ff	771	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
bogdanm	0:9b334a45a8ff	772	/**
bogdanm	0:9b334a45a8ff	773	* @}
bogdanm	0:9b334a45a8ff	774	*/
bogdanm	0:9b334a45a8ff	775	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
bogdanm	0:9b334a45a8ff	776	* @{
bogdanm	0:9b334a45a8ff	777	*/
bogdanm	0:9b334a45a8ff	778	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm	0:9b334a45a8ff	779	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	780
bogdanm	0:9b334a45a8ff	781	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	782	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
bogdanm	0:9b334a45a8ff	783	/**
bogdanm	0:9b334a45a8ff	784	* @}
bogdanm	0:9b334a45a8ff	785	*/
bogdanm	0:9b334a45a8ff	786
bogdanm	0:9b334a45a8ff	787	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
bogdanm	0:9b334a45a8ff	788	* @{
bogdanm	0:9b334a45a8ff	789	*/
bogdanm	0:9b334a45a8ff	790	#define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	791	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm	0:9b334a45a8ff	792	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm	0:9b334a45a8ff	793	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	794	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm	0:9b334a45a8ff	795	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	796	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
bogdanm	0:9b334a45a8ff	797	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	798
bogdanm	0:9b334a45a8ff	799	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
bogdanm	0:9b334a45a8ff	800	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	801	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	802	((SOURCE) == TIM_TRGO_OC1) \|\| \
bogdanm	0:9b334a45a8ff	803	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
bogdanm	0:9b334a45a8ff	804	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
bogdanm	0:9b334a45a8ff	805	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
bogdanm	0:9b334a45a8ff	806	((SOURCE) == TIM_TRGO_OC4REF))
bogdanm	0:9b334a45a8ff	807
bogdanm	0:9b334a45a8ff	808
bogdanm	0:9b334a45a8ff	809	/**
bogdanm	0:9b334a45a8ff	810	* @}
bogdanm	0:9b334a45a8ff	811	*/
bogdanm	0:9b334a45a8ff	812	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
bogdanm	0:9b334a45a8ff	813	* @{
bogdanm	0:9b334a45a8ff	814	*/
bogdanm	0:9b334a45a8ff	815
bogdanm	0:9b334a45a8ff	816	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm	0:9b334a45a8ff	817	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	818	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	819	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm	0:9b334a45a8ff	820	/**
bogdanm	0:9b334a45a8ff	821	* @}
bogdanm	0:9b334a45a8ff	822	*/
bogdanm	0:9b334a45a8ff	823	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
bogdanm	0:9b334a45a8ff	824	* @{
bogdanm	0:9b334a45a8ff	825	*/
bogdanm	0:9b334a45a8ff	826
bogdanm	0:9b334a45a8ff	827	#define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	828	#define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm	0:9b334a45a8ff	829	#define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm	0:9b334a45a8ff	830	#define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm	0:9b334a45a8ff	831	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm	0:9b334a45a8ff	832	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm	0:9b334a45a8ff	833	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm	0:9b334a45a8ff	834	#define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm	0:9b334a45a8ff	835	#define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm	0:9b334a45a8ff	836	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	837	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	838	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	839	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	840	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
bogdanm	0:9b334a45a8ff	841	((SELECTION) == TIM_TS_TI1FP1) \|\| \
bogdanm	0:9b334a45a8ff	842	((SELECTION) == TIM_TS_TI2FP2) \|\| \
bogdanm	0:9b334a45a8ff	843	((SELECTION) == TIM_TS_ETRF))
bogdanm	0:9b334a45a8ff	844	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	845	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	846	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	847	((SELECTION) == TIM_TS_ITR3))
bogdanm	0:9b334a45a8ff	848	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	849	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	850	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	851	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	852	((SELECTION) == TIM_TS_NONE))
bogdanm	0:9b334a45a8ff	853	/**
bogdanm	0:9b334a45a8ff	854	* @}
bogdanm	0:9b334a45a8ff	855	*/
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
bogdanm	0:9b334a45a8ff	858	* @{
bogdanm	0:9b334a45a8ff	859	*/
bogdanm	0:9b334a45a8ff	860	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
bogdanm	0:9b334a45a8ff	861	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
bogdanm	0:9b334a45a8ff	862	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	863	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	864	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	865
bogdanm	0:9b334a45a8ff	866	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
bogdanm	0:9b334a45a8ff	867	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
bogdanm	0:9b334a45a8ff	868	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
bogdanm	0:9b334a45a8ff	869	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
bogdanm	0:9b334a45a8ff	870	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm	0:9b334a45a8ff	871	/**
bogdanm	0:9b334a45a8ff	872	* @}
bogdanm	0:9b334a45a8ff	873	*/
bogdanm	0:9b334a45a8ff	874
bogdanm	0:9b334a45a8ff	875	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
bogdanm	0:9b334a45a8ff	876	* @{
bogdanm	0:9b334a45a8ff	877	*/
bogdanm	0:9b334a45a8ff	878	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	879	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	880	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	881	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	882
bogdanm	0:9b334a45a8ff	883	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	884	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	885	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	886	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	887	/**
bogdanm	0:9b334a45a8ff	888	* @}
bogdanm	0:9b334a45a8ff	889	*/
bogdanm	0:9b334a45a8ff	890
bogdanm	0:9b334a45a8ff	891	/** @defgroup TIM_Trigger_Filter TIM Trigger Filter
bogdanm	0:9b334a45a8ff	892	* @{
bogdanm	0:9b334a45a8ff	893	*/
bogdanm	0:9b334a45a8ff	894
bogdanm	0:9b334a45a8ff	895	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	896	/**
bogdanm	0:9b334a45a8ff	897	* @}
bogdanm	0:9b334a45a8ff	898	*/
bogdanm	0:9b334a45a8ff	899
bogdanm	0:9b334a45a8ff	900	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
bogdanm	0:9b334a45a8ff	901	* @{
bogdanm	0:9b334a45a8ff	902	*/
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	905	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm	0:9b334a45a8ff	906
bogdanm	0:9b334a45a8ff	907	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
bogdanm	0:9b334a45a8ff	908	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	/**
bogdanm	0:9b334a45a8ff	911	* @}
bogdanm	0:9b334a45a8ff	912	*/
bogdanm	0:9b334a45a8ff	913
bogdanm	0:9b334a45a8ff	914	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
bogdanm	0:9b334a45a8ff	915	* @{
bogdanm	0:9b334a45a8ff	916	*/
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	#define TIM_DMABurstLength_1Transfer (0x00000000)
bogdanm	0:9b334a45a8ff	919	#define TIM_DMABurstLength_2Transfers (0x00000100)
bogdanm	0:9b334a45a8ff	920	#define TIM_DMABurstLength_3Transfers (0x00000200)
bogdanm	0:9b334a45a8ff	921	#define TIM_DMABurstLength_4Transfers (0x00000300)
bogdanm	0:9b334a45a8ff	922	#define TIM_DMABurstLength_5Transfers (0x00000400)
bogdanm	0:9b334a45a8ff	923	#define TIM_DMABurstLength_6Transfers (0x00000500)
bogdanm	0:9b334a45a8ff	924	#define TIM_DMABurstLength_7Transfers (0x00000600)
bogdanm	0:9b334a45a8ff	925	#define TIM_DMABurstLength_8Transfers (0x00000700)
bogdanm	0:9b334a45a8ff	926	#define TIM_DMABurstLength_9Transfers (0x00000800)
bogdanm	0:9b334a45a8ff	927	#define TIM_DMABurstLength_10Transfers (0x00000900)
bogdanm	0:9b334a45a8ff	928	#define TIM_DMABurstLength_11Transfers (0x00000A00)
bogdanm	0:9b334a45a8ff	929	#define TIM_DMABurstLength_12Transfers (0x00000B00)
bogdanm	0:9b334a45a8ff	930	#define TIM_DMABurstLength_13Transfers (0x00000C00)
bogdanm	0:9b334a45a8ff	931	#define TIM_DMABurstLength_14Transfers (0x00000D00)
bogdanm	0:9b334a45a8ff	932	#define TIM_DMABurstLength_15Transfers (0x00000E00)
bogdanm	0:9b334a45a8ff	933	#define TIM_DMABurstLength_16Transfers (0x00000F00)
bogdanm	0:9b334a45a8ff	934	#define TIM_DMABurstLength_17Transfers (0x00001000)
bogdanm	0:9b334a45a8ff	935	#define TIM_DMABurstLength_18Transfers (0x00001100)
bogdanm	0:9b334a45a8ff	936	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
bogdanm	0:9b334a45a8ff	937	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
bogdanm	0:9b334a45a8ff	938	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
bogdanm	0:9b334a45a8ff	939	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
bogdanm	0:9b334a45a8ff	940	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
bogdanm	0:9b334a45a8ff	941	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
bogdanm	0:9b334a45a8ff	942	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
bogdanm	0:9b334a45a8ff	943	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
bogdanm	0:9b334a45a8ff	944	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
bogdanm	0:9b334a45a8ff	945	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
bogdanm	0:9b334a45a8ff	946	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
bogdanm	0:9b334a45a8ff	947	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
bogdanm	0:9b334a45a8ff	948	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
bogdanm	0:9b334a45a8ff	949	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
bogdanm	0:9b334a45a8ff	950	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
bogdanm	0:9b334a45a8ff	951	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
bogdanm	0:9b334a45a8ff	952	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
bogdanm	0:9b334a45a8ff	953	((LENGTH) == TIM_DMABurstLength_18Transfers))
bogdanm	0:9b334a45a8ff	954	/**
bogdanm	0:9b334a45a8ff	955	* @}
bogdanm	0:9b334a45a8ff	956	*/
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958	/** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value
bogdanm	0:9b334a45a8ff	959	* @{
bogdanm	0:9b334a45a8ff	960	*/
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	963	/**
bogdanm	0:9b334a45a8ff	964	* @}
bogdanm	0:9b334a45a8ff	965	*/
bogdanm	0:9b334a45a8ff	966
bogdanm	0:9b334a45a8ff	967	/** @defgroup DMA_Handle_index TIM DMA Handle Index
bogdanm	0:9b334a45a8ff	968	* @{
bogdanm	0:9b334a45a8ff	969	*/
bogdanm	0:9b334a45a8ff	970	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
bogdanm	0:9b334a45a8ff	971	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
bogdanm	0:9b334a45a8ff	972	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
bogdanm	0:9b334a45a8ff	973	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
bogdanm	0:9b334a45a8ff	974	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
bogdanm	0:9b334a45a8ff	975	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
bogdanm	0:9b334a45a8ff	976	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
bogdanm	0:9b334a45a8ff	977	/**
bogdanm	0:9b334a45a8ff	978	* @}
bogdanm	0:9b334a45a8ff	979	*/
bogdanm	0:9b334a45a8ff	980
bogdanm	0:9b334a45a8ff	981	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
bogdanm	0:9b334a45a8ff	982	* @{
bogdanm	0:9b334a45a8ff	983	*/
bogdanm	0:9b334a45a8ff	984	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	985	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	986	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	987	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	988	/**
bogdanm	0:9b334a45a8ff	989	* @}
bogdanm	0:9b334a45a8ff	990	*/
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992	/**
bogdanm	0:9b334a45a8ff	993	* @}
bogdanm	0:9b334a45a8ff	994	*/
bogdanm	0:9b334a45a8ff	995
bogdanm	0:9b334a45a8ff	996	/* Exported macros -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	997	/** @defgroup TIM_Exported_Macros TIM Exported Macros
bogdanm	0:9b334a45a8ff	998	* @{
bogdanm	0:9b334a45a8ff	999	*/
bogdanm	0:9b334a45a8ff	1000
bogdanm	0:9b334a45a8ff	1001	/** @brief Reset TIM handle state
bogdanm	0:9b334a45a8ff	1002	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1003	* @retval None
bogdanm	0:9b334a45a8ff	1004	*/
bogdanm	0:9b334a45a8ff	1005	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1006
bogdanm	0:9b334a45a8ff	1007	/**
bogdanm	0:9b334a45a8ff	1008	* @brief Enable the TIM peripheral.
bogdanm	0:9b334a45a8ff	1009	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1010	* @retval None
bogdanm	0:9b334a45a8ff	1011	*/
bogdanm	0:9b334a45a8ff	1012	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	/**
bogdanm	0:9b334a45a8ff	1015	* @brief Enable the TIM main Output.
bogdanm	0:9b334a45a8ff	1016	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1017	* @retval None
bogdanm	0:9b334a45a8ff	1018	*/
bogdanm	0:9b334a45a8ff	1019	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
bogdanm	0:9b334a45a8ff	1020
bogdanm	0:9b334a45a8ff	1021	/* The counter of a timer instance is disabled only if all the CCx and CCxN
bogdanm	0:9b334a45a8ff	1022	channels have been disabled */
bogdanm	0:9b334a45a8ff	1023	#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
bogdanm	0:9b334a45a8ff	1024	#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/**
bogdanm	0:9b334a45a8ff	1027	* @brief Disable the TIM peripheral.
bogdanm	0:9b334a45a8ff	1028	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1029	* @retval None
bogdanm	0:9b334a45a8ff	1030	*/
bogdanm	0:9b334a45a8ff	1031	#define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1032	do { \
bogdanm	0:9b334a45a8ff	1033	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1034	{ \
bogdanm	0:9b334a45a8ff	1035	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1036	{ \
bogdanm	0:9b334a45a8ff	1037	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm	0:9b334a45a8ff	1038	} \
bogdanm	0:9b334a45a8ff	1039	} \
bogdanm	0:9b334a45a8ff	1040	} while(0)
bogdanm	0:9b334a45a8ff	1041	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
bogdanm	0:9b334a45a8ff	1042	channels have been disabled */
bogdanm	0:9b334a45a8ff	1043	/**
bogdanm	0:9b334a45a8ff	1044	* @brief Disable the TIM main Output.
bogdanm	0:9b334a45a8ff	1045	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1046	* @retval None
bogdanm	0:9b334a45a8ff	1047	*/
bogdanm	0:9b334a45a8ff	1048	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1049	do { \
bogdanm	0:9b334a45a8ff	1050	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1051	{ \
bogdanm	0:9b334a45a8ff	1052	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1053	{ \
bogdanm	0:9b334a45a8ff	1054	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
bogdanm	0:9b334a45a8ff	1055	} \
bogdanm	0:9b334a45a8ff	1056	} \
bogdanm	0:9b334a45a8ff	1057	} while(0)
bogdanm	0:9b334a45a8ff	1058
bogdanm	0:9b334a45a8ff	1059	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1060	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
bogdanm	0:9b334a45a8ff	1061	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1062	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm	0:9b334a45a8ff	1063	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	1064	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm	0:9b334a45a8ff	1065
bogdanm	0:9b334a45a8ff	1066	#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	0:9b334a45a8ff	1067	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1068
bogdanm	0:9b334a45a8ff	1069	#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm	0:9b334a45a8ff	1070	#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm	0:9b334a45a8ff	1071
bogdanm	0:9b334a45a8ff	1072	#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	0:9b334a45a8ff	1073	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
bogdanm	0:9b334a45a8ff	1074	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
bogdanm	0:9b334a45a8ff	1075	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
bogdanm	0:9b334a45a8ff	1076	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
bogdanm	0:9b334a45a8ff	1077
bogdanm	0:9b334a45a8ff	1078	#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1079	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm	0:9b334a45a8ff	1080	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm	0:9b334a45a8ff	1081	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm	0:9b334a45a8ff	1082	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm	0:9b334a45a8ff	1083
bogdanm	0:9b334a45a8ff	1084	/**
bogdanm	0:9b334a45a8ff	1085	* @brief Sets the TIM Counter Register value on runtime.
bogdanm	0:9b334a45a8ff	1086	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1087	* @param __COUNTER__: specifies the Counter register new value.
bogdanm	0:9b334a45a8ff	1088	* @retval None
bogdanm	0:9b334a45a8ff	1089	*/
bogdanm	0:9b334a45a8ff	1090	#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm	0:9b334a45a8ff	1091
bogdanm	0:9b334a45a8ff	1092	/**
bogdanm	0:9b334a45a8ff	1093	* @brief Gets the TIM Counter Register value on runtime.
bogdanm	0:9b334a45a8ff	1094	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1095	* @retval None
bogdanm	0:9b334a45a8ff	1096	*/
bogdanm	0:9b334a45a8ff	1097	#define __HAL_TIM_GetCounter(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1098	((__HANDLE__)->Instance->CNT)
bogdanm	0:9b334a45a8ff	1099
bogdanm	0:9b334a45a8ff	1100	/**
bogdanm	0:9b334a45a8ff	1101	* @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm	0:9b334a45a8ff	1102	* another time any Init function.
bogdanm	0:9b334a45a8ff	1103	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1104	* @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm	0:9b334a45a8ff	1105	* @retval None
bogdanm	0:9b334a45a8ff	1106	*/
bogdanm	0:9b334a45a8ff	1107	#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
bogdanm	0:9b334a45a8ff	1108	do{ \
bogdanm	0:9b334a45a8ff	1109	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm	0:9b334a45a8ff	1110	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm	0:9b334a45a8ff	1111	} while(0)
bogdanm	0:9b334a45a8ff	1112
bogdanm	0:9b334a45a8ff	1113	/**
bogdanm	0:9b334a45a8ff	1114	* @brief Gets the TIM Autoreload Register value on runtime
bogdanm	0:9b334a45a8ff	1115	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1116	* @retval None
bogdanm	0:9b334a45a8ff	1117	*/
bogdanm	0:9b334a45a8ff	1118	#define __HAL_TIM_GetAutoreload(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1119	((__HANDLE__)->Instance->ARR)
bogdanm	0:9b334a45a8ff	1120
bogdanm	0:9b334a45a8ff	1121	/**
bogdanm	0:9b334a45a8ff	1122	* @brief Sets the TIM Clock Division value on runtime without calling
bogdanm	0:9b334a45a8ff	1123	* another time any Init function.
bogdanm	0:9b334a45a8ff	1124	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1125	* @param __CKD__: specifies the clock division value.
bogdanm	0:9b334a45a8ff	1126	* This parameter can be one of the following value:
bogdanm	0:9b334a45a8ff	1127	* @arg TIM_CLOCKDIVISION_DIV1
bogdanm	0:9b334a45a8ff	1128	* @arg TIM_CLOCKDIVISION_DIV2
bogdanm	0:9b334a45a8ff	1129	* @arg TIM_CLOCKDIVISION_DIV4
bogdanm	0:9b334a45a8ff	1130	* @retval None
bogdanm	0:9b334a45a8ff	1131	*/
bogdanm	0:9b334a45a8ff	1132	#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
bogdanm	0:9b334a45a8ff	1133	do{ \
bogdanm	0:9b334a45a8ff	1134	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm	0:9b334a45a8ff	1135	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
bogdanm	0:9b334a45a8ff	1136	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm	0:9b334a45a8ff	1137	} while(0)
bogdanm	0:9b334a45a8ff	1138
bogdanm	0:9b334a45a8ff	1139	/**
bogdanm	0:9b334a45a8ff	1140	* @brief Gets the TIM Clock Division value on runtime
bogdanm	0:9b334a45a8ff	1141	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1142	* @retval None
bogdanm	0:9b334a45a8ff	1143	*/
bogdanm	0:9b334a45a8ff	1144	#define __HAL_TIM_GetClockDivision(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1145	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm	0:9b334a45a8ff	1146
bogdanm	0:9b334a45a8ff	1147	/**
bogdanm	0:9b334a45a8ff	1148	* @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm	0:9b334a45a8ff	1149	* another time HAL_TIM_IC_ConfigChannel() function.
bogdanm	0:9b334a45a8ff	1150	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1151	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1152	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1153	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1154	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1155	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1156	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1157	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm	0:9b334a45a8ff	1158	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1159	* @arg TIM_ICPSC_DIV1: no prescaler
bogdanm	0:9b334a45a8ff	1160	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm	0:9b334a45a8ff	1161	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm	0:9b334a45a8ff	1162	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm	0:9b334a45a8ff	1163	* @retval None
bogdanm	0:9b334a45a8ff	1164	*/
bogdanm	0:9b334a45a8ff	1165	#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	0:9b334a45a8ff	1166	do{ \
bogdanm	0:9b334a45a8ff	1167	__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
bogdanm	0:9b334a45a8ff	1168	__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm	0:9b334a45a8ff	1169	} while(0)
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	/**
bogdanm	0:9b334a45a8ff	1172	* @brief Gets the TIM Input Capture prescaler on runtime
bogdanm	0:9b334a45a8ff	1173	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1174	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1175	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1176	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm	0:9b334a45a8ff	1177	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm	0:9b334a45a8ff	1178	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm	0:9b334a45a8ff	1179	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm	0:9b334a45a8ff	1180	* @retval None
bogdanm	0:9b334a45a8ff	1181	*/
bogdanm	0:9b334a45a8ff	1182	#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1183	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm	0:9b334a45a8ff	1184	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm	0:9b334a45a8ff	1185	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm	0:9b334a45a8ff	1186	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm	0:9b334a45a8ff	1187
bogdanm	0:9b334a45a8ff	1188	/**
bogdanm	0:9b334a45a8ff	1189	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	0:9b334a45a8ff	1190	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1191	* @note When the USR bit of the TIMx_CR1 register is set, only counter
bogdanm	0:9b334a45a8ff	1192	* overflow/underflow generates an update interrupt or DMA request (if
bogdanm	0:9b334a45a8ff	1193	* enabled)
bogdanm	0:9b334a45a8ff	1194	* @retval None
bogdanm	0:9b334a45a8ff	1195	*/
bogdanm	0:9b334a45a8ff	1196	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1197	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
bogdanm	0:9b334a45a8ff	1198
bogdanm	0:9b334a45a8ff	1199	/**
bogdanm	0:9b334a45a8ff	1200	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	0:9b334a45a8ff	1201	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1202	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
bogdanm	0:9b334a45a8ff	1203	* following events generate an update interrupt or DMA request (if
bogdanm	0:9b334a45a8ff	1204	* enabled):
bogdanm	0:9b334a45a8ff	1205	* Counter overflow/underflow
bogdanm	0:9b334a45a8ff	1206	* Setting the UG bit
bogdanm	0:9b334a45a8ff	1207	* Update generation through the slave mode controller
bogdanm	0:9b334a45a8ff	1208	* @retval None
bogdanm	0:9b334a45a8ff	1209	*/
bogdanm	0:9b334a45a8ff	1210	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1211	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	/**
bogdanm	0:9b334a45a8ff	1214	* @}
bogdanm	0:9b334a45a8ff	1215	*/
bogdanm	0:9b334a45a8ff	1216
bogdanm	0:9b334a45a8ff	1217	/* Include TIM HAL Extended module */
bogdanm	0:9b334a45a8ff	1218	#include "stm32f3xx_hal_tim_ex.h"
bogdanm	0:9b334a45a8ff	1219
bogdanm	0:9b334a45a8ff	1220	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1221	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
bogdanm	0:9b334a45a8ff	1222	* @{
bogdanm	0:9b334a45a8ff	1223	*/
bogdanm	0:9b334a45a8ff	1224
bogdanm	0:9b334a45a8ff	1225	/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
bogdanm	0:9b334a45a8ff	1226	* @brief Time Base functions
bogdanm	0:9b334a45a8ff	1227	* @{
bogdanm	0:9b334a45a8ff	1228	*/
bogdanm	0:9b334a45a8ff	1229	/* Time Base functions ********************************************************/
bogdanm	0:9b334a45a8ff	1230	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1231	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1232	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1233	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1234	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1235	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1236	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1237	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1238	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1239	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1240	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1241	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1242	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1243	/**
bogdanm	0:9b334a45a8ff	1244	* @}
bogdanm	0:9b334a45a8ff	1245	*/
bogdanm	0:9b334a45a8ff	1246
bogdanm	0:9b334a45a8ff	1247	/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
bogdanm	0:9b334a45a8ff	1248	* @brief Time Output Compare functions
bogdanm	0:9b334a45a8ff	1249	* @{
bogdanm	0:9b334a45a8ff	1250	*/
bogdanm	0:9b334a45a8ff	1251	/* Timer Output Compare functions **********************************************/
bogdanm	0:9b334a45a8ff	1252	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1253	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1254	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1255	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1256	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1257	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1258	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1259	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1260	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1261	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1262	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1263	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1264	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1265	/**
bogdanm	0:9b334a45a8ff	1266	* @}
bogdanm	0:9b334a45a8ff	1267	*/
bogdanm	0:9b334a45a8ff	1268
bogdanm	0:9b334a45a8ff	1269	/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
bogdanm	0:9b334a45a8ff	1270	* @brief Time PWM functions
bogdanm	0:9b334a45a8ff	1271	* @{
bogdanm	0:9b334a45a8ff	1272	*/
bogdanm	0:9b334a45a8ff	1273	/* Timer PWM functions *********************************************************/
bogdanm	0:9b334a45a8ff	1274	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1275	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1276	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1277	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1278	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1279	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1280	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1281	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1282	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1283	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1284	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1285	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1286	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1287	/**
bogdanm	0:9b334a45a8ff	1288	* @}
bogdanm	0:9b334a45a8ff	1289	*/
bogdanm	0:9b334a45a8ff	1290
bogdanm	0:9b334a45a8ff	1291	/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
bogdanm	0:9b334a45a8ff	1292	* @brief Time Input Capture functions
bogdanm	0:9b334a45a8ff	1293	* @{
bogdanm	0:9b334a45a8ff	1294	*/
bogdanm	0:9b334a45a8ff	1295	/* Timer Input Capture functions ***********************************************/
bogdanm	0:9b334a45a8ff	1296	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1297	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1298	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1299	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1300	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1301	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1302	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1303	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1304	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1305	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1306	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1307	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1308	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1309	/**
bogdanm	0:9b334a45a8ff	1310	* @}
bogdanm	0:9b334a45a8ff	1311	*/
bogdanm	0:9b334a45a8ff	1312
bogdanm	0:9b334a45a8ff	1313	/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
bogdanm	0:9b334a45a8ff	1314	* @brief Time One Pulse functions
bogdanm	0:9b334a45a8ff	1315	* @{
bogdanm	0:9b334a45a8ff	1316	*/
bogdanm	0:9b334a45a8ff	1317	/* Timer One Pulse functions ***************************************************/
bogdanm	0:9b334a45a8ff	1318	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm	0:9b334a45a8ff	1319	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1320	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1321	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1322	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1323	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1324	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1325	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1326	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1327	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1328	/**
bogdanm	0:9b334a45a8ff	1329	* @}
bogdanm	0:9b334a45a8ff	1330	*/
bogdanm	0:9b334a45a8ff	1331
bogdanm	0:9b334a45a8ff	1332	/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
bogdanm	0:9b334a45a8ff	1333	* @brief Time Encoder functions
bogdanm	0:9b334a45a8ff	1334	* @{
bogdanm	0:9b334a45a8ff	1335	*/
bogdanm	0:9b334a45a8ff	1336	/* Timer Encoder functions *****************************************************/
bogdanm	0:9b334a45a8ff	1337	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
bogdanm	0:9b334a45a8ff	1338	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1339	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1340	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1341	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1342	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1343	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1344	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1345	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1346	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1347	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1348	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
bogdanm	0:9b334a45a8ff	1349	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1350	/**
bogdanm	0:9b334a45a8ff	1351	* @}
bogdanm	0:9b334a45a8ff	1352	*/
bogdanm	0:9b334a45a8ff	1353
bogdanm	0:9b334a45a8ff	1354	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
bogdanm	0:9b334a45a8ff	1355	* @brief IRQ handler management
bogdanm	0:9b334a45a8ff	1356	* @{
bogdanm	0:9b334a45a8ff	1357	*/
bogdanm	0:9b334a45a8ff	1358	/* Interrupt Handler functions **********************************************/
bogdanm	0:9b334a45a8ff	1359	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1360	/**
bogdanm	0:9b334a45a8ff	1361	* @}
bogdanm	0:9b334a45a8ff	1362	*/
bogdanm	0:9b334a45a8ff	1363
bogdanm	0:9b334a45a8ff	1364	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1365	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	1366	* @{
bogdanm	0:9b334a45a8ff	1367	*/
bogdanm	0:9b334a45a8ff	1368	/* Control functions *********************************************************/
bogdanm	0:9b334a45a8ff	1369	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1370	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1371	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1372	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm	0:9b334a45a8ff	1373	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1374	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
bogdanm	0:9b334a45a8ff	1375	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm	0:9b334a45a8ff	1376	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	0:9b334a45a8ff	1377	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	0:9b334a45a8ff	1378	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	0:9b334a45a8ff	1379	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	0:9b334a45a8ff	1380	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	0:9b334a45a8ff	1381	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	0:9b334a45a8ff	1382	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	0:9b334a45a8ff	1383	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm	0:9b334a45a8ff	1384	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1385	/**
bogdanm	0:9b334a45a8ff	1386	* @}
bogdanm	0:9b334a45a8ff	1387	*/
bogdanm	0:9b334a45a8ff	1388
bogdanm	0:9b334a45a8ff	1389	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
bogdanm	0:9b334a45a8ff	1390	* @brief TIM Callbacks functions
bogdanm	0:9b334a45a8ff	1391	* @{
bogdanm	0:9b334a45a8ff	1392	*/
bogdanm	0:9b334a45a8ff	1393	/* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm	0:9b334a45a8ff	1394	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1395	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1396	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1397	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1398	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1399	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1400	/**
bogdanm	0:9b334a45a8ff	1401	* @}
bogdanm	0:9b334a45a8ff	1402	*/
bogdanm	0:9b334a45a8ff	1403
bogdanm	0:9b334a45a8ff	1404	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
bogdanm	0:9b334a45a8ff	1405	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	1406	* @{
bogdanm	0:9b334a45a8ff	1407	*/
bogdanm	0:9b334a45a8ff	1408	/* Peripheral State functions **************************************************/
bogdanm	0:9b334a45a8ff	1409	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1410	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1411	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1412	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1413	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1414	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1415	/**
bogdanm	0:9b334a45a8ff	1416	* @}
bogdanm	0:9b334a45a8ff	1417	*/
bogdanm	0:9b334a45a8ff	1418
bogdanm	0:9b334a45a8ff	1419	/**
bogdanm	0:9b334a45a8ff	1420	* @}
bogdanm	0:9b334a45a8ff	1421	*/
bogdanm	0:9b334a45a8ff	1422
bogdanm	0:9b334a45a8ff	1423	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
bogdanm	0:9b334a45a8ff	1424	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	1425	void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	1426	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	1427	void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	1428	void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	1429	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm	0:9b334a45a8ff	1430	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
bogdanm	0:9b334a45a8ff	1431
bogdanm	0:9b334a45a8ff	1432	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1433	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1434	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1435	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
bogdanm	0:9b334a45a8ff	1436
bogdanm	0:9b334a45a8ff	1437	/**
bogdanm	0:9b334a45a8ff	1438	* @}
bogdanm	0:9b334a45a8ff	1439	*/
bogdanm	0:9b334a45a8ff	1440
bogdanm	0:9b334a45a8ff	1441	/**
bogdanm	0:9b334a45a8ff	1442	* @}
bogdanm	0:9b334a45a8ff	1443	*/
bogdanm	0:9b334a45a8ff	1444
bogdanm	0:9b334a45a8ff	1445	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1446	}
bogdanm	0:9b334a45a8ff	1447	#endif
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	#endif /* __STM32F3xx_HAL_TIM_H */
bogdanm	0:9b334a45a8ff	1450
bogdanm	0:9b334a45a8ff	1451	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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