mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s_ex.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f3xx_hal_i2s_ex.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.1.0
bogdanm	0:9b334a45a8ff	6	* @date 12-Sept-2014
bogdanm	0:9b334a45a8ff	7	* @brief I2S Extended HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of I2S Extended peripheral:
bogdanm	0:9b334a45a8ff	10	* + Extended features Functions
bogdanm	0:9b334a45a8ff	11	*
bogdanm	0:9b334a45a8ff	12	@verbatim
bogdanm	0:9b334a45a8ff	13	==============================================================================
bogdanm	0:9b334a45a8ff	14	##### I2S Extended features #####
bogdanm	0:9b334a45a8ff	15	==============================================================================
bogdanm	0:9b334a45a8ff	16	[..]
bogdanm	0:9b334a45a8ff	17	(#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
bogdanm	0:9b334a45a8ff	18	data simultaneously using two data lines. Each SPI peripheral has an extended block
bogdanm	0:9b334a45a8ff	19	called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3).
bogdanm	0:9b334a45a8ff	20	(#) The Extended block is not a full SPI IP, it is used only as I2S slave to
bogdanm	0:9b334a45a8ff	21	implement full duplex mode. The Extended block uses the same clock sources
bogdanm	0:9b334a45a8ff	22	as its master (refer to the following Figure).
bogdanm	0:9b334a45a8ff	23
bogdanm	0:9b334a45a8ff	24	+-----------------------+
bogdanm	0:9b334a45a8ff	25	I2Sx_SCK \| \|
bogdanm	0:9b334a45a8ff	26	----------+-->\| I2Sx \|------------------->I2Sx_SD(in/out)
bogdanm	0:9b334a45a8ff	27	+--\|-->\| \|
bogdanm	0:9b334a45a8ff	28	\| \| +-----------------------+
bogdanm	0:9b334a45a8ff	29	\| \|
bogdanm	0:9b334a45a8ff	30	I2S_WS \| \|
bogdanm	0:9b334a45a8ff	31	------>\| \|
bogdanm	0:9b334a45a8ff	32	\| \| +-----------------------+
bogdanm	0:9b334a45a8ff	33	\| +-->\| \|
bogdanm	0:9b334a45a8ff	34	\| \| I2Sx_ext \|------------------->I2Sx_extSD(in/out)
bogdanm	0:9b334a45a8ff	35	+----->\| \|
bogdanm	0:9b334a45a8ff	36	+-----------------------+
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	(#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
bogdanm	0:9b334a45a8ff	39
bogdanm	0:9b334a45a8ff	40	-@- Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
bogdanm	0:9b334a45a8ff	41	I2Sx can be I2S2 or I2S3.
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	===============================================================================
bogdanm	0:9b334a45a8ff	44	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	45	===============================================================================
bogdanm	0:9b334a45a8ff	46	[..]
bogdanm	0:9b334a45a8ff	47	Three mode of operations are available within this driver :
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	* Polling mode IO operation *
bogdanm	0:9b334a45a8ff	50	=================================
bogdanm	0:9b334a45a8ff	51	[..]
bogdanm	0:9b334a45a8ff	52	(+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
bogdanm	0:9b334a45a8ff	53
bogdanm	0:9b334a45a8ff	54	* Interrupt mode IO operation *
bogdanm	0:9b334a45a8ff	55	===================================
bogdanm	0:9b334a45a8ff	56	[..]
bogdanm	0:9b334a45a8ff	57	(+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
bogdanm	0:9b334a45a8ff	58	(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	59	add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm	0:9b334a45a8ff	60	(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	61	add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm	0:9b334a45a8ff	62	(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	63	add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm	0:9b334a45a8ff	64	(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	65	add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm	0:9b334a45a8ff	66	(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	67	add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm	0:9b334a45a8ff	68
bogdanm	0:9b334a45a8ff	69	* DMA mode IO operation *
bogdanm	0:9b334a45a8ff	70	==============================
bogdanm	0:9b334a45a8ff	71	[..]
bogdanm	0:9b334a45a8ff	72	(+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
bogdanm	0:9b334a45a8ff	73	(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	74	add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm	0:9b334a45a8ff	75	(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	76	add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm	0:9b334a45a8ff	77	(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	78	add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm	0:9b334a45a8ff	79	(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	80	add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm	0:9b334a45a8ff	81	(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	82	add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm	0:9b334a45a8ff	83	(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
bogdanm	0:9b334a45a8ff	84	(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
bogdanm	0:9b334a45a8ff	85	(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
bogdanm	0:9b334a45a8ff	86
bogdanm	0:9b334a45a8ff	87	@endverbatim
bogdanm	0:9b334a45a8ff	88	******************************************************************************
bogdanm	0:9b334a45a8ff	89	* @attention
bogdanm	0:9b334a45a8ff	90	*
bogdanm	0:9b334a45a8ff	91	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	92	*
bogdanm	0:9b334a45a8ff	93	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	94	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	95	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	96	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	97	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	98	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	99	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	100	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	101	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	102	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	103	*
bogdanm	0:9b334a45a8ff	104	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	105	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	106	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	107	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	108	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	109	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	110	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	111	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	112	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	113	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	114	*
bogdanm	0:9b334a45a8ff	115	******************************************************************************
bogdanm	0:9b334a45a8ff	116	*/
bogdanm	0:9b334a45a8ff	117
bogdanm	0:9b334a45a8ff	118	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	119	#include "stm32f3xx_hal.h"
bogdanm	0:9b334a45a8ff	120
bogdanm	0:9b334a45a8ff	121	/** @addtogroup STM32F3xx_HAL_Driver
bogdanm	0:9b334a45a8ff	122	* @{
bogdanm	0:9b334a45a8ff	123	*/
bogdanm	0:9b334a45a8ff	124
bogdanm	0:9b334a45a8ff	125	#ifdef HAL_I2S_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	126
bogdanm	0:9b334a45a8ff	127	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	128	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	0:9b334a45a8ff	129	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
bogdanm	0:9b334a45a8ff	130	defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	133	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	/** @defgroup I2SEx I2S Extended HAL module driver
bogdanm	0:9b334a45a8ff	136	* @brief I2S Extended HAL module driver
bogdanm	0:9b334a45a8ff	137	* @{
bogdanm	0:9b334a45a8ff	138	*/
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	141	/** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef
bogdanm	0:9b334a45a8ff	142	* @{
bogdanm	0:9b334a45a8ff	143	*/
bogdanm	0:9b334a45a8ff	144	typedef enum
bogdanm	0:9b334a45a8ff	145	{
bogdanm	0:9b334a45a8ff	146	I2S_USE_I2S = 0x00, /!< I2Sx should be used /
bogdanm	0:9b334a45a8ff	147	I2S_USE_I2SEXT = 0x01 /!< I2Sx_ext should be used /
bogdanm	0:9b334a45a8ff	148	}I2S_UseTypeDef;
bogdanm	0:9b334a45a8ff	149	/**
bogdanm	0:9b334a45a8ff	150	* @}
bogdanm	0:9b334a45a8ff	151	*/
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	154	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	155	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	156	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	157	/** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
bogdanm	0:9b334a45a8ff	158	* @{
bogdanm	0:9b334a45a8ff	159	*/
bogdanm	0:9b334a45a8ff	160	static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	161	static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	162	static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
bogdanm	0:9b334a45a8ff	163	static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
bogdanm	0:9b334a45a8ff	164	static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
bogdanm	0:9b334a45a8ff	165	uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
bogdanm	0:9b334a45a8ff	166	/**
bogdanm	0:9b334a45a8ff	167	* @}
bogdanm	0:9b334a45a8ff	168	*/
bogdanm	0:9b334a45a8ff	169
bogdanm	0:9b334a45a8ff	170	/**
bogdanm	0:9b334a45a8ff	171	* @}
bogdanm	0:9b334a45a8ff	172	*/
bogdanm	0:9b334a45a8ff	173	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	174	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	0:9b334a45a8ff	175
bogdanm	0:9b334a45a8ff	176	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	177
bogdanm	0:9b334a45a8ff	178	/** @addtogroup I2S I2S HAL module driver
bogdanm	0:9b334a45a8ff	179	* @{
bogdanm	0:9b334a45a8ff	180	*/
bogdanm	0:9b334a45a8ff	181
bogdanm	0:9b334a45a8ff	182	/** @addtogroup I2S_Exported_Functions I2S Exported Functions
bogdanm	0:9b334a45a8ff	183	* @{
bogdanm	0:9b334a45a8ff	184	*/
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	/** @addtogroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	187	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	188	*
bogdanm	0:9b334a45a8ff	189	@verbatim
bogdanm	0:9b334a45a8ff	190	===============================================================================
bogdanm	0:9b334a45a8ff	191	##### Initialization/de-initialization functions #####
bogdanm	0:9b334a45a8ff	192	===============================================================================
bogdanm	0:9b334a45a8ff	193	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	194	de-initialiaze the I2Sx peripheral in simplex mode:
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	(+) User must Implement HAL_I2S_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	197	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	198
bogdanm	0:9b334a45a8ff	199	(+) Call the function HAL_I2S_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	200	the selected configuration:
bogdanm	0:9b334a45a8ff	201	(++) Mode
bogdanm	0:9b334a45a8ff	202	(++) Standard
bogdanm	0:9b334a45a8ff	203	(++) Data Format
bogdanm	0:9b334a45a8ff	204	(++) MCLK Output
bogdanm	0:9b334a45a8ff	205	(++) Audio frequency
bogdanm	0:9b334a45a8ff	206	(++) Polarity
bogdanm	0:9b334a45a8ff	207
bogdanm	0:9b334a45a8ff	208	(+) Call the function HAL_I2S_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	209	of the selected I2Sx periperal.
bogdanm	0:9b334a45a8ff	210	@endverbatim
bogdanm	0:9b334a45a8ff	211	* @{
bogdanm	0:9b334a45a8ff	212	*/
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	/**
bogdanm	0:9b334a45a8ff	215	* @brief Initializes the I2S according to the specified parameters
bogdanm	0:9b334a45a8ff	216	* in the I2S_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	217	* @param hi2s: I2S handle
bogdanm	0:9b334a45a8ff	218	* @retval HAL status
bogdanm	0:9b334a45a8ff	219	*/
bogdanm	0:9b334a45a8ff	220	HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	221	{
bogdanm	0:9b334a45a8ff	222	uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
bogdanm	0:9b334a45a8ff	223	uint32_t tmp = 0, i2sclk = 0;
bogdanm	0:9b334a45a8ff	224	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	225	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	0:9b334a45a8ff	226	RCC_PeriphCLKInitTypeDef rccperiphclkinit;
bogdanm	0:9b334a45a8ff	227	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	228	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	0:9b334a45a8ff	229
bogdanm	0:9b334a45a8ff	230	/* Check the I2S handle allocation */
bogdanm	0:9b334a45a8ff	231	if(hi2s == HAL_NULL)
bogdanm	0:9b334a45a8ff	232	{
bogdanm	0:9b334a45a8ff	233	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	234	}
bogdanm	0:9b334a45a8ff	235
bogdanm	0:9b334a45a8ff	236	/* Check the parameters */
bogdanm	0:9b334a45a8ff	237	assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
bogdanm	0:9b334a45a8ff	238	assert_param(IS_I2S_MODE(hi2s->Init.Mode));
bogdanm	0:9b334a45a8ff	239	assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
bogdanm	0:9b334a45a8ff	240	assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
bogdanm	0:9b334a45a8ff	241	assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
bogdanm	0:9b334a45a8ff	242	assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
bogdanm	0:9b334a45a8ff	243	assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
bogdanm	0:9b334a45a8ff	244	assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
bogdanm	0:9b334a45a8ff	245	assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	hi2s->State = HAL_I2S_STATE_BUSY;
bogdanm	0:9b334a45a8ff	248
bogdanm	0:9b334a45a8ff	249	/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
bogdanm	0:9b334a45a8ff	250	HAL_I2S_MspInit(hi2s);
bogdanm	0:9b334a45a8ff	251
bogdanm	0:9b334a45a8ff	252	/----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------/
bogdanm	0:9b334a45a8ff	253	/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
bogdanm	0:9b334a45a8ff	254	hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CKPOL \| \
bogdanm	0:9b334a45a8ff	255	SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC \| SPI_I2SCFGR_I2SCFG \| \
bogdanm	0:9b334a45a8ff	256	SPI_I2SCFGR_I2SE \| SPI_I2SCFGR_I2SMOD);
bogdanm	0:9b334a45a8ff	257	hi2s->Instance->I2SPR = 0x0002;
bogdanm	0:9b334a45a8ff	258
bogdanm	0:9b334a45a8ff	259	/* Get the I2SCFGR register value */
bogdanm	0:9b334a45a8ff	260	tmpreg = hi2s->Instance->I2SCFGR;
bogdanm	0:9b334a45a8ff	261
bogdanm	0:9b334a45a8ff	262	/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
bogdanm	0:9b334a45a8ff	263	if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
bogdanm	0:9b334a45a8ff	264	{
bogdanm	0:9b334a45a8ff	265	i2sodd = (uint16_t)0;
bogdanm	0:9b334a45a8ff	266	i2sdiv = (uint16_t)2;
bogdanm	0:9b334a45a8ff	267	}
bogdanm	0:9b334a45a8ff	268	/* If the requested audio frequency is not the default, compute the prescaler */
bogdanm	0:9b334a45a8ff	269	else
bogdanm	0:9b334a45a8ff	270	{
bogdanm	0:9b334a45a8ff	271	/* Check the frame length (For the Prescaler computing) *******************/
bogdanm	0:9b334a45a8ff	272	if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
bogdanm	0:9b334a45a8ff	273	{
bogdanm	0:9b334a45a8ff	274	/* Packet length is 16 bits */
bogdanm	0:9b334a45a8ff	275	packetlength = 1;
bogdanm	0:9b334a45a8ff	276	}
bogdanm	0:9b334a45a8ff	277	else
bogdanm	0:9b334a45a8ff	278	{
bogdanm	0:9b334a45a8ff	279	/* Packet length is 32 bits */
bogdanm	0:9b334a45a8ff	280	packetlength = 2;
bogdanm	0:9b334a45a8ff	281	}
bogdanm	0:9b334a45a8ff	282
bogdanm	0:9b334a45a8ff	283	/* Get I2S source Clock frequency ****************************************/
bogdanm	0:9b334a45a8ff	284	#if defined (STM32F302xE) \|\| defined (STM32F303xE) \|\| defined (STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	285	defined (STM32F302xC) \|\| defined (STM32F303xC) \|\| defined (STM32F358xx)
bogdanm	0:9b334a45a8ff	286	rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_I2S;
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	/* If an external I2S clock has to be used, the specific define should be set
bogdanm	0:9b334a45a8ff	289	in the project configuration or in the stm32f3xx_conf.h file */
bogdanm	0:9b334a45a8ff	290	if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
bogdanm	0:9b334a45a8ff	291	{
bogdanm	0:9b334a45a8ff	292	/* Set external clock as I2S clock source */
bogdanm	0:9b334a45a8ff	293	rccperiphclkinit.I2sClockSelection = RCC_I2SCLKSOURCE_EXT;
bogdanm	0:9b334a45a8ff	294	HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
bogdanm	0:9b334a45a8ff	295
bogdanm	0:9b334a45a8ff	296	/* Set the I2S clock to the external clock value */
bogdanm	0:9b334a45a8ff	297	i2sclk = EXTERNAL_CLOCK_VALUE;
bogdanm	0:9b334a45a8ff	298	}
bogdanm	0:9b334a45a8ff	299	else
bogdanm	0:9b334a45a8ff	300	{
bogdanm	0:9b334a45a8ff	301	/* Set SYSCLK as I2S clock source */
bogdanm	0:9b334a45a8ff	302	rccperiphclkinit.I2sClockSelection = RCC_I2SCLKSOURCE_SYSCLK;
bogdanm	0:9b334a45a8ff	303	HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
bogdanm	0:9b334a45a8ff	304
bogdanm	0:9b334a45a8ff	305	/* Get the I2S source clock value */
bogdanm	0:9b334a45a8ff	306	i2sclk = HAL_RCC_GetSysClockFreq();
bogdanm	0:9b334a45a8ff	307	}
bogdanm	0:9b334a45a8ff	308	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	309	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311	#if defined (STM32F373xC) \|\| defined (STM32F378xx)
bogdanm	0:9b334a45a8ff	312	if(hi2s->Instance == SPI1)
bogdanm	0:9b334a45a8ff	313	{
bogdanm	0:9b334a45a8ff	314	i2sclk = HAL_RCC_GetPCLK2Freq();
bogdanm	0:9b334a45a8ff	315	}
bogdanm	0:9b334a45a8ff	316	else if((hi2s->Instance == SPI2) \|\| (hi2s->Instance == SPI3))
bogdanm	0:9b334a45a8ff	317	{
bogdanm	0:9b334a45a8ff	318	i2sclk = HAL_RCC_GetPCLK1Freq();
bogdanm	0:9b334a45a8ff	319	}
bogdanm	0:9b334a45a8ff	320	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	0:9b334a45a8ff	321
bogdanm	0:9b334a45a8ff	322	/* Compute the Real divider depending on the MCLK output state, with a floating point */
bogdanm	0:9b334a45a8ff	323	if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
bogdanm	0:9b334a45a8ff	324	{
bogdanm	0:9b334a45a8ff	325	/* MCLK output is enabled */
bogdanm	0:9b334a45a8ff	326	tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
bogdanm	0:9b334a45a8ff	327	}
bogdanm	0:9b334a45a8ff	328	else
bogdanm	0:9b334a45a8ff	329	{
bogdanm	0:9b334a45a8ff	330	/* MCLK output is disabled */
bogdanm	0:9b334a45a8ff	331	tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
bogdanm	0:9b334a45a8ff	332	}
bogdanm	0:9b334a45a8ff	333
bogdanm	0:9b334a45a8ff	334	/* Remove the flatting point */
bogdanm	0:9b334a45a8ff	335	tmp = tmp / 10;
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	/* Check the parity of the divider */
bogdanm	0:9b334a45a8ff	338	i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	/* Compute the i2sdiv prescaler */
bogdanm	0:9b334a45a8ff	341	i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
bogdanm	0:9b334a45a8ff	342
bogdanm	0:9b334a45a8ff	343	/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
bogdanm	0:9b334a45a8ff	344	i2sodd = (uint16_t) (i2sodd << 8);
bogdanm	0:9b334a45a8ff	345	}
bogdanm	0:9b334a45a8ff	346
bogdanm	0:9b334a45a8ff	347	/* Test if the divider is 1 or 0 or greater than 0xFF */
bogdanm	0:9b334a45a8ff	348	if((i2sdiv < 2) \|\| (i2sdiv > 0xFF))
bogdanm	0:9b334a45a8ff	349	{
bogdanm	0:9b334a45a8ff	350	/* Set the default values */
bogdanm	0:9b334a45a8ff	351	i2sdiv = 2;
bogdanm	0:9b334a45a8ff	352	i2sodd = 0;
bogdanm	0:9b334a45a8ff	353	}
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/* Write to SPIx I2SPR register the computed value */
bogdanm	0:9b334a45a8ff	356	hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv \| (uint16_t)(i2sodd \| (uint16_t)hi2s->Init.MCLKOutput));
bogdanm	0:9b334a45a8ff	357
bogdanm	0:9b334a45a8ff	358	/* Configure the I2S with the I2S_InitStruct values */
bogdanm	0:9b334a45a8ff	359	tmpreg \|= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD \| (uint16_t)(hi2s->Init.Mode \| \
bogdanm	0:9b334a45a8ff	360	(uint16_t)(hi2s->Init.Standard \| (uint16_t)(hi2s->Init.DataFormat \| \
bogdanm	0:9b334a45a8ff	361	(uint16_t)hi2s->Init.CPOL))));
bogdanm	0:9b334a45a8ff	362
bogdanm	0:9b334a45a8ff	363	/* Write to SPIx I2SCFGR */
bogdanm	0:9b334a45a8ff	364	hi2s->Instance->I2SCFGR = tmpreg;
bogdanm	0:9b334a45a8ff	365
bogdanm	0:9b334a45a8ff	366	#if defined (STM32F302xE) \|\| defined (STM32F303xE) \|\| defined (STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	367	defined (STM32F302xC) \|\| defined (STM32F303xC) \|\| defined (STM32F358xx)
bogdanm	0:9b334a45a8ff	368	if (hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
bogdanm	0:9b334a45a8ff	369	{
bogdanm	0:9b334a45a8ff	370	/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
bogdanm	0:9b334a45a8ff	371	I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CKPOL \| \
bogdanm	0:9b334a45a8ff	372	SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC \| SPI_I2SCFGR_I2SCFG \| \
bogdanm	0:9b334a45a8ff	373	SPI_I2SCFGR_I2SE \| SPI_I2SCFGR_I2SMOD);
bogdanm	0:9b334a45a8ff	374	I2SxEXT(hi2s->Instance)->I2SPR = 0x0002;
bogdanm	0:9b334a45a8ff	375
bogdanm	0:9b334a45a8ff	376	/* Get the I2SCFGR register value */
bogdanm	0:9b334a45a8ff	377	tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
bogdanm	0:9b334a45a8ff	378
bogdanm	0:9b334a45a8ff	379	/* Get the mode to be configured for the extended I2S */
bogdanm	0:9b334a45a8ff	380	if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) \|\| (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
bogdanm	0:9b334a45a8ff	381	{
bogdanm	0:9b334a45a8ff	382	tmp = I2S_MODE_SLAVE_RX;
bogdanm	0:9b334a45a8ff	383	}
bogdanm	0:9b334a45a8ff	384	else
bogdanm	0:9b334a45a8ff	385	{
bogdanm	0:9b334a45a8ff	386	if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) \|\| (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
bogdanm	0:9b334a45a8ff	387	{
bogdanm	0:9b334a45a8ff	388	tmp = I2S_MODE_SLAVE_TX;
bogdanm	0:9b334a45a8ff	389	}
bogdanm	0:9b334a45a8ff	390	}
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	/* Configure the I2S Slave with the I2S Master parameter values */
bogdanm	0:9b334a45a8ff	393	tmpreg \|= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD \| (uint16_t)(tmp \| \
bogdanm	0:9b334a45a8ff	394	(uint16_t)(hi2s->Init.Standard \| (uint16_t)(hi2s->Init.DataFormat \| \
bogdanm	0:9b334a45a8ff	395	(uint16_t)hi2s->Init.CPOL))));
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397	/* Write to SPIx I2SCFGR */
bogdanm	0:9b334a45a8ff	398	I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
bogdanm	0:9b334a45a8ff	399	}
bogdanm	0:9b334a45a8ff	400	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	401	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	0:9b334a45a8ff	402
bogdanm	0:9b334a45a8ff	403	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	404	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	405
bogdanm	0:9b334a45a8ff	406	return HAL_OK;
bogdanm	0:9b334a45a8ff	407	}
bogdanm	0:9b334a45a8ff	408	/**
bogdanm	0:9b334a45a8ff	409	* @}
bogdanm	0:9b334a45a8ff	410	*/
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412	#if defined (STM32F302xE) \|\| defined (STM32F303xE) \|\| defined (STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	413	defined (STM32F302xC) \|\| defined (STM32F303xC) \|\| defined (STM32F358xx)
bogdanm	0:9b334a45a8ff	414	/** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions
bogdanm	0:9b334a45a8ff	415	* @{
bogdanm	0:9b334a45a8ff	416	*/
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	/**
bogdanm	0:9b334a45a8ff	419	* @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode.
bogdanm	0:9b334a45a8ff	420	* @param hi2s: I2S handle
bogdanm	0:9b334a45a8ff	421	* @retval HAL status
bogdanm	0:9b334a45a8ff	422	*/
bogdanm	0:9b334a45a8ff	423	void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	424	{
bogdanm	0:9b334a45a8ff	425	__IO uint32_t i2ssr = hi2s->Instance->SR ;
bogdanm	0:9b334a45a8ff	426	__IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR;
bogdanm	0:9b334a45a8ff	427
bogdanm	0:9b334a45a8ff	428	/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
bogdanm	0:9b334a45a8ff	429	if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) \|\| ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
bogdanm	0:9b334a45a8ff	430	{
bogdanm	0:9b334a45a8ff	431	/* I2S in mode Transmitter -------------------------------------------------*/
bogdanm	0:9b334a45a8ff	432	if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
bogdanm	0:9b334a45a8ff	433	{
bogdanm	0:9b334a45a8ff	434	/* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
bogdanm	0:9b334a45a8ff	435	the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
bogdanm	0:9b334a45a8ff	436	I2S_FullDuplexTx_IT(hi2s, I2S_USE_I2S);
bogdanm	0:9b334a45a8ff	437	}
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	/* I2Sext in mode Receiver -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	440	if(((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
bogdanm	0:9b334a45a8ff	441	{
bogdanm	0:9b334a45a8ff	442	/* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
bogdanm	0:9b334a45a8ff	443	the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
bogdanm	0:9b334a45a8ff	444	I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT);
bogdanm	0:9b334a45a8ff	445	}
bogdanm	0:9b334a45a8ff	446
bogdanm	0:9b334a45a8ff	447	/* I2Sext Overrun error interrupt occured --------------------------------*/
bogdanm	0:9b334a45a8ff	448	if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
bogdanm	0:9b334a45a8ff	449	{
bogdanm	0:9b334a45a8ff	450	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	451	__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	452
bogdanm	0:9b334a45a8ff	453	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	454	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	455
bogdanm	0:9b334a45a8ff	456	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	457	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	460	hi2s->ErrorCode \|= HAL_I2S_ERROR_OVR;
bogdanm	0:9b334a45a8ff	461	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	462	}
bogdanm	0:9b334a45a8ff	463
bogdanm	0:9b334a45a8ff	464	/* I2S Underrun error interrupt occured ----------------------------------*/
bogdanm	0:9b334a45a8ff	465	if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
bogdanm	0:9b334a45a8ff	466	{
bogdanm	0:9b334a45a8ff	467	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	468	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	471	__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	472
bogdanm	0:9b334a45a8ff	473	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	474	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	475
bogdanm	0:9b334a45a8ff	476	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	477	hi2s->ErrorCode \|= HAL_I2S_ERROR_UDR;
bogdanm	0:9b334a45a8ff	478	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	479	}
bogdanm	0:9b334a45a8ff	480	}
bogdanm	0:9b334a45a8ff	481	/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
bogdanm	0:9b334a45a8ff	482	else
bogdanm	0:9b334a45a8ff	483	{
bogdanm	0:9b334a45a8ff	484	/* I2Sext in mode Transmitter ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	485	if(((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
bogdanm	0:9b334a45a8ff	486	{
bogdanm	0:9b334a45a8ff	487	/* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
bogdanm	0:9b334a45a8ff	488	the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
bogdanm	0:9b334a45a8ff	489	I2S_FullDuplexTx_IT(hi2s, I2S_USE_I2SEXT);
bogdanm	0:9b334a45a8ff	490	}
bogdanm	0:9b334a45a8ff	491
bogdanm	0:9b334a45a8ff	492	/* I2S in mode Receiver --------------------------------------------------*/
bogdanm	0:9b334a45a8ff	493	if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
bogdanm	0:9b334a45a8ff	494	{
bogdanm	0:9b334a45a8ff	495	/* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
bogdanm	0:9b334a45a8ff	496	the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
bogdanm	0:9b334a45a8ff	497	I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2S);
bogdanm	0:9b334a45a8ff	498	}
bogdanm	0:9b334a45a8ff	499
bogdanm	0:9b334a45a8ff	500	/* I2S Overrun error interrupt occured -------------------------------------*/
bogdanm	0:9b334a45a8ff	501	if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
bogdanm	0:9b334a45a8ff	502	{
bogdanm	0:9b334a45a8ff	503	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	504	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	505
bogdanm	0:9b334a45a8ff	506	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	507	__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	508
bogdanm	0:9b334a45a8ff	509	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	510	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	511
bogdanm	0:9b334a45a8ff	512	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	513	hi2s->ErrorCode \|= HAL_I2S_ERROR_OVR;
bogdanm	0:9b334a45a8ff	514	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	515	}
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	/* I2Sext Underrun error interrupt occured -------------------------------*/
bogdanm	0:9b334a45a8ff	518	if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
bogdanm	0:9b334a45a8ff	519	{
bogdanm	0:9b334a45a8ff	520	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	521	__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	524	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	527	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	530	hi2s->ErrorCode \|= HAL_I2S_ERROR_UDR;
bogdanm	0:9b334a45a8ff	531	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	532	}
bogdanm	0:9b334a45a8ff	533	}
bogdanm	0:9b334a45a8ff	534	}
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	/**
bogdanm	0:9b334a45a8ff	537	* @brief Tx and Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	538	* @param hi2s: I2S handle
bogdanm	0:9b334a45a8ff	539	* @retval None
bogdanm	0:9b334a45a8ff	540	*/
bogdanm	0:9b334a45a8ff	541	__weak void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	542	{
bogdanm	0:9b334a45a8ff	543	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	544	the HAL_I2S_TxRxCpltCallback could be implenetd in the user file
bogdanm	0:9b334a45a8ff	545	*/
bogdanm	0:9b334a45a8ff	546	}
bogdanm	0:9b334a45a8ff	547
bogdanm	0:9b334a45a8ff	548	/**
bogdanm	0:9b334a45a8ff	549	* @}
bogdanm	0:9b334a45a8ff	550	*/
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	553	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	0:9b334a45a8ff	554
bogdanm	0:9b334a45a8ff	555	/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	556	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	557	*
bogdanm	0:9b334a45a8ff	558	*
bogdanm	0:9b334a45a8ff	559	@verbatim
bogdanm	0:9b334a45a8ff	560	===============================================================================
bogdanm	0:9b334a45a8ff	561	##### Peripheral State functions #####
bogdanm	0:9b334a45a8ff	562	===============================================================================
bogdanm	0:9b334a45a8ff	563	[..]
bogdanm	0:9b334a45a8ff	564	This subsection permit to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	565	and the data flow.
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567	@endverbatim
bogdanm	0:9b334a45a8ff	568	* @{
bogdanm	0:9b334a45a8ff	569	*/
bogdanm	0:9b334a45a8ff	570	/**
bogdanm	0:9b334a45a8ff	571	* @brief Pauses the audio stream playing from the Media.
bogdanm	0:9b334a45a8ff	572	* @param hi2s : I2S handle
bogdanm	0:9b334a45a8ff	573	* @retval None
bogdanm	0:9b334a45a8ff	574	*/
bogdanm	0:9b334a45a8ff	575	HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	576	{
bogdanm	0:9b334a45a8ff	577	/* Process Locked */
bogdanm	0:9b334a45a8ff	578	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	581	{
bogdanm	0:9b334a45a8ff	582	/* Pause the audio file playing by disabling the I2S DMA request */
bogdanm	0:9b334a45a8ff	583	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	584	}
bogdanm	0:9b334a45a8ff	585	else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	586	{
bogdanm	0:9b334a45a8ff	587	/* Pause the audio file playing by disabling the I2S DMA request */
bogdanm	0:9b334a45a8ff	588	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	589	}
bogdanm	0:9b334a45a8ff	590	#if defined (STM32F302xE) \|\| defined (STM32F303xE) \|\| defined (STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	591	defined (STM32F302xC) \|\| defined (STM32F303xC) \|\| defined (STM32F358xx)
bogdanm	0:9b334a45a8ff	592	else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	593	{
bogdanm	0:9b334a45a8ff	594	/* Pause the audio file playing by disabling the I2S DMA request */
bogdanm	0:9b334a45a8ff	595	hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN \| SPI_CR2_TXDMAEN));
bogdanm	0:9b334a45a8ff	596	I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN \| SPI_CR2_TXDMAEN));
bogdanm	0:9b334a45a8ff	597	}
bogdanm	0:9b334a45a8ff	598	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	599	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	602	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	603
bogdanm	0:9b334a45a8ff	604	return HAL_OK;
bogdanm	0:9b334a45a8ff	605	}
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	/**
bogdanm	0:9b334a45a8ff	608	* @brief Resumes the audio stream playing from the Media.
bogdanm	0:9b334a45a8ff	609	* @param hi2s : I2S handle
bogdanm	0:9b334a45a8ff	610	* @retval None
bogdanm	0:9b334a45a8ff	611	*/
bogdanm	0:9b334a45a8ff	612	HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	613	{
bogdanm	0:9b334a45a8ff	614	/* Process Locked */
bogdanm	0:9b334a45a8ff	615	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	618	{
bogdanm	0:9b334a45a8ff	619	/* Enable the I2S DMA request */
bogdanm	0:9b334a45a8ff	620	hi2s->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	621	}
bogdanm	0:9b334a45a8ff	622	else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	623	{
bogdanm	0:9b334a45a8ff	624	/* Enable the I2S DMA request */
bogdanm	0:9b334a45a8ff	625	hi2s->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	626	}
bogdanm	0:9b334a45a8ff	627	#if defined (STM32F302xE) \|\| defined (STM32F303xE) \|\| defined (STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	628	defined (STM32F302xC) \|\| defined (STM32F303xC) \|\| defined (STM32F358xx)
bogdanm	0:9b334a45a8ff	629	else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	630	{
bogdanm	0:9b334a45a8ff	631	/* Pause the audio file playing by disabling the I2S DMA request */
bogdanm	0:9b334a45a8ff	632	hi2s->Instance->CR2 \|= (SPI_CR2_RXDMAEN \| SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	633	I2SxEXT(hi2s->Instance)->CR2 \|= (SPI_CR2_RXDMAEN \| SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	634
bogdanm	0:9b334a45a8ff	635	/* If the I2Sext peripheral is still not enabled, enable it */
bogdanm	0:9b334a45a8ff	636	if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
bogdanm	0:9b334a45a8ff	637	{
bogdanm	0:9b334a45a8ff	638	/* Enable I2Sext peripheral */
bogdanm	0:9b334a45a8ff	639	__HAL_I2SEXT_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	640	}
bogdanm	0:9b334a45a8ff	641	}
bogdanm	0:9b334a45a8ff	642	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	643	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	0:9b334a45a8ff	644
bogdanm	0:9b334a45a8ff	645	/* If the I2S peripheral is still not enabled, enable it */
bogdanm	0:9b334a45a8ff	646	if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
bogdanm	0:9b334a45a8ff	647	{
bogdanm	0:9b334a45a8ff	648	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	649	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	650	}
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	653	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	654
bogdanm	0:9b334a45a8ff	655	return HAL_OK;
bogdanm	0:9b334a45a8ff	656	}
bogdanm	0:9b334a45a8ff	657
bogdanm	0:9b334a45a8ff	658	/**
bogdanm	0:9b334a45a8ff	659	* @brief Resumes the audio stream playing from the Media.
bogdanm	0:9b334a45a8ff	660	* @param hi2s: I2S handle
bogdanm	0:9b334a45a8ff	661	* @retval None
bogdanm	0:9b334a45a8ff	662	*/
bogdanm	0:9b334a45a8ff	663	HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	664	{
bogdanm	0:9b334a45a8ff	665	/* Process Locked */
bogdanm	0:9b334a45a8ff	666	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	667
bogdanm	0:9b334a45a8ff	668	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	669	{
bogdanm	0:9b334a45a8ff	670	/* Disable the I2S DMA requests */
bogdanm	0:9b334a45a8ff	671	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	672
bogdanm	0:9b334a45a8ff	673	/* Disable the I2S DMA Channel */
bogdanm	0:9b334a45a8ff	674	HAL_DMA_Abort(hi2s->hdmatx);
bogdanm	0:9b334a45a8ff	675	}
bogdanm	0:9b334a45a8ff	676	else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	677	{
bogdanm	0:9b334a45a8ff	678	/* Disable the I2S DMA requests */
bogdanm	0:9b334a45a8ff	679	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	680
bogdanm	0:9b334a45a8ff	681	/* Disable the I2S DMA Channel */
bogdanm	0:9b334a45a8ff	682	HAL_DMA_Abort(hi2s->hdmarx);
bogdanm	0:9b334a45a8ff	683	}
bogdanm	0:9b334a45a8ff	684	#if defined (STM32F302xE) \|\| defined (STM32F303xE) \|\| defined (STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	685	defined (STM32F302xC) \|\| defined (STM32F303xC) \|\| defined (STM32F358xx)
bogdanm	0:9b334a45a8ff	686	else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	687	{
bogdanm	0:9b334a45a8ff	688	/* Disable the I2S DMA requests */
bogdanm	0:9b334a45a8ff	689	hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN \| SPI_CR2_TXDMAEN));
bogdanm	0:9b334a45a8ff	690	I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN \| SPI_CR2_TXDMAEN));
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692	/* Disable the I2S DMA Channels */
bogdanm	0:9b334a45a8ff	693	HAL_DMA_Abort(hi2s->hdmatx);
bogdanm	0:9b334a45a8ff	694	HAL_DMA_Abort(hi2s->hdmarx);
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	/* Disable I2Sext peripheral */
bogdanm	0:9b334a45a8ff	697	__HAL_I2SEXT_DISABLE(hi2s);
bogdanm	0:9b334a45a8ff	698	}
bogdanm	0:9b334a45a8ff	699	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	700	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	0:9b334a45a8ff	701
bogdanm	0:9b334a45a8ff	702	/* Disable I2S peripheral */
bogdanm	0:9b334a45a8ff	703	__HAL_I2S_DISABLE(hi2s);
bogdanm	0:9b334a45a8ff	704
bogdanm	0:9b334a45a8ff	705	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	706
bogdanm	0:9b334a45a8ff	707	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	708	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	709
bogdanm	0:9b334a45a8ff	710	return HAL_OK;
bogdanm	0:9b334a45a8ff	711	}
bogdanm	0:9b334a45a8ff	712
bogdanm	0:9b334a45a8ff	713	/**
bogdanm	0:9b334a45a8ff	714	* @}
bogdanm	0:9b334a45a8ff	715	*/
bogdanm	0:9b334a45a8ff	716
bogdanm	0:9b334a45a8ff	717	/**
bogdanm	0:9b334a45a8ff	718	* @}
bogdanm	0:9b334a45a8ff	719	*/
bogdanm	0:9b334a45a8ff	720
bogdanm	0:9b334a45a8ff	721	/**
bogdanm	0:9b334a45a8ff	722	* @}
bogdanm	0:9b334a45a8ff	723	*/
bogdanm	0:9b334a45a8ff	724
bogdanm	0:9b334a45a8ff	725	#if defined (STM32F302xE) \|\| defined (STM32F303xE) \|\| defined (STM32F398xx) \|\| \
bogdanm	0:9b334a45a8ff	726	defined (STM32F302xC) \|\| defined (STM32F303xC) \|\| defined (STM32F358xx)
bogdanm	0:9b334a45a8ff	727	/** @addtogroup I2SEx I2S Extended HAL module driver
bogdanm	0:9b334a45a8ff	728	* @brief I2S Extended HAL module driver
bogdanm	0:9b334a45a8ff	729	* @{
bogdanm	0:9b334a45a8ff	730	*/
bogdanm	0:9b334a45a8ff	731
bogdanm	0:9b334a45a8ff	732	/** @defgroup I2SEx_Exported_Functions I2S Extended Exported Functions
bogdanm	0:9b334a45a8ff	733	* @{
bogdanm	0:9b334a45a8ff	734	*/
bogdanm	0:9b334a45a8ff	735
bogdanm	0:9b334a45a8ff	736	/** @defgroup I2SEx_Exported_Functions_Group1 Extended features functions
bogdanm	0:9b334a45a8ff	737	* @brief Extended features functions
bogdanm	0:9b334a45a8ff	738	*
bogdanm	0:9b334a45a8ff	739	@verbatim
bogdanm	0:9b334a45a8ff	740	===============================================================================
bogdanm	0:9b334a45a8ff	741	##### Extended features Functions #####
bogdanm	0:9b334a45a8ff	742	===============================================================================
bogdanm	0:9b334a45a8ff	743	[..]
bogdanm	0:9b334a45a8ff	744	This subsection provides a set of functions allowing to manage the I2S data
bogdanm	0:9b334a45a8ff	745	transfers.
bogdanm	0:9b334a45a8ff	746
bogdanm	0:9b334a45a8ff	747	(#) There is two mode of transfer:
bogdanm	0:9b334a45a8ff	748	(++) Blocking mode: The communication is performed in the polling mode.
bogdanm	0:9b334a45a8ff	749	The status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	750	after finishing transfer.
bogdanm	0:9b334a45a8ff	751	(++) No-Blocking mode: The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	752	or DMA. These functions return the status of the transfer startup.
bogdanm	0:9b334a45a8ff	753	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	754	dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	755	using DMA mode.
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	(#) Blocking mode functions are :
bogdanm	0:9b334a45a8ff	758	(++) HAL_I2S_TransmitReceive()
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760	(#) No-Blocking mode functions with Interrupt are:
bogdanm	0:9b334a45a8ff	761	(++) HAL_I2S_TransmitReceive_IT()
bogdanm	0:9b334a45a8ff	762	(++) HAL_I2SFullDuplex_IRQHandler()
bogdanm	0:9b334a45a8ff	763
bogdanm	0:9b334a45a8ff	764	(#) No-Blocking mode functions with DMA are:
bogdanm	0:9b334a45a8ff	765	(++) HAL_I2S_TransmitReceive_DMA()
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
bogdanm	0:9b334a45a8ff	768	(++) HAL_I2S_TxRxCpltCallback()
bogdanm	0:9b334a45a8ff	769	(++) HAL_I2S_TxRxErrorCallback()
bogdanm	0:9b334a45a8ff	770
bogdanm	0:9b334a45a8ff	771	@endverbatim
bogdanm	0:9b334a45a8ff	772	* @{
bogdanm	0:9b334a45a8ff	773	*/
bogdanm	0:9b334a45a8ff	774
bogdanm	0:9b334a45a8ff	775	/**
bogdanm	0:9b334a45a8ff	776	* @brief Full-Duplex Transmit/Receive data in blocking mode.
bogdanm	0:9b334a45a8ff	777	* @param hi2s: I2S handle
bogdanm	0:9b334a45a8ff	778	* @param pTxData: a 16-bit pointer to the Transmit data buffer.
bogdanm	0:9b334a45a8ff	779	* @param pRxData: a 16-bit pointer to the Receive data buffer.
bogdanm	0:9b334a45a8ff	780	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	781	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	782	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	783	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	784	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	785	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	786	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	787	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	788	* @retval HAL status
bogdanm	0:9b334a45a8ff	789	*/
bogdanm	0:9b334a45a8ff	790	HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef hi2s, uint16_t pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	791	{
bogdanm	0:9b334a45a8ff	792	if((pTxData == HAL_NULL ) \|\| (pRxData == HAL_NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	793	{
bogdanm	0:9b334a45a8ff	794	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	795	}
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	/* Check the I2S State */
bogdanm	0:9b334a45a8ff	798	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	799	{
bogdanm	0:9b334a45a8ff	800	/* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
bogdanm	0:9b334a45a8ff	801	is selected during the I2S configuration phase, the Size parameter means the number
bogdanm	0:9b334a45a8ff	802	of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
bogdanm	0:9b334a45a8ff	803	frame is selected the Size parameter means the number of 16-bit data length. */
bogdanm	0:9b334a45a8ff	804	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	805	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	806	{
bogdanm	0:9b334a45a8ff	807	hi2s->TxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	808	hi2s->TxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	809	hi2s->RxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	810	hi2s->RxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	811	}
bogdanm	0:9b334a45a8ff	812	else
bogdanm	0:9b334a45a8ff	813	{
bogdanm	0:9b334a45a8ff	814	hi2s->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	815	hi2s->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	816	hi2s->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	817	hi2s->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	818	}
bogdanm	0:9b334a45a8ff	819
bogdanm	0:9b334a45a8ff	820	/* Process Locked */
bogdanm	0:9b334a45a8ff	821	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	/* Set the I2S State busy TX/RX */
bogdanm	0:9b334a45a8ff	826	hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
bogdanm	0:9b334a45a8ff	829	if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) \|\| ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
bogdanm	0:9b334a45a8ff	830	{
bogdanm	0:9b334a45a8ff	831	/* Prepare the First Data before enabling the I2S */
bogdanm	0:9b334a45a8ff	832	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
bogdanm	0:9b334a45a8ff	833	{
bogdanm	0:9b334a45a8ff	834	hi2s->Instance->DR = (*pTxData++);
bogdanm	0:9b334a45a8ff	835	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	836	}
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838	/* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
bogdanm	0:9b334a45a8ff	839	to avoid the clock de-synchronization between Master and Slave. */
bogdanm	0:9b334a45a8ff	840	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	841	{
bogdanm	0:9b334a45a8ff	842	/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
bogdanm	0:9b334a45a8ff	843	__HAL_I2SEXT_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	844
bogdanm	0:9b334a45a8ff	845	/* Enable I2Sx peripheral */
bogdanm	0:9b334a45a8ff	846	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	847	}
bogdanm	0:9b334a45a8ff	848
bogdanm	0:9b334a45a8ff	849	while(hi2s->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	850	{
bogdanm	0:9b334a45a8ff	851	/* Wait until TXE flag is set */
bogdanm	0:9b334a45a8ff	852	if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
bogdanm	0:9b334a45a8ff	853	{
bogdanm	0:9b334a45a8ff	854	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	855	hi2s->ErrorCode \|= HAL_I2S_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	856	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	857	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	858	}
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	if (hi2s->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	861	{
bogdanm	0:9b334a45a8ff	862	/* Check if an underrun occurs */
bogdanm	0:9b334a45a8ff	863	if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
bogdanm	0:9b334a45a8ff	864	{
bogdanm	0:9b334a45a8ff	865	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	866	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	869	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	870
bogdanm	0:9b334a45a8ff	871	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	872	hi2s->ErrorCode \|= HAL_I2S_ERROR_UDR;
bogdanm	0:9b334a45a8ff	873	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	874
bogdanm	0:9b334a45a8ff	875	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	876	}
bogdanm	0:9b334a45a8ff	877
bogdanm	0:9b334a45a8ff	878	hi2s->Instance->DR = (*pTxData++);
bogdanm	0:9b334a45a8ff	879	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	880	}
bogdanm	0:9b334a45a8ff	881
bogdanm	0:9b334a45a8ff	882	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	883	if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
bogdanm	0:9b334a45a8ff	884	{
bogdanm	0:9b334a45a8ff	885	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	886	hi2s->ErrorCode \|= HAL_I2S_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	887	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	888	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	889	}
bogdanm	0:9b334a45a8ff	890
bogdanm	0:9b334a45a8ff	891	/* Check if an overrun occurs */
bogdanm	0:9b334a45a8ff	892	if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
bogdanm	0:9b334a45a8ff	893	{
bogdanm	0:9b334a45a8ff	894	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	895	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	896
bogdanm	0:9b334a45a8ff	897	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	898	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	899
bogdanm	0:9b334a45a8ff	900	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	901	hi2s->ErrorCode \|= HAL_I2S_ERROR_OVR;
bogdanm	0:9b334a45a8ff	902	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	905	}
bogdanm	0:9b334a45a8ff	906
bogdanm	0:9b334a45a8ff	907	(*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
bogdanm	0:9b334a45a8ff	908	hi2s->RxXferCount--;
bogdanm	0:9b334a45a8ff	909	}
bogdanm	0:9b334a45a8ff	910	}
bogdanm	0:9b334a45a8ff	911	/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
bogdanm	0:9b334a45a8ff	912	else
bogdanm	0:9b334a45a8ff	913	{
bogdanm	0:9b334a45a8ff	914	/* Prepare the First Data before enabling the I2S */
bogdanm	0:9b334a45a8ff	915	I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
bogdanm	0:9b334a45a8ff	916	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	919	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	920	{
bogdanm	0:9b334a45a8ff	921	/* Enable I2S peripheral before the I2Sext*/
bogdanm	0:9b334a45a8ff	922	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	923
bogdanm	0:9b334a45a8ff	924	/* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
bogdanm	0:9b334a45a8ff	925	__HAL_I2SEXT_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	926	}
bogdanm	0:9b334a45a8ff	927
bogdanm	0:9b334a45a8ff	928	/* Check if Master Receiver mode is selected */
bogdanm	0:9b334a45a8ff	929	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm	0:9b334a45a8ff	930	{
bogdanm	0:9b334a45a8ff	931	/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
bogdanm	0:9b334a45a8ff	932	access to the SPI_SR register. */
bogdanm	0:9b334a45a8ff	933	__HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm	0:9b334a45a8ff	934	}
bogdanm	0:9b334a45a8ff	935
bogdanm	0:9b334a45a8ff	936	while(hi2s->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	937	{
bogdanm	0:9b334a45a8ff	938	/* Wait until TXE flag is set */
bogdanm	0:9b334a45a8ff	939	if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
bogdanm	0:9b334a45a8ff	940	{
bogdanm	0:9b334a45a8ff	941	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	942	hi2s->ErrorCode \|= HAL_I2S_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	943	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	944	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	945	}
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	if (hi2s->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	948	{
bogdanm	0:9b334a45a8ff	949	/* Check if an underrun occurs */
bogdanm	0:9b334a45a8ff	950	if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
bogdanm	0:9b334a45a8ff	951	{
bogdanm	0:9b334a45a8ff	952	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	953	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	956	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	959	hi2s->ErrorCode \|= HAL_I2S_ERROR_UDR;
bogdanm	0:9b334a45a8ff	960	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	963	}
bogdanm	0:9b334a45a8ff	964
bogdanm	0:9b334a45a8ff	965	I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
bogdanm	0:9b334a45a8ff	966	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	967	}
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	970	if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
bogdanm	0:9b334a45a8ff	971	{
bogdanm	0:9b334a45a8ff	972	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	973	hi2s->ErrorCode \|= HAL_I2S_ERROR_TIMEOUT;
bogdanm	0:9b334a45a8ff	974	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	975	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	976	}
bogdanm	0:9b334a45a8ff	977
bogdanm	0:9b334a45a8ff	978	/* Check if an overrun occurs */
bogdanm	0:9b334a45a8ff	979	if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
bogdanm	0:9b334a45a8ff	980	{
bogdanm	0:9b334a45a8ff	981	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	982	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	983
bogdanm	0:9b334a45a8ff	984	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	985	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	986
bogdanm	0:9b334a45a8ff	987	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	988	hi2s->ErrorCode \|= HAL_I2S_ERROR_OVR;
bogdanm	0:9b334a45a8ff	989	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	992	}
bogdanm	0:9b334a45a8ff	993
bogdanm	0:9b334a45a8ff	994	(*pRxData++) = hi2s->Instance->DR;
bogdanm	0:9b334a45a8ff	995	hi2s->RxXferCount--;
bogdanm	0:9b334a45a8ff	996	}
bogdanm	0:9b334a45a8ff	997	}
bogdanm	0:9b334a45a8ff	998
bogdanm	0:9b334a45a8ff	999	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	1000	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1001
bogdanm	0:9b334a45a8ff	1002	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1003	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1004
bogdanm	0:9b334a45a8ff	1005	return HAL_OK;
bogdanm	0:9b334a45a8ff	1006	}
bogdanm	0:9b334a45a8ff	1007	else
bogdanm	0:9b334a45a8ff	1008	{
bogdanm	0:9b334a45a8ff	1009	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1010	}
bogdanm	0:9b334a45a8ff	1011	}
bogdanm	0:9b334a45a8ff	1012
bogdanm	0:9b334a45a8ff	1013	/**
bogdanm	0:9b334a45a8ff	1014	* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
bogdanm	0:9b334a45a8ff	1015	* @param hi2s: I2S handle
bogdanm	0:9b334a45a8ff	1016	* @param pTxData: a 16-bit pointer to the Transmit data buffer.
bogdanm	0:9b334a45a8ff	1017	* @param pRxData: a 16-bit pointer to the Receive data buffer.
bogdanm	0:9b334a45a8ff	1018	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	1019	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	1020	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	1021	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	1022	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	1023	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	1024	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	1025	* @retval HAL status
bogdanm	0:9b334a45a8ff	1026	*/
bogdanm	0:9b334a45a8ff	1027	HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef hi2s, uint16_t pTxData, uint16_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1028	{
bogdanm	0:9b334a45a8ff	1029	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	1030	{
bogdanm	0:9b334a45a8ff	1031	if((pTxData == HAL_NULL ) \|\| (pRxData == HAL_NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1032	{
bogdanm	0:9b334a45a8ff	1033	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1034	}
bogdanm	0:9b334a45a8ff	1035
bogdanm	0:9b334a45a8ff	1036	hi2s->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	1037	hi2s->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039	/* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
bogdanm	0:9b334a45a8ff	1040	is selected during the I2S configuration phase, the Size parameter means the number
bogdanm	0:9b334a45a8ff	1041	of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
bogdanm	0:9b334a45a8ff	1042	frame is selected the Size parameter means the number of 16-bit data length. */
bogdanm	0:9b334a45a8ff	1043	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	1044	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	1045	{
bogdanm	0:9b334a45a8ff	1046	hi2s->TxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	1047	hi2s->TxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	1048	hi2s->RxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	1049	hi2s->RxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	1050	}
bogdanm	0:9b334a45a8ff	1051	else
bogdanm	0:9b334a45a8ff	1052	{
bogdanm	0:9b334a45a8ff	1053	hi2s->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1054	hi2s->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1055	hi2s->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1056	hi2s->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1057	}
bogdanm	0:9b334a45a8ff	1058
bogdanm	0:9b334a45a8ff	1059	/* Process Locked */
bogdanm	0:9b334a45a8ff	1060	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	1061
bogdanm	0:9b334a45a8ff	1062	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1063	hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1064
bogdanm	0:9b334a45a8ff	1065	/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
bogdanm	0:9b334a45a8ff	1066	if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) \|\| ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
bogdanm	0:9b334a45a8ff	1067	{
bogdanm	0:9b334a45a8ff	1068	/* Enable I2Sext RXNE and ERR interrupts */
bogdanm	0:9b334a45a8ff	1069	__HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1070
bogdanm	0:9b334a45a8ff	1071	/* Enable I2Sx TXE and ERR interrupts */
bogdanm	0:9b334a45a8ff	1072	__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1073
bogdanm	0:9b334a45a8ff	1074	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	1075	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	1076	{
bogdanm	0:9b334a45a8ff	1077	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
bogdanm	0:9b334a45a8ff	1078	{
bogdanm	0:9b334a45a8ff	1079	/* Prepare the First Data before enabling the I2S */
bogdanm	0:9b334a45a8ff	1080	if(hi2s->TxXferCount != 0)
bogdanm	0:9b334a45a8ff	1081	{
bogdanm	0:9b334a45a8ff	1082	/* Transmit First data */
bogdanm	0:9b334a45a8ff	1083	hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	1084	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	1085
bogdanm	0:9b334a45a8ff	1086	if(hi2s->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1087	{
bogdanm	0:9b334a45a8ff	1088	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1089	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	if(hi2s->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1092	{
bogdanm	0:9b334a45a8ff	1093	/* Disable I2Sext RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1094	__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE\| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1095
bogdanm	0:9b334a45a8ff	1096	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1097	HAL_I2S_TxRxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1098	}
bogdanm	0:9b334a45a8ff	1099	}
bogdanm	0:9b334a45a8ff	1100	}
bogdanm	0:9b334a45a8ff	1101	}
bogdanm	0:9b334a45a8ff	1102	/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
bogdanm	0:9b334a45a8ff	1103	__HAL_I2SEXT_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	1104
bogdanm	0:9b334a45a8ff	1105	/* Enable I2Sx peripheral */
bogdanm	0:9b334a45a8ff	1106	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	1107	}
bogdanm	0:9b334a45a8ff	1108	}
bogdanm	0:9b334a45a8ff	1109	/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
bogdanm	0:9b334a45a8ff	1110	else
bogdanm	0:9b334a45a8ff	1111	{
bogdanm	0:9b334a45a8ff	1112	/* Enable I2Sext TXE and ERR interrupts */
bogdanm	0:9b334a45a8ff	1113	__HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1114
bogdanm	0:9b334a45a8ff	1115	/* Enable I2Sext RXNE and ERR interrupts */
bogdanm	0:9b334a45a8ff	1116	__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1117
bogdanm	0:9b334a45a8ff	1118	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	1119	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	1120	{
bogdanm	0:9b334a45a8ff	1121	/* Prepare the First Data before enabling the I2S */
bogdanm	0:9b334a45a8ff	1122	if(hi2s->TxXferCount != 0)
bogdanm	0:9b334a45a8ff	1123	{
bogdanm	0:9b334a45a8ff	1124	/* Transmit First data */
bogdanm	0:9b334a45a8ff	1125	I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	1126	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	1127
bogdanm	0:9b334a45a8ff	1128	if(hi2s->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1129	{
bogdanm	0:9b334a45a8ff	1130	/* Disable I2Sext TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1131	__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1132
bogdanm	0:9b334a45a8ff	1133	if(hi2s->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1134	{
bogdanm	0:9b334a45a8ff	1135	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1136	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE\| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1137
bogdanm	0:9b334a45a8ff	1138	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1139	HAL_I2S_TxRxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1140	}
bogdanm	0:9b334a45a8ff	1141	}
bogdanm	0:9b334a45a8ff	1142	}
bogdanm	0:9b334a45a8ff	1143	/* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
bogdanm	0:9b334a45a8ff	1144	__HAL_I2SEXT_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	1147	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	1148	}
bogdanm	0:9b334a45a8ff	1149	}
bogdanm	0:9b334a45a8ff	1150	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1151	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1152
bogdanm	0:9b334a45a8ff	1153	return HAL_OK;
bogdanm	0:9b334a45a8ff	1154	}
bogdanm	0:9b334a45a8ff	1155	else
bogdanm	0:9b334a45a8ff	1156	{
bogdanm	0:9b334a45a8ff	1157	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1158	}
bogdanm	0:9b334a45a8ff	1159	}
bogdanm	0:9b334a45a8ff	1160
bogdanm	0:9b334a45a8ff	1161	/**
bogdanm	0:9b334a45a8ff	1162	* @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
bogdanm	0:9b334a45a8ff	1163	* @param hi2s: I2S handle
bogdanm	0:9b334a45a8ff	1164	* @param pTxData: a 16-bit pointer to the Transmit data buffer.
bogdanm	0:9b334a45a8ff	1165	* @param pRxData: a 16-bit pointer to the Receive data buffer.
bogdanm	0:9b334a45a8ff	1166	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	1167	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	1168	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	1169	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	1170	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	1171	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	1172	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	1173	* @retval HAL status
bogdanm	0:9b334a45a8ff	1174	*/
bogdanm	0:9b334a45a8ff	1175	HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef hi2s, uint16_t pTxData, uint16_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1176	{
bogdanm	0:9b334a45a8ff	1177	uint32_t *tmp;
bogdanm	0:9b334a45a8ff	1178
bogdanm	0:9b334a45a8ff	1179	if((pTxData == HAL_NULL ) \|\| (pRxData == HAL_NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1180	{
bogdanm	0:9b334a45a8ff	1181	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1182	}
bogdanm	0:9b334a45a8ff	1183
bogdanm	0:9b334a45a8ff	1184	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	1185	{
bogdanm	0:9b334a45a8ff	1186	hi2s->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	1187	hi2s->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	1188
bogdanm	0:9b334a45a8ff	1189	/* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
bogdanm	0:9b334a45a8ff	1190	is selected during the I2S configuration phase, the Size parameter means the number
bogdanm	0:9b334a45a8ff	1191	of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
bogdanm	0:9b334a45a8ff	1192	frame is selected the Size parameter means the number of 16-bit data length. */
bogdanm	0:9b334a45a8ff	1193	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	1194	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	1195	{
bogdanm	0:9b334a45a8ff	1196	hi2s->TxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	1197	hi2s->TxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	1198	hi2s->RxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	1199	hi2s->RxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	1200	}
bogdanm	0:9b334a45a8ff	1201	else
bogdanm	0:9b334a45a8ff	1202	{
bogdanm	0:9b334a45a8ff	1203	hi2s->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1204	hi2s->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1205	hi2s->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1206	hi2s->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1207	}
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209	/* Process Locked */
bogdanm	0:9b334a45a8ff	1210	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	1211
bogdanm	0:9b334a45a8ff	1212	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1213	hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1214
bogdanm	0:9b334a45a8ff	1215	/* Set the I2S Rx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1216	hi2s->hdmarx->XferCpltCallback = I2S_TxRxDMACplt;
bogdanm	0:9b334a45a8ff	1217
bogdanm	0:9b334a45a8ff	1218	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1219	hi2s->hdmarx->XferErrorCallback = I2S_TxRxDMAError;
bogdanm	0:9b334a45a8ff	1220
bogdanm	0:9b334a45a8ff	1221	/* Set the I2S Tx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1222	hi2s->hdmatx->XferCpltCallback = I2S_TxRxDMACplt;
bogdanm	0:9b334a45a8ff	1223
bogdanm	0:9b334a45a8ff	1224	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1225	hi2s->hdmatx->XferErrorCallback = I2S_TxRxDMAError;
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227	/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
bogdanm	0:9b334a45a8ff	1228	if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) \|\| ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
bogdanm	0:9b334a45a8ff	1229	{
bogdanm	0:9b334a45a8ff	1230	/* Enable the Rx DMA Channel */
bogdanm	0:9b334a45a8ff	1231	tmp = (uint32_t*)&pRxData;
bogdanm	0:9b334a45a8ff	1232	HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, (uint32_t)tmp, hi2s->RxXferSize);
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1235	I2SxEXT(hi2s->Instance)->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	/* Enable the Tx DMA Channel */
bogdanm	0:9b334a45a8ff	1238	tmp = (uint32_t*)&pTxData;
bogdanm	0:9b334a45a8ff	1239	HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
bogdanm	0:9b334a45a8ff	1240
bogdanm	0:9b334a45a8ff	1241	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1242	hi2s->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	1243
bogdanm	0:9b334a45a8ff	1244	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	1245	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	1246	{
bogdanm	0:9b334a45a8ff	1247	/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
bogdanm	0:9b334a45a8ff	1248	__HAL_I2SEXT_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	1249
bogdanm	0:9b334a45a8ff	1250	/* Enable I2S peripheral after the I2Sext*/
bogdanm	0:9b334a45a8ff	1251	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	1252	}
bogdanm	0:9b334a45a8ff	1253	}
bogdanm	0:9b334a45a8ff	1254	else
bogdanm	0:9b334a45a8ff	1255	{
bogdanm	0:9b334a45a8ff	1256	/* Check if Master Receiver mode is selected */
bogdanm	0:9b334a45a8ff	1257	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm	0:9b334a45a8ff	1258	{
bogdanm	0:9b334a45a8ff	1259	/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
bogdanm	0:9b334a45a8ff	1260	access to the SPI_SR register. */
bogdanm	0:9b334a45a8ff	1261	__HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm	0:9b334a45a8ff	1262	}
bogdanm	0:9b334a45a8ff	1263
bogdanm	0:9b334a45a8ff	1264	/* Enable the Tx DMA Channel */
bogdanm	0:9b334a45a8ff	1265	tmp = (uint32_t*)&pTxData;
bogdanm	0:9b334a45a8ff	1266	HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1269	I2SxEXT(hi2s->Instance)->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	1270
bogdanm	0:9b334a45a8ff	1271	/* Enable the Rx DMA Channel */
bogdanm	0:9b334a45a8ff	1272	tmp = (uint32_t*)&pRxData;
bogdanm	0:9b334a45a8ff	1273	HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)tmp, hi2s->RxXferSize);
bogdanm	0:9b334a45a8ff	1274
bogdanm	0:9b334a45a8ff	1275	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1276	hi2s->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	1277
bogdanm	0:9b334a45a8ff	1278	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	1279	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	1280	{
bogdanm	0:9b334a45a8ff	1281	/* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
bogdanm	0:9b334a45a8ff	1282	__HAL_I2SEXT_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	1283
bogdanm	0:9b334a45a8ff	1284	/* Enable I2S peripheral after the I2Sext*/
bogdanm	0:9b334a45a8ff	1285	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	1286	}
bogdanm	0:9b334a45a8ff	1287	}
bogdanm	0:9b334a45a8ff	1288
bogdanm	0:9b334a45a8ff	1289	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1290	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	return HAL_OK;
bogdanm	0:9b334a45a8ff	1293	}
bogdanm	0:9b334a45a8ff	1294	else
bogdanm	0:9b334a45a8ff	1295	{
bogdanm	0:9b334a45a8ff	1296	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1297	}
bogdanm	0:9b334a45a8ff	1298	}
bogdanm	0:9b334a45a8ff	1299
bogdanm	0:9b334a45a8ff	1300	/**
bogdanm	0:9b334a45a8ff	1301	* @}
bogdanm	0:9b334a45a8ff	1302	*/
bogdanm	0:9b334a45a8ff	1303
bogdanm	0:9b334a45a8ff	1304	/**
bogdanm	0:9b334a45a8ff	1305	* @}
bogdanm	0:9b334a45a8ff	1306	*/
bogdanm	0:9b334a45a8ff	1307
bogdanm	0:9b334a45a8ff	1308	/** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions
bogdanm	0:9b334a45a8ff	1309	* @{
bogdanm	0:9b334a45a8ff	1310	*/
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	/**
bogdanm	0:9b334a45a8ff	1313	* @brief DMA I2S transmit receive process complete callback
bogdanm	0:9b334a45a8ff	1314	* @param hdma: DMA handle
bogdanm	0:9b334a45a8ff	1315	* @retval None
bogdanm	0:9b334a45a8ff	1316	*/
bogdanm	0:9b334a45a8ff	1317	static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1318	{
bogdanm	0:9b334a45a8ff	1319	I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	if (hi2s->hdmarx == hdma)
bogdanm	0:9b334a45a8ff	1322	{
bogdanm	0:9b334a45a8ff	1323	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1324	if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) \|\| ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
bogdanm	0:9b334a45a8ff	1325	{
bogdanm	0:9b334a45a8ff	1326	I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1327	}
bogdanm	0:9b334a45a8ff	1328	else
bogdanm	0:9b334a45a8ff	1329	{
bogdanm	0:9b334a45a8ff	1330	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1331	}
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333	hi2s->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1334
bogdanm	0:9b334a45a8ff	1335	if (hi2s->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1336	{
bogdanm	0:9b334a45a8ff	1337	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1338
bogdanm	0:9b334a45a8ff	1339	HAL_I2S_TxRxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1340	}
bogdanm	0:9b334a45a8ff	1341	}
bogdanm	0:9b334a45a8ff	1342
bogdanm	0:9b334a45a8ff	1343	if (hi2s->hdmatx == hdma)
bogdanm	0:9b334a45a8ff	1344	{
bogdanm	0:9b334a45a8ff	1345	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1346	if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) \|\| ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
bogdanm	0:9b334a45a8ff	1347	{
bogdanm	0:9b334a45a8ff	1348	hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1349	}
bogdanm	0:9b334a45a8ff	1350	else
bogdanm	0:9b334a45a8ff	1351	{
bogdanm	0:9b334a45a8ff	1352	I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1353	}
bogdanm	0:9b334a45a8ff	1354
bogdanm	0:9b334a45a8ff	1355	hi2s->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1356
bogdanm	0:9b334a45a8ff	1357	if (hi2s->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1358	{
bogdanm	0:9b334a45a8ff	1359	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1360
bogdanm	0:9b334a45a8ff	1361	HAL_I2S_TxRxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1362	}
bogdanm	0:9b334a45a8ff	1363	}
bogdanm	0:9b334a45a8ff	1364	}
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	/**
bogdanm	0:9b334a45a8ff	1367	* @brief DMA I2S communication error callback
bogdanm	0:9b334a45a8ff	1368	* @param hdma : DMA handle
bogdanm	0:9b334a45a8ff	1369	* @retval None
bogdanm	0:9b334a45a8ff	1370	*/
bogdanm	0:9b334a45a8ff	1371	static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1372	{
bogdanm	0:9b334a45a8ff	1373	I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1374
bogdanm	0:9b334a45a8ff	1375	/* Disable Rx and Tx DMA Request */
bogdanm	0:9b334a45a8ff	1376	hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN \| SPI_CR2_TXDMAEN));
bogdanm	0:9b334a45a8ff	1377	I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN \| SPI_CR2_TXDMAEN));
bogdanm	0:9b334a45a8ff	1378
bogdanm	0:9b334a45a8ff	1379	hi2s->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1380	hi2s->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1381
bogdanm	0:9b334a45a8ff	1382	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1383
bogdanm	0:9b334a45a8ff	1384	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	1385	hi2s->ErrorCode \|= HAL_I2S_ERROR_DMA;
bogdanm	0:9b334a45a8ff	1386	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	1387	}
bogdanm	0:9b334a45a8ff	1388
bogdanm	0:9b334a45a8ff	1389	/**
bogdanm	0:9b334a45a8ff	1390	* @brief Full-Duplex IT handler transmit function
bogdanm	0:9b334a45a8ff	1391	* @param hi2s: I2S handle
bogdanm	0:9b334a45a8ff	1392	* @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
bogdanm	0:9b334a45a8ff	1393	* @retval None
bogdanm	0:9b334a45a8ff	1394	*/
bogdanm	0:9b334a45a8ff	1395	static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
bogdanm	0:9b334a45a8ff	1396	{
bogdanm	0:9b334a45a8ff	1397	if(i2sUsed == I2S_USE_I2S)
bogdanm	0:9b334a45a8ff	1398	{
bogdanm	0:9b334a45a8ff	1399	/* Transmit data */
bogdanm	0:9b334a45a8ff	1400	hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	1401	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	1402
bogdanm	0:9b334a45a8ff	1403	if(hi2s->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1404	{
bogdanm	0:9b334a45a8ff	1405	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1406	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1407
bogdanm	0:9b334a45a8ff	1408	if(hi2s->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1409	{
bogdanm	0:9b334a45a8ff	1410	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1411	HAL_I2S_TxRxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1412	}
bogdanm	0:9b334a45a8ff	1413	}
bogdanm	0:9b334a45a8ff	1414	}
bogdanm	0:9b334a45a8ff	1415	else
bogdanm	0:9b334a45a8ff	1416	{
bogdanm	0:9b334a45a8ff	1417	/* Transmit data */
bogdanm	0:9b334a45a8ff	1418	I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	1419	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	if(hi2s->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1422	{
bogdanm	0:9b334a45a8ff	1423	/* Disable I2Sext TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1424	__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1425
bogdanm	0:9b334a45a8ff	1426	if(hi2s->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1427	{
bogdanm	0:9b334a45a8ff	1428	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1429	HAL_I2S_TxRxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1430	}
bogdanm	0:9b334a45a8ff	1431	}
bogdanm	0:9b334a45a8ff	1432	}
bogdanm	0:9b334a45a8ff	1433	}
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	/**
bogdanm	0:9b334a45a8ff	1436	* @brief Full-Duplex IT handler receive function
bogdanm	0:9b334a45a8ff	1437	* @param hi2s: I2S handle
bogdanm	0:9b334a45a8ff	1438	* @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
bogdanm	0:9b334a45a8ff	1439	* @retval None
bogdanm	0:9b334a45a8ff	1440	*/
bogdanm	0:9b334a45a8ff	1441	static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
bogdanm	0:9b334a45a8ff	1442	{
bogdanm	0:9b334a45a8ff	1443	if(i2sUsed == I2S_USE_I2S)
bogdanm	0:9b334a45a8ff	1444	{
bogdanm	0:9b334a45a8ff	1445	/* Receive data */
bogdanm	0:9b334a45a8ff	1446	(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
bogdanm	0:9b334a45a8ff	1447	hi2s->RxXferCount--;
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	if(hi2s->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1450	{
bogdanm	0:9b334a45a8ff	1451	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1452	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1453
bogdanm	0:9b334a45a8ff	1454	if(hi2s->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1455	{
bogdanm	0:9b334a45a8ff	1456	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1457	HAL_I2S_TxRxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1458	}
bogdanm	0:9b334a45a8ff	1459	}
bogdanm	0:9b334a45a8ff	1460	}
bogdanm	0:9b334a45a8ff	1461	else
bogdanm	0:9b334a45a8ff	1462	{
bogdanm	0:9b334a45a8ff	1463	/* Receive data */
bogdanm	0:9b334a45a8ff	1464	(*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
bogdanm	0:9b334a45a8ff	1465	hi2s->RxXferCount--;
bogdanm	0:9b334a45a8ff	1466
bogdanm	0:9b334a45a8ff	1467	if(hi2s->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1468	{
bogdanm	0:9b334a45a8ff	1469	/* Disable I2Sext RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1470	__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1471
bogdanm	0:9b334a45a8ff	1472	if(hi2s->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1473	{
bogdanm	0:9b334a45a8ff	1474	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1475	HAL_I2S_TxRxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1476	}
bogdanm	0:9b334a45a8ff	1477	}
bogdanm	0:9b334a45a8ff	1478	}
bogdanm	0:9b334a45a8ff	1479	}
bogdanm	0:9b334a45a8ff	1480
bogdanm	0:9b334a45a8ff	1481	/**
bogdanm	0:9b334a45a8ff	1482	* @brief This function handles I2S Communication Timeout.
bogdanm	0:9b334a45a8ff	1483	* @param hi2s: I2S handle
bogdanm	0:9b334a45a8ff	1484	* @param Flag: Flag checked
bogdanm	0:9b334a45a8ff	1485	* @param State: Value of the flag expected
bogdanm	0:9b334a45a8ff	1486	* @param Timeout: Duration of the timeout
bogdanm	0:9b334a45a8ff	1487	* @param i2sUsed: I2S instance reference
bogdanm	0:9b334a45a8ff	1488	* @retval HAL status
bogdanm	0:9b334a45a8ff	1489	*/
bogdanm	0:9b334a45a8ff	1490	static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
bogdanm	0:9b334a45a8ff	1491	uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
bogdanm	0:9b334a45a8ff	1492	{
bogdanm	0:9b334a45a8ff	1493	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1494
bogdanm	0:9b334a45a8ff	1495	if(i2sUsed == I2S_USE_I2S)
bogdanm	0:9b334a45a8ff	1496	{
bogdanm	0:9b334a45a8ff	1497	while((__HAL_I2S_GET_FLAG(hi2s, Flag)) != State)
bogdanm	0:9b334a45a8ff	1498	{
bogdanm	0:9b334a45a8ff	1499	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1500	{
bogdanm	0:9b334a45a8ff	1501	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	1502	{
bogdanm	0:9b334a45a8ff	1503	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	1504	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1507	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1508
bogdanm	0:9b334a45a8ff	1509	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1510	}
bogdanm	0:9b334a45a8ff	1511	}
bogdanm	0:9b334a45a8ff	1512	}
bogdanm	0:9b334a45a8ff	1513	}
bogdanm	0:9b334a45a8ff	1514	else
bogdanm	0:9b334a45a8ff	1515	{
bogdanm	0:9b334a45a8ff	1516	while((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) != State)
bogdanm	0:9b334a45a8ff	1517	{
bogdanm	0:9b334a45a8ff	1518	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1519	{
bogdanm	0:9b334a45a8ff	1520	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	1521	{
bogdanm	0:9b334a45a8ff	1522	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	1523	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1524
bogdanm	0:9b334a45a8ff	1525	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1526	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1527
bogdanm	0:9b334a45a8ff	1528	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1529	}
bogdanm	0:9b334a45a8ff	1530	}
bogdanm	0:9b334a45a8ff	1531	}
bogdanm	0:9b334a45a8ff	1532	}
bogdanm	0:9b334a45a8ff	1533
bogdanm	0:9b334a45a8ff	1534	return HAL_OK;
bogdanm	0:9b334a45a8ff	1535	}
bogdanm	0:9b334a45a8ff	1536	/**
bogdanm	0:9b334a45a8ff	1537	* @}
bogdanm	0:9b334a45a8ff	1538	*/
bogdanm	0:9b334a45a8ff	1539
bogdanm	0:9b334a45a8ff	1540	/**
bogdanm	0:9b334a45a8ff	1541	* @}
bogdanm	0:9b334a45a8ff	1542	*/
bogdanm	0:9b334a45a8ff	1543	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	1544	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	0:9b334a45a8ff	1545
bogdanm	0:9b334a45a8ff	1546	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	0:9b334a45a8ff	1547	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	0:9b334a45a8ff	1548	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| */
bogdanm	0:9b334a45a8ff	1549	/* STM32F373xC \|\| STM32F378xx */
bogdanm	0:9b334a45a8ff	1550
bogdanm	0:9b334a45a8ff	1551	#endif /* HAL_I2S_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1552
bogdanm	0:9b334a45a8ff	1553	/**
bogdanm	0:9b334a45a8ff	1554	* @}
bogdanm	0:9b334a45a8ff	1555	*/
bogdanm	0:9b334a45a8ff	1556
bogdanm	0:9b334a45a8ff	1557	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s_ex.c@0:9b334a45a8ff, 2015-10-01 (annotated)

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