fix LPC812 PWM
Fork of mbed-dev by
targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma_ex.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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bogdanm | 0:9b334a45a8ff | 1 | /** |
bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f3xx_hal_dma_ex.h |
bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
bogdanm | 0:9b334a45a8ff | 5 | * @version V1.1.0 |
bogdanm | 0:9b334a45a8ff | 6 | * @date 12-Sept-2014 |
bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file of DMA HAL Extended module. |
bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 9 | * @attention |
bogdanm | 0:9b334a45a8ff | 10 | * |
bogdanm | 0:9b334a45a8ff | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
bogdanm | 0:9b334a45a8ff | 12 | * |
bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
bogdanm | 0:9b334a45a8ff | 23 | * |
bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 0:9b334a45a8ff | 34 | * |
bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 36 | */ |
bogdanm | 0:9b334a45a8ff | 37 | |
bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32F3xx_HAL_DMA_EX_H |
bogdanm | 0:9b334a45a8ff | 40 | #define __STM32F3xx_HAL_DMA_EX_H |
bogdanm | 0:9b334a45a8ff | 41 | |
bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
bogdanm | 0:9b334a45a8ff | 44 | #endif |
bogdanm | 0:9b334a45a8ff | 45 | |
bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 47 | #include "stm32f3xx_hal_def.h" |
bogdanm | 0:9b334a45a8ff | 48 | |
bogdanm | 0:9b334a45a8ff | 49 | /** @addtogroup STM32F3xx_HAL_Driver |
bogdanm | 0:9b334a45a8ff | 50 | * @{ |
bogdanm | 0:9b334a45a8ff | 51 | */ |
bogdanm | 0:9b334a45a8ff | 52 | |
bogdanm | 0:9b334a45a8ff | 53 | /** @addtogroup DMAEx DMA Extended HAL module driver |
bogdanm | 0:9b334a45a8ff | 54 | * @{ |
bogdanm | 0:9b334a45a8ff | 55 | */ |
bogdanm | 0:9b334a45a8ff | 56 | |
bogdanm | 0:9b334a45a8ff | 57 | /* Exported types ------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 58 | /* Exported constants --------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 59 | /* Exported macros -----------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 60 | /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros |
bogdanm | 0:9b334a45a8ff | 61 | * @{ |
bogdanm | 0:9b334a45a8ff | 62 | */ |
bogdanm | 0:9b334a45a8ff | 63 | /* Interrupt & Flag management */ |
bogdanm | 0:9b334a45a8ff | 64 | |
bogdanm | 0:9b334a45a8ff | 65 | /** |
bogdanm | 0:9b334a45a8ff | 66 | * @brief Returns the current DMA Channel transfer complete flag. |
bogdanm | 0:9b334a45a8ff | 67 | * @param __HANDLE__: DMA handle |
bogdanm | 0:9b334a45a8ff | 68 | * @retval The specified transfer complete flag index. |
bogdanm | 0:9b334a45a8ff | 69 | */ |
bogdanm | 0:9b334a45a8ff | 70 | |
bogdanm | 0:9b334a45a8ff | 71 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
bogdanm | 0:9b334a45a8ff | 72 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
bogdanm | 0:9b334a45a8ff | 73 | defined(STM32F373xC) || defined(STM32F378xx) |
bogdanm | 0:9b334a45a8ff | 74 | /** @defgroup STM32F302xE_STM32F303xE_STM32F398xx_STM32F302xC_STM32F303xC_STM32F3058xx_STM32F373xC_STM32F378xx Product devices |
bogdanm | 0:9b334a45a8ff | 75 | * @{ |
bogdanm | 0:9b334a45a8ff | 76 | */ |
bogdanm | 0:9b334a45a8ff | 77 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
bogdanm | 0:9b334a45a8ff | 78 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
bogdanm | 0:9b334a45a8ff | 79 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
bogdanm | 0:9b334a45a8ff | 80 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
bogdanm | 0:9b334a45a8ff | 81 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
bogdanm | 0:9b334a45a8ff | 82 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
bogdanm | 0:9b334a45a8ff | 83 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
bogdanm | 0:9b334a45a8ff | 84 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ |
bogdanm | 0:9b334a45a8ff | 85 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ |
bogdanm | 0:9b334a45a8ff | 86 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ |
bogdanm | 0:9b334a45a8ff | 87 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ |
bogdanm | 0:9b334a45a8ff | 88 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ |
bogdanm | 0:9b334a45a8ff | 89 | DMA_FLAG_TC5) |
bogdanm | 0:9b334a45a8ff | 90 | |
bogdanm | 0:9b334a45a8ff | 91 | /** |
bogdanm | 0:9b334a45a8ff | 92 | * @brief Returns the current DMA Channel half transfer complete flag. |
bogdanm | 0:9b334a45a8ff | 93 | * @param __HANDLE__: DMA handle |
bogdanm | 0:9b334a45a8ff | 94 | * @retval The specified half transfer complete flag index. |
bogdanm | 0:9b334a45a8ff | 95 | */ |
bogdanm | 0:9b334a45a8ff | 96 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
bogdanm | 0:9b334a45a8ff | 97 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
bogdanm | 0:9b334a45a8ff | 98 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
bogdanm | 0:9b334a45a8ff | 99 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
bogdanm | 0:9b334a45a8ff | 100 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
bogdanm | 0:9b334a45a8ff | 101 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
bogdanm | 0:9b334a45a8ff | 102 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
bogdanm | 0:9b334a45a8ff | 103 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ |
bogdanm | 0:9b334a45a8ff | 104 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ |
bogdanm | 0:9b334a45a8ff | 105 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ |
bogdanm | 0:9b334a45a8ff | 106 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ |
bogdanm | 0:9b334a45a8ff | 107 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ |
bogdanm | 0:9b334a45a8ff | 108 | DMA_FLAG_HT5) |
bogdanm | 0:9b334a45a8ff | 109 | |
bogdanm | 0:9b334a45a8ff | 110 | /** |
bogdanm | 0:9b334a45a8ff | 111 | * @brief Returns the current DMA Channel transfer error flag. |
bogdanm | 0:9b334a45a8ff | 112 | * @param __HANDLE__: DMA handle |
bogdanm | 0:9b334a45a8ff | 113 | * @retval The specified transfer error flag index. |
bogdanm | 0:9b334a45a8ff | 114 | */ |
bogdanm | 0:9b334a45a8ff | 115 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
bogdanm | 0:9b334a45a8ff | 116 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
bogdanm | 0:9b334a45a8ff | 117 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
bogdanm | 0:9b334a45a8ff | 118 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
bogdanm | 0:9b334a45a8ff | 119 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
bogdanm | 0:9b334a45a8ff | 120 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
bogdanm | 0:9b334a45a8ff | 121 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
bogdanm | 0:9b334a45a8ff | 122 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ |
bogdanm | 0:9b334a45a8ff | 123 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ |
bogdanm | 0:9b334a45a8ff | 124 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ |
bogdanm | 0:9b334a45a8ff | 125 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ |
bogdanm | 0:9b334a45a8ff | 126 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ |
bogdanm | 0:9b334a45a8ff | 127 | DMA_FLAG_TE5) |
bogdanm | 0:9b334a45a8ff | 128 | |
bogdanm | 0:9b334a45a8ff | 129 | /** |
bogdanm | 0:9b334a45a8ff | 130 | * @brief Get the DMA Channel pending flags. |
bogdanm | 0:9b334a45a8ff | 131 | * @param __HANDLE__: DMA handle |
bogdanm | 0:9b334a45a8ff | 132 | * @param __FLAG__: Get the specified flag. |
bogdanm | 0:9b334a45a8ff | 133 | * This parameter can be any combination of the following values: |
bogdanm | 0:9b334a45a8ff | 134 | * @arg DMA_FLAG_TCx: Transfer complete flag |
bogdanm | 0:9b334a45a8ff | 135 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
bogdanm | 0:9b334a45a8ff | 136 | * @arg DMA_FLAG_TEx: Transfer error flag |
bogdanm | 0:9b334a45a8ff | 137 | * Where x can be 0, 1, 2, 3, 4, 5, 6 or 7 to select the DMA Channel flag. |
bogdanm | 0:9b334a45a8ff | 138 | * @retval The state of FLAG (SET or RESET). |
bogdanm | 0:9b334a45a8ff | 139 | */ |
bogdanm | 0:9b334a45a8ff | 140 | |
bogdanm | 0:9b334a45a8ff | 141 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
bogdanm | 0:9b334a45a8ff | 142 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ |
bogdanm | 0:9b334a45a8ff | 143 | (DMA1->ISR & (__FLAG__))) |
bogdanm | 0:9b334a45a8ff | 144 | |
bogdanm | 0:9b334a45a8ff | 145 | /** |
bogdanm | 0:9b334a45a8ff | 146 | * @brief Clears the DMA Channel pending flags. |
bogdanm | 0:9b334a45a8ff | 147 | * @param __HANDLE__: DMA handle |
bogdanm | 0:9b334a45a8ff | 148 | * @param __FLAG__: specifies the flag to clear. |
bogdanm | 0:9b334a45a8ff | 149 | * This parameter can be any combination of the following values: |
bogdanm | 0:9b334a45a8ff | 150 | * @arg DMA_FLAG_TCx: Transfer complete flag |
bogdanm | 0:9b334a45a8ff | 151 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
bogdanm | 0:9b334a45a8ff | 152 | * @arg DMA_FLAG_TEx: Transfer error flag |
bogdanm | 0:9b334a45a8ff | 153 | * Where x can be 0, 1, 2, 3, 4, 5, 6 or 7 to select the DMA Channel flag. |
bogdanm | 0:9b334a45a8ff | 154 | * @retval None |
bogdanm | 0:9b334a45a8ff | 155 | */ |
bogdanm | 0:9b334a45a8ff | 156 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
bogdanm | 0:9b334a45a8ff | 157 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ |
bogdanm | 0:9b334a45a8ff | 158 | (DMA1->IFCR = (__FLAG__))) |
bogdanm | 0:9b334a45a8ff | 159 | |
bogdanm | 0:9b334a45a8ff | 160 | /** |
bogdanm | 0:9b334a45a8ff | 161 | * @} |
bogdanm | 0:9b334a45a8ff | 162 | */ |
bogdanm | 0:9b334a45a8ff | 163 | |
bogdanm | 0:9b334a45a8ff | 164 | #else |
bogdanm | 0:9b334a45a8ff | 165 | |
bogdanm | 0:9b334a45a8ff | 166 | /** @defgroup STM32F301x8_STM32F302x8_STM32F318xx_STM32F303x8_STM32F334x8_STM32F328xx Product devices |
bogdanm | 0:9b334a45a8ff | 167 | * @{ |
bogdanm | 0:9b334a45a8ff | 168 | */ |
bogdanm | 0:9b334a45a8ff | 169 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
bogdanm | 0:9b334a45a8ff | 170 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
bogdanm | 0:9b334a45a8ff | 171 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
bogdanm | 0:9b334a45a8ff | 172 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
bogdanm | 0:9b334a45a8ff | 173 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
bogdanm | 0:9b334a45a8ff | 174 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
bogdanm | 0:9b334a45a8ff | 175 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
bogdanm | 0:9b334a45a8ff | 176 | DMA_FLAG_TC7) |
bogdanm | 0:9b334a45a8ff | 177 | |
bogdanm | 0:9b334a45a8ff | 178 | /** |
bogdanm | 0:9b334a45a8ff | 179 | * @brief Returns the current DMA Channel half transfer complete flag. |
bogdanm | 0:9b334a45a8ff | 180 | * @param __HANDLE__: DMA handle |
bogdanm | 0:9b334a45a8ff | 181 | * @retval The specified half transfer complete flag index. |
bogdanm | 0:9b334a45a8ff | 182 | */ |
bogdanm | 0:9b334a45a8ff | 183 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
bogdanm | 0:9b334a45a8ff | 184 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
bogdanm | 0:9b334a45a8ff | 185 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
bogdanm | 0:9b334a45a8ff | 186 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
bogdanm | 0:9b334a45a8ff | 187 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
bogdanm | 0:9b334a45a8ff | 188 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
bogdanm | 0:9b334a45a8ff | 189 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
bogdanm | 0:9b334a45a8ff | 190 | DMA_FLAG_HT7) |
bogdanm | 0:9b334a45a8ff | 191 | |
bogdanm | 0:9b334a45a8ff | 192 | /** |
bogdanm | 0:9b334a45a8ff | 193 | * @brief Returns the current DMA Channel transfer error flag. |
bogdanm | 0:9b334a45a8ff | 194 | * @param __HANDLE__: DMA handle |
bogdanm | 0:9b334a45a8ff | 195 | * @retval The specified transfer error flag index. |
bogdanm | 0:9b334a45a8ff | 196 | */ |
bogdanm | 0:9b334a45a8ff | 197 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
bogdanm | 0:9b334a45a8ff | 198 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
bogdanm | 0:9b334a45a8ff | 199 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
bogdanm | 0:9b334a45a8ff | 200 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
bogdanm | 0:9b334a45a8ff | 201 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
bogdanm | 0:9b334a45a8ff | 202 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
bogdanm | 0:9b334a45a8ff | 203 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
bogdanm | 0:9b334a45a8ff | 204 | DMA_FLAG_TE7) |
bogdanm | 0:9b334a45a8ff | 205 | |
bogdanm | 0:9b334a45a8ff | 206 | /** |
bogdanm | 0:9b334a45a8ff | 207 | * @brief Get the DMA Channel pending flags. |
bogdanm | 0:9b334a45a8ff | 208 | * @param __HANDLE__: DMA handle |
bogdanm | 0:9b334a45a8ff | 209 | * @param __FLAG__: Get the specified flag. |
bogdanm | 0:9b334a45a8ff | 210 | * This parameter can be any combination of the following values: |
bogdanm | 0:9b334a45a8ff | 211 | * @arg DMA_FLAG_TCx: Transfer complete flag |
bogdanm | 0:9b334a45a8ff | 212 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
bogdanm | 0:9b334a45a8ff | 213 | * @arg DMA_FLAG_TEx: Transfer error flag |
bogdanm | 0:9b334a45a8ff | 214 | * Where x can be 0, 1, 2, 3, 4, 5, 6 or 7 to select the DMA Channel flag. |
bogdanm | 0:9b334a45a8ff | 215 | * @retval The state of FLAG (SET or RESET). |
bogdanm | 0:9b334a45a8ff | 216 | */ |
bogdanm | 0:9b334a45a8ff | 217 | |
bogdanm | 0:9b334a45a8ff | 218 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
bogdanm | 0:9b334a45a8ff | 219 | |
bogdanm | 0:9b334a45a8ff | 220 | /** |
bogdanm | 0:9b334a45a8ff | 221 | * @brief Clears the DMA Channel pending flags. |
bogdanm | 0:9b334a45a8ff | 222 | * @param __HANDLE__: DMA handle |
bogdanm | 0:9b334a45a8ff | 223 | * @param __FLAG__: specifies the flag to clear. |
bogdanm | 0:9b334a45a8ff | 224 | * This parameter can be any combination of the following values: |
bogdanm | 0:9b334a45a8ff | 225 | * @arg DMA_FLAG_TCx: Transfer complete flag |
bogdanm | 0:9b334a45a8ff | 226 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
bogdanm | 0:9b334a45a8ff | 227 | * @arg DMA_FLAG_TEx: Transfer error flag |
bogdanm | 0:9b334a45a8ff | 228 | * Where x can be 0, 1, 2, 3, 4, 5, 6 or 7 to select the DMA Channel flag. |
bogdanm | 0:9b334a45a8ff | 229 | * @retval None |
bogdanm | 0:9b334a45a8ff | 230 | */ |
bogdanm | 0:9b334a45a8ff | 231 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__)) |
bogdanm | 0:9b334a45a8ff | 232 | |
bogdanm | 0:9b334a45a8ff | 233 | /** |
bogdanm | 0:9b334a45a8ff | 234 | * @} |
bogdanm | 0:9b334a45a8ff | 235 | */ |
bogdanm | 0:9b334a45a8ff | 236 | |
bogdanm | 0:9b334a45a8ff | 237 | #endif |
bogdanm | 0:9b334a45a8ff | 238 | |
bogdanm | 0:9b334a45a8ff | 239 | /** |
bogdanm | 0:9b334a45a8ff | 240 | * @} |
bogdanm | 0:9b334a45a8ff | 241 | */ |
bogdanm | 0:9b334a45a8ff | 242 | |
bogdanm | 0:9b334a45a8ff | 243 | /** |
bogdanm | 0:9b334a45a8ff | 244 | * @} |
bogdanm | 0:9b334a45a8ff | 245 | */ |
bogdanm | 0:9b334a45a8ff | 246 | |
bogdanm | 0:9b334a45a8ff | 247 | /** |
bogdanm | 0:9b334a45a8ff | 248 | * @} |
bogdanm | 0:9b334a45a8ff | 249 | */ |
bogdanm | 0:9b334a45a8ff | 250 | |
bogdanm | 0:9b334a45a8ff | 251 | #ifdef __cplusplus |
bogdanm | 0:9b334a45a8ff | 252 | } |
bogdanm | 0:9b334a45a8ff | 253 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
bogdanm | 0:9b334a45a8ff | 254 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
bogdanm | 0:9b334a45a8ff | 255 | /* STM32F373xC || STM32F378xx */ |
bogdanm | 0:9b334a45a8ff | 256 | |
bogdanm | 0:9b334a45a8ff | 257 | #endif /* __STM32F3xx_HAL_DMA_H */ |
bogdanm | 0:9b334a45a8ff | 258 | |
bogdanm | 0:9b334a45a8ff | 259 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |