en 129
fix LPC812 PWM
Fork of
mbed-dev
by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f3xx_hal.h |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.1.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 12-Sept-2014 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief This file contains all the functions prototypes for the HAL |
| bogdanm | 0:9b334a45a8ff | 8 | * module driver. |
| bogdanm | 0:9b334a45a8ff | 9 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 10 | * @attention |
| bogdanm | 0:9b334a45a8ff | 11 | * |
| bogdanm | 0:9b334a45a8ff | 12 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 13 | * |
| bogdanm | 0:9b334a45a8ff | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 15 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 17 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 19 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 20 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 22 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 23 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 24 | * |
| bogdanm | 0:9b334a45a8ff | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 35 | * |
| bogdanm | 0:9b334a45a8ff | 36 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 37 | */ |
| bogdanm | 0:9b334a45a8ff | 38 | |
| bogdanm | 0:9b334a45a8ff | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 40 | #ifndef __STM32F3xx_HAL_H |
| bogdanm | 0:9b334a45a8ff | 41 | #define __STM32F3xx_HAL_H |
| bogdanm | 0:9b334a45a8ff | 42 | |
| bogdanm | 0:9b334a45a8ff | 43 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 44 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 45 | #endif |
| bogdanm | 0:9b334a45a8ff | 46 | |
| bogdanm | 0:9b334a45a8ff | 47 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 48 | #include "stm32f3xx_hal_conf.h" |
| bogdanm | 0:9b334a45a8ff | 49 | |
| bogdanm | 0:9b334a45a8ff | 50 | /** @addtogroup STM32F3xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 51 | * @{ |
| bogdanm | 0:9b334a45a8ff | 52 | */ |
| bogdanm | 0:9b334a45a8ff | 53 | |
| bogdanm | 0:9b334a45a8ff | 54 | /** @addtogroup HAL |
| bogdanm | 0:9b334a45a8ff | 55 | * @{ |
| bogdanm | 0:9b334a45a8ff | 56 | */ |
| bogdanm | 0:9b334a45a8ff | 57 | |
| bogdanm | 0:9b334a45a8ff | 58 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 59 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 60 | /** @defgroup HAL_Exported_Constants HAL Exported Constants |
| bogdanm | 0:9b334a45a8ff | 61 | * @{ |
| bogdanm | 0:9b334a45a8ff | 62 | */ |
| bogdanm | 0:9b334a45a8ff | 63 | /** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region |
| bogdanm | 0:9b334a45a8ff | 64 | * @brief SYSCFG registers bit address in the alias region |
| bogdanm | 0:9b334a45a8ff | 65 | * @{ |
| bogdanm | 0:9b334a45a8ff | 66 | */ |
| bogdanm | 0:9b334a45a8ff | 67 | /* ------------ SYSCFG registers bit address in the alias region -------------*/ |
| bogdanm | 0:9b334a45a8ff | 68 | #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) |
| bogdanm | 0:9b334a45a8ff | 69 | /* --- CFGR2 Register ---*/ |
| bogdanm | 0:9b334a45a8ff | 70 | /* Alias word address of BYP_ADDR_PAR bit */ |
| bogdanm | 0:9b334a45a8ff | 71 | #define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18) |
| bogdanm | 0:9b334a45a8ff | 72 | #define BYPADDRPAR_BitNumber 0x04 |
| bogdanm | 0:9b334a45a8ff | 73 | #define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4)) |
| bogdanm | 0:9b334a45a8ff | 74 | /** |
| bogdanm | 0:9b334a45a8ff | 75 | * @} |
| bogdanm | 0:9b334a45a8ff | 76 | */ |
| bogdanm | 0:9b334a45a8ff | 77 | |
| bogdanm | 0:9b334a45a8ff | 78 | #if defined(SYSCFG_CFGR1_DMA_RMP) |
| bogdanm | 0:9b334a45a8ff | 79 | /** @defgroup HAL_DMA_Remapping DMA Remapping |
| bogdanm | 0:9b334a45a8ff | 80 | * Elements values convention: 0xXXYYYYYY |
| bogdanm | 0:9b334a45a8ff | 81 | * - YYYYYY : Position in the register |
| bogdanm | 0:9b334a45a8ff | 82 | * - XX : Register index |
| bogdanm | 0:9b334a45a8ff | 83 | * - 00: CFGR1 register in SYSCFG |
| bogdanm | 0:9b334a45a8ff | 84 | * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices) |
| bogdanm | 0:9b334a45a8ff | 85 | * @{ |
| bogdanm | 0:9b334a45a8ff | 86 | */ |
| bogdanm | 0:9b334a45a8ff | 87 | #define HAL_REMAPDMA_ADC24_DMA2_CH34 ((uint32_t)0x00000100) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) |
| bogdanm | 0:9b334a45a8ff | 88 | 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */ |
| bogdanm | 0:9b334a45a8ff | 89 | #define HAL_REMAPDMA_TIM16_DMA1_CH6 ((uint32_t)0x00000800) /*!< TIM16 DMA request remap |
| bogdanm | 0:9b334a45a8ff | 90 | 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */ |
| bogdanm | 0:9b334a45a8ff | 91 | #define HAL_REMAPDMA_TIM17_DMA1_CH7 ((uint32_t)0x00001000) /*!< TIM17 DMA request remap |
| bogdanm | 0:9b334a45a8ff | 92 | 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */ |
| bogdanm | 0:9b334a45a8ff | 93 | #define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 ((uint32_t)0x00002000) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) |
| bogdanm | 0:9b334a45a8ff | 94 | 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */ |
| bogdanm | 0:9b334a45a8ff | 95 | #define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 ((uint32_t)0x00004000) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) |
| bogdanm | 0:9b334a45a8ff | 96 | 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */ |
| bogdanm | 0:9b334a45a8ff | 97 | #define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 98 | 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */ |
| bogdanm | 0:9b334a45a8ff | 99 | #define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 100 | 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */ |
| bogdanm | 0:9b334a45a8ff | 101 | #if defined(SYSCFG_CFGR3_DMA_RMP) |
| bogdanm | 0:9b334a45a8ff | 102 | #if !defined(HAL_REMAP_CFGR3_MASK) |
| bogdanm | 0:9b334a45a8ff | 103 | #define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000) |
| bogdanm | 0:9b334a45a8ff | 104 | #endif |
| bogdanm | 0:9b334a45a8ff | 105 | |
| bogdanm | 0:9b334a45a8ff | 106 | #define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 ((uint32_t)0x01000003) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 107 | 11: Map on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 108 | #define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 ((uint32_t)0x01000001) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 109 | 01: Map on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 110 | #define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 ((uint32_t)0x01000002) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 111 | 10: Map on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 112 | #define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 ((uint32_t)0x0100000C) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 113 | 11: Map on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 114 | #define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 ((uint32_t)0x01000004) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 115 | 01: Map on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 116 | #define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 ((uint32_t)0x01000008) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 117 | 10: Map on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 118 | #define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 ((uint32_t)0x01000030) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 119 | 11: Map on DMA1 channel 7 */ |
| bogdanm | 0:9b334a45a8ff | 120 | #define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 ((uint32_t)0x01000010) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 121 | 01: Map on DMA1 channel 3 */ |
| bogdanm | 0:9b334a45a8ff | 122 | #define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 ((uint32_t)0x01000020) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 123 | 10: Map on DMA1 channel 5 */ |
| bogdanm | 0:9b334a45a8ff | 124 | #define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 ((uint32_t)0x010000C0) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 125 | 11: Map on DMA1 channel 6 */ |
| bogdanm | 0:9b334a45a8ff | 126 | #define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 ((uint32_t)0x01000040) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 127 | 01: Map on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 128 | #define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 ((uint32_t)0x01000080) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only) |
| bogdanm | 0:9b334a45a8ff | 129 | 10: Map on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 130 | #define HAL_REMAPDMA_ADC2_DMA1_CH2 ((uint32_t)0x01000100) /*!< ADC2 DMA remap |
| bogdanm | 0:9b334a45a8ff | 131 | x0: No remap (ADC2 on DMA2) |
| bogdanm | 0:9b334a45a8ff | 132 | 10: Map on DMA1 channel 2 */ |
| bogdanm | 0:9b334a45a8ff | 133 | #define HAL_REMAPDMA_ADC2_DMA1_CH4 ((uint32_t)0x01000300) /*!< ADC2 DMA remap |
| bogdanm | 0:9b334a45a8ff | 134 | 11: Map on DMA1 channel 4 */ |
| bogdanm | 0:9b334a45a8ff | 135 | #endif /* SYSCFG_CFGR3_DMA_RMP */ |
| bogdanm | 0:9b334a45a8ff | 136 | |
| bogdanm | 0:9b334a45a8ff | 137 | #if defined(SYSCFG_CFGR3_DMA_RMP) |
| bogdanm | 0:9b334a45a8ff | 138 | #define IS_HAL_REMAPDMA(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \ |
| bogdanm | 0:9b334a45a8ff | 139 | (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \ |
| bogdanm | 0:9b334a45a8ff | 140 | (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \ |
| bogdanm | 0:9b334a45a8ff | 141 | (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \ |
| bogdanm | 0:9b334a45a8ff | 142 | (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \ |
| bogdanm | 0:9b334a45a8ff | 143 | (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \ |
| bogdanm | 0:9b334a45a8ff | 144 | (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \ |
| bogdanm | 0:9b334a45a8ff | 145 | (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \ |
| bogdanm | 0:9b334a45a8ff | 146 | (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \ |
| bogdanm | 0:9b334a45a8ff | 147 | (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \ |
| bogdanm | 0:9b334a45a8ff | 148 | (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \ |
| bogdanm | 0:9b334a45a8ff | 149 | (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \ |
| bogdanm | 0:9b334a45a8ff | 150 | (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \ |
| bogdanm | 0:9b334a45a8ff | 151 | (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \ |
| bogdanm | 0:9b334a45a8ff | 152 | (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \ |
| bogdanm | 0:9b334a45a8ff | 153 | (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \ |
| bogdanm | 0:9b334a45a8ff | 154 | (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \ |
| bogdanm | 0:9b334a45a8ff | 155 | (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \ |
| bogdanm | 0:9b334a45a8ff | 156 | (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \ |
| bogdanm | 0:9b334a45a8ff | 157 | (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \ |
| bogdanm | 0:9b334a45a8ff | 158 | (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4)) |
| bogdanm | 0:9b334a45a8ff | 159 | #else |
| bogdanm | 0:9b334a45a8ff | 160 | #define IS_HAL_REMAPDMA(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \ |
| bogdanm | 0:9b334a45a8ff | 161 | (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \ |
| bogdanm | 0:9b334a45a8ff | 162 | (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \ |
| bogdanm | 0:9b334a45a8ff | 163 | (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \ |
| bogdanm | 0:9b334a45a8ff | 164 | (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \ |
| bogdanm | 0:9b334a45a8ff | 165 | (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \ |
| bogdanm | 0:9b334a45a8ff | 166 | (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5)) |
| bogdanm | 0:9b334a45a8ff | 167 | #endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/ |
| bogdanm | 0:9b334a45a8ff | 168 | /** |
| bogdanm | 0:9b334a45a8ff | 169 | * @} |
| bogdanm | 0:9b334a45a8ff | 170 | */ |
| bogdanm | 0:9b334a45a8ff | 171 | #endif /* SYSCFG_CFGR1_DMA_RMP */ |
| bogdanm | 0:9b334a45a8ff | 172 | |
| bogdanm | 0:9b334a45a8ff | 173 | /** @defgroup HAL_Trigger_Remapping Trigger Remapping |
| bogdanm | 0:9b334a45a8ff | 174 | * Elements values convention: 0xXXYYYYYY |
| bogdanm | 0:9b334a45a8ff | 175 | * - YYYYYY : Position in the register |
| bogdanm | 0:9b334a45a8ff | 176 | * - XX : Register index |
| bogdanm | 0:9b334a45a8ff | 177 | * - 00: CFGR1 register in SYSCFG |
| bogdanm | 0:9b334a45a8ff | 178 | * - 01: CFGR3 register in SYSCFG |
| bogdanm | 0:9b334a45a8ff | 179 | * @{ |
| bogdanm | 0:9b334a45a8ff | 180 | */ |
| bogdanm | 0:9b334a45a8ff | 181 | #define HAL_REMAPTRIGGER_DAC1_TRIG ((uint32_t)0x00000080) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices) |
| bogdanm | 0:9b334a45a8ff | 182 | 0: No remap (DAC trigger is TIM8_TRGO) |
| bogdanm | 0:9b334a45a8ff | 183 | 1: Remap (DAC trigger is TIM3_TRGO) */ |
| bogdanm | 0:9b334a45a8ff | 184 | #define HAL_REMAPTRIGGER_TIM1_ITR3 ((uint32_t)0x00000040) /*!< TIM1 ITR3 trigger remap |
| bogdanm | 0:9b334a45a8ff | 185 | 0: No remap |
| bogdanm | 0:9b334a45a8ff | 186 | 1: Remap (TIM1_TRG3 = TIM17_OC) */ |
| bogdanm | 0:9b334a45a8ff | 187 | #if defined(SYSCFG_CFGR3_TRIGGER_RMP) |
| bogdanm | 0:9b334a45a8ff | 188 | #if !defined(HAL_REMAP_CFGR3_MASK) |
| bogdanm | 0:9b334a45a8ff | 189 | #define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000) |
| bogdanm | 0:9b334a45a8ff | 190 | #endif |
| bogdanm | 0:9b334a45a8ff | 191 | #define HAL_REMAPTRIGGER_DAC1_TRIG3 ((uint32_t)0x01010000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap |
| bogdanm | 0:9b334a45a8ff | 192 | 0: Remap (DAC trigger is TIM15_TRGO) |
| bogdanm | 0:9b334a45a8ff | 193 | 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */ |
| bogdanm | 0:9b334a45a8ff | 194 | #define HAL_REMAPTRIGGER_DAC1_TRIG5 ((uint32_t)0x01020000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap |
| bogdanm | 0:9b334a45a8ff | 195 | 0: No remap |
| bogdanm | 0:9b334a45a8ff | 196 | 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */ |
| bogdanm | 0:9b334a45a8ff | 197 | #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \ |
| bogdanm | 0:9b334a45a8ff | 198 | (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \ |
| bogdanm | 0:9b334a45a8ff | 199 | (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \ |
| bogdanm | 0:9b334a45a8ff | 200 | (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5)) |
| bogdanm | 0:9b334a45a8ff | 201 | #else |
| bogdanm | 0:9b334a45a8ff | 202 | #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \ |
| bogdanm | 0:9b334a45a8ff | 203 | (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3)) |
| bogdanm | 0:9b334a45a8ff | 204 | #endif /* SYSCFG_CFGR3_TRIGGER_RMP */ |
| bogdanm | 0:9b334a45a8ff | 205 | /** |
| bogdanm | 0:9b334a45a8ff | 206 | * @} |
| bogdanm | 0:9b334a45a8ff | 207 | */ |
| bogdanm | 0:9b334a45a8ff | 208 | |
| bogdanm | 0:9b334a45a8ff | 209 | #if defined (STM32F303xE) || defined (STM32F398xx) |
| bogdanm | 0:9b334a45a8ff | 210 | /** @defgroup HAL_ADC_Trigger_Remapping ADC Trigger Remapping |
| bogdanm | 0:9b334a45a8ff | 211 | * @{ |
| bogdanm | 0:9b334a45a8ff | 212 | */ |
| bogdanm | 0:9b334a45a8ff | 213 | #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2 |
| bogdanm | 0:9b334a45a8ff | 214 | 0: No remap (TIM1_CC3) |
| bogdanm | 0:9b334a45a8ff | 215 | 1: Remap (TIM20_TRGO) */ |
| bogdanm | 0:9b334a45a8ff | 216 | #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3 |
| bogdanm | 0:9b334a45a8ff | 217 | 0: No remap (TIM2_CC2) |
| bogdanm | 0:9b334a45a8ff | 218 | 1: Remap (TIM20_TRGO2) */ |
| bogdanm | 0:9b334a45a8ff | 219 | #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5 |
| bogdanm | 0:9b334a45a8ff | 220 | 0: No remap (TIM4_CC4) |
| bogdanm | 0:9b334a45a8ff | 221 | 1: Remap (TIM20_CC1) */ |
| bogdanm | 0:9b334a45a8ff | 222 | #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13 |
| bogdanm | 0:9b334a45a8ff | 223 | 0: No remap (TIM6_TRGO) |
| bogdanm | 0:9b334a45a8ff | 224 | 1: Remap (TIM20_CC2) */ |
| bogdanm | 0:9b334a45a8ff | 225 | #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15 |
| bogdanm | 0:9b334a45a8ff | 226 | 0: No remap (TIM3_CC4) |
| bogdanm | 0:9b334a45a8ff | 227 | 1: Remap (TIM20_CC3) */ |
| bogdanm | 0:9b334a45a8ff | 228 | #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3 |
| bogdanm | 0:9b334a45a8ff | 229 | 0: No remap (TIM2_CC1) |
| bogdanm | 0:9b334a45a8ff | 230 | 1: Remap (TIM20_TRGO) */ |
| bogdanm | 0:9b334a45a8ff | 231 | #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6 |
| bogdanm | 0:9b334a45a8ff | 232 | 0: No remap (EXTI line 15) |
| bogdanm | 0:9b334a45a8ff | 233 | 1: Remap (TIM20_TRGO2) */ |
| bogdanm | 0:9b334a45a8ff | 234 | #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13 |
| bogdanm | 0:9b334a45a8ff | 235 | 0: No remap (TIM3_CC1) |
| bogdanm | 0:9b334a45a8ff | 236 | 1: Remap (TIM20_CC4) */ |
| bogdanm | 0:9b334a45a8ff | 237 | #define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5 |
| bogdanm | 0:9b334a45a8ff | 238 | 0: No remap (EXTI line 2) |
| bogdanm | 0:9b334a45a8ff | 239 | 1: Remap (TIM20_TRGO) */ |
| bogdanm | 0:9b334a45a8ff | 240 | #define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6 |
| bogdanm | 0:9b334a45a8ff | 241 | 0: No remap (TIM4_CC1) |
| bogdanm | 0:9b334a45a8ff | 242 | 1: Remap (TIM20_TRGO2) */ |
| bogdanm | 0:9b334a45a8ff | 243 | #define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15 |
| bogdanm | 0:9b334a45a8ff | 244 | 0: No remap (TIM2_CC1) |
| bogdanm | 0:9b334a45a8ff | 245 | 1: Remap (TIM20_CC1) */ |
| bogdanm | 0:9b334a45a8ff | 246 | #define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5 |
| bogdanm | 0:9b334a45a8ff | 247 | 0: No remap (TIM4_CC3) |
| bogdanm | 0:9b334a45a8ff | 248 | 1: Remap (TIM20_TRGO) */ |
| bogdanm | 0:9b334a45a8ff | 249 | #define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11 |
| bogdanm | 0:9b334a45a8ff | 250 | 0: No remap (TIM1_CC3) |
| bogdanm | 0:9b334a45a8ff | 251 | 1: Remap (TIM20_TRGO2) */ |
| bogdanm | 0:9b334a45a8ff | 252 | #define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14 |
| bogdanm | 0:9b334a45a8ff | 253 | 0: No remap (TIM7_TRGO) |
| bogdanm | 0:9b334a45a8ff | 254 | 1: Remap (TIM20_CC2) */ |
| bogdanm | 0:9b334a45a8ff | 255 | |
| bogdanm | 0:9b334a45a8ff | 256 | #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \ |
| bogdanm | 0:9b334a45a8ff | 257 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \ |
| bogdanm | 0:9b334a45a8ff | 258 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \ |
| bogdanm | 0:9b334a45a8ff | 259 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \ |
| bogdanm | 0:9b334a45a8ff | 260 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \ |
| bogdanm | 0:9b334a45a8ff | 261 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \ |
| bogdanm | 0:9b334a45a8ff | 262 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \ |
| bogdanm | 0:9b334a45a8ff | 263 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \ |
| bogdanm | 0:9b334a45a8ff | 264 | (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \ |
| bogdanm | 0:9b334a45a8ff | 265 | (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \ |
| bogdanm | 0:9b334a45a8ff | 266 | (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \ |
| bogdanm | 0:9b334a45a8ff | 267 | (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \ |
| bogdanm | 0:9b334a45a8ff | 268 | (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \ |
| bogdanm | 0:9b334a45a8ff | 269 | (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14)) |
| bogdanm | 0:9b334a45a8ff | 270 | /** |
| bogdanm | 0:9b334a45a8ff | 271 | * @} |
| bogdanm | 0:9b334a45a8ff | 272 | */ |
| bogdanm | 0:9b334a45a8ff | 273 | #endif /* STM32F303xE || STM32F398xx */ |
| bogdanm | 0:9b334a45a8ff | 274 | |
| bogdanm | 0:9b334a45a8ff | 275 | /** @defgroup HAL_FastModePlus_I2C I2C Fast Mode Plus |
| bogdanm | 0:9b334a45a8ff | 276 | * @{ |
| bogdanm | 0:9b334a45a8ff | 277 | */ |
| bogdanm | 0:9b334a45a8ff | 278 | #if defined(SYSCFG_CFGR1_I2C1_FMP) |
| bogdanm | 0:9b334a45a8ff | 279 | #define HAL_SYSCFG_FASTMODEPLUS_I2C1 ((uint32_t)SYSCFG_CFGR1_I2C1_FMP) /*!< I2C1 fast mode Plus driving capability activation |
| bogdanm | 0:9b334a45a8ff | 280 | 0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits |
| bogdanm | 0:9b334a45a8ff | 281 | 1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */ |
| bogdanm | 0:9b334a45a8ff | 282 | #endif /* SYSCFG_CFGR1_I2C1_FMP */ |
| bogdanm | 0:9b334a45a8ff | 283 | |
| bogdanm | 0:9b334a45a8ff | 284 | #if defined(SYSCFG_CFGR1_I2C2_FMP) |
| bogdanm | 0:9b334a45a8ff | 285 | #define HAL_SYSCFG_FASTMODEPLUS_I2C2 ((uint32_t)SYSCFG_CFGR1_I2C2_FMP) /*!< I2C2 fast mode Plus driving capability activation |
| bogdanm | 0:9b334a45a8ff | 286 | 0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits |
| bogdanm | 0:9b334a45a8ff | 287 | 1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */ |
| bogdanm | 0:9b334a45a8ff | 288 | #endif /* SYSCFG_CFGR1_I2C2_FMP */ |
| bogdanm | 0:9b334a45a8ff | 289 | |
| bogdanm | 0:9b334a45a8ff | 290 | #if defined(SYSCFG_CFGR1_I2C3_FMP) |
| bogdanm | 0:9b334a45a8ff | 291 | #define HAL_SYSCFG_FASTMODEPLUS_I2C3 ((uint32_t)SYSCFG_CFGR1_I2C3_FMP) /*!< I2C3 fast mode Plus driving capability activation |
| bogdanm | 0:9b334a45a8ff | 292 | 0: FM+ mode is not enabled on I2C3 pins selected through AF selection bits |
| bogdanm | 0:9b334a45a8ff | 293 | 1: FM+ mode is enabled on I2C3 pins selected through AF selection bits */ |
| bogdanm | 0:9b334a45a8ff | 294 | #endif /* SYSCFG_CFGR1_I2C3_FMP */ |
| bogdanm | 0:9b334a45a8ff | 295 | |
| bogdanm | 0:9b334a45a8ff | 296 | #if defined(SYSCFG_CFGR1_I2C_PB6_FMP) |
| bogdanm | 0:9b334a45a8ff | 297 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| bogdanm | 0:9b334a45a8ff | 298 | 0: PB6 pin operates in standard mode |
| bogdanm | 0:9b334a45a8ff | 299 | 1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */ |
| bogdanm | 0:9b334a45a8ff | 300 | #endif /* SYSCFG_CFGR1_I2C_PB6_FMP */ |
| bogdanm | 0:9b334a45a8ff | 301 | |
| bogdanm | 0:9b334a45a8ff | 302 | #if defined(SYSCFG_CFGR1_I2C_PB7_FMP) |
| bogdanm | 0:9b334a45a8ff | 303 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| bogdanm | 0:9b334a45a8ff | 304 | 0: PB7 pin operates in standard mode |
| bogdanm | 0:9b334a45a8ff | 305 | 1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */ |
| bogdanm | 0:9b334a45a8ff | 306 | #endif /* SYSCFG_CFGR1_I2C_PB7_FMP */ |
| bogdanm | 0:9b334a45a8ff | 307 | |
| bogdanm | 0:9b334a45a8ff | 308 | #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) |
| bogdanm | 0:9b334a45a8ff | 309 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| bogdanm | 0:9b334a45a8ff | 310 | 0: PB8 pin operates in standard mode |
| bogdanm | 0:9b334a45a8ff | 311 | 1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */ |
| bogdanm | 0:9b334a45a8ff | 312 | #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ |
| bogdanm | 0:9b334a45a8ff | 313 | |
| bogdanm | 0:9b334a45a8ff | 314 | #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) |
| bogdanm | 0:9b334a45a8ff | 315 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| bogdanm | 0:9b334a45a8ff | 316 | 0: PB9 pin operates in standard mode |
| bogdanm | 0:9b334a45a8ff | 317 | 1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */ |
| bogdanm | 0:9b334a45a8ff | 318 | #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ |
| bogdanm | 0:9b334a45a8ff | 319 | |
| bogdanm | 0:9b334a45a8ff | 320 | #if defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP) && defined(SYSCFG_CFGR1_I2C3_FMP) |
| bogdanm | 0:9b334a45a8ff | 321 | #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ |
| bogdanm | 0:9b334a45a8ff | 322 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C2) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \ |
| bogdanm | 0:9b334a45a8ff | 323 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C3) == HAL_SYSCFG_FASTMODEPLUS_I2C3) || \ |
| bogdanm | 0:9b334a45a8ff | 324 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ |
| bogdanm | 0:9b334a45a8ff | 325 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ |
| bogdanm | 0:9b334a45a8ff | 326 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ |
| bogdanm | 0:9b334a45a8ff | 327 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) |
| bogdanm | 0:9b334a45a8ff | 328 | #elif defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP) |
| bogdanm | 0:9b334a45a8ff | 329 | #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ |
| bogdanm | 0:9b334a45a8ff | 330 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C2) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \ |
| bogdanm | 0:9b334a45a8ff | 331 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ |
| bogdanm | 0:9b334a45a8ff | 332 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ |
| bogdanm | 0:9b334a45a8ff | 333 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ |
| bogdanm | 0:9b334a45a8ff | 334 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) |
| bogdanm | 0:9b334a45a8ff | 335 | #elif defined(SYSCFG_CFGR1_I2C1_FMP) |
| bogdanm | 0:9b334a45a8ff | 336 | #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ |
| bogdanm | 0:9b334a45a8ff | 337 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ |
| bogdanm | 0:9b334a45a8ff | 338 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ |
| bogdanm | 0:9b334a45a8ff | 339 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ |
| bogdanm | 0:9b334a45a8ff | 340 | (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) |
| bogdanm | 0:9b334a45a8ff | 341 | #endif /* SYSCFG_CFGR1_I2C1_FMP && SYSCFG_CFGR1_I2C2_FMP && SYSCFG_CFGR3_I2C1_FMP */ |
| bogdanm | 0:9b334a45a8ff | 342 | /** |
| bogdanm | 0:9b334a45a8ff | 343 | * @} |
| bogdanm | 0:9b334a45a8ff | 344 | */ |
| bogdanm | 0:9b334a45a8ff | 345 | |
| bogdanm | 0:9b334a45a8ff | 346 | #if defined(SYSCFG_RCR_PAGE0) |
| bogdanm | 0:9b334a45a8ff | 347 | /* CCM-SRAM defined */ |
| bogdanm | 0:9b334a45a8ff | 348 | /** @defgroup HAL_Page_Write_Protection CCM RAM page write protection |
| bogdanm | 0:9b334a45a8ff | 349 | * @{ |
| bogdanm | 0:9b334a45a8ff | 350 | */ |
| bogdanm | 0:9b334a45a8ff | 351 | #define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */ |
| bogdanm | 0:9b334a45a8ff | 352 | #define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */ |
| bogdanm | 0:9b334a45a8ff | 353 | #define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */ |
| bogdanm | 0:9b334a45a8ff | 354 | #define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */ |
| bogdanm | 0:9b334a45a8ff | 355 | #if defined(SYSCFG_RCR_PAGE4) |
| bogdanm | 0:9b334a45a8ff | 356 | /* More than 4KB CCM-SRAM defined */ |
| bogdanm | 0:9b334a45a8ff | 357 | #define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */ |
| bogdanm | 0:9b334a45a8ff | 358 | #define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */ |
| bogdanm | 0:9b334a45a8ff | 359 | #define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */ |
| bogdanm | 0:9b334a45a8ff | 360 | #define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */ |
| bogdanm | 0:9b334a45a8ff | 361 | #endif /* SYSCFG_RCR_PAGE4 */ |
| bogdanm | 0:9b334a45a8ff | 362 | #if defined(SYSCFG_RCR_PAGE8) |
| bogdanm | 0:9b334a45a8ff | 363 | #define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */ |
| bogdanm | 0:9b334a45a8ff | 364 | #define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */ |
| bogdanm | 0:9b334a45a8ff | 365 | #define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */ |
| bogdanm | 0:9b334a45a8ff | 366 | #define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */ |
| bogdanm | 0:9b334a45a8ff | 367 | #define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */ |
| bogdanm | 0:9b334a45a8ff | 368 | #define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */ |
| bogdanm | 0:9b334a45a8ff | 369 | #define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */ |
| bogdanm | 0:9b334a45a8ff | 370 | #define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */ |
| bogdanm | 0:9b334a45a8ff | 371 | #endif /* SYSCFG_RCR_PAGE8 */ |
| bogdanm | 0:9b334a45a8ff | 372 | |
| bogdanm | 0:9b334a45a8ff | 373 | #if defined(SYSCFG_RCR_PAGE8) |
| bogdanm | 0:9b334a45a8ff | 374 | #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0xFFFF)) |
| bogdanm | 0:9b334a45a8ff | 375 | #elif defined(SYSCFG_RCR_PAGE4) |
| bogdanm | 0:9b334a45a8ff | 376 | #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0x00FF)) |
| bogdanm | 0:9b334a45a8ff | 377 | #else |
| bogdanm | 0:9b334a45a8ff | 378 | #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0x000F)) |
| bogdanm | 0:9b334a45a8ff | 379 | #endif /* SYSCFG_RCR_PAGE8 */ |
| bogdanm | 0:9b334a45a8ff | 380 | /** |
| bogdanm | 0:9b334a45a8ff | 381 | * @} |
| bogdanm | 0:9b334a45a8ff | 382 | */ |
| bogdanm | 0:9b334a45a8ff | 383 | #endif /* SYSCFG_RCR_PAGE0 */ |
| bogdanm | 0:9b334a45a8ff | 384 | |
| bogdanm | 0:9b334a45a8ff | 385 | /** @defgroup HAL_SYSCFG_Interrupts SYSCFG Interrupts |
| bogdanm | 0:9b334a45a8ff | 386 | * @{ |
| bogdanm | 0:9b334a45a8ff | 387 | */ |
| bogdanm | 0:9b334a45a8ff | 388 | #define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 389 | #define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 390 | #define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 391 | #define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 392 | #define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 393 | #define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 394 | |
| bogdanm | 0:9b334a45a8ff | 395 | #define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \ |
| bogdanm | 0:9b334a45a8ff | 396 | (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \ |
| bogdanm | 0:9b334a45a8ff | 397 | (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \ |
| bogdanm | 0:9b334a45a8ff | 398 | (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \ |
| bogdanm | 0:9b334a45a8ff | 399 | (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \ |
| bogdanm | 0:9b334a45a8ff | 400 | (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5)) |
| bogdanm | 0:9b334a45a8ff | 401 | |
| bogdanm | 0:9b334a45a8ff | 402 | /** |
| bogdanm | 0:9b334a45a8ff | 403 | * @} |
| bogdanm | 0:9b334a45a8ff | 404 | */ |
| bogdanm | 0:9b334a45a8ff | 405 | |
| bogdanm | 0:9b334a45a8ff | 406 | /** |
| bogdanm | 0:9b334a45a8ff | 407 | * @} |
| bogdanm | 0:9b334a45a8ff | 408 | */ |
| bogdanm | 0:9b334a45a8ff | 409 | |
| bogdanm | 0:9b334a45a8ff | 410 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 411 | /** @defgroup HAL_Exported_Macros HAL Exported Macros |
| bogdanm | 0:9b334a45a8ff | 412 | * @{ |
| bogdanm | 0:9b334a45a8ff | 413 | */ |
| bogdanm | 0:9b334a45a8ff | 414 | |
| bogdanm | 0:9b334a45a8ff | 415 | /** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode |
| bogdanm | 0:9b334a45a8ff | 416 | * @{ |
| bogdanm | 0:9b334a45a8ff | 417 | */ |
| bogdanm | 0:9b334a45a8ff | 418 | #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
| bogdanm | 0:9b334a45a8ff | 419 | #define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
| bogdanm | 0:9b334a45a8ff | 420 | #define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
| bogdanm | 0:9b334a45a8ff | 421 | #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ |
| bogdanm | 0:9b334a45a8ff | 422 | |
| bogdanm | 0:9b334a45a8ff | 423 | #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
| bogdanm | 0:9b334a45a8ff | 424 | #define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
| bogdanm | 0:9b334a45a8ff | 425 | #define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
| bogdanm | 0:9b334a45a8ff | 426 | #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ |
| bogdanm | 0:9b334a45a8ff | 427 | |
| bogdanm | 0:9b334a45a8ff | 428 | #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP) |
| bogdanm | 0:9b334a45a8ff | 429 | #define __HAL_FREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) |
| bogdanm | 0:9b334a45a8ff | 430 | #define __HAL_UNFREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) |
| bogdanm | 0:9b334a45a8ff | 431 | #endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */ |
| bogdanm | 0:9b334a45a8ff | 432 | |
| bogdanm | 0:9b334a45a8ff | 433 | #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP) |
| bogdanm | 0:9b334a45a8ff | 434 | #define __HAL_FREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) |
| bogdanm | 0:9b334a45a8ff | 435 | #define __HAL_UNFREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) |
| bogdanm | 0:9b334a45a8ff | 436 | #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */ |
| bogdanm | 0:9b334a45a8ff | 437 | |
| bogdanm | 0:9b334a45a8ff | 438 | #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
| bogdanm | 0:9b334a45a8ff | 439 | #define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
| bogdanm | 0:9b334a45a8ff | 440 | #define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
| bogdanm | 0:9b334a45a8ff | 441 | #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ |
| bogdanm | 0:9b334a45a8ff | 442 | |
| bogdanm | 0:9b334a45a8ff | 443 | #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
| bogdanm | 0:9b334a45a8ff | 444 | #define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
| bogdanm | 0:9b334a45a8ff | 445 | #define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
| bogdanm | 0:9b334a45a8ff | 446 | #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ |
| bogdanm | 0:9b334a45a8ff | 447 | |
| bogdanm | 0:9b334a45a8ff | 448 | #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP) |
| bogdanm | 0:9b334a45a8ff | 449 | #define __HAL_FREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) |
| bogdanm | 0:9b334a45a8ff | 450 | #define __HAL_UNFREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) |
| bogdanm | 0:9b334a45a8ff | 451 | #endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */ |
| bogdanm | 0:9b334a45a8ff | 452 | |
| bogdanm | 0:9b334a45a8ff | 453 | #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP) |
| bogdanm | 0:9b334a45a8ff | 454 | #define __HAL_FREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) |
| bogdanm | 0:9b334a45a8ff | 455 | #define __HAL_UNFREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) |
| bogdanm | 0:9b334a45a8ff | 456 | #endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */ |
| bogdanm | 0:9b334a45a8ff | 457 | |
| bogdanm | 0:9b334a45a8ff | 458 | #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) |
| bogdanm | 0:9b334a45a8ff | 459 | #define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
| bogdanm | 0:9b334a45a8ff | 460 | #define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
| bogdanm | 0:9b334a45a8ff | 461 | #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ |
| bogdanm | 0:9b334a45a8ff | 462 | |
| bogdanm | 0:9b334a45a8ff | 463 | #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP) |
| bogdanm | 0:9b334a45a8ff | 464 | #define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP)) |
| bogdanm | 0:9b334a45a8ff | 465 | #define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP)) |
| bogdanm | 0:9b334a45a8ff | 466 | #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ |
| bogdanm | 0:9b334a45a8ff | 467 | |
| bogdanm | 0:9b334a45a8ff | 468 | #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) |
| bogdanm | 0:9b334a45a8ff | 469 | #define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
| bogdanm | 0:9b334a45a8ff | 470 | #define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
| bogdanm | 0:9b334a45a8ff | 471 | #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ |
| bogdanm | 0:9b334a45a8ff | 472 | |
| bogdanm | 0:9b334a45a8ff | 473 | #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
| bogdanm | 0:9b334a45a8ff | 474 | #define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
| bogdanm | 0:9b334a45a8ff | 475 | #define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
| bogdanm | 0:9b334a45a8ff | 476 | #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ |
| bogdanm | 0:9b334a45a8ff | 477 | |
| bogdanm | 0:9b334a45a8ff | 478 | #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
| bogdanm | 0:9b334a45a8ff | 479 | #define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
| bogdanm | 0:9b334a45a8ff | 480 | #define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
| bogdanm | 0:9b334a45a8ff | 481 | #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ |
| bogdanm | 0:9b334a45a8ff | 482 | |
| bogdanm | 0:9b334a45a8ff | 483 | #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) |
| bogdanm | 0:9b334a45a8ff | 484 | #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
| bogdanm | 0:9b334a45a8ff | 485 | #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
| bogdanm | 0:9b334a45a8ff | 486 | #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ |
| bogdanm | 0:9b334a45a8ff | 487 | |
| bogdanm | 0:9b334a45a8ff | 488 | #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) |
| bogdanm | 0:9b334a45a8ff | 489 | #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) |
| bogdanm | 0:9b334a45a8ff | 490 | #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) |
| bogdanm | 0:9b334a45a8ff | 491 | #endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */ |
| bogdanm | 0:9b334a45a8ff | 492 | |
| bogdanm | 0:9b334a45a8ff | 493 | #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT) |
| bogdanm | 0:9b334a45a8ff | 494 | #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) |
| bogdanm | 0:9b334a45a8ff | 495 | #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) |
| bogdanm | 0:9b334a45a8ff | 496 | #endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */ |
| bogdanm | 0:9b334a45a8ff | 497 | |
| bogdanm | 0:9b334a45a8ff | 498 | #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) |
| bogdanm | 0:9b334a45a8ff | 499 | #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP)) |
| bogdanm | 0:9b334a45a8ff | 500 | #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP)) |
| bogdanm | 0:9b334a45a8ff | 501 | #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ |
| bogdanm | 0:9b334a45a8ff | 502 | /** |
| bogdanm | 0:9b334a45a8ff | 503 | * @} |
| bogdanm | 0:9b334a45a8ff | 504 | */ |
| bogdanm | 0:9b334a45a8ff | 505 | |
| bogdanm | 0:9b334a45a8ff | 506 | /** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode |
| bogdanm | 0:9b334a45a8ff | 507 | * @{ |
| bogdanm | 0:9b334a45a8ff | 508 | */ |
| bogdanm | 0:9b334a45a8ff | 509 | #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) |
| bogdanm | 0:9b334a45a8ff | 510 | #define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
| bogdanm | 0:9b334a45a8ff | 511 | #define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
| bogdanm | 0:9b334a45a8ff | 512 | #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ |
| bogdanm | 0:9b334a45a8ff | 513 | |
| bogdanm | 0:9b334a45a8ff | 514 | #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP) |
| bogdanm | 0:9b334a45a8ff | 515 | #define __HAL_FREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) |
| bogdanm | 0:9b334a45a8ff | 516 | #define __HAL_UNFREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) |
| bogdanm | 0:9b334a45a8ff | 517 | #endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */ |
| bogdanm | 0:9b334a45a8ff | 518 | |
| bogdanm | 0:9b334a45a8ff | 519 | #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) |
| bogdanm | 0:9b334a45a8ff | 520 | #define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) |
| bogdanm | 0:9b334a45a8ff | 521 | #define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) |
| bogdanm | 0:9b334a45a8ff | 522 | #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ |
| bogdanm | 0:9b334a45a8ff | 523 | |
| bogdanm | 0:9b334a45a8ff | 524 | #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) |
| bogdanm | 0:9b334a45a8ff | 525 | #define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) |
| bogdanm | 0:9b334a45a8ff | 526 | #define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) |
| bogdanm | 0:9b334a45a8ff | 527 | #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ |
| bogdanm | 0:9b334a45a8ff | 528 | |
| bogdanm | 0:9b334a45a8ff | 529 | #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) |
| bogdanm | 0:9b334a45a8ff | 530 | #define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) |
| bogdanm | 0:9b334a45a8ff | 531 | #define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) |
| bogdanm | 0:9b334a45a8ff | 532 | #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ |
| bogdanm | 0:9b334a45a8ff | 533 | |
| bogdanm | 0:9b334a45a8ff | 534 | #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP) |
| bogdanm | 0:9b334a45a8ff | 535 | #define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP)) |
| bogdanm | 0:9b334a45a8ff | 536 | #define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP)) |
| bogdanm | 0:9b334a45a8ff | 537 | #endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */ |
| bogdanm | 0:9b334a45a8ff | 538 | |
| bogdanm | 0:9b334a45a8ff | 539 | #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP) |
| bogdanm | 0:9b334a45a8ff | 540 | #define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP)) |
| bogdanm | 0:9b334a45a8ff | 541 | #define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP)) |
| bogdanm | 0:9b334a45a8ff | 542 | #endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */ |
| bogdanm | 0:9b334a45a8ff | 543 | /** |
| bogdanm | 0:9b334a45a8ff | 544 | * @} |
| bogdanm | 0:9b334a45a8ff | 545 | */ |
| bogdanm | 0:9b334a45a8ff | 546 | |
| bogdanm | 0:9b334a45a8ff | 547 | /** @defgroup Memory_Mapping_Selection Memory Mapping Selection |
| bogdanm | 0:9b334a45a8ff | 548 | * @{ |
| bogdanm | 0:9b334a45a8ff | 549 | */ |
| bogdanm | 0:9b334a45a8ff | 550 | #if defined(SYSCFG_CFGR1_MEM_MODE) |
| bogdanm | 0:9b334a45a8ff | 551 | /** @brief Main Flash memory mapped at 0x00000000 |
| bogdanm | 0:9b334a45a8ff | 552 | */ |
| bogdanm | 0:9b334a45a8ff | 553 | #define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) |
| bogdanm | 0:9b334a45a8ff | 554 | #endif /* SYSCFG_CFGR1_MEM_MODE */ |
| bogdanm | 0:9b334a45a8ff | 555 | |
| bogdanm | 0:9b334a45a8ff | 556 | #if defined(SYSCFG_CFGR1_MEM_MODE_0) |
| bogdanm | 0:9b334a45a8ff | 557 | /** @brief System Flash memory mapped at 0x00000000 |
| bogdanm | 0:9b334a45a8ff | 558 | */ |
| bogdanm | 0:9b334a45a8ff | 559 | #define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ |
| bogdanm | 0:9b334a45a8ff | 560 | SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ |
| bogdanm | 0:9b334a45a8ff | 561 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 562 | #endif /* SYSCFG_CFGR1_MEM_MODE_0 */ |
| bogdanm | 0:9b334a45a8ff | 563 | |
| bogdanm | 0:9b334a45a8ff | 564 | #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) |
| bogdanm | 0:9b334a45a8ff | 565 | /** @brief Embedded SRAM mapped at 0x00000000 |
| bogdanm | 0:9b334a45a8ff | 566 | */ |
| bogdanm | 0:9b334a45a8ff | 567 | #define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ |
| bogdanm | 0:9b334a45a8ff | 568 | SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ |
| bogdanm | 0:9b334a45a8ff | 569 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 570 | #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ |
| bogdanm | 0:9b334a45a8ff | 571 | |
| bogdanm | 0:9b334a45a8ff | 572 | #if defined(SYSCFG_CFGR1_MEM_MODE_2) |
| bogdanm | 0:9b334a45a8ff | 573 | #define __HAL_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ |
| bogdanm | 0:9b334a45a8ff | 574 | SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \ |
| bogdanm | 0:9b334a45a8ff | 575 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 576 | #endif /* SYSCFG_CFGR1_MEM_MODE_2 */ |
| bogdanm | 0:9b334a45a8ff | 577 | /** |
| bogdanm | 0:9b334a45a8ff | 578 | * @} |
| bogdanm | 0:9b334a45a8ff | 579 | */ |
| bogdanm | 0:9b334a45a8ff | 580 | |
| bogdanm | 0:9b334a45a8ff | 581 | /** @defgroup Encoder_Mode Encoder Mode |
| bogdanm | 0:9b334a45a8ff | 582 | * @{ |
| bogdanm | 0:9b334a45a8ff | 583 | */ |
| bogdanm | 0:9b334a45a8ff | 584 | #if defined(SYSCFG_CFGR1_ENCODER_MODE) |
| bogdanm | 0:9b334a45a8ff | 585 | /** @brief No Encoder mode |
| bogdanm | 0:9b334a45a8ff | 586 | */ |
| bogdanm | 0:9b334a45a8ff | 587 | #define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE)) |
| bogdanm | 0:9b334a45a8ff | 588 | #endif /* SYSCFG_CFGR1_ENCODER_MODE */ |
| bogdanm | 0:9b334a45a8ff | 589 | |
| bogdanm | 0:9b334a45a8ff | 590 | #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) |
| bogdanm | 0:9b334a45a8ff | 591 | /** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively |
| bogdanm | 0:9b334a45a8ff | 592 | */ |
| bogdanm | 0:9b334a45a8ff | 593 | #define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ |
| bogdanm | 0:9b334a45a8ff | 594 | SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \ |
| bogdanm | 0:9b334a45a8ff | 595 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 596 | #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */ |
| bogdanm | 0:9b334a45a8ff | 597 | |
| bogdanm | 0:9b334a45a8ff | 598 | #if defined(SYSCFG_CFGR1_ENCODER_MODE_1) |
| bogdanm | 0:9b334a45a8ff | 599 | /** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively |
| bogdanm | 0:9b334a45a8ff | 600 | */ |
| bogdanm | 0:9b334a45a8ff | 601 | #define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ |
| bogdanm | 0:9b334a45a8ff | 602 | SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \ |
| bogdanm | 0:9b334a45a8ff | 603 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 604 | #endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */ |
| bogdanm | 0:9b334a45a8ff | 605 | |
| bogdanm | 0:9b334a45a8ff | 606 | #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1) |
| bogdanm | 0:9b334a45a8ff | 607 | /** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices) |
| bogdanm | 0:9b334a45a8ff | 608 | */ |
| bogdanm | 0:9b334a45a8ff | 609 | #define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ |
| bogdanm | 0:9b334a45a8ff | 610 | SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \ |
| bogdanm | 0:9b334a45a8ff | 611 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 612 | #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */ |
| bogdanm | 0:9b334a45a8ff | 613 | /** |
| bogdanm | 0:9b334a45a8ff | 614 | * @} |
| bogdanm | 0:9b334a45a8ff | 615 | */ |
| bogdanm | 0:9b334a45a8ff | 616 | |
| bogdanm | 0:9b334a45a8ff | 617 | /** @defgroup DMA_Remap_Enable DMA Remap Enable |
| bogdanm | 0:9b334a45a8ff | 618 | * @{ |
| bogdanm | 0:9b334a45a8ff | 619 | */ |
| bogdanm | 0:9b334a45a8ff | 620 | #if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP) |
| bogdanm | 0:9b334a45a8ff | 621 | /** @brief DMA remapping enable/disable macros |
| bogdanm | 0:9b334a45a8ff | 622 | * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping |
| bogdanm | 0:9b334a45a8ff | 623 | */ |
| bogdanm | 0:9b334a45a8ff | 624 | #define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 625 | (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ |
| bogdanm | 0:9b334a45a8ff | 626 | (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \ |
| bogdanm | 0:9b334a45a8ff | 627 | (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 628 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 629 | #define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 630 | (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ |
| bogdanm | 0:9b334a45a8ff | 631 | (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \ |
| bogdanm | 0:9b334a45a8ff | 632 | (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 633 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 634 | #elif defined(SYSCFG_CFGR1_DMA_RMP) |
| bogdanm | 0:9b334a45a8ff | 635 | /** @brief DMA remapping enable/disable macros |
| bogdanm | 0:9b334a45a8ff | 636 | * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping |
| bogdanm | 0:9b334a45a8ff | 637 | */ |
| bogdanm | 0:9b334a45a8ff | 638 | #define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 639 | SYSCFG->CFGR1 |= (__DMA_REMAP__); \ |
| bogdanm | 0:9b334a45a8ff | 640 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 641 | #define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 642 | SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ |
| bogdanm | 0:9b334a45a8ff | 643 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 644 | #endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */ |
| bogdanm | 0:9b334a45a8ff | 645 | /** |
| bogdanm | 0:9b334a45a8ff | 646 | * @} |
| bogdanm | 0:9b334a45a8ff | 647 | */ |
| bogdanm | 0:9b334a45a8ff | 648 | |
| bogdanm | 0:9b334a45a8ff | 649 | /** @defgroup I2C2_Fast_Mode_Plus_Enable I2C2 Fast Mode Plus Enable |
| bogdanm | 0:9b334a45a8ff | 650 | * @{ |
| bogdanm | 0:9b334a45a8ff | 651 | */ |
| bogdanm | 0:9b334a45a8ff | 652 | /** @brief Fast mode Plus driving capability enable/disable macros |
| bogdanm | 0:9b334a45a8ff | 653 | * @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C |
| bogdanm | 0:9b334a45a8ff | 654 | */ |
| bogdanm | 0:9b334a45a8ff | 655 | #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \ |
| bogdanm | 0:9b334a45a8ff | 656 | SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \ |
| bogdanm | 0:9b334a45a8ff | 657 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 658 | |
| bogdanm | 0:9b334a45a8ff | 659 | #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \ |
| bogdanm | 0:9b334a45a8ff | 660 | SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \ |
| bogdanm | 0:9b334a45a8ff | 661 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 662 | /** |
| bogdanm | 0:9b334a45a8ff | 663 | * @} |
| bogdanm | 0:9b334a45a8ff | 664 | */ |
| bogdanm | 0:9b334a45a8ff | 665 | |
| bogdanm | 0:9b334a45a8ff | 666 | /** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable |
| bogdanm | 0:9b334a45a8ff | 667 | * @{ |
| bogdanm | 0:9b334a45a8ff | 668 | */ |
| bogdanm | 0:9b334a45a8ff | 669 | /** @brief SYSCFG interrupt enable/disable macros |
| bogdanm | 0:9b334a45a8ff | 670 | * @param __INTERRUPT__: This parameter can be a value of @ref HAL_SYSCFG_Interrupts |
| bogdanm | 0:9b334a45a8ff | 671 | */ |
| bogdanm | 0:9b334a45a8ff | 672 | #define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \ |
| bogdanm | 0:9b334a45a8ff | 673 | SYSCFG->CFGR1 |= (__INTERRUPT__); \ |
| bogdanm | 0:9b334a45a8ff | 674 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 675 | |
| bogdanm | 0:9b334a45a8ff | 676 | #define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \ |
| bogdanm | 0:9b334a45a8ff | 677 | SYSCFG->CFGR1 &= ~(__INTERRUPT__); \ |
| bogdanm | 0:9b334a45a8ff | 678 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 679 | /** |
| bogdanm | 0:9b334a45a8ff | 680 | * @} |
| bogdanm | 0:9b334a45a8ff | 681 | */ |
| bogdanm | 0:9b334a45a8ff | 682 | |
| bogdanm | 0:9b334a45a8ff | 683 | #if defined(SYSCFG_CFGR1_USB_IT_RMP) |
| bogdanm | 0:9b334a45a8ff | 684 | /** @defgroup USB_Interrupt_Remap USB Interrupt Remap |
| bogdanm | 0:9b334a45a8ff | 685 | * @{ |
| bogdanm | 0:9b334a45a8ff | 686 | */ |
| bogdanm | 0:9b334a45a8ff | 687 | /** @brief USB interrupt remapping enable/disable macros |
| bogdanm | 0:9b334a45a8ff | 688 | */ |
| bogdanm | 0:9b334a45a8ff | 689 | #define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP)) |
| bogdanm | 0:9b334a45a8ff | 690 | #define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP)) |
| bogdanm | 0:9b334a45a8ff | 691 | /** |
| bogdanm | 0:9b334a45a8ff | 692 | * @} |
| bogdanm | 0:9b334a45a8ff | 693 | */ |
| bogdanm | 0:9b334a45a8ff | 694 | #endif /* SYSCFG_CFGR1_USB_IT_RMP */ |
| bogdanm | 0:9b334a45a8ff | 695 | |
| bogdanm | 0:9b334a45a8ff | 696 | #if defined(SYSCFG_CFGR1_VBAT) |
| bogdanm | 0:9b334a45a8ff | 697 | /** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable |
| bogdanm | 0:9b334a45a8ff | 698 | * @{ |
| bogdanm | 0:9b334a45a8ff | 699 | */ |
| bogdanm | 0:9b334a45a8ff | 700 | /** @brief SYSCFG interrupt enable/disable macros |
| bogdanm | 0:9b334a45a8ff | 701 | */ |
| bogdanm | 0:9b334a45a8ff | 702 | #define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT)) |
| bogdanm | 0:9b334a45a8ff | 703 | #define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT)) |
| bogdanm | 0:9b334a45a8ff | 704 | /** |
| bogdanm | 0:9b334a45a8ff | 705 | * @} |
| bogdanm | 0:9b334a45a8ff | 706 | */ |
| bogdanm | 0:9b334a45a8ff | 707 | #endif /* SYSCFG_CFGR1_VBAT */ |
| bogdanm | 0:9b334a45a8ff | 708 | |
| bogdanm | 0:9b334a45a8ff | 709 | #if defined(SYSCFG_CFGR2_LOCKUP_LOCK) |
| bogdanm | 0:9b334a45a8ff | 710 | /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable |
| bogdanm | 0:9b334a45a8ff | 711 | * @{ |
| bogdanm | 0:9b334a45a8ff | 712 | */ |
| bogdanm | 0:9b334a45a8ff | 713 | /** @brief SYSCFG Break Lockup lock |
| bogdanm | 0:9b334a45a8ff | 714 | * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input |
| bogdanm | 0:9b334a45a8ff | 715 | * @note The selected configuration is locked and can be unlocked by system reset |
| bogdanm | 0:9b334a45a8ff | 716 | */ |
| bogdanm | 0:9b334a45a8ff | 717 | #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ |
| bogdanm | 0:9b334a45a8ff | 718 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ |
| bogdanm | 0:9b334a45a8ff | 719 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 720 | /** |
| bogdanm | 0:9b334a45a8ff | 721 | * @} |
| bogdanm | 0:9b334a45a8ff | 722 | */ |
| bogdanm | 0:9b334a45a8ff | 723 | #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ |
| bogdanm | 0:9b334a45a8ff | 724 | |
| bogdanm | 0:9b334a45a8ff | 725 | #if defined(SYSCFG_CFGR2_PVD_LOCK) |
| bogdanm | 0:9b334a45a8ff | 726 | /** @defgroup PVD_Lock_Enable PVD Lock |
| bogdanm | 0:9b334a45a8ff | 727 | * @{ |
| bogdanm | 0:9b334a45a8ff | 728 | */ |
| bogdanm | 0:9b334a45a8ff | 729 | /** @brief SYSCFG Break PVD lock |
| bogdanm | 0:9b334a45a8ff | 730 | * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register |
| bogdanm | 0:9b334a45a8ff | 731 | * @note The selected configuration is locked and can be unlocked by system reset |
| bogdanm | 0:9b334a45a8ff | 732 | */ |
| bogdanm | 0:9b334a45a8ff | 733 | #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ |
| bogdanm | 0:9b334a45a8ff | 734 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ |
| bogdanm | 0:9b334a45a8ff | 735 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 736 | /** |
| bogdanm | 0:9b334a45a8ff | 737 | * @} |
| bogdanm | 0:9b334a45a8ff | 738 | */ |
| bogdanm | 0:9b334a45a8ff | 739 | #endif /* SYSCFG_CFGR2_PVD_LOCK */ |
| bogdanm | 0:9b334a45a8ff | 740 | |
| bogdanm | 0:9b334a45a8ff | 741 | #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) |
| bogdanm | 0:9b334a45a8ff | 742 | /** @defgroup SRAM_Parity_Lock SRAM Parity Lock |
| bogdanm | 0:9b334a45a8ff | 743 | * @{ |
| bogdanm | 0:9b334a45a8ff | 744 | */ |
| bogdanm | 0:9b334a45a8ff | 745 | /** @brief SYSCFG Break SRAM PARITY lock |
| bogdanm | 0:9b334a45a8ff | 746 | * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 |
| bogdanm | 0:9b334a45a8ff | 747 | * @note The selected configuration is locked and can be unlocked by system reset |
| bogdanm | 0:9b334a45a8ff | 748 | */ |
| bogdanm | 0:9b334a45a8ff | 749 | #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ |
| bogdanm | 0:9b334a45a8ff | 750 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ |
| bogdanm | 0:9b334a45a8ff | 751 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 752 | /** |
| bogdanm | 0:9b334a45a8ff | 753 | * @} |
| bogdanm | 0:9b334a45a8ff | 754 | */ |
| bogdanm | 0:9b334a45a8ff | 755 | #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */ |
| bogdanm | 0:9b334a45a8ff | 756 | |
| bogdanm | 0:9b334a45a8ff | 757 | /** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable |
| bogdanm | 0:9b334a45a8ff | 758 | * @{ |
| bogdanm | 0:9b334a45a8ff | 759 | */ |
| bogdanm | 0:9b334a45a8ff | 760 | #if defined(SYSCFG_CFGR3_TRIGGER_RMP) |
| bogdanm | 0:9b334a45a8ff | 761 | /** @brief Trigger remapping enable/disable macros |
| bogdanm | 0:9b334a45a8ff | 762 | * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping |
| bogdanm | 0:9b334a45a8ff | 763 | */ |
| bogdanm | 0:9b334a45a8ff | 764 | #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 765 | (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ |
| bogdanm | 0:9b334a45a8ff | 766 | (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \ |
| bogdanm | 0:9b334a45a8ff | 767 | (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 768 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 769 | #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 770 | (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ |
| bogdanm | 0:9b334a45a8ff | 771 | (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \ |
| bogdanm | 0:9b334a45a8ff | 772 | (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 773 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 774 | #else |
| bogdanm | 0:9b334a45a8ff | 775 | /** @brief Trigger remapping enable/disable macros |
| bogdanm | 0:9b334a45a8ff | 776 | * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping |
| bogdanm | 0:9b334a45a8ff | 777 | */ |
| bogdanm | 0:9b334a45a8ff | 778 | #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 779 | (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \ |
| bogdanm | 0:9b334a45a8ff | 780 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 781 | #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 782 | (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \ |
| bogdanm | 0:9b334a45a8ff | 783 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 784 | #endif /* SYSCFG_CFGR3_TRIGGER_RMP */ |
| bogdanm | 0:9b334a45a8ff | 785 | /** |
| bogdanm | 0:9b334a45a8ff | 786 | * @} |
| bogdanm | 0:9b334a45a8ff | 787 | */ |
| bogdanm | 0:9b334a45a8ff | 788 | |
| bogdanm | 0:9b334a45a8ff | 789 | #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) |
| bogdanm | 0:9b334a45a8ff | 790 | /** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable |
| bogdanm | 0:9b334a45a8ff | 791 | * @{ |
| bogdanm | 0:9b334a45a8ff | 792 | */ |
| bogdanm | 0:9b334a45a8ff | 793 | /** @brief ADC trigger remapping enable/disable macros |
| bogdanm | 0:9b334a45a8ff | 794 | * @param __ADCTRIGGER_REMAP__: This parameter can be a value of @ref HAL_ADC_Trigger_Remapping |
| bogdanm | 0:9b334a45a8ff | 795 | */ |
| bogdanm | 0:9b334a45a8ff | 796 | #define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 797 | (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \ |
| bogdanm | 0:9b334a45a8ff | 798 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 799 | #define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \ |
| bogdanm | 0:9b334a45a8ff | 800 | (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \ |
| bogdanm | 0:9b334a45a8ff | 801 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 802 | /** |
| bogdanm | 0:9b334a45a8ff | 803 | * @} |
| bogdanm | 0:9b334a45a8ff | 804 | */ |
| bogdanm | 0:9b334a45a8ff | 805 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
| bogdanm | 0:9b334a45a8ff | 806 | |
| bogdanm | 0:9b334a45a8ff | 807 | #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR) |
| bogdanm | 0:9b334a45a8ff | 808 | /** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable |
| bogdanm | 0:9b334a45a8ff | 809 | * @{ |
| bogdanm | 0:9b334a45a8ff | 810 | */ |
| bogdanm | 0:9b334a45a8ff | 811 | /** |
| bogdanm | 0:9b334a45a8ff | 812 | * @brief Parity check on RAM disable macro |
| bogdanm | 0:9b334a45a8ff | 813 | * @note Disabling the parity check on RAM locks the configuration bit. |
| bogdanm | 0:9b334a45a8ff | 814 | * To re-enable the parity check on RAM perform a system reset. |
| bogdanm | 0:9b334a45a8ff | 815 | */ |
| bogdanm | 0:9b334a45a8ff | 816 | #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = (uint32_t)0x00000001) |
| bogdanm | 0:9b334a45a8ff | 817 | /** |
| bogdanm | 0:9b334a45a8ff | 818 | * @} |
| bogdanm | 0:9b334a45a8ff | 819 | */ |
| bogdanm | 0:9b334a45a8ff | 820 | #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */ |
| bogdanm | 0:9b334a45a8ff | 821 | |
| bogdanm | 0:9b334a45a8ff | 822 | #if defined(SYSCFG_RCR_PAGE0) |
| bogdanm | 0:9b334a45a8ff | 823 | /** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable |
| bogdanm | 0:9b334a45a8ff | 824 | * @{ |
| bogdanm | 0:9b334a45a8ff | 825 | */ |
| bogdanm | 0:9b334a45a8ff | 826 | /** @brief CCM RAM page write protection enable macro |
| bogdanm | 0:9b334a45a8ff | 827 | * @param __PAGE_WP__: This parameter can be a value of @ref HAL_Page_Write_Protection |
| bogdanm | 0:9b334a45a8ff | 828 | * @note write protection can only be disabled by a system reset |
| bogdanm | 0:9b334a45a8ff | 829 | */ |
| bogdanm | 0:9b334a45a8ff | 830 | #define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \ |
| bogdanm | 0:9b334a45a8ff | 831 | SYSCFG->RCR |= (__PAGE_WP__); \ |
| bogdanm | 0:9b334a45a8ff | 832 | }while(0) |
| bogdanm | 0:9b334a45a8ff | 833 | /** |
| bogdanm | 0:9b334a45a8ff | 834 | * @} |
| bogdanm | 0:9b334a45a8ff | 835 | */ |
| bogdanm | 0:9b334a45a8ff | 836 | #endif /* SYSCFG_RCR_PAGE0 */ |
| bogdanm | 0:9b334a45a8ff | 837 | |
| bogdanm | 0:9b334a45a8ff | 838 | /** |
| bogdanm | 0:9b334a45a8ff | 839 | * @} |
| bogdanm | 0:9b334a45a8ff | 840 | */ |
| bogdanm | 0:9b334a45a8ff | 841 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 842 | /** @addtogroup HAL_Exported_Functions HAL Exported Functions |
| bogdanm | 0:9b334a45a8ff | 843 | * @{ |
| bogdanm | 0:9b334a45a8ff | 844 | */ |
| bogdanm | 0:9b334a45a8ff | 845 | |
| bogdanm | 0:9b334a45a8ff | 846 | /** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions |
| bogdanm | 0:9b334a45a8ff | 847 | * @brief Initialization and de-initialization functions |
| bogdanm | 0:9b334a45a8ff | 848 | * @{ |
| bogdanm | 0:9b334a45a8ff | 849 | */ |
| bogdanm | 0:9b334a45a8ff | 850 | /* Initialization and de-initialization functions ******************************/ |
| bogdanm | 0:9b334a45a8ff | 851 | HAL_StatusTypeDef HAL_Init(void); |
| bogdanm | 0:9b334a45a8ff | 852 | HAL_StatusTypeDef HAL_DeInit(void); |
| bogdanm | 0:9b334a45a8ff | 853 | void HAL_MspInit(void); |
| bogdanm | 0:9b334a45a8ff | 854 | void HAL_MspDeInit(void); |
| bogdanm | 0:9b334a45a8ff | 855 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
| bogdanm | 0:9b334a45a8ff | 856 | /** |
| bogdanm | 0:9b334a45a8ff | 857 | * @} |
| bogdanm | 0:9b334a45a8ff | 858 | */ |
| bogdanm | 0:9b334a45a8ff | 859 | |
| bogdanm | 0:9b334a45a8ff | 860 | /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions |
| bogdanm | 0:9b334a45a8ff | 861 | * @brief HAL Control functions |
| bogdanm | 0:9b334a45a8ff | 862 | * @{ |
| bogdanm | 0:9b334a45a8ff | 863 | */ |
| bogdanm | 0:9b334a45a8ff | 864 | /* Peripheral Control functions ************************************************/ |
| bogdanm | 0:9b334a45a8ff | 865 | void HAL_IncTick(void); |
| bogdanm | 0:9b334a45a8ff | 866 | void HAL_Delay(__IO uint32_t Delay); |
| bogdanm | 0:9b334a45a8ff | 867 | void HAL_SuspendTick(void); |
| bogdanm | 0:9b334a45a8ff | 868 | void HAL_ResumeTick(void); |
| bogdanm | 0:9b334a45a8ff | 869 | uint32_t HAL_GetTick(void); |
| bogdanm | 0:9b334a45a8ff | 870 | uint32_t HAL_GetHalVersion(void); |
| bogdanm | 0:9b334a45a8ff | 871 | uint32_t HAL_GetREVID(void); |
| bogdanm | 0:9b334a45a8ff | 872 | uint32_t HAL_GetDEVID(void); |
| bogdanm | 0:9b334a45a8ff | 873 | void HAL_EnableDBGSleepMode(void); |
| bogdanm | 0:9b334a45a8ff | 874 | void HAL_DisableDBGSleepMode(void); |
| bogdanm | 0:9b334a45a8ff | 875 | void HAL_EnableDBGStopMode(void); |
| bogdanm | 0:9b334a45a8ff | 876 | void HAL_DisableDBGStopMode(void); |
| bogdanm | 0:9b334a45a8ff | 877 | void HAL_EnableDBGStandbyMode(void); |
| bogdanm | 0:9b334a45a8ff | 878 | void HAL_DisableDBGStandbyMode(void); |
| bogdanm | 0:9b334a45a8ff | 879 | /** |
| bogdanm | 0:9b334a45a8ff | 880 | * @} |
| bogdanm | 0:9b334a45a8ff | 881 | */ |
| bogdanm | 0:9b334a45a8ff | 882 | |
| bogdanm | 0:9b334a45a8ff | 883 | /** |
| bogdanm | 0:9b334a45a8ff | 884 | * @} |
| bogdanm | 0:9b334a45a8ff | 885 | */ |
| bogdanm | 0:9b334a45a8ff | 886 | |
| bogdanm | 0:9b334a45a8ff | 887 | /** |
| bogdanm | 0:9b334a45a8ff | 888 | * @} |
| bogdanm | 0:9b334a45a8ff | 889 | */ |
| bogdanm | 0:9b334a45a8ff | 890 | |
| bogdanm | 0:9b334a45a8ff | 891 | /** |
| bogdanm | 0:9b334a45a8ff | 892 | * @} |
| bogdanm | 0:9b334a45a8ff | 893 | */ |
| bogdanm | 0:9b334a45a8ff | 894 | |
| bogdanm | 0:9b334a45a8ff | 895 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 896 | } |
| bogdanm | 0:9b334a45a8ff | 897 | #endif |
| bogdanm | 0:9b334a45a8ff | 898 | |
| bogdanm | 0:9b334a45a8ff | 899 | #endif /* __STM32F3xx_HAL_H */ |
| bogdanm | 0:9b334a45a8ff | 900 | |
| bogdanm | 0:9b334a45a8ff | 901 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |