mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 124:6a4a5b7d7324

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f1xx_hal_tim.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 15-December-2014
bogdanm	0:9b334a45a8ff	7	* @brief Header file of TIM HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F1xx_HAL_TIM_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F1xx_HAL_TIM_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32f1xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32F1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup TIM
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup TIM_Exported_Types TIM Exported Types
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61	/**
bogdanm	0:9b334a45a8ff	62	* @brief TIM Time base Configuration Structure definition
bogdanm	0:9b334a45a8ff	63	*/
bogdanm	0:9b334a45a8ff	64	typedef struct
bogdanm	0:9b334a45a8ff	65	{
bogdanm	0:9b334a45a8ff	66	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm	0:9b334a45a8ff	67	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	68
bogdanm	0:9b334a45a8ff	69	uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm	0:9b334a45a8ff	70	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm	0:9b334a45a8ff	73	Auto-Reload Register at the next update event.
bogdanm	0:9b334a45a8ff	74	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm	0:9b334a45a8ff	75
bogdanm	0:9b334a45a8ff	76	uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm	0:9b334a45a8ff	77	This parameter can be a value of @ref TIM_ClockDivision */
bogdanm	0:9b334a45a8ff	78
bogdanm	0:9b334a45a8ff	79	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm	0:9b334a45a8ff	80	reaches zero, an update event is generated and counting restarts
bogdanm	0:9b334a45a8ff	81	from the RCR value (N).
bogdanm	0:9b334a45a8ff	82	This means in PWM mode that (N+1) corresponds to:
bogdanm	0:9b334a45a8ff	83	- the number of PWM periods in edge-aligned mode
bogdanm	0:9b334a45a8ff	84	- the number of half PWM period in center-aligned mode
bogdanm	0:9b334a45a8ff	85	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
bogdanm	0:9b334a45a8ff	86	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	87	} TIM_Base_InitTypeDef;
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	/**
bogdanm	0:9b334a45a8ff	90	* @brief TIM Output Compare Configuration Structure definition
bogdanm	0:9b334a45a8ff	91	*/
bogdanm	0:9b334a45a8ff	92	typedef struct
bogdanm	0:9b334a45a8ff	93	{
bogdanm	0:9b334a45a8ff	94	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	0:9b334a45a8ff	95	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	98	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	99
bogdanm	0:9b334a45a8ff	100	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	0:9b334a45a8ff	101	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	0:9b334a45a8ff	102
bogdanm	0:9b334a45a8ff	103	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	0:9b334a45a8ff	104	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	0:9b334a45a8ff	105	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	106
bogdanm	0:9b334a45a8ff	107	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm	0:9b334a45a8ff	108	This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm	0:9b334a45a8ff	109	@note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111
bogdanm	0:9b334a45a8ff	112	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	113	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	0:9b334a45a8ff	114	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	115
bogdanm	0:9b334a45a8ff	116	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	117	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	0:9b334a45a8ff	118	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	119	} TIM_OC_InitTypeDef;
bogdanm	0:9b334a45a8ff	120
bogdanm	0:9b334a45a8ff	121	/**
bogdanm	0:9b334a45a8ff	122	* @brief TIM One Pulse Mode Configuration Structure definition
bogdanm	0:9b334a45a8ff	123	*/
bogdanm	0:9b334a45a8ff	124	typedef struct
bogdanm	0:9b334a45a8ff	125	{
bogdanm	0:9b334a45a8ff	126	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	0:9b334a45a8ff	127	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	0:9b334a45a8ff	128
bogdanm	0:9b334a45a8ff	129	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	0:9b334a45a8ff	130	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	0:9b334a45a8ff	133	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	0:9b334a45a8ff	136	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	0:9b334a45a8ff	137	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	138
bogdanm	0:9b334a45a8ff	139	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	140	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	0:9b334a45a8ff	141	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	142
bogdanm	0:9b334a45a8ff	143	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	0:9b334a45a8ff	144	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	0:9b334a45a8ff	145	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	148	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	149
bogdanm	0:9b334a45a8ff	150	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	151	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	154	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	155	} TIM_OnePulse_InitTypeDef;
bogdanm	0:9b334a45a8ff	156
bogdanm	0:9b334a45a8ff	157
bogdanm	0:9b334a45a8ff	158	/**
bogdanm	0:9b334a45a8ff	159	* @brief TIM Input Capture Configuration Structure definition
bogdanm	0:9b334a45a8ff	160	*/
bogdanm	0:9b334a45a8ff	161	typedef struct
bogdanm	0:9b334a45a8ff	162	{
bogdanm	0:9b334a45a8ff	163	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	164	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	165
bogdanm	0:9b334a45a8ff	166	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	167	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	170	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	171
bogdanm	0:9b334a45a8ff	172	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	173	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	174	} TIM_IC_InitTypeDef;
bogdanm	0:9b334a45a8ff	175
bogdanm	0:9b334a45a8ff	176	/**
bogdanm	0:9b334a45a8ff	177	* @brief TIM Encoder Configuration Structure definition
bogdanm	0:9b334a45a8ff	178	*/
bogdanm	0:9b334a45a8ff	179	typedef struct
bogdanm	0:9b334a45a8ff	180	{
bogdanm	0:9b334a45a8ff	181	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	182	This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	185	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	186
bogdanm	0:9b334a45a8ff	187	uint32_t IC1Selection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	188	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	189
bogdanm	0:9b334a45a8ff	190	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	191	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	194	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	0:9b334a45a8ff	197	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	0:9b334a45a8ff	198
bogdanm	0:9b334a45a8ff	199	uint32_t IC2Selection; /*!< Specifies the input.
bogdanm	0:9b334a45a8ff	200	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	0:9b334a45a8ff	203	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	0:9b334a45a8ff	204
bogdanm	0:9b334a45a8ff	205	uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm	0:9b334a45a8ff	206	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	207	} TIM_Encoder_InitTypeDef;
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209
bogdanm	0:9b334a45a8ff	210	/**
bogdanm	0:9b334a45a8ff	211	* @brief TIM Clock Configuration Handle Structure definition
bogdanm	0:9b334a45a8ff	212	*/
bogdanm	0:9b334a45a8ff	213	typedef struct
bogdanm	0:9b334a45a8ff	214	{
bogdanm	0:9b334a45a8ff	215	uint32_t ClockSource; /*!< TIM clock sources
bogdanm	0:9b334a45a8ff	216	This parameter can be a value of @ref TIM_Clock_Source */
bogdanm	0:9b334a45a8ff	217	uint32_t ClockPolarity; /*!< TIM clock polarity
bogdanm	0:9b334a45a8ff	218	This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm	0:9b334a45a8ff	219	uint32_t ClockPrescaler; /*!< TIM clock prescaler
bogdanm	0:9b334a45a8ff	220	This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm	0:9b334a45a8ff	221	uint32_t ClockFilter; /*!< TIM clock filter
bogdanm	0:9b334a45a8ff	222	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	223	}TIM_ClockConfigTypeDef;
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225	/**
bogdanm	0:9b334a45a8ff	226	* @brief TIM Clear Input Configuration Handle Structure definition
bogdanm	0:9b334a45a8ff	227	*/
bogdanm	0:9b334a45a8ff	228	typedef struct
bogdanm	0:9b334a45a8ff	229	{
bogdanm	0:9b334a45a8ff	230	uint32_t ClearInputState; /*!< TIM clear Input state
bogdanm	0:9b334a45a8ff	231	This parameter can be ENABLE or DISABLE */
bogdanm	0:9b334a45a8ff	232	uint32_t ClearInputSource; /*!< TIM clear Input sources
bogdanm	0:9b334a45a8ff	233	This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm	0:9b334a45a8ff	234	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
bogdanm	0:9b334a45a8ff	235	This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm	0:9b334a45a8ff	236	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
bogdanm	0:9b334a45a8ff	237	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm	0:9b334a45a8ff	238	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
bogdanm	0:9b334a45a8ff	239	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	240	}TIM_ClearInputConfigTypeDef;
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	/**
bogdanm	0:9b334a45a8ff	243	* @brief TIM Slave configuration Structure definition
bogdanm	0:9b334a45a8ff	244	*/
bogdanm	0:9b334a45a8ff	245	typedef struct {
bogdanm	0:9b334a45a8ff	246	uint32_t SlaveMode; /*!< Slave mode selection
bogdanm	0:9b334a45a8ff	247	This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm	0:9b334a45a8ff	248	uint32_t InputTrigger; /*!< Input Trigger source
bogdanm	0:9b334a45a8ff	249	This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm	0:9b334a45a8ff	250	uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm	0:9b334a45a8ff	251	This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm	0:9b334a45a8ff	252	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm	0:9b334a45a8ff	253	This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm	0:9b334a45a8ff	254	uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm	0:9b334a45a8ff	255	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	0:9b334a45a8ff	256
bogdanm	0:9b334a45a8ff	257	}TIM_SlaveConfigTypeDef;
bogdanm	0:9b334a45a8ff	258
bogdanm	0:9b334a45a8ff	259	/**
bogdanm	0:9b334a45a8ff	260	* @brief HAL State structures definition
bogdanm	0:9b334a45a8ff	261	*/
bogdanm	0:9b334a45a8ff	262	typedef enum
bogdanm	0:9b334a45a8ff	263	{
bogdanm	0:9b334a45a8ff	264	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
bogdanm	0:9b334a45a8ff	265	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	0:9b334a45a8ff	266	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
bogdanm	0:9b334a45a8ff	267	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	0:9b334a45a8ff	268	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
bogdanm	0:9b334a45a8ff	269	}HAL_TIM_StateTypeDef;
bogdanm	0:9b334a45a8ff	270
bogdanm	0:9b334a45a8ff	271	/**
bogdanm	0:9b334a45a8ff	272	* @brief HAL Active channel structures definition
bogdanm	0:9b334a45a8ff	273	*/
bogdanm	0:9b334a45a8ff	274	typedef enum
bogdanm	0:9b334a45a8ff	275	{
bogdanm	0:9b334a45a8ff	276	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
bogdanm	0:9b334a45a8ff	277	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
bogdanm	0:9b334a45a8ff	278	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
bogdanm	0:9b334a45a8ff	279	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
bogdanm	0:9b334a45a8ff	280	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
bogdanm	0:9b334a45a8ff	281	}HAL_TIM_ActiveChannel;
bogdanm	0:9b334a45a8ff	282
bogdanm	0:9b334a45a8ff	283	/**
bogdanm	0:9b334a45a8ff	284	* @brief TIM Time Base Handle Structure definition
bogdanm	0:9b334a45a8ff	285	*/
bogdanm	0:9b334a45a8ff	286	typedef struct
bogdanm	0:9b334a45a8ff	287	{
bogdanm	0:9b334a45a8ff	288	TIM_TypeDef Instance; /!< Register base address */
bogdanm	0:9b334a45a8ff	289	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
bogdanm	0:9b334a45a8ff	290	HAL_TIM_ActiveChannel Channel; /!< Active channel /
bogdanm	0:9b334a45a8ff	291	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
bogdanm	0:9b334a45a8ff	292	This array is accessed by a @ref TIM_DMA_Handle_index */
bogdanm	0:9b334a45a8ff	293	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	0:9b334a45a8ff	294	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
bogdanm	0:9b334a45a8ff	295	}TIM_HandleTypeDef;
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/**
bogdanm	0:9b334a45a8ff	298	* @}
bogdanm	0:9b334a45a8ff	299	*/
bogdanm	0:9b334a45a8ff	300
bogdanm	0:9b334a45a8ff	301	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	302	/** @defgroup TIM_Exported_Constants TIM Exported Constants
bogdanm	0:9b334a45a8ff	303	* @{
bogdanm	0:9b334a45a8ff	304	*/
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
bogdanm	0:9b334a45a8ff	307	* @{
bogdanm	0:9b334a45a8ff	308	*/
bogdanm	0:9b334a45a8ff	309	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	310	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	311	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
bogdanm	0:9b334a45a8ff	312	/**
bogdanm	0:9b334a45a8ff	313	* @}
bogdanm	0:9b334a45a8ff	314	*/
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
bogdanm	0:9b334a45a8ff	317	* @{
bogdanm	0:9b334a45a8ff	318	*/
bogdanm	0:9b334a45a8ff	319	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
bogdanm	0:9b334a45a8ff	320	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
bogdanm	0:9b334a45a8ff	321	/**
bogdanm	0:9b334a45a8ff	322	* @}
bogdanm	0:9b334a45a8ff	323	*/
bogdanm	0:9b334a45a8ff	324
bogdanm	0:9b334a45a8ff	325	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
bogdanm	0:9b334a45a8ff	326	* @{
bogdanm	0:9b334a45a8ff	327	*/
bogdanm	0:9b334a45a8ff	328	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	329	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
bogdanm	0:9b334a45a8ff	330	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
bogdanm	0:9b334a45a8ff	331	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
bogdanm	0:9b334a45a8ff	332	/**
bogdanm	0:9b334a45a8ff	333	* @}
bogdanm	0:9b334a45a8ff	334	*/
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	/** @defgroup TIM_Counter_Mode TIM Counter Mode
bogdanm	0:9b334a45a8ff	337	* @{
bogdanm	0:9b334a45a8ff	338	*/
bogdanm	0:9b334a45a8ff	339	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	340	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm	0:9b334a45a8ff	341	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm	0:9b334a45a8ff	342	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm	0:9b334a45a8ff	343	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm	0:9b334a45a8ff	344	/**
bogdanm	0:9b334a45a8ff	345	* @}
bogdanm	0:9b334a45a8ff	346	*/
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	/** @defgroup TIM_ClockDivision TIM ClockDivision
bogdanm	0:9b334a45a8ff	349	* @{
bogdanm	0:9b334a45a8ff	350	*/
bogdanm	0:9b334a45a8ff	351	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	352	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm	0:9b334a45a8ff	353	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm	0:9b334a45a8ff	354	/**
bogdanm	0:9b334a45a8ff	355	* @}
bogdanm	0:9b334a45a8ff	356	*/
bogdanm	0:9b334a45a8ff	357
bogdanm	0:9b334a45a8ff	358	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
bogdanm	0:9b334a45a8ff	359	* @{
bogdanm	0:9b334a45a8ff	360	*/
bogdanm	0:9b334a45a8ff	361	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	362	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm	0:9b334a45a8ff	363	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	364	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
bogdanm	0:9b334a45a8ff	365	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	366	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm	0:9b334a45a8ff	367	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	368	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm	0:9b334a45a8ff	369	/**
bogdanm	0:9b334a45a8ff	370	* @}
bogdanm	0:9b334a45a8ff	371	*/
bogdanm	0:9b334a45a8ff	372
bogdanm	0:9b334a45a8ff	373	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
bogdanm	0:9b334a45a8ff	374	* @{
bogdanm	0:9b334a45a8ff	375	*/
bogdanm	0:9b334a45a8ff	376	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	377	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm	0:9b334a45a8ff	378	/**
bogdanm	0:9b334a45a8ff	379	* @}
bogdanm	0:9b334a45a8ff	380	*/
bogdanm	0:9b334a45a8ff	381
bogdanm	0:9b334a45a8ff	382	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
bogdanm	0:9b334a45a8ff	383	* @{
bogdanm	0:9b334a45a8ff	384	*/
bogdanm	0:9b334a45a8ff	385	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	386	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm	0:9b334a45a8ff	387	/**
bogdanm	0:9b334a45a8ff	388	* @}
bogdanm	0:9b334a45a8ff	389	*/
bogdanm	0:9b334a45a8ff	390
bogdanm	0:9b334a45a8ff	391	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
bogdanm	0:9b334a45a8ff	392	* @{
bogdanm	0:9b334a45a8ff	393	*/
bogdanm	0:9b334a45a8ff	394	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	395	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm	0:9b334a45a8ff	396	/**
bogdanm	0:9b334a45a8ff	397	* @}
bogdanm	0:9b334a45a8ff	398	*/
bogdanm	0:9b334a45a8ff	399
bogdanm	0:9b334a45a8ff	400	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
bogdanm	0:9b334a45a8ff	401	* @{
bogdanm	0:9b334a45a8ff	402	*/
bogdanm	0:9b334a45a8ff	403	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	404	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm	0:9b334a45a8ff	405	/**
bogdanm	0:9b334a45a8ff	406	* @}
bogdanm	0:9b334a45a8ff	407	*/
bogdanm	0:9b334a45a8ff	408
bogdanm	0:9b334a45a8ff	409	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
bogdanm	0:9b334a45a8ff	410	* @{
bogdanm	0:9b334a45a8ff	411	*/
bogdanm	0:9b334a45a8ff	412	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	413	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm	0:9b334a45a8ff	414	/**
bogdanm	0:9b334a45a8ff	415	* @}
bogdanm	0:9b334a45a8ff	416	*/
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
bogdanm	0:9b334a45a8ff	419	* @{
bogdanm	0:9b334a45a8ff	420	*/
bogdanm	0:9b334a45a8ff	421	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
bogdanm	0:9b334a45a8ff	422	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	423	/**
bogdanm	0:9b334a45a8ff	424	* @}
bogdanm	0:9b334a45a8ff	425	*/
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
bogdanm	0:9b334a45a8ff	428	* @{
bogdanm	0:9b334a45a8ff	429	*/
bogdanm	0:9b334a45a8ff	430	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
bogdanm	0:9b334a45a8ff	431	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	432	/**
bogdanm	0:9b334a45a8ff	433	* @}
bogdanm	0:9b334a45a8ff	434	*/
bogdanm	0:9b334a45a8ff	435
bogdanm	0:9b334a45a8ff	436	/** @defgroup TIM_Channel TIM Channel
bogdanm	0:9b334a45a8ff	437	* @{
bogdanm	0:9b334a45a8ff	438	*/
bogdanm	0:9b334a45a8ff	439	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	440	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	441	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm	0:9b334a45a8ff	442	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm	0:9b334a45a8ff	443	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm	0:9b334a45a8ff	444	/**
bogdanm	0:9b334a45a8ff	445	* @}
bogdanm	0:9b334a45a8ff	446	*/
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
bogdanm	0:9b334a45a8ff	449	* @{
bogdanm	0:9b334a45a8ff	450	*/
bogdanm	0:9b334a45a8ff	451	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm	0:9b334a45a8ff	452	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm	0:9b334a45a8ff	453	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm	0:9b334a45a8ff	454	/**
bogdanm	0:9b334a45a8ff	455	* @}
bogdanm	0:9b334a45a8ff	456	*/
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
bogdanm	0:9b334a45a8ff	459	* @{
bogdanm	0:9b334a45a8ff	460	*/
bogdanm	0:9b334a45a8ff	461	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	0:9b334a45a8ff	462	connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm	0:9b334a45a8ff	463	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	0:9b334a45a8ff	464	connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm	0:9b334a45a8ff	465	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
bogdanm	0:9b334a45a8ff	466	/**
bogdanm	0:9b334a45a8ff	467	* @}
bogdanm	0:9b334a45a8ff	468	*/
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
bogdanm	0:9b334a45a8ff	471	* @{
bogdanm	0:9b334a45a8ff	472	*/
bogdanm	0:9b334a45a8ff	473	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
bogdanm	0:9b334a45a8ff	474	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
bogdanm	0:9b334a45a8ff	475	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
bogdanm	0:9b334a45a8ff	476	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
bogdanm	0:9b334a45a8ff	477	/**
bogdanm	0:9b334a45a8ff	478	* @}
bogdanm	0:9b334a45a8ff	479	*/
bogdanm	0:9b334a45a8ff	480
bogdanm	0:9b334a45a8ff	481	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
bogdanm	0:9b334a45a8ff	482	* @{
bogdanm	0:9b334a45a8ff	483	*/
bogdanm	0:9b334a45a8ff	484	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm	0:9b334a45a8ff	485	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	486	/**
bogdanm	0:9b334a45a8ff	487	* @}
bogdanm	0:9b334a45a8ff	488	*/
bogdanm	0:9b334a45a8ff	489
bogdanm	0:9b334a45a8ff	490	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
bogdanm	0:9b334a45a8ff	491	* @{
bogdanm	0:9b334a45a8ff	492	*/
bogdanm	0:9b334a45a8ff	493	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm	0:9b334a45a8ff	494	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm	0:9b334a45a8ff	495	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
bogdanm	0:9b334a45a8ff	496	/**
bogdanm	0:9b334a45a8ff	497	* @}
bogdanm	0:9b334a45a8ff	498	*/
bogdanm	0:9b334a45a8ff	499
bogdanm	0:9b334a45a8ff	500	/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
bogdanm	0:9b334a45a8ff	501	* @{
bogdanm	0:9b334a45a8ff	502	*/
bogdanm	0:9b334a45a8ff	503	#define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm	0:9b334a45a8ff	504	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm	0:9b334a45a8ff	505	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm	0:9b334a45a8ff	506	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm	0:9b334a45a8ff	507	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm	0:9b334a45a8ff	508	#define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm	0:9b334a45a8ff	509	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm	0:9b334a45a8ff	510	#define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm	0:9b334a45a8ff	511	/**
bogdanm	0:9b334a45a8ff	512	* @}
bogdanm	0:9b334a45a8ff	513	*/
bogdanm	0:9b334a45a8ff	514
bogdanm	0:9b334a45a8ff	515	/** @defgroup TIM_Commutation_Source TIM Commutation Source
bogdanm	0:9b334a45a8ff	516	* @{
bogdanm	0:9b334a45a8ff	517	*/
bogdanm	0:9b334a45a8ff	518	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
bogdanm	0:9b334a45a8ff	519	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	/**
bogdanm	0:9b334a45a8ff	522	* @}
bogdanm	0:9b334a45a8ff	523	*/
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525	/** @defgroup TIM_DMA_sources TIM DMA Sources
bogdanm	0:9b334a45a8ff	526	* @{
bogdanm	0:9b334a45a8ff	527	*/
bogdanm	0:9b334a45a8ff	528	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm	0:9b334a45a8ff	529	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm	0:9b334a45a8ff	530	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm	0:9b334a45a8ff	531	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm	0:9b334a45a8ff	532	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm	0:9b334a45a8ff	533	#define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm	0:9b334a45a8ff	534	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm	0:9b334a45a8ff	535	/**
bogdanm	0:9b334a45a8ff	536	* @}
bogdanm	0:9b334a45a8ff	537	*/
bogdanm	0:9b334a45a8ff	538
bogdanm	0:9b334a45a8ff	539	/** @defgroup TIM_Event_Source TIM Event Source
bogdanm	0:9b334a45a8ff	540	* @{
bogdanm	0:9b334a45a8ff	541	*/
bogdanm	0:9b334a45a8ff	542	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
bogdanm	0:9b334a45a8ff	543	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
bogdanm	0:9b334a45a8ff	544	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
bogdanm	0:9b334a45a8ff	545	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
bogdanm	0:9b334a45a8ff	546	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
bogdanm	0:9b334a45a8ff	547	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
bogdanm	0:9b334a45a8ff	548	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
bogdanm	0:9b334a45a8ff	549	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
bogdanm	0:9b334a45a8ff	550	/**
bogdanm	0:9b334a45a8ff	551	* @}
bogdanm	0:9b334a45a8ff	552	*/
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554	/** @defgroup TIM_Flag_definition TIM Flag Definition
bogdanm	0:9b334a45a8ff	555	* @{
bogdanm	0:9b334a45a8ff	556	*/
bogdanm	0:9b334a45a8ff	557	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm	0:9b334a45a8ff	558	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm	0:9b334a45a8ff	559	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm	0:9b334a45a8ff	560	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm	0:9b334a45a8ff	561	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm	0:9b334a45a8ff	562	#define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm	0:9b334a45a8ff	563	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm	0:9b334a45a8ff	564	#define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm	0:9b334a45a8ff	565	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm	0:9b334a45a8ff	566	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm	0:9b334a45a8ff	567	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm	0:9b334a45a8ff	568	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm	0:9b334a45a8ff	569	/**
bogdanm	0:9b334a45a8ff	570	* @}
bogdanm	0:9b334a45a8ff	571	*/
bogdanm	0:9b334a45a8ff	572
bogdanm	0:9b334a45a8ff	573	/** @defgroup TIM_Clock_Source TIM Clock Source
bogdanm	0:9b334a45a8ff	574	* @{
bogdanm	0:9b334a45a8ff	575	*/
bogdanm	0:9b334a45a8ff	576	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm	0:9b334a45a8ff	577	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm	0:9b334a45a8ff	578	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	579	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm	0:9b334a45a8ff	580	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm	0:9b334a45a8ff	581	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
bogdanm	0:9b334a45a8ff	582	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	583	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	584	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
bogdanm	0:9b334a45a8ff	585	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm	0:9b334a45a8ff	586	/**
bogdanm	0:9b334a45a8ff	587	* @}
bogdanm	0:9b334a45a8ff	588	*/
bogdanm	0:9b334a45a8ff	589
bogdanm	0:9b334a45a8ff	590	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
bogdanm	0:9b334a45a8ff	591	* @{
bogdanm	0:9b334a45a8ff	592	*/
bogdanm	0:9b334a45a8ff	593	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
bogdanm	0:9b334a45a8ff	594	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
bogdanm	0:9b334a45a8ff	595	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	596	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	597	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
bogdanm	0:9b334a45a8ff	598	/**
bogdanm	0:9b334a45a8ff	599	* @}
bogdanm	0:9b334a45a8ff	600	*/
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
bogdanm	0:9b334a45a8ff	603	* @{
bogdanm	0:9b334a45a8ff	604	*/
bogdanm	0:9b334a45a8ff	605	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	606	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	607	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	608	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	609	/**
bogdanm	0:9b334a45a8ff	610	* @}
bogdanm	0:9b334a45a8ff	611	*/
bogdanm	0:9b334a45a8ff	612
bogdanm	0:9b334a45a8ff	613	/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
bogdanm	0:9b334a45a8ff	614	* @{
bogdanm	0:9b334a45a8ff	615	*/
bogdanm	0:9b334a45a8ff	616	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	617	#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
bogdanm	0:9b334a45a8ff	618	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	619	/**
bogdanm	0:9b334a45a8ff	620	* @}
bogdanm	0:9b334a45a8ff	621	*/
bogdanm	0:9b334a45a8ff	622
bogdanm	0:9b334a45a8ff	623	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
bogdanm	0:9b334a45a8ff	624	* @{
bogdanm	0:9b334a45a8ff	625	*/
bogdanm	0:9b334a45a8ff	626	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
bogdanm	0:9b334a45a8ff	627	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
bogdanm	0:9b334a45a8ff	628	/**
bogdanm	0:9b334a45a8ff	629	* @}
bogdanm	0:9b334a45a8ff	630	*/
bogdanm	0:9b334a45a8ff	631
bogdanm	0:9b334a45a8ff	632	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
bogdanm	0:9b334a45a8ff	633	* @{
bogdanm	0:9b334a45a8ff	634	*/
bogdanm	0:9b334a45a8ff	635	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	636	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	637	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	638	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	639	/**
bogdanm	0:9b334a45a8ff	640	* @}
bogdanm	0:9b334a45a8ff	641	*/
bogdanm	0:9b334a45a8ff	642
bogdanm	0:9b334a45a8ff	643	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
bogdanm	0:9b334a45a8ff	644	* @{
bogdanm	0:9b334a45a8ff	645	*/
bogdanm	0:9b334a45a8ff	646	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
bogdanm	0:9b334a45a8ff	647	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	648	/**
bogdanm	0:9b334a45a8ff	649	* @}
bogdanm	0:9b334a45a8ff	650	*/
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
bogdanm	0:9b334a45a8ff	653	* @{
bogdanm	0:9b334a45a8ff	654	*/
bogdanm	0:9b334a45a8ff	655	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm	0:9b334a45a8ff	656	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	657	/**
bogdanm	0:9b334a45a8ff	658	* @}
bogdanm	0:9b334a45a8ff	659	*/
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	/** @defgroup TIM_Lock_level TIM Lock level
bogdanm	0:9b334a45a8ff	662	* @{
bogdanm	0:9b334a45a8ff	663	*/
bogdanm	0:9b334a45a8ff	664	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	665	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm	0:9b334a45a8ff	666	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm	0:9b334a45a8ff	667	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm	0:9b334a45a8ff	668	/**
bogdanm	0:9b334a45a8ff	669	* @}
bogdanm	0:9b334a45a8ff	670	*/
bogdanm	0:9b334a45a8ff	671
bogdanm	0:9b334a45a8ff	672	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
bogdanm	0:9b334a45a8ff	673	* @{
bogdanm	0:9b334a45a8ff	674	*/
bogdanm	0:9b334a45a8ff	675	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
bogdanm	0:9b334a45a8ff	676	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	677	/**
bogdanm	0:9b334a45a8ff	678	* @}
bogdanm	0:9b334a45a8ff	679	*/
bogdanm	0:9b334a45a8ff	680
bogdanm	0:9b334a45a8ff	681	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
bogdanm	0:9b334a45a8ff	682	* @{
bogdanm	0:9b334a45a8ff	683	*/
bogdanm	0:9b334a45a8ff	684	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	685	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm	0:9b334a45a8ff	686	/**
bogdanm	0:9b334a45a8ff	687	* @}
bogdanm	0:9b334a45a8ff	688	*/
bogdanm	0:9b334a45a8ff	689	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
bogdanm	0:9b334a45a8ff	690	* @{
bogdanm	0:9b334a45a8ff	691	*/
bogdanm	0:9b334a45a8ff	692	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm	0:9b334a45a8ff	693	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	694	/**
bogdanm	0:9b334a45a8ff	695	* @}
bogdanm	0:9b334a45a8ff	696	*/
bogdanm	0:9b334a45a8ff	697
bogdanm	0:9b334a45a8ff	698	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
bogdanm	0:9b334a45a8ff	699	* @{
bogdanm	0:9b334a45a8ff	700	*/
bogdanm	0:9b334a45a8ff	701	#define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	702	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm	0:9b334a45a8ff	703	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm	0:9b334a45a8ff	704	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	705	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm	0:9b334a45a8ff	706	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	707	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
bogdanm	0:9b334a45a8ff	708	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	0:9b334a45a8ff	709	/**
bogdanm	0:9b334a45a8ff	710	* @}
bogdanm	0:9b334a45a8ff	711	*/
bogdanm	0:9b334a45a8ff	712
bogdanm	0:9b334a45a8ff	713	/** @defgroup TIM_Slave_Mode TIM Slave Mode
bogdanm	0:9b334a45a8ff	714	* @{
bogdanm	0:9b334a45a8ff	715	*/
bogdanm	0:9b334a45a8ff	716	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	717	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	718	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
bogdanm	0:9b334a45a8ff	719	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
bogdanm	0:9b334a45a8ff	720	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
bogdanm	0:9b334a45a8ff	721	/**
bogdanm	0:9b334a45a8ff	722	* @}
bogdanm	0:9b334a45a8ff	723	*/
bogdanm	0:9b334a45a8ff	724
bogdanm	0:9b334a45a8ff	725	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
bogdanm	0:9b334a45a8ff	726	* @{
bogdanm	0:9b334a45a8ff	727	*/
bogdanm	0:9b334a45a8ff	728	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm	0:9b334a45a8ff	729	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	730	/**
bogdanm	0:9b334a45a8ff	731	* @}
bogdanm	0:9b334a45a8ff	732	*/
bogdanm	0:9b334a45a8ff	733
bogdanm	0:9b334a45a8ff	734	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
bogdanm	0:9b334a45a8ff	735	* @{
bogdanm	0:9b334a45a8ff	736	*/
bogdanm	0:9b334a45a8ff	737	#define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	738	#define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm	0:9b334a45a8ff	739	#define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm	0:9b334a45a8ff	740	#define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm	0:9b334a45a8ff	741	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm	0:9b334a45a8ff	742	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm	0:9b334a45a8ff	743	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm	0:9b334a45a8ff	744	#define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm	0:9b334a45a8ff	745	#define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm	0:9b334a45a8ff	746	/**
bogdanm	0:9b334a45a8ff	747	* @}
bogdanm	0:9b334a45a8ff	748	*/
bogdanm	0:9b334a45a8ff	749
bogdanm	0:9b334a45a8ff	750	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
bogdanm	0:9b334a45a8ff	751	* @{
bogdanm	0:9b334a45a8ff	752	*/
bogdanm	0:9b334a45a8ff	753	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
bogdanm	0:9b334a45a8ff	754	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
bogdanm	0:9b334a45a8ff	755	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	756	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	757	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	0:9b334a45a8ff	758	/**
bogdanm	0:9b334a45a8ff	759	* @}
bogdanm	0:9b334a45a8ff	760	*/
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
bogdanm	0:9b334a45a8ff	763	* @{
bogdanm	0:9b334a45a8ff	764	*/
bogdanm	0:9b334a45a8ff	765	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	0:9b334a45a8ff	766	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
bogdanm	0:9b334a45a8ff	767	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
bogdanm	0:9b334a45a8ff	768	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
bogdanm	0:9b334a45a8ff	769	/**
bogdanm	0:9b334a45a8ff	770	* @}
bogdanm	0:9b334a45a8ff	771	*/
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
bogdanm	0:9b334a45a8ff	774	* @{
bogdanm	0:9b334a45a8ff	775	*/
bogdanm	0:9b334a45a8ff	776	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	777	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm	0:9b334a45a8ff	778	/**
bogdanm	0:9b334a45a8ff	779	* @}
bogdanm	0:9b334a45a8ff	780	*/
bogdanm	0:9b334a45a8ff	781
bogdanm	0:9b334a45a8ff	782	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
bogdanm	0:9b334a45a8ff	783	* @{
bogdanm	0:9b334a45a8ff	784	*/
bogdanm	0:9b334a45a8ff	785	#define TIM_DMABASE_CR1 (0x00000000)
bogdanm	0:9b334a45a8ff	786	#define TIM_DMABASE_CR2 (0x00000001)
bogdanm	0:9b334a45a8ff	787	#define TIM_DMABASE_SMCR (0x00000002)
bogdanm	0:9b334a45a8ff	788	#define TIM_DMABASE_DIER (0x00000003)
bogdanm	0:9b334a45a8ff	789	#define TIM_DMABASE_SR (0x00000004)
bogdanm	0:9b334a45a8ff	790	#define TIM_DMABASE_EGR (0x00000005)
bogdanm	0:9b334a45a8ff	791	#define TIM_DMABASE_CCMR1 (0x00000006)
bogdanm	0:9b334a45a8ff	792	#define TIM_DMABASE_CCMR2 (0x00000007)
bogdanm	0:9b334a45a8ff	793	#define TIM_DMABASE_CCER (0x00000008)
bogdanm	0:9b334a45a8ff	794	#define TIM_DMABASE_CNT (0x00000009)
bogdanm	0:9b334a45a8ff	795	#define TIM_DMABASE_PSC (0x0000000A)
bogdanm	0:9b334a45a8ff	796	#define TIM_DMABASE_ARR (0x0000000B)
bogdanm	0:9b334a45a8ff	797	#define TIM_DMABASE_RCR (0x0000000C)
bogdanm	0:9b334a45a8ff	798	#define TIM_DMABASE_CCR1 (0x0000000D)
bogdanm	0:9b334a45a8ff	799	#define TIM_DMABASE_CCR2 (0x0000000E)
bogdanm	0:9b334a45a8ff	800	#define TIM_DMABASE_CCR3 (0x0000000F)
bogdanm	0:9b334a45a8ff	801	#define TIM_DMABASE_CCR4 (0x00000010)
bogdanm	0:9b334a45a8ff	802	#define TIM_DMABASE_BDTR (0x00000011)
bogdanm	0:9b334a45a8ff	803	#define TIM_DMABASE_DCR (0x00000012)
bogdanm	0:9b334a45a8ff	804	/**
bogdanm	0:9b334a45a8ff	805	* @}
bogdanm	0:9b334a45a8ff	806	*/
bogdanm	0:9b334a45a8ff	807
bogdanm	0:9b334a45a8ff	808	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
bogdanm	0:9b334a45a8ff	809	* @{
bogdanm	0:9b334a45a8ff	810	*/
bogdanm	0:9b334a45a8ff	811	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
bogdanm	0:9b334a45a8ff	812	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
bogdanm	0:9b334a45a8ff	813	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
bogdanm	0:9b334a45a8ff	814	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
bogdanm	0:9b334a45a8ff	815	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
bogdanm	0:9b334a45a8ff	816	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
bogdanm	0:9b334a45a8ff	817	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
bogdanm	0:9b334a45a8ff	818	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
bogdanm	0:9b334a45a8ff	819	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
bogdanm	0:9b334a45a8ff	820	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
bogdanm	0:9b334a45a8ff	821	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
bogdanm	0:9b334a45a8ff	822	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
bogdanm	0:9b334a45a8ff	823	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
bogdanm	0:9b334a45a8ff	824	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
bogdanm	0:9b334a45a8ff	825	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
bogdanm	0:9b334a45a8ff	826	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
bogdanm	0:9b334a45a8ff	827	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
bogdanm	0:9b334a45a8ff	828	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
bogdanm	0:9b334a45a8ff	829	/**
bogdanm	0:9b334a45a8ff	830	* @}
bogdanm	0:9b334a45a8ff	831	*/
bogdanm	0:9b334a45a8ff	832
bogdanm	0:9b334a45a8ff	833	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
bogdanm	0:9b334a45a8ff	834	* @{
bogdanm	0:9b334a45a8ff	835	*/
bogdanm	0:9b334a45a8ff	836	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
bogdanm	0:9b334a45a8ff	837	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
bogdanm	0:9b334a45a8ff	838	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
bogdanm	0:9b334a45a8ff	839	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
bogdanm	0:9b334a45a8ff	840	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
bogdanm	0:9b334a45a8ff	841	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
bogdanm	0:9b334a45a8ff	842	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
bogdanm	0:9b334a45a8ff	843	/**
bogdanm	0:9b334a45a8ff	844	* @}
bogdanm	0:9b334a45a8ff	845	*/
bogdanm	0:9b334a45a8ff	846
bogdanm	0:9b334a45a8ff	847	/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
bogdanm	0:9b334a45a8ff	848	* @{
bogdanm	0:9b334a45a8ff	849	*/
bogdanm	0:9b334a45a8ff	850	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm	0:9b334a45a8ff	851	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	852	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
bogdanm	0:9b334a45a8ff	853	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
bogdanm	0:9b334a45a8ff	854	/**
bogdanm	0:9b334a45a8ff	855	* @}
bogdanm	0:9b334a45a8ff	856	*/
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858	/**
bogdanm	0:9b334a45a8ff	859	* @}
bogdanm	0:9b334a45a8ff	860	*/
bogdanm	0:9b334a45a8ff	861
bogdanm	0:9b334a45a8ff	862	/* Private Constants -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	863	/** @defgroup TIM_Private_Constants TIM Private Constants
bogdanm	0:9b334a45a8ff	864	* @{
bogdanm	0:9b334a45a8ff	865	*/
bogdanm	0:9b334a45a8ff	866
bogdanm	0:9b334a45a8ff	867	/* The counter of a timer instance is disabled only if all the CCx
bogdanm	0:9b334a45a8ff	868	channels have been disabled */
bogdanm	0:9b334a45a8ff	869	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
bogdanm	0:9b334a45a8ff	870
bogdanm	0:9b334a45a8ff	871	/* The counter of a timer instance is disabled only if all the CCx and CCxN
bogdanm	0:9b334a45a8ff	872	channels have been disabled */
bogdanm	0:9b334a45a8ff	873	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
bogdanm	0:9b334a45a8ff	874	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
bogdanm	0:9b334a45a8ff	875
bogdanm	0:9b334a45a8ff	876	/**
bogdanm	0:9b334a45a8ff	877	* @}
bogdanm	0:9b334a45a8ff	878	*/
bogdanm	0:9b334a45a8ff	879
bogdanm	0:9b334a45a8ff	880	/* Private Macros -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	881	/** @defgroup TIM_Private_Macros TIM Private Macros
bogdanm	0:9b334a45a8ff	882	* @{
bogdanm	0:9b334a45a8ff	883	*/
bogdanm	0:9b334a45a8ff	884
bogdanm	0:9b334a45a8ff	885	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
bogdanm	0:9b334a45a8ff	886	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
bogdanm	0:9b334a45a8ff	887	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
bogdanm	0:9b334a45a8ff	888	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
bogdanm	0:9b334a45a8ff	889	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm	0:9b334a45a8ff	890
bogdanm	0:9b334a45a8ff	891	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	892	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	893	((DIV) == TIM_CLOCKDIVISION_DIV4))
bogdanm	0:9b334a45a8ff	894
bogdanm	0:9b334a45a8ff	895	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
bogdanm	0:9b334a45a8ff	896	((MODE) == TIM_OCMODE_PWM2))
bogdanm	0:9b334a45a8ff	897
bogdanm	0:9b334a45a8ff	898	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
bogdanm	0:9b334a45a8ff	899	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	900	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	901	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
bogdanm	0:9b334a45a8ff	902	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	903	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
bogdanm	0:9b334a45a8ff	904
bogdanm	0:9b334a45a8ff	905	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	906	((STATE) == TIM_OCFAST_ENABLE))
bogdanm	0:9b334a45a8ff	907
bogdanm	0:9b334a45a8ff	908	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	909	((POLARITY) == TIM_OCPOLARITY_LOW))
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	912	((POLARITY) == TIM_OCNPOLARITY_LOW))
bogdanm	0:9b334a45a8ff	913
bogdanm	0:9b334a45a8ff	914	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
bogdanm	0:9b334a45a8ff	915	((STATE) == TIM_OCIDLESTATE_RESET))
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
bogdanm	0:9b334a45a8ff	918	((STATE) == TIM_OCNIDLESTATE_RESET))
bogdanm	0:9b334a45a8ff	919
bogdanm	0:9b334a45a8ff	920	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	921	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	922	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	0:9b334a45a8ff	923	((CHANNEL) == TIM_CHANNEL_4) \|\| \
bogdanm	0:9b334a45a8ff	924	((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm	0:9b334a45a8ff	925
bogdanm	0:9b334a45a8ff	926	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	927	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	0:9b334a45a8ff	930	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	0:9b334a45a8ff	931	((CHANNEL) == TIM_CHANNEL_3))
bogdanm	0:9b334a45a8ff	932
bogdanm	0:9b334a45a8ff	933	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	934	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	935	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm	0:9b334a45a8ff	936
bogdanm	0:9b334a45a8ff	937	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
bogdanm	0:9b334a45a8ff	938	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
bogdanm	0:9b334a45a8ff	939	((SELECTION) == TIM_ICSELECTION_TRC))
bogdanm	0:9b334a45a8ff	940
bogdanm	0:9b334a45a8ff	941	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	942	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	943	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	944	((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm	0:9b334a45a8ff	945
bogdanm	0:9b334a45a8ff	946	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
bogdanm	0:9b334a45a8ff	947	((MODE) == TIM_OPMODE_REPETITIVE))
bogdanm	0:9b334a45a8ff	948
bogdanm	0:9b334a45a8ff	949	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
bogdanm	0:9b334a45a8ff	950	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
bogdanm	0:9b334a45a8ff	951	((MODE) == TIM_ENCODERMODE_TI12))
bogdanm	0:9b334a45a8ff	952
bogdanm	0:9b334a45a8ff	953	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	0:9b334a45a8ff	956
bogdanm	0:9b334a45a8ff	957	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
bogdanm	0:9b334a45a8ff	958	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
bogdanm	0:9b334a45a8ff	959	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	960	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	961	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	962	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	963	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
bogdanm	0:9b334a45a8ff	964	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
bogdanm	0:9b334a45a8ff	965	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
bogdanm	0:9b334a45a8ff	966	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm	0:9b334a45a8ff	967
bogdanm	0:9b334a45a8ff	968	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
bogdanm	0:9b334a45a8ff	969	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
bogdanm	0:9b334a45a8ff	970	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	971	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
bogdanm	0:9b334a45a8ff	972	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm	0:9b334a45a8ff	973
bogdanm	0:9b334a45a8ff	974	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	975	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	976	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	977	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	978
bogdanm	0:9b334a45a8ff	979	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	980
bogdanm	0:9b334a45a8ff	981	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
bogdanm	0:9b334a45a8ff	982	((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) \|\| \
bogdanm	0:9b334a45a8ff	983	((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
bogdanm	0:9b334a45a8ff	984
bogdanm	0:9b334a45a8ff	985	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
bogdanm	0:9b334a45a8ff	986	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	989	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	990	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	991	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	992
bogdanm	0:9b334a45a8ff	993	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	996	((STATE) == TIM_OSSR_DISABLE))
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	999	((STATE) == TIM_OSSI_DISABLE))
bogdanm	0:9b334a45a8ff	1000
bogdanm	0:9b334a45a8ff	1001	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
bogdanm	0:9b334a45a8ff	1002	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
bogdanm	0:9b334a45a8ff	1003	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
bogdanm	0:9b334a45a8ff	1004	((LEVEL) == TIM_LOCKLEVEL_3))
bogdanm	0:9b334a45a8ff	1005
bogdanm	0:9b334a45a8ff	1006	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1007	((STATE) == TIM_BREAK_DISABLE))
bogdanm	0:9b334a45a8ff	1008
bogdanm	0:9b334a45a8ff	1009	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
bogdanm	0:9b334a45a8ff	1010	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1013	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
bogdanm	0:9b334a45a8ff	1014
bogdanm	0:9b334a45a8ff	1015	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1016	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1017	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	1018	((SOURCE) == TIM_TRGO_OC1) \|\| \
bogdanm	0:9b334a45a8ff	1019	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
bogdanm	0:9b334a45a8ff	1020	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
bogdanm	0:9b334a45a8ff	1021	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
bogdanm	0:9b334a45a8ff	1022	((SOURCE) == TIM_TRGO_OC4REF))
bogdanm	0:9b334a45a8ff	1023
bogdanm	0:9b334a45a8ff	1024	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1025	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
bogdanm	0:9b334a45a8ff	1026	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1027	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
bogdanm	0:9b334a45a8ff	1028	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm	0:9b334a45a8ff	1029
bogdanm	0:9b334a45a8ff	1030	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1031	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm	0:9b334a45a8ff	1032
bogdanm	0:9b334a45a8ff	1033	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	1034	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	1035	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	1036	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	1037	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
bogdanm	0:9b334a45a8ff	1038	((SELECTION) == TIM_TS_TI1FP1) \|\| \
bogdanm	0:9b334a45a8ff	1039	((SELECTION) == TIM_TS_TI2FP2) \|\| \
bogdanm	0:9b334a45a8ff	1040	((SELECTION) == TIM_TS_ETRF))
bogdanm	0:9b334a45a8ff	1041
bogdanm	0:9b334a45a8ff	1042	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	0:9b334a45a8ff	1043	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	0:9b334a45a8ff	1044	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	0:9b334a45a8ff	1045	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	0:9b334a45a8ff	1046	((SELECTION) == TIM_TS_NONE))
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
bogdanm	0:9b334a45a8ff	1049	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
bogdanm	0:9b334a45a8ff	1050	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
bogdanm	0:9b334a45a8ff	1051	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
bogdanm	0:9b334a45a8ff	1052	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1055	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1056	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	1057	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	1058
bogdanm	0:9b334a45a8ff	1059	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
bogdanm	0:9b334a45a8ff	1062	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
bogdanm	0:9b334a45a8ff	1065	((BASE) == TIM_DMABASE_CR2) \|\| \
bogdanm	0:9b334a45a8ff	1066	((BASE) == TIM_DMABASE_SMCR) \|\| \
bogdanm	0:9b334a45a8ff	1067	((BASE) == TIM_DMABASE_DIER) \|\| \
bogdanm	0:9b334a45a8ff	1068	((BASE) == TIM_DMABASE_SR) \|\| \
bogdanm	0:9b334a45a8ff	1069	((BASE) == TIM_DMABASE_EGR) \|\| \
bogdanm	0:9b334a45a8ff	1070	((BASE) == TIM_DMABASE_CCMR1) \|\| \
bogdanm	0:9b334a45a8ff	1071	((BASE) == TIM_DMABASE_CCMR2) \|\| \
bogdanm	0:9b334a45a8ff	1072	((BASE) == TIM_DMABASE_CCER) \|\| \
bogdanm	0:9b334a45a8ff	1073	((BASE) == TIM_DMABASE_CNT) \|\| \
bogdanm	0:9b334a45a8ff	1074	((BASE) == TIM_DMABASE_PSC) \|\| \
bogdanm	0:9b334a45a8ff	1075	((BASE) == TIM_DMABASE_ARR) \|\| \
bogdanm	0:9b334a45a8ff	1076	((BASE) == TIM_DMABASE_RCR) \|\| \
bogdanm	0:9b334a45a8ff	1077	((BASE) == TIM_DMABASE_CCR1) \|\| \
bogdanm	0:9b334a45a8ff	1078	((BASE) == TIM_DMABASE_CCR2) \|\| \
bogdanm	0:9b334a45a8ff	1079	((BASE) == TIM_DMABASE_CCR3) \|\| \
bogdanm	0:9b334a45a8ff	1080	((BASE) == TIM_DMABASE_CCR4) \|\| \
bogdanm	0:9b334a45a8ff	1081	((BASE) == TIM_DMABASE_BDTR) \|\| \
bogdanm	0:9b334a45a8ff	1082	((BASE) == TIM_DMABASE_DCR))
bogdanm	0:9b334a45a8ff	1083
bogdanm	0:9b334a45a8ff	1084	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
bogdanm	0:9b334a45a8ff	1085	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1086	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1087	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1088	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1089	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1090	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1091	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1092	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1093	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1094	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1095	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1096	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1097	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1098	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1099	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1100	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
bogdanm	0:9b334a45a8ff	1101	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	0:9b334a45a8ff	1104
bogdanm	0:9b334a45a8ff	1105	/** @brief Set TIM IC prescaler
bogdanm	0:9b334a45a8ff	1106	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1107	* @param __CHANNEL__: specifies TIM Channel
bogdanm	0:9b334a45a8ff	1108	* @param __ICPSC__: specifies the prescaler value.
bogdanm	0:9b334a45a8ff	1109	* @retval None
bogdanm	0:9b334a45a8ff	1110	*/
bogdanm	0:9b334a45a8ff	1111	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	0:9b334a45a8ff	1112	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
bogdanm	0:9b334a45a8ff	1113	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
bogdanm	0:9b334a45a8ff	1114	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
bogdanm	0:9b334a45a8ff	1115	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
bogdanm	0:9b334a45a8ff	1116
bogdanm	0:9b334a45a8ff	1117	/** @brief Reset TIM IC prescaler
bogdanm	0:9b334a45a8ff	1118	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1119	* @param __CHANNEL__: specifies TIM Channel
bogdanm	0:9b334a45a8ff	1120	* @retval None
bogdanm	0:9b334a45a8ff	1121	*/
bogdanm	0:9b334a45a8ff	1122	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1123	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
bogdanm	0:9b334a45a8ff	1124	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
bogdanm	0:9b334a45a8ff	1125	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
bogdanm	0:9b334a45a8ff	1126	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
bogdanm	0:9b334a45a8ff	1127
bogdanm	0:9b334a45a8ff	1128
bogdanm	0:9b334a45a8ff	1129	/** @brief Set TIM IC polarity
bogdanm	0:9b334a45a8ff	1130	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1131	* @param __CHANNEL__: specifies TIM Channel
bogdanm	0:9b334a45a8ff	1132	* @param __POLARITY__: specifies TIM Channel Polarity
bogdanm	0:9b334a45a8ff	1133	* @retval None
bogdanm	0:9b334a45a8ff	1134	*/
bogdanm	0:9b334a45a8ff	1135	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
bogdanm	0:9b334a45a8ff	1136	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
bogdanm	0:9b334a45a8ff	1137	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
bogdanm	0:9b334a45a8ff	1138	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
bogdanm	0:9b334a45a8ff	1139	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
bogdanm	0:9b334a45a8ff	1140
bogdanm	0:9b334a45a8ff	1141	/** @brief Reset TIM IC polarity
bogdanm	0:9b334a45a8ff	1142	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1143	* @param __CHANNEL__: specifies TIM Channel
bogdanm	0:9b334a45a8ff	1144	* @retval None
bogdanm	0:9b334a45a8ff	1145	*/
bogdanm	0:9b334a45a8ff	1146	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1147	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
bogdanm	0:9b334a45a8ff	1148	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
bogdanm	0:9b334a45a8ff	1149	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
bogdanm	0:9b334a45a8ff	1150	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
bogdanm	0:9b334a45a8ff	1151
bogdanm	0:9b334a45a8ff	1152	/**
bogdanm	0:9b334a45a8ff	1153	* @}
bogdanm	0:9b334a45a8ff	1154	*/
bogdanm	0:9b334a45a8ff	1155
bogdanm	0:9b334a45a8ff	1156	/* Private Functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1157	/** @addtogroup TIM_Private_Functions
bogdanm	0:9b334a45a8ff	1158	* @{
bogdanm	0:9b334a45a8ff	1159	*/
bogdanm	0:9b334a45a8ff	1160	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
bogdanm	0:9b334a45a8ff	1161	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm	0:9b334a45a8ff	1162	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	0:9b334a45a8ff	1163	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1164	void TIM_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1165	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	1166	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
bogdanm	0:9b334a45a8ff	1167	/**
bogdanm	0:9b334a45a8ff	1168	* @}
bogdanm	0:9b334a45a8ff	1169	*/
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	/* Exported macros -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1172	/** @defgroup TIM_Exported_Macros TIM Exported Macros
bogdanm	0:9b334a45a8ff	1173	* @{
bogdanm	0:9b334a45a8ff	1174	*/
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	/** @brief Reset TIM handle state
bogdanm	0:9b334a45a8ff	1177	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1178	* @retval None
bogdanm	0:9b334a45a8ff	1179	*/
bogdanm	0:9b334a45a8ff	1180	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	/**
bogdanm	0:9b334a45a8ff	1183	* @brief Enable the TIM peripheral.
bogdanm	0:9b334a45a8ff	1184	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1185	* @retval None
bogdanm	0:9b334a45a8ff	1186	*/
bogdanm	0:9b334a45a8ff	1187	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
bogdanm	0:9b334a45a8ff	1188
bogdanm	0:9b334a45a8ff	1189	/**
bogdanm	0:9b334a45a8ff	1190	* @brief Enable the TIM main Output.
bogdanm	0:9b334a45a8ff	1191	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1192	* @retval None
bogdanm	0:9b334a45a8ff	1193	*/
bogdanm	0:9b334a45a8ff	1194	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	/**
bogdanm	0:9b334a45a8ff	1197	* @brief Disable the TIM peripheral.
bogdanm	0:9b334a45a8ff	1198	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1199	* @retval None
bogdanm	0:9b334a45a8ff	1200	*/
bogdanm	0:9b334a45a8ff	1201	#define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1202	do { \
bogdanm	0:9b334a45a8ff	1203	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1204	{ \
bogdanm	0:9b334a45a8ff	1205	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1206	{ \
bogdanm	0:9b334a45a8ff	1207	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm	0:9b334a45a8ff	1208	} \
bogdanm	0:9b334a45a8ff	1209	} \
bogdanm	0:9b334a45a8ff	1210	} while(0)
bogdanm	0:9b334a45a8ff	1211	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
bogdanm	0:9b334a45a8ff	1212	channels have been disabled */
bogdanm	0:9b334a45a8ff	1213	/**
bogdanm	0:9b334a45a8ff	1214	* @brief Disable the TIM main Output.
bogdanm	0:9b334a45a8ff	1215	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1216	* @retval None
bogdanm	0:9b334a45a8ff	1217	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
bogdanm	0:9b334a45a8ff	1218	*/
bogdanm	0:9b334a45a8ff	1219	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1220	do { \
bogdanm	0:9b334a45a8ff	1221	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1222	{ \
bogdanm	0:9b334a45a8ff	1223	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
bogdanm	0:9b334a45a8ff	1224	{ \
bogdanm	0:9b334a45a8ff	1225	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
bogdanm	0:9b334a45a8ff	1226	} \
bogdanm	0:9b334a45a8ff	1227	} \
bogdanm	0:9b334a45a8ff	1228	} while(0)
bogdanm	0:9b334a45a8ff	1229
bogdanm	0:9b334a45a8ff	1230	/**
bogdanm	0:9b334a45a8ff	1231	* @brief Enables the specified TIM interrupt.
bogdanm	0:9b334a45a8ff	1232	* @param __HANDLE__: specifies the TIM Handle.
bogdanm	0:9b334a45a8ff	1233	* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
bogdanm	0:9b334a45a8ff	1234	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1235	* @arg TIM_IT_UPDATE: Update interrupt
bogdanm	0:9b334a45a8ff	1236	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
bogdanm	0:9b334a45a8ff	1237	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
bogdanm	0:9b334a45a8ff	1238	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
bogdanm	0:9b334a45a8ff	1239	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
bogdanm	0:9b334a45a8ff	1240	* @arg TIM_IT_COM: Commutation interrupt
bogdanm	0:9b334a45a8ff	1241	* @arg TIM_IT_TRIGGER: Trigger interrupt
bogdanm	0:9b334a45a8ff	1242	* @arg TIM_IT_BREAK: Break interrupt
bogdanm	0:9b334a45a8ff	1243	* @retval None
bogdanm	0:9b334a45a8ff	1244	*/
bogdanm	0:9b334a45a8ff	1245	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1246
bogdanm	0:9b334a45a8ff	1247	/**
bogdanm	0:9b334a45a8ff	1248	* @brief Disables the specified TIM interrupt.
bogdanm	0:9b334a45a8ff	1249	* @param __HANDLE__: specifies the TIM Handle.
bogdanm	0:9b334a45a8ff	1250	* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
bogdanm	0:9b334a45a8ff	1251	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1252	* @arg TIM_IT_UPDATE: Update interrupt
bogdanm	0:9b334a45a8ff	1253	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
bogdanm	0:9b334a45a8ff	1254	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
bogdanm	0:9b334a45a8ff	1255	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
bogdanm	0:9b334a45a8ff	1256	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
bogdanm	0:9b334a45a8ff	1257	* @arg TIM_IT_COM: Commutation interrupt
bogdanm	0:9b334a45a8ff	1258	* @arg TIM_IT_TRIGGER: Trigger interrupt
bogdanm	0:9b334a45a8ff	1259	* @arg TIM_IT_BREAK: Break interrupt
bogdanm	0:9b334a45a8ff	1260	* @retval None
bogdanm	0:9b334a45a8ff	1261	*/
bogdanm	0:9b334a45a8ff	1262	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1263
bogdanm	0:9b334a45a8ff	1264	/**
bogdanm	0:9b334a45a8ff	1265	* @brief Enables the specified DMA request.
bogdanm	0:9b334a45a8ff	1266	* @param __HANDLE__: specifies the TIM Handle.
bogdanm	0:9b334a45a8ff	1267	* @param __DMA__: specifies the TIM DMA request to enable.
bogdanm	0:9b334a45a8ff	1268	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1269	* @arg TIM_DMA_UPDATE: Update DMA request
bogdanm	0:9b334a45a8ff	1270	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
bogdanm	0:9b334a45a8ff	1271	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
bogdanm	0:9b334a45a8ff	1272	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
bogdanm	0:9b334a45a8ff	1273	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
bogdanm	0:9b334a45a8ff	1274	* @arg TIM_DMA_COM: Commutation DMA request
bogdanm	0:9b334a45a8ff	1275	* @arg TIM_DMA_TRIGGER: Trigger DMA request
bogdanm	0:9b334a45a8ff	1276	* @retval None
bogdanm	0:9b334a45a8ff	1277	*/
bogdanm	0:9b334a45a8ff	1278	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/**
bogdanm	0:9b334a45a8ff	1281	* @brief Disables the specified DMA request.
bogdanm	0:9b334a45a8ff	1282	* @param __HANDLE__: specifies the TIM Handle.
bogdanm	0:9b334a45a8ff	1283	* @param __DMA__: specifies the TIM DMA request to disable.
bogdanm	0:9b334a45a8ff	1284	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1285	* @arg TIM_DMA_UPDATE: Update DMA request
bogdanm	0:9b334a45a8ff	1286	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
bogdanm	0:9b334a45a8ff	1287	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
bogdanm	0:9b334a45a8ff	1288	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
bogdanm	0:9b334a45a8ff	1289	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
bogdanm	0:9b334a45a8ff	1290	* @arg TIM_DMA_COM: Commutation DMA request
bogdanm	0:9b334a45a8ff	1291	* @arg TIM_DMA_TRIGGER: Trigger DMA request
bogdanm	0:9b334a45a8ff	1292	* @retval None
bogdanm	0:9b334a45a8ff	1293	*/
bogdanm	0:9b334a45a8ff	1294	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	/**
bogdanm	0:9b334a45a8ff	1297	* @brief Checks whether the specified TIM interrupt flag is set or not.
bogdanm	0:9b334a45a8ff	1298	* @param __HANDLE__: specifies the TIM Handle.
bogdanm	0:9b334a45a8ff	1299	* @param __FLAG__: specifies the TIM interrupt flag to check.
bogdanm	0:9b334a45a8ff	1300	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1301	* @arg TIM_FLAG_UPDATE: Update interrupt flag
bogdanm	0:9b334a45a8ff	1302	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
bogdanm	0:9b334a45a8ff	1303	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
bogdanm	0:9b334a45a8ff	1304	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
bogdanm	0:9b334a45a8ff	1305	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
bogdanm	0:9b334a45a8ff	1306	* @arg TIM_FLAG_COM: Commutation interrupt flag
bogdanm	0:9b334a45a8ff	1307	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
bogdanm	0:9b334a45a8ff	1308	* @arg TIM_FLAG_BREAK: Break interrupt flag
bogdanm	0:9b334a45a8ff	1309	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
bogdanm	0:9b334a45a8ff	1310	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
bogdanm	0:9b334a45a8ff	1311	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
bogdanm	0:9b334a45a8ff	1312	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
bogdanm	0:9b334a45a8ff	1313	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1314	*/
bogdanm	0:9b334a45a8ff	1315	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	1316
bogdanm	0:9b334a45a8ff	1317	/**
bogdanm	0:9b334a45a8ff	1318	* @brief Clears the specified TIM interrupt flag.
bogdanm	0:9b334a45a8ff	1319	* @param __HANDLE__: specifies the TIM Handle.
bogdanm	0:9b334a45a8ff	1320	* @param __FLAG__: specifies the TIM interrupt flag to clear.
bogdanm	0:9b334a45a8ff	1321	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1322	* @arg TIM_FLAG_UPDATE: Update interrupt flag
bogdanm	0:9b334a45a8ff	1323	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
bogdanm	0:9b334a45a8ff	1324	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
bogdanm	0:9b334a45a8ff	1325	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
bogdanm	0:9b334a45a8ff	1326	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
bogdanm	0:9b334a45a8ff	1327	* @arg TIM_FLAG_COM: Commutation interrupt flag
bogdanm	0:9b334a45a8ff	1328	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
bogdanm	0:9b334a45a8ff	1329	* @arg TIM_FLAG_BREAK: Break interrupt flag
bogdanm	0:9b334a45a8ff	1330	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
bogdanm	0:9b334a45a8ff	1331	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
bogdanm	0:9b334a45a8ff	1332	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
bogdanm	0:9b334a45a8ff	1333	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
bogdanm	0:9b334a45a8ff	1334	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1335	*/
bogdanm	0:9b334a45a8ff	1336	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm	0:9b334a45a8ff	1337
bogdanm	0:9b334a45a8ff	1338	/**
bogdanm	0:9b334a45a8ff	1339	* @brief Checks whether the specified TIM interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	1340	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1341	* @param __INTERRUPT__: specifies the TIM interrupt source to check.
bogdanm	0:9b334a45a8ff	1342	* @retval The state of TIM_IT (SET or RESET).
bogdanm	0:9b334a45a8ff	1343	*/
bogdanm	0:9b334a45a8ff	1344	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	0:9b334a45a8ff	1345
bogdanm	0:9b334a45a8ff	1346	/**
bogdanm	0:9b334a45a8ff	1347	* @brief Clear the TIM interrupt pending bits
bogdanm	0:9b334a45a8ff	1348	* @param __HANDLE__: TIM handle
bogdanm	0:9b334a45a8ff	1349	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	1350	* @retval None
bogdanm	0:9b334a45a8ff	1351	*/
bogdanm	0:9b334a45a8ff	1352	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1353
bogdanm	0:9b334a45a8ff	1354	/**
bogdanm	0:9b334a45a8ff	1355	* @brief Indicates whether or not the TIM Counter is used as downcounter
bogdanm	0:9b334a45a8ff	1356	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1357	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
bogdanm	0:9b334a45a8ff	1358	* @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
bogdanm	0:9b334a45a8ff	1359	mode.
bogdanm	0:9b334a45a8ff	1360	*/
bogdanm	0:9b334a45a8ff	1361	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm	0:9b334a45a8ff	1362
bogdanm	0:9b334a45a8ff	1363	/**
bogdanm	0:9b334a45a8ff	1364	* @brief Sets the TIM active prescaler register value on update event.
bogdanm	0:9b334a45a8ff	1365	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1366	* @param __PRESC__: specifies the active prescaler register new value.
bogdanm	0:9b334a45a8ff	1367	* @retval None
bogdanm	0:9b334a45a8ff	1368	*/
bogdanm	0:9b334a45a8ff	1369	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm	0:9b334a45a8ff	1370
bogdanm	0:9b334a45a8ff	1371	/**
bogdanm	0:9b334a45a8ff	1372	* @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm	0:9b334a45a8ff	1373	* calling another time ConfigChannel function.
bogdanm	0:9b334a45a8ff	1374	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1375	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1376	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1377	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1378	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1379	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1380	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1381	* @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm	0:9b334a45a8ff	1382	* @retval None
bogdanm	0:9b334a45a8ff	1383	*/
bogdanm	0:9b334a45a8ff	1384	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm	0:9b334a45a8ff	1385	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	/**
bogdanm	0:9b334a45a8ff	1388	* @brief Gets the TIM Capture Compare Register value on runtime
bogdanm	0:9b334a45a8ff	1389	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1390	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm	0:9b334a45a8ff	1391	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1392	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm	0:9b334a45a8ff	1393	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm	0:9b334a45a8ff	1394	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm	0:9b334a45a8ff	1395	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm	0:9b334a45a8ff	1396	* @retval None
bogdanm	0:9b334a45a8ff	1397	*/
bogdanm	0:9b334a45a8ff	1398	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1399	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm	0:9b334a45a8ff	1400
bogdanm	0:9b334a45a8ff	1401	/**
bogdanm	0:9b334a45a8ff	1402	* @brief Sets the TIM Counter Register value on runtime.
bogdanm	0:9b334a45a8ff	1403	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1404	* @param __COUNTER__: specifies the Counter register new value.
bogdanm	0:9b334a45a8ff	1405	* @retval None
bogdanm	0:9b334a45a8ff	1406	*/
bogdanm	0:9b334a45a8ff	1407	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	/**
bogdanm	0:9b334a45a8ff	1410	* @brief Gets the TIM Counter Register value on runtime.
bogdanm	0:9b334a45a8ff	1411	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1412	* @retval None
bogdanm	0:9b334a45a8ff	1413	*/
bogdanm	0:9b334a45a8ff	1414	#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1415	((__HANDLE__)->Instance->CNT)
bogdanm	0:9b334a45a8ff	1416
bogdanm	0:9b334a45a8ff	1417	/**
bogdanm	0:9b334a45a8ff	1418	* @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm	0:9b334a45a8ff	1419	* another time any Init function.
bogdanm	0:9b334a45a8ff	1420	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1421	* @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm	0:9b334a45a8ff	1422	* @retval None
bogdanm	0:9b334a45a8ff	1423	*/
bogdanm	0:9b334a45a8ff	1424	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
bogdanm	0:9b334a45a8ff	1425	do{ \
bogdanm	0:9b334a45a8ff	1426	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm	0:9b334a45a8ff	1427	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm	0:9b334a45a8ff	1428	} while(0)
bogdanm	0:9b334a45a8ff	1429
bogdanm	0:9b334a45a8ff	1430	/**
bogdanm	0:9b334a45a8ff	1431	* @brief Gets the TIM Autoreload Register value on runtime
bogdanm	0:9b334a45a8ff	1432	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1433	* @retval None
bogdanm	0:9b334a45a8ff	1434	*/
bogdanm	0:9b334a45a8ff	1435	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1436	((__HANDLE__)->Instance->ARR)
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	/**
bogdanm	0:9b334a45a8ff	1439	* @brief Sets the TIM Clock Division value on runtime without calling
bogdanm	0:9b334a45a8ff	1440	* another time any Init function.
bogdanm	0:9b334a45a8ff	1441	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1442	* @param __CKD__: specifies the clock division value.
bogdanm	0:9b334a45a8ff	1443	* This parameter can be one of the following value:
bogdanm	0:9b334a45a8ff	1444	* @arg TIM_CLOCKDIVISION_DIV1
bogdanm	0:9b334a45a8ff	1445	* @arg TIM_CLOCKDIVISION_DIV2
bogdanm	0:9b334a45a8ff	1446	* @arg TIM_CLOCKDIVISION_DIV4
bogdanm	0:9b334a45a8ff	1447	* @retval None
bogdanm	0:9b334a45a8ff	1448	*/
bogdanm	0:9b334a45a8ff	1449	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
bogdanm	0:9b334a45a8ff	1450	do{ \
bogdanm	0:9b334a45a8ff	1451	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm	0:9b334a45a8ff	1452	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
bogdanm	0:9b334a45a8ff	1453	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm	0:9b334a45a8ff	1454	} while(0)
bogdanm	0:9b334a45a8ff	1455
bogdanm	0:9b334a45a8ff	1456	/**
bogdanm	0:9b334a45a8ff	1457	* @brief Gets the TIM Clock Division value on runtime
bogdanm	0:9b334a45a8ff	1458	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1459	* @retval None
bogdanm	0:9b334a45a8ff	1460	*/
bogdanm	0:9b334a45a8ff	1461	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1462	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm	0:9b334a45a8ff	1463
bogdanm	0:9b334a45a8ff	1464	/**
bogdanm	0:9b334a45a8ff	1465	* @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm	0:9b334a45a8ff	1466	* another time HAL_TIM_IC_ConfigChannel() function.
bogdanm	0:9b334a45a8ff	1467	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1468	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1469	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1470	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1471	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1472	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1473	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1474	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm	0:9b334a45a8ff	1475	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1476	* @arg TIM_ICPSC_DIV1: no prescaler
bogdanm	0:9b334a45a8ff	1477	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm	0:9b334a45a8ff	1478	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm	0:9b334a45a8ff	1479	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm	0:9b334a45a8ff	1480	* @retval None
bogdanm	0:9b334a45a8ff	1481	*/
bogdanm	0:9b334a45a8ff	1482	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	0:9b334a45a8ff	1483	do{ \
bogdanm	0:9b334a45a8ff	1484	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
bogdanm	0:9b334a45a8ff	1485	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm	0:9b334a45a8ff	1486	} while(0)
bogdanm	0:9b334a45a8ff	1487
bogdanm	0:9b334a45a8ff	1488	/**
bogdanm	0:9b334a45a8ff	1489	* @brief Gets the TIM Input Capture prescaler on runtime
bogdanm	0:9b334a45a8ff	1490	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1491	* @param __CHANNEL__: TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1492	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1493	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm	0:9b334a45a8ff	1494	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm	0:9b334a45a8ff	1495	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm	0:9b334a45a8ff	1496	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm	0:9b334a45a8ff	1497	* @retval None
bogdanm	0:9b334a45a8ff	1498	*/
bogdanm	0:9b334a45a8ff	1499	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
bogdanm	0:9b334a45a8ff	1500	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm	0:9b334a45a8ff	1501	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm	0:9b334a45a8ff	1502	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm	0:9b334a45a8ff	1503	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	/**
bogdanm	0:9b334a45a8ff	1506	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	0:9b334a45a8ff	1507	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1508	* @note When the USR bit of the TIMx_CR1 register is set, only counter
bogdanm	0:9b334a45a8ff	1509	* overflow/underflow generates an update interrupt or DMA request (if
bogdanm	0:9b334a45a8ff	1510	* enabled)
bogdanm	0:9b334a45a8ff	1511	* @retval None
bogdanm	0:9b334a45a8ff	1512	*/
bogdanm	0:9b334a45a8ff	1513	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1514	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
bogdanm	0:9b334a45a8ff	1515
bogdanm	0:9b334a45a8ff	1516	/**
bogdanm	0:9b334a45a8ff	1517	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	0:9b334a45a8ff	1518	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1519	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
bogdanm	0:9b334a45a8ff	1520	* following events generate an update interrupt or DMA request (if
bogdanm	0:9b334a45a8ff	1521	* enabled):
bogdanm	0:9b334a45a8ff	1522	* (+) Counter overflow/underflow
bogdanm	0:9b334a45a8ff	1523	* (+) Setting the UG bit
bogdanm	0:9b334a45a8ff	1524	* (+) Update generation through the slave mode controller
bogdanm	0:9b334a45a8ff	1525	* @retval None
bogdanm	0:9b334a45a8ff	1526	*/
bogdanm	0:9b334a45a8ff	1527	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	1528	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
bogdanm	0:9b334a45a8ff	1529
bogdanm	0:9b334a45a8ff	1530	/**
bogdanm	0:9b334a45a8ff	1531	* @brief Sets the TIM Capture x input polarity on runtime.
bogdanm	0:9b334a45a8ff	1532	* @param __HANDLE__: TIM handle.
bogdanm	0:9b334a45a8ff	1533	* @param __CHANNEL__: TIM Channels to be configured.
bogdanm	0:9b334a45a8ff	1534	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1535	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1536	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1537	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1538	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1539	* @param __POLARITY__: Polarity for TIx source
bogdanm	0:9b334a45a8ff	1540	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
bogdanm	0:9b334a45a8ff	1541	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
bogdanm	0:9b334a45a8ff	1542	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
bogdanm	0:9b334a45a8ff	1543	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
bogdanm	0:9b334a45a8ff	1544	* @retval None
bogdanm	0:9b334a45a8ff	1545	*/
bogdanm	0:9b334a45a8ff	1546	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
bogdanm	0:9b334a45a8ff	1547	do{ \
bogdanm	0:9b334a45a8ff	1548	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
bogdanm	0:9b334a45a8ff	1549	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
bogdanm	0:9b334a45a8ff	1550	}while(0)
bogdanm	0:9b334a45a8ff	1551
bogdanm	0:9b334a45a8ff	1552	/**
bogdanm	0:9b334a45a8ff	1553	* @}
bogdanm	0:9b334a45a8ff	1554	*/
bogdanm	0:9b334a45a8ff	1555
bogdanm	0:9b334a45a8ff	1556	/* Include TIM HAL Extension module */
bogdanm	0:9b334a45a8ff	1557	#include "stm32f1xx_hal_tim_ex.h"
bogdanm	0:9b334a45a8ff	1558
bogdanm	0:9b334a45a8ff	1559	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1560	/** @addtogroup TIM_Exported_Functions
bogdanm	0:9b334a45a8ff	1561	* @{
bogdanm	0:9b334a45a8ff	1562	*/
bogdanm	0:9b334a45a8ff	1563
bogdanm	0:9b334a45a8ff	1564	/** @addtogroup TIM_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	1565	* @{
bogdanm	0:9b334a45a8ff	1566	*/
bogdanm	0:9b334a45a8ff	1567	/* Time Base functions ********************************************************/
bogdanm	0:9b334a45a8ff	1568	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1569	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1570	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1571	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1572	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1573	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1574	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1575	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1576	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1577	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1578	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1579	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1580	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1581	/**
bogdanm	0:9b334a45a8ff	1582	* @}
bogdanm	0:9b334a45a8ff	1583	*/
bogdanm	0:9b334a45a8ff	1584
bogdanm	0:9b334a45a8ff	1585	/** @addtogroup TIM_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	1586	* @{
bogdanm	0:9b334a45a8ff	1587	*/
bogdanm	0:9b334a45a8ff	1588	/* Timer Output Compare functions **********************************************/
bogdanm	0:9b334a45a8ff	1589	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1590	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1591	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1592	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1593	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1594	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1595	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1596	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1597	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1598	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1599	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1600	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1601	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1602
bogdanm	0:9b334a45a8ff	1603	/**
bogdanm	0:9b334a45a8ff	1604	* @}
bogdanm	0:9b334a45a8ff	1605	*/
bogdanm	0:9b334a45a8ff	1606
bogdanm	0:9b334a45a8ff	1607	/** @addtogroup TIM_Exported_Functions_Group3
bogdanm	0:9b334a45a8ff	1608	* @{
bogdanm	0:9b334a45a8ff	1609	*/
bogdanm	0:9b334a45a8ff	1610	/* Timer PWM functions *********************************************************/
bogdanm	0:9b334a45a8ff	1611	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1612	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1613	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1614	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1615	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1616	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1617	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1618	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1619	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1620	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1621	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1622	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1623	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1624	/**
bogdanm	0:9b334a45a8ff	1625	* @}
bogdanm	0:9b334a45a8ff	1626	*/
bogdanm	0:9b334a45a8ff	1627
bogdanm	0:9b334a45a8ff	1628	/** @addtogroup TIM_Exported_Functions_Group4
bogdanm	0:9b334a45a8ff	1629	* @{
bogdanm	0:9b334a45a8ff	1630	*/
bogdanm	0:9b334a45a8ff	1631	/* Timer Input Capture functions ***********************************************/
bogdanm	0:9b334a45a8ff	1632	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1633	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1634	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1635	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1636	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1637	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1638	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1639	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1640	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1641	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1642	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1643	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	0:9b334a45a8ff	1644	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1645	/**
bogdanm	0:9b334a45a8ff	1646	* @}
bogdanm	0:9b334a45a8ff	1647	*/
bogdanm	0:9b334a45a8ff	1648
bogdanm	0:9b334a45a8ff	1649	/** @addtogroup TIM_Exported_Functions_Group5
bogdanm	0:9b334a45a8ff	1650	* @{
bogdanm	0:9b334a45a8ff	1651	*/
bogdanm	0:9b334a45a8ff	1652	/* Timer One Pulse functions ***************************************************/
bogdanm	0:9b334a45a8ff	1653	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm	0:9b334a45a8ff	1654	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1655	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1656	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1657	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1658	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1659	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1660	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1661	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1662	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	0:9b334a45a8ff	1663	/**
bogdanm	0:9b334a45a8ff	1664	* @}
bogdanm	0:9b334a45a8ff	1665	*/
bogdanm	0:9b334a45a8ff	1666
bogdanm	0:9b334a45a8ff	1667	/** @addtogroup TIM_Exported_Functions_Group6
bogdanm	0:9b334a45a8ff	1668	* @{
bogdanm	0:9b334a45a8ff	1669	*/
bogdanm	0:9b334a45a8ff	1670	/* Timer Encoder functions *****************************************************/
bogdanm	0:9b334a45a8ff	1671	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
bogdanm	0:9b334a45a8ff	1672	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1673	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1674	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1675	/* Blocking mode: Polling */
bogdanm	0:9b334a45a8ff	1676	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1677	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1678	/* Non-Blocking mode: Interrupt */
bogdanm	0:9b334a45a8ff	1679	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1680	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1681	/* Non-Blocking mode: DMA */
bogdanm	0:9b334a45a8ff	1682	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
bogdanm	0:9b334a45a8ff	1683	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1684
bogdanm	0:9b334a45a8ff	1685	/**
bogdanm	0:9b334a45a8ff	1686	* @}
bogdanm	0:9b334a45a8ff	1687	*/
bogdanm	0:9b334a45a8ff	1688
bogdanm	0:9b334a45a8ff	1689	/** @addtogroup TIM_Exported_Functions_Group7
bogdanm	0:9b334a45a8ff	1690	* @{
bogdanm	0:9b334a45a8ff	1691	*/
bogdanm	0:9b334a45a8ff	1692	/* Interrupt Handler functions **********************************************/
bogdanm	0:9b334a45a8ff	1693	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1694	/**
bogdanm	0:9b334a45a8ff	1695	* @}
bogdanm	0:9b334a45a8ff	1696	*/
bogdanm	0:9b334a45a8ff	1697
bogdanm	0:9b334a45a8ff	1698	/** @addtogroup TIM_Exported_Functions_Group8
bogdanm	0:9b334a45a8ff	1699	* @{
bogdanm	0:9b334a45a8ff	1700	*/
bogdanm	0:9b334a45a8ff	1701	/* Control functions *********************************************************/
bogdanm	0:9b334a45a8ff	1702	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1703	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1704	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1705	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm	0:9b334a45a8ff	1706	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1707	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
bogdanm	0:9b334a45a8ff	1708	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm	0:9b334a45a8ff	1709	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	0:9b334a45a8ff	1710	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	0:9b334a45a8ff	1711	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	0:9b334a45a8ff	1712	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	0:9b334a45a8ff	1713	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	0:9b334a45a8ff	1714	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	0:9b334a45a8ff	1715	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	0:9b334a45a8ff	1716	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	0:9b334a45a8ff	1717	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm	0:9b334a45a8ff	1718	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	0:9b334a45a8ff	1719
bogdanm	0:9b334a45a8ff	1720	/**
bogdanm	0:9b334a45a8ff	1721	* @}
bogdanm	0:9b334a45a8ff	1722	*/
bogdanm	0:9b334a45a8ff	1723
bogdanm	0:9b334a45a8ff	1724	/** @addtogroup TIM_Exported_Functions_Group9
bogdanm	0:9b334a45a8ff	1725	* @{
bogdanm	0:9b334a45a8ff	1726	*/
bogdanm	0:9b334a45a8ff	1727	/* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm	0:9b334a45a8ff	1728	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1729	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1730	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1731	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1732	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1733	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1734	/**
bogdanm	0:9b334a45a8ff	1735	* @}
bogdanm	0:9b334a45a8ff	1736	*/
bogdanm	0:9b334a45a8ff	1737
bogdanm	0:9b334a45a8ff	1738	/** @addtogroup TIM_Exported_Functions_Group10
bogdanm	0:9b334a45a8ff	1739	* @{
bogdanm	0:9b334a45a8ff	1740	*/
bogdanm	0:9b334a45a8ff	1741	/* Peripheral State functions **************************************************/
bogdanm	0:9b334a45a8ff	1742	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1743	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1744	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1745	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1746	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1747	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm	0:9b334a45a8ff	1748
bogdanm	0:9b334a45a8ff	1749	/**
bogdanm	0:9b334a45a8ff	1750	* @}
bogdanm	0:9b334a45a8ff	1751	*/
bogdanm	0:9b334a45a8ff	1752
bogdanm	0:9b334a45a8ff	1753	/**
bogdanm	0:9b334a45a8ff	1754	* @}
bogdanm	0:9b334a45a8ff	1755	*/
bogdanm	0:9b334a45a8ff	1756
bogdanm	0:9b334a45a8ff	1757	/**
bogdanm	0:9b334a45a8ff	1758	* @}
bogdanm	0:9b334a45a8ff	1759	*/
bogdanm	0:9b334a45a8ff	1760
bogdanm	0:9b334a45a8ff	1761	/**
bogdanm	0:9b334a45a8ff	1762	* @}
bogdanm	0:9b334a45a8ff	1763	*/
bogdanm	0:9b334a45a8ff	1764
bogdanm	0:9b334a45a8ff	1765	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1766	}
bogdanm	0:9b334a45a8ff	1767	#endif
bogdanm	0:9b334a45a8ff	1768
bogdanm	0:9b334a45a8ff	1769	#endif /* __STM32F1xx_HAL_TIM_H */
bogdanm	0:9b334a45a8ff	1770
bogdanm	0:9b334a45a8ff	1771	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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