mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_eth.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 124:6a4a5b7d7324

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f1xx_hal_eth.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 15-December-2014
bogdanm	0:9b334a45a8ff	7	* @brief ETH HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Ethernet (ETH) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + IO operation functions
bogdanm	0:9b334a45a8ff	12	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	13	* + Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	14	*
bogdanm	0:9b334a45a8ff	15	@verbatim
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	18	==============================================================================
bogdanm	0:9b334a45a8ff	19	[..]
bogdanm	0:9b334a45a8ff	20	(#)Declare a ETH_HandleTypeDef handle structure, for example:
bogdanm	0:9b334a45a8ff	21	ETH_HandleTypeDef heth;
bogdanm	0:9b334a45a8ff	22
bogdanm	0:9b334a45a8ff	23	(#)Fill parameters of Init structure in heth handle
bogdanm	0:9b334a45a8ff	24
bogdanm	0:9b334a45a8ff	25	(#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
bogdanm	0:9b334a45a8ff	26
bogdanm	0:9b334a45a8ff	27	(#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
bogdanm	0:9b334a45a8ff	28	(##) Enable the Ethernet interface clock using
bogdanm	0:9b334a45a8ff	29	(+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	30	(+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	31	(+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	32
bogdanm	0:9b334a45a8ff	33	(##) Initialize the related GPIO clocks
bogdanm	0:9b334a45a8ff	34	(##) Configure Ethernet pin-out
bogdanm	0:9b334a45a8ff	35	(##) Configure Ethernet NVIC interrupt (IT mode)
bogdanm	0:9b334a45a8ff	36
bogdanm	0:9b334a45a8ff	37	(#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
bogdanm	0:9b334a45a8ff	38	(##) HAL_ETH_DMATxDescListInit(); for Transmission process
bogdanm	0:9b334a45a8ff	39	(##) HAL_ETH_DMARxDescListInit(); for Reception process
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	(#)Enable MAC and DMA transmission and reception:
bogdanm	0:9b334a45a8ff	42	(##) HAL_ETH_Start();
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	(#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
bogdanm	0:9b334a45a8ff	45	the frame to MAC TX FIFO:
bogdanm	0:9b334a45a8ff	46	(##) HAL_ETH_TransmitFrame();
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	(#)Poll for a received frame in ETH RX DMA Descriptors and get received
bogdanm	0:9b334a45a8ff	49	frame parameters
bogdanm	0:9b334a45a8ff	50	(##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
bogdanm	0:9b334a45a8ff	51
bogdanm	0:9b334a45a8ff	52	(#) Get a received frame when an ETH RX interrupt occurs:
bogdanm	0:9b334a45a8ff	53	(##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
bogdanm	0:9b334a45a8ff	54
bogdanm	0:9b334a45a8ff	55	(#) Communicate with external PHY device:
bogdanm	0:9b334a45a8ff	56	(##) Read a specific register from the PHY
bogdanm	0:9b334a45a8ff	57	HAL_ETH_ReadPHYRegister();
bogdanm	0:9b334a45a8ff	58	(##) Write data to a specific RHY register:
bogdanm	0:9b334a45a8ff	59	HAL_ETH_WritePHYRegister();
bogdanm	0:9b334a45a8ff	60
bogdanm	0:9b334a45a8ff	61	(#) Configure the Ethernet MAC after ETH peripheral initialization
bogdanm	0:9b334a45a8ff	62	HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
bogdanm	0:9b334a45a8ff	63
bogdanm	0:9b334a45a8ff	64	(#) Configure the Ethernet DMA after ETH peripheral initialization
bogdanm	0:9b334a45a8ff	65	HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67	-@- The PTP protocol and the DMA descriptors ring mode are not supported
bogdanm	0:9b334a45a8ff	68	in this driver
bogdanm	0:9b334a45a8ff	69
bogdanm	0:9b334a45a8ff	70	@endverbatim
bogdanm	0:9b334a45a8ff	71	******************************************************************************
bogdanm	0:9b334a45a8ff	72	* @attention
bogdanm	0:9b334a45a8ff	73	*
bogdanm	0:9b334a45a8ff	74	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	75	*
bogdanm	0:9b334a45a8ff	76	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	77	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	78	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	79	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	80	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	81	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	82	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	83	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	84	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	85	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	86	*
bogdanm	0:9b334a45a8ff	87	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	88	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	89	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	90	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	91	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	92	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	93	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	94	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	95	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	96	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	97	*
bogdanm	0:9b334a45a8ff	98	******************************************************************************
bogdanm	0:9b334a45a8ff	99	*/
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	102	#include "stm32f1xx_hal.h"
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	/** @addtogroup STM32F1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	105	* @{
bogdanm	0:9b334a45a8ff	106	*/
bogdanm	0:9b334a45a8ff	107	#if defined (STM32F107xC)
bogdanm	0:9b334a45a8ff	108
bogdanm	0:9b334a45a8ff	109	/** @defgroup ETH ETH
bogdanm	0:9b334a45a8ff	110	* @brief ETH HAL module driver
bogdanm	0:9b334a45a8ff	111	* @{
bogdanm	0:9b334a45a8ff	112	*/
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	#ifdef HAL_ETH_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	115
bogdanm	0:9b334a45a8ff	116	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	117	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	118	/** @defgroup ETH_Private_Constants ETH Private Constants
bogdanm	0:9b334a45a8ff	119	* @{
bogdanm	0:9b334a45a8ff	120	*/
bogdanm	0:9b334a45a8ff	121	#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
bogdanm	0:9b334a45a8ff	122	#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
bogdanm	0:9b334a45a8ff	123
bogdanm	0:9b334a45a8ff	124	/**
bogdanm	0:9b334a45a8ff	125	* @}
bogdanm	0:9b334a45a8ff	126	*/
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	129	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	130	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	131	/** @defgroup ETH_Private_Functions ETH Private Functions
bogdanm	0:9b334a45a8ff	132	* @{
bogdanm	0:9b334a45a8ff	133	*/
bogdanm	0:9b334a45a8ff	134	static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
bogdanm	0:9b334a45a8ff	135	static void ETH_MACAddressConfig(ETH_HandleTypeDef heth, uint32_t MacAddr, uint8_t Addr);
bogdanm	0:9b334a45a8ff	136	static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	137	static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	138	static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	139	static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	140	static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	141	static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	142	static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	143	static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	144	static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
bogdanm	0:9b334a45a8ff	145
bogdanm	0:9b334a45a8ff	146	/**
bogdanm	0:9b334a45a8ff	147	* @}
bogdanm	0:9b334a45a8ff	148	*/
bogdanm	0:9b334a45a8ff	149	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	/** @defgroup ETH_Exported_Functions ETH Exported Functions
bogdanm	0:9b334a45a8ff	152	* @{
bogdanm	0:9b334a45a8ff	153	*/
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155	/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	156	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	157	*
bogdanm	0:9b334a45a8ff	158	@verbatim
bogdanm	0:9b334a45a8ff	159	===============================================================================
bogdanm	0:9b334a45a8ff	160	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	161	===============================================================================
bogdanm	0:9b334a45a8ff	162	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	163	(+) Initialize and configure the Ethernet peripheral
bogdanm	0:9b334a45a8ff	164	(+) De-initialize the Ethernet peripheral
bogdanm	0:9b334a45a8ff	165
bogdanm	0:9b334a45a8ff	166	@endverbatim
bogdanm	0:9b334a45a8ff	167	* @{
bogdanm	0:9b334a45a8ff	168	*/
bogdanm	0:9b334a45a8ff	169
bogdanm	0:9b334a45a8ff	170	/**
bogdanm	0:9b334a45a8ff	171	* @brief Initializes the Ethernet MAC and DMA according to default
bogdanm	0:9b334a45a8ff	172	* parameters.
bogdanm	0:9b334a45a8ff	173	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	174	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	175	* @retval HAL status
bogdanm	0:9b334a45a8ff	176	*/
bogdanm	0:9b334a45a8ff	177	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	178	{
bogdanm	0:9b334a45a8ff	179	uint32_t tmpreg = 0, phyreg = 0;
bogdanm	0:9b334a45a8ff	180	uint32_t hclk = 60000000;
bogdanm	0:9b334a45a8ff	181	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	182	uint32_t err = ETH_SUCCESS;
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	/* Check the ETH peripheral state */
bogdanm	0:9b334a45a8ff	185	if(heth == NULL)
bogdanm	0:9b334a45a8ff	186	{
bogdanm	0:9b334a45a8ff	187	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	188	}
bogdanm	0:9b334a45a8ff	189
bogdanm	0:9b334a45a8ff	190	/* Check parameters */
bogdanm	0:9b334a45a8ff	191	assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
bogdanm	0:9b334a45a8ff	192	assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
bogdanm	0:9b334a45a8ff	193	assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
bogdanm	0:9b334a45a8ff	194	assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	if(heth->State == HAL_ETH_STATE_RESET)
bogdanm	0:9b334a45a8ff	197	{
bogdanm	0:9b334a45a8ff	198	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	199	heth-> Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	/* Init the low level hardware : GPIO, CLOCK, NVIC. */
bogdanm	0:9b334a45a8ff	202	HAL_ETH_MspInit(heth);
bogdanm	0:9b334a45a8ff	203	}
bogdanm	0:9b334a45a8ff	204
bogdanm	0:9b334a45a8ff	205	/* Select MII or RMII Mode*/
bogdanm	0:9b334a45a8ff	206	AFIO->MAPR &= ~(AFIO_MAPR_MII_RMII_SEL);
bogdanm	0:9b334a45a8ff	207	AFIO->MAPR \|= (uint32_t)heth->Init.MediaInterface;
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209	/* Ethernet Software reset */
bogdanm	0:9b334a45a8ff	210	/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
bogdanm	0:9b334a45a8ff	211	/* After reset all the registers holds their respective reset values */
bogdanm	0:9b334a45a8ff	212	(heth->Instance)->DMABMR \|= ETH_DMABMR_SR;
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	/* Wait for software reset */
bogdanm	0:9b334a45a8ff	215	while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
bogdanm	0:9b334a45a8ff	216	{
bogdanm	0:9b334a45a8ff	217	}
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	/-------------------------------- MAC Initialization ----------------------/
bogdanm	0:9b334a45a8ff	220	/* Get the ETHERNET MACMIIAR value */
bogdanm	0:9b334a45a8ff	221	tmpreg = (heth->Instance)->MACMIIAR;
bogdanm	0:9b334a45a8ff	222	/* Clear CSR Clock Range CR[2:0] bits */
bogdanm	0:9b334a45a8ff	223	tmpreg &= ETH_MACMIIAR_CR_MASK;
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225	/* Get hclk frequency value */
bogdanm	0:9b334a45a8ff	226	hclk = HAL_RCC_GetHCLKFreq();
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	/* Set CR bits depending on hclk value */
bogdanm	0:9b334a45a8ff	229	if((hclk >= 20000000)&&(hclk < 35000000))
bogdanm	0:9b334a45a8ff	230	{
bogdanm	0:9b334a45a8ff	231	/* CSR Clock Range between 20-35 MHz */
bogdanm	0:9b334a45a8ff	232	tmpreg \|= (uint32_t)ETH_MACMIIAR_CR_DIV16;
bogdanm	0:9b334a45a8ff	233	}
bogdanm	0:9b334a45a8ff	234	else if((hclk >= 35000000)&&(hclk < 60000000))
bogdanm	0:9b334a45a8ff	235	{
bogdanm	0:9b334a45a8ff	236	/* CSR Clock Range between 35-60 MHz */
bogdanm	0:9b334a45a8ff	237	tmpreg \|= (uint32_t)ETH_MACMIIAR_CR_DIV26;
bogdanm	0:9b334a45a8ff	238	}
bogdanm	0:9b334a45a8ff	239	else
bogdanm	0:9b334a45a8ff	240	{
bogdanm	0:9b334a45a8ff	241	/* CSR Clock Range between 60-72 MHz */
bogdanm	0:9b334a45a8ff	242	tmpreg \|= (uint32_t)ETH_MACMIIAR_CR_DIV42;
bogdanm	0:9b334a45a8ff	243	}
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
bogdanm	0:9b334a45a8ff	246	(heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	247
bogdanm	0:9b334a45a8ff	248	/-------------------- PHY initialization and configuration ----------------/
bogdanm	0:9b334a45a8ff	249	/* Put the PHY in reset mode */
bogdanm	0:9b334a45a8ff	250	if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
bogdanm	0:9b334a45a8ff	251	{
bogdanm	0:9b334a45a8ff	252	/* In case of write timeout */
bogdanm	0:9b334a45a8ff	253	err = ETH_ERROR;
bogdanm	0:9b334a45a8ff	254
bogdanm	0:9b334a45a8ff	255	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	256	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	/* Set the ETH peripheral state to READY */
bogdanm	0:9b334a45a8ff	259	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	/* Return HAL_ERROR */
bogdanm	0:9b334a45a8ff	262	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	263	}
bogdanm	0:9b334a45a8ff	264
bogdanm	0:9b334a45a8ff	265	/* Delay to assure PHY reset */
bogdanm	0:9b334a45a8ff	266	HAL_Delay(PHY_RESET_DELAY);
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
bogdanm	0:9b334a45a8ff	269	{
bogdanm	0:9b334a45a8ff	270	/* Get tick */
bogdanm	0:9b334a45a8ff	271	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	/* We wait for linked status */
bogdanm	0:9b334a45a8ff	274	do
bogdanm	0:9b334a45a8ff	275	{
bogdanm	0:9b334a45a8ff	276	HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
bogdanm	0:9b334a45a8ff	277
bogdanm	0:9b334a45a8ff	278	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	279	if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	280	{
bogdanm	0:9b334a45a8ff	281	/* In case of write timeout */
bogdanm	0:9b334a45a8ff	282	err = ETH_ERROR;
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	285	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	288
bogdanm	0:9b334a45a8ff	289	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	290	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	293	}
bogdanm	0:9b334a45a8ff	294	} while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
bogdanm	0:9b334a45a8ff	295
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297	/* Enable Auto-Negotiation */
bogdanm	0:9b334a45a8ff	298	if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
bogdanm	0:9b334a45a8ff	299	{
bogdanm	0:9b334a45a8ff	300	/* In case of write timeout */
bogdanm	0:9b334a45a8ff	301	err = ETH_ERROR;
bogdanm	0:9b334a45a8ff	302
bogdanm	0:9b334a45a8ff	303	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	304	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	/* Set the ETH peripheral state to READY */
bogdanm	0:9b334a45a8ff	307	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	308
bogdanm	0:9b334a45a8ff	309	/* Return HAL_ERROR */
bogdanm	0:9b334a45a8ff	310	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	311	}
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	/* Get tick */
bogdanm	0:9b334a45a8ff	314	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	/* Wait until the auto-negotiation will be completed */
bogdanm	0:9b334a45a8ff	317	do
bogdanm	0:9b334a45a8ff	318	{
bogdanm	0:9b334a45a8ff	319	HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	322	if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	323	{
bogdanm	0:9b334a45a8ff	324	/* In case of write timeout */
bogdanm	0:9b334a45a8ff	325	err = ETH_ERROR;
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	328	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	333	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	334
bogdanm	0:9b334a45a8ff	335	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	336	}
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	} while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	/* Read the result of the auto-negotiation */
bogdanm	0:9b334a45a8ff	341	if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
bogdanm	0:9b334a45a8ff	342	{
bogdanm	0:9b334a45a8ff	343	/* In case of write timeout */
bogdanm	0:9b334a45a8ff	344	err = ETH_ERROR;
bogdanm	0:9b334a45a8ff	345
bogdanm	0:9b334a45a8ff	346	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	347	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	348
bogdanm	0:9b334a45a8ff	349	/* Set the ETH peripheral state to READY */
bogdanm	0:9b334a45a8ff	350	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/* Return HAL_ERROR */
bogdanm	0:9b334a45a8ff	353	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	354	}
bogdanm	0:9b334a45a8ff	355
bogdanm	0:9b334a45a8ff	356	/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
bogdanm	0:9b334a45a8ff	357	if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
bogdanm	0:9b334a45a8ff	358	{
bogdanm	0:9b334a45a8ff	359	/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
bogdanm	0:9b334a45a8ff	360	(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
bogdanm	0:9b334a45a8ff	361	}
bogdanm	0:9b334a45a8ff	362	else
bogdanm	0:9b334a45a8ff	363	{
bogdanm	0:9b334a45a8ff	364	/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
bogdanm	0:9b334a45a8ff	365	(heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
bogdanm	0:9b334a45a8ff	366	}
bogdanm	0:9b334a45a8ff	367	/* Configure the MAC with the speed fixed by the auto-negotiation process */
bogdanm	0:9b334a45a8ff	368	if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
bogdanm	0:9b334a45a8ff	369	{
bogdanm	0:9b334a45a8ff	370	/* Set Ethernet speed to 10M following the auto-negotiation */
bogdanm	0:9b334a45a8ff	371	(heth->Init).Speed = ETH_SPEED_10M;
bogdanm	0:9b334a45a8ff	372	}
bogdanm	0:9b334a45a8ff	373	else
bogdanm	0:9b334a45a8ff	374	{
bogdanm	0:9b334a45a8ff	375	/* Set Ethernet speed to 100M following the auto-negotiation */
bogdanm	0:9b334a45a8ff	376	(heth->Init).Speed = ETH_SPEED_100M;
bogdanm	0:9b334a45a8ff	377	}
bogdanm	0:9b334a45a8ff	378	}
bogdanm	0:9b334a45a8ff	379	else /* AutoNegotiation Disable */
bogdanm	0:9b334a45a8ff	380	{
bogdanm	0:9b334a45a8ff	381	/* Check parameters */
bogdanm	0:9b334a45a8ff	382	assert_param(IS_ETH_SPEED(heth->Init.Speed));
bogdanm	0:9b334a45a8ff	383	assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
bogdanm	0:9b334a45a8ff	384
bogdanm	0:9b334a45a8ff	385	/* Set MAC Speed and Duplex Mode */
bogdanm	0:9b334a45a8ff	386	if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) \|
bogdanm	0:9b334a45a8ff	387	(uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
bogdanm	0:9b334a45a8ff	388	{
bogdanm	0:9b334a45a8ff	389	/* In case of write timeout */
bogdanm	0:9b334a45a8ff	390	err = ETH_ERROR;
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	393	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	394
bogdanm	0:9b334a45a8ff	395	/* Set the ETH peripheral state to READY */
bogdanm	0:9b334a45a8ff	396	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	397
bogdanm	0:9b334a45a8ff	398	/* Return HAL_ERROR */
bogdanm	0:9b334a45a8ff	399	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	400	}
bogdanm	0:9b334a45a8ff	401
bogdanm	0:9b334a45a8ff	402	/* Delay to assure PHY configuration */
bogdanm	0:9b334a45a8ff	403	HAL_Delay(PHY_CONFIG_DELAY);
bogdanm	0:9b334a45a8ff	404	}
bogdanm	0:9b334a45a8ff	405
bogdanm	0:9b334a45a8ff	406	/* Config MAC and DMA */
bogdanm	0:9b334a45a8ff	407	ETH_MACDMAConfig(heth, err);
bogdanm	0:9b334a45a8ff	408
bogdanm	0:9b334a45a8ff	409	/* Set ETH HAL State to Ready */
bogdanm	0:9b334a45a8ff	410	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412	/* Return function status */
bogdanm	0:9b334a45a8ff	413	return HAL_OK;
bogdanm	0:9b334a45a8ff	414	}
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416	/**
bogdanm	0:9b334a45a8ff	417	* @brief De-Initializes the ETH peripheral.
bogdanm	0:9b334a45a8ff	418	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	419	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	420	* @retval HAL status
bogdanm	0:9b334a45a8ff	421	*/
bogdanm	0:9b334a45a8ff	422	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	423	{
bogdanm	0:9b334a45a8ff	424	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	425	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	/* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
bogdanm	0:9b334a45a8ff	428	HAL_ETH_MspDeInit(heth);
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	/* Set ETH HAL state to Disabled */
bogdanm	0:9b334a45a8ff	431	heth->State= HAL_ETH_STATE_RESET;
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/* Release Lock */
bogdanm	0:9b334a45a8ff	434	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	435
bogdanm	0:9b334a45a8ff	436	/* Return function status */
bogdanm	0:9b334a45a8ff	437	return HAL_OK;
bogdanm	0:9b334a45a8ff	438	}
bogdanm	0:9b334a45a8ff	439
bogdanm	0:9b334a45a8ff	440	/**
bogdanm	0:9b334a45a8ff	441	* @brief Initializes the DMA Tx descriptors in chain mode.
bogdanm	0:9b334a45a8ff	442	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	443	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	444	* @param DMATxDescTab: Pointer to the first Tx desc list
bogdanm	0:9b334a45a8ff	445	* @param TxBuff: Pointer to the first TxBuffer list
bogdanm	0:9b334a45a8ff	446	* @param TxBuffCount: Number of the used Tx desc in the list
bogdanm	0:9b334a45a8ff	447	* @retval HAL status
bogdanm	0:9b334a45a8ff	448	*/
bogdanm	0:9b334a45a8ff	449	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
bogdanm	0:9b334a45a8ff	450	{
bogdanm	0:9b334a45a8ff	451	uint32_t i = 0;
bogdanm	0:9b334a45a8ff	452	ETH_DMADescTypeDef *dmatxdesc;
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	/* Process Locked */
bogdanm	0:9b334a45a8ff	455	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	456
bogdanm	0:9b334a45a8ff	457	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	458	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	459
bogdanm	0:9b334a45a8ff	460	/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
bogdanm	0:9b334a45a8ff	461	heth->TxDesc = DMATxDescTab;
bogdanm	0:9b334a45a8ff	462
bogdanm	0:9b334a45a8ff	463	/* Fill each DMATxDesc descriptor with the right values */
bogdanm	0:9b334a45a8ff	464	for(i=0; i < TxBuffCount; i++)
bogdanm	0:9b334a45a8ff	465	{
bogdanm	0:9b334a45a8ff	466	/* Get the pointer on the ith member of the Tx Desc list */
bogdanm	0:9b334a45a8ff	467	dmatxdesc = DMATxDescTab + i;
bogdanm	0:9b334a45a8ff	468
bogdanm	0:9b334a45a8ff	469	/* Set Second Address Chained bit */
bogdanm	0:9b334a45a8ff	470	dmatxdesc->Status = ETH_DMATXDESC_TCH;
bogdanm	0:9b334a45a8ff	471
bogdanm	0:9b334a45a8ff	472	/* Set Buffer1 address pointer */
bogdanm	0:9b334a45a8ff	473	dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
bogdanm	0:9b334a45a8ff	474
bogdanm	0:9b334a45a8ff	475	if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
bogdanm	0:9b334a45a8ff	476	{
bogdanm	0:9b334a45a8ff	477	/* Set the DMA Tx descriptors checksum insertion */
bogdanm	0:9b334a45a8ff	478	dmatxdesc->Status \|= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
bogdanm	0:9b334a45a8ff	479	}
bogdanm	0:9b334a45a8ff	480
bogdanm	0:9b334a45a8ff	481	/* Initialize the next descriptor with the Next Descriptor Polling Enable */
bogdanm	0:9b334a45a8ff	482	if(i < (TxBuffCount-1))
bogdanm	0:9b334a45a8ff	483	{
bogdanm	0:9b334a45a8ff	484	/* Set next descriptor address register with next descriptor base address */
bogdanm	0:9b334a45a8ff	485	dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
bogdanm	0:9b334a45a8ff	486	}
bogdanm	0:9b334a45a8ff	487	else
bogdanm	0:9b334a45a8ff	488	{
bogdanm	0:9b334a45a8ff	489	/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
bogdanm	0:9b334a45a8ff	490	dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
bogdanm	0:9b334a45a8ff	491	}
bogdanm	0:9b334a45a8ff	492	}
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	/* Set Transmit Descriptor List Address Register */
bogdanm	0:9b334a45a8ff	495	(heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
bogdanm	0:9b334a45a8ff	496
bogdanm	0:9b334a45a8ff	497	/* Set ETH HAL State to Ready */
bogdanm	0:9b334a45a8ff	498	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	499
bogdanm	0:9b334a45a8ff	500	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	501	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/* Return function status */
bogdanm	0:9b334a45a8ff	504	return HAL_OK;
bogdanm	0:9b334a45a8ff	505	}
bogdanm	0:9b334a45a8ff	506
bogdanm	0:9b334a45a8ff	507	/**
bogdanm	0:9b334a45a8ff	508	* @brief Initializes the DMA Rx descriptors in chain mode.
bogdanm	0:9b334a45a8ff	509	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	510	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	511	* @param DMARxDescTab: Pointer to the first Rx desc list
bogdanm	0:9b334a45a8ff	512	* @param RxBuff: Pointer to the first RxBuffer list
bogdanm	0:9b334a45a8ff	513	* @param RxBuffCount: Number of the used Rx desc in the list
bogdanm	0:9b334a45a8ff	514	* @retval HAL status
bogdanm	0:9b334a45a8ff	515	*/
bogdanm	0:9b334a45a8ff	516	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
bogdanm	0:9b334a45a8ff	517	{
bogdanm	0:9b334a45a8ff	518	uint32_t i = 0;
bogdanm	0:9b334a45a8ff	519	ETH_DMADescTypeDef *DMARxDesc;
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	/* Process Locked */
bogdanm	0:9b334a45a8ff	522	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	523
bogdanm	0:9b334a45a8ff	524	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	525	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	/* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
bogdanm	0:9b334a45a8ff	528	heth->RxDesc = DMARxDescTab;
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/* Fill each DMARxDesc descriptor with the right values */
bogdanm	0:9b334a45a8ff	531	for(i=0; i < RxBuffCount; i++)
bogdanm	0:9b334a45a8ff	532	{
bogdanm	0:9b334a45a8ff	533	/* Get the pointer on the ith member of the Rx Desc list */
bogdanm	0:9b334a45a8ff	534	DMARxDesc = DMARxDescTab+i;
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	/* Set Own bit of the Rx descriptor Status */
bogdanm	0:9b334a45a8ff	537	DMARxDesc->Status = ETH_DMARXDESC_OWN;
bogdanm	0:9b334a45a8ff	538
bogdanm	0:9b334a45a8ff	539	/* Set Buffer1 size and Second Address Chained bit */
bogdanm	0:9b334a45a8ff	540	DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH \| ETH_RX_BUF_SIZE;
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	/* Set Buffer1 address pointer */
bogdanm	0:9b334a45a8ff	543	DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
bogdanm	0:9b334a45a8ff	544
bogdanm	0:9b334a45a8ff	545	if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
bogdanm	0:9b334a45a8ff	546	{
bogdanm	0:9b334a45a8ff	547	/* Enable Ethernet DMA Rx Descriptor interrupt */
bogdanm	0:9b334a45a8ff	548	DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
bogdanm	0:9b334a45a8ff	549	}
bogdanm	0:9b334a45a8ff	550
bogdanm	0:9b334a45a8ff	551	/* Initialize the next descriptor with the Next Descriptor Polling Enable */
bogdanm	0:9b334a45a8ff	552	if(i < (RxBuffCount-1))
bogdanm	0:9b334a45a8ff	553	{
bogdanm	0:9b334a45a8ff	554	/* Set next descriptor address register with next descriptor base address */
bogdanm	0:9b334a45a8ff	555	DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
bogdanm	0:9b334a45a8ff	556	}
bogdanm	0:9b334a45a8ff	557	else
bogdanm	0:9b334a45a8ff	558	{
bogdanm	0:9b334a45a8ff	559	/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
bogdanm	0:9b334a45a8ff	560	DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
bogdanm	0:9b334a45a8ff	561	}
bogdanm	0:9b334a45a8ff	562	}
bogdanm	0:9b334a45a8ff	563
bogdanm	0:9b334a45a8ff	564	/* Set Receive Descriptor List Address Register */
bogdanm	0:9b334a45a8ff	565	(heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567	/* Set ETH HAL State to Ready */
bogdanm	0:9b334a45a8ff	568	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	569
bogdanm	0:9b334a45a8ff	570	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	571	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	572
bogdanm	0:9b334a45a8ff	573	/* Return function status */
bogdanm	0:9b334a45a8ff	574	return HAL_OK;
bogdanm	0:9b334a45a8ff	575	}
bogdanm	0:9b334a45a8ff	576
bogdanm	0:9b334a45a8ff	577	/**
bogdanm	0:9b334a45a8ff	578	* @brief Initializes the ETH MSP.
bogdanm	0:9b334a45a8ff	579	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	580	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	581	* @retval None
bogdanm	0:9b334a45a8ff	582	*/
bogdanm	0:9b334a45a8ff	583	__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	584	{
bogdanm	0:9b334a45a8ff	585	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	586	the HAL_ETH_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	587	*/
bogdanm	0:9b334a45a8ff	588	}
bogdanm	0:9b334a45a8ff	589
bogdanm	0:9b334a45a8ff	590	/**
bogdanm	0:9b334a45a8ff	591	* @brief DeInitializes ETH MSP.
bogdanm	0:9b334a45a8ff	592	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	593	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	594	* @retval None
bogdanm	0:9b334a45a8ff	595	*/
bogdanm	0:9b334a45a8ff	596	__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	597	{
bogdanm	0:9b334a45a8ff	598	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	599	the HAL_ETH_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	600	*/
bogdanm	0:9b334a45a8ff	601	}
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	/**
bogdanm	0:9b334a45a8ff	604	* @}
bogdanm	0:9b334a45a8ff	605	*/
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	608	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	609	*
bogdanm	0:9b334a45a8ff	610	@verbatim
bogdanm	0:9b334a45a8ff	611	==============================================================================
bogdanm	0:9b334a45a8ff	612	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	613	==============================================================================
bogdanm	0:9b334a45a8ff	614	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	615	(+) Transmit a frame
bogdanm	0:9b334a45a8ff	616	HAL_ETH_TransmitFrame();
bogdanm	0:9b334a45a8ff	617	(+) Receive a frame
bogdanm	0:9b334a45a8ff	618	HAL_ETH_GetReceivedFrame();
bogdanm	0:9b334a45a8ff	619	HAL_ETH_GetReceivedFrame_IT();
bogdanm	0:9b334a45a8ff	620	(+) Read from an External PHY register
bogdanm	0:9b334a45a8ff	621	HAL_ETH_ReadPHYRegister();
bogdanm	0:9b334a45a8ff	622	(+) Write to an External PHY register
bogdanm	0:9b334a45a8ff	623	HAL_ETH_WritePHYRegister();
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625	@endverbatim
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	* @{
bogdanm	0:9b334a45a8ff	628	*/
bogdanm	0:9b334a45a8ff	629
bogdanm	0:9b334a45a8ff	630	/**
bogdanm	0:9b334a45a8ff	631	* @brief Sends an Ethernet frame.
bogdanm	0:9b334a45a8ff	632	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	633	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	634	* @param FrameLength: Amount of data to be sent
bogdanm	0:9b334a45a8ff	635	* @retval HAL status
bogdanm	0:9b334a45a8ff	636	*/
bogdanm	0:9b334a45a8ff	637	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
bogdanm	0:9b334a45a8ff	638	{
bogdanm	0:9b334a45a8ff	639	uint32_t bufcount = 0, size = 0, i = 0;
bogdanm	0:9b334a45a8ff	640
bogdanm	0:9b334a45a8ff	641	/* Process Locked */
bogdanm	0:9b334a45a8ff	642	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	645	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	646
bogdanm	0:9b334a45a8ff	647	if (FrameLength == 0)
bogdanm	0:9b334a45a8ff	648	{
bogdanm	0:9b334a45a8ff	649	/* Set ETH HAL state to READY */
bogdanm	0:9b334a45a8ff	650	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	653	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	654
bogdanm	0:9b334a45a8ff	655	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	656	}
bogdanm	0:9b334a45a8ff	657
bogdanm	0:9b334a45a8ff	658	/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
bogdanm	0:9b334a45a8ff	659	if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
bogdanm	0:9b334a45a8ff	660	{
bogdanm	0:9b334a45a8ff	661	/* OWN bit set */
bogdanm	0:9b334a45a8ff	662	heth->State = HAL_ETH_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	665	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	666
bogdanm	0:9b334a45a8ff	667	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	668	}
bogdanm	0:9b334a45a8ff	669
bogdanm	0:9b334a45a8ff	670	/* Get the number of needed Tx buffers for the current frame */
bogdanm	0:9b334a45a8ff	671	if (FrameLength > ETH_TX_BUF_SIZE)
bogdanm	0:9b334a45a8ff	672	{
bogdanm	0:9b334a45a8ff	673	bufcount = FrameLength/ETH_TX_BUF_SIZE;
bogdanm	0:9b334a45a8ff	674	if (FrameLength % ETH_TX_BUF_SIZE)
bogdanm	0:9b334a45a8ff	675	{
bogdanm	0:9b334a45a8ff	676	bufcount++;
bogdanm	0:9b334a45a8ff	677	}
bogdanm	0:9b334a45a8ff	678	}
bogdanm	0:9b334a45a8ff	679	else
bogdanm	0:9b334a45a8ff	680	{
bogdanm	0:9b334a45a8ff	681	bufcount = 1;
bogdanm	0:9b334a45a8ff	682	}
bogdanm	0:9b334a45a8ff	683	if (bufcount == 1)
bogdanm	0:9b334a45a8ff	684	{
bogdanm	0:9b334a45a8ff	685	/* Set LAST and FIRST segment */
bogdanm	0:9b334a45a8ff	686	heth->TxDesc->Status \|=ETH_DMATXDESC_FS\|ETH_DMATXDESC_LS;
bogdanm	0:9b334a45a8ff	687	/* Set frame size */
bogdanm	0:9b334a45a8ff	688	heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
bogdanm	0:9b334a45a8ff	689	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
bogdanm	0:9b334a45a8ff	690	heth->TxDesc->Status \|= ETH_DMATXDESC_OWN;
bogdanm	0:9b334a45a8ff	691	/* Point to next descriptor */
bogdanm	0:9b334a45a8ff	692	heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	693	}
bogdanm	0:9b334a45a8ff	694	else
bogdanm	0:9b334a45a8ff	695	{
bogdanm	0:9b334a45a8ff	696	for (i=0; i< bufcount; i++)
bogdanm	0:9b334a45a8ff	697	{
bogdanm	0:9b334a45a8ff	698	/* Clear FIRST and LAST segment bits */
bogdanm	0:9b334a45a8ff	699	heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS \| ETH_DMATXDESC_LS);
bogdanm	0:9b334a45a8ff	700
bogdanm	0:9b334a45a8ff	701	if (i == 0)
bogdanm	0:9b334a45a8ff	702	{
bogdanm	0:9b334a45a8ff	703	/* Setting the first segment bit */
bogdanm	0:9b334a45a8ff	704	heth->TxDesc->Status \|= ETH_DMATXDESC_FS;
bogdanm	0:9b334a45a8ff	705	}
bogdanm	0:9b334a45a8ff	706
bogdanm	0:9b334a45a8ff	707	/* Program size */
bogdanm	0:9b334a45a8ff	708	heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
bogdanm	0:9b334a45a8ff	709
bogdanm	0:9b334a45a8ff	710	if (i == (bufcount-1))
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	/* Setting the last segment bit */
bogdanm	0:9b334a45a8ff	713	heth->TxDesc->Status \|= ETH_DMATXDESC_LS;
bogdanm	0:9b334a45a8ff	714	size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
bogdanm	0:9b334a45a8ff	715	heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
bogdanm	0:9b334a45a8ff	716	}
bogdanm	0:9b334a45a8ff	717
bogdanm	0:9b334a45a8ff	718	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
bogdanm	0:9b334a45a8ff	719	heth->TxDesc->Status \|= ETH_DMATXDESC_OWN;
bogdanm	0:9b334a45a8ff	720	/* point to next descriptor */
bogdanm	0:9b334a45a8ff	721	heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	722	}
bogdanm	0:9b334a45a8ff	723	}
bogdanm	0:9b334a45a8ff	724
bogdanm	0:9b334a45a8ff	725	/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
bogdanm	0:9b334a45a8ff	726	if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
bogdanm	0:9b334a45a8ff	727	{
bogdanm	0:9b334a45a8ff	728	/* Clear TBUS ETHERNET DMA flag */
bogdanm	0:9b334a45a8ff	729	(heth->Instance)->DMASR = ETH_DMASR_TBUS;
bogdanm	0:9b334a45a8ff	730	/* Resume DMA transmission*/
bogdanm	0:9b334a45a8ff	731	(heth->Instance)->DMATPDR = 0;
bogdanm	0:9b334a45a8ff	732	}
bogdanm	0:9b334a45a8ff	733
bogdanm	0:9b334a45a8ff	734	/* Set ETH HAL State to Ready */
bogdanm	0:9b334a45a8ff	735	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	736
bogdanm	0:9b334a45a8ff	737	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	738	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	/* Return function status */
bogdanm	0:9b334a45a8ff	741	return HAL_OK;
bogdanm	0:9b334a45a8ff	742	}
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	/**
bogdanm	0:9b334a45a8ff	745	* @brief Checks for received frames.
bogdanm	0:9b334a45a8ff	746	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	747	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	748	* @retval HAL status
bogdanm	0:9b334a45a8ff	749	*/
bogdanm	0:9b334a45a8ff	750	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	751	{
bogdanm	0:9b334a45a8ff	752	uint32_t framelength = 0;
bogdanm	0:9b334a45a8ff	753
bogdanm	0:9b334a45a8ff	754	/* Process Locked */
bogdanm	0:9b334a45a8ff	755	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	/* Check the ETH state to BUSY */
bogdanm	0:9b334a45a8ff	758	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760	/* Check if segment is not owned by DMA */
bogdanm	0:9b334a45a8ff	761	/* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
bogdanm	0:9b334a45a8ff	762	if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
bogdanm	0:9b334a45a8ff	763	{
bogdanm	0:9b334a45a8ff	764	/* Check if last segment */
bogdanm	0:9b334a45a8ff	765	if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
bogdanm	0:9b334a45a8ff	766	{
bogdanm	0:9b334a45a8ff	767	/* increment segment count */
bogdanm	0:9b334a45a8ff	768	(heth->RxFrameInfos).SegCount++;
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	/* Check if last segment is first segment: one segment contains the frame */
bogdanm	0:9b334a45a8ff	771	if ((heth->RxFrameInfos).SegCount == 1)
bogdanm	0:9b334a45a8ff	772	{
bogdanm	0:9b334a45a8ff	773	(heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
bogdanm	0:9b334a45a8ff	774	}
bogdanm	0:9b334a45a8ff	775
bogdanm	0:9b334a45a8ff	776	heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
bogdanm	0:9b334a45a8ff	777
bogdanm	0:9b334a45a8ff	778	/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
bogdanm	0:9b334a45a8ff	779	framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
bogdanm	0:9b334a45a8ff	780	heth->RxFrameInfos.length = framelength;
bogdanm	0:9b334a45a8ff	781
bogdanm	0:9b334a45a8ff	782	/* Get the address of the buffer start address */
bogdanm	0:9b334a45a8ff	783	heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
bogdanm	0:9b334a45a8ff	784	/* point to next descriptor */
bogdanm	0:9b334a45a8ff	785	heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	786
bogdanm	0:9b334a45a8ff	787	/* Set HAL State to Ready */
bogdanm	0:9b334a45a8ff	788	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	789
bogdanm	0:9b334a45a8ff	790	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	791	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	792
bogdanm	0:9b334a45a8ff	793	/* Return function status */
bogdanm	0:9b334a45a8ff	794	return HAL_OK;
bogdanm	0:9b334a45a8ff	795	}
bogdanm	0:9b334a45a8ff	796	/* Check if first segment */
bogdanm	0:9b334a45a8ff	797	else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
bogdanm	0:9b334a45a8ff	798	{
bogdanm	0:9b334a45a8ff	799	(heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
bogdanm	0:9b334a45a8ff	800	(heth->RxFrameInfos).LSRxDesc = NULL;
bogdanm	0:9b334a45a8ff	801	(heth->RxFrameInfos).SegCount = 1;
bogdanm	0:9b334a45a8ff	802	/* Point to next descriptor */
bogdanm	0:9b334a45a8ff	803	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	804	}
bogdanm	0:9b334a45a8ff	805	/* Check if intermediate segment */
bogdanm	0:9b334a45a8ff	806	else
bogdanm	0:9b334a45a8ff	807	{
bogdanm	0:9b334a45a8ff	808	(heth->RxFrameInfos).SegCount++;
bogdanm	0:9b334a45a8ff	809	/* Point to next descriptor */
bogdanm	0:9b334a45a8ff	810	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	811	}
bogdanm	0:9b334a45a8ff	812	}
bogdanm	0:9b334a45a8ff	813
bogdanm	0:9b334a45a8ff	814	/* Set ETH HAL State to Ready */
bogdanm	0:9b334a45a8ff	815	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	818	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	819
bogdanm	0:9b334a45a8ff	820	/* Return function status */
bogdanm	0:9b334a45a8ff	821	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	822	}
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	/**
bogdanm	0:9b334a45a8ff	825	* @brief Gets the Received frame in interrupt mode.
bogdanm	0:9b334a45a8ff	826	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	827	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	828	* @retval HAL status
bogdanm	0:9b334a45a8ff	829	*/
bogdanm	0:9b334a45a8ff	830	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	831	{
bogdanm	0:9b334a45a8ff	832	uint32_t descriptorscancounter = 0;
bogdanm	0:9b334a45a8ff	833
bogdanm	0:9b334a45a8ff	834	/* Process Locked */
bogdanm	0:9b334a45a8ff	835	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	836
bogdanm	0:9b334a45a8ff	837	/* Set ETH HAL State to BUSY */
bogdanm	0:9b334a45a8ff	838	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	/* Scan descriptors owned by CPU */
bogdanm	0:9b334a45a8ff	841	while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
bogdanm	0:9b334a45a8ff	842	{
bogdanm	0:9b334a45a8ff	843	/* Just for security */
bogdanm	0:9b334a45a8ff	844	descriptorscancounter++;
bogdanm	0:9b334a45a8ff	845
bogdanm	0:9b334a45a8ff	846	/* Check if first segment in frame */
bogdanm	0:9b334a45a8ff	847	/* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
bogdanm	0:9b334a45a8ff	848	if((heth->RxDesc->Status & (ETH_DMARXDESC_FS \| ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
bogdanm	0:9b334a45a8ff	849	{
bogdanm	0:9b334a45a8ff	850	heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
bogdanm	0:9b334a45a8ff	851	heth->RxFrameInfos.SegCount = 1;
bogdanm	0:9b334a45a8ff	852	/* Point to next descriptor */
bogdanm	0:9b334a45a8ff	853	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	854	}
bogdanm	0:9b334a45a8ff	855	/* Check if intermediate segment */
bogdanm	0:9b334a45a8ff	856	/* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
bogdanm	0:9b334a45a8ff	857	else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS \| ETH_DMARXDESC_FS)) == (uint32_t)RESET)
bogdanm	0:9b334a45a8ff	858	{
bogdanm	0:9b334a45a8ff	859	/* Increment segment count */
bogdanm	0:9b334a45a8ff	860	(heth->RxFrameInfos.SegCount)++;
bogdanm	0:9b334a45a8ff	861	/* Point to next descriptor */
bogdanm	0:9b334a45a8ff	862	heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	863	}
bogdanm	0:9b334a45a8ff	864	/* Should be last segment */
bogdanm	0:9b334a45a8ff	865	else
bogdanm	0:9b334a45a8ff	866	{
bogdanm	0:9b334a45a8ff	867	/* Last segment */
bogdanm	0:9b334a45a8ff	868	heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
bogdanm	0:9b334a45a8ff	869
bogdanm	0:9b334a45a8ff	870	/* Increment segment count */
bogdanm	0:9b334a45a8ff	871	(heth->RxFrameInfos.SegCount)++;
bogdanm	0:9b334a45a8ff	872
bogdanm	0:9b334a45a8ff	873	/* Check if last segment is first segment: one segment contains the frame */
bogdanm	0:9b334a45a8ff	874	if ((heth->RxFrameInfos.SegCount) == 1)
bogdanm	0:9b334a45a8ff	875	{
bogdanm	0:9b334a45a8ff	876	heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
bogdanm	0:9b334a45a8ff	877	}
bogdanm	0:9b334a45a8ff	878
bogdanm	0:9b334a45a8ff	879	/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
bogdanm	0:9b334a45a8ff	880	heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
bogdanm	0:9b334a45a8ff	881
bogdanm	0:9b334a45a8ff	882	/* Get the address of the buffer start address */
bogdanm	0:9b334a45a8ff	883	heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
bogdanm	0:9b334a45a8ff	884
bogdanm	0:9b334a45a8ff	885	/* Point to next descriptor */
bogdanm	0:9b334a45a8ff	886	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
bogdanm	0:9b334a45a8ff	887
bogdanm	0:9b334a45a8ff	888	/* Set HAL State to Ready */
bogdanm	0:9b334a45a8ff	889	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	890
bogdanm	0:9b334a45a8ff	891	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	892	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	893
bogdanm	0:9b334a45a8ff	894	/* Return function status */
bogdanm	0:9b334a45a8ff	895	return HAL_OK;
bogdanm	0:9b334a45a8ff	896	}
bogdanm	0:9b334a45a8ff	897	}
bogdanm	0:9b334a45a8ff	898
bogdanm	0:9b334a45a8ff	899	/* Set HAL State to Ready */
bogdanm	0:9b334a45a8ff	900	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	901
bogdanm	0:9b334a45a8ff	902	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	903	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	904
bogdanm	0:9b334a45a8ff	905	/* Return function status */
bogdanm	0:9b334a45a8ff	906	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	907	}
bogdanm	0:9b334a45a8ff	908
bogdanm	0:9b334a45a8ff	909	/**
bogdanm	0:9b334a45a8ff	910	* @brief This function handles ETH interrupt request.
bogdanm	0:9b334a45a8ff	911	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	912	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	913	* @retval HAL status
bogdanm	0:9b334a45a8ff	914	*/
bogdanm	0:9b334a45a8ff	915	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	916	{
bogdanm	0:9b334a45a8ff	917	/* Frame received */
bogdanm	0:9b334a45a8ff	918	if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
bogdanm	0:9b334a45a8ff	919	{
bogdanm	0:9b334a45a8ff	920	/* Receive complete callback */
bogdanm	0:9b334a45a8ff	921	HAL_ETH_RxCpltCallback(heth);
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	/* Clear the Eth DMA Rx IT pending bits */
bogdanm	0:9b334a45a8ff	924	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
bogdanm	0:9b334a45a8ff	925
bogdanm	0:9b334a45a8ff	926	/* Set HAL State to Ready */
bogdanm	0:9b334a45a8ff	927	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	930	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	}
bogdanm	0:9b334a45a8ff	933	/* Frame transmitted */
bogdanm	0:9b334a45a8ff	934	else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
bogdanm	0:9b334a45a8ff	935	{
bogdanm	0:9b334a45a8ff	936	/* Transfer complete callback */
bogdanm	0:9b334a45a8ff	937	HAL_ETH_TxCpltCallback(heth);
bogdanm	0:9b334a45a8ff	938
bogdanm	0:9b334a45a8ff	939	/* Clear the Eth DMA Tx IT pending bits */
bogdanm	0:9b334a45a8ff	940	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	/* Set HAL State to Ready */
bogdanm	0:9b334a45a8ff	943	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	944
bogdanm	0:9b334a45a8ff	945	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	946	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	947	}
bogdanm	0:9b334a45a8ff	948
bogdanm	0:9b334a45a8ff	949	/* Clear the interrupt flags */
bogdanm	0:9b334a45a8ff	950	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
bogdanm	0:9b334a45a8ff	951
bogdanm	0:9b334a45a8ff	952	/* ETH DMA Error */
bogdanm	0:9b334a45a8ff	953	if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
bogdanm	0:9b334a45a8ff	954	{
bogdanm	0:9b334a45a8ff	955	/* Ethernet Error callback */
bogdanm	0:9b334a45a8ff	956	HAL_ETH_ErrorCallback(heth);
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958	/* Clear the interrupt flags */
bogdanm	0:9b334a45a8ff	959	__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
bogdanm	0:9b334a45a8ff	960
bogdanm	0:9b334a45a8ff	961	/* Set HAL State to Ready */
bogdanm	0:9b334a45a8ff	962	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	963
bogdanm	0:9b334a45a8ff	964	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	965	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	966	}
bogdanm	0:9b334a45a8ff	967	}
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	/**
bogdanm	0:9b334a45a8ff	970	* @brief Tx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	971	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	972	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	973	* @retval None
bogdanm	0:9b334a45a8ff	974	*/
bogdanm	0:9b334a45a8ff	975	__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	976	{
bogdanm	0:9b334a45a8ff	977	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	978	the HAL_ETH_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	979	*/
bogdanm	0:9b334a45a8ff	980	}
bogdanm	0:9b334a45a8ff	981
bogdanm	0:9b334a45a8ff	982	/**
bogdanm	0:9b334a45a8ff	983	* @brief Rx Transfer completed callbacks.
bogdanm	0:9b334a45a8ff	984	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	985	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	986	* @retval None
bogdanm	0:9b334a45a8ff	987	*/
bogdanm	0:9b334a45a8ff	988	__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	989	{
bogdanm	0:9b334a45a8ff	990	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	991	the HAL_ETH_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	992	*/
bogdanm	0:9b334a45a8ff	993	}
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995	/**
bogdanm	0:9b334a45a8ff	996	* @brief Ethernet transfer error callbacks
bogdanm	0:9b334a45a8ff	997	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	998	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	999	* @retval None
bogdanm	0:9b334a45a8ff	1000	*/
bogdanm	0:9b334a45a8ff	1001	__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1002	{
bogdanm	0:9b334a45a8ff	1003	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1004	the HAL_ETH_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1005	*/
bogdanm	0:9b334a45a8ff	1006	}
bogdanm	0:9b334a45a8ff	1007
bogdanm	0:9b334a45a8ff	1008	/**
bogdanm	0:9b334a45a8ff	1009	* @brief Reads a PHY register
bogdanm	0:9b334a45a8ff	1010	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1011	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1012	* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
bogdanm	0:9b334a45a8ff	1013	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1014	* PHY_BCR: Transceiver Basic Control Register,
bogdanm	0:9b334a45a8ff	1015	* PHY_BSR: Transceiver Basic Status Register.
bogdanm	0:9b334a45a8ff	1016	* More PHY register could be read depending on the used PHY
bogdanm	0:9b334a45a8ff	1017	* @param RegValue: PHY register value
bogdanm	0:9b334a45a8ff	1018	* @retval HAL status
bogdanm	0:9b334a45a8ff	1019	*/
bogdanm	0:9b334a45a8ff	1020	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue)
bogdanm	0:9b334a45a8ff	1021	{
bogdanm	0:9b334a45a8ff	1022	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1023	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1024
bogdanm	0:9b334a45a8ff	1025	/* Check parameters */
bogdanm	0:9b334a45a8ff	1026	assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	/* Check the ETH peripheral state */
bogdanm	0:9b334a45a8ff	1029	if(heth->State == HAL_ETH_STATE_BUSY_RD)
bogdanm	0:9b334a45a8ff	1030	{
bogdanm	0:9b334a45a8ff	1031	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1032	}
bogdanm	0:9b334a45a8ff	1033	/* Set ETH HAL State to BUSY_RD */
bogdanm	0:9b334a45a8ff	1034	heth->State = HAL_ETH_STATE_BUSY_RD;
bogdanm	0:9b334a45a8ff	1035
bogdanm	0:9b334a45a8ff	1036	/* Get the ETHERNET MACMIIAR value */
bogdanm	0:9b334a45a8ff	1037	tmpreg = heth->Instance->MACMIIAR;
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039	/* Keep only the CSR Clock Range CR[2:0] bits value */
bogdanm	0:9b334a45a8ff	1040	tmpreg &= ~ETH_MACMIIAR_CR_MASK;
bogdanm	0:9b334a45a8ff	1041
bogdanm	0:9b334a45a8ff	1042	/* Prepare the MII address register value */
bogdanm	0:9b334a45a8ff	1043	tmpreg \|=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
bogdanm	0:9b334a45a8ff	1044	tmpreg \|=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
bogdanm	0:9b334a45a8ff	1045	tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
bogdanm	0:9b334a45a8ff	1046	tmpreg \|= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	/* Write the result value into the MII Address register */
bogdanm	0:9b334a45a8ff	1049	heth->Instance->MACMIIAR = tmpreg;
bogdanm	0:9b334a45a8ff	1050
bogdanm	0:9b334a45a8ff	1051	/* Get tick */
bogdanm	0:9b334a45a8ff	1052	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	/* Check for the Busy flag */
bogdanm	0:9b334a45a8ff	1055	while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
bogdanm	0:9b334a45a8ff	1056	{
bogdanm	0:9b334a45a8ff	1057	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	1058	if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
bogdanm	0:9b334a45a8ff	1059	{
bogdanm	0:9b334a45a8ff	1060	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1061
bogdanm	0:9b334a45a8ff	1062	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1063	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	1064
bogdanm	0:9b334a45a8ff	1065	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1066	}
bogdanm	0:9b334a45a8ff	1067
bogdanm	0:9b334a45a8ff	1068	tmpreg = heth->Instance->MACMIIAR;
bogdanm	0:9b334a45a8ff	1069	}
bogdanm	0:9b334a45a8ff	1070
bogdanm	0:9b334a45a8ff	1071	/* Get MACMIIDR value */
bogdanm	0:9b334a45a8ff	1072	*RegValue = (uint16_t)(heth->Instance->MACMIIDR);
bogdanm	0:9b334a45a8ff	1073
bogdanm	0:9b334a45a8ff	1074	/* Set ETH HAL State to READY */
bogdanm	0:9b334a45a8ff	1075	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077	/* Return function status */
bogdanm	0:9b334a45a8ff	1078	return HAL_OK;
bogdanm	0:9b334a45a8ff	1079	}
bogdanm	0:9b334a45a8ff	1080
bogdanm	0:9b334a45a8ff	1081	/**
bogdanm	0:9b334a45a8ff	1082	* @brief Writes to a PHY register.
bogdanm	0:9b334a45a8ff	1083	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1084	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1085	* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
bogdanm	0:9b334a45a8ff	1086	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1087	* PHY_BCR: Transceiver Control Register.
bogdanm	0:9b334a45a8ff	1088	* More PHY register could be written depending on the used PHY
bogdanm	0:9b334a45a8ff	1089	* @param RegValue: the value to write
bogdanm	0:9b334a45a8ff	1090	* @retval HAL status
bogdanm	0:9b334a45a8ff	1091	*/
bogdanm	0:9b334a45a8ff	1092	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
bogdanm	0:9b334a45a8ff	1093	{
bogdanm	0:9b334a45a8ff	1094	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1095	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1096
bogdanm	0:9b334a45a8ff	1097	/* Check parameters */
bogdanm	0:9b334a45a8ff	1098	assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
bogdanm	0:9b334a45a8ff	1099
bogdanm	0:9b334a45a8ff	1100	/* Check the ETH peripheral state */
bogdanm	0:9b334a45a8ff	1101	if(heth->State == HAL_ETH_STATE_BUSY_WR)
bogdanm	0:9b334a45a8ff	1102	{
bogdanm	0:9b334a45a8ff	1103	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1104	}
bogdanm	0:9b334a45a8ff	1105	/* Set ETH HAL State to BUSY_WR */
bogdanm	0:9b334a45a8ff	1106	heth->State = HAL_ETH_STATE_BUSY_WR;
bogdanm	0:9b334a45a8ff	1107
bogdanm	0:9b334a45a8ff	1108	/* Get the ETHERNET MACMIIAR value */
bogdanm	0:9b334a45a8ff	1109	tmpreg = heth->Instance->MACMIIAR;
bogdanm	0:9b334a45a8ff	1110
bogdanm	0:9b334a45a8ff	1111	/* Keep only the CSR Clock Range CR[2:0] bits value */
bogdanm	0:9b334a45a8ff	1112	tmpreg &= ~ETH_MACMIIAR_CR_MASK;
bogdanm	0:9b334a45a8ff	1113
bogdanm	0:9b334a45a8ff	1114	/* Prepare the MII register address value */
bogdanm	0:9b334a45a8ff	1115	tmpreg \|=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
bogdanm	0:9b334a45a8ff	1116	tmpreg \|=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
bogdanm	0:9b334a45a8ff	1117	tmpreg \|= ETH_MACMIIAR_MW; /* Set the write mode */
bogdanm	0:9b334a45a8ff	1118	tmpreg \|= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	/* Give the value to the MII data register */
bogdanm	0:9b334a45a8ff	1121	heth->Instance->MACMIIDR = (uint16_t)RegValue;
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	/* Write the result value into the MII Address register */
bogdanm	0:9b334a45a8ff	1124	heth->Instance->MACMIIAR = tmpreg;
bogdanm	0:9b334a45a8ff	1125
bogdanm	0:9b334a45a8ff	1126	/* Get tick */
bogdanm	0:9b334a45a8ff	1127	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1128
bogdanm	0:9b334a45a8ff	1129	/* Check for the Busy flag */
bogdanm	0:9b334a45a8ff	1130	while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
bogdanm	0:9b334a45a8ff	1131	{
bogdanm	0:9b334a45a8ff	1132	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	1133	if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
bogdanm	0:9b334a45a8ff	1134	{
bogdanm	0:9b334a45a8ff	1135	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1136
bogdanm	0:9b334a45a8ff	1137	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1138	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	1139
bogdanm	0:9b334a45a8ff	1140	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1141	}
bogdanm	0:9b334a45a8ff	1142
bogdanm	0:9b334a45a8ff	1143	tmpreg = heth->Instance->MACMIIAR;
bogdanm	0:9b334a45a8ff	1144	}
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146	/* Set ETH HAL State to READY */
bogdanm	0:9b334a45a8ff	1147	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1148
bogdanm	0:9b334a45a8ff	1149	/* Return function status */
bogdanm	0:9b334a45a8ff	1150	return HAL_OK;
bogdanm	0:9b334a45a8ff	1151	}
bogdanm	0:9b334a45a8ff	1152
bogdanm	0:9b334a45a8ff	1153	/**
bogdanm	0:9b334a45a8ff	1154	* @}
bogdanm	0:9b334a45a8ff	1155	*/
bogdanm	0:9b334a45a8ff	1156
bogdanm	0:9b334a45a8ff	1157	/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1158	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	1159	*
bogdanm	0:9b334a45a8ff	1160	@verbatim
bogdanm	0:9b334a45a8ff	1161	===============================================================================
bogdanm	0:9b334a45a8ff	1162	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	1163	===============================================================================
bogdanm	0:9b334a45a8ff	1164	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1165	(+) Enable MAC and DMA transmission and reception.
bogdanm	0:9b334a45a8ff	1166	HAL_ETH_Start();
bogdanm	0:9b334a45a8ff	1167	(+) Disable MAC and DMA transmission and reception.
bogdanm	0:9b334a45a8ff	1168	HAL_ETH_Stop();
bogdanm	0:9b334a45a8ff	1169	(+) Set the MAC configuration in runtime mode
bogdanm	0:9b334a45a8ff	1170	HAL_ETH_ConfigMAC();
bogdanm	0:9b334a45a8ff	1171	(+) Set the DMA configuration in runtime mode
bogdanm	0:9b334a45a8ff	1172	HAL_ETH_ConfigDMA();
bogdanm	0:9b334a45a8ff	1173
bogdanm	0:9b334a45a8ff	1174	@endverbatim
bogdanm	0:9b334a45a8ff	1175	* @{
bogdanm	0:9b334a45a8ff	1176	*/
bogdanm	0:9b334a45a8ff	1177
bogdanm	0:9b334a45a8ff	1178	/**
bogdanm	0:9b334a45a8ff	1179	* @brief Enables Ethernet MAC and DMA reception/transmission
bogdanm	0:9b334a45a8ff	1180	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1181	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1182	* @retval HAL status
bogdanm	0:9b334a45a8ff	1183	*/
bogdanm	0:9b334a45a8ff	1184	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1185	{
bogdanm	0:9b334a45a8ff	1186	/* Process Locked */
bogdanm	0:9b334a45a8ff	1187	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	1188
bogdanm	0:9b334a45a8ff	1189	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	1190	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1191
bogdanm	0:9b334a45a8ff	1192	/* Enable transmit state machine of the MAC for transmission on the MII */
bogdanm	0:9b334a45a8ff	1193	ETH_MACTransmissionEnable(heth);
bogdanm	0:9b334a45a8ff	1194
bogdanm	0:9b334a45a8ff	1195	/* Enable receive state machine of the MAC for reception from the MII */
bogdanm	0:9b334a45a8ff	1196	ETH_MACReceptionEnable(heth);
bogdanm	0:9b334a45a8ff	1197
bogdanm	0:9b334a45a8ff	1198	/* Flush Transmit FIFO */
bogdanm	0:9b334a45a8ff	1199	ETH_FlushTransmitFIFO(heth);
bogdanm	0:9b334a45a8ff	1200
bogdanm	0:9b334a45a8ff	1201	/* Start DMA transmission */
bogdanm	0:9b334a45a8ff	1202	ETH_DMATransmissionEnable(heth);
bogdanm	0:9b334a45a8ff	1203
bogdanm	0:9b334a45a8ff	1204	/* Start DMA reception */
bogdanm	0:9b334a45a8ff	1205	ETH_DMAReceptionEnable(heth);
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	/* Set the ETH state to READY*/
bogdanm	0:9b334a45a8ff	1208	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1211	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	/* Return function status */
bogdanm	0:9b334a45a8ff	1214	return HAL_OK;
bogdanm	0:9b334a45a8ff	1215	}
bogdanm	0:9b334a45a8ff	1216
bogdanm	0:9b334a45a8ff	1217	/**
bogdanm	0:9b334a45a8ff	1218	* @brief Stop Ethernet MAC and DMA reception/transmission
bogdanm	0:9b334a45a8ff	1219	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1220	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1221	* @retval HAL status
bogdanm	0:9b334a45a8ff	1222	*/
bogdanm	0:9b334a45a8ff	1223	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1224	{
bogdanm	0:9b334a45a8ff	1225	/* Process Locked */
bogdanm	0:9b334a45a8ff	1226	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	1227
bogdanm	0:9b334a45a8ff	1228	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	1229	heth->State = HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1230
bogdanm	0:9b334a45a8ff	1231	/* Stop DMA transmission */
bogdanm	0:9b334a45a8ff	1232	ETH_DMATransmissionDisable(heth);
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	/* Stop DMA reception */
bogdanm	0:9b334a45a8ff	1235	ETH_DMAReceptionDisable(heth);
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	/* Disable receive state machine of the MAC for reception from the MII */
bogdanm	0:9b334a45a8ff	1238	ETH_MACReceptionDisable(heth);
bogdanm	0:9b334a45a8ff	1239
bogdanm	0:9b334a45a8ff	1240	/* Flush Transmit FIFO */
bogdanm	0:9b334a45a8ff	1241	ETH_FlushTransmitFIFO(heth);
bogdanm	0:9b334a45a8ff	1242
bogdanm	0:9b334a45a8ff	1243	/* Disable transmit state machine of the MAC for transmission on the MII */
bogdanm	0:9b334a45a8ff	1244	ETH_MACTransmissionDisable(heth);
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	/* Set the ETH state*/
bogdanm	0:9b334a45a8ff	1247	heth->State = HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1248
bogdanm	0:9b334a45a8ff	1249	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1250	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	1251
bogdanm	0:9b334a45a8ff	1252	/* Return function status */
bogdanm	0:9b334a45a8ff	1253	return HAL_OK;
bogdanm	0:9b334a45a8ff	1254	}
bogdanm	0:9b334a45a8ff	1255
bogdanm	0:9b334a45a8ff	1256	/**
bogdanm	0:9b334a45a8ff	1257	* @brief Set ETH MAC Configuration.
bogdanm	0:9b334a45a8ff	1258	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1259	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1260	* @param macconf: MAC Configuration structure
bogdanm	0:9b334a45a8ff	1261	* @retval HAL status
bogdanm	0:9b334a45a8ff	1262	*/
bogdanm	0:9b334a45a8ff	1263	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf)
bogdanm	0:9b334a45a8ff	1264	{
bogdanm	0:9b334a45a8ff	1265	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267	/* Process Locked */
bogdanm	0:9b334a45a8ff	1268	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	1269
bogdanm	0:9b334a45a8ff	1270	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	1271	heth->State= HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1272
bogdanm	0:9b334a45a8ff	1273	assert_param(IS_ETH_SPEED(heth->Init.Speed));
bogdanm	0:9b334a45a8ff	1274	assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	if (macconf != NULL)
bogdanm	0:9b334a45a8ff	1277	{
bogdanm	0:9b334a45a8ff	1278	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1279	assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
bogdanm	0:9b334a45a8ff	1280	assert_param(IS_ETH_JABBER(macconf->Jabber));
bogdanm	0:9b334a45a8ff	1281	assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
bogdanm	0:9b334a45a8ff	1282	assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
bogdanm	0:9b334a45a8ff	1283	assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
bogdanm	0:9b334a45a8ff	1284	assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
bogdanm	0:9b334a45a8ff	1285	assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
bogdanm	0:9b334a45a8ff	1286	assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
bogdanm	0:9b334a45a8ff	1287	assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
bogdanm	0:9b334a45a8ff	1288	assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
bogdanm	0:9b334a45a8ff	1289	assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
bogdanm	0:9b334a45a8ff	1290	assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
bogdanm	0:9b334a45a8ff	1291	assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
bogdanm	0:9b334a45a8ff	1292	assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
bogdanm	0:9b334a45a8ff	1293	assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
bogdanm	0:9b334a45a8ff	1294	assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
bogdanm	0:9b334a45a8ff	1295	assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
bogdanm	0:9b334a45a8ff	1296	assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
bogdanm	0:9b334a45a8ff	1297	assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
bogdanm	0:9b334a45a8ff	1298	assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
bogdanm	0:9b334a45a8ff	1299	assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
bogdanm	0:9b334a45a8ff	1300	assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
bogdanm	0:9b334a45a8ff	1301	assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
bogdanm	0:9b334a45a8ff	1302	assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
bogdanm	0:9b334a45a8ff	1303	assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
bogdanm	0:9b334a45a8ff	1304	assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
bogdanm	0:9b334a45a8ff	1305	assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
bogdanm	0:9b334a45a8ff	1306
bogdanm	0:9b334a45a8ff	1307	/------------------------ ETHERNET MACCR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1308	/* Get the ETHERNET MACCR value */
bogdanm	0:9b334a45a8ff	1309	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1310	/* Clear WD, PCE, PS, TE and RE bits */
bogdanm	0:9b334a45a8ff	1311	tmpreg &= ETH_MACCR_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	1312
bogdanm	0:9b334a45a8ff	1313	tmpreg \|= (uint32_t)(macconf->Watchdog \|
bogdanm	0:9b334a45a8ff	1314	macconf->Jabber \|
bogdanm	0:9b334a45a8ff	1315	macconf->InterFrameGap \|
bogdanm	0:9b334a45a8ff	1316	macconf->CarrierSense \|
bogdanm	0:9b334a45a8ff	1317	(heth->Init).Speed \|
bogdanm	0:9b334a45a8ff	1318	macconf->ReceiveOwn \|
bogdanm	0:9b334a45a8ff	1319	macconf->LoopbackMode \|
bogdanm	0:9b334a45a8ff	1320	(heth->Init).DuplexMode \|
bogdanm	0:9b334a45a8ff	1321	macconf->ChecksumOffload \|
bogdanm	0:9b334a45a8ff	1322	macconf->RetryTransmission \|
bogdanm	0:9b334a45a8ff	1323	macconf->AutomaticPadCRCStrip \|
bogdanm	0:9b334a45a8ff	1324	macconf->BackOffLimit \|
bogdanm	0:9b334a45a8ff	1325	macconf->DeferralCheck);
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	/* Write to ETHERNET MACCR */
bogdanm	0:9b334a45a8ff	1328	(heth->Instance)->MACCR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1329
bogdanm	0:9b334a45a8ff	1330	/* Wait until the write operation will be taken into account :
bogdanm	0:9b334a45a8ff	1331	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1332	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1333	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1334	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1335
bogdanm	0:9b334a45a8ff	1336	/----------------------- ETHERNET MACFFR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1337	/* Write to ETHERNET MACFFR */
bogdanm	0:9b334a45a8ff	1338	(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll \|
bogdanm	0:9b334a45a8ff	1339	macconf->SourceAddrFilter \|
bogdanm	0:9b334a45a8ff	1340	macconf->PassControlFrames \|
bogdanm	0:9b334a45a8ff	1341	macconf->BroadcastFramesReception \|
bogdanm	0:9b334a45a8ff	1342	macconf->DestinationAddrFilter \|
bogdanm	0:9b334a45a8ff	1343	macconf->PromiscuousMode \|
bogdanm	0:9b334a45a8ff	1344	macconf->MulticastFramesFilter \|
bogdanm	0:9b334a45a8ff	1345	macconf->UnicastFramesFilter);
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	/* Wait until the write operation will be taken into account :
bogdanm	0:9b334a45a8ff	1348	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1349	tmpreg = (heth->Instance)->MACFFR;
bogdanm	0:9b334a45a8ff	1350	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1351	(heth->Instance)->MACFFR = tmpreg;
bogdanm	0:9b334a45a8ff	1352
bogdanm	0:9b334a45a8ff	1353	/--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------/
bogdanm	0:9b334a45a8ff	1354	/* Write to ETHERNET MACHTHR */
bogdanm	0:9b334a45a8ff	1355	(heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
bogdanm	0:9b334a45a8ff	1356
bogdanm	0:9b334a45a8ff	1357	/* Write to ETHERNET MACHTLR */
bogdanm	0:9b334a45a8ff	1358	(heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
bogdanm	0:9b334a45a8ff	1359	/----------------------- ETHERNET MACFCR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1360
bogdanm	0:9b334a45a8ff	1361	/* Get the ETHERNET MACFCR value */
bogdanm	0:9b334a45a8ff	1362	tmpreg = (heth->Instance)->MACFCR;
bogdanm	0:9b334a45a8ff	1363	/* Clear xx bits */
bogdanm	0:9b334a45a8ff	1364	tmpreg &= ETH_MACFCR_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	tmpreg \|= (uint32_t)((macconf->PauseTime << 16) \|
bogdanm	0:9b334a45a8ff	1367	macconf->ZeroQuantaPause \|
bogdanm	0:9b334a45a8ff	1368	macconf->PauseLowThreshold \|
bogdanm	0:9b334a45a8ff	1369	macconf->UnicastPauseFrameDetect \|
bogdanm	0:9b334a45a8ff	1370	macconf->ReceiveFlowControl \|
bogdanm	0:9b334a45a8ff	1371	macconf->TransmitFlowControl);
bogdanm	0:9b334a45a8ff	1372
bogdanm	0:9b334a45a8ff	1373	/* Write to ETHERNET MACFCR */
bogdanm	0:9b334a45a8ff	1374	(heth->Instance)->MACFCR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1375
bogdanm	0:9b334a45a8ff	1376	/* Wait until the write operation will be taken into account :
bogdanm	0:9b334a45a8ff	1377	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1378	tmpreg = (heth->Instance)->MACFCR;
bogdanm	0:9b334a45a8ff	1379	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1380	(heth->Instance)->MACFCR = tmpreg;
bogdanm	0:9b334a45a8ff	1381
bogdanm	0:9b334a45a8ff	1382	/----------------------- ETHERNET MACVLANTR Configuration -----------------/
bogdanm	0:9b334a45a8ff	1383	(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison \|
bogdanm	0:9b334a45a8ff	1384	macconf->VLANTagIdentifier);
bogdanm	0:9b334a45a8ff	1385
bogdanm	0:9b334a45a8ff	1386	/* Wait until the write operation will be taken into account :
bogdanm	0:9b334a45a8ff	1387	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1388	tmpreg = (heth->Instance)->MACVLANTR;
bogdanm	0:9b334a45a8ff	1389	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1390	(heth->Instance)->MACVLANTR = tmpreg;
bogdanm	0:9b334a45a8ff	1391	}
bogdanm	0:9b334a45a8ff	1392	else /* macconf == NULL : here we just configure Speed and Duplex mode */
bogdanm	0:9b334a45a8ff	1393	{
bogdanm	0:9b334a45a8ff	1394	/------------------------ ETHERNET MACCR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1395	/* Get the ETHERNET MACCR value */
bogdanm	0:9b334a45a8ff	1396	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1397
bogdanm	0:9b334a45a8ff	1398	/* Clear FES and DM bits */
bogdanm	0:9b334a45a8ff	1399	tmpreg &= ~((uint32_t)0x00004800);
bogdanm	0:9b334a45a8ff	1400
bogdanm	0:9b334a45a8ff	1401	tmpreg \|= (uint32_t)(heth->Init.Speed \| heth->Init.DuplexMode);
bogdanm	0:9b334a45a8ff	1402
bogdanm	0:9b334a45a8ff	1403	/* Write to ETHERNET MACCR */
bogdanm	0:9b334a45a8ff	1404	(heth->Instance)->MACCR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1405
bogdanm	0:9b334a45a8ff	1406	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1407	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1408	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1409	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1410	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1411	}
bogdanm	0:9b334a45a8ff	1412
bogdanm	0:9b334a45a8ff	1413	/* Set the ETH state to Ready */
bogdanm	0:9b334a45a8ff	1414	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1415
bogdanm	0:9b334a45a8ff	1416	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1417	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	1418
bogdanm	0:9b334a45a8ff	1419	/* Return function status */
bogdanm	0:9b334a45a8ff	1420	return HAL_OK;
bogdanm	0:9b334a45a8ff	1421	}
bogdanm	0:9b334a45a8ff	1422
bogdanm	0:9b334a45a8ff	1423	/**
bogdanm	0:9b334a45a8ff	1424	* @brief Sets ETH DMA Configuration.
bogdanm	0:9b334a45a8ff	1425	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1426	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1427	* @param dmaconf: DMA Configuration structure
bogdanm	0:9b334a45a8ff	1428	* @retval HAL status
bogdanm	0:9b334a45a8ff	1429	*/
bogdanm	0:9b334a45a8ff	1430	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf)
bogdanm	0:9b334a45a8ff	1431	{
bogdanm	0:9b334a45a8ff	1432	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	/* Process Locked */
bogdanm	0:9b334a45a8ff	1435	__HAL_LOCK(heth);
bogdanm	0:9b334a45a8ff	1436
bogdanm	0:9b334a45a8ff	1437	/* Set the ETH peripheral state to BUSY */
bogdanm	0:9b334a45a8ff	1438	heth->State= HAL_ETH_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1439
bogdanm	0:9b334a45a8ff	1440	/* Check parameters */
bogdanm	0:9b334a45a8ff	1441	assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
bogdanm	0:9b334a45a8ff	1442	assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
bogdanm	0:9b334a45a8ff	1443	assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
bogdanm	0:9b334a45a8ff	1444	assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
bogdanm	0:9b334a45a8ff	1445	assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
bogdanm	0:9b334a45a8ff	1446	assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
bogdanm	0:9b334a45a8ff	1447	assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
bogdanm	0:9b334a45a8ff	1448	assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
bogdanm	0:9b334a45a8ff	1449	assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
bogdanm	0:9b334a45a8ff	1450	assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
bogdanm	0:9b334a45a8ff	1451	assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
bogdanm	0:9b334a45a8ff	1452	assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
bogdanm	0:9b334a45a8ff	1453	assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
bogdanm	0:9b334a45a8ff	1454	assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
bogdanm	0:9b334a45a8ff	1455	assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
bogdanm	0:9b334a45a8ff	1456
bogdanm	0:9b334a45a8ff	1457	/----------------------- ETHERNET DMAOMR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1458	/* Get the ETHERNET DMAOMR value */
bogdanm	0:9b334a45a8ff	1459	tmpreg = (heth->Instance)->DMAOMR;
bogdanm	0:9b334a45a8ff	1460	/* Clear xx bits */
bogdanm	0:9b334a45a8ff	1461	tmpreg &= ETH_DMAOMR_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	1462
bogdanm	0:9b334a45a8ff	1463	tmpreg \|= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame \|
bogdanm	0:9b334a45a8ff	1464	dmaconf->ReceiveStoreForward \|
bogdanm	0:9b334a45a8ff	1465	dmaconf->FlushReceivedFrame \|
bogdanm	0:9b334a45a8ff	1466	dmaconf->TransmitStoreForward \|
bogdanm	0:9b334a45a8ff	1467	dmaconf->TransmitThresholdControl \|
bogdanm	0:9b334a45a8ff	1468	dmaconf->ForwardErrorFrames \|
bogdanm	0:9b334a45a8ff	1469	dmaconf->ForwardUndersizedGoodFrames \|
bogdanm	0:9b334a45a8ff	1470	dmaconf->ReceiveThresholdControl \|
bogdanm	0:9b334a45a8ff	1471	dmaconf->SecondFrameOperate);
bogdanm	0:9b334a45a8ff	1472
bogdanm	0:9b334a45a8ff	1473	/* Write to ETHERNET DMAOMR */
bogdanm	0:9b334a45a8ff	1474	(heth->Instance)->DMAOMR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1475
bogdanm	0:9b334a45a8ff	1476	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1477	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1478	tmpreg = (heth->Instance)->DMAOMR;
bogdanm	0:9b334a45a8ff	1479	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1480	(heth->Instance)->DMAOMR = tmpreg;
bogdanm	0:9b334a45a8ff	1481
bogdanm	0:9b334a45a8ff	1482	/----------------------- ETHERNET DMABMR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1483	(heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats \|
bogdanm	0:9b334a45a8ff	1484	dmaconf->FixedBurst \|
bogdanm	0:9b334a45a8ff	1485	dmaconf->RxDMABurstLength \| /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
bogdanm	0:9b334a45a8ff	1486	dmaconf->TxDMABurstLength \|
bogdanm	0:9b334a45a8ff	1487	(dmaconf->DescriptorSkipLength << 2) \|
bogdanm	0:9b334a45a8ff	1488	dmaconf->DMAArbitration \|
bogdanm	0:9b334a45a8ff	1489	ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
bogdanm	0:9b334a45a8ff	1490
bogdanm	0:9b334a45a8ff	1491	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1492	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1493	tmpreg = (heth->Instance)->DMABMR;
bogdanm	0:9b334a45a8ff	1494	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1495	(heth->Instance)->DMABMR = tmpreg;
bogdanm	0:9b334a45a8ff	1496
bogdanm	0:9b334a45a8ff	1497	/* Set the ETH state to Ready */
bogdanm	0:9b334a45a8ff	1498	heth->State= HAL_ETH_STATE_READY;
bogdanm	0:9b334a45a8ff	1499
bogdanm	0:9b334a45a8ff	1500	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1501	__HAL_UNLOCK(heth);
bogdanm	0:9b334a45a8ff	1502
bogdanm	0:9b334a45a8ff	1503	/* Return function status */
bogdanm	0:9b334a45a8ff	1504	return HAL_OK;
bogdanm	0:9b334a45a8ff	1505	}
bogdanm	0:9b334a45a8ff	1506
bogdanm	0:9b334a45a8ff	1507	/**
bogdanm	0:9b334a45a8ff	1508	* @}
bogdanm	0:9b334a45a8ff	1509	*/
bogdanm	0:9b334a45a8ff	1510
bogdanm	0:9b334a45a8ff	1511	/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
bogdanm	0:9b334a45a8ff	1512	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	1513	*
bogdanm	0:9b334a45a8ff	1514	@verbatim
bogdanm	0:9b334a45a8ff	1515	===============================================================================
bogdanm	0:9b334a45a8ff	1516	##### Peripheral State functions #####
bogdanm	0:9b334a45a8ff	1517	===============================================================================
bogdanm	0:9b334a45a8ff	1518	[..]
bogdanm	0:9b334a45a8ff	1519	This subsection permits to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	1520	and the data flow.
bogdanm	0:9b334a45a8ff	1521	(+) Get the ETH handle state:
bogdanm	0:9b334a45a8ff	1522	HAL_ETH_GetState();
bogdanm	0:9b334a45a8ff	1523
bogdanm	0:9b334a45a8ff	1524
bogdanm	0:9b334a45a8ff	1525	@endverbatim
bogdanm	0:9b334a45a8ff	1526	* @{
bogdanm	0:9b334a45a8ff	1527	*/
bogdanm	0:9b334a45a8ff	1528
bogdanm	0:9b334a45a8ff	1529	/**
bogdanm	0:9b334a45a8ff	1530	* @brief Return the ETH HAL state
bogdanm	0:9b334a45a8ff	1531	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1532	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1533	* @retval HAL state
bogdanm	0:9b334a45a8ff	1534	*/
bogdanm	0:9b334a45a8ff	1535	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1536	{
bogdanm	0:9b334a45a8ff	1537	/* Return ETH state */
bogdanm	0:9b334a45a8ff	1538	return heth->State;
bogdanm	0:9b334a45a8ff	1539	}
bogdanm	0:9b334a45a8ff	1540
bogdanm	0:9b334a45a8ff	1541	/**
bogdanm	0:9b334a45a8ff	1542	* @}
bogdanm	0:9b334a45a8ff	1543	*/
bogdanm	0:9b334a45a8ff	1544
bogdanm	0:9b334a45a8ff	1545	/**
bogdanm	0:9b334a45a8ff	1546	* @}
bogdanm	0:9b334a45a8ff	1547	*/
bogdanm	0:9b334a45a8ff	1548
bogdanm	0:9b334a45a8ff	1549	/** @addtogroup ETH_Private_Functions
bogdanm	0:9b334a45a8ff	1550	* @{
bogdanm	0:9b334a45a8ff	1551	*/
bogdanm	0:9b334a45a8ff	1552
bogdanm	0:9b334a45a8ff	1553	/**
bogdanm	0:9b334a45a8ff	1554	* @brief Configures Ethernet MAC and DMA with default parameters.
bogdanm	0:9b334a45a8ff	1555	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1556	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1557	* @param err: Ethernet Init error
bogdanm	0:9b334a45a8ff	1558	* @retval HAL status
bogdanm	0:9b334a45a8ff	1559	*/
bogdanm	0:9b334a45a8ff	1560	static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
bogdanm	0:9b334a45a8ff	1561	{
bogdanm	0:9b334a45a8ff	1562	ETH_MACInitTypeDef macinit;
bogdanm	0:9b334a45a8ff	1563	ETH_DMAInitTypeDef dmainit;
bogdanm	0:9b334a45a8ff	1564	uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1565
bogdanm	0:9b334a45a8ff	1566	if (err != ETH_SUCCESS) /* Auto-negotiation failed */
bogdanm	0:9b334a45a8ff	1567	{
bogdanm	0:9b334a45a8ff	1568	/* Set Ethernet duplex mode to Full-duplex */
bogdanm	0:9b334a45a8ff	1569	(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
bogdanm	0:9b334a45a8ff	1570
bogdanm	0:9b334a45a8ff	1571	/* Set Ethernet speed to 100M */
bogdanm	0:9b334a45a8ff	1572	(heth->Init).Speed = ETH_SPEED_100M;
bogdanm	0:9b334a45a8ff	1573	}
bogdanm	0:9b334a45a8ff	1574
bogdanm	0:9b334a45a8ff	1575	/* Ethernet MAC default initialization **************************************/
bogdanm	0:9b334a45a8ff	1576	macinit.Watchdog = ETH_WATCHDOG_ENABLE;
bogdanm	0:9b334a45a8ff	1577	macinit.Jabber = ETH_JABBER_ENABLE;
bogdanm	0:9b334a45a8ff	1578	macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
bogdanm	0:9b334a45a8ff	1579	macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
bogdanm	0:9b334a45a8ff	1580	macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
bogdanm	0:9b334a45a8ff	1581	macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
bogdanm	0:9b334a45a8ff	1582	if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
bogdanm	0:9b334a45a8ff	1583	{
bogdanm	0:9b334a45a8ff	1584	macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
bogdanm	0:9b334a45a8ff	1585	}
bogdanm	0:9b334a45a8ff	1586	else
bogdanm	0:9b334a45a8ff	1587	{
bogdanm	0:9b334a45a8ff	1588	macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
bogdanm	0:9b334a45a8ff	1589	}
bogdanm	0:9b334a45a8ff	1590	macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
bogdanm	0:9b334a45a8ff	1591	macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
bogdanm	0:9b334a45a8ff	1592	macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
bogdanm	0:9b334a45a8ff	1593	macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
bogdanm	0:9b334a45a8ff	1594	macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
bogdanm	0:9b334a45a8ff	1595	macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
bogdanm	0:9b334a45a8ff	1596	macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
bogdanm	0:9b334a45a8ff	1597	macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
bogdanm	0:9b334a45a8ff	1598	macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
bogdanm	0:9b334a45a8ff	1599	macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
bogdanm	0:9b334a45a8ff	1600	macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
bogdanm	0:9b334a45a8ff	1601	macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
bogdanm	0:9b334a45a8ff	1602	macinit.HashTableHigh = 0x0;
bogdanm	0:9b334a45a8ff	1603	macinit.HashTableLow = 0x0;
bogdanm	0:9b334a45a8ff	1604	macinit.PauseTime = 0x0;
bogdanm	0:9b334a45a8ff	1605	macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
bogdanm	0:9b334a45a8ff	1606	macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
bogdanm	0:9b334a45a8ff	1607	macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
bogdanm	0:9b334a45a8ff	1608	macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
bogdanm	0:9b334a45a8ff	1609	macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
bogdanm	0:9b334a45a8ff	1610	macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
bogdanm	0:9b334a45a8ff	1611	macinit.VLANTagIdentifier = 0x0;
bogdanm	0:9b334a45a8ff	1612
bogdanm	0:9b334a45a8ff	1613	/------------------------ ETHERNET MACCR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1614	/* Get the ETHERNET MACCR value */
bogdanm	0:9b334a45a8ff	1615	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1616	/* Clear WD, PCE, PS, TE and RE bits */
bogdanm	0:9b334a45a8ff	1617	tmpreg &= ETH_MACCR_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	1618	/* Set the WD bit according to ETH Watchdog value */
bogdanm	0:9b334a45a8ff	1619	/* Set the JD: bit according to ETH Jabber value */
bogdanm	0:9b334a45a8ff	1620	/* Set the IFG bit according to ETH InterFrameGap value */
bogdanm	0:9b334a45a8ff	1621	/* Set the DCRS bit according to ETH CarrierSense value */
bogdanm	0:9b334a45a8ff	1622	/* Set the FES bit according to ETH Speed value */
bogdanm	0:9b334a45a8ff	1623	/* Set the DO bit according to ETH ReceiveOwn value */
bogdanm	0:9b334a45a8ff	1624	/* Set the LM bit according to ETH LoopbackMode value */
bogdanm	0:9b334a45a8ff	1625	/* Set the DM bit according to ETH Mode value */
bogdanm	0:9b334a45a8ff	1626	/* Set the IPCO bit according to ETH ChecksumOffload value */
bogdanm	0:9b334a45a8ff	1627	/* Set the DR bit according to ETH RetryTransmission value */
bogdanm	0:9b334a45a8ff	1628	/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
bogdanm	0:9b334a45a8ff	1629	/* Set the BL bit according to ETH BackOffLimit value */
bogdanm	0:9b334a45a8ff	1630	/* Set the DC bit according to ETH DeferralCheck value */
bogdanm	0:9b334a45a8ff	1631	tmpreg \|= (uint32_t)(macinit.Watchdog \|
bogdanm	0:9b334a45a8ff	1632	macinit.Jabber \|
bogdanm	0:9b334a45a8ff	1633	macinit.InterFrameGap \|
bogdanm	0:9b334a45a8ff	1634	macinit.CarrierSense \|
bogdanm	0:9b334a45a8ff	1635	(heth->Init).Speed \|
bogdanm	0:9b334a45a8ff	1636	macinit.ReceiveOwn \|
bogdanm	0:9b334a45a8ff	1637	macinit.LoopbackMode \|
bogdanm	0:9b334a45a8ff	1638	(heth->Init).DuplexMode \|
bogdanm	0:9b334a45a8ff	1639	macinit.ChecksumOffload \|
bogdanm	0:9b334a45a8ff	1640	macinit.RetryTransmission \|
bogdanm	0:9b334a45a8ff	1641	macinit.AutomaticPadCRCStrip \|
bogdanm	0:9b334a45a8ff	1642	macinit.BackOffLimit \|
bogdanm	0:9b334a45a8ff	1643	macinit.DeferralCheck);
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	/* Write to ETHERNET MACCR */
bogdanm	0:9b334a45a8ff	1646	(heth->Instance)->MACCR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1647
bogdanm	0:9b334a45a8ff	1648	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1649	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1650	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1651	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1652	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1653
bogdanm	0:9b334a45a8ff	1654	/----------------------- ETHERNET MACFFR Configuration --------------------/
bogdanm	0:9b334a45a8ff	1655	/* Set the RA bit according to ETH ReceiveAll value */
bogdanm	0:9b334a45a8ff	1656	/* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
bogdanm	0:9b334a45a8ff	1657	/* Set the PCF bit according to ETH PassControlFrames value */
bogdanm	0:9b334a45a8ff	1658	/* Set the DBF bit according to ETH BroadcastFramesReception value */
bogdanm	0:9b334a45a8ff	1659	/* Set the DAIF bit according to ETH DestinationAddrFilter value */
bogdanm	0:9b334a45a8ff	1660	/* Set the PR bit according to ETH PromiscuousMode value */
bogdanm	0:9b334a45a8ff	1661	/* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
bogdanm	0:9b334a45a8ff	1662	/* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
bogdanm	0:9b334a45a8ff	1663	/* Write to ETHERNET MACFFR */
bogdanm	0:9b334a45a8ff	1664	(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll \|
bogdanm	0:9b334a45a8ff	1665	macinit.SourceAddrFilter \|
bogdanm	0:9b334a45a8ff	1666	macinit.PassControlFrames \|
bogdanm	0:9b334a45a8ff	1667	macinit.BroadcastFramesReception \|
bogdanm	0:9b334a45a8ff	1668	macinit.DestinationAddrFilter \|
bogdanm	0:9b334a45a8ff	1669	macinit.PromiscuousMode \|
bogdanm	0:9b334a45a8ff	1670	macinit.MulticastFramesFilter \|
bogdanm	0:9b334a45a8ff	1671	macinit.UnicastFramesFilter);
bogdanm	0:9b334a45a8ff	1672
bogdanm	0:9b334a45a8ff	1673	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1674	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1675	tmpreg = (heth->Instance)->MACFFR;
bogdanm	0:9b334a45a8ff	1676	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1677	(heth->Instance)->MACFFR = tmpreg;
bogdanm	0:9b334a45a8ff	1678
bogdanm	0:9b334a45a8ff	1679	/--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------/
bogdanm	0:9b334a45a8ff	1680	/* Write to ETHERNET MACHTHR */
bogdanm	0:9b334a45a8ff	1681	(heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
bogdanm	0:9b334a45a8ff	1682
bogdanm	0:9b334a45a8ff	1683	/* Write to ETHERNET MACHTLR */
bogdanm	0:9b334a45a8ff	1684	(heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
bogdanm	0:9b334a45a8ff	1685	/----------------------- ETHERNET MACFCR Configuration -------------------/
bogdanm	0:9b334a45a8ff	1686
bogdanm	0:9b334a45a8ff	1687	/* Get the ETHERNET MACFCR value */
bogdanm	0:9b334a45a8ff	1688	tmpreg = (heth->Instance)->MACFCR;
bogdanm	0:9b334a45a8ff	1689	/* Clear xx bits */
bogdanm	0:9b334a45a8ff	1690	tmpreg &= ETH_MACFCR_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	1691
bogdanm	0:9b334a45a8ff	1692	/* Set the PT bit according to ETH PauseTime value */
bogdanm	0:9b334a45a8ff	1693	/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
bogdanm	0:9b334a45a8ff	1694	/* Set the PLT bit according to ETH PauseLowThreshold value */
bogdanm	0:9b334a45a8ff	1695	/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
bogdanm	0:9b334a45a8ff	1696	/* Set the RFE bit according to ETH ReceiveFlowControl value */
bogdanm	0:9b334a45a8ff	1697	/* Set the TFE bit according to ETH TransmitFlowControl value */
bogdanm	0:9b334a45a8ff	1698	tmpreg \|= (uint32_t)((macinit.PauseTime << 16) \|
bogdanm	0:9b334a45a8ff	1699	macinit.ZeroQuantaPause \|
bogdanm	0:9b334a45a8ff	1700	macinit.PauseLowThreshold \|
bogdanm	0:9b334a45a8ff	1701	macinit.UnicastPauseFrameDetect \|
bogdanm	0:9b334a45a8ff	1702	macinit.ReceiveFlowControl \|
bogdanm	0:9b334a45a8ff	1703	macinit.TransmitFlowControl);
bogdanm	0:9b334a45a8ff	1704
bogdanm	0:9b334a45a8ff	1705	/* Write to ETHERNET MACFCR */
bogdanm	0:9b334a45a8ff	1706	(heth->Instance)->MACFCR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1707
bogdanm	0:9b334a45a8ff	1708	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1709	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1710	tmpreg = (heth->Instance)->MACFCR;
bogdanm	0:9b334a45a8ff	1711	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1712	(heth->Instance)->MACFCR = tmpreg;
bogdanm	0:9b334a45a8ff	1713
bogdanm	0:9b334a45a8ff	1714	/----------------------- ETHERNET MACVLANTR Configuration ----------------/
bogdanm	0:9b334a45a8ff	1715	/* Set the ETV bit according to ETH VLANTagComparison value */
bogdanm	0:9b334a45a8ff	1716	/* Set the VL bit according to ETH VLANTagIdentifier value */
bogdanm	0:9b334a45a8ff	1717	(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison \|
bogdanm	0:9b334a45a8ff	1718	macinit.VLANTagIdentifier);
bogdanm	0:9b334a45a8ff	1719
bogdanm	0:9b334a45a8ff	1720	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1721	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1722	tmpreg = (heth->Instance)->MACVLANTR;
bogdanm	0:9b334a45a8ff	1723	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1724	(heth->Instance)->MACVLANTR = tmpreg;
bogdanm	0:9b334a45a8ff	1725
bogdanm	0:9b334a45a8ff	1726	/* Ethernet DMA default initialization ************************************/
bogdanm	0:9b334a45a8ff	1727	dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
bogdanm	0:9b334a45a8ff	1728	dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
bogdanm	0:9b334a45a8ff	1729	dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
bogdanm	0:9b334a45a8ff	1730	dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
bogdanm	0:9b334a45a8ff	1731	dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
bogdanm	0:9b334a45a8ff	1732	dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
bogdanm	0:9b334a45a8ff	1733	dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
bogdanm	0:9b334a45a8ff	1734	dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
bogdanm	0:9b334a45a8ff	1735	dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
bogdanm	0:9b334a45a8ff	1736	dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
bogdanm	0:9b334a45a8ff	1737	dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
bogdanm	0:9b334a45a8ff	1738	dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
bogdanm	0:9b334a45a8ff	1739	dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
bogdanm	0:9b334a45a8ff	1740	dmainit.DescriptorSkipLength = 0x0;
bogdanm	0:9b334a45a8ff	1741	dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
bogdanm	0:9b334a45a8ff	1742
bogdanm	0:9b334a45a8ff	1743	/* Get the ETHERNET DMAOMR value */
bogdanm	0:9b334a45a8ff	1744	tmpreg = (heth->Instance)->DMAOMR;
bogdanm	0:9b334a45a8ff	1745	/* Clear xx bits */
bogdanm	0:9b334a45a8ff	1746	tmpreg &= ETH_DMAOMR_CLEAR_MASK;
bogdanm	0:9b334a45a8ff	1747
bogdanm	0:9b334a45a8ff	1748	/* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
bogdanm	0:9b334a45a8ff	1749	/* Set the RSF bit according to ETH ReceiveStoreForward value */
bogdanm	0:9b334a45a8ff	1750	/* Set the DFF bit according to ETH FlushReceivedFrame value */
bogdanm	0:9b334a45a8ff	1751	/* Set the TSF bit according to ETH TransmitStoreForward value */
bogdanm	0:9b334a45a8ff	1752	/* Set the TTC bit according to ETH TransmitThresholdControl value */
bogdanm	0:9b334a45a8ff	1753	/* Set the FEF bit according to ETH ForwardErrorFrames value */
bogdanm	0:9b334a45a8ff	1754	/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
bogdanm	0:9b334a45a8ff	1755	/* Set the RTC bit according to ETH ReceiveThresholdControl value */
bogdanm	0:9b334a45a8ff	1756	/* Set the OSF bit according to ETH SecondFrameOperate value */
bogdanm	0:9b334a45a8ff	1757	tmpreg \|= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame \|
bogdanm	0:9b334a45a8ff	1758	dmainit.ReceiveStoreForward \|
bogdanm	0:9b334a45a8ff	1759	dmainit.FlushReceivedFrame \|
bogdanm	0:9b334a45a8ff	1760	dmainit.TransmitStoreForward \|
bogdanm	0:9b334a45a8ff	1761	dmainit.TransmitThresholdControl \|
bogdanm	0:9b334a45a8ff	1762	dmainit.ForwardErrorFrames \|
bogdanm	0:9b334a45a8ff	1763	dmainit.ForwardUndersizedGoodFrames \|
bogdanm	0:9b334a45a8ff	1764	dmainit.ReceiveThresholdControl \|
bogdanm	0:9b334a45a8ff	1765	dmainit.SecondFrameOperate);
bogdanm	0:9b334a45a8ff	1766
bogdanm	0:9b334a45a8ff	1767	/* Write to ETHERNET DMAOMR */
bogdanm	0:9b334a45a8ff	1768	(heth->Instance)->DMAOMR = (uint32_t)tmpreg;
bogdanm	0:9b334a45a8ff	1769
bogdanm	0:9b334a45a8ff	1770	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1771	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1772	tmpreg = (heth->Instance)->DMAOMR;
bogdanm	0:9b334a45a8ff	1773	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1774	(heth->Instance)->DMAOMR = tmpreg;
bogdanm	0:9b334a45a8ff	1775
bogdanm	0:9b334a45a8ff	1776	/----------------------- ETHERNET DMABMR Configuration ------------------/
bogdanm	0:9b334a45a8ff	1777	/* Set the AAL bit according to ETH AddressAlignedBeats value */
bogdanm	0:9b334a45a8ff	1778	/* Set the FB bit according to ETH FixedBurst value */
bogdanm	0:9b334a45a8ff	1779	/* Set the RPBL and 4PBL bits according to ETH RxDMABurstLength value /
bogdanm	0:9b334a45a8ff	1780	/* Set the PBL and 4PBL bits according to ETH TxDMABurstLength value /
bogdanm	0:9b334a45a8ff	1781	/* Set the DSL bit according to ETH DesciptorSkipLength value */
bogdanm	0:9b334a45a8ff	1782	/* Set the PR and DA bits according to ETH DMAArbitration value */
bogdanm	0:9b334a45a8ff	1783	(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats \|
bogdanm	0:9b334a45a8ff	1784	dmainit.FixedBurst \|
bogdanm	0:9b334a45a8ff	1785	dmainit.RxDMABurstLength \| /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
bogdanm	0:9b334a45a8ff	1786	dmainit.TxDMABurstLength \|
bogdanm	0:9b334a45a8ff	1787	(dmainit.DescriptorSkipLength << 2) \|
bogdanm	0:9b334a45a8ff	1788	dmainit.DMAArbitration \|
bogdanm	0:9b334a45a8ff	1789	ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
bogdanm	0:9b334a45a8ff	1790
bogdanm	0:9b334a45a8ff	1791	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1792	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1793	tmpreg = (heth->Instance)->DMABMR;
bogdanm	0:9b334a45a8ff	1794	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1795	(heth->Instance)->DMABMR = tmpreg;
bogdanm	0:9b334a45a8ff	1796
bogdanm	0:9b334a45a8ff	1797	if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
bogdanm	0:9b334a45a8ff	1798	{
bogdanm	0:9b334a45a8ff	1799	/* Enable the Ethernet Rx Interrupt */
bogdanm	0:9b334a45a8ff	1800	__HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS \| ETH_DMA_IT_R);
bogdanm	0:9b334a45a8ff	1801	}
bogdanm	0:9b334a45a8ff	1802
bogdanm	0:9b334a45a8ff	1803	/* Initialize MAC address in ethernet MAC */
bogdanm	0:9b334a45a8ff	1804	ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
bogdanm	0:9b334a45a8ff	1805	}
bogdanm	0:9b334a45a8ff	1806
bogdanm	0:9b334a45a8ff	1807	/**
bogdanm	0:9b334a45a8ff	1808	* @brief Configures the selected MAC address.
bogdanm	0:9b334a45a8ff	1809	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1810	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1811	* @param MacAddr: The MAC address to configure
bogdanm	0:9b334a45a8ff	1812	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1813	* @arg ETH_MAC_Address0: MAC Address0
bogdanm	0:9b334a45a8ff	1814	* @arg ETH_MAC_Address1: MAC Address1
bogdanm	0:9b334a45a8ff	1815	* @arg ETH_MAC_Address2: MAC Address2
bogdanm	0:9b334a45a8ff	1816	* @arg ETH_MAC_Address3: MAC Address3
bogdanm	0:9b334a45a8ff	1817	* @param Addr: Pointer to MAC address buffer data (6 bytes)
bogdanm	0:9b334a45a8ff	1818	* @retval HAL status
bogdanm	0:9b334a45a8ff	1819	*/
bogdanm	0:9b334a45a8ff	1820	static void ETH_MACAddressConfig(ETH_HandleTypeDef heth, uint32_t MacAddr, uint8_t Addr)
bogdanm	0:9b334a45a8ff	1821	{
bogdanm	0:9b334a45a8ff	1822	uint32_t tmpreg;
bogdanm	0:9b334a45a8ff	1823
bogdanm	0:9b334a45a8ff	1824	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1825	assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
bogdanm	0:9b334a45a8ff	1826
bogdanm	0:9b334a45a8ff	1827	/* Calculate the selected MAC address high register */
bogdanm	0:9b334a45a8ff	1828	tmpreg = ((uint32_t)Addr[5] << 8) \| (uint32_t)Addr[4];
bogdanm	0:9b334a45a8ff	1829	/* Load the selected MAC address high register */
bogdanm	0:9b334a45a8ff	1830	((__IO uint32_t )((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
bogdanm	0:9b334a45a8ff	1831	/* Calculate the selected MAC address low register */
bogdanm	0:9b334a45a8ff	1832	tmpreg = ((uint32_t)Addr[3] << 24) \| ((uint32_t)Addr[2] << 16) \| ((uint32_t)Addr[1] << 8) \| Addr[0];
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834	/* Load the selected MAC address low register */
bogdanm	0:9b334a45a8ff	1835	((__IO uint32_t )((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
bogdanm	0:9b334a45a8ff	1836	}
bogdanm	0:9b334a45a8ff	1837
bogdanm	0:9b334a45a8ff	1838	/**
bogdanm	0:9b334a45a8ff	1839	* @brief Enables the MAC transmission.
bogdanm	0:9b334a45a8ff	1840	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1841	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1842	* @retval None
bogdanm	0:9b334a45a8ff	1843	*/
bogdanm	0:9b334a45a8ff	1844	static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1845	{
bogdanm	0:9b334a45a8ff	1846	__IO uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1847
bogdanm	0:9b334a45a8ff	1848	/* Enable the MAC transmission */
bogdanm	0:9b334a45a8ff	1849	(heth->Instance)->MACCR \|= ETH_MACCR_TE;
bogdanm	0:9b334a45a8ff	1850
bogdanm	0:9b334a45a8ff	1851	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1852	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1853	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1854	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1855	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1856	}
bogdanm	0:9b334a45a8ff	1857
bogdanm	0:9b334a45a8ff	1858	/**
bogdanm	0:9b334a45a8ff	1859	* @brief Disables the MAC transmission.
bogdanm	0:9b334a45a8ff	1860	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1861	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1862	* @retval None
bogdanm	0:9b334a45a8ff	1863	*/
bogdanm	0:9b334a45a8ff	1864	static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1865	{
bogdanm	0:9b334a45a8ff	1866	__IO uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1867
bogdanm	0:9b334a45a8ff	1868	/* Disable the MAC transmission */
bogdanm	0:9b334a45a8ff	1869	(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
bogdanm	0:9b334a45a8ff	1870
bogdanm	0:9b334a45a8ff	1871	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1872	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1873	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1874	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1875	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1876	}
bogdanm	0:9b334a45a8ff	1877
bogdanm	0:9b334a45a8ff	1878	/**
bogdanm	0:9b334a45a8ff	1879	* @brief Enables the MAC reception.
bogdanm	0:9b334a45a8ff	1880	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1881	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1882	* @retval None
bogdanm	0:9b334a45a8ff	1883	*/
bogdanm	0:9b334a45a8ff	1884	static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1885	{
bogdanm	0:9b334a45a8ff	1886	__IO uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1887
bogdanm	0:9b334a45a8ff	1888	/* Enable the MAC reception */
bogdanm	0:9b334a45a8ff	1889	(heth->Instance)->MACCR \|= ETH_MACCR_RE;
bogdanm	0:9b334a45a8ff	1890
bogdanm	0:9b334a45a8ff	1891	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1892	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1893	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1894	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1895	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1896	}
bogdanm	0:9b334a45a8ff	1897
bogdanm	0:9b334a45a8ff	1898	/**
bogdanm	0:9b334a45a8ff	1899	* @brief Disables the MAC reception.
bogdanm	0:9b334a45a8ff	1900	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1901	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1902	* @retval None
bogdanm	0:9b334a45a8ff	1903	*/
bogdanm	0:9b334a45a8ff	1904	static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1905	{
bogdanm	0:9b334a45a8ff	1906	__IO uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1907
bogdanm	0:9b334a45a8ff	1908	/* Disable the MAC reception */
bogdanm	0:9b334a45a8ff	1909	(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
bogdanm	0:9b334a45a8ff	1910
bogdanm	0:9b334a45a8ff	1911	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1912	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1913	tmpreg = (heth->Instance)->MACCR;
bogdanm	0:9b334a45a8ff	1914	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1915	(heth->Instance)->MACCR = tmpreg;
bogdanm	0:9b334a45a8ff	1916	}
bogdanm	0:9b334a45a8ff	1917
bogdanm	0:9b334a45a8ff	1918	/**
bogdanm	0:9b334a45a8ff	1919	* @brief Enables the DMA transmission.
bogdanm	0:9b334a45a8ff	1920	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1921	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1922	* @retval None
bogdanm	0:9b334a45a8ff	1923	*/
bogdanm	0:9b334a45a8ff	1924	static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1925	{
bogdanm	0:9b334a45a8ff	1926	/* Enable the DMA transmission */
bogdanm	0:9b334a45a8ff	1927	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_ST;
bogdanm	0:9b334a45a8ff	1928	}
bogdanm	0:9b334a45a8ff	1929
bogdanm	0:9b334a45a8ff	1930	/**
bogdanm	0:9b334a45a8ff	1931	* @brief Disables the DMA transmission.
bogdanm	0:9b334a45a8ff	1932	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1933	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1934	* @retval None
bogdanm	0:9b334a45a8ff	1935	*/
bogdanm	0:9b334a45a8ff	1936	static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1937	{
bogdanm	0:9b334a45a8ff	1938	/* Disable the DMA transmission */
bogdanm	0:9b334a45a8ff	1939	(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
bogdanm	0:9b334a45a8ff	1940	}
bogdanm	0:9b334a45a8ff	1941
bogdanm	0:9b334a45a8ff	1942	/**
bogdanm	0:9b334a45a8ff	1943	* @brief Enables the DMA reception.
bogdanm	0:9b334a45a8ff	1944	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1945	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1946	* @retval None
bogdanm	0:9b334a45a8ff	1947	*/
bogdanm	0:9b334a45a8ff	1948	static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1949	{
bogdanm	0:9b334a45a8ff	1950	/* Enable the DMA reception */
bogdanm	0:9b334a45a8ff	1951	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_SR;
bogdanm	0:9b334a45a8ff	1952	}
bogdanm	0:9b334a45a8ff	1953
bogdanm	0:9b334a45a8ff	1954	/**
bogdanm	0:9b334a45a8ff	1955	* @brief Disables the DMA reception.
bogdanm	0:9b334a45a8ff	1956	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1957	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1958	* @retval None
bogdanm	0:9b334a45a8ff	1959	*/
bogdanm	0:9b334a45a8ff	1960	static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1961	{
bogdanm	0:9b334a45a8ff	1962	/* Disable the DMA reception */
bogdanm	0:9b334a45a8ff	1963	(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
bogdanm	0:9b334a45a8ff	1964	}
bogdanm	0:9b334a45a8ff	1965
bogdanm	0:9b334a45a8ff	1966	/**
bogdanm	0:9b334a45a8ff	1967	* @brief Clears the ETHERNET transmit FIFO.
bogdanm	0:9b334a45a8ff	1968	* @param heth: pointer to a ETH_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1969	* the configuration information for ETHERNET module
bogdanm	0:9b334a45a8ff	1970	* @retval None
bogdanm	0:9b334a45a8ff	1971	*/
bogdanm	0:9b334a45a8ff	1972	static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
bogdanm	0:9b334a45a8ff	1973	{
bogdanm	0:9b334a45a8ff	1974	__IO uint32_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	1975
bogdanm	0:9b334a45a8ff	1976	/* Set the Flush Transmit FIFO bit */
bogdanm	0:9b334a45a8ff	1977	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_FTF;
bogdanm	0:9b334a45a8ff	1978
bogdanm	0:9b334a45a8ff	1979	/* Wait until the write operation will be taken into account:
bogdanm	0:9b334a45a8ff	1980	at least four TX_CLK/RX_CLK clock cycles */
bogdanm	0:9b334a45a8ff	1981	tmpreg = (heth->Instance)->DMAOMR;
bogdanm	0:9b334a45a8ff	1982	HAL_Delay(ETH_REG_WRITE_DELAY);
bogdanm	0:9b334a45a8ff	1983	(heth->Instance)->DMAOMR = tmpreg;
bogdanm	0:9b334a45a8ff	1984	}
bogdanm	0:9b334a45a8ff	1985
bogdanm	0:9b334a45a8ff	1986	/**
bogdanm	0:9b334a45a8ff	1987	* @}
bogdanm	0:9b334a45a8ff	1988	*/
bogdanm	0:9b334a45a8ff	1989
bogdanm	0:9b334a45a8ff	1990	#endif /* HAL_ETH_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1991	/**
bogdanm	0:9b334a45a8ff	1992	* @}
bogdanm	0:9b334a45a8ff	1993	*/
bogdanm	0:9b334a45a8ff	1994
bogdanm	0:9b334a45a8ff	1995	#endif /* STM32F107xC */
bogdanm	0:9b334a45a8ff	1996	/**
bogdanm	0:9b334a45a8ff	1997	* @}
bogdanm	0:9b334a45a8ff	1998	*/
bogdanm	0:9b334a45a8ff	1999
bogdanm	0:9b334a45a8ff	2000	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_eth.c@0:9b334a45a8ff, 2015-10-01 (annotated)

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