en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
124:6a4a5b7d7324
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file system_stm32f1xx.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V4.0.0
bogdanm 0:9b334a45a8ff 6 * @date 16-December-2014
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * 1. This file provides two functions and one global variable to be called from
bogdanm 0:9b334a45a8ff 10 * user application:
bogdanm 0:9b334a45a8ff 11 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
bogdanm 0:9b334a45a8ff 12 * factors, AHB/APBx prescalers and Flash settings).
bogdanm 0:9b334a45a8ff 13 * This function is called at startup just after reset and
bogdanm 0:9b334a45a8ff 14 * before branch to main program. This call is made inside
bogdanm 0:9b334a45a8ff 15 * the "startup_stm32f1xx_xx.s" file.
bogdanm 0:9b334a45a8ff 16 *
bogdanm 0:9b334a45a8ff 17 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
bogdanm 0:9b334a45a8ff 18 * by the user application to setup the SysTick
bogdanm 0:9b334a45a8ff 19 * timer or configure other parameters.
bogdanm 0:9b334a45a8ff 20 *
bogdanm 0:9b334a45a8ff 21 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
bogdanm 0:9b334a45a8ff 22 * be called whenever the core clock is changed
bogdanm 0:9b334a45a8ff 23 * during program execution.
bogdanm 0:9b334a45a8ff 24 *
bogdanm 0:9b334a45a8ff 25 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
bogdanm 0:9b334a45a8ff 26 * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
bogdanm 0:9b334a45a8ff 27 * configure the system clock before to branch to main program.
bogdanm 0:9b334a45a8ff 28 *
bogdanm 0:9b334a45a8ff 29 * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
bogdanm 0:9b334a45a8ff 30 * the product used), refer to "HSE_VALUE".
bogdanm 0:9b334a45a8ff 31 * When HSE is used as system clock source, directly or through PLL, and you
bogdanm 0:9b334a45a8ff 32 * are using different crystal you have to adapt the HSE value to your own
bogdanm 0:9b334a45a8ff 33 * configuration.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 * This file configures the system clock as follows:
bogdanm 0:9b334a45a8ff 36 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 37 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
bogdanm 0:9b334a45a8ff 38 * | (external 8 MHz clock) | (internal 8 MHz)
bogdanm 0:9b334a45a8ff 39 * | 2- PLL_HSE_XTAL |
bogdanm 0:9b334a45a8ff 40 * | (external 8 MHz xtal) |
bogdanm 0:9b334a45a8ff 41 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 42 * SYSCLK(MHz) | 24 | 24
bogdanm 0:9b334a45a8ff 43 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 44 * AHBCLK (MHz) | 24 | 24
bogdanm 0:9b334a45a8ff 45 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 46 * APB1CLK (MHz) | 24 | 24
bogdanm 0:9b334a45a8ff 47 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 48 * APB2CLK (MHz) | 24 | 24
bogdanm 0:9b334a45a8ff 49 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 50 ******************************************************************************
bogdanm 0:9b334a45a8ff 51 * @attention
bogdanm 0:9b334a45a8ff 52 *
bogdanm 0:9b334a45a8ff 53 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 54 *
bogdanm 0:9b334a45a8ff 55 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 56 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 57 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 58 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 59 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 60 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 61 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 62 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 63 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 64 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 65 *
bogdanm 0:9b334a45a8ff 66 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 67 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 69 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 72 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 73 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 74 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 75 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 76 *
bogdanm 0:9b334a45a8ff 77 ******************************************************************************
bogdanm 0:9b334a45a8ff 78 */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 /** @addtogroup CMSIS
bogdanm 0:9b334a45a8ff 81 * @{
bogdanm 0:9b334a45a8ff 82 */
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 /** @addtogroup stm32f1xx_system
bogdanm 0:9b334a45a8ff 85 * @{
bogdanm 0:9b334a45a8ff 86 */
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 /** @addtogroup STM32F1xx_System_Private_Includes
bogdanm 0:9b334a45a8ff 89 * @{
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 #include "stm32f1xx.h"
bogdanm 0:9b334a45a8ff 93 #include "hal_tick.h"
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 /**
bogdanm 0:9b334a45a8ff 96 * @}
bogdanm 0:9b334a45a8ff 97 */
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
bogdanm 0:9b334a45a8ff 100 * @{
bogdanm 0:9b334a45a8ff 101 */
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /**
bogdanm 0:9b334a45a8ff 104 * @}
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 /** @addtogroup STM32F1xx_System_Private_Defines
bogdanm 0:9b334a45a8ff 108 * @{
bogdanm 0:9b334a45a8ff 109 */
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 #if !defined (HSE_VALUE)
bogdanm 0:9b334a45a8ff 112 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
bogdanm 0:9b334a45a8ff 113 This value can be provided and adapted by the user application. */
bogdanm 0:9b334a45a8ff 114 #endif /* HSE_VALUE */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 #if !defined (HSI_VALUE)
bogdanm 0:9b334a45a8ff 117 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
bogdanm 0:9b334a45a8ff 118 This value can be provided and adapted by the user application. */
bogdanm 0:9b334a45a8ff 119 #endif /* HSI_VALUE */
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 /*!< Uncomment the following line if you need to use external SRAM */
bogdanm 0:9b334a45a8ff 122 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
bogdanm 0:9b334a45a8ff 123 /* #define DATA_IN_ExtSRAM */
bogdanm 0:9b334a45a8ff 124 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 /*!< Uncomment the following line if you need to relocate your vector Table in
bogdanm 0:9b334a45a8ff 127 Internal SRAM. */
bogdanm 0:9b334a45a8ff 128 /* #define VECT_TAB_SRAM */
bogdanm 0:9b334a45a8ff 129 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
bogdanm 0:9b334a45a8ff 130 This value must be a multiple of 0x200. */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 /**
bogdanm 0:9b334a45a8ff 134 * @}
bogdanm 0:9b334a45a8ff 135 */
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /** @addtogroup STM32F1xx_System_Private_Macros
bogdanm 0:9b334a45a8ff 138 * @{
bogdanm 0:9b334a45a8ff 139 */
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
bogdanm 0:9b334a45a8ff 142 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
bogdanm 0:9b334a45a8ff 143 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 /**
bogdanm 0:9b334a45a8ff 146 * @}
bogdanm 0:9b334a45a8ff 147 */
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 /** @addtogroup STM32F1xx_System_Private_Variables
bogdanm 0:9b334a45a8ff 150 * @{
bogdanm 0:9b334a45a8ff 151 */
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 /*******************************************************************************
bogdanm 0:9b334a45a8ff 154 * Clock Definitions
bogdanm 0:9b334a45a8ff 155 *******************************************************************************/
bogdanm 0:9b334a45a8ff 156 #if defined(STM32F100xB) ||defined(STM32F100xE)
bogdanm 0:9b334a45a8ff 157 uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */
bogdanm 0:9b334a45a8ff 158 #else /*!< HSI Selected as System Clock source */
bogdanm 0:9b334a45a8ff 159 uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */
bogdanm 0:9b334a45a8ff 160 #endif
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm 0:9b334a45a8ff 163 /**
bogdanm 0:9b334a45a8ff 164 * @}
bogdanm 0:9b334a45a8ff 165 */
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
bogdanm 0:9b334a45a8ff 168 * @{
bogdanm 0:9b334a45a8ff 169 */
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
bogdanm 0:9b334a45a8ff 172 #ifdef DATA_IN_ExtSRAM
bogdanm 0:9b334a45a8ff 173 static void SystemInit_ExtMemCtl(void);
bogdanm 0:9b334a45a8ff 174 #endif /* DATA_IN_ExtSRAM */
bogdanm 0:9b334a45a8ff 175 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 178 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
bogdanm 0:9b334a45a8ff 179 #endif
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 uint8_t SetSysClock_PLL_HSI(void);
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /**
bogdanm 0:9b334a45a8ff 184 * @}
bogdanm 0:9b334a45a8ff 185 */
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 /** @addtogroup STM32F1xx_System_Private_Functions
bogdanm 0:9b334a45a8ff 188 * @{
bogdanm 0:9b334a45a8ff 189 */
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 /**
bogdanm 0:9b334a45a8ff 192 * @brief Setup the microcontroller system
bogdanm 0:9b334a45a8ff 193 * Initialize the Embedded Flash Interface, the PLL and update the
bogdanm 0:9b334a45a8ff 194 * SystemCoreClock variable.
bogdanm 0:9b334a45a8ff 195 * @note This function should be used only after reset.
bogdanm 0:9b334a45a8ff 196 * @param None
bogdanm 0:9b334a45a8ff 197 * @retval None
bogdanm 0:9b334a45a8ff 198 */
bogdanm 0:9b334a45a8ff 199 void SystemInit (void)
bogdanm 0:9b334a45a8ff 200 {
bogdanm 0:9b334a45a8ff 201 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
bogdanm 0:9b334a45a8ff 202 /* Set HSION bit */
bogdanm 0:9b334a45a8ff 203 RCC->CR |= (uint32_t)0x00000001;
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
bogdanm 0:9b334a45a8ff 206 #if !defined(STM32F105xC) && !defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 207 RCC->CFGR &= (uint32_t)0xF8FF0000;
bogdanm 0:9b334a45a8ff 208 #else
bogdanm 0:9b334a45a8ff 209 RCC->CFGR &= (uint32_t)0xF0FF0000;
bogdanm 0:9b334a45a8ff 210 #endif /* STM32F105xC */
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 /* Reset HSEON, CSSON and PLLON bits */
bogdanm 0:9b334a45a8ff 213 RCC->CR &= (uint32_t)0xFEF6FFFF;
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /* Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 216 RCC->CR &= (uint32_t)0xFFFBFFFF;
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
bogdanm 0:9b334a45a8ff 219 RCC->CFGR &= (uint32_t)0xFF80FFFF;
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 #if defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 222 /* Reset PLL2ON and PLL3ON bits */
bogdanm 0:9b334a45a8ff 223 RCC->CR &= (uint32_t)0xEBFFFFFF;
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 /* Disable all interrupts and clear pending bits */
bogdanm 0:9b334a45a8ff 226 RCC->CIR = 0x00FF0000;
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /* Reset CFGR2 register */
bogdanm 0:9b334a45a8ff 229 RCC->CFGR2 = 0x00000000;
bogdanm 0:9b334a45a8ff 230 #elif defined(STM32F100xB) || defined(STM32F100xE)
bogdanm 0:9b334a45a8ff 231 /* Disable all interrupts and clear pending bits */
bogdanm 0:9b334a45a8ff 232 RCC->CIR = 0x009F0000;
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 /* Reset CFGR2 register */
bogdanm 0:9b334a45a8ff 235 RCC->CFGR2 = 0x00000000;
bogdanm 0:9b334a45a8ff 236 #else
bogdanm 0:9b334a45a8ff 237 /* Disable all interrupts and clear pending bits */
bogdanm 0:9b334a45a8ff 238 RCC->CIR = 0x009F0000;
bogdanm 0:9b334a45a8ff 239 #endif /* STM32F105xC */
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
bogdanm 0:9b334a45a8ff 242 #ifdef DATA_IN_ExtSRAM
bogdanm 0:9b334a45a8ff 243 SystemInit_ExtMemCtl();
bogdanm 0:9b334a45a8ff 244 #endif /* DATA_IN_ExtSRAM */
bogdanm 0:9b334a45a8ff 245 #endif
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 #ifdef VECT_TAB_SRAM
bogdanm 0:9b334a45a8ff 248 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
bogdanm 0:9b334a45a8ff 249 #else
bogdanm 0:9b334a45a8ff 250 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
bogdanm 0:9b334a45a8ff 251 #endif
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 /* Configure the Cube driver */
bogdanm 0:9b334a45a8ff 254 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
bogdanm 0:9b334a45a8ff 255 HAL_Init();
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /* Configure the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 258 AHB/APBx prescalers and Flash settings */
bogdanm 0:9b334a45a8ff 259 SetSysClock();
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 /* Reset the timer to avoid issues after the RAM initialization */
bogdanm 0:9b334a45a8ff 262 TIM_MST_RESET_ON;
bogdanm 0:9b334a45a8ff 263 TIM_MST_RESET_OFF;
bogdanm 0:9b334a45a8ff 264 }
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 /**
bogdanm 0:9b334a45a8ff 267 * @brief Update SystemCoreClock variable according to Clock Register Values.
bogdanm 0:9b334a45a8ff 268 * The SystemCoreClock variable contains the core clock (HCLK), it can
bogdanm 0:9b334a45a8ff 269 * be used by the user application to setup the SysTick timer or configure
bogdanm 0:9b334a45a8ff 270 * other parameters.
bogdanm 0:9b334a45a8ff 271 *
bogdanm 0:9b334a45a8ff 272 * @note Each time the core clock (HCLK) changes, this function must be called
bogdanm 0:9b334a45a8ff 273 * to update SystemCoreClock variable value. Otherwise, any configuration
bogdanm 0:9b334a45a8ff 274 * based on this variable will be incorrect.
bogdanm 0:9b334a45a8ff 275 *
bogdanm 0:9b334a45a8ff 276 * @note - The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 277 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 278 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 279 *
bogdanm 0:9b334a45a8ff 280 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 281 *
bogdanm 0:9b334a45a8ff 282 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 283 *
bogdanm 0:9b334a45a8ff 284 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 285 * or HSI_VALUE(*) multiplied by the PLL factors.
bogdanm 0:9b334a45a8ff 286 *
bogdanm 0:9b334a45a8ff 287 * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
bogdanm 0:9b334a45a8ff 288 * 8 MHz) but the real value may vary depending on the variations
bogdanm 0:9b334a45a8ff 289 * in voltage and temperature.
bogdanm 0:9b334a45a8ff 290 *
bogdanm 0:9b334a45a8ff 291 * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
bogdanm 0:9b334a45a8ff 292 * 8 MHz or 25 MHz, depending on the product used), user has to ensure
bogdanm 0:9b334a45a8ff 293 * that HSE_VALUE is same as the real frequency of the crystal used.
bogdanm 0:9b334a45a8ff 294 * Otherwise, this function may have wrong result.
bogdanm 0:9b334a45a8ff 295 *
bogdanm 0:9b334a45a8ff 296 * - The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 297 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 298 * @param None
bogdanm 0:9b334a45a8ff 299 * @retval None
bogdanm 0:9b334a45a8ff 300 */
bogdanm 0:9b334a45a8ff 301 void SystemCoreClockUpdate (void)
bogdanm 0:9b334a45a8ff 302 {
bogdanm 0:9b334a45a8ff 303 uint32_t tmp = 0, pllmull = 0, pllsource = 0;
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 #if defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 306 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
bogdanm 0:9b334a45a8ff 307 #endif /* STM32F105xC */
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 #if defined(STM32F100xB) || defined(STM32F100xE)
bogdanm 0:9b334a45a8ff 310 uint32_t prediv1factor = 0;
bogdanm 0:9b334a45a8ff 311 #endif /* STM32F100xB or STM32F100xE */
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 314 tmp = RCC->CFGR & RCC_CFGR_SWS;
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 switch (tmp)
bogdanm 0:9b334a45a8ff 317 {
bogdanm 0:9b334a45a8ff 318 case 0x00: /* HSI used as system clock */
bogdanm 0:9b334a45a8ff 319 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 320 break;
bogdanm 0:9b334a45a8ff 321 case 0x04: /* HSE used as system clock */
bogdanm 0:9b334a45a8ff 322 SystemCoreClock = HSE_VALUE;
bogdanm 0:9b334a45a8ff 323 break;
bogdanm 0:9b334a45a8ff 324 case 0x08: /* PLL used as system clock */
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /* Get PLL clock source and multiplication factor ----------------------*/
bogdanm 0:9b334a45a8ff 327 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
bogdanm 0:9b334a45a8ff 328 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 #if !defined(STM32F105xC) && !defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 331 pllmull = ( pllmull >> 18) + 2;
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 if (pllsource == 0x00)
bogdanm 0:9b334a45a8ff 334 {
bogdanm 0:9b334a45a8ff 335 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
bogdanm 0:9b334a45a8ff 336 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
bogdanm 0:9b334a45a8ff 337 }
bogdanm 0:9b334a45a8ff 338 else
bogdanm 0:9b334a45a8ff 339 {
bogdanm 0:9b334a45a8ff 340 #if defined(STM32F100xB) || defined(STM32F100xE)
bogdanm 0:9b334a45a8ff 341 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
bogdanm 0:9b334a45a8ff 342 /* HSE oscillator clock selected as PREDIV1 clock entry */
bogdanm 0:9b334a45a8ff 343 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
bogdanm 0:9b334a45a8ff 344 #else
bogdanm 0:9b334a45a8ff 345 /* HSE selected as PLL clock entry */
bogdanm 0:9b334a45a8ff 346 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 347 {/* HSE oscillator clock divided by 2 */
bogdanm 0:9b334a45a8ff 348 SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
bogdanm 0:9b334a45a8ff 349 }
bogdanm 0:9b334a45a8ff 350 else
bogdanm 0:9b334a45a8ff 351 {
bogdanm 0:9b334a45a8ff 352 SystemCoreClock = HSE_VALUE * pllmull;
bogdanm 0:9b334a45a8ff 353 }
bogdanm 0:9b334a45a8ff 354 #endif
bogdanm 0:9b334a45a8ff 355 }
bogdanm 0:9b334a45a8ff 356 #else
bogdanm 0:9b334a45a8ff 357 pllmull = pllmull >> 18;
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 if (pllmull != 0x0D)
bogdanm 0:9b334a45a8ff 360 {
bogdanm 0:9b334a45a8ff 361 pllmull += 2;
bogdanm 0:9b334a45a8ff 362 }
bogdanm 0:9b334a45a8ff 363 else
bogdanm 0:9b334a45a8ff 364 { /* PLL multiplication factor = PLL input clock * 6.5 */
bogdanm 0:9b334a45a8ff 365 pllmull = 13 / 2;
bogdanm 0:9b334a45a8ff 366 }
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 if (pllsource == 0x00)
bogdanm 0:9b334a45a8ff 369 {
bogdanm 0:9b334a45a8ff 370 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
bogdanm 0:9b334a45a8ff 371 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
bogdanm 0:9b334a45a8ff 372 }
bogdanm 0:9b334a45a8ff 373 else
bogdanm 0:9b334a45a8ff 374 {/* PREDIV1 selected as PLL clock entry */
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /* Get PREDIV1 clock source and division factor */
bogdanm 0:9b334a45a8ff 377 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
bogdanm 0:9b334a45a8ff 378 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 if (prediv1source == 0)
bogdanm 0:9b334a45a8ff 381 {
bogdanm 0:9b334a45a8ff 382 /* HSE oscillator clock selected as PREDIV1 clock entry */
bogdanm 0:9b334a45a8ff 383 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
bogdanm 0:9b334a45a8ff 384 }
bogdanm 0:9b334a45a8ff 385 else
bogdanm 0:9b334a45a8ff 386 {/* PLL2 clock selected as PREDIV1 clock entry */
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 /* Get PREDIV2 division factor and PLL2 multiplication factor */
bogdanm 0:9b334a45a8ff 389 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
bogdanm 0:9b334a45a8ff 390 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
bogdanm 0:9b334a45a8ff 391 SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
bogdanm 0:9b334a45a8ff 392 }
bogdanm 0:9b334a45a8ff 393 }
bogdanm 0:9b334a45a8ff 394 #endif /* STM32F105xC */
bogdanm 0:9b334a45a8ff 395 break;
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 default:
bogdanm 0:9b334a45a8ff 398 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 399 break;
bogdanm 0:9b334a45a8ff 400 }
bogdanm 0:9b334a45a8ff 401
bogdanm 0:9b334a45a8ff 402 /* Compute HCLK clock frequency ----------------*/
bogdanm 0:9b334a45a8ff 403 /* Get HCLK prescaler */
bogdanm 0:9b334a45a8ff 404 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
bogdanm 0:9b334a45a8ff 405 /* HCLK clock frequency */
bogdanm 0:9b334a45a8ff 406 SystemCoreClock >>= tmp;
bogdanm 0:9b334a45a8ff 407 }
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
bogdanm 0:9b334a45a8ff 410 /**
bogdanm 0:9b334a45a8ff 411 * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
bogdanm 0:9b334a45a8ff 412 * before jump to __main
bogdanm 0:9b334a45a8ff 413 * @param None
bogdanm 0:9b334a45a8ff 414 * @retval None
bogdanm 0:9b334a45a8ff 415 */
bogdanm 0:9b334a45a8ff 416 #ifdef DATA_IN_ExtSRAM
bogdanm 0:9b334a45a8ff 417 /**
bogdanm 0:9b334a45a8ff 418 * @brief Setup the external memory controller.
bogdanm 0:9b334a45a8ff 419 * Called in startup_stm32f1xx_xx.s/.c before jump to main.
bogdanm 0:9b334a45a8ff 420 * This function configures the external SRAM mounted on STM3210E-EVAL
bogdanm 0:9b334a45a8ff 421 * board (STM32 High density devices). This SRAM will be used as program
bogdanm 0:9b334a45a8ff 422 * data memory (including heap and stack).
bogdanm 0:9b334a45a8ff 423 * @param None
bogdanm 0:9b334a45a8ff 424 * @retval None
bogdanm 0:9b334a45a8ff 425 */
bogdanm 0:9b334a45a8ff 426 void SystemInit_ExtMemCtl(void)
bogdanm 0:9b334a45a8ff 427 {
bogdanm 0:9b334a45a8ff 428 __IO uint32_t tmpreg;
bogdanm 0:9b334a45a8ff 429 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
bogdanm 0:9b334a45a8ff 430 required, then adjust the Register Addresses */
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /* Enable FSMC clock */
bogdanm 0:9b334a45a8ff 433 RCC->AHBENR = 0x00000114;
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 /* Delay after an RCC peripheral clock enabling */
bogdanm 0:9b334a45a8ff 436 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
bogdanm 0:9b334a45a8ff 439 RCC->APB2ENR = 0x000001E0;
bogdanm 0:9b334a45a8ff 440
bogdanm 0:9b334a45a8ff 441 /* Delay after an RCC peripheral clock enabling */
bogdanm 0:9b334a45a8ff 442 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 (void)(tmpreg);
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
bogdanm 0:9b334a45a8ff 447 /*---------------- SRAM Address lines configuration -------------------------*/
bogdanm 0:9b334a45a8ff 448 /*---------------- NOE and NWE configuration --------------------------------*/
bogdanm 0:9b334a45a8ff 449 /*---------------- NE3 configuration ----------------------------------------*/
bogdanm 0:9b334a45a8ff 450 /*---------------- NBL0, NBL1 configuration ---------------------------------*/
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 GPIOD->CRL = 0x44BB44BB;
bogdanm 0:9b334a45a8ff 453 GPIOD->CRH = 0xBBBBBBBB;
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 GPIOE->CRL = 0xB44444BB;
bogdanm 0:9b334a45a8ff 456 GPIOE->CRH = 0xBBBBBBBB;
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 GPIOF->CRL = 0x44BBBBBB;
bogdanm 0:9b334a45a8ff 459 GPIOF->CRH = 0xBBBB4444;
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 GPIOG->CRL = 0x44BBBBBB;
bogdanm 0:9b334a45a8ff 462 GPIOG->CRH = 0x444B4B44;
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /*---------------- FSMC Configuration ---------------------------------------*/
bogdanm 0:9b334a45a8ff 465 /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 FSMC_Bank1->BTCR[4] = 0x00001091;
bogdanm 0:9b334a45a8ff 468 FSMC_Bank1->BTCR[5] = 0x00110212;
bogdanm 0:9b334a45a8ff 469 }
bogdanm 0:9b334a45a8ff 470 #endif /* DATA_IN_ExtSRAM */
bogdanm 0:9b334a45a8ff 471 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /**
bogdanm 0:9b334a45a8ff 474 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 475 * AHB/APBx prescalers and Flash settings
bogdanm 0:9b334a45a8ff 476 * @note This function should be called only once the RCC clock configuration
bogdanm 0:9b334a45a8ff 477 * is reset to the default reset state (done in SystemInit() function).
bogdanm 0:9b334a45a8ff 478 * @param None
bogdanm 0:9b334a45a8ff 479 * @retval None
bogdanm 0:9b334a45a8ff 480 */
bogdanm 0:9b334a45a8ff 481 void SetSysClock(void)
bogdanm 0:9b334a45a8ff 482 {
bogdanm 0:9b334a45a8ff 483 /* 1- Try to start with HSE and external clock */
bogdanm 0:9b334a45a8ff 484 #if USE_PLL_HSE_EXTC != 0
bogdanm 0:9b334a45a8ff 485 if (SetSysClock_PLL_HSE(1) == 0)
bogdanm 0:9b334a45a8ff 486 #endif
bogdanm 0:9b334a45a8ff 487 {
bogdanm 0:9b334a45a8ff 488 /* 2- If fail try to start with HSE and external xtal */
bogdanm 0:9b334a45a8ff 489 #if USE_PLL_HSE_XTAL != 0
bogdanm 0:9b334a45a8ff 490 if (SetSysClock_PLL_HSE(0) == 0)
bogdanm 0:9b334a45a8ff 491 #endif
bogdanm 0:9b334a45a8ff 492 {
bogdanm 0:9b334a45a8ff 493 /* 3- If fail start with HSI clock */
bogdanm 0:9b334a45a8ff 494 if (SetSysClock_PLL_HSI() == 0)
bogdanm 0:9b334a45a8ff 495 {
bogdanm 0:9b334a45a8ff 496 while(1)
bogdanm 0:9b334a45a8ff 497 {
bogdanm 0:9b334a45a8ff 498 // [TODO] Put something here to tell the user that a problem occured...
bogdanm 0:9b334a45a8ff 499 }
bogdanm 0:9b334a45a8ff 500 }
bogdanm 0:9b334a45a8ff 501 }
bogdanm 0:9b334a45a8ff 502 }
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504 /* Output clock on MCO1 pin(PA8) for debugging purpose */
bogdanm 0:9b334a45a8ff 505 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 24 MHz
bogdanm 0:9b334a45a8ff 506 }
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 509 /******************************************************************************/
bogdanm 0:9b334a45a8ff 510 /* PLL (clocked by HSE) used as System clock source */
bogdanm 0:9b334a45a8ff 511 /******************************************************************************/
bogdanm 0:9b334a45a8ff 512 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
bogdanm 0:9b334a45a8ff 513 {
bogdanm 0:9b334a45a8ff 514 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 515 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /* Enable HSE oscillator and activate PLL with HSE as source */
bogdanm 0:9b334a45a8ff 518 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 519 if (bypass == 0)
bogdanm 0:9b334a45a8ff 520 {
bogdanm 0:9b334a45a8ff 521 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
bogdanm 0:9b334a45a8ff 522 }
bogdanm 0:9b334a45a8ff 523 else
bogdanm 0:9b334a45a8ff 524 {
bogdanm 0:9b334a45a8ff 525 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
bogdanm 0:9b334a45a8ff 526 }
bogdanm 0:9b334a45a8ff 527 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV2;
bogdanm 0:9b334a45a8ff 528 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 529 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
bogdanm 0:9b334a45a8ff 530 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; // 24 MHz (4 MHz * 6)
bogdanm 0:9b334a45a8ff 531 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 532 {
bogdanm 0:9b334a45a8ff 533 return 0; // FAIL
bogdanm 0:9b334a45a8ff 534 }
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
bogdanm 0:9b334a45a8ff 537 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
bogdanm 0:9b334a45a8ff 538 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
bogdanm 0:9b334a45a8ff 539 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz
bogdanm 0:9b334a45a8ff 540 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz
bogdanm 0:9b334a45a8ff 541 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz
bogdanm 0:9b334a45a8ff 542 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
bogdanm 0:9b334a45a8ff 543 {
bogdanm 0:9b334a45a8ff 544 return 0; // FAIL
bogdanm 0:9b334a45a8ff 545 }
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 /* Output clock on MCO1 pin(PA8) for debugging purpose */
bogdanm 0:9b334a45a8ff 548 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 return 1; // OK
bogdanm 0:9b334a45a8ff 551 }
bogdanm 0:9b334a45a8ff 552 #endif
bogdanm 0:9b334a45a8ff 553
bogdanm 0:9b334a45a8ff 554 /******************************************************************************/
bogdanm 0:9b334a45a8ff 555 /* PLL (clocked by HSI) used as System clock source */
bogdanm 0:9b334a45a8ff 556 /******************************************************************************/
bogdanm 0:9b334a45a8ff 557 uint8_t SetSysClock_PLL_HSI(void)
bogdanm 0:9b334a45a8ff 558 {
bogdanm 0:9b334a45a8ff 559 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 560 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 561
bogdanm 0:9b334a45a8ff 562 /* Enable HSI oscillator and activate PLL with HSI as source */
bogdanm 0:9b334a45a8ff 563 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 564 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
bogdanm 0:9b334a45a8ff 565 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
bogdanm 0:9b334a45a8ff 566 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
bogdanm 0:9b334a45a8ff 567 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 568 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
bogdanm 0:9b334a45a8ff 569 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; // 24 MHz (8 MHz/2 * 6)
bogdanm 0:9b334a45a8ff 570 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 571 {
bogdanm 0:9b334a45a8ff 572 return 0; // FAIL
bogdanm 0:9b334a45a8ff 573 }
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
bogdanm 0:9b334a45a8ff 576 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
bogdanm 0:9b334a45a8ff 577 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
bogdanm 0:9b334a45a8ff 578 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz
bogdanm 0:9b334a45a8ff 579 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz
bogdanm 0:9b334a45a8ff 580 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz
bogdanm 0:9b334a45a8ff 581 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
bogdanm 0:9b334a45a8ff 582 {
bogdanm 0:9b334a45a8ff 583 return 0; // FAIL
bogdanm 0:9b334a45a8ff 584 }
bogdanm 0:9b334a45a8ff 585
bogdanm 0:9b334a45a8ff 586 /* Output clock on MCO1 pin(PA8) for debugging purpose */
bogdanm 0:9b334a45a8ff 587 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589 return 1; // OK
bogdanm 0:9b334a45a8ff 590 }
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592 /**
bogdanm 0:9b334a45a8ff 593 * @}
bogdanm 0:9b334a45a8ff 594 */
bogdanm 0:9b334a45a8ff 595
bogdanm 0:9b334a45a8ff 596 /**
bogdanm 0:9b334a45a8ff 597 * @}
bogdanm 0:9b334a45a8ff 598 */
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 /**
bogdanm 0:9b334a45a8ff 601 * @}
bogdanm 0:9b334a45a8ff 602 */
bogdanm 0:9b334a45a8ff 603 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/