en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f0xx_hal_tim.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.3.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief TIM HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Timer (TIM) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Time Base Initialization
bogdanm 0:9b334a45a8ff 11 * + Time Base Start
bogdanm 0:9b334a45a8ff 12 * + Time Base Start Interruption
bogdanm 0:9b334a45a8ff 13 * + Time Base Start DMA
bogdanm 0:9b334a45a8ff 14 * + Time Output Compare/PWM Initialization
bogdanm 0:9b334a45a8ff 15 * + Time Output Compare/PWM Channel Configuration
bogdanm 0:9b334a45a8ff 16 * + Time Output Compare/PWM Start
bogdanm 0:9b334a45a8ff 17 * + Time Output Compare/PWM Start Interruption
bogdanm 0:9b334a45a8ff 18 * + Time Output Compare/PWM Start DMA
bogdanm 0:9b334a45a8ff 19 * + Time Input Capture Initialization
bogdanm 0:9b334a45a8ff 20 * + Time Input Capture Channel Configuration
bogdanm 0:9b334a45a8ff 21 * + Time Input Capture Start
bogdanm 0:9b334a45a8ff 22 * + Time Input Capture Start Interruption
bogdanm 0:9b334a45a8ff 23 * + Time Input Capture Start DMA
bogdanm 0:9b334a45a8ff 24 * + Time One Pulse Initialization
bogdanm 0:9b334a45a8ff 25 * + Time One Pulse Channel Configuration
bogdanm 0:9b334a45a8ff 26 * + Time One Pulse Start
bogdanm 0:9b334a45a8ff 27 * + Time Encoder Interface Initialization
bogdanm 0:9b334a45a8ff 28 * + Time Encoder Interface Start
bogdanm 0:9b334a45a8ff 29 * + Time Encoder Interface Start Interruption
bogdanm 0:9b334a45a8ff 30 * + Time Encoder Interface Start DMA
bogdanm 0:9b334a45a8ff 31 * + Commutation Event configuration with Interruption and DMA
bogdanm 0:9b334a45a8ff 32 * + Time OCRef clear configuration
bogdanm 0:9b334a45a8ff 33 * + Time External Clock configuration
bogdanm 0:9b334a45a8ff 34 @verbatim
bogdanm 0:9b334a45a8ff 35 ==============================================================================
bogdanm 0:9b334a45a8ff 36 ##### TIMER Generic features #####
bogdanm 0:9b334a45a8ff 37 ==============================================================================
bogdanm 0:9b334a45a8ff 38 [..] The Timer features include:
bogdanm 0:9b334a45a8ff 39 (#) 16-bit up, down, up/down auto-reload counter.
bogdanm 0:9b334a45a8ff 40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
bogdanm 0:9b334a45a8ff 41 counter clock frequency either by any factor between 1 and 65536.
bogdanm 0:9b334a45a8ff 42 (#) Up to 4 independent channels for:
bogdanm 0:9b334a45a8ff 43 (++) Input Capture
bogdanm 0:9b334a45a8ff 44 (++) Output Compare
bogdanm 0:9b334a45a8ff 45 (++) PWM generation (Edge and Center-aligned Mode)
bogdanm 0:9b334a45a8ff 46 (++) One-pulse mode output
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 49 ==============================================================================
bogdanm 0:9b334a45a8ff 50 [..]
bogdanm 0:9b334a45a8ff 51 (#) Initialize the TIM low level resources by implementing the following functions
bogdanm 0:9b334a45a8ff 52 depending from feature used :
bogdanm 0:9b334a45a8ff 53 (++) Time Base : HAL_TIM_Base_MspInit()
bogdanm 0:9b334a45a8ff 54 (++) Input Capture : HAL_TIM_IC_MspInit()
bogdanm 0:9b334a45a8ff 55 (++) Output Compare : HAL_TIM_OC_MspInit()
bogdanm 0:9b334a45a8ff 56 (++) PWM generation : HAL_TIM_PWM_MspInit()
bogdanm 0:9b334a45a8ff 57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
bogdanm 0:9b334a45a8ff 58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 (#) Initialize the TIM low level resources :
bogdanm 0:9b334a45a8ff 61 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 62 (##) TIM pins configuration
bogdanm 0:9b334a45a8ff 63 (+++) Enable the clock for the TIM GPIOs using the following function:
bogdanm 0:9b334a45a8ff 64 __HAL_RCC_GPIOx_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 (#) The external Clock can be configured, if needed (the default clock is the
bogdanm 0:9b334a45a8ff 68 internal clock from the APBx), using the following function:
bogdanm 0:9b334a45a8ff 69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
bogdanm 0:9b334a45a8ff 70 any start function.
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 (#) Configure the TIM in the desired functioning mode using one of the
bogdanm 0:9b334a45a8ff 73 Initialization function of this driver:
bogdanm 0:9b334a45a8ff 74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
bogdanm 0:9b334a45a8ff 75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
bogdanm 0:9b334a45a8ff 76 Output Compare signal.
bogdanm 0:9b334a45a8ff 77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
bogdanm 0:9b334a45a8ff 78 PWM signal.
bogdanm 0:9b334a45a8ff 79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
bogdanm 0:9b334a45a8ff 80 external signal.
bogdanm 0:9b334a45a8ff 81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
bogdanm 0:9b334a45a8ff 82 in One Pulse Mode.
bogdanm 0:9b334a45a8ff 83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
bogdanm 0:9b334a45a8ff 86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
bogdanm 0:9b334a45a8ff 87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
bogdanm 0:9b334a45a8ff 88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
bogdanm 0:9b334a45a8ff 89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
bogdanm 0:9b334a45a8ff 90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
bogdanm 0:9b334a45a8ff 91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 (#) The DMA Burst is managed with the two following functions:
bogdanm 0:9b334a45a8ff 94 HAL_TIM_DMABurst_WriteStart()
bogdanm 0:9b334a45a8ff 95 HAL_TIM_DMABurst_ReadStart()
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 @endverbatim
bogdanm 0:9b334a45a8ff 98 ******************************************************************************
bogdanm 0:9b334a45a8ff 99 * @attention
bogdanm 0:9b334a45a8ff 100 *
bogdanm 0:9b334a45a8ff 101 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 102 *
bogdanm 0:9b334a45a8ff 103 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 104 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 105 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 106 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 108 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 109 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 111 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 112 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 113 *
bogdanm 0:9b334a45a8ff 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 124 *
bogdanm 0:9b334a45a8ff 125 ******************************************************************************
bogdanm 0:9b334a45a8ff 126 */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 129 #include "stm32f0xx_hal.h"
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 0:9b334a45a8ff 132 * @{
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /** @defgroup TIM TIM
bogdanm 0:9b334a45a8ff 136 * @brief TIM HAL module driver
bogdanm 0:9b334a45a8ff 137 * @{
bogdanm 0:9b334a45a8ff 138 */
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 #ifdef HAL_TIM_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 143 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 144 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 145 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 146 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 /** @defgroup TIM_Private_Functions TIM_Private_Functions
bogdanm 0:9b334a45a8ff 149 * @{
bogdanm 0:9b334a45a8ff 150 */
bogdanm 0:9b334a45a8ff 151 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
bogdanm 0:9b334a45a8ff 152 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
bogdanm 0:9b334a45a8ff 153 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
bogdanm 0:9b334a45a8ff 154 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm 0:9b334a45a8ff 155 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm 0:9b334a45a8ff 156 uint32_t TIM_ICFilter);
bogdanm 0:9b334a45a8ff 157 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
bogdanm 0:9b334a45a8ff 158 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm 0:9b334a45a8ff 159 uint32_t TIM_ICFilter);
bogdanm 0:9b334a45a8ff 160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm 0:9b334a45a8ff 161 uint32_t TIM_ICFilter);
bogdanm 0:9b334a45a8ff 162 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm 0:9b334a45a8ff 163 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
bogdanm 0:9b334a45a8ff 164 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
bogdanm 0:9b334a45a8ff 165 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 166 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 167 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
bogdanm 0:9b334a45a8ff 168 TIM_SlaveConfigTypeDef * sSlaveConfig);
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /**
bogdanm 0:9b334a45a8ff 171 * @}
bogdanm 0:9b334a45a8ff 172 */
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 /** @defgroup TIM_Exported_Functions TIM Exported Functions
bogdanm 0:9b334a45a8ff 177 * @{
bogdanm 0:9b334a45a8ff 178 */
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
bogdanm 0:9b334a45a8ff 181 * @brief Time Base functions
bogdanm 0:9b334a45a8ff 182 *
bogdanm 0:9b334a45a8ff 183 @verbatim
bogdanm 0:9b334a45a8ff 184 ==============================================================================
bogdanm 0:9b334a45a8ff 185 ##### Time Base functions #####
bogdanm 0:9b334a45a8ff 186 ==============================================================================
bogdanm 0:9b334a45a8ff 187 [..]
bogdanm 0:9b334a45a8ff 188 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 189 (+) Initialize and configure the TIM base.
bogdanm 0:9b334a45a8ff 190 (+) De-initialize the TIM base.
bogdanm 0:9b334a45a8ff 191 (+) Start the Time Base.
bogdanm 0:9b334a45a8ff 192 (+) Stop the Time Base.
bogdanm 0:9b334a45a8ff 193 (+) Start the Time Base and enable interrupt.
bogdanm 0:9b334a45a8ff 194 (+) Stop the Time Base and disable interrupt.
bogdanm 0:9b334a45a8ff 195 (+) Start the Time Base and enable DMA transfer.
bogdanm 0:9b334a45a8ff 196 (+) Stop the Time Base and disable DMA transfer.
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 @endverbatim
bogdanm 0:9b334a45a8ff 199 * @{
bogdanm 0:9b334a45a8ff 200 */
bogdanm 0:9b334a45a8ff 201 /**
bogdanm 0:9b334a45a8ff 202 * @brief Initializes the TIM Time base Unit according to the specified
bogdanm 0:9b334a45a8ff 203 * parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 204 * @param htim : TIM Base handle
bogdanm 0:9b334a45a8ff 205 * @retval HAL status
bogdanm 0:9b334a45a8ff 206 */
bogdanm 0:9b334a45a8ff 207 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 208 {
bogdanm 0:9b334a45a8ff 209 /* Check the TIM handle allocation */
bogdanm 0:9b334a45a8ff 210 if(htim == NULL)
bogdanm 0:9b334a45a8ff 211 {
bogdanm 0:9b334a45a8ff 212 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 213 }
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /* Check the parameters */
bogdanm 0:9b334a45a8ff 216 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 217 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm 0:9b334a45a8ff 218 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 if(htim->State == HAL_TIM_STATE_RESET)
bogdanm 0:9b334a45a8ff 221 {
bogdanm 0:9b334a45a8ff 222 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 223 htim->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 /* Init the low level hardware : GPIO, CLOCK, NVIC */
bogdanm 0:9b334a45a8ff 226 HAL_TIM_Base_MspInit(htim);
bogdanm 0:9b334a45a8ff 227 }
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 /* Set the TIM state */
bogdanm 0:9b334a45a8ff 230 htim->State= HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232 /* Set the Time Base configuration */
bogdanm 0:9b334a45a8ff 233 TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 /* Initialize the TIM state*/
bogdanm 0:9b334a45a8ff 236 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 return HAL_OK;
bogdanm 0:9b334a45a8ff 239 }
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 /**
bogdanm 0:9b334a45a8ff 242 * @brief DeInitializes the TIM Base peripheral
bogdanm 0:9b334a45a8ff 243 * @param htim : TIM Base handle
bogdanm 0:9b334a45a8ff 244 * @retval HAL status
bogdanm 0:9b334a45a8ff 245 */
bogdanm 0:9b334a45a8ff 246 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 247 {
bogdanm 0:9b334a45a8ff 248 /* Check the parameters */
bogdanm 0:9b334a45a8ff 249 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 /* Disable the TIM Peripheral Clock */
bogdanm 0:9b334a45a8ff 254 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm 0:9b334a45a8ff 257 HAL_TIM_Base_MspDeInit(htim);
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 /* Change TIM state */
bogdanm 0:9b334a45a8ff 260 htim->State = HAL_TIM_STATE_RESET;
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /* Release Lock */
bogdanm 0:9b334a45a8ff 263 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 return HAL_OK;
bogdanm 0:9b334a45a8ff 266 }
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 /**
bogdanm 0:9b334a45a8ff 269 * @brief Initializes the TIM Base MSP.
bogdanm 0:9b334a45a8ff 270 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 271 * @retval None
bogdanm 0:9b334a45a8ff 272 */
bogdanm 0:9b334a45a8ff 273 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 274 {
bogdanm 0:9b334a45a8ff 275 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 276 the HAL_TIM_Base_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 277 */
bogdanm 0:9b334a45a8ff 278 }
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /**
bogdanm 0:9b334a45a8ff 281 * @brief DeInitializes TIM Base MSP.
bogdanm 0:9b334a45a8ff 282 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 283 * @retval None
bogdanm 0:9b334a45a8ff 284 */
bogdanm 0:9b334a45a8ff 285 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 286 {
bogdanm 0:9b334a45a8ff 287 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 288 the HAL_TIM_Base_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 289 */
bogdanm 0:9b334a45a8ff 290 }
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 /**
bogdanm 0:9b334a45a8ff 294 * @brief Starts the TIM Base generation.
bogdanm 0:9b334a45a8ff 295 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 296 * @retval HAL status
bogdanm 0:9b334a45a8ff 297 */
bogdanm 0:9b334a45a8ff 298 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 299 {
bogdanm 0:9b334a45a8ff 300 /* Check the parameters */
bogdanm 0:9b334a45a8ff 301 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 /* Set the TIM state */
bogdanm 0:9b334a45a8ff 304 htim->State= HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 305
bogdanm 0:9b334a45a8ff 306 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 307 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /* Change the TIM state*/
bogdanm 0:9b334a45a8ff 310 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 /* Return function status */
bogdanm 0:9b334a45a8ff 313 return HAL_OK;
bogdanm 0:9b334a45a8ff 314 }
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 /**
bogdanm 0:9b334a45a8ff 317 * @brief Stops the TIM Base generation.
bogdanm 0:9b334a45a8ff 318 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 319 * @retval HAL status
bogdanm 0:9b334a45a8ff 320 */
bogdanm 0:9b334a45a8ff 321 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 322 {
bogdanm 0:9b334a45a8ff 323 /* Check the parameters */
bogdanm 0:9b334a45a8ff 324 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /* Set the TIM state */
bogdanm 0:9b334a45a8ff 327 htim->State= HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 330 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /* Change the TIM state*/
bogdanm 0:9b334a45a8ff 333 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /* Return function status */
bogdanm 0:9b334a45a8ff 336 return HAL_OK;
bogdanm 0:9b334a45a8ff 337 }
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 /**
bogdanm 0:9b334a45a8ff 340 * @brief Starts the TIM Base generation in interrupt mode.
bogdanm 0:9b334a45a8ff 341 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 342 * @retval HAL status
bogdanm 0:9b334a45a8ff 343 */
bogdanm 0:9b334a45a8ff 344 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 345 {
bogdanm 0:9b334a45a8ff 346 /* Check the parameters */
bogdanm 0:9b334a45a8ff 347 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 /* Enable the TIM Update interrupt */
bogdanm 0:9b334a45a8ff 350 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 353 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /* Return function status */
bogdanm 0:9b334a45a8ff 356 return HAL_OK;
bogdanm 0:9b334a45a8ff 357 }
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /**
bogdanm 0:9b334a45a8ff 360 * @brief Stops the TIM Base generation in interrupt mode.
bogdanm 0:9b334a45a8ff 361 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 362 * @retval HAL status
bogdanm 0:9b334a45a8ff 363 */
bogdanm 0:9b334a45a8ff 364 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 365 {
bogdanm 0:9b334a45a8ff 366 /* Check the parameters */
bogdanm 0:9b334a45a8ff 367 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 368 /* Disable the TIM Update interrupt */
bogdanm 0:9b334a45a8ff 369 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 372 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 /* Return function status */
bogdanm 0:9b334a45a8ff 375 return HAL_OK;
bogdanm 0:9b334a45a8ff 376 }
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378 /**
bogdanm 0:9b334a45a8ff 379 * @brief Starts the TIM Base generation in DMA mode.
bogdanm 0:9b334a45a8ff 380 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 381 * @param pData : The source Buffer address.
bogdanm 0:9b334a45a8ff 382 * @param Length : The length of data to be transferred from memory to peripheral.
bogdanm 0:9b334a45a8ff 383 * @retval HAL status
bogdanm 0:9b334a45a8ff 384 */
bogdanm 0:9b334a45a8ff 385 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
bogdanm 0:9b334a45a8ff 386 {
bogdanm 0:9b334a45a8ff 387 /* Check the parameters */
bogdanm 0:9b334a45a8ff 388 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 391 {
bogdanm 0:9b334a45a8ff 392 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 393 }
bogdanm 0:9b334a45a8ff 394 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 395 {
bogdanm 0:9b334a45a8ff 396 if((pData == 0 ) && (Length > 0))
bogdanm 0:9b334a45a8ff 397 {
bogdanm 0:9b334a45a8ff 398 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 399 }
bogdanm 0:9b334a45a8ff 400 else
bogdanm 0:9b334a45a8ff 401 {
bogdanm 0:9b334a45a8ff 402 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 403 }
bogdanm 0:9b334a45a8ff 404 }
bogdanm 0:9b334a45a8ff 405 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 406 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm 0:9b334a45a8ff 407
bogdanm 0:9b334a45a8ff 408 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 409 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 412 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /* Enable the TIM Update DMA request */
bogdanm 0:9b334a45a8ff 415 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 418 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 /* Return function status */
bogdanm 0:9b334a45a8ff 421 return HAL_OK;
bogdanm 0:9b334a45a8ff 422 }
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /**
bogdanm 0:9b334a45a8ff 425 * @brief Stops the TIM Base generation in DMA mode.
bogdanm 0:9b334a45a8ff 426 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 427 * @retval HAL status
bogdanm 0:9b334a45a8ff 428 */
bogdanm 0:9b334a45a8ff 429 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 430 {
bogdanm 0:9b334a45a8ff 431 /* Check the parameters */
bogdanm 0:9b334a45a8ff 432 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 /* Disable the TIM Update DMA request */
bogdanm 0:9b334a45a8ff 435 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
bogdanm 0:9b334a45a8ff 436
bogdanm 0:9b334a45a8ff 437 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 438 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 /* Change the htim state */
bogdanm 0:9b334a45a8ff 441 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 /* Return function status */
bogdanm 0:9b334a45a8ff 444 return HAL_OK;
bogdanm 0:9b334a45a8ff 445 }
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 /**
bogdanm 0:9b334a45a8ff 448 * @}
bogdanm 0:9b334a45a8ff 449 */
bogdanm 0:9b334a45a8ff 450
bogdanm 0:9b334a45a8ff 451 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
bogdanm 0:9b334a45a8ff 452 * @brief Time Output Compare functions
bogdanm 0:9b334a45a8ff 453 *
bogdanm 0:9b334a45a8ff 454 @verbatim
bogdanm 0:9b334a45a8ff 455 ==============================================================================
bogdanm 0:9b334a45a8ff 456 ##### Time Output Compare functions #####
bogdanm 0:9b334a45a8ff 457 ==============================================================================
bogdanm 0:9b334a45a8ff 458 [..]
bogdanm 0:9b334a45a8ff 459 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 460 (+) Initialize and configure the TIM Output Compare.
bogdanm 0:9b334a45a8ff 461 (+) De-initialize the TIM Output Compare.
bogdanm 0:9b334a45a8ff 462 (+) Start the Time Output Compare.
bogdanm 0:9b334a45a8ff 463 (+) Stop the Time Output Compare.
bogdanm 0:9b334a45a8ff 464 (+) Start the Time Output Compare and enable interrupt.
bogdanm 0:9b334a45a8ff 465 (+) Stop the Time Output Compare and disable interrupt.
bogdanm 0:9b334a45a8ff 466 (+) Start the Time Output Compare and enable DMA transfer.
bogdanm 0:9b334a45a8ff 467 (+) Stop the Time Output Compare and disable DMA transfer.
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 @endverbatim
bogdanm 0:9b334a45a8ff 470 * @{
bogdanm 0:9b334a45a8ff 471 */
bogdanm 0:9b334a45a8ff 472 /**
bogdanm 0:9b334a45a8ff 473 * @brief Initializes the TIM Output Compare according to the specified
bogdanm 0:9b334a45a8ff 474 * parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 475 * @param htim : TIM Output Compare handle
bogdanm 0:9b334a45a8ff 476 * @retval HAL status
bogdanm 0:9b334a45a8ff 477 */
bogdanm 0:9b334a45a8ff 478 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
bogdanm 0:9b334a45a8ff 479 {
bogdanm 0:9b334a45a8ff 480 /* Check the TIM handle allocation */
bogdanm 0:9b334a45a8ff 481 if(htim == NULL)
bogdanm 0:9b334a45a8ff 482 {
bogdanm 0:9b334a45a8ff 483 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 484 }
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 /* Check the parameters */
bogdanm 0:9b334a45a8ff 487 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 488 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm 0:9b334a45a8ff 489 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491 if(htim->State == HAL_TIM_STATE_RESET)
bogdanm 0:9b334a45a8ff 492 {
bogdanm 0:9b334a45a8ff 493 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 494 htim->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm 0:9b334a45a8ff 497 HAL_TIM_OC_MspInit(htim);
bogdanm 0:9b334a45a8ff 498 }
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 /* Set the TIM state */
bogdanm 0:9b334a45a8ff 501 htim->State= HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 502
bogdanm 0:9b334a45a8ff 503 /* Init the base time for the Output Compare */
bogdanm 0:9b334a45a8ff 504 TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 /* Initialize the TIM state*/
bogdanm 0:9b334a45a8ff 507 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 508
bogdanm 0:9b334a45a8ff 509 return HAL_OK;
bogdanm 0:9b334a45a8ff 510 }
bogdanm 0:9b334a45a8ff 511
bogdanm 0:9b334a45a8ff 512 /**
bogdanm 0:9b334a45a8ff 513 * @brief DeInitializes the TIM peripheral
bogdanm 0:9b334a45a8ff 514 * @param htim : TIM Output Compare handle
bogdanm 0:9b334a45a8ff 515 * @retval HAL status
bogdanm 0:9b334a45a8ff 516 */
bogdanm 0:9b334a45a8ff 517 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 518 {
bogdanm 0:9b334a45a8ff 519 /* Check the parameters */
bogdanm 0:9b334a45a8ff 520 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /* Disable the TIM Peripheral Clock */
bogdanm 0:9b334a45a8ff 525 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 526
bogdanm 0:9b334a45a8ff 527 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm 0:9b334a45a8ff 528 HAL_TIM_OC_MspDeInit(htim);
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /* Change TIM state */
bogdanm 0:9b334a45a8ff 531 htim->State = HAL_TIM_STATE_RESET;
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 /* Release Lock */
bogdanm 0:9b334a45a8ff 534 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 return HAL_OK;
bogdanm 0:9b334a45a8ff 537 }
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 /**
bogdanm 0:9b334a45a8ff 540 * @brief Initializes the TIM Output Compare MSP.
bogdanm 0:9b334a45a8ff 541 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 542 * @retval None
bogdanm 0:9b334a45a8ff 543 */
bogdanm 0:9b334a45a8ff 544 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 545 {
bogdanm 0:9b334a45a8ff 546 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 547 the HAL_TIM_OC_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 548 */
bogdanm 0:9b334a45a8ff 549 }
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /**
bogdanm 0:9b334a45a8ff 552 * @brief DeInitializes TIM Output Compare MSP.
bogdanm 0:9b334a45a8ff 553 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 554 * @retval None
bogdanm 0:9b334a45a8ff 555 */
bogdanm 0:9b334a45a8ff 556 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 557 {
bogdanm 0:9b334a45a8ff 558 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 559 the HAL_TIM_OC_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 560 */
bogdanm 0:9b334a45a8ff 561 }
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 /**
bogdanm 0:9b334a45a8ff 564 * @brief Starts the TIM Output Compare signal generation.
bogdanm 0:9b334a45a8ff 565 * @param htim : TIM Output Compare handle
bogdanm 0:9b334a45a8ff 566 * @param Channel : TIM Channel to be enabled
bogdanm 0:9b334a45a8ff 567 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 568 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 569 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 570 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 571 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 572 * @retval HAL status
bogdanm 0:9b334a45a8ff 573 */
bogdanm 0:9b334a45a8ff 574 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 575 {
bogdanm 0:9b334a45a8ff 576 /* Check the parameters */
bogdanm 0:9b334a45a8ff 577 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /* Enable the Output compare channel */
bogdanm 0:9b334a45a8ff 580 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 581
bogdanm 0:9b334a45a8ff 582 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 583 {
bogdanm 0:9b334a45a8ff 584 /* Enable the main output */
bogdanm 0:9b334a45a8ff 585 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 586 }
bogdanm 0:9b334a45a8ff 587
bogdanm 0:9b334a45a8ff 588 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 589 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 /* Return function status */
bogdanm 0:9b334a45a8ff 592 return HAL_OK;
bogdanm 0:9b334a45a8ff 593 }
bogdanm 0:9b334a45a8ff 594
bogdanm 0:9b334a45a8ff 595 /**
bogdanm 0:9b334a45a8ff 596 * @brief Stops the TIM Output Compare signal generation.
bogdanm 0:9b334a45a8ff 597 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 598 * @param Channel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 599 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 600 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 601 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 602 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 603 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 604 * @retval HAL status
bogdanm 0:9b334a45a8ff 605 */
bogdanm 0:9b334a45a8ff 606 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 607 {
bogdanm 0:9b334a45a8ff 608 /* Check the parameters */
bogdanm 0:9b334a45a8ff 609 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 610
bogdanm 0:9b334a45a8ff 611 /* Disable the Output compare channel */
bogdanm 0:9b334a45a8ff 612 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 613
bogdanm 0:9b334a45a8ff 614 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 615 {
bogdanm 0:9b334a45a8ff 616 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 617 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 618 }
bogdanm 0:9b334a45a8ff 619
bogdanm 0:9b334a45a8ff 620 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 621 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 /* Return function status */
bogdanm 0:9b334a45a8ff 624 return HAL_OK;
bogdanm 0:9b334a45a8ff 625 }
bogdanm 0:9b334a45a8ff 626
bogdanm 0:9b334a45a8ff 627 /**
bogdanm 0:9b334a45a8ff 628 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
bogdanm 0:9b334a45a8ff 629 * @param htim : TIM OC handle
bogdanm 0:9b334a45a8ff 630 * @param Channel : TIM Channel to be enabled
bogdanm 0:9b334a45a8ff 631 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 632 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 633 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 634 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 635 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 636 * @retval HAL status
bogdanm 0:9b334a45a8ff 637 */
bogdanm 0:9b334a45a8ff 638 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 639 {
bogdanm 0:9b334a45a8ff 640 /* Check the parameters */
bogdanm 0:9b334a45a8ff 641 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 642
bogdanm 0:9b334a45a8ff 643 switch (Channel)
bogdanm 0:9b334a45a8ff 644 {
bogdanm 0:9b334a45a8ff 645 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 646 {
bogdanm 0:9b334a45a8ff 647 /* Enable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 648 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 649 }
bogdanm 0:9b334a45a8ff 650 break;
bogdanm 0:9b334a45a8ff 651
bogdanm 0:9b334a45a8ff 652 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 653 {
bogdanm 0:9b334a45a8ff 654 /* Enable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 655 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 656 }
bogdanm 0:9b334a45a8ff 657 break;
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 660 {
bogdanm 0:9b334a45a8ff 661 /* Enable the TIM Capture/Compare 3 interrupt */
bogdanm 0:9b334a45a8ff 662 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 663 }
bogdanm 0:9b334a45a8ff 664 break;
bogdanm 0:9b334a45a8ff 665
bogdanm 0:9b334a45a8ff 666 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 667 {
bogdanm 0:9b334a45a8ff 668 /* Enable the TIM Capture/Compare 4 interrupt */
bogdanm 0:9b334a45a8ff 669 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 670 }
bogdanm 0:9b334a45a8ff 671 break;
bogdanm 0:9b334a45a8ff 672
bogdanm 0:9b334a45a8ff 673 default:
bogdanm 0:9b334a45a8ff 674 break;
bogdanm 0:9b334a45a8ff 675 }
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 /* Enable the Output compare channel */
bogdanm 0:9b334a45a8ff 678 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 679
bogdanm 0:9b334a45a8ff 680 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 681 {
bogdanm 0:9b334a45a8ff 682 /* Enable the main output */
bogdanm 0:9b334a45a8ff 683 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 684 }
bogdanm 0:9b334a45a8ff 685
bogdanm 0:9b334a45a8ff 686 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 687 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 688
bogdanm 0:9b334a45a8ff 689 /* Return function status */
bogdanm 0:9b334a45a8ff 690 return HAL_OK;
bogdanm 0:9b334a45a8ff 691 }
bogdanm 0:9b334a45a8ff 692
bogdanm 0:9b334a45a8ff 693 /**
bogdanm 0:9b334a45a8ff 694 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
bogdanm 0:9b334a45a8ff 695 * @param htim : TIM Output Compare handle
bogdanm 0:9b334a45a8ff 696 * @param Channel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 697 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 698 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 699 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 700 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 701 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 702 * @retval HAL status
bogdanm 0:9b334a45a8ff 703 */
bogdanm 0:9b334a45a8ff 704 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 705 {
bogdanm 0:9b334a45a8ff 706 /* Check the parameters */
bogdanm 0:9b334a45a8ff 707 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 708
bogdanm 0:9b334a45a8ff 709 switch (Channel)
bogdanm 0:9b334a45a8ff 710 {
bogdanm 0:9b334a45a8ff 711 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 712 {
bogdanm 0:9b334a45a8ff 713 /* Disable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 714 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 715 }
bogdanm 0:9b334a45a8ff 716 break;
bogdanm 0:9b334a45a8ff 717
bogdanm 0:9b334a45a8ff 718 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 719 {
bogdanm 0:9b334a45a8ff 720 /* Disable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 721 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 722 }
bogdanm 0:9b334a45a8ff 723 break;
bogdanm 0:9b334a45a8ff 724
bogdanm 0:9b334a45a8ff 725 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 726 {
bogdanm 0:9b334a45a8ff 727 /* Disable the TIM Capture/Compare 3 interrupt */
bogdanm 0:9b334a45a8ff 728 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 729 }
bogdanm 0:9b334a45a8ff 730 break;
bogdanm 0:9b334a45a8ff 731
bogdanm 0:9b334a45a8ff 732 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 733 {
bogdanm 0:9b334a45a8ff 734 /* Disable the TIM Capture/Compare 4 interrupt */
bogdanm 0:9b334a45a8ff 735 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 736 }
bogdanm 0:9b334a45a8ff 737 break;
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 default:
bogdanm 0:9b334a45a8ff 740 break;
bogdanm 0:9b334a45a8ff 741 }
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743 /* Disable the Output compare channel */
bogdanm 0:9b334a45a8ff 744 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 745
bogdanm 0:9b334a45a8ff 746 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 747 {
bogdanm 0:9b334a45a8ff 748 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 749 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 750 }
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 753 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 754
bogdanm 0:9b334a45a8ff 755 /* Return function status */
bogdanm 0:9b334a45a8ff 756 return HAL_OK;
bogdanm 0:9b334a45a8ff 757 }
bogdanm 0:9b334a45a8ff 758
bogdanm 0:9b334a45a8ff 759 /**
bogdanm 0:9b334a45a8ff 760 * @brief Starts the TIM Output Compare signal generation in DMA mode.
bogdanm 0:9b334a45a8ff 761 * @param htim : TIM Output Compare handle
bogdanm 0:9b334a45a8ff 762 * @param Channel : TIM Channel to be enabled
bogdanm 0:9b334a45a8ff 763 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 764 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 765 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 766 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 767 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 768 * @param pData : The source Buffer address.
bogdanm 0:9b334a45a8ff 769 * @param Length : The length of data to be transferred from memory to TIM peripheral
bogdanm 0:9b334a45a8ff 770 * @retval HAL status
bogdanm 0:9b334a45a8ff 771 */
bogdanm 0:9b334a45a8ff 772 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
bogdanm 0:9b334a45a8ff 773 {
bogdanm 0:9b334a45a8ff 774 /* Check the parameters */
bogdanm 0:9b334a45a8ff 775 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 776
bogdanm 0:9b334a45a8ff 777 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 778 {
bogdanm 0:9b334a45a8ff 779 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 780 }
bogdanm 0:9b334a45a8ff 781 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 782 {
bogdanm 0:9b334a45a8ff 783 if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm 0:9b334a45a8ff 784 {
bogdanm 0:9b334a45a8ff 785 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 786 }
bogdanm 0:9b334a45a8ff 787 else
bogdanm 0:9b334a45a8ff 788 {
bogdanm 0:9b334a45a8ff 789 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 790 }
bogdanm 0:9b334a45a8ff 791 }
bogdanm 0:9b334a45a8ff 792 switch (Channel)
bogdanm 0:9b334a45a8ff 793 {
bogdanm 0:9b334a45a8ff 794 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 795 {
bogdanm 0:9b334a45a8ff 796 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 797 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 798
bogdanm 0:9b334a45a8ff 799 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 800 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 801
bogdanm 0:9b334a45a8ff 802 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 803 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm 0:9b334a45a8ff 804
bogdanm 0:9b334a45a8ff 805 /* Enable the TIM Capture/Compare 1 DMA request */
bogdanm 0:9b334a45a8ff 806 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 807 }
bogdanm 0:9b334a45a8ff 808 break;
bogdanm 0:9b334a45a8ff 809
bogdanm 0:9b334a45a8ff 810 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 811 {
bogdanm 0:9b334a45a8ff 812 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 813 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 814
bogdanm 0:9b334a45a8ff 815 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 816 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 817
bogdanm 0:9b334a45a8ff 818 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 819 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm 0:9b334a45a8ff 820
bogdanm 0:9b334a45a8ff 821 /* Enable the TIM Capture/Compare 2 DMA request */
bogdanm 0:9b334a45a8ff 822 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 823 }
bogdanm 0:9b334a45a8ff 824 break;
bogdanm 0:9b334a45a8ff 825
bogdanm 0:9b334a45a8ff 826 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 827 {
bogdanm 0:9b334a45a8ff 828 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 829 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 830
bogdanm 0:9b334a45a8ff 831 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 832 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 833
bogdanm 0:9b334a45a8ff 834 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 835 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm 0:9b334a45a8ff 836
bogdanm 0:9b334a45a8ff 837 /* Enable the TIM Capture/Compare 3 DMA request */
bogdanm 0:9b334a45a8ff 838 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 839 }
bogdanm 0:9b334a45a8ff 840 break;
bogdanm 0:9b334a45a8ff 841
bogdanm 0:9b334a45a8ff 842 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 843 {
bogdanm 0:9b334a45a8ff 844 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 845 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 846
bogdanm 0:9b334a45a8ff 847 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 848 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 849
bogdanm 0:9b334a45a8ff 850 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 851 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm 0:9b334a45a8ff 852
bogdanm 0:9b334a45a8ff 853 /* Enable the TIM Capture/Compare 4 DMA request */
bogdanm 0:9b334a45a8ff 854 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 855 }
bogdanm 0:9b334a45a8ff 856 break;
bogdanm 0:9b334a45a8ff 857
bogdanm 0:9b334a45a8ff 858 default:
bogdanm 0:9b334a45a8ff 859 break;
bogdanm 0:9b334a45a8ff 860 }
bogdanm 0:9b334a45a8ff 861
bogdanm 0:9b334a45a8ff 862 /* Enable the Output compare channel */
bogdanm 0:9b334a45a8ff 863 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 864
bogdanm 0:9b334a45a8ff 865 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 866 {
bogdanm 0:9b334a45a8ff 867 /* Enable the main output */
bogdanm 0:9b334a45a8ff 868 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 869 }
bogdanm 0:9b334a45a8ff 870
bogdanm 0:9b334a45a8ff 871 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 872 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 873
bogdanm 0:9b334a45a8ff 874 /* Return function status */
bogdanm 0:9b334a45a8ff 875 return HAL_OK;
bogdanm 0:9b334a45a8ff 876 }
bogdanm 0:9b334a45a8ff 877
bogdanm 0:9b334a45a8ff 878 /**
bogdanm 0:9b334a45a8ff 879 * @brief Stops the TIM Output Compare signal generation in DMA mode.
bogdanm 0:9b334a45a8ff 880 * @param htim : TIM Output Compare handle
bogdanm 0:9b334a45a8ff 881 * @param Channel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 882 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 883 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 884 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 885 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 886 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 887 * @retval HAL status
bogdanm 0:9b334a45a8ff 888 */
bogdanm 0:9b334a45a8ff 889 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 890 {
bogdanm 0:9b334a45a8ff 891 /* Check the parameters */
bogdanm 0:9b334a45a8ff 892 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 switch (Channel)
bogdanm 0:9b334a45a8ff 895 {
bogdanm 0:9b334a45a8ff 896 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 897 {
bogdanm 0:9b334a45a8ff 898 /* Disable the TIM Capture/Compare 1 DMA request */
bogdanm 0:9b334a45a8ff 899 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 900 }
bogdanm 0:9b334a45a8ff 901 break;
bogdanm 0:9b334a45a8ff 902
bogdanm 0:9b334a45a8ff 903 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 904 {
bogdanm 0:9b334a45a8ff 905 /* Disable the TIM Capture/Compare 2 DMA request */
bogdanm 0:9b334a45a8ff 906 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 907 }
bogdanm 0:9b334a45a8ff 908 break;
bogdanm 0:9b334a45a8ff 909
bogdanm 0:9b334a45a8ff 910 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 911 {
bogdanm 0:9b334a45a8ff 912 /* Disable the TIM Capture/Compare 3 DMA request */
bogdanm 0:9b334a45a8ff 913 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 914 }
bogdanm 0:9b334a45a8ff 915 break;
bogdanm 0:9b334a45a8ff 916
bogdanm 0:9b334a45a8ff 917 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 918 {
bogdanm 0:9b334a45a8ff 919 /* Disable the TIM Capture/Compare 4 interrupt */
bogdanm 0:9b334a45a8ff 920 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 921 }
bogdanm 0:9b334a45a8ff 922 break;
bogdanm 0:9b334a45a8ff 923
bogdanm 0:9b334a45a8ff 924 default:
bogdanm 0:9b334a45a8ff 925 break;
bogdanm 0:9b334a45a8ff 926 }
bogdanm 0:9b334a45a8ff 927
bogdanm 0:9b334a45a8ff 928 /* Disable the Output compare channel */
bogdanm 0:9b334a45a8ff 929 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 930
bogdanm 0:9b334a45a8ff 931 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 932 {
bogdanm 0:9b334a45a8ff 933 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 934 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 935 }
bogdanm 0:9b334a45a8ff 936
bogdanm 0:9b334a45a8ff 937 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 938 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 939
bogdanm 0:9b334a45a8ff 940 /* Change the htim state */
bogdanm 0:9b334a45a8ff 941 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 942
bogdanm 0:9b334a45a8ff 943 /* Return function status */
bogdanm 0:9b334a45a8ff 944 return HAL_OK;
bogdanm 0:9b334a45a8ff 945 }
bogdanm 0:9b334a45a8ff 946
bogdanm 0:9b334a45a8ff 947 /**
bogdanm 0:9b334a45a8ff 948 * @}
bogdanm 0:9b334a45a8ff 949 */
bogdanm 0:9b334a45a8ff 950
bogdanm 0:9b334a45a8ff 951 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
bogdanm 0:9b334a45a8ff 952 * @brief Time PWM functions
bogdanm 0:9b334a45a8ff 953 *
bogdanm 0:9b334a45a8ff 954 @verbatim
bogdanm 0:9b334a45a8ff 955 ==============================================================================
bogdanm 0:9b334a45a8ff 956 ##### Time PWM functions #####
bogdanm 0:9b334a45a8ff 957 ==============================================================================
bogdanm 0:9b334a45a8ff 958 [..]
bogdanm 0:9b334a45a8ff 959 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 960 (+) Initialize and configure the TIM OPWM.
bogdanm 0:9b334a45a8ff 961 (+) De-initialize the TIM PWM.
bogdanm 0:9b334a45a8ff 962 (+) Start the Time PWM.
bogdanm 0:9b334a45a8ff 963 (+) Stop the Time PWM.
bogdanm 0:9b334a45a8ff 964 (+) Start the Time PWM and enable interrupt.
bogdanm 0:9b334a45a8ff 965 (+) Stop the Time PWM and disable interrupt.
bogdanm 0:9b334a45a8ff 966 (+) Start the Time PWM and enable DMA transfer.
bogdanm 0:9b334a45a8ff 967 (+) Stop the Time PWM and disable DMA transfer.
bogdanm 0:9b334a45a8ff 968
bogdanm 0:9b334a45a8ff 969 @endverbatim
bogdanm 0:9b334a45a8ff 970 * @{
bogdanm 0:9b334a45a8ff 971 */
bogdanm 0:9b334a45a8ff 972 /**
bogdanm 0:9b334a45a8ff 973 * @brief Initializes the TIM PWM Time Base according to the specified
bogdanm 0:9b334a45a8ff 974 * parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 975 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 976 * @retval HAL status
bogdanm 0:9b334a45a8ff 977 */
bogdanm 0:9b334a45a8ff 978 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 979 {
bogdanm 0:9b334a45a8ff 980 /* Check the TIM handle allocation */
bogdanm 0:9b334a45a8ff 981 if(htim == NULL)
bogdanm 0:9b334a45a8ff 982 {
bogdanm 0:9b334a45a8ff 983 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 984 }
bogdanm 0:9b334a45a8ff 985
bogdanm 0:9b334a45a8ff 986 /* Check the parameters */
bogdanm 0:9b334a45a8ff 987 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 988 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm 0:9b334a45a8ff 989 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm 0:9b334a45a8ff 990
bogdanm 0:9b334a45a8ff 991 if(htim->State == HAL_TIM_STATE_RESET)
bogdanm 0:9b334a45a8ff 992 {
bogdanm 0:9b334a45a8ff 993 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 994 htim->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 995
bogdanm 0:9b334a45a8ff 996 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm 0:9b334a45a8ff 997 HAL_TIM_PWM_MspInit(htim);
bogdanm 0:9b334a45a8ff 998 }
bogdanm 0:9b334a45a8ff 999
bogdanm 0:9b334a45a8ff 1000 /* Set the TIM state */
bogdanm 0:9b334a45a8ff 1001 htim->State= HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1002
bogdanm 0:9b334a45a8ff 1003 /* Init the base time for the PWM */
bogdanm 0:9b334a45a8ff 1004 TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm 0:9b334a45a8ff 1005
bogdanm 0:9b334a45a8ff 1006 /* Initialize the TIM state*/
bogdanm 0:9b334a45a8ff 1007 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 1008
bogdanm 0:9b334a45a8ff 1009 return HAL_OK;
bogdanm 0:9b334a45a8ff 1010 }
bogdanm 0:9b334a45a8ff 1011
bogdanm 0:9b334a45a8ff 1012 /**
bogdanm 0:9b334a45a8ff 1013 * @brief DeInitializes the TIM peripheral
bogdanm 0:9b334a45a8ff 1014 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1015 * @retval HAL status
bogdanm 0:9b334a45a8ff 1016 */
bogdanm 0:9b334a45a8ff 1017 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 1018 {
bogdanm 0:9b334a45a8ff 1019 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1020 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1021
bogdanm 0:9b334a45a8ff 1022 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1023
bogdanm 0:9b334a45a8ff 1024 /* Disable the TIM Peripheral Clock */
bogdanm 0:9b334a45a8ff 1025 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1026
bogdanm 0:9b334a45a8ff 1027 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm 0:9b334a45a8ff 1028 HAL_TIM_PWM_MspDeInit(htim);
bogdanm 0:9b334a45a8ff 1029
bogdanm 0:9b334a45a8ff 1030 /* Change TIM state */
bogdanm 0:9b334a45a8ff 1031 htim->State = HAL_TIM_STATE_RESET;
bogdanm 0:9b334a45a8ff 1032
bogdanm 0:9b334a45a8ff 1033 /* Release Lock */
bogdanm 0:9b334a45a8ff 1034 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 1035
bogdanm 0:9b334a45a8ff 1036 return HAL_OK;
bogdanm 0:9b334a45a8ff 1037 }
bogdanm 0:9b334a45a8ff 1038
bogdanm 0:9b334a45a8ff 1039 /**
bogdanm 0:9b334a45a8ff 1040 * @brief Initializes the TIM PWM MSP.
bogdanm 0:9b334a45a8ff 1041 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1042 * @retval None
bogdanm 0:9b334a45a8ff 1043 */
bogdanm 0:9b334a45a8ff 1044 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 1045 {
bogdanm 0:9b334a45a8ff 1046 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1047 the HAL_TIM_PWM_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 1048 */
bogdanm 0:9b334a45a8ff 1049 }
bogdanm 0:9b334a45a8ff 1050
bogdanm 0:9b334a45a8ff 1051 /**
bogdanm 0:9b334a45a8ff 1052 * @brief DeInitializes TIM PWM MSP.
bogdanm 0:9b334a45a8ff 1053 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1054 * @retval None
bogdanm 0:9b334a45a8ff 1055 */
bogdanm 0:9b334a45a8ff 1056 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 1057 {
bogdanm 0:9b334a45a8ff 1058 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1059 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 1060 */
bogdanm 0:9b334a45a8ff 1061 }
bogdanm 0:9b334a45a8ff 1062
bogdanm 0:9b334a45a8ff 1063 /**
bogdanm 0:9b334a45a8ff 1064 * @brief Starts the PWM signal generation.
bogdanm 0:9b334a45a8ff 1065 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1066 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 1067 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1068 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1069 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1070 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1071 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1072 * @retval HAL status
bogdanm 0:9b334a45a8ff 1073 */
bogdanm 0:9b334a45a8ff 1074 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1075 {
bogdanm 0:9b334a45a8ff 1076 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1077 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1078
bogdanm 0:9b334a45a8ff 1079 /* Enable the Capture compare channel */
bogdanm 0:9b334a45a8ff 1080 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 1081
bogdanm 0:9b334a45a8ff 1082 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 1083 {
bogdanm 0:9b334a45a8ff 1084 /* Enable the main output */
bogdanm 0:9b334a45a8ff 1085 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1086 }
bogdanm 0:9b334a45a8ff 1087
bogdanm 0:9b334a45a8ff 1088 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 1089 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1090
bogdanm 0:9b334a45a8ff 1091 /* Return function status */
bogdanm 0:9b334a45a8ff 1092 return HAL_OK;
bogdanm 0:9b334a45a8ff 1093 }
bogdanm 0:9b334a45a8ff 1094
bogdanm 0:9b334a45a8ff 1095 /**
bogdanm 0:9b334a45a8ff 1096 * @brief Stops the PWM signal generation.
bogdanm 0:9b334a45a8ff 1097 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1098 * @param Channel : TIM Channels to be disabled
bogdanm 0:9b334a45a8ff 1099 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1100 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1101 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1102 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1103 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1104 * @retval HAL status
bogdanm 0:9b334a45a8ff 1105 */
bogdanm 0:9b334a45a8ff 1106 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1107 {
bogdanm 0:9b334a45a8ff 1108 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1109 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1110
bogdanm 0:9b334a45a8ff 1111 /* Disable the Capture compare channel */
bogdanm 0:9b334a45a8ff 1112 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 1113
bogdanm 0:9b334a45a8ff 1114 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 1115 {
bogdanm 0:9b334a45a8ff 1116 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 1117 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1118 }
bogdanm 0:9b334a45a8ff 1119
bogdanm 0:9b334a45a8ff 1120 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1121 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1122
bogdanm 0:9b334a45a8ff 1123 /* Change the htim state */
bogdanm 0:9b334a45a8ff 1124 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 1125
bogdanm 0:9b334a45a8ff 1126 /* Return function status */
bogdanm 0:9b334a45a8ff 1127 return HAL_OK;
bogdanm 0:9b334a45a8ff 1128 }
bogdanm 0:9b334a45a8ff 1129
bogdanm 0:9b334a45a8ff 1130 /**
bogdanm 0:9b334a45a8ff 1131 * @brief Starts the PWM signal generation in interrupt mode.
bogdanm 0:9b334a45a8ff 1132 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1133 * @param Channel : TIM Channel to be disabled
bogdanm 0:9b334a45a8ff 1134 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1135 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1136 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1137 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1138 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1139 * @retval HAL status
bogdanm 0:9b334a45a8ff 1140 */
bogdanm 0:9b334a45a8ff 1141 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1142 {
bogdanm 0:9b334a45a8ff 1143 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1144 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1145
bogdanm 0:9b334a45a8ff 1146 switch (Channel)
bogdanm 0:9b334a45a8ff 1147 {
bogdanm 0:9b334a45a8ff 1148 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1149 {
bogdanm 0:9b334a45a8ff 1150 /* Enable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 1151 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 1152 }
bogdanm 0:9b334a45a8ff 1153 break;
bogdanm 0:9b334a45a8ff 1154
bogdanm 0:9b334a45a8ff 1155 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1156 {
bogdanm 0:9b334a45a8ff 1157 /* Enable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 1158 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 1159 }
bogdanm 0:9b334a45a8ff 1160 break;
bogdanm 0:9b334a45a8ff 1161
bogdanm 0:9b334a45a8ff 1162 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1163 {
bogdanm 0:9b334a45a8ff 1164 /* Enable the TIM Capture/Compare 3 interrupt */
bogdanm 0:9b334a45a8ff 1165 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 1166 }
bogdanm 0:9b334a45a8ff 1167 break;
bogdanm 0:9b334a45a8ff 1168
bogdanm 0:9b334a45a8ff 1169 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1170 {
bogdanm 0:9b334a45a8ff 1171 /* Enable the TIM Capture/Compare 4 interrupt */
bogdanm 0:9b334a45a8ff 1172 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 1173 }
bogdanm 0:9b334a45a8ff 1174 break;
bogdanm 0:9b334a45a8ff 1175
bogdanm 0:9b334a45a8ff 1176 default:
bogdanm 0:9b334a45a8ff 1177 break;
bogdanm 0:9b334a45a8ff 1178 }
bogdanm 0:9b334a45a8ff 1179
bogdanm 0:9b334a45a8ff 1180 /* Enable the Capture compare channel */
bogdanm 0:9b334a45a8ff 1181 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 1182
bogdanm 0:9b334a45a8ff 1183 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 1184 {
bogdanm 0:9b334a45a8ff 1185 /* Enable the main output */
bogdanm 0:9b334a45a8ff 1186 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1187 }
bogdanm 0:9b334a45a8ff 1188
bogdanm 0:9b334a45a8ff 1189 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 1190 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1191
bogdanm 0:9b334a45a8ff 1192 /* Return function status */
bogdanm 0:9b334a45a8ff 1193 return HAL_OK;
bogdanm 0:9b334a45a8ff 1194 }
bogdanm 0:9b334a45a8ff 1195
bogdanm 0:9b334a45a8ff 1196 /**
bogdanm 0:9b334a45a8ff 1197 * @brief Stops the PWM signal generation in interrupt mode.
bogdanm 0:9b334a45a8ff 1198 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1199 * @param Channel : TIM Channels to be disabled
bogdanm 0:9b334a45a8ff 1200 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1201 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1202 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1203 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1204 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1205 * @retval HAL status
bogdanm 0:9b334a45a8ff 1206 */
bogdanm 0:9b334a45a8ff 1207 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1208 {
bogdanm 0:9b334a45a8ff 1209 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1210 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1211
bogdanm 0:9b334a45a8ff 1212 switch (Channel)
bogdanm 0:9b334a45a8ff 1213 {
bogdanm 0:9b334a45a8ff 1214 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1215 {
bogdanm 0:9b334a45a8ff 1216 /* Disable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 1217 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 1218 }
bogdanm 0:9b334a45a8ff 1219 break;
bogdanm 0:9b334a45a8ff 1220
bogdanm 0:9b334a45a8ff 1221 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1222 {
bogdanm 0:9b334a45a8ff 1223 /* Disable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 1224 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 1225 }
bogdanm 0:9b334a45a8ff 1226 break;
bogdanm 0:9b334a45a8ff 1227
bogdanm 0:9b334a45a8ff 1228 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1229 {
bogdanm 0:9b334a45a8ff 1230 /* Disable the TIM Capture/Compare 3 interrupt */
bogdanm 0:9b334a45a8ff 1231 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 1232 }
bogdanm 0:9b334a45a8ff 1233 break;
bogdanm 0:9b334a45a8ff 1234
bogdanm 0:9b334a45a8ff 1235 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1236 {
bogdanm 0:9b334a45a8ff 1237 /* Disable the TIM Capture/Compare 4 interrupt */
bogdanm 0:9b334a45a8ff 1238 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 1239 }
bogdanm 0:9b334a45a8ff 1240 break;
bogdanm 0:9b334a45a8ff 1241
bogdanm 0:9b334a45a8ff 1242 default:
bogdanm 0:9b334a45a8ff 1243 break;
bogdanm 0:9b334a45a8ff 1244 }
bogdanm 0:9b334a45a8ff 1245
bogdanm 0:9b334a45a8ff 1246 /* Disable the Capture compare channel */
bogdanm 0:9b334a45a8ff 1247 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 1248
bogdanm 0:9b334a45a8ff 1249 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 1250 {
bogdanm 0:9b334a45a8ff 1251 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 1252 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1253 }
bogdanm 0:9b334a45a8ff 1254
bogdanm 0:9b334a45a8ff 1255 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1256 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1257
bogdanm 0:9b334a45a8ff 1258 /* Return function status */
bogdanm 0:9b334a45a8ff 1259 return HAL_OK;
bogdanm 0:9b334a45a8ff 1260 }
bogdanm 0:9b334a45a8ff 1261
bogdanm 0:9b334a45a8ff 1262 /**
bogdanm 0:9b334a45a8ff 1263 * @brief Starts the TIM PWM signal generation in DMA mode.
bogdanm 0:9b334a45a8ff 1264 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1265 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 1266 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1267 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1268 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1269 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1270 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1271 * @param pData : The source Buffer address.
bogdanm 0:9b334a45a8ff 1272 * @param Length : The length of data to be transferred from memory to TIM peripheral
bogdanm 0:9b334a45a8ff 1273 * @retval HAL status
bogdanm 0:9b334a45a8ff 1274 */
bogdanm 0:9b334a45a8ff 1275 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
bogdanm 0:9b334a45a8ff 1276 {
bogdanm 0:9b334a45a8ff 1277 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1278 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1279
bogdanm 0:9b334a45a8ff 1280 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 1281 {
bogdanm 0:9b334a45a8ff 1282 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1283 }
bogdanm 0:9b334a45a8ff 1284 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 1285 {
bogdanm 0:9b334a45a8ff 1286 if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm 0:9b334a45a8ff 1287 {
bogdanm 0:9b334a45a8ff 1288 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1289 }
bogdanm 0:9b334a45a8ff 1290 else
bogdanm 0:9b334a45a8ff 1291 {
bogdanm 0:9b334a45a8ff 1292 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1293 }
bogdanm 0:9b334a45a8ff 1294 }
bogdanm 0:9b334a45a8ff 1295 switch (Channel)
bogdanm 0:9b334a45a8ff 1296 {
bogdanm 0:9b334a45a8ff 1297 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1298 {
bogdanm 0:9b334a45a8ff 1299 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1300 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 1301
bogdanm 0:9b334a45a8ff 1302 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1303 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1304
bogdanm 0:9b334a45a8ff 1305 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 1306 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm 0:9b334a45a8ff 1307
bogdanm 0:9b334a45a8ff 1308 /* Enable the TIM Capture/Compare 1 DMA request */
bogdanm 0:9b334a45a8ff 1309 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 1310 }
bogdanm 0:9b334a45a8ff 1311 break;
bogdanm 0:9b334a45a8ff 1312
bogdanm 0:9b334a45a8ff 1313 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1314 {
bogdanm 0:9b334a45a8ff 1315 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1316 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 1317
bogdanm 0:9b334a45a8ff 1318 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1319 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1320
bogdanm 0:9b334a45a8ff 1321 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 1322 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm 0:9b334a45a8ff 1323
bogdanm 0:9b334a45a8ff 1324 /* Enable the TIM Capture/Compare 2 DMA request */
bogdanm 0:9b334a45a8ff 1325 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 1326 }
bogdanm 0:9b334a45a8ff 1327 break;
bogdanm 0:9b334a45a8ff 1328
bogdanm 0:9b334a45a8ff 1329 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1330 {
bogdanm 0:9b334a45a8ff 1331 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1332 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 1333
bogdanm 0:9b334a45a8ff 1334 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1335 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1336
bogdanm 0:9b334a45a8ff 1337 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 1338 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm 0:9b334a45a8ff 1339
bogdanm 0:9b334a45a8ff 1340 /* Enable the TIM Output Capture/Compare 3 request */
bogdanm 0:9b334a45a8ff 1341 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 1342 }
bogdanm 0:9b334a45a8ff 1343 break;
bogdanm 0:9b334a45a8ff 1344
bogdanm 0:9b334a45a8ff 1345 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1346 {
bogdanm 0:9b334a45a8ff 1347 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1348 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 1349
bogdanm 0:9b334a45a8ff 1350 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1351 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1352
bogdanm 0:9b334a45a8ff 1353 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 1354 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm 0:9b334a45a8ff 1355
bogdanm 0:9b334a45a8ff 1356 /* Enable the TIM Capture/Compare 4 DMA request */
bogdanm 0:9b334a45a8ff 1357 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 1358 }
bogdanm 0:9b334a45a8ff 1359 break;
bogdanm 0:9b334a45a8ff 1360
bogdanm 0:9b334a45a8ff 1361 default:
bogdanm 0:9b334a45a8ff 1362 break;
bogdanm 0:9b334a45a8ff 1363 }
bogdanm 0:9b334a45a8ff 1364
bogdanm 0:9b334a45a8ff 1365 /* Enable the Capture compare channel */
bogdanm 0:9b334a45a8ff 1366 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 1367
bogdanm 0:9b334a45a8ff 1368 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 1369 {
bogdanm 0:9b334a45a8ff 1370 /* Enable the main output */
bogdanm 0:9b334a45a8ff 1371 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1372 }
bogdanm 0:9b334a45a8ff 1373
bogdanm 0:9b334a45a8ff 1374 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 1375 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1376
bogdanm 0:9b334a45a8ff 1377 /* Return function status */
bogdanm 0:9b334a45a8ff 1378 return HAL_OK;
bogdanm 0:9b334a45a8ff 1379 }
bogdanm 0:9b334a45a8ff 1380
bogdanm 0:9b334a45a8ff 1381 /**
bogdanm 0:9b334a45a8ff 1382 * @brief Stops the TIM PWM signal generation in DMA mode.
bogdanm 0:9b334a45a8ff 1383 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1384 * @param Channel : TIM Channels to be disabled
bogdanm 0:9b334a45a8ff 1385 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1386 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1387 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1388 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1389 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1390 * @retval HAL status
bogdanm 0:9b334a45a8ff 1391 */
bogdanm 0:9b334a45a8ff 1392 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1393 {
bogdanm 0:9b334a45a8ff 1394 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1395 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1396
bogdanm 0:9b334a45a8ff 1397 switch (Channel)
bogdanm 0:9b334a45a8ff 1398 {
bogdanm 0:9b334a45a8ff 1399 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1400 {
bogdanm 0:9b334a45a8ff 1401 /* Disable the TIM Capture/Compare 1 DMA request */
bogdanm 0:9b334a45a8ff 1402 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 1403 }
bogdanm 0:9b334a45a8ff 1404 break;
bogdanm 0:9b334a45a8ff 1405
bogdanm 0:9b334a45a8ff 1406 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1407 {
bogdanm 0:9b334a45a8ff 1408 /* Disable the TIM Capture/Compare 2 DMA request */
bogdanm 0:9b334a45a8ff 1409 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 1410 }
bogdanm 0:9b334a45a8ff 1411 break;
bogdanm 0:9b334a45a8ff 1412
bogdanm 0:9b334a45a8ff 1413 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1414 {
bogdanm 0:9b334a45a8ff 1415 /* Disable the TIM Capture/Compare 3 DMA request */
bogdanm 0:9b334a45a8ff 1416 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 1417 }
bogdanm 0:9b334a45a8ff 1418 break;
bogdanm 0:9b334a45a8ff 1419
bogdanm 0:9b334a45a8ff 1420 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1421 {
bogdanm 0:9b334a45a8ff 1422 /* Disable the TIM Capture/Compare 4 interrupt */
bogdanm 0:9b334a45a8ff 1423 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 1424 }
bogdanm 0:9b334a45a8ff 1425 break;
bogdanm 0:9b334a45a8ff 1426
bogdanm 0:9b334a45a8ff 1427 default:
bogdanm 0:9b334a45a8ff 1428 break;
bogdanm 0:9b334a45a8ff 1429 }
bogdanm 0:9b334a45a8ff 1430
bogdanm 0:9b334a45a8ff 1431 /* Disable the Capture compare channel */
bogdanm 0:9b334a45a8ff 1432 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 1433
bogdanm 0:9b334a45a8ff 1434 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 1435 {
bogdanm 0:9b334a45a8ff 1436 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 1437 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1438 }
bogdanm 0:9b334a45a8ff 1439
bogdanm 0:9b334a45a8ff 1440 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1441 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1442
bogdanm 0:9b334a45a8ff 1443 /* Change the htim state */
bogdanm 0:9b334a45a8ff 1444 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 1445
bogdanm 0:9b334a45a8ff 1446 /* Return function status */
bogdanm 0:9b334a45a8ff 1447 return HAL_OK;
bogdanm 0:9b334a45a8ff 1448 }
bogdanm 0:9b334a45a8ff 1449
bogdanm 0:9b334a45a8ff 1450 /**
bogdanm 0:9b334a45a8ff 1451 * @}
bogdanm 0:9b334a45a8ff 1452 */
bogdanm 0:9b334a45a8ff 1453
bogdanm 0:9b334a45a8ff 1454 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
bogdanm 0:9b334a45a8ff 1455 * @brief Time Input Capture functions
bogdanm 0:9b334a45a8ff 1456 *
bogdanm 0:9b334a45a8ff 1457 @verbatim
bogdanm 0:9b334a45a8ff 1458 ==============================================================================
bogdanm 0:9b334a45a8ff 1459 ##### Time Input Capture functions #####
bogdanm 0:9b334a45a8ff 1460 ==============================================================================
bogdanm 0:9b334a45a8ff 1461 [..]
bogdanm 0:9b334a45a8ff 1462 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 1463 (+) Initialize and configure the TIM Input Capture.
bogdanm 0:9b334a45a8ff 1464 (+) De-initialize the TIM Input Capture.
bogdanm 0:9b334a45a8ff 1465 (+) Start the Time Input Capture.
bogdanm 0:9b334a45a8ff 1466 (+) Stop the Time Input Capture.
bogdanm 0:9b334a45a8ff 1467 (+) Start the Time Input Capture and enable interrupt.
bogdanm 0:9b334a45a8ff 1468 (+) Stop the Time Input Capture and disable interrupt.
bogdanm 0:9b334a45a8ff 1469 (+) Start the Time Input Capture and enable DMA transfer.
bogdanm 0:9b334a45a8ff 1470 (+) Stop the Time Input Capture and disable DMA transfer.
bogdanm 0:9b334a45a8ff 1471
bogdanm 0:9b334a45a8ff 1472 @endverbatim
bogdanm 0:9b334a45a8ff 1473 * @{
bogdanm 0:9b334a45a8ff 1474 */
bogdanm 0:9b334a45a8ff 1475 /**
bogdanm 0:9b334a45a8ff 1476 * @brief Initializes the TIM Input Capture Time base according to the specified
bogdanm 0:9b334a45a8ff 1477 * parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 1478 * @param htim : TIM Input Capture handle
bogdanm 0:9b334a45a8ff 1479 * @retval HAL status
bogdanm 0:9b334a45a8ff 1480 */
bogdanm 0:9b334a45a8ff 1481 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 1482 {
bogdanm 0:9b334a45a8ff 1483 /* Check the TIM handle allocation */
bogdanm 0:9b334a45a8ff 1484 if(htim == NULL)
bogdanm 0:9b334a45a8ff 1485 {
bogdanm 0:9b334a45a8ff 1486 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1487 }
bogdanm 0:9b334a45a8ff 1488
bogdanm 0:9b334a45a8ff 1489 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1490 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1491 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm 0:9b334a45a8ff 1492 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm 0:9b334a45a8ff 1493
bogdanm 0:9b334a45a8ff 1494 if(htim->State == HAL_TIM_STATE_RESET)
bogdanm 0:9b334a45a8ff 1495 {
bogdanm 0:9b334a45a8ff 1496 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 1497 htim->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 1498
bogdanm 0:9b334a45a8ff 1499 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm 0:9b334a45a8ff 1500 HAL_TIM_IC_MspInit(htim);
bogdanm 0:9b334a45a8ff 1501 }
bogdanm 0:9b334a45a8ff 1502
bogdanm 0:9b334a45a8ff 1503 /* Set the TIM state */
bogdanm 0:9b334a45a8ff 1504 htim->State= HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1505
bogdanm 0:9b334a45a8ff 1506 /* Init the base time for the input capture */
bogdanm 0:9b334a45a8ff 1507 TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm 0:9b334a45a8ff 1508
bogdanm 0:9b334a45a8ff 1509 /* Initialize the TIM state*/
bogdanm 0:9b334a45a8ff 1510 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 1511
bogdanm 0:9b334a45a8ff 1512 return HAL_OK;
bogdanm 0:9b334a45a8ff 1513 }
bogdanm 0:9b334a45a8ff 1514
bogdanm 0:9b334a45a8ff 1515 /**
bogdanm 0:9b334a45a8ff 1516 * @brief DeInitializes the TIM peripheral
bogdanm 0:9b334a45a8ff 1517 * @param htim : TIM Input Capture handle
bogdanm 0:9b334a45a8ff 1518 * @retval HAL status
bogdanm 0:9b334a45a8ff 1519 */
bogdanm 0:9b334a45a8ff 1520 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 1521 {
bogdanm 0:9b334a45a8ff 1522 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1523 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1524
bogdanm 0:9b334a45a8ff 1525 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1526
bogdanm 0:9b334a45a8ff 1527 /* Disable the TIM Peripheral Clock */
bogdanm 0:9b334a45a8ff 1528 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1529
bogdanm 0:9b334a45a8ff 1530 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
bogdanm 0:9b334a45a8ff 1531 HAL_TIM_IC_MspDeInit(htim);
bogdanm 0:9b334a45a8ff 1532
bogdanm 0:9b334a45a8ff 1533 /* Change TIM state */
bogdanm 0:9b334a45a8ff 1534 htim->State = HAL_TIM_STATE_RESET;
bogdanm 0:9b334a45a8ff 1535
bogdanm 0:9b334a45a8ff 1536 /* Release Lock */
bogdanm 0:9b334a45a8ff 1537 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 1538
bogdanm 0:9b334a45a8ff 1539 return HAL_OK;
bogdanm 0:9b334a45a8ff 1540 }
bogdanm 0:9b334a45a8ff 1541
bogdanm 0:9b334a45a8ff 1542 /**
bogdanm 0:9b334a45a8ff 1543 * @brief Initializes the TIM Input Capture MSP.
bogdanm 0:9b334a45a8ff 1544 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1545 * @retval None
bogdanm 0:9b334a45a8ff 1546 */
bogdanm 0:9b334a45a8ff 1547 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 1548 {
bogdanm 0:9b334a45a8ff 1549 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1550 the HAL_TIM_IC_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 1551 */
bogdanm 0:9b334a45a8ff 1552 }
bogdanm 0:9b334a45a8ff 1553
bogdanm 0:9b334a45a8ff 1554 /**
bogdanm 0:9b334a45a8ff 1555 * @brief DeInitializes TIM Input Capture MSP.
bogdanm 0:9b334a45a8ff 1556 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1557 * @retval None
bogdanm 0:9b334a45a8ff 1558 */
bogdanm 0:9b334a45a8ff 1559 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 1560 {
bogdanm 0:9b334a45a8ff 1561 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1562 the HAL_TIM_IC_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 1563 */
bogdanm 0:9b334a45a8ff 1564 }
bogdanm 0:9b334a45a8ff 1565
bogdanm 0:9b334a45a8ff 1566 /**
bogdanm 0:9b334a45a8ff 1567 * @brief Starts the TIM Input Capture measurement.
bogdanm 0:9b334a45a8ff 1568 * @param htim : TIM Input Capture handle
bogdanm 0:9b334a45a8ff 1569 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 1570 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1571 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1572 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1573 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1574 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1575 * @retval HAL status
bogdanm 0:9b334a45a8ff 1576 */
bogdanm 0:9b334a45a8ff 1577 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1578 {
bogdanm 0:9b334a45a8ff 1579 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1580 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1581
bogdanm 0:9b334a45a8ff 1582 /* Enable the Input Capture channel */
bogdanm 0:9b334a45a8ff 1583 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 1584
bogdanm 0:9b334a45a8ff 1585 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 1586 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1587
bogdanm 0:9b334a45a8ff 1588 /* Return function status */
bogdanm 0:9b334a45a8ff 1589 return HAL_OK;
bogdanm 0:9b334a45a8ff 1590 }
bogdanm 0:9b334a45a8ff 1591
bogdanm 0:9b334a45a8ff 1592 /**
bogdanm 0:9b334a45a8ff 1593 * @brief Stops the TIM Input Capture measurement.
bogdanm 0:9b334a45a8ff 1594 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1595 * @param Channel : TIM Channels to be disabled
bogdanm 0:9b334a45a8ff 1596 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1597 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1598 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1599 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1600 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1601 * @retval HAL status
bogdanm 0:9b334a45a8ff 1602 */
bogdanm 0:9b334a45a8ff 1603 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1604 {
bogdanm 0:9b334a45a8ff 1605 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1606 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1607
bogdanm 0:9b334a45a8ff 1608 /* Disable the Input Capture channel */
bogdanm 0:9b334a45a8ff 1609 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 1610
bogdanm 0:9b334a45a8ff 1611 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1612 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1613
bogdanm 0:9b334a45a8ff 1614 /* Return function status */
bogdanm 0:9b334a45a8ff 1615 return HAL_OK;
bogdanm 0:9b334a45a8ff 1616 }
bogdanm 0:9b334a45a8ff 1617
bogdanm 0:9b334a45a8ff 1618 /**
bogdanm 0:9b334a45a8ff 1619 * @brief Starts the TIM Input Capture measurement in interrupt mode.
bogdanm 0:9b334a45a8ff 1620 * @param htim : TIM Input Capture handle
bogdanm 0:9b334a45a8ff 1621 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 1622 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1623 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1624 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1625 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1626 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1627 * @retval HAL status
bogdanm 0:9b334a45a8ff 1628 */
bogdanm 0:9b334a45a8ff 1629 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1630 {
bogdanm 0:9b334a45a8ff 1631 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1632 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1633
bogdanm 0:9b334a45a8ff 1634 switch (Channel)
bogdanm 0:9b334a45a8ff 1635 {
bogdanm 0:9b334a45a8ff 1636 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1637 {
bogdanm 0:9b334a45a8ff 1638 /* Enable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 1639 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 1640 }
bogdanm 0:9b334a45a8ff 1641 break;
bogdanm 0:9b334a45a8ff 1642
bogdanm 0:9b334a45a8ff 1643 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1644 {
bogdanm 0:9b334a45a8ff 1645 /* Enable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 1646 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 1647 }
bogdanm 0:9b334a45a8ff 1648 break;
bogdanm 0:9b334a45a8ff 1649
bogdanm 0:9b334a45a8ff 1650 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1651 {
bogdanm 0:9b334a45a8ff 1652 /* Enable the TIM Capture/Compare 3 interrupt */
bogdanm 0:9b334a45a8ff 1653 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 1654 }
bogdanm 0:9b334a45a8ff 1655 break;
bogdanm 0:9b334a45a8ff 1656
bogdanm 0:9b334a45a8ff 1657 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1658 {
bogdanm 0:9b334a45a8ff 1659 /* Enable the TIM Capture/Compare 4 interrupt */
bogdanm 0:9b334a45a8ff 1660 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 1661 }
bogdanm 0:9b334a45a8ff 1662 break;
bogdanm 0:9b334a45a8ff 1663
bogdanm 0:9b334a45a8ff 1664 default:
bogdanm 0:9b334a45a8ff 1665 break;
bogdanm 0:9b334a45a8ff 1666 }
bogdanm 0:9b334a45a8ff 1667 /* Enable the Input Capture channel */
bogdanm 0:9b334a45a8ff 1668 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 1669
bogdanm 0:9b334a45a8ff 1670 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 1671 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1672
bogdanm 0:9b334a45a8ff 1673 /* Return function status */
bogdanm 0:9b334a45a8ff 1674 return HAL_OK;
bogdanm 0:9b334a45a8ff 1675 }
bogdanm 0:9b334a45a8ff 1676
bogdanm 0:9b334a45a8ff 1677 /**
bogdanm 0:9b334a45a8ff 1678 * @brief Stops the TIM Input Capture measurement in interrupt mode.
bogdanm 0:9b334a45a8ff 1679 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 1680 * @param Channel : TIM Channels to be disabled
bogdanm 0:9b334a45a8ff 1681 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1682 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1683 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1684 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1685 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1686 * @retval HAL status
bogdanm 0:9b334a45a8ff 1687 */
bogdanm 0:9b334a45a8ff 1688 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1689 {
bogdanm 0:9b334a45a8ff 1690 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1691 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1692
bogdanm 0:9b334a45a8ff 1693 switch (Channel)
bogdanm 0:9b334a45a8ff 1694 {
bogdanm 0:9b334a45a8ff 1695 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1696 {
bogdanm 0:9b334a45a8ff 1697 /* Disable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 1698 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 1699 }
bogdanm 0:9b334a45a8ff 1700 break;
bogdanm 0:9b334a45a8ff 1701
bogdanm 0:9b334a45a8ff 1702 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1703 {
bogdanm 0:9b334a45a8ff 1704 /* Disable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 1705 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 1706 }
bogdanm 0:9b334a45a8ff 1707 break;
bogdanm 0:9b334a45a8ff 1708
bogdanm 0:9b334a45a8ff 1709 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1710 {
bogdanm 0:9b334a45a8ff 1711 /* Disable the TIM Capture/Compare 3 interrupt */
bogdanm 0:9b334a45a8ff 1712 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 1713 }
bogdanm 0:9b334a45a8ff 1714 break;
bogdanm 0:9b334a45a8ff 1715
bogdanm 0:9b334a45a8ff 1716 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1717 {
bogdanm 0:9b334a45a8ff 1718 /* Disable the TIM Capture/Compare 4 interrupt */
bogdanm 0:9b334a45a8ff 1719 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 1720 }
bogdanm 0:9b334a45a8ff 1721 break;
bogdanm 0:9b334a45a8ff 1722
bogdanm 0:9b334a45a8ff 1723 default:
bogdanm 0:9b334a45a8ff 1724 break;
bogdanm 0:9b334a45a8ff 1725 }
bogdanm 0:9b334a45a8ff 1726
bogdanm 0:9b334a45a8ff 1727 /* Disable the Input Capture channel */
bogdanm 0:9b334a45a8ff 1728 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 1729
bogdanm 0:9b334a45a8ff 1730 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1731 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1732
bogdanm 0:9b334a45a8ff 1733 /* Return function status */
bogdanm 0:9b334a45a8ff 1734 return HAL_OK;
bogdanm 0:9b334a45a8ff 1735 }
bogdanm 0:9b334a45a8ff 1736
bogdanm 0:9b334a45a8ff 1737 /**
bogdanm 0:9b334a45a8ff 1738 * @brief Starts the TIM Input Capture measurement in DMA mode.
bogdanm 0:9b334a45a8ff 1739 * @param htim : TIM Input Capture handle
bogdanm 0:9b334a45a8ff 1740 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 1741 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1742 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1743 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1744 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1745 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1746 * @param pData : The destination Buffer address.
bogdanm 0:9b334a45a8ff 1747 * @param Length : The length of data to be transferred from TIM peripheral to memory.
bogdanm 0:9b334a45a8ff 1748 * @retval HAL status
bogdanm 0:9b334a45a8ff 1749 */
bogdanm 0:9b334a45a8ff 1750 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
bogdanm 0:9b334a45a8ff 1751 {
bogdanm 0:9b334a45a8ff 1752 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1753 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1754 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1755
bogdanm 0:9b334a45a8ff 1756 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 1757 {
bogdanm 0:9b334a45a8ff 1758 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1759 }
bogdanm 0:9b334a45a8ff 1760 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 1761 {
bogdanm 0:9b334a45a8ff 1762 if((pData == 0 ) && (Length > 0))
bogdanm 0:9b334a45a8ff 1763 {
bogdanm 0:9b334a45a8ff 1764 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1765 }
bogdanm 0:9b334a45a8ff 1766 else
bogdanm 0:9b334a45a8ff 1767 {
bogdanm 0:9b334a45a8ff 1768 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1769 }
bogdanm 0:9b334a45a8ff 1770 }
bogdanm 0:9b334a45a8ff 1771
bogdanm 0:9b334a45a8ff 1772 switch (Channel)
bogdanm 0:9b334a45a8ff 1773 {
bogdanm 0:9b334a45a8ff 1774 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1775 {
bogdanm 0:9b334a45a8ff 1776 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1777 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 1778
bogdanm 0:9b334a45a8ff 1779 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1780 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1781
bogdanm 0:9b334a45a8ff 1782 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 1783 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
bogdanm 0:9b334a45a8ff 1784
bogdanm 0:9b334a45a8ff 1785 /* Enable the TIM Capture/Compare 1 DMA request */
bogdanm 0:9b334a45a8ff 1786 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 1787 }
bogdanm 0:9b334a45a8ff 1788 break;
bogdanm 0:9b334a45a8ff 1789
bogdanm 0:9b334a45a8ff 1790 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1791 {
bogdanm 0:9b334a45a8ff 1792 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1793 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 1794
bogdanm 0:9b334a45a8ff 1795 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1796 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1797
bogdanm 0:9b334a45a8ff 1798 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 1799 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
bogdanm 0:9b334a45a8ff 1800
bogdanm 0:9b334a45a8ff 1801 /* Enable the TIM Capture/Compare 2 DMA request */
bogdanm 0:9b334a45a8ff 1802 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 1803 }
bogdanm 0:9b334a45a8ff 1804 break;
bogdanm 0:9b334a45a8ff 1805
bogdanm 0:9b334a45a8ff 1806 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1807 {
bogdanm 0:9b334a45a8ff 1808 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1809 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 1810
bogdanm 0:9b334a45a8ff 1811 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1812 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1813
bogdanm 0:9b334a45a8ff 1814 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 1815 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
bogdanm 0:9b334a45a8ff 1816
bogdanm 0:9b334a45a8ff 1817 /* Enable the TIM Capture/Compare 3 DMA request */
bogdanm 0:9b334a45a8ff 1818 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 1819 }
bogdanm 0:9b334a45a8ff 1820 break;
bogdanm 0:9b334a45a8ff 1821
bogdanm 0:9b334a45a8ff 1822 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1823 {
bogdanm 0:9b334a45a8ff 1824 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 1825 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 1826
bogdanm 0:9b334a45a8ff 1827 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 1828 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 1829
bogdanm 0:9b334a45a8ff 1830 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 1831 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
bogdanm 0:9b334a45a8ff 1832
bogdanm 0:9b334a45a8ff 1833 /* Enable the TIM Capture/Compare 4 DMA request */
bogdanm 0:9b334a45a8ff 1834 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 1835 }
bogdanm 0:9b334a45a8ff 1836 break;
bogdanm 0:9b334a45a8ff 1837
bogdanm 0:9b334a45a8ff 1838 default:
bogdanm 0:9b334a45a8ff 1839 break;
bogdanm 0:9b334a45a8ff 1840 }
bogdanm 0:9b334a45a8ff 1841
bogdanm 0:9b334a45a8ff 1842 /* Enable the Input Capture channel */
bogdanm 0:9b334a45a8ff 1843 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 1844
bogdanm 0:9b334a45a8ff 1845 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 1846 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 1847
bogdanm 0:9b334a45a8ff 1848 /* Return function status */
bogdanm 0:9b334a45a8ff 1849 return HAL_OK;
bogdanm 0:9b334a45a8ff 1850 }
bogdanm 0:9b334a45a8ff 1851
bogdanm 0:9b334a45a8ff 1852 /**
bogdanm 0:9b334a45a8ff 1853 * @brief Stops the TIM Input Capture measurement in DMA mode.
bogdanm 0:9b334a45a8ff 1854 * @param htim : TIM Input Capture handle
bogdanm 0:9b334a45a8ff 1855 * @param Channel : TIM Channels to be disabled
bogdanm 0:9b334a45a8ff 1856 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1857 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 1858 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 1859 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 1860 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 1861 * @retval HAL status
bogdanm 0:9b334a45a8ff 1862 */
bogdanm 0:9b334a45a8ff 1863 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 1864 {
bogdanm 0:9b334a45a8ff 1865 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1866 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
bogdanm 0:9b334a45a8ff 1867 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1868
bogdanm 0:9b334a45a8ff 1869 switch (Channel)
bogdanm 0:9b334a45a8ff 1870 {
bogdanm 0:9b334a45a8ff 1871 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 1872 {
bogdanm 0:9b334a45a8ff 1873 /* Disable the TIM Capture/Compare 1 DMA request */
bogdanm 0:9b334a45a8ff 1874 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 1875 }
bogdanm 0:9b334a45a8ff 1876 break;
bogdanm 0:9b334a45a8ff 1877
bogdanm 0:9b334a45a8ff 1878 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 1879 {
bogdanm 0:9b334a45a8ff 1880 /* Disable the TIM Capture/Compare 2 DMA request */
bogdanm 0:9b334a45a8ff 1881 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 1882 }
bogdanm 0:9b334a45a8ff 1883 break;
bogdanm 0:9b334a45a8ff 1884
bogdanm 0:9b334a45a8ff 1885 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 1886 {
bogdanm 0:9b334a45a8ff 1887 /* Disable the TIM Capture/Compare 3 DMA request */
bogdanm 0:9b334a45a8ff 1888 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm 0:9b334a45a8ff 1889 }
bogdanm 0:9b334a45a8ff 1890 break;
bogdanm 0:9b334a45a8ff 1891
bogdanm 0:9b334a45a8ff 1892 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 1893 {
bogdanm 0:9b334a45a8ff 1894 /* Disable the TIM Capture/Compare 4 DMA request */
bogdanm 0:9b334a45a8ff 1895 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm 0:9b334a45a8ff 1896 }
bogdanm 0:9b334a45a8ff 1897 break;
bogdanm 0:9b334a45a8ff 1898
bogdanm 0:9b334a45a8ff 1899 default:
bogdanm 0:9b334a45a8ff 1900 break;
bogdanm 0:9b334a45a8ff 1901 }
bogdanm 0:9b334a45a8ff 1902
bogdanm 0:9b334a45a8ff 1903 /* Disable the Input Capture channel */
bogdanm 0:9b334a45a8ff 1904 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 1905
bogdanm 0:9b334a45a8ff 1906 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 1907 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 1908
bogdanm 0:9b334a45a8ff 1909 /* Change the htim state */
bogdanm 0:9b334a45a8ff 1910 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 1911
bogdanm 0:9b334a45a8ff 1912 /* Return function status */
bogdanm 0:9b334a45a8ff 1913 return HAL_OK;
bogdanm 0:9b334a45a8ff 1914 }
bogdanm 0:9b334a45a8ff 1915 /**
bogdanm 0:9b334a45a8ff 1916 * @}
bogdanm 0:9b334a45a8ff 1917 */
bogdanm 0:9b334a45a8ff 1918
bogdanm 0:9b334a45a8ff 1919 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
bogdanm 0:9b334a45a8ff 1920 * @brief Time One Pulse functions
bogdanm 0:9b334a45a8ff 1921 *
bogdanm 0:9b334a45a8ff 1922 @verbatim
bogdanm 0:9b334a45a8ff 1923 ==============================================================================
bogdanm 0:9b334a45a8ff 1924 ##### Time One Pulse functions #####
bogdanm 0:9b334a45a8ff 1925 ==============================================================================
bogdanm 0:9b334a45a8ff 1926 [..]
bogdanm 0:9b334a45a8ff 1927 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 1928 (+) Initialize and configure the TIM One Pulse.
bogdanm 0:9b334a45a8ff 1929 (+) De-initialize the TIM One Pulse.
bogdanm 0:9b334a45a8ff 1930 (+) Start the Time One Pulse.
bogdanm 0:9b334a45a8ff 1931 (+) Stop the Time One Pulse.
bogdanm 0:9b334a45a8ff 1932 (+) Start the Time One Pulse and enable interrupt.
bogdanm 0:9b334a45a8ff 1933 (+) Stop the Time One Pulse and disable interrupt.
bogdanm 0:9b334a45a8ff 1934 (+) Start the Time One Pulse and enable DMA transfer.
bogdanm 0:9b334a45a8ff 1935 (+) Stop the Time One Pulse and disable DMA transfer.
bogdanm 0:9b334a45a8ff 1936
bogdanm 0:9b334a45a8ff 1937 @endverbatim
bogdanm 0:9b334a45a8ff 1938 * @{
bogdanm 0:9b334a45a8ff 1939 */
bogdanm 0:9b334a45a8ff 1940 /**
bogdanm 0:9b334a45a8ff 1941 * @brief Initializes the TIM One Pulse Time Base according to the specified
bogdanm 0:9b334a45a8ff 1942 * parameters in the TIM_HandleTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 1943 * @param htim : TIM OnePulse handle
bogdanm 0:9b334a45a8ff 1944 * @param OnePulseMode : Select the One pulse mode.
bogdanm 0:9b334a45a8ff 1945 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1946 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
bogdanm 0:9b334a45a8ff 1947 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
bogdanm 0:9b334a45a8ff 1948 * @retval HAL status
bogdanm 0:9b334a45a8ff 1949 */
bogdanm 0:9b334a45a8ff 1950 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
bogdanm 0:9b334a45a8ff 1951 {
bogdanm 0:9b334a45a8ff 1952 /* Check the TIM handle allocation */
bogdanm 0:9b334a45a8ff 1953 if(htim == NULL)
bogdanm 0:9b334a45a8ff 1954 {
bogdanm 0:9b334a45a8ff 1955 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1956 }
bogdanm 0:9b334a45a8ff 1957
bogdanm 0:9b334a45a8ff 1958 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1959 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 1960 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm 0:9b334a45a8ff 1961 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm 0:9b334a45a8ff 1962 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
bogdanm 0:9b334a45a8ff 1963
bogdanm 0:9b334a45a8ff 1964 if(htim->State == HAL_TIM_STATE_RESET)
bogdanm 0:9b334a45a8ff 1965 {
bogdanm 0:9b334a45a8ff 1966 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 1967 htim->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 1968
bogdanm 0:9b334a45a8ff 1969 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm 0:9b334a45a8ff 1970 HAL_TIM_OnePulse_MspInit(htim);
bogdanm 0:9b334a45a8ff 1971 }
bogdanm 0:9b334a45a8ff 1972
bogdanm 0:9b334a45a8ff 1973 /* Set the TIM state */
bogdanm 0:9b334a45a8ff 1974 htim->State= HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1975
bogdanm 0:9b334a45a8ff 1976 /* Configure the Time base in the One Pulse Mode */
bogdanm 0:9b334a45a8ff 1977 TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm 0:9b334a45a8ff 1978
bogdanm 0:9b334a45a8ff 1979 /* Reset the OPM Bit */
bogdanm 0:9b334a45a8ff 1980 htim->Instance->CR1 &= ~TIM_CR1_OPM;
bogdanm 0:9b334a45a8ff 1981
bogdanm 0:9b334a45a8ff 1982 /* Configure the OPM Mode */
bogdanm 0:9b334a45a8ff 1983 htim->Instance->CR1 |= OnePulseMode;
bogdanm 0:9b334a45a8ff 1984
bogdanm 0:9b334a45a8ff 1985 /* Initialize the TIM state*/
bogdanm 0:9b334a45a8ff 1986 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 1987
bogdanm 0:9b334a45a8ff 1988 return HAL_OK;
bogdanm 0:9b334a45a8ff 1989 }
bogdanm 0:9b334a45a8ff 1990
bogdanm 0:9b334a45a8ff 1991 /**
bogdanm 0:9b334a45a8ff 1992 * @brief DeInitializes the TIM One Pulse
bogdanm 0:9b334a45a8ff 1993 * @param htim : TIM One Pulse handle
bogdanm 0:9b334a45a8ff 1994 * @retval HAL status
bogdanm 0:9b334a45a8ff 1995 */
bogdanm 0:9b334a45a8ff 1996 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 1997 {
bogdanm 0:9b334a45a8ff 1998 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1999 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2000
bogdanm 0:9b334a45a8ff 2001 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 2002
bogdanm 0:9b334a45a8ff 2003 /* Disable the TIM Peripheral Clock */
bogdanm 0:9b334a45a8ff 2004 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 2005
bogdanm 0:9b334a45a8ff 2006 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm 0:9b334a45a8ff 2007 HAL_TIM_OnePulse_MspDeInit(htim);
bogdanm 0:9b334a45a8ff 2008
bogdanm 0:9b334a45a8ff 2009 /* Change TIM state */
bogdanm 0:9b334a45a8ff 2010 htim->State = HAL_TIM_STATE_RESET;
bogdanm 0:9b334a45a8ff 2011
bogdanm 0:9b334a45a8ff 2012 /* Release Lock */
bogdanm 0:9b334a45a8ff 2013 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2014
bogdanm 0:9b334a45a8ff 2015 return HAL_OK;
bogdanm 0:9b334a45a8ff 2016 }
bogdanm 0:9b334a45a8ff 2017
bogdanm 0:9b334a45a8ff 2018 /**
bogdanm 0:9b334a45a8ff 2019 * @brief Initializes the TIM One Pulse MSP.
bogdanm 0:9b334a45a8ff 2020 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 2021 * @retval None
bogdanm 0:9b334a45a8ff 2022 */
bogdanm 0:9b334a45a8ff 2023 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 2024 {
bogdanm 0:9b334a45a8ff 2025 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 2026 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 2027 */
bogdanm 0:9b334a45a8ff 2028 }
bogdanm 0:9b334a45a8ff 2029
bogdanm 0:9b334a45a8ff 2030 /**
bogdanm 0:9b334a45a8ff 2031 * @brief DeInitializes TIM One Pulse MSP.
bogdanm 0:9b334a45a8ff 2032 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 2033 * @retval None
bogdanm 0:9b334a45a8ff 2034 */
bogdanm 0:9b334a45a8ff 2035 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 2036 {
bogdanm 0:9b334a45a8ff 2037 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 2038 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 2039 */
bogdanm 0:9b334a45a8ff 2040 }
bogdanm 0:9b334a45a8ff 2041
bogdanm 0:9b334a45a8ff 2042 /**
bogdanm 0:9b334a45a8ff 2043 * @brief Starts the TIM One Pulse signal generation.
bogdanm 0:9b334a45a8ff 2044 * @param htim : TIM One Pulse handle
bogdanm 0:9b334a45a8ff 2045 * @param OutputChannel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 2046 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2047 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 2048 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 2049 * @retval HAL status
bogdanm 0:9b334a45a8ff 2050 */
bogdanm 0:9b334a45a8ff 2051 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm 0:9b334a45a8ff 2052 {
bogdanm 0:9b334a45a8ff 2053 /* Enable the Capture compare and the Input Capture channels
bogdanm 0:9b334a45a8ff 2054 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm 0:9b334a45a8ff 2055 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm 0:9b334a45a8ff 2056 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm 0:9b334a45a8ff 2057 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm 0:9b334a45a8ff 2058
bogdanm 0:9b334a45a8ff 2059 No need to enable the counter, it's enabled automatically by hardware
bogdanm 0:9b334a45a8ff 2060 (the counter starts in response to a stimulus and generate a pulse */
bogdanm 0:9b334a45a8ff 2061
bogdanm 0:9b334a45a8ff 2062 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2063 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2064
bogdanm 0:9b334a45a8ff 2065 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 2066 {
bogdanm 0:9b334a45a8ff 2067 /* Enable the main output */
bogdanm 0:9b334a45a8ff 2068 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 2069 }
bogdanm 0:9b334a45a8ff 2070
bogdanm 0:9b334a45a8ff 2071 /* Return function status */
bogdanm 0:9b334a45a8ff 2072 return HAL_OK;
bogdanm 0:9b334a45a8ff 2073 }
bogdanm 0:9b334a45a8ff 2074
bogdanm 0:9b334a45a8ff 2075 /**
bogdanm 0:9b334a45a8ff 2076 * @brief Stops the TIM One Pulse signal generation.
bogdanm 0:9b334a45a8ff 2077 * @param htim : TIM One Pulse handle
bogdanm 0:9b334a45a8ff 2078 * @param OutputChannel : TIM Channels to be disable
bogdanm 0:9b334a45a8ff 2079 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2080 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 2081 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 2082 * @retval HAL status
bogdanm 0:9b334a45a8ff 2083 */
bogdanm 0:9b334a45a8ff 2084 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm 0:9b334a45a8ff 2085 {
bogdanm 0:9b334a45a8ff 2086 /* Disable the Capture compare and the Input Capture channels
bogdanm 0:9b334a45a8ff 2087 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm 0:9b334a45a8ff 2088 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm 0:9b334a45a8ff 2089 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm 0:9b334a45a8ff 2090 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm 0:9b334a45a8ff 2091
bogdanm 0:9b334a45a8ff 2092 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2093 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2094
bogdanm 0:9b334a45a8ff 2095 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 2096 {
bogdanm 0:9b334a45a8ff 2097 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 2098 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 2099 }
bogdanm 0:9b334a45a8ff 2100
bogdanm 0:9b334a45a8ff 2101 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 2102 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 2103
bogdanm 0:9b334a45a8ff 2104 /* Return function status */
bogdanm 0:9b334a45a8ff 2105 return HAL_OK;
bogdanm 0:9b334a45a8ff 2106 }
bogdanm 0:9b334a45a8ff 2107
bogdanm 0:9b334a45a8ff 2108 /**
bogdanm 0:9b334a45a8ff 2109 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
bogdanm 0:9b334a45a8ff 2110 * @param htim : TIM One Pulse handle
bogdanm 0:9b334a45a8ff 2111 * @param OutputChannel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 2112 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2113 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 2114 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 2115 * @retval HAL status
bogdanm 0:9b334a45a8ff 2116 */
bogdanm 0:9b334a45a8ff 2117 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm 0:9b334a45a8ff 2118 {
bogdanm 0:9b334a45a8ff 2119 /* Enable the Capture compare and the Input Capture channels
bogdanm 0:9b334a45a8ff 2120 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm 0:9b334a45a8ff 2121 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm 0:9b334a45a8ff 2122 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm 0:9b334a45a8ff 2123 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
bogdanm 0:9b334a45a8ff 2124
bogdanm 0:9b334a45a8ff 2125 No need to enable the counter, it's enabled automatically by hardware
bogdanm 0:9b334a45a8ff 2126 (the counter starts in response to a stimulus and generate a pulse */
bogdanm 0:9b334a45a8ff 2127
bogdanm 0:9b334a45a8ff 2128 /* Enable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 2129 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 2130
bogdanm 0:9b334a45a8ff 2131 /* Enable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 2132 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 2133
bogdanm 0:9b334a45a8ff 2134 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2135 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2136
bogdanm 0:9b334a45a8ff 2137 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 2138 {
bogdanm 0:9b334a45a8ff 2139 /* Enable the main output */
bogdanm 0:9b334a45a8ff 2140 __HAL_TIM_MOE_ENABLE(htim);
bogdanm 0:9b334a45a8ff 2141 }
bogdanm 0:9b334a45a8ff 2142
bogdanm 0:9b334a45a8ff 2143 /* Return function status */
bogdanm 0:9b334a45a8ff 2144 return HAL_OK;
bogdanm 0:9b334a45a8ff 2145 }
bogdanm 0:9b334a45a8ff 2146
bogdanm 0:9b334a45a8ff 2147 /**
bogdanm 0:9b334a45a8ff 2148 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
bogdanm 0:9b334a45a8ff 2149 * @param htim : TIM One Pulse handle
bogdanm 0:9b334a45a8ff 2150 * @param OutputChannel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 2151 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2152 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 2153 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 2154 * @retval HAL status
bogdanm 0:9b334a45a8ff 2155 */
bogdanm 0:9b334a45a8ff 2156 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm 0:9b334a45a8ff 2157 {
bogdanm 0:9b334a45a8ff 2158 /* Disable the TIM Capture/Compare 1 interrupt */
bogdanm 0:9b334a45a8ff 2159 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 2160
bogdanm 0:9b334a45a8ff 2161 /* Disable the TIM Capture/Compare 2 interrupt */
bogdanm 0:9b334a45a8ff 2162 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 2163
bogdanm 0:9b334a45a8ff 2164 /* Disable the Capture compare and the Input Capture channels
bogdanm 0:9b334a45a8ff 2165 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
bogdanm 0:9b334a45a8ff 2166 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
bogdanm 0:9b334a45a8ff 2167 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
bogdanm 0:9b334a45a8ff 2168 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
bogdanm 0:9b334a45a8ff 2169 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2170 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2171
bogdanm 0:9b334a45a8ff 2172 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
bogdanm 0:9b334a45a8ff 2173 {
bogdanm 0:9b334a45a8ff 2174 /* Disable the Main Ouput */
bogdanm 0:9b334a45a8ff 2175 __HAL_TIM_MOE_DISABLE(htim);
bogdanm 0:9b334a45a8ff 2176 }
bogdanm 0:9b334a45a8ff 2177
bogdanm 0:9b334a45a8ff 2178 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 2179 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 2180
bogdanm 0:9b334a45a8ff 2181 /* Return function status */
bogdanm 0:9b334a45a8ff 2182 return HAL_OK;
bogdanm 0:9b334a45a8ff 2183 }
bogdanm 0:9b334a45a8ff 2184
bogdanm 0:9b334a45a8ff 2185 /**
bogdanm 0:9b334a45a8ff 2186 * @}
bogdanm 0:9b334a45a8ff 2187 */
bogdanm 0:9b334a45a8ff 2188
bogdanm 0:9b334a45a8ff 2189 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
bogdanm 0:9b334a45a8ff 2190 * @brief Time Encoder functions
bogdanm 0:9b334a45a8ff 2191 *
bogdanm 0:9b334a45a8ff 2192 @verbatim
bogdanm 0:9b334a45a8ff 2193 ==============================================================================
bogdanm 0:9b334a45a8ff 2194 ##### Time Encoder functions #####
bogdanm 0:9b334a45a8ff 2195 ==============================================================================
bogdanm 0:9b334a45a8ff 2196 [..]
bogdanm 0:9b334a45a8ff 2197 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 2198 (+) Initialize and configure the TIM Encoder.
bogdanm 0:9b334a45a8ff 2199 (+) De-initialize the TIM Encoder.
bogdanm 0:9b334a45a8ff 2200 (+) Start the Time Encoder.
bogdanm 0:9b334a45a8ff 2201 (+) Stop the Time Encoder.
bogdanm 0:9b334a45a8ff 2202 (+) Start the Time Encoder and enable interrupt.
bogdanm 0:9b334a45a8ff 2203 (+) Stop the Time Encoder and disable interrupt.
bogdanm 0:9b334a45a8ff 2204 (+) Start the Time Encoder and enable DMA transfer.
bogdanm 0:9b334a45a8ff 2205 (+) Stop the Time Encoder and disable DMA transfer.
bogdanm 0:9b334a45a8ff 2206
bogdanm 0:9b334a45a8ff 2207 @endverbatim
bogdanm 0:9b334a45a8ff 2208 * @{
bogdanm 0:9b334a45a8ff 2209 */
bogdanm 0:9b334a45a8ff 2210 /**
bogdanm 0:9b334a45a8ff 2211 * @brief Initializes the TIM Encoder Interface and create the associated handle.
bogdanm 0:9b334a45a8ff 2212 * @param htim : TIM Encoder Interface handle
bogdanm 0:9b334a45a8ff 2213 * @param sConfig : TIM Encoder Interface configuration structure
bogdanm 0:9b334a45a8ff 2214 * @retval HAL status
bogdanm 0:9b334a45a8ff 2215 */
bogdanm 0:9b334a45a8ff 2216 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
bogdanm 0:9b334a45a8ff 2217 {
bogdanm 0:9b334a45a8ff 2218 uint32_t tmpsmcr = 0;
bogdanm 0:9b334a45a8ff 2219 uint32_t tmpccmr1 = 0;
bogdanm 0:9b334a45a8ff 2220 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 2221
bogdanm 0:9b334a45a8ff 2222 /* Check the TIM handle allocation */
bogdanm 0:9b334a45a8ff 2223 if(htim == NULL)
bogdanm 0:9b334a45a8ff 2224 {
bogdanm 0:9b334a45a8ff 2225 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 2226 }
bogdanm 0:9b334a45a8ff 2227
bogdanm 0:9b334a45a8ff 2228 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2229 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2230 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
bogdanm 0:9b334a45a8ff 2231 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
bogdanm 0:9b334a45a8ff 2232 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
bogdanm 0:9b334a45a8ff 2233 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
bogdanm 0:9b334a45a8ff 2234 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
bogdanm 0:9b334a45a8ff 2235 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
bogdanm 0:9b334a45a8ff 2236 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
bogdanm 0:9b334a45a8ff 2237 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
bogdanm 0:9b334a45a8ff 2238 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
bogdanm 0:9b334a45a8ff 2239
bogdanm 0:9b334a45a8ff 2240 if(htim->State == HAL_TIM_STATE_RESET)
bogdanm 0:9b334a45a8ff 2241 {
bogdanm 0:9b334a45a8ff 2242 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 2243 htim->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 2244
bogdanm 0:9b334a45a8ff 2245 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm 0:9b334a45a8ff 2246 HAL_TIM_Encoder_MspInit(htim);
bogdanm 0:9b334a45a8ff 2247 }
bogdanm 0:9b334a45a8ff 2248
bogdanm 0:9b334a45a8ff 2249 /* Set the TIM state */
bogdanm 0:9b334a45a8ff 2250 htim->State= HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 2251
bogdanm 0:9b334a45a8ff 2252 /* Reset the SMS bits */
bogdanm 0:9b334a45a8ff 2253 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm 0:9b334a45a8ff 2254
bogdanm 0:9b334a45a8ff 2255 /* Configure the Time base in the Encoder Mode */
bogdanm 0:9b334a45a8ff 2256 TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm 0:9b334a45a8ff 2257
bogdanm 0:9b334a45a8ff 2258 /* Get the TIMx SMCR register value */
bogdanm 0:9b334a45a8ff 2259 tmpsmcr = htim->Instance->SMCR;
bogdanm 0:9b334a45a8ff 2260
bogdanm 0:9b334a45a8ff 2261 /* Get the TIMx CCMR1 register value */
bogdanm 0:9b334a45a8ff 2262 tmpccmr1 = htim->Instance->CCMR1;
bogdanm 0:9b334a45a8ff 2263
bogdanm 0:9b334a45a8ff 2264 /* Get the TIMx CCER register value */
bogdanm 0:9b334a45a8ff 2265 tmpccer = htim->Instance->CCER;
bogdanm 0:9b334a45a8ff 2266
bogdanm 0:9b334a45a8ff 2267 /* Set the encoder Mode */
bogdanm 0:9b334a45a8ff 2268 tmpsmcr |= sConfig->EncoderMode;
bogdanm 0:9b334a45a8ff 2269
bogdanm 0:9b334a45a8ff 2270 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
bogdanm 0:9b334a45a8ff 2271 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
bogdanm 0:9b334a45a8ff 2272 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
bogdanm 0:9b334a45a8ff 2273
bogdanm 0:9b334a45a8ff 2274 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
bogdanm 0:9b334a45a8ff 2275 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
bogdanm 0:9b334a45a8ff 2276 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
bogdanm 0:9b334a45a8ff 2277 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
bogdanm 0:9b334a45a8ff 2278 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
bogdanm 0:9b334a45a8ff 2279
bogdanm 0:9b334a45a8ff 2280 /* Set the TI1 and the TI2 Polarities */
bogdanm 0:9b334a45a8ff 2281 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
bogdanm 0:9b334a45a8ff 2282 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
bogdanm 0:9b334a45a8ff 2283 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
bogdanm 0:9b334a45a8ff 2284
bogdanm 0:9b334a45a8ff 2285 /* Write to TIMx SMCR */
bogdanm 0:9b334a45a8ff 2286 htim->Instance->SMCR = tmpsmcr;
bogdanm 0:9b334a45a8ff 2287
bogdanm 0:9b334a45a8ff 2288 /* Write to TIMx CCMR1 */
bogdanm 0:9b334a45a8ff 2289 htim->Instance->CCMR1 = tmpccmr1;
bogdanm 0:9b334a45a8ff 2290
bogdanm 0:9b334a45a8ff 2291 /* Write to TIMx CCER */
bogdanm 0:9b334a45a8ff 2292 htim->Instance->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 2293
bogdanm 0:9b334a45a8ff 2294 /* Initialize the TIM state*/
bogdanm 0:9b334a45a8ff 2295 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 2296
bogdanm 0:9b334a45a8ff 2297 return HAL_OK;
bogdanm 0:9b334a45a8ff 2298 }
bogdanm 0:9b334a45a8ff 2299
bogdanm 0:9b334a45a8ff 2300
bogdanm 0:9b334a45a8ff 2301 /**
bogdanm 0:9b334a45a8ff 2302 * @brief DeInitializes the TIM Encoder interface
bogdanm 0:9b334a45a8ff 2303 * @param htim : TIM Encoder handle
bogdanm 0:9b334a45a8ff 2304 * @retval HAL status
bogdanm 0:9b334a45a8ff 2305 */
bogdanm 0:9b334a45a8ff 2306 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 2307 {
bogdanm 0:9b334a45a8ff 2308 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2309 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2310
bogdanm 0:9b334a45a8ff 2311 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 2312
bogdanm 0:9b334a45a8ff 2313 /* Disable the TIM Peripheral Clock */
bogdanm 0:9b334a45a8ff 2314 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 2315
bogdanm 0:9b334a45a8ff 2316 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm 0:9b334a45a8ff 2317 HAL_TIM_Encoder_MspDeInit(htim);
bogdanm 0:9b334a45a8ff 2318
bogdanm 0:9b334a45a8ff 2319 /* Change TIM state */
bogdanm 0:9b334a45a8ff 2320 htim->State = HAL_TIM_STATE_RESET;
bogdanm 0:9b334a45a8ff 2321
bogdanm 0:9b334a45a8ff 2322 /* Release Lock */
bogdanm 0:9b334a45a8ff 2323 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2324
bogdanm 0:9b334a45a8ff 2325 return HAL_OK;
bogdanm 0:9b334a45a8ff 2326 }
bogdanm 0:9b334a45a8ff 2327
bogdanm 0:9b334a45a8ff 2328 /**
bogdanm 0:9b334a45a8ff 2329 * @brief Initializes the TIM Encoder Interface MSP.
bogdanm 0:9b334a45a8ff 2330 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 2331 * @retval None
bogdanm 0:9b334a45a8ff 2332 */
bogdanm 0:9b334a45a8ff 2333 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 2334 {
bogdanm 0:9b334a45a8ff 2335 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 2336 the HAL_TIM_Encoder_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 2337 */
bogdanm 0:9b334a45a8ff 2338 }
bogdanm 0:9b334a45a8ff 2339
bogdanm 0:9b334a45a8ff 2340 /**
bogdanm 0:9b334a45a8ff 2341 * @brief DeInitializes TIM Encoder Interface MSP.
bogdanm 0:9b334a45a8ff 2342 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 2343 * @retval None
bogdanm 0:9b334a45a8ff 2344 */
bogdanm 0:9b334a45a8ff 2345 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 2346 {
bogdanm 0:9b334a45a8ff 2347 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 2348 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 2349 */
bogdanm 0:9b334a45a8ff 2350 }
bogdanm 0:9b334a45a8ff 2351
bogdanm 0:9b334a45a8ff 2352 /**
bogdanm 0:9b334a45a8ff 2353 * @brief Starts the TIM Encoder Interface.
bogdanm 0:9b334a45a8ff 2354 * @param htim : TIM Encoder Interface handle
bogdanm 0:9b334a45a8ff 2355 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 2356 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2357 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 2358 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 2359 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm 0:9b334a45a8ff 2360 * @retval HAL status
bogdanm 0:9b334a45a8ff 2361 */
bogdanm 0:9b334a45a8ff 2362 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 2363 {
bogdanm 0:9b334a45a8ff 2364 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2365 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2366
bogdanm 0:9b334a45a8ff 2367 /* Enable the encoder interface channels */
bogdanm 0:9b334a45a8ff 2368 switch (Channel)
bogdanm 0:9b334a45a8ff 2369 {
bogdanm 0:9b334a45a8ff 2370 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 2371 {
bogdanm 0:9b334a45a8ff 2372 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2373 break;
bogdanm 0:9b334a45a8ff 2374 }
bogdanm 0:9b334a45a8ff 2375 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 2376 {
bogdanm 0:9b334a45a8ff 2377 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2378 break;
bogdanm 0:9b334a45a8ff 2379 }
bogdanm 0:9b334a45a8ff 2380 default :
bogdanm 0:9b334a45a8ff 2381 {
bogdanm 0:9b334a45a8ff 2382 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2383 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2384 break;
bogdanm 0:9b334a45a8ff 2385 }
bogdanm 0:9b334a45a8ff 2386 }
bogdanm 0:9b334a45a8ff 2387 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 2388 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 2389
bogdanm 0:9b334a45a8ff 2390 /* Return function status */
bogdanm 0:9b334a45a8ff 2391 return HAL_OK;
bogdanm 0:9b334a45a8ff 2392 }
bogdanm 0:9b334a45a8ff 2393
bogdanm 0:9b334a45a8ff 2394 /**
bogdanm 0:9b334a45a8ff 2395 * @brief Stops the TIM Encoder Interface.
bogdanm 0:9b334a45a8ff 2396 * @param htim : TIM Encoder Interface handle
bogdanm 0:9b334a45a8ff 2397 * @param Channel : TIM Channels to be disabled
bogdanm 0:9b334a45a8ff 2398 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2399 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 2400 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 2401 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm 0:9b334a45a8ff 2402 * @retval HAL status
bogdanm 0:9b334a45a8ff 2403 */
bogdanm 0:9b334a45a8ff 2404 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 2405 {
bogdanm 0:9b334a45a8ff 2406 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2407 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2408
bogdanm 0:9b334a45a8ff 2409 /* Disable the Input Capture channels 1 and 2
bogdanm 0:9b334a45a8ff 2410 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm 0:9b334a45a8ff 2411 switch (Channel)
bogdanm 0:9b334a45a8ff 2412 {
bogdanm 0:9b334a45a8ff 2413 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 2414 {
bogdanm 0:9b334a45a8ff 2415 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2416 break;
bogdanm 0:9b334a45a8ff 2417 }
bogdanm 0:9b334a45a8ff 2418 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 2419 {
bogdanm 0:9b334a45a8ff 2420 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2421 break;
bogdanm 0:9b334a45a8ff 2422 }
bogdanm 0:9b334a45a8ff 2423 default :
bogdanm 0:9b334a45a8ff 2424 {
bogdanm 0:9b334a45a8ff 2425 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2426 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2427 break;
bogdanm 0:9b334a45a8ff 2428 }
bogdanm 0:9b334a45a8ff 2429 }
bogdanm 0:9b334a45a8ff 2430
bogdanm 0:9b334a45a8ff 2431 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 2432 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 2433
bogdanm 0:9b334a45a8ff 2434 /* Return function status */
bogdanm 0:9b334a45a8ff 2435 return HAL_OK;
bogdanm 0:9b334a45a8ff 2436 }
bogdanm 0:9b334a45a8ff 2437
bogdanm 0:9b334a45a8ff 2438 /**
bogdanm 0:9b334a45a8ff 2439 * @brief Starts the TIM Encoder Interface in interrupt mode.
bogdanm 0:9b334a45a8ff 2440 * @param htim : TIM Encoder Interface handle
bogdanm 0:9b334a45a8ff 2441 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 2442 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2443 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 2444 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 2445 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm 0:9b334a45a8ff 2446 * @retval HAL status
bogdanm 0:9b334a45a8ff 2447 */
bogdanm 0:9b334a45a8ff 2448 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 2449 {
bogdanm 0:9b334a45a8ff 2450 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2451 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2452
bogdanm 0:9b334a45a8ff 2453 /* Enable the encoder interface channels */
bogdanm 0:9b334a45a8ff 2454 /* Enable the capture compare Interrupts 1 and/or 2 */
bogdanm 0:9b334a45a8ff 2455 switch (Channel)
bogdanm 0:9b334a45a8ff 2456 {
bogdanm 0:9b334a45a8ff 2457 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 2458 {
bogdanm 0:9b334a45a8ff 2459 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2460 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 2461 break;
bogdanm 0:9b334a45a8ff 2462 }
bogdanm 0:9b334a45a8ff 2463 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 2464 {
bogdanm 0:9b334a45a8ff 2465 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2466 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 2467 break;
bogdanm 0:9b334a45a8ff 2468 }
bogdanm 0:9b334a45a8ff 2469 default :
bogdanm 0:9b334a45a8ff 2470 {
bogdanm 0:9b334a45a8ff 2471 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2472 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2473 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 2474 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 2475 break;
bogdanm 0:9b334a45a8ff 2476 }
bogdanm 0:9b334a45a8ff 2477 }
bogdanm 0:9b334a45a8ff 2478
bogdanm 0:9b334a45a8ff 2479 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 2480 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 2481
bogdanm 0:9b334a45a8ff 2482 /* Return function status */
bogdanm 0:9b334a45a8ff 2483 return HAL_OK;
bogdanm 0:9b334a45a8ff 2484 }
bogdanm 0:9b334a45a8ff 2485
bogdanm 0:9b334a45a8ff 2486 /**
bogdanm 0:9b334a45a8ff 2487 * @brief Stops the TIM Encoder Interface in interrupt mode.
bogdanm 0:9b334a45a8ff 2488 * @param htim : TIM Encoder Interface handle
bogdanm 0:9b334a45a8ff 2489 * @param Channel : TIM Channels to be disabled
bogdanm 0:9b334a45a8ff 2490 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2491 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 2492 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 2493 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm 0:9b334a45a8ff 2494 * @retval HAL status
bogdanm 0:9b334a45a8ff 2495 */
bogdanm 0:9b334a45a8ff 2496 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 2497 {
bogdanm 0:9b334a45a8ff 2498 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2499 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2500
bogdanm 0:9b334a45a8ff 2501 /* Disable the Input Capture channels 1 and 2
bogdanm 0:9b334a45a8ff 2502 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm 0:9b334a45a8ff 2503 if(Channel == TIM_CHANNEL_1)
bogdanm 0:9b334a45a8ff 2504 {
bogdanm 0:9b334a45a8ff 2505 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2506
bogdanm 0:9b334a45a8ff 2507 /* Disable the capture compare Interrupts 1 */
bogdanm 0:9b334a45a8ff 2508 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 2509 }
bogdanm 0:9b334a45a8ff 2510 else if(Channel == TIM_CHANNEL_2)
bogdanm 0:9b334a45a8ff 2511 {
bogdanm 0:9b334a45a8ff 2512 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2513
bogdanm 0:9b334a45a8ff 2514 /* Disable the capture compare Interrupts 2 */
bogdanm 0:9b334a45a8ff 2515 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 2516 }
bogdanm 0:9b334a45a8ff 2517 else
bogdanm 0:9b334a45a8ff 2518 {
bogdanm 0:9b334a45a8ff 2519 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2520 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2521
bogdanm 0:9b334a45a8ff 2522 /* Disable the capture compare Interrupts 1 and 2 */
bogdanm 0:9b334a45a8ff 2523 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 2524 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 2525 }
bogdanm 0:9b334a45a8ff 2526
bogdanm 0:9b334a45a8ff 2527 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 2528 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 2529
bogdanm 0:9b334a45a8ff 2530 /* Change the htim state */
bogdanm 0:9b334a45a8ff 2531 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 2532
bogdanm 0:9b334a45a8ff 2533 /* Return function status */
bogdanm 0:9b334a45a8ff 2534 return HAL_OK;
bogdanm 0:9b334a45a8ff 2535 }
bogdanm 0:9b334a45a8ff 2536
bogdanm 0:9b334a45a8ff 2537 /**
bogdanm 0:9b334a45a8ff 2538 * @brief Starts the TIM Encoder Interface in DMA mode.
bogdanm 0:9b334a45a8ff 2539 * @param htim : TIM Encoder Interface handle
bogdanm 0:9b334a45a8ff 2540 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 2541 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2542 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 2543 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 2544 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm 0:9b334a45a8ff 2545 * @param pData1 : The destination Buffer address for IC1.
bogdanm 0:9b334a45a8ff 2546 * @param pData2 : The destination Buffer address for IC2.
bogdanm 0:9b334a45a8ff 2547 * @param Length : The length of data to be transferred from TIM peripheral to memory.
bogdanm 0:9b334a45a8ff 2548 * @retval HAL status
bogdanm 0:9b334a45a8ff 2549 */
bogdanm 0:9b334a45a8ff 2550 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
bogdanm 0:9b334a45a8ff 2551 {
bogdanm 0:9b334a45a8ff 2552 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2553 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2554
bogdanm 0:9b334a45a8ff 2555 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 2556 {
bogdanm 0:9b334a45a8ff 2557 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 2558 }
bogdanm 0:9b334a45a8ff 2559 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 2560 {
bogdanm 0:9b334a45a8ff 2561 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
bogdanm 0:9b334a45a8ff 2562 {
bogdanm 0:9b334a45a8ff 2563 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 2564 }
bogdanm 0:9b334a45a8ff 2565 else
bogdanm 0:9b334a45a8ff 2566 {
bogdanm 0:9b334a45a8ff 2567 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 2568 }
bogdanm 0:9b334a45a8ff 2569 }
bogdanm 0:9b334a45a8ff 2570
bogdanm 0:9b334a45a8ff 2571 switch (Channel)
bogdanm 0:9b334a45a8ff 2572 {
bogdanm 0:9b334a45a8ff 2573 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 2574 {
bogdanm 0:9b334a45a8ff 2575 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 2576 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 2577
bogdanm 0:9b334a45a8ff 2578 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 2579 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 2580
bogdanm 0:9b334a45a8ff 2581 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 2582 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
bogdanm 0:9b334a45a8ff 2583
bogdanm 0:9b334a45a8ff 2584 /* Enable the TIM Input Capture DMA request */
bogdanm 0:9b334a45a8ff 2585 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 2586
bogdanm 0:9b334a45a8ff 2587 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 2588 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 2589
bogdanm 0:9b334a45a8ff 2590 /* Enable the Capture compare channel */
bogdanm 0:9b334a45a8ff 2591 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2592 }
bogdanm 0:9b334a45a8ff 2593 break;
bogdanm 0:9b334a45a8ff 2594
bogdanm 0:9b334a45a8ff 2595 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 2596 {
bogdanm 0:9b334a45a8ff 2597 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 2598 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 2599
bogdanm 0:9b334a45a8ff 2600 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 2601 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
bogdanm 0:9b334a45a8ff 2602 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 2603 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm 0:9b334a45a8ff 2604
bogdanm 0:9b334a45a8ff 2605 /* Enable the TIM Input Capture DMA request */
bogdanm 0:9b334a45a8ff 2606 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 2607
bogdanm 0:9b334a45a8ff 2608 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 2609 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 2610
bogdanm 0:9b334a45a8ff 2611 /* Enable the Capture compare channel */
bogdanm 0:9b334a45a8ff 2612 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2613 }
bogdanm 0:9b334a45a8ff 2614 break;
bogdanm 0:9b334a45a8ff 2615
bogdanm 0:9b334a45a8ff 2616 case TIM_CHANNEL_ALL:
bogdanm 0:9b334a45a8ff 2617 {
bogdanm 0:9b334a45a8ff 2618 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 2619 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 2620
bogdanm 0:9b334a45a8ff 2621 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 2622 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 2623
bogdanm 0:9b334a45a8ff 2624 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 2625 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
bogdanm 0:9b334a45a8ff 2626
bogdanm 0:9b334a45a8ff 2627 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 2628 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 2629
bogdanm 0:9b334a45a8ff 2630 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 2631 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 2632
bogdanm 0:9b334a45a8ff 2633 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 2634 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
bogdanm 0:9b334a45a8ff 2635
bogdanm 0:9b334a45a8ff 2636 /* Enable the Peripheral */
bogdanm 0:9b334a45a8ff 2637 __HAL_TIM_ENABLE(htim);
bogdanm 0:9b334a45a8ff 2638
bogdanm 0:9b334a45a8ff 2639 /* Enable the Capture compare channel */
bogdanm 0:9b334a45a8ff 2640 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2641 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
bogdanm 0:9b334a45a8ff 2642
bogdanm 0:9b334a45a8ff 2643 /* Enable the TIM Input Capture DMA request */
bogdanm 0:9b334a45a8ff 2644 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 2645 /* Enable the TIM Input Capture DMA request */
bogdanm 0:9b334a45a8ff 2646 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 2647 }
bogdanm 0:9b334a45a8ff 2648 break;
bogdanm 0:9b334a45a8ff 2649
bogdanm 0:9b334a45a8ff 2650 default:
bogdanm 0:9b334a45a8ff 2651 break;
bogdanm 0:9b334a45a8ff 2652 }
bogdanm 0:9b334a45a8ff 2653 /* Return function status */
bogdanm 0:9b334a45a8ff 2654 return HAL_OK;
bogdanm 0:9b334a45a8ff 2655 }
bogdanm 0:9b334a45a8ff 2656
bogdanm 0:9b334a45a8ff 2657 /**
bogdanm 0:9b334a45a8ff 2658 * @brief Stops the TIM Encoder Interface in DMA mode.
bogdanm 0:9b334a45a8ff 2659 * @param htim : TIM Encoder Interface handle
bogdanm 0:9b334a45a8ff 2660 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 2661 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2662 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 2663 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 2664 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
bogdanm 0:9b334a45a8ff 2665 * @retval HAL status
bogdanm 0:9b334a45a8ff 2666 */
bogdanm 0:9b334a45a8ff 2667 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 2668 {
bogdanm 0:9b334a45a8ff 2669 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2670 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2671
bogdanm 0:9b334a45a8ff 2672 /* Disable the Input Capture channels 1 and 2
bogdanm 0:9b334a45a8ff 2673 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
bogdanm 0:9b334a45a8ff 2674 if(Channel == TIM_CHANNEL_1)
bogdanm 0:9b334a45a8ff 2675 {
bogdanm 0:9b334a45a8ff 2676 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2677
bogdanm 0:9b334a45a8ff 2678 /* Disable the capture compare DMA Request 1 */
bogdanm 0:9b334a45a8ff 2679 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 2680 }
bogdanm 0:9b334a45a8ff 2681 else if(Channel == TIM_CHANNEL_2)
bogdanm 0:9b334a45a8ff 2682 {
bogdanm 0:9b334a45a8ff 2683 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2684
bogdanm 0:9b334a45a8ff 2685 /* Disable the capture compare DMA Request 2 */
bogdanm 0:9b334a45a8ff 2686 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 2687 }
bogdanm 0:9b334a45a8ff 2688 else
bogdanm 0:9b334a45a8ff 2689 {
bogdanm 0:9b334a45a8ff 2690 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2691 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
bogdanm 0:9b334a45a8ff 2692
bogdanm 0:9b334a45a8ff 2693 /* Disable the capture compare DMA Request 1 and 2 */
bogdanm 0:9b334a45a8ff 2694 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm 0:9b334a45a8ff 2695 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm 0:9b334a45a8ff 2696 }
bogdanm 0:9b334a45a8ff 2697
bogdanm 0:9b334a45a8ff 2698 /* Disable the Peripheral */
bogdanm 0:9b334a45a8ff 2699 __HAL_TIM_DISABLE(htim);
bogdanm 0:9b334a45a8ff 2700
bogdanm 0:9b334a45a8ff 2701 /* Change the htim state */
bogdanm 0:9b334a45a8ff 2702 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 2703
bogdanm 0:9b334a45a8ff 2704 /* Return function status */
bogdanm 0:9b334a45a8ff 2705 return HAL_OK;
bogdanm 0:9b334a45a8ff 2706 }
bogdanm 0:9b334a45a8ff 2707
bogdanm 0:9b334a45a8ff 2708 /**
bogdanm 0:9b334a45a8ff 2709 * @}
bogdanm 0:9b334a45a8ff 2710 */
bogdanm 0:9b334a45a8ff 2711 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
bogdanm 0:9b334a45a8ff 2712 * @brief IRQ handler management
bogdanm 0:9b334a45a8ff 2713 *
bogdanm 0:9b334a45a8ff 2714 @verbatim
bogdanm 0:9b334a45a8ff 2715 ==============================================================================
bogdanm 0:9b334a45a8ff 2716 ##### IRQ handler management #####
bogdanm 0:9b334a45a8ff 2717 ==============================================================================
bogdanm 0:9b334a45a8ff 2718 [..]
bogdanm 0:9b334a45a8ff 2719 This section provides Timer IRQ handler function.
bogdanm 0:9b334a45a8ff 2720
bogdanm 0:9b334a45a8ff 2721 @endverbatim
bogdanm 0:9b334a45a8ff 2722 * @{
bogdanm 0:9b334a45a8ff 2723 */
bogdanm 0:9b334a45a8ff 2724 /**
bogdanm 0:9b334a45a8ff 2725 * @brief This function handles TIM interrupts requests.
bogdanm 0:9b334a45a8ff 2726 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 2727 * @retval None
bogdanm 0:9b334a45a8ff 2728 */
bogdanm 0:9b334a45a8ff 2729 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 2730 {
bogdanm 0:9b334a45a8ff 2731 /* Capture compare 1 event */
bogdanm 0:9b334a45a8ff 2732 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
bogdanm 0:9b334a45a8ff 2733 {
bogdanm 0:9b334a45a8ff 2734 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
bogdanm 0:9b334a45a8ff 2735 {
bogdanm 0:9b334a45a8ff 2736 {
bogdanm 0:9b334a45a8ff 2737 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
bogdanm 0:9b334a45a8ff 2738 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm 0:9b334a45a8ff 2739
bogdanm 0:9b334a45a8ff 2740 /* Input capture event */
bogdanm 0:9b334a45a8ff 2741 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
bogdanm 0:9b334a45a8ff 2742 {
bogdanm 0:9b334a45a8ff 2743 HAL_TIM_IC_CaptureCallback(htim);
bogdanm 0:9b334a45a8ff 2744 }
bogdanm 0:9b334a45a8ff 2745 /* Output compare event */
bogdanm 0:9b334a45a8ff 2746 else
bogdanm 0:9b334a45a8ff 2747 {
bogdanm 0:9b334a45a8ff 2748 HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm 0:9b334a45a8ff 2749 HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm 0:9b334a45a8ff 2750 }
bogdanm 0:9b334a45a8ff 2751 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm 0:9b334a45a8ff 2752 }
bogdanm 0:9b334a45a8ff 2753 }
bogdanm 0:9b334a45a8ff 2754 }
bogdanm 0:9b334a45a8ff 2755 /* Capture compare 2 event */
bogdanm 0:9b334a45a8ff 2756 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
bogdanm 0:9b334a45a8ff 2757 {
bogdanm 0:9b334a45a8ff 2758 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
bogdanm 0:9b334a45a8ff 2759 {
bogdanm 0:9b334a45a8ff 2760 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
bogdanm 0:9b334a45a8ff 2761 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm 0:9b334a45a8ff 2762 /* Input capture event */
bogdanm 0:9b334a45a8ff 2763 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
bogdanm 0:9b334a45a8ff 2764 {
bogdanm 0:9b334a45a8ff 2765 HAL_TIM_IC_CaptureCallback(htim);
bogdanm 0:9b334a45a8ff 2766 }
bogdanm 0:9b334a45a8ff 2767 /* Output compare event */
bogdanm 0:9b334a45a8ff 2768 else
bogdanm 0:9b334a45a8ff 2769 {
bogdanm 0:9b334a45a8ff 2770 HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm 0:9b334a45a8ff 2771 HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm 0:9b334a45a8ff 2772 }
bogdanm 0:9b334a45a8ff 2773 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm 0:9b334a45a8ff 2774 }
bogdanm 0:9b334a45a8ff 2775 }
bogdanm 0:9b334a45a8ff 2776 /* Capture compare 3 event */
bogdanm 0:9b334a45a8ff 2777 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
bogdanm 0:9b334a45a8ff 2778 {
bogdanm 0:9b334a45a8ff 2779 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
bogdanm 0:9b334a45a8ff 2780 {
bogdanm 0:9b334a45a8ff 2781 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
bogdanm 0:9b334a45a8ff 2782 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm 0:9b334a45a8ff 2783 /* Input capture event */
bogdanm 0:9b334a45a8ff 2784 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
bogdanm 0:9b334a45a8ff 2785 {
bogdanm 0:9b334a45a8ff 2786 HAL_TIM_IC_CaptureCallback(htim);
bogdanm 0:9b334a45a8ff 2787 }
bogdanm 0:9b334a45a8ff 2788 /* Output compare event */
bogdanm 0:9b334a45a8ff 2789 else
bogdanm 0:9b334a45a8ff 2790 {
bogdanm 0:9b334a45a8ff 2791 HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm 0:9b334a45a8ff 2792 HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm 0:9b334a45a8ff 2793 }
bogdanm 0:9b334a45a8ff 2794 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm 0:9b334a45a8ff 2795 }
bogdanm 0:9b334a45a8ff 2796 }
bogdanm 0:9b334a45a8ff 2797 /* Capture compare 4 event */
bogdanm 0:9b334a45a8ff 2798 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
bogdanm 0:9b334a45a8ff 2799 {
bogdanm 0:9b334a45a8ff 2800 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
bogdanm 0:9b334a45a8ff 2801 {
bogdanm 0:9b334a45a8ff 2802 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
bogdanm 0:9b334a45a8ff 2803 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm 0:9b334a45a8ff 2804 /* Input capture event */
bogdanm 0:9b334a45a8ff 2805 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
bogdanm 0:9b334a45a8ff 2806 {
bogdanm 0:9b334a45a8ff 2807 HAL_TIM_IC_CaptureCallback(htim);
bogdanm 0:9b334a45a8ff 2808 }
bogdanm 0:9b334a45a8ff 2809 /* Output compare event */
bogdanm 0:9b334a45a8ff 2810 else
bogdanm 0:9b334a45a8ff 2811 {
bogdanm 0:9b334a45a8ff 2812 HAL_TIM_OC_DelayElapsedCallback(htim);
bogdanm 0:9b334a45a8ff 2813 HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm 0:9b334a45a8ff 2814 }
bogdanm 0:9b334a45a8ff 2815 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm 0:9b334a45a8ff 2816 }
bogdanm 0:9b334a45a8ff 2817 }
bogdanm 0:9b334a45a8ff 2818 /* TIM Update event */
bogdanm 0:9b334a45a8ff 2819 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
bogdanm 0:9b334a45a8ff 2820 {
bogdanm 0:9b334a45a8ff 2821 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
bogdanm 0:9b334a45a8ff 2822 {
bogdanm 0:9b334a45a8ff 2823 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
bogdanm 0:9b334a45a8ff 2824 HAL_TIM_PeriodElapsedCallback(htim);
bogdanm 0:9b334a45a8ff 2825 }
bogdanm 0:9b334a45a8ff 2826 }
bogdanm 0:9b334a45a8ff 2827 /* TIM Break input event */
bogdanm 0:9b334a45a8ff 2828 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
bogdanm 0:9b334a45a8ff 2829 {
bogdanm 0:9b334a45a8ff 2830 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
bogdanm 0:9b334a45a8ff 2831 {
bogdanm 0:9b334a45a8ff 2832 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
bogdanm 0:9b334a45a8ff 2833 HAL_TIMEx_BreakCallback(htim);
bogdanm 0:9b334a45a8ff 2834 }
bogdanm 0:9b334a45a8ff 2835 }
bogdanm 0:9b334a45a8ff 2836 /* TIM Trigger detection event */
bogdanm 0:9b334a45a8ff 2837 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
bogdanm 0:9b334a45a8ff 2838 {
bogdanm 0:9b334a45a8ff 2839 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
bogdanm 0:9b334a45a8ff 2840 {
bogdanm 0:9b334a45a8ff 2841 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
bogdanm 0:9b334a45a8ff 2842 HAL_TIM_TriggerCallback(htim);
bogdanm 0:9b334a45a8ff 2843 }
bogdanm 0:9b334a45a8ff 2844 }
bogdanm 0:9b334a45a8ff 2845 /* TIM commutation event */
bogdanm 0:9b334a45a8ff 2846 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
bogdanm 0:9b334a45a8ff 2847 {
bogdanm 0:9b334a45a8ff 2848 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
bogdanm 0:9b334a45a8ff 2849 {
bogdanm 0:9b334a45a8ff 2850 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
bogdanm 0:9b334a45a8ff 2851 HAL_TIMEx_CommutationCallback(htim);
bogdanm 0:9b334a45a8ff 2852 }
bogdanm 0:9b334a45a8ff 2853 }
bogdanm 0:9b334a45a8ff 2854 }
bogdanm 0:9b334a45a8ff 2855
bogdanm 0:9b334a45a8ff 2856 /**
bogdanm 0:9b334a45a8ff 2857 * @}
bogdanm 0:9b334a45a8ff 2858 */
bogdanm 0:9b334a45a8ff 2859
bogdanm 0:9b334a45a8ff 2860 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
bogdanm 0:9b334a45a8ff 2861 * @brief Peripheral Control functions
bogdanm 0:9b334a45a8ff 2862 *
bogdanm 0:9b334a45a8ff 2863 @verbatim
bogdanm 0:9b334a45a8ff 2864 ==============================================================================
bogdanm 0:9b334a45a8ff 2865 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 2866 ==============================================================================
bogdanm 0:9b334a45a8ff 2867 [..]
bogdanm 0:9b334a45a8ff 2868 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 2869 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
bogdanm 0:9b334a45a8ff 2870 (+) Configure External Clock source.
bogdanm 0:9b334a45a8ff 2871 (+) Configure Complementary channels, break features and dead time.
bogdanm 0:9b334a45a8ff 2872 (+) Configure Master and the Slave synchronization.
bogdanm 0:9b334a45a8ff 2873 (+) Configure the DMA Burst Mode.
bogdanm 0:9b334a45a8ff 2874
bogdanm 0:9b334a45a8ff 2875 @endverbatim
bogdanm 0:9b334a45a8ff 2876 * @{
bogdanm 0:9b334a45a8ff 2877 */
bogdanm 0:9b334a45a8ff 2878
bogdanm 0:9b334a45a8ff 2879 /**
bogdanm 0:9b334a45a8ff 2880 * @brief Initializes the TIM Output Compare Channels according to the specified
bogdanm 0:9b334a45a8ff 2881 * parameters in the TIM_OC_InitTypeDef.
bogdanm 0:9b334a45a8ff 2882 * @param htim : TIM Output Compare handle
bogdanm 0:9b334a45a8ff 2883 * @param sConfig : TIM Output Compare configuration structure
bogdanm 0:9b334a45a8ff 2884 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 2885 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2886 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 2887 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 2888 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 2889 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 2890 * @retval HAL status
bogdanm 0:9b334a45a8ff 2891 */
bogdanm 0:9b334a45a8ff 2892 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
bogdanm 0:9b334a45a8ff 2893 {
bogdanm 0:9b334a45a8ff 2894 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2895 assert_param(IS_TIM_CHANNELS(Channel));
bogdanm 0:9b334a45a8ff 2896 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
bogdanm 0:9b334a45a8ff 2897 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm 0:9b334a45a8ff 2898 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
bogdanm 0:9b334a45a8ff 2899 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
bogdanm 0:9b334a45a8ff 2900 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
bogdanm 0:9b334a45a8ff 2901
bogdanm 0:9b334a45a8ff 2902 /* Check input state */
bogdanm 0:9b334a45a8ff 2903 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 2904
bogdanm 0:9b334a45a8ff 2905 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 2906
bogdanm 0:9b334a45a8ff 2907 switch (Channel)
bogdanm 0:9b334a45a8ff 2908 {
bogdanm 0:9b334a45a8ff 2909 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 2910 {
bogdanm 0:9b334a45a8ff 2911 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2912 /* Configure the TIM Channel 1 in Output Compare */
bogdanm 0:9b334a45a8ff 2913 TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 2914 }
bogdanm 0:9b334a45a8ff 2915 break;
bogdanm 0:9b334a45a8ff 2916
bogdanm 0:9b334a45a8ff 2917 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 2918 {
bogdanm 0:9b334a45a8ff 2919 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2920 /* Configure the TIM Channel 2 in Output Compare */
bogdanm 0:9b334a45a8ff 2921 TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 2922 }
bogdanm 0:9b334a45a8ff 2923 break;
bogdanm 0:9b334a45a8ff 2924
bogdanm 0:9b334a45a8ff 2925 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 2926 {
bogdanm 0:9b334a45a8ff 2927 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2928 /* Configure the TIM Channel 3 in Output Compare */
bogdanm 0:9b334a45a8ff 2929 TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 2930 }
bogdanm 0:9b334a45a8ff 2931 break;
bogdanm 0:9b334a45a8ff 2932
bogdanm 0:9b334a45a8ff 2933 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 2934 {
bogdanm 0:9b334a45a8ff 2935 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2936 /* Configure the TIM Channel 4 in Output Compare */
bogdanm 0:9b334a45a8ff 2937 TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 2938 }
bogdanm 0:9b334a45a8ff 2939 break;
bogdanm 0:9b334a45a8ff 2940
bogdanm 0:9b334a45a8ff 2941 default:
bogdanm 0:9b334a45a8ff 2942 break;
bogdanm 0:9b334a45a8ff 2943 }
bogdanm 0:9b334a45a8ff 2944 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 2945
bogdanm 0:9b334a45a8ff 2946 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 2947
bogdanm 0:9b334a45a8ff 2948 return HAL_OK;
bogdanm 0:9b334a45a8ff 2949 }
bogdanm 0:9b334a45a8ff 2950
bogdanm 0:9b334a45a8ff 2951 /**
bogdanm 0:9b334a45a8ff 2952 * @brief Initializes the TIM Input Capture Channels according to the specified
bogdanm 0:9b334a45a8ff 2953 * parameters in the TIM_IC_InitTypeDef.
bogdanm 0:9b334a45a8ff 2954 * @param htim : TIM IC handle
bogdanm 0:9b334a45a8ff 2955 * @param sConfig : TIM Input Capture configuration structure
bogdanm 0:9b334a45a8ff 2956 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 2957 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2958 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 2959 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 2960 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 2961 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 2962 * @retval HAL status
bogdanm 0:9b334a45a8ff 2963 */
bogdanm 0:9b334a45a8ff 2964 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
bogdanm 0:9b334a45a8ff 2965 {
bogdanm 0:9b334a45a8ff 2966 /* Check the parameters */
bogdanm 0:9b334a45a8ff 2967 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2968 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
bogdanm 0:9b334a45a8ff 2969 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
bogdanm 0:9b334a45a8ff 2970 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
bogdanm 0:9b334a45a8ff 2971 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
bogdanm 0:9b334a45a8ff 2972
bogdanm 0:9b334a45a8ff 2973 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 2974
bogdanm 0:9b334a45a8ff 2975 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 2976
bogdanm 0:9b334a45a8ff 2977 if (Channel == TIM_CHANNEL_1)
bogdanm 0:9b334a45a8ff 2978 {
bogdanm 0:9b334a45a8ff 2979 /* TI1 Configuration */
bogdanm 0:9b334a45a8ff 2980 TIM_TI1_SetConfig(htim->Instance,
bogdanm 0:9b334a45a8ff 2981 sConfig->ICPolarity,
bogdanm 0:9b334a45a8ff 2982 sConfig->ICSelection,
bogdanm 0:9b334a45a8ff 2983 sConfig->ICFilter);
bogdanm 0:9b334a45a8ff 2984
bogdanm 0:9b334a45a8ff 2985 /* Reset the IC1PSC Bits */
bogdanm 0:9b334a45a8ff 2986 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm 0:9b334a45a8ff 2987
bogdanm 0:9b334a45a8ff 2988 /* Set the IC1PSC value */
bogdanm 0:9b334a45a8ff 2989 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
bogdanm 0:9b334a45a8ff 2990 }
bogdanm 0:9b334a45a8ff 2991 else if (Channel == TIM_CHANNEL_2)
bogdanm 0:9b334a45a8ff 2992 {
bogdanm 0:9b334a45a8ff 2993 /* TI2 Configuration */
bogdanm 0:9b334a45a8ff 2994 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 2995
bogdanm 0:9b334a45a8ff 2996 TIM_TI2_SetConfig(htim->Instance,
bogdanm 0:9b334a45a8ff 2997 sConfig->ICPolarity,
bogdanm 0:9b334a45a8ff 2998 sConfig->ICSelection,
bogdanm 0:9b334a45a8ff 2999 sConfig->ICFilter);
bogdanm 0:9b334a45a8ff 3000
bogdanm 0:9b334a45a8ff 3001 /* Reset the IC2PSC Bits */
bogdanm 0:9b334a45a8ff 3002 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm 0:9b334a45a8ff 3003
bogdanm 0:9b334a45a8ff 3004 /* Set the IC2PSC value */
bogdanm 0:9b334a45a8ff 3005 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
bogdanm 0:9b334a45a8ff 3006 }
bogdanm 0:9b334a45a8ff 3007 else if (Channel == TIM_CHANNEL_3)
bogdanm 0:9b334a45a8ff 3008 {
bogdanm 0:9b334a45a8ff 3009 /* TI3 Configuration */
bogdanm 0:9b334a45a8ff 3010 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3011
bogdanm 0:9b334a45a8ff 3012 TIM_TI3_SetConfig(htim->Instance,
bogdanm 0:9b334a45a8ff 3013 sConfig->ICPolarity,
bogdanm 0:9b334a45a8ff 3014 sConfig->ICSelection,
bogdanm 0:9b334a45a8ff 3015 sConfig->ICFilter);
bogdanm 0:9b334a45a8ff 3016
bogdanm 0:9b334a45a8ff 3017 /* Reset the IC3PSC Bits */
bogdanm 0:9b334a45a8ff 3018 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
bogdanm 0:9b334a45a8ff 3019
bogdanm 0:9b334a45a8ff 3020 /* Set the IC3PSC value */
bogdanm 0:9b334a45a8ff 3021 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
bogdanm 0:9b334a45a8ff 3022 }
bogdanm 0:9b334a45a8ff 3023 else
bogdanm 0:9b334a45a8ff 3024 {
bogdanm 0:9b334a45a8ff 3025 /* TI4 Configuration */
bogdanm 0:9b334a45a8ff 3026 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3027
bogdanm 0:9b334a45a8ff 3028 TIM_TI4_SetConfig(htim->Instance,
bogdanm 0:9b334a45a8ff 3029 sConfig->ICPolarity,
bogdanm 0:9b334a45a8ff 3030 sConfig->ICSelection,
bogdanm 0:9b334a45a8ff 3031 sConfig->ICFilter);
bogdanm 0:9b334a45a8ff 3032
bogdanm 0:9b334a45a8ff 3033 /* Reset the IC4PSC Bits */
bogdanm 0:9b334a45a8ff 3034 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
bogdanm 0:9b334a45a8ff 3035
bogdanm 0:9b334a45a8ff 3036 /* Set the IC4PSC value */
bogdanm 0:9b334a45a8ff 3037 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
bogdanm 0:9b334a45a8ff 3038 }
bogdanm 0:9b334a45a8ff 3039
bogdanm 0:9b334a45a8ff 3040 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 3041
bogdanm 0:9b334a45a8ff 3042 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 3043
bogdanm 0:9b334a45a8ff 3044 return HAL_OK;
bogdanm 0:9b334a45a8ff 3045 }
bogdanm 0:9b334a45a8ff 3046
bogdanm 0:9b334a45a8ff 3047 /**
bogdanm 0:9b334a45a8ff 3048 * @brief Initializes the TIM PWM channels according to the specified
bogdanm 0:9b334a45a8ff 3049 * parameters in the TIM_OC_InitTypeDef.
bogdanm 0:9b334a45a8ff 3050 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 3051 * @param sConfig : TIM PWM configuration structure
bogdanm 0:9b334a45a8ff 3052 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 3053 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3054 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 3055 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 3056 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 3057 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 3058 * @retval HAL status
bogdanm 0:9b334a45a8ff 3059 */
bogdanm 0:9b334a45a8ff 3060 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
bogdanm 0:9b334a45a8ff 3061 {
bogdanm 0:9b334a45a8ff 3062 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 3063
bogdanm 0:9b334a45a8ff 3064 /* Check the parameters */
bogdanm 0:9b334a45a8ff 3065 assert_param(IS_TIM_CHANNELS(Channel));
bogdanm 0:9b334a45a8ff 3066 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
bogdanm 0:9b334a45a8ff 3067 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
bogdanm 0:9b334a45a8ff 3068 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
bogdanm 0:9b334a45a8ff 3069 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
bogdanm 0:9b334a45a8ff 3070 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
bogdanm 0:9b334a45a8ff 3071 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
bogdanm 0:9b334a45a8ff 3072
bogdanm 0:9b334a45a8ff 3073 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 3074
bogdanm 0:9b334a45a8ff 3075 switch (Channel)
bogdanm 0:9b334a45a8ff 3076 {
bogdanm 0:9b334a45a8ff 3077 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 3078 {
bogdanm 0:9b334a45a8ff 3079 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3080 /* Configure the Channel 1 in PWM mode */
bogdanm 0:9b334a45a8ff 3081 TIM_OC1_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 3082
bogdanm 0:9b334a45a8ff 3083 /* Set the Preload enable bit for channel1 */
bogdanm 0:9b334a45a8ff 3084 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
bogdanm 0:9b334a45a8ff 3085
bogdanm 0:9b334a45a8ff 3086 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 3087 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
bogdanm 0:9b334a45a8ff 3088 htim->Instance->CCMR1 |= sConfig->OCFastMode;
bogdanm 0:9b334a45a8ff 3089 }
bogdanm 0:9b334a45a8ff 3090 break;
bogdanm 0:9b334a45a8ff 3091
bogdanm 0:9b334a45a8ff 3092 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 3093 {
bogdanm 0:9b334a45a8ff 3094 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3095 /* Configure the Channel 2 in PWM mode */
bogdanm 0:9b334a45a8ff 3096 TIM_OC2_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 3097
bogdanm 0:9b334a45a8ff 3098 /* Set the Preload enable bit for channel2 */
bogdanm 0:9b334a45a8ff 3099 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
bogdanm 0:9b334a45a8ff 3100
bogdanm 0:9b334a45a8ff 3101 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 3102 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
bogdanm 0:9b334a45a8ff 3103 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
bogdanm 0:9b334a45a8ff 3104 }
bogdanm 0:9b334a45a8ff 3105 break;
bogdanm 0:9b334a45a8ff 3106
bogdanm 0:9b334a45a8ff 3107 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 3108 {
bogdanm 0:9b334a45a8ff 3109 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3110 /* Configure the Channel 3 in PWM mode */
bogdanm 0:9b334a45a8ff 3111 TIM_OC3_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 3112
bogdanm 0:9b334a45a8ff 3113 /* Set the Preload enable bit for channel3 */
bogdanm 0:9b334a45a8ff 3114 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
bogdanm 0:9b334a45a8ff 3115
bogdanm 0:9b334a45a8ff 3116 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 3117 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
bogdanm 0:9b334a45a8ff 3118 htim->Instance->CCMR2 |= sConfig->OCFastMode;
bogdanm 0:9b334a45a8ff 3119 }
bogdanm 0:9b334a45a8ff 3120 break;
bogdanm 0:9b334a45a8ff 3121
bogdanm 0:9b334a45a8ff 3122 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 3123 {
bogdanm 0:9b334a45a8ff 3124 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3125 /* Configure the Channel 4 in PWM mode */
bogdanm 0:9b334a45a8ff 3126 TIM_OC4_SetConfig(htim->Instance, sConfig);
bogdanm 0:9b334a45a8ff 3127
bogdanm 0:9b334a45a8ff 3128 /* Set the Preload enable bit for channel4 */
bogdanm 0:9b334a45a8ff 3129 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
bogdanm 0:9b334a45a8ff 3130
bogdanm 0:9b334a45a8ff 3131 /* Configure the Output Fast mode */
bogdanm 0:9b334a45a8ff 3132 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
bogdanm 0:9b334a45a8ff 3133 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
bogdanm 0:9b334a45a8ff 3134 }
bogdanm 0:9b334a45a8ff 3135 break;
bogdanm 0:9b334a45a8ff 3136
bogdanm 0:9b334a45a8ff 3137 default:
bogdanm 0:9b334a45a8ff 3138 break;
bogdanm 0:9b334a45a8ff 3139 }
bogdanm 0:9b334a45a8ff 3140
bogdanm 0:9b334a45a8ff 3141 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 3142
bogdanm 0:9b334a45a8ff 3143 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 3144
bogdanm 0:9b334a45a8ff 3145 return HAL_OK;
bogdanm 0:9b334a45a8ff 3146 }
bogdanm 0:9b334a45a8ff 3147
bogdanm 0:9b334a45a8ff 3148 /**
bogdanm 0:9b334a45a8ff 3149 * @brief Initializes the TIM One Pulse Channels according to the specified
bogdanm 0:9b334a45a8ff 3150 * parameters in the TIM_OnePulse_InitTypeDef.
bogdanm 0:9b334a45a8ff 3151 * @param htim : TIM One Pulse handle
bogdanm 0:9b334a45a8ff 3152 * @param sConfig : TIM One Pulse configuration structure
bogdanm 0:9b334a45a8ff 3153 * @param OutputChannel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 3154 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3155 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 3156 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 3157 * @param InputChannel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 3158 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3159 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 3160 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 3161 * @retval HAL status
bogdanm 0:9b334a45a8ff 3162 */
bogdanm 0:9b334a45a8ff 3163 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
bogdanm 0:9b334a45a8ff 3164 {
bogdanm 0:9b334a45a8ff 3165 TIM_OC_InitTypeDef temp1;
bogdanm 0:9b334a45a8ff 3166
bogdanm 0:9b334a45a8ff 3167 /* Check the parameters */
bogdanm 0:9b334a45a8ff 3168 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
bogdanm 0:9b334a45a8ff 3169 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
bogdanm 0:9b334a45a8ff 3170
bogdanm 0:9b334a45a8ff 3171 if(OutputChannel != InputChannel)
bogdanm 0:9b334a45a8ff 3172 {
bogdanm 0:9b334a45a8ff 3173 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 3174
bogdanm 0:9b334a45a8ff 3175 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 3176
bogdanm 0:9b334a45a8ff 3177 /* Extract the Ouput compare configuration from sConfig structure */
bogdanm 0:9b334a45a8ff 3178 temp1.OCMode = sConfig->OCMode;
bogdanm 0:9b334a45a8ff 3179 temp1.Pulse = sConfig->Pulse;
bogdanm 0:9b334a45a8ff 3180 temp1.OCPolarity = sConfig->OCPolarity;
bogdanm 0:9b334a45a8ff 3181 temp1.OCNPolarity = sConfig->OCNPolarity;
bogdanm 0:9b334a45a8ff 3182 temp1.OCIdleState = sConfig->OCIdleState;
bogdanm 0:9b334a45a8ff 3183 temp1.OCNIdleState = sConfig->OCNIdleState;
bogdanm 0:9b334a45a8ff 3184
bogdanm 0:9b334a45a8ff 3185 switch (OutputChannel)
bogdanm 0:9b334a45a8ff 3186 {
bogdanm 0:9b334a45a8ff 3187 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 3188 {
bogdanm 0:9b334a45a8ff 3189 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3190
bogdanm 0:9b334a45a8ff 3191 TIM_OC1_SetConfig(htim->Instance, &temp1);
bogdanm 0:9b334a45a8ff 3192 }
bogdanm 0:9b334a45a8ff 3193 break;
bogdanm 0:9b334a45a8ff 3194 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 3195 {
bogdanm 0:9b334a45a8ff 3196 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3197
bogdanm 0:9b334a45a8ff 3198 TIM_OC2_SetConfig(htim->Instance, &temp1);
bogdanm 0:9b334a45a8ff 3199 }
bogdanm 0:9b334a45a8ff 3200 break;
bogdanm 0:9b334a45a8ff 3201 default:
bogdanm 0:9b334a45a8ff 3202 break;
bogdanm 0:9b334a45a8ff 3203 }
bogdanm 0:9b334a45a8ff 3204 switch (InputChannel)
bogdanm 0:9b334a45a8ff 3205 {
bogdanm 0:9b334a45a8ff 3206 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 3207 {
bogdanm 0:9b334a45a8ff 3208 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3209
bogdanm 0:9b334a45a8ff 3210 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm 0:9b334a45a8ff 3211 sConfig->ICSelection, sConfig->ICFilter);
bogdanm 0:9b334a45a8ff 3212
bogdanm 0:9b334a45a8ff 3213 /* Reset the IC1PSC Bits */
bogdanm 0:9b334a45a8ff 3214 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm 0:9b334a45a8ff 3215
bogdanm 0:9b334a45a8ff 3216 /* Select the Trigger source */
bogdanm 0:9b334a45a8ff 3217 htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm 0:9b334a45a8ff 3218 htim->Instance->SMCR |= TIM_TS_TI1FP1;
bogdanm 0:9b334a45a8ff 3219
bogdanm 0:9b334a45a8ff 3220 /* Select the Slave Mode */
bogdanm 0:9b334a45a8ff 3221 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm 0:9b334a45a8ff 3222 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
bogdanm 0:9b334a45a8ff 3223 }
bogdanm 0:9b334a45a8ff 3224 break;
bogdanm 0:9b334a45a8ff 3225 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 3226 {
bogdanm 0:9b334a45a8ff 3227 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3228
bogdanm 0:9b334a45a8ff 3229 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
bogdanm 0:9b334a45a8ff 3230 sConfig->ICSelection, sConfig->ICFilter);
bogdanm 0:9b334a45a8ff 3231
bogdanm 0:9b334a45a8ff 3232 /* Reset the IC2PSC Bits */
bogdanm 0:9b334a45a8ff 3233 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
bogdanm 0:9b334a45a8ff 3234
bogdanm 0:9b334a45a8ff 3235 /* Select the Trigger source */
bogdanm 0:9b334a45a8ff 3236 htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm 0:9b334a45a8ff 3237 htim->Instance->SMCR |= TIM_TS_TI2FP2;
bogdanm 0:9b334a45a8ff 3238
bogdanm 0:9b334a45a8ff 3239 /* Select the Slave Mode */
bogdanm 0:9b334a45a8ff 3240 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm 0:9b334a45a8ff 3241 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
bogdanm 0:9b334a45a8ff 3242 }
bogdanm 0:9b334a45a8ff 3243 break;
bogdanm 0:9b334a45a8ff 3244
bogdanm 0:9b334a45a8ff 3245 default:
bogdanm 0:9b334a45a8ff 3246 break;
bogdanm 0:9b334a45a8ff 3247 }
bogdanm 0:9b334a45a8ff 3248
bogdanm 0:9b334a45a8ff 3249 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 3250
bogdanm 0:9b334a45a8ff 3251 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 3252
bogdanm 0:9b334a45a8ff 3253 return HAL_OK;
bogdanm 0:9b334a45a8ff 3254 }
bogdanm 0:9b334a45a8ff 3255 else
bogdanm 0:9b334a45a8ff 3256 {
bogdanm 0:9b334a45a8ff 3257 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 3258 }
bogdanm 0:9b334a45a8ff 3259 }
bogdanm 0:9b334a45a8ff 3260
bogdanm 0:9b334a45a8ff 3261 /**
bogdanm 0:9b334a45a8ff 3262 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
bogdanm 0:9b334a45a8ff 3263 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 3264 * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
bogdanm 0:9b334a45a8ff 3265 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3266 * @arg TIM_DMABASE_CR1
bogdanm 0:9b334a45a8ff 3267 * @arg TIM_DMABASE_CR2
bogdanm 0:9b334a45a8ff 3268 * @arg TIM_DMABASE_SMCR
bogdanm 0:9b334a45a8ff 3269 * @arg TIM_DMABASE_DIER
bogdanm 0:9b334a45a8ff 3270 * @arg TIM_DMABASE_SR
bogdanm 0:9b334a45a8ff 3271 * @arg TIM_DMABASE_EGR
bogdanm 0:9b334a45a8ff 3272 * @arg TIM_DMABASE_CCMR1
bogdanm 0:9b334a45a8ff 3273 * @arg TIM_DMABASE_CCMR2
bogdanm 0:9b334a45a8ff 3274 * @arg TIM_DMABASE_CCER
bogdanm 0:9b334a45a8ff 3275 * @arg TIM_DMABASE_CNT
bogdanm 0:9b334a45a8ff 3276 * @arg TIM_DMABASE_PSC
bogdanm 0:9b334a45a8ff 3277 * @arg TIM_DMABASE_ARR
bogdanm 0:9b334a45a8ff 3278 * @arg TIM_DMABASE_RCR
bogdanm 0:9b334a45a8ff 3279 * @arg TIM_DMABASE_CCR1
bogdanm 0:9b334a45a8ff 3280 * @arg TIM_DMABASE_CCR2
bogdanm 0:9b334a45a8ff 3281 * @arg TIM_DMABASE_CCR3
bogdanm 0:9b334a45a8ff 3282 * @arg TIM_DMABASE_CCR4
bogdanm 0:9b334a45a8ff 3283 * @arg TIM_DMABASE_BDTR
bogdanm 0:9b334a45a8ff 3284 * @arg TIM_DMABASE_DCR
bogdanm 0:9b334a45a8ff 3285 * @param BurstRequestSrc : TIM DMA Request sources
bogdanm 0:9b334a45a8ff 3286 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3287 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm 0:9b334a45a8ff 3288 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm 0:9b334a45a8ff 3289 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm 0:9b334a45a8ff 3290 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm 0:9b334a45a8ff 3291 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm 0:9b334a45a8ff 3292 * @arg TIM_DMA_COM: TIM Commutation DMA source
bogdanm 0:9b334a45a8ff 3293 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm 0:9b334a45a8ff 3294 * @param BurstBuffer : The Buffer address.
bogdanm 0:9b334a45a8ff 3295 * @param BurstLength : DMA Burst length. This parameter can be one value
bogdanm 0:9b334a45a8ff 3296 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
bogdanm 0:9b334a45a8ff 3297 * @retval HAL status
bogdanm 0:9b334a45a8ff 3298 */
bogdanm 0:9b334a45a8ff 3299 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm 0:9b334a45a8ff 3300 uint32_t* BurstBuffer, uint32_t BurstLength)
bogdanm 0:9b334a45a8ff 3301 {
bogdanm 0:9b334a45a8ff 3302 /* Check the parameters */
bogdanm 0:9b334a45a8ff 3303 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3304 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm 0:9b334a45a8ff 3305 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm 0:9b334a45a8ff 3306 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm 0:9b334a45a8ff 3307
bogdanm 0:9b334a45a8ff 3308 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 3309 {
bogdanm 0:9b334a45a8ff 3310 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 3311 }
bogdanm 0:9b334a45a8ff 3312 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 3313 {
bogdanm 0:9b334a45a8ff 3314 if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm 0:9b334a45a8ff 3315 {
bogdanm 0:9b334a45a8ff 3316 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 3317 }
bogdanm 0:9b334a45a8ff 3318 else
bogdanm 0:9b334a45a8ff 3319 {
bogdanm 0:9b334a45a8ff 3320 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 3321 }
bogdanm 0:9b334a45a8ff 3322 }
bogdanm 0:9b334a45a8ff 3323 switch(BurstRequestSrc)
bogdanm 0:9b334a45a8ff 3324 {
bogdanm 0:9b334a45a8ff 3325 case TIM_DMA_UPDATE:
bogdanm 0:9b334a45a8ff 3326 {
bogdanm 0:9b334a45a8ff 3327 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3328 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm 0:9b334a45a8ff 3329
bogdanm 0:9b334a45a8ff 3330 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3331 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3332
bogdanm 0:9b334a45a8ff 3333 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3334 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3335 }
bogdanm 0:9b334a45a8ff 3336 break;
bogdanm 0:9b334a45a8ff 3337 case TIM_DMA_CC1:
bogdanm 0:9b334a45a8ff 3338 {
bogdanm 0:9b334a45a8ff 3339 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3340 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 3341
bogdanm 0:9b334a45a8ff 3342 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3343 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3344
bogdanm 0:9b334a45a8ff 3345 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3346 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3347 }
bogdanm 0:9b334a45a8ff 3348 break;
bogdanm 0:9b334a45a8ff 3349 case TIM_DMA_CC2:
bogdanm 0:9b334a45a8ff 3350 {
bogdanm 0:9b334a45a8ff 3351 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3352 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 3353
bogdanm 0:9b334a45a8ff 3354 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3355 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3356
bogdanm 0:9b334a45a8ff 3357 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3358 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3359 }
bogdanm 0:9b334a45a8ff 3360 break;
bogdanm 0:9b334a45a8ff 3361 case TIM_DMA_CC3:
bogdanm 0:9b334a45a8ff 3362 {
bogdanm 0:9b334a45a8ff 3363 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3364 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 3365
bogdanm 0:9b334a45a8ff 3366 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3367 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3368
bogdanm 0:9b334a45a8ff 3369 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3370 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3371 }
bogdanm 0:9b334a45a8ff 3372 break;
bogdanm 0:9b334a45a8ff 3373 case TIM_DMA_CC4:
bogdanm 0:9b334a45a8ff 3374 {
bogdanm 0:9b334a45a8ff 3375 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3376 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm 0:9b334a45a8ff 3377
bogdanm 0:9b334a45a8ff 3378 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3379 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3380
bogdanm 0:9b334a45a8ff 3381 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3382 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3383 }
bogdanm 0:9b334a45a8ff 3384 break;
bogdanm 0:9b334a45a8ff 3385 case TIM_DMA_COM:
bogdanm 0:9b334a45a8ff 3386 {
bogdanm 0:9b334a45a8ff 3387 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3388 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
bogdanm 0:9b334a45a8ff 3389
bogdanm 0:9b334a45a8ff 3390 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3391 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3392
bogdanm 0:9b334a45a8ff 3393 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3394 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3395 }
bogdanm 0:9b334a45a8ff 3396 break;
bogdanm 0:9b334a45a8ff 3397 case TIM_DMA_TRIGGER:
bogdanm 0:9b334a45a8ff 3398 {
bogdanm 0:9b334a45a8ff 3399 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3400 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm 0:9b334a45a8ff 3401
bogdanm 0:9b334a45a8ff 3402 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3403 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3404
bogdanm 0:9b334a45a8ff 3405 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3406 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3407 }
bogdanm 0:9b334a45a8ff 3408 break;
bogdanm 0:9b334a45a8ff 3409 default:
bogdanm 0:9b334a45a8ff 3410 break;
bogdanm 0:9b334a45a8ff 3411 }
bogdanm 0:9b334a45a8ff 3412 /* configure the DMA Burst Mode */
bogdanm 0:9b334a45a8ff 3413 htim->Instance->DCR = BurstBaseAddress | BurstLength;
bogdanm 0:9b334a45a8ff 3414
bogdanm 0:9b334a45a8ff 3415 /* Enable the TIM DMA Request */
bogdanm 0:9b334a45a8ff 3416 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm 0:9b334a45a8ff 3417
bogdanm 0:9b334a45a8ff 3418 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 3419
bogdanm 0:9b334a45a8ff 3420 /* Return function status */
bogdanm 0:9b334a45a8ff 3421 return HAL_OK;
bogdanm 0:9b334a45a8ff 3422 }
bogdanm 0:9b334a45a8ff 3423
bogdanm 0:9b334a45a8ff 3424 /**
bogdanm 0:9b334a45a8ff 3425 * @brief Stops the TIM DMA Burst mode
bogdanm 0:9b334a45a8ff 3426 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 3427 * @param BurstRequestSrc : TIM DMA Request sources to disable
bogdanm 0:9b334a45a8ff 3428 * @retval HAL status
bogdanm 0:9b334a45a8ff 3429 */
bogdanm 0:9b334a45a8ff 3430 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm 0:9b334a45a8ff 3431 {
bogdanm 0:9b334a45a8ff 3432 /* Check the parameters */
bogdanm 0:9b334a45a8ff 3433 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm 0:9b334a45a8ff 3434
bogdanm 0:9b334a45a8ff 3435 /* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm 0:9b334a45a8ff 3436 switch(BurstRequestSrc)
bogdanm 0:9b334a45a8ff 3437 {
bogdanm 0:9b334a45a8ff 3438 case TIM_DMA_UPDATE:
bogdanm 0:9b334a45a8ff 3439 {
bogdanm 0:9b334a45a8ff 3440 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm 0:9b334a45a8ff 3441 }
bogdanm 0:9b334a45a8ff 3442 break;
bogdanm 0:9b334a45a8ff 3443 case TIM_DMA_CC1:
bogdanm 0:9b334a45a8ff 3444 {
bogdanm 0:9b334a45a8ff 3445 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm 0:9b334a45a8ff 3446 }
bogdanm 0:9b334a45a8ff 3447 break;
bogdanm 0:9b334a45a8ff 3448 case TIM_DMA_CC2:
bogdanm 0:9b334a45a8ff 3449 {
bogdanm 0:9b334a45a8ff 3450 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm 0:9b334a45a8ff 3451 }
bogdanm 0:9b334a45a8ff 3452 break;
bogdanm 0:9b334a45a8ff 3453 case TIM_DMA_CC3:
bogdanm 0:9b334a45a8ff 3454 {
bogdanm 0:9b334a45a8ff 3455 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm 0:9b334a45a8ff 3456 }
bogdanm 0:9b334a45a8ff 3457 break;
bogdanm 0:9b334a45a8ff 3458 case TIM_DMA_CC4:
bogdanm 0:9b334a45a8ff 3459 {
bogdanm 0:9b334a45a8ff 3460 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm 0:9b334a45a8ff 3461 }
bogdanm 0:9b334a45a8ff 3462 break;
bogdanm 0:9b334a45a8ff 3463 case TIM_DMA_COM:
bogdanm 0:9b334a45a8ff 3464 {
bogdanm 0:9b334a45a8ff 3465 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
bogdanm 0:9b334a45a8ff 3466 }
bogdanm 0:9b334a45a8ff 3467 break;
bogdanm 0:9b334a45a8ff 3468 case TIM_DMA_TRIGGER:
bogdanm 0:9b334a45a8ff 3469 {
bogdanm 0:9b334a45a8ff 3470 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm 0:9b334a45a8ff 3471 }
bogdanm 0:9b334a45a8ff 3472 break;
bogdanm 0:9b334a45a8ff 3473 default:
bogdanm 0:9b334a45a8ff 3474 break;
bogdanm 0:9b334a45a8ff 3475 }
bogdanm 0:9b334a45a8ff 3476
bogdanm 0:9b334a45a8ff 3477 /* Disable the TIM Update DMA request */
bogdanm 0:9b334a45a8ff 3478 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm 0:9b334a45a8ff 3479
bogdanm 0:9b334a45a8ff 3480 /* Return function status */
bogdanm 0:9b334a45a8ff 3481 return HAL_OK;
bogdanm 0:9b334a45a8ff 3482 }
bogdanm 0:9b334a45a8ff 3483
bogdanm 0:9b334a45a8ff 3484 /**
bogdanm 0:9b334a45a8ff 3485 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
bogdanm 0:9b334a45a8ff 3486 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 3487 * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
bogdanm 0:9b334a45a8ff 3488 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3489 * @arg TIM_DMABASE_CR1
bogdanm 0:9b334a45a8ff 3490 * @arg TIM_DMABASE_CR2
bogdanm 0:9b334a45a8ff 3491 * @arg TIM_DMABASE_SMCR
bogdanm 0:9b334a45a8ff 3492 * @arg TIM_DMABASE_DIER
bogdanm 0:9b334a45a8ff 3493 * @arg TIM_DMABASE_SR
bogdanm 0:9b334a45a8ff 3494 * @arg TIM_DMABASE_EGR
bogdanm 0:9b334a45a8ff 3495 * @arg TIM_DMABASE_CCMR1
bogdanm 0:9b334a45a8ff 3496 * @arg TIM_DMABASE_CCMR2
bogdanm 0:9b334a45a8ff 3497 * @arg TIM_DMABASE_CCER
bogdanm 0:9b334a45a8ff 3498 * @arg TIM_DMABASE_CNT
bogdanm 0:9b334a45a8ff 3499 * @arg TIM_DMABASE_PSC
bogdanm 0:9b334a45a8ff 3500 * @arg TIM_DMABASE_ARR
bogdanm 0:9b334a45a8ff 3501 * @arg TIM_DMABASE_RCR
bogdanm 0:9b334a45a8ff 3502 * @arg TIM_DMABASE_CCR1
bogdanm 0:9b334a45a8ff 3503 * @arg TIM_DMABASE_CCR2
bogdanm 0:9b334a45a8ff 3504 * @arg TIM_DMABASE_CCR3
bogdanm 0:9b334a45a8ff 3505 * @arg TIM_DMABASE_CCR4
bogdanm 0:9b334a45a8ff 3506 * @arg TIM_DMABASE_BDTR
bogdanm 0:9b334a45a8ff 3507 * @arg TIM_DMABASE_DCR
bogdanm 0:9b334a45a8ff 3508 * @param BurstRequestSrc : TIM DMA Request sources
bogdanm 0:9b334a45a8ff 3509 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3510 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
bogdanm 0:9b334a45a8ff 3511 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
bogdanm 0:9b334a45a8ff 3512 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
bogdanm 0:9b334a45a8ff 3513 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
bogdanm 0:9b334a45a8ff 3514 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
bogdanm 0:9b334a45a8ff 3515 * @arg TIM_DMA_COM: TIM Commutation DMA source
bogdanm 0:9b334a45a8ff 3516 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
bogdanm 0:9b334a45a8ff 3517 * @param BurstBuffer : The Buffer address.
bogdanm 0:9b334a45a8ff 3518 * @param BurstLength : DMA Burst length. This parameter can be one value
bogdanm 0:9b334a45a8ff 3519 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
bogdanm 0:9b334a45a8ff 3520 * @retval HAL status
bogdanm 0:9b334a45a8ff 3521 */
bogdanm 0:9b334a45a8ff 3522 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
bogdanm 0:9b334a45a8ff 3523 uint32_t *BurstBuffer, uint32_t BurstLength)
bogdanm 0:9b334a45a8ff 3524 {
bogdanm 0:9b334a45a8ff 3525 /* Check the parameters */
bogdanm 0:9b334a45a8ff 3526 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3527 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
bogdanm 0:9b334a45a8ff 3528 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm 0:9b334a45a8ff 3529 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
bogdanm 0:9b334a45a8ff 3530
bogdanm 0:9b334a45a8ff 3531 if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm 0:9b334a45a8ff 3532 {
bogdanm 0:9b334a45a8ff 3533 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 3534 }
bogdanm 0:9b334a45a8ff 3535 else if((htim->State == HAL_TIM_STATE_READY))
bogdanm 0:9b334a45a8ff 3536 {
bogdanm 0:9b334a45a8ff 3537 if((BurstBuffer == 0 ) && (BurstLength > 0))
bogdanm 0:9b334a45a8ff 3538 {
bogdanm 0:9b334a45a8ff 3539 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 3540 }
bogdanm 0:9b334a45a8ff 3541 else
bogdanm 0:9b334a45a8ff 3542 {
bogdanm 0:9b334a45a8ff 3543 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 3544 }
bogdanm 0:9b334a45a8ff 3545 }
bogdanm 0:9b334a45a8ff 3546 switch(BurstRequestSrc)
bogdanm 0:9b334a45a8ff 3547 {
bogdanm 0:9b334a45a8ff 3548 case TIM_DMA_UPDATE:
bogdanm 0:9b334a45a8ff 3549 {
bogdanm 0:9b334a45a8ff 3550 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3551 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
bogdanm 0:9b334a45a8ff 3552
bogdanm 0:9b334a45a8ff 3553 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3554 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3555
bogdanm 0:9b334a45a8ff 3556 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3557 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3558 }
bogdanm 0:9b334a45a8ff 3559 break;
bogdanm 0:9b334a45a8ff 3560 case TIM_DMA_CC1:
bogdanm 0:9b334a45a8ff 3561 {
bogdanm 0:9b334a45a8ff 3562 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3563 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 3564
bogdanm 0:9b334a45a8ff 3565 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3566 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3567
bogdanm 0:9b334a45a8ff 3568 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3569 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3570 }
bogdanm 0:9b334a45a8ff 3571 break;
bogdanm 0:9b334a45a8ff 3572 case TIM_DMA_CC2:
bogdanm 0:9b334a45a8ff 3573 {
bogdanm 0:9b334a45a8ff 3574 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3575 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 3576
bogdanm 0:9b334a45a8ff 3577 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3578 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3579
bogdanm 0:9b334a45a8ff 3580 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3581 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3582 }
bogdanm 0:9b334a45a8ff 3583 break;
bogdanm 0:9b334a45a8ff 3584 case TIM_DMA_CC3:
bogdanm 0:9b334a45a8ff 3585 {
bogdanm 0:9b334a45a8ff 3586 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3587 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 3588
bogdanm 0:9b334a45a8ff 3589 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3590 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3591
bogdanm 0:9b334a45a8ff 3592 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3593 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3594 }
bogdanm 0:9b334a45a8ff 3595 break;
bogdanm 0:9b334a45a8ff 3596 case TIM_DMA_CC4:
bogdanm 0:9b334a45a8ff 3597 {
bogdanm 0:9b334a45a8ff 3598 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3599 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm 0:9b334a45a8ff 3600
bogdanm 0:9b334a45a8ff 3601 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3602 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3603
bogdanm 0:9b334a45a8ff 3604 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3605 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3606 }
bogdanm 0:9b334a45a8ff 3607 break;
bogdanm 0:9b334a45a8ff 3608 case TIM_DMA_COM:
bogdanm 0:9b334a45a8ff 3609 {
bogdanm 0:9b334a45a8ff 3610 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3611 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
bogdanm 0:9b334a45a8ff 3612
bogdanm 0:9b334a45a8ff 3613 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3614 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3615
bogdanm 0:9b334a45a8ff 3616 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3617 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3618 }
bogdanm 0:9b334a45a8ff 3619 break;
bogdanm 0:9b334a45a8ff 3620 case TIM_DMA_TRIGGER:
bogdanm 0:9b334a45a8ff 3621 {
bogdanm 0:9b334a45a8ff 3622 /* Set the DMA Period elapsed callback */
bogdanm 0:9b334a45a8ff 3623 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
bogdanm 0:9b334a45a8ff 3624
bogdanm 0:9b334a45a8ff 3625 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 3626 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
bogdanm 0:9b334a45a8ff 3627
bogdanm 0:9b334a45a8ff 3628 /* Enable the DMA channel */
bogdanm 0:9b334a45a8ff 3629 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
bogdanm 0:9b334a45a8ff 3630 }
bogdanm 0:9b334a45a8ff 3631 break;
bogdanm 0:9b334a45a8ff 3632 default:
bogdanm 0:9b334a45a8ff 3633 break;
bogdanm 0:9b334a45a8ff 3634 }
bogdanm 0:9b334a45a8ff 3635
bogdanm 0:9b334a45a8ff 3636 /* configure the DMA Burst Mode */
bogdanm 0:9b334a45a8ff 3637 htim->Instance->DCR = BurstBaseAddress | BurstLength;
bogdanm 0:9b334a45a8ff 3638
bogdanm 0:9b334a45a8ff 3639 /* Enable the TIM DMA Request */
bogdanm 0:9b334a45a8ff 3640 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
bogdanm 0:9b334a45a8ff 3641
bogdanm 0:9b334a45a8ff 3642 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 3643
bogdanm 0:9b334a45a8ff 3644 /* Return function status */
bogdanm 0:9b334a45a8ff 3645 return HAL_OK;
bogdanm 0:9b334a45a8ff 3646 }
bogdanm 0:9b334a45a8ff 3647
bogdanm 0:9b334a45a8ff 3648 /**
bogdanm 0:9b334a45a8ff 3649 * @brief Stop the DMA burst reading
bogdanm 0:9b334a45a8ff 3650 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 3651 * @param BurstRequestSrc : TIM DMA Request sources to disable.
bogdanm 0:9b334a45a8ff 3652 * @retval HAL status
bogdanm 0:9b334a45a8ff 3653 */
bogdanm 0:9b334a45a8ff 3654 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
bogdanm 0:9b334a45a8ff 3655 {
bogdanm 0:9b334a45a8ff 3656 /* Check the parameters */
bogdanm 0:9b334a45a8ff 3657 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
bogdanm 0:9b334a45a8ff 3658
bogdanm 0:9b334a45a8ff 3659 /* Abort the DMA transfer (at least disable the DMA channel) */
bogdanm 0:9b334a45a8ff 3660 switch(BurstRequestSrc)
bogdanm 0:9b334a45a8ff 3661 {
bogdanm 0:9b334a45a8ff 3662 case TIM_DMA_UPDATE:
bogdanm 0:9b334a45a8ff 3663 {
bogdanm 0:9b334a45a8ff 3664 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
bogdanm 0:9b334a45a8ff 3665 }
bogdanm 0:9b334a45a8ff 3666 break;
bogdanm 0:9b334a45a8ff 3667 case TIM_DMA_CC1:
bogdanm 0:9b334a45a8ff 3668 {
bogdanm 0:9b334a45a8ff 3669 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
bogdanm 0:9b334a45a8ff 3670 }
bogdanm 0:9b334a45a8ff 3671 break;
bogdanm 0:9b334a45a8ff 3672 case TIM_DMA_CC2:
bogdanm 0:9b334a45a8ff 3673 {
bogdanm 0:9b334a45a8ff 3674 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
bogdanm 0:9b334a45a8ff 3675 }
bogdanm 0:9b334a45a8ff 3676 break;
bogdanm 0:9b334a45a8ff 3677 case TIM_DMA_CC3:
bogdanm 0:9b334a45a8ff 3678 {
bogdanm 0:9b334a45a8ff 3679 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
bogdanm 0:9b334a45a8ff 3680 }
bogdanm 0:9b334a45a8ff 3681 break;
bogdanm 0:9b334a45a8ff 3682 case TIM_DMA_CC4:
bogdanm 0:9b334a45a8ff 3683 {
bogdanm 0:9b334a45a8ff 3684 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
bogdanm 0:9b334a45a8ff 3685 }
bogdanm 0:9b334a45a8ff 3686 break;
bogdanm 0:9b334a45a8ff 3687 case TIM_DMA_COM:
bogdanm 0:9b334a45a8ff 3688 {
bogdanm 0:9b334a45a8ff 3689 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
bogdanm 0:9b334a45a8ff 3690 }
bogdanm 0:9b334a45a8ff 3691 break;
bogdanm 0:9b334a45a8ff 3692 case TIM_DMA_TRIGGER:
bogdanm 0:9b334a45a8ff 3693 {
bogdanm 0:9b334a45a8ff 3694 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
bogdanm 0:9b334a45a8ff 3695 }
bogdanm 0:9b334a45a8ff 3696 break;
bogdanm 0:9b334a45a8ff 3697 default:
bogdanm 0:9b334a45a8ff 3698 break;
bogdanm 0:9b334a45a8ff 3699 }
bogdanm 0:9b334a45a8ff 3700
bogdanm 0:9b334a45a8ff 3701 /* Disable the TIM Update DMA request */
bogdanm 0:9b334a45a8ff 3702 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
bogdanm 0:9b334a45a8ff 3703
bogdanm 0:9b334a45a8ff 3704 /* Return function status */
bogdanm 0:9b334a45a8ff 3705 return HAL_OK;
bogdanm 0:9b334a45a8ff 3706 }
bogdanm 0:9b334a45a8ff 3707
bogdanm 0:9b334a45a8ff 3708 /**
bogdanm 0:9b334a45a8ff 3709 * @brief Generate a software event
bogdanm 0:9b334a45a8ff 3710 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 3711 * @param EventSource : specifies the event source.
bogdanm 0:9b334a45a8ff 3712 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3713 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
bogdanm 0:9b334a45a8ff 3714 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
bogdanm 0:9b334a45a8ff 3715 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
bogdanm 0:9b334a45a8ff 3716 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
bogdanm 0:9b334a45a8ff 3717 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
bogdanm 0:9b334a45a8ff 3718 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
bogdanm 0:9b334a45a8ff 3719 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
bogdanm 0:9b334a45a8ff 3720 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
bogdanm 0:9b334a45a8ff 3721 * @note TIM6 and TIM7 can only generate an update event.
bogdanm 0:9b334a45a8ff 3722 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
bogdanm 0:9b334a45a8ff 3723 * @retval HAL status
bogdanm 0:9b334a45a8ff 3724 */
bogdanm 0:9b334a45a8ff 3725
bogdanm 0:9b334a45a8ff 3726 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
bogdanm 0:9b334a45a8ff 3727 {
bogdanm 0:9b334a45a8ff 3728 /* Check the parameters */
bogdanm 0:9b334a45a8ff 3729 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3730 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
bogdanm 0:9b334a45a8ff 3731
bogdanm 0:9b334a45a8ff 3732 /* Process Locked */
bogdanm 0:9b334a45a8ff 3733 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 3734
bogdanm 0:9b334a45a8ff 3735 /* Change the TIM state */
bogdanm 0:9b334a45a8ff 3736 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 3737
bogdanm 0:9b334a45a8ff 3738 /* Set the event sources */
bogdanm 0:9b334a45a8ff 3739 htim->Instance->EGR = EventSource;
bogdanm 0:9b334a45a8ff 3740
bogdanm 0:9b334a45a8ff 3741 /* Change the TIM state */
bogdanm 0:9b334a45a8ff 3742 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 3743
bogdanm 0:9b334a45a8ff 3744 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 3745
bogdanm 0:9b334a45a8ff 3746 /* Return function status */
bogdanm 0:9b334a45a8ff 3747 return HAL_OK;
bogdanm 0:9b334a45a8ff 3748 }
bogdanm 0:9b334a45a8ff 3749
bogdanm 0:9b334a45a8ff 3750 /**
bogdanm 0:9b334a45a8ff 3751 * @brief Configures the OCRef clear feature
bogdanm 0:9b334a45a8ff 3752 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 3753 * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
bogdanm 0:9b334a45a8ff 3754 * contains the OCREF clear feature and parameters for the TIM peripheral.
bogdanm 0:9b334a45a8ff 3755 * @param Channel : specifies the TIM Channel
bogdanm 0:9b334a45a8ff 3756 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3757 * @arg TIM_CHANNEL_1: TIM Channel 1
bogdanm 0:9b334a45a8ff 3758 * @arg TIM_CHANNEL_2: TIM Channel 2
bogdanm 0:9b334a45a8ff 3759 * @arg TIM_CHANNEL_3: TIM Channel 3
bogdanm 0:9b334a45a8ff 3760 * @arg TIM_CHANNEL_4: TIM Channel 4
bogdanm 0:9b334a45a8ff 3761 * @retval HAL status
bogdanm 0:9b334a45a8ff 3762 */
bogdanm 0:9b334a45a8ff 3763 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
bogdanm 0:9b334a45a8ff 3764 {
bogdanm 0:9b334a45a8ff 3765 uint32_t tmpsmcr = 0;
bogdanm 0:9b334a45a8ff 3766
bogdanm 0:9b334a45a8ff 3767 /* Check the parameters */
bogdanm 0:9b334a45a8ff 3768 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3769 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
bogdanm 0:9b334a45a8ff 3770 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
bogdanm 0:9b334a45a8ff 3771 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
bogdanm 0:9b334a45a8ff 3772 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
bogdanm 0:9b334a45a8ff 3773
bogdanm 0:9b334a45a8ff 3774 /* Process Locked */
bogdanm 0:9b334a45a8ff 3775 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 3776
bogdanm 0:9b334a45a8ff 3777 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 3778
bogdanm 0:9b334a45a8ff 3779 switch (sClearInputConfig->ClearInputSource)
bogdanm 0:9b334a45a8ff 3780 {
bogdanm 0:9b334a45a8ff 3781 case TIM_CLEARINPUTSOURCE_NONE:
bogdanm 0:9b334a45a8ff 3782 {
bogdanm 0:9b334a45a8ff 3783 /* Clear the OCREF clear selection bit */
bogdanm 0:9b334a45a8ff 3784 tmpsmcr &= ~TIM_SMCR_OCCS;
bogdanm 0:9b334a45a8ff 3785
bogdanm 0:9b334a45a8ff 3786 /* Clear the ETR Bits */
bogdanm 0:9b334a45a8ff 3787 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
bogdanm 0:9b334a45a8ff 3788
bogdanm 0:9b334a45a8ff 3789 /* Set TIMx_SMCR */
bogdanm 0:9b334a45a8ff 3790 htim->Instance->SMCR = tmpsmcr;
bogdanm 0:9b334a45a8ff 3791 }
bogdanm 0:9b334a45a8ff 3792 break;
bogdanm 0:9b334a45a8ff 3793
bogdanm 0:9b334a45a8ff 3794 case TIM_CLEARINPUTSOURCE_ETR:
bogdanm 0:9b334a45a8ff 3795 {
bogdanm 0:9b334a45a8ff 3796 TIM_ETR_SetConfig(htim->Instance,
bogdanm 0:9b334a45a8ff 3797 sClearInputConfig->ClearInputPrescaler,
bogdanm 0:9b334a45a8ff 3798 sClearInputConfig->ClearInputPolarity,
bogdanm 0:9b334a45a8ff 3799 sClearInputConfig->ClearInputFilter);
bogdanm 0:9b334a45a8ff 3800
bogdanm 0:9b334a45a8ff 3801 /* Set the OCREF clear selection bit */
bogdanm 0:9b334a45a8ff 3802 htim->Instance->SMCR |= TIM_SMCR_OCCS;
bogdanm 0:9b334a45a8ff 3803 }
bogdanm 0:9b334a45a8ff 3804 break;
bogdanm 0:9b334a45a8ff 3805 default:
bogdanm 0:9b334a45a8ff 3806 break;
bogdanm 0:9b334a45a8ff 3807 }
bogdanm 0:9b334a45a8ff 3808
bogdanm 0:9b334a45a8ff 3809 switch (Channel)
bogdanm 0:9b334a45a8ff 3810 {
bogdanm 0:9b334a45a8ff 3811 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 3812 {
bogdanm 0:9b334a45a8ff 3813 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 3814 {
bogdanm 0:9b334a45a8ff 3815 /* Enable the Ocref clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 3816 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
bogdanm 0:9b334a45a8ff 3817 }
bogdanm 0:9b334a45a8ff 3818 else
bogdanm 0:9b334a45a8ff 3819 {
bogdanm 0:9b334a45a8ff 3820 /* Disable the Ocref clear feature for Channel 1 */
bogdanm 0:9b334a45a8ff 3821 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
bogdanm 0:9b334a45a8ff 3822 }
bogdanm 0:9b334a45a8ff 3823 }
bogdanm 0:9b334a45a8ff 3824 break;
bogdanm 0:9b334a45a8ff 3825 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 3826 {
bogdanm 0:9b334a45a8ff 3827 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3828 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 3829 {
bogdanm 0:9b334a45a8ff 3830 /* Enable the Ocref clear feature for Channel 2 */
bogdanm 0:9b334a45a8ff 3831 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
bogdanm 0:9b334a45a8ff 3832 }
bogdanm 0:9b334a45a8ff 3833 else
bogdanm 0:9b334a45a8ff 3834 {
bogdanm 0:9b334a45a8ff 3835 /* Disable the Ocref clear feature for Channel 2 */
bogdanm 0:9b334a45a8ff 3836 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
bogdanm 0:9b334a45a8ff 3837 }
bogdanm 0:9b334a45a8ff 3838 }
bogdanm 0:9b334a45a8ff 3839 break;
bogdanm 0:9b334a45a8ff 3840 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 3841 {
bogdanm 0:9b334a45a8ff 3842 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3843 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 3844 {
bogdanm 0:9b334a45a8ff 3845 /* Enable the Ocref clear feature for Channel 3 */
bogdanm 0:9b334a45a8ff 3846 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
bogdanm 0:9b334a45a8ff 3847 }
bogdanm 0:9b334a45a8ff 3848 else
bogdanm 0:9b334a45a8ff 3849 {
bogdanm 0:9b334a45a8ff 3850 /* Disable the Ocref clear feature for Channel 3 */
bogdanm 0:9b334a45a8ff 3851 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
bogdanm 0:9b334a45a8ff 3852 }
bogdanm 0:9b334a45a8ff 3853 }
bogdanm 0:9b334a45a8ff 3854 break;
bogdanm 0:9b334a45a8ff 3855 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 3856 {
bogdanm 0:9b334a45a8ff 3857 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3858 if(sClearInputConfig->ClearInputState != RESET)
bogdanm 0:9b334a45a8ff 3859 {
bogdanm 0:9b334a45a8ff 3860 /* Enable the Ocref clear feature for Channel 4 */
bogdanm 0:9b334a45a8ff 3861 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
bogdanm 0:9b334a45a8ff 3862 }
bogdanm 0:9b334a45a8ff 3863 else
bogdanm 0:9b334a45a8ff 3864 {
bogdanm 0:9b334a45a8ff 3865 /* Disable the Ocref clear feature for Channel 4 */
bogdanm 0:9b334a45a8ff 3866 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
bogdanm 0:9b334a45a8ff 3867 }
bogdanm 0:9b334a45a8ff 3868 }
bogdanm 0:9b334a45a8ff 3869 break;
bogdanm 0:9b334a45a8ff 3870 default:
bogdanm 0:9b334a45a8ff 3871 break;
bogdanm 0:9b334a45a8ff 3872 }
bogdanm 0:9b334a45a8ff 3873
bogdanm 0:9b334a45a8ff 3874 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 3875
bogdanm 0:9b334a45a8ff 3876 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 3877
bogdanm 0:9b334a45a8ff 3878 return HAL_OK;
bogdanm 0:9b334a45a8ff 3879 }
bogdanm 0:9b334a45a8ff 3880
bogdanm 0:9b334a45a8ff 3881 /**
bogdanm 0:9b334a45a8ff 3882 * @brief Configures the clock source to be used
bogdanm 0:9b334a45a8ff 3883 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 3884 * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
bogdanm 0:9b334a45a8ff 3885 * contains the clock source information for the TIM peripheral.
bogdanm 0:9b334a45a8ff 3886 * @retval HAL status
bogdanm 0:9b334a45a8ff 3887 */
bogdanm 0:9b334a45a8ff 3888 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
bogdanm 0:9b334a45a8ff 3889 {
bogdanm 0:9b334a45a8ff 3890 uint32_t tmpsmcr = 0;
bogdanm 0:9b334a45a8ff 3891
bogdanm 0:9b334a45a8ff 3892 /* Process Locked */
bogdanm 0:9b334a45a8ff 3893 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 3894
bogdanm 0:9b334a45a8ff 3895 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 3896
bogdanm 0:9b334a45a8ff 3897 /* Check the parameters */
bogdanm 0:9b334a45a8ff 3898 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
bogdanm 0:9b334a45a8ff 3899 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
bogdanm 0:9b334a45a8ff 3900 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
bogdanm 0:9b334a45a8ff 3901 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
bogdanm 0:9b334a45a8ff 3902
bogdanm 0:9b334a45a8ff 3903 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
bogdanm 0:9b334a45a8ff 3904 tmpsmcr = htim->Instance->SMCR;
bogdanm 0:9b334a45a8ff 3905 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
bogdanm 0:9b334a45a8ff 3906 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
bogdanm 0:9b334a45a8ff 3907 htim->Instance->SMCR = tmpsmcr;
bogdanm 0:9b334a45a8ff 3908
bogdanm 0:9b334a45a8ff 3909 switch (sClockSourceConfig->ClockSource)
bogdanm 0:9b334a45a8ff 3910 {
bogdanm 0:9b334a45a8ff 3911 case TIM_CLOCKSOURCE_INTERNAL:
bogdanm 0:9b334a45a8ff 3912 {
bogdanm 0:9b334a45a8ff 3913 assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3914 /* Disable slave mode to clock the prescaler directly with the internal clock */
bogdanm 0:9b334a45a8ff 3915 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm 0:9b334a45a8ff 3916 }
bogdanm 0:9b334a45a8ff 3917 break;
bogdanm 0:9b334a45a8ff 3918
bogdanm 0:9b334a45a8ff 3919 case TIM_CLOCKSOURCE_ETRMODE1:
bogdanm 0:9b334a45a8ff 3920 {
bogdanm 0:9b334a45a8ff 3921 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
bogdanm 0:9b334a45a8ff 3922 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3923
bogdanm 0:9b334a45a8ff 3924 /* Configure the ETR Clock source */
bogdanm 0:9b334a45a8ff 3925 TIM_ETR_SetConfig(htim->Instance,
bogdanm 0:9b334a45a8ff 3926 sClockSourceConfig->ClockPrescaler,
bogdanm 0:9b334a45a8ff 3927 sClockSourceConfig->ClockPolarity,
bogdanm 0:9b334a45a8ff 3928 sClockSourceConfig->ClockFilter);
bogdanm 0:9b334a45a8ff 3929 /* Get the TIMx SMCR register value */
bogdanm 0:9b334a45a8ff 3930 tmpsmcr = htim->Instance->SMCR;
bogdanm 0:9b334a45a8ff 3931 /* Reset the SMS and TS Bits */
bogdanm 0:9b334a45a8ff 3932 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
bogdanm 0:9b334a45a8ff 3933 /* Select the External clock mode1 and the ETRF trigger */
bogdanm 0:9b334a45a8ff 3934 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
bogdanm 0:9b334a45a8ff 3935 /* Write to TIMx SMCR */
bogdanm 0:9b334a45a8ff 3936 htim->Instance->SMCR = tmpsmcr;
bogdanm 0:9b334a45a8ff 3937 }
bogdanm 0:9b334a45a8ff 3938 break;
bogdanm 0:9b334a45a8ff 3939
bogdanm 0:9b334a45a8ff 3940 case TIM_CLOCKSOURCE_ETRMODE2:
bogdanm 0:9b334a45a8ff 3941 {
bogdanm 0:9b334a45a8ff 3942 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
bogdanm 0:9b334a45a8ff 3943 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3944
bogdanm 0:9b334a45a8ff 3945 /* Configure the ETR Clock source */
bogdanm 0:9b334a45a8ff 3946 TIM_ETR_SetConfig(htim->Instance,
bogdanm 0:9b334a45a8ff 3947 sClockSourceConfig->ClockPrescaler,
bogdanm 0:9b334a45a8ff 3948 sClockSourceConfig->ClockPolarity,
bogdanm 0:9b334a45a8ff 3949 sClockSourceConfig->ClockFilter);
bogdanm 0:9b334a45a8ff 3950 /* Enable the External clock mode2 */
bogdanm 0:9b334a45a8ff 3951 htim->Instance->SMCR |= TIM_SMCR_ECE;
bogdanm 0:9b334a45a8ff 3952 }
bogdanm 0:9b334a45a8ff 3953 break;
bogdanm 0:9b334a45a8ff 3954
bogdanm 0:9b334a45a8ff 3955 case TIM_CLOCKSOURCE_TI1:
bogdanm 0:9b334a45a8ff 3956 {
bogdanm 0:9b334a45a8ff 3957 /* Check whether or not the timer instance supports external clock mode 1 */
bogdanm 0:9b334a45a8ff 3958 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3959
bogdanm 0:9b334a45a8ff 3960 TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm 0:9b334a45a8ff 3961 sClockSourceConfig->ClockPolarity,
bogdanm 0:9b334a45a8ff 3962 sClockSourceConfig->ClockFilter);
bogdanm 0:9b334a45a8ff 3963 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
bogdanm 0:9b334a45a8ff 3964 }
bogdanm 0:9b334a45a8ff 3965 break;
bogdanm 0:9b334a45a8ff 3966 case TIM_CLOCKSOURCE_TI2:
bogdanm 0:9b334a45a8ff 3967 {
bogdanm 0:9b334a45a8ff 3968 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
bogdanm 0:9b334a45a8ff 3969 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3970
bogdanm 0:9b334a45a8ff 3971 TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm 0:9b334a45a8ff 3972 sClockSourceConfig->ClockPolarity,
bogdanm 0:9b334a45a8ff 3973 sClockSourceConfig->ClockFilter);
bogdanm 0:9b334a45a8ff 3974 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
bogdanm 0:9b334a45a8ff 3975 }
bogdanm 0:9b334a45a8ff 3976 break;
bogdanm 0:9b334a45a8ff 3977 case TIM_CLOCKSOURCE_TI1ED:
bogdanm 0:9b334a45a8ff 3978 {
bogdanm 0:9b334a45a8ff 3979 /* Check whether or not the timer instance supports external clock mode 1 */
bogdanm 0:9b334a45a8ff 3980 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3981
bogdanm 0:9b334a45a8ff 3982 TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm 0:9b334a45a8ff 3983 sClockSourceConfig->ClockPolarity,
bogdanm 0:9b334a45a8ff 3984 sClockSourceConfig->ClockFilter);
bogdanm 0:9b334a45a8ff 3985 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
bogdanm 0:9b334a45a8ff 3986 }
bogdanm 0:9b334a45a8ff 3987 break;
bogdanm 0:9b334a45a8ff 3988 case TIM_CLOCKSOURCE_ITR0:
bogdanm 0:9b334a45a8ff 3989 {
bogdanm 0:9b334a45a8ff 3990 /* Check whether or not the timer instance supports external clock mode 1 */
bogdanm 0:9b334a45a8ff 3991 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 3992
bogdanm 0:9b334a45a8ff 3993 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
bogdanm 0:9b334a45a8ff 3994 }
bogdanm 0:9b334a45a8ff 3995 break;
bogdanm 0:9b334a45a8ff 3996 case TIM_CLOCKSOURCE_ITR1:
bogdanm 0:9b334a45a8ff 3997 {
bogdanm 0:9b334a45a8ff 3998 /* Check whether or not the timer instance supports external clock mode 1 */
bogdanm 0:9b334a45a8ff 3999 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4000
bogdanm 0:9b334a45a8ff 4001 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
bogdanm 0:9b334a45a8ff 4002 }
bogdanm 0:9b334a45a8ff 4003 break;
bogdanm 0:9b334a45a8ff 4004 case TIM_CLOCKSOURCE_ITR2:
bogdanm 0:9b334a45a8ff 4005 {
bogdanm 0:9b334a45a8ff 4006 /* Check whether or not the timer instance supports external clock mode 1 */
bogdanm 0:9b334a45a8ff 4007 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4008
bogdanm 0:9b334a45a8ff 4009 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
bogdanm 0:9b334a45a8ff 4010 }
bogdanm 0:9b334a45a8ff 4011 break;
bogdanm 0:9b334a45a8ff 4012 case TIM_CLOCKSOURCE_ITR3:
bogdanm 0:9b334a45a8ff 4013 {
bogdanm 0:9b334a45a8ff 4014 /* Check whether or not the timer instance supports external clock mode 1 */
bogdanm 0:9b334a45a8ff 4015 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4016
bogdanm 0:9b334a45a8ff 4017 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
bogdanm 0:9b334a45a8ff 4018 }
bogdanm 0:9b334a45a8ff 4019 break;
bogdanm 0:9b334a45a8ff 4020
bogdanm 0:9b334a45a8ff 4021 default:
bogdanm 0:9b334a45a8ff 4022 break;
bogdanm 0:9b334a45a8ff 4023 }
bogdanm 0:9b334a45a8ff 4024 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 4025
bogdanm 0:9b334a45a8ff 4026 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 4027
bogdanm 0:9b334a45a8ff 4028 return HAL_OK;
bogdanm 0:9b334a45a8ff 4029 }
bogdanm 0:9b334a45a8ff 4030
bogdanm 0:9b334a45a8ff 4031 /**
bogdanm 0:9b334a45a8ff 4032 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
bogdanm 0:9b334a45a8ff 4033 * or a XOR combination between CH1_input, CH2_input & CH3_input
bogdanm 0:9b334a45a8ff 4034 * @param htim : TIM handle.
bogdanm 0:9b334a45a8ff 4035 * @param TI1_Selection : Indicate whether or not channel 1 is connected to the
bogdanm 0:9b334a45a8ff 4036 * output of a XOR gate.
bogdanm 0:9b334a45a8ff 4037 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 4038 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
bogdanm 0:9b334a45a8ff 4039 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
bogdanm 0:9b334a45a8ff 4040 * pins are connected to the TI1 input (XOR combination)
bogdanm 0:9b334a45a8ff 4041 * @retval HAL status
bogdanm 0:9b334a45a8ff 4042 */
bogdanm 0:9b334a45a8ff 4043 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
bogdanm 0:9b334a45a8ff 4044 {
bogdanm 0:9b334a45a8ff 4045 uint32_t tmpcr2 = 0;
bogdanm 0:9b334a45a8ff 4046
bogdanm 0:9b334a45a8ff 4047 /* Check the parameters */
bogdanm 0:9b334a45a8ff 4048 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4049 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
bogdanm 0:9b334a45a8ff 4050
bogdanm 0:9b334a45a8ff 4051 /* Get the TIMx CR2 register value */
bogdanm 0:9b334a45a8ff 4052 tmpcr2 = htim->Instance->CR2;
bogdanm 0:9b334a45a8ff 4053
bogdanm 0:9b334a45a8ff 4054 /* Reset the TI1 selection */
bogdanm 0:9b334a45a8ff 4055 tmpcr2 &= ~TIM_CR2_TI1S;
bogdanm 0:9b334a45a8ff 4056
bogdanm 0:9b334a45a8ff 4057 /* Set the the TI1 selection */
bogdanm 0:9b334a45a8ff 4058 tmpcr2 |= TI1_Selection;
bogdanm 0:9b334a45a8ff 4059
bogdanm 0:9b334a45a8ff 4060 /* Write to TIMxCR2 */
bogdanm 0:9b334a45a8ff 4061 htim->Instance->CR2 = tmpcr2;
bogdanm 0:9b334a45a8ff 4062
bogdanm 0:9b334a45a8ff 4063 return HAL_OK;
bogdanm 0:9b334a45a8ff 4064 }
bogdanm 0:9b334a45a8ff 4065
bogdanm 0:9b334a45a8ff 4066 /**
bogdanm 0:9b334a45a8ff 4067 * @brief Configures the TIM in Slave mode
bogdanm 0:9b334a45a8ff 4068 * @param htim : TIM handle.
bogdanm 0:9b334a45a8ff 4069 * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm 0:9b334a45a8ff 4070 * contains the selected trigger (internal trigger input, filtered
bogdanm 0:9b334a45a8ff 4071 * timer input or external trigger input) and the ) and the Slave
bogdanm 0:9b334a45a8ff 4072 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm 0:9b334a45a8ff 4073 * @retval HAL status
bogdanm 0:9b334a45a8ff 4074 */
bogdanm 0:9b334a45a8ff 4075 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm 0:9b334a45a8ff 4076 {
bogdanm 0:9b334a45a8ff 4077 /* Check the parameters */
bogdanm 0:9b334a45a8ff 4078 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4079 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm 0:9b334a45a8ff 4080 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm 0:9b334a45a8ff 4081
bogdanm 0:9b334a45a8ff 4082 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 4083
bogdanm 0:9b334a45a8ff 4084 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 4085
bogdanm 0:9b334a45a8ff 4086 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
bogdanm 0:9b334a45a8ff 4087
bogdanm 0:9b334a45a8ff 4088 /* Disable Trigger Interrupt */
bogdanm 0:9b334a45a8ff 4089 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
bogdanm 0:9b334a45a8ff 4090
bogdanm 0:9b334a45a8ff 4091 /* Disable Trigger DMA request */
bogdanm 0:9b334a45a8ff 4092 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
bogdanm 0:9b334a45a8ff 4093
bogdanm 0:9b334a45a8ff 4094 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 4095
bogdanm 0:9b334a45a8ff 4096 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 4097
bogdanm 0:9b334a45a8ff 4098 return HAL_OK;
bogdanm 0:9b334a45a8ff 4099 }
bogdanm 0:9b334a45a8ff 4100
bogdanm 0:9b334a45a8ff 4101 /**
bogdanm 0:9b334a45a8ff 4102 * @brief Configures the TIM in Slave mode in interrupt mode
bogdanm 0:9b334a45a8ff 4103 * @param htim: TIM handle.
bogdanm 0:9b334a45a8ff 4104 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
bogdanm 0:9b334a45a8ff 4105 * contains the selected trigger (internal trigger input, filtered
bogdanm 0:9b334a45a8ff 4106 * timer input or external trigger input) and the ) and the Slave
bogdanm 0:9b334a45a8ff 4107 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
bogdanm 0:9b334a45a8ff 4108 * @retval HAL status
bogdanm 0:9b334a45a8ff 4109 */
bogdanm 0:9b334a45a8ff 4110 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
bogdanm 0:9b334a45a8ff 4111 TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm 0:9b334a45a8ff 4112 {
bogdanm 0:9b334a45a8ff 4113 /* Check the parameters */
bogdanm 0:9b334a45a8ff 4114 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4115 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
bogdanm 0:9b334a45a8ff 4116 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
bogdanm 0:9b334a45a8ff 4117
bogdanm 0:9b334a45a8ff 4118 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 4119
bogdanm 0:9b334a45a8ff 4120 htim->State = HAL_TIM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 4121
bogdanm 0:9b334a45a8ff 4122 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
bogdanm 0:9b334a45a8ff 4123
bogdanm 0:9b334a45a8ff 4124 /* Enable Trigger Interrupt */
bogdanm 0:9b334a45a8ff 4125 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
bogdanm 0:9b334a45a8ff 4126
bogdanm 0:9b334a45a8ff 4127 /* Disable Trigger DMA request */
bogdanm 0:9b334a45a8ff 4128 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
bogdanm 0:9b334a45a8ff 4129
bogdanm 0:9b334a45a8ff 4130 htim->State = HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 4131
bogdanm 0:9b334a45a8ff 4132 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 4133
bogdanm 0:9b334a45a8ff 4134 return HAL_OK;
bogdanm 0:9b334a45a8ff 4135 }
bogdanm 0:9b334a45a8ff 4136
bogdanm 0:9b334a45a8ff 4137 /**
bogdanm 0:9b334a45a8ff 4138 * @brief Read the captured value from Capture Compare unit
bogdanm 0:9b334a45a8ff 4139 * @param htim : TIM handle.
bogdanm 0:9b334a45a8ff 4140 * @param Channel : TIM Channels to be enabled
bogdanm 0:9b334a45a8ff 4141 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 4142 * @arg TIM_CHANNEL_1 : TIM Channel 1 selected
bogdanm 0:9b334a45a8ff 4143 * @arg TIM_CHANNEL_2 : TIM Channel 2 selected
bogdanm 0:9b334a45a8ff 4144 * @arg TIM_CHANNEL_3 : TIM Channel 3 selected
bogdanm 0:9b334a45a8ff 4145 * @arg TIM_CHANNEL_4 : TIM Channel 4 selected
bogdanm 0:9b334a45a8ff 4146 * @retval Captured value
bogdanm 0:9b334a45a8ff 4147 */
bogdanm 0:9b334a45a8ff 4148 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm 0:9b334a45a8ff 4149 {
bogdanm 0:9b334a45a8ff 4150 uint32_t tmpreg = 0;
bogdanm 0:9b334a45a8ff 4151
bogdanm 0:9b334a45a8ff 4152 __HAL_LOCK(htim);
bogdanm 0:9b334a45a8ff 4153
bogdanm 0:9b334a45a8ff 4154 switch (Channel)
bogdanm 0:9b334a45a8ff 4155 {
bogdanm 0:9b334a45a8ff 4156 case TIM_CHANNEL_1:
bogdanm 0:9b334a45a8ff 4157 {
bogdanm 0:9b334a45a8ff 4158 /* Check the parameters */
bogdanm 0:9b334a45a8ff 4159 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4160
bogdanm 0:9b334a45a8ff 4161 /* Return the capture 1 value */
bogdanm 0:9b334a45a8ff 4162 tmpreg = htim->Instance->CCR1;
bogdanm 0:9b334a45a8ff 4163
bogdanm 0:9b334a45a8ff 4164 break;
bogdanm 0:9b334a45a8ff 4165 }
bogdanm 0:9b334a45a8ff 4166 case TIM_CHANNEL_2:
bogdanm 0:9b334a45a8ff 4167 {
bogdanm 0:9b334a45a8ff 4168 /* Check the parameters */
bogdanm 0:9b334a45a8ff 4169 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4170
bogdanm 0:9b334a45a8ff 4171 /* Return the capture 2 value */
bogdanm 0:9b334a45a8ff 4172 tmpreg = htim->Instance->CCR2;
bogdanm 0:9b334a45a8ff 4173
bogdanm 0:9b334a45a8ff 4174 break;
bogdanm 0:9b334a45a8ff 4175 }
bogdanm 0:9b334a45a8ff 4176
bogdanm 0:9b334a45a8ff 4177 case TIM_CHANNEL_3:
bogdanm 0:9b334a45a8ff 4178 {
bogdanm 0:9b334a45a8ff 4179 /* Check the parameters */
bogdanm 0:9b334a45a8ff 4180 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4181
bogdanm 0:9b334a45a8ff 4182 /* Return the capture 3 value */
bogdanm 0:9b334a45a8ff 4183 tmpreg = htim->Instance->CCR3;
bogdanm 0:9b334a45a8ff 4184
bogdanm 0:9b334a45a8ff 4185 break;
bogdanm 0:9b334a45a8ff 4186 }
bogdanm 0:9b334a45a8ff 4187
bogdanm 0:9b334a45a8ff 4188 case TIM_CHANNEL_4:
bogdanm 0:9b334a45a8ff 4189 {
bogdanm 0:9b334a45a8ff 4190 /* Check the parameters */
bogdanm 0:9b334a45a8ff 4191 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4192
bogdanm 0:9b334a45a8ff 4193 /* Return the capture 4 value */
bogdanm 0:9b334a45a8ff 4194 tmpreg = htim->Instance->CCR4;
bogdanm 0:9b334a45a8ff 4195
bogdanm 0:9b334a45a8ff 4196 break;
bogdanm 0:9b334a45a8ff 4197 }
bogdanm 0:9b334a45a8ff 4198
bogdanm 0:9b334a45a8ff 4199 default:
bogdanm 0:9b334a45a8ff 4200 break;
bogdanm 0:9b334a45a8ff 4201 }
bogdanm 0:9b334a45a8ff 4202
bogdanm 0:9b334a45a8ff 4203 __HAL_UNLOCK(htim);
bogdanm 0:9b334a45a8ff 4204 return tmpreg;
bogdanm 0:9b334a45a8ff 4205 }
bogdanm 0:9b334a45a8ff 4206
bogdanm 0:9b334a45a8ff 4207 /**
bogdanm 0:9b334a45a8ff 4208 * @}
bogdanm 0:9b334a45a8ff 4209 */
bogdanm 0:9b334a45a8ff 4210
bogdanm 0:9b334a45a8ff 4211 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
bogdanm 0:9b334a45a8ff 4212 * @brief TIM Callbacks functions
bogdanm 0:9b334a45a8ff 4213 *
bogdanm 0:9b334a45a8ff 4214 @verbatim
bogdanm 0:9b334a45a8ff 4215 ==============================================================================
bogdanm 0:9b334a45a8ff 4216 ##### TIM Callbacks functions #####
bogdanm 0:9b334a45a8ff 4217 ==============================================================================
bogdanm 0:9b334a45a8ff 4218 [..]
bogdanm 0:9b334a45a8ff 4219 This section provides TIM callback functions:
bogdanm 0:9b334a45a8ff 4220 (+) Timer Period elapsed callback
bogdanm 0:9b334a45a8ff 4221 (+) Timer Output Compare callback
bogdanm 0:9b334a45a8ff 4222 (+) Timer Input capture callback
bogdanm 0:9b334a45a8ff 4223 (+) Timer Trigger callback
bogdanm 0:9b334a45a8ff 4224 (+) Timer Error callback
bogdanm 0:9b334a45a8ff 4225
bogdanm 0:9b334a45a8ff 4226 @endverbatim
bogdanm 0:9b334a45a8ff 4227 * @{
bogdanm 0:9b334a45a8ff 4228 */
bogdanm 0:9b334a45a8ff 4229
bogdanm 0:9b334a45a8ff 4230 /**
bogdanm 0:9b334a45a8ff 4231 * @brief Period elapsed callback in non blocking mode
bogdanm 0:9b334a45a8ff 4232 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 4233 * @retval None
bogdanm 0:9b334a45a8ff 4234 */
bogdanm 0:9b334a45a8ff 4235 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 4236 {
bogdanm 0:9b334a45a8ff 4237 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 4238 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 4239 */
bogdanm 0:9b334a45a8ff 4240
bogdanm 0:9b334a45a8ff 4241 }
bogdanm 0:9b334a45a8ff 4242 /**
bogdanm 0:9b334a45a8ff 4243 * @brief Output Compare callback in non blocking mode
bogdanm 0:9b334a45a8ff 4244 * @param htim : TIM OC handle
bogdanm 0:9b334a45a8ff 4245 * @retval None
bogdanm 0:9b334a45a8ff 4246 */
bogdanm 0:9b334a45a8ff 4247 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 4248 {
bogdanm 0:9b334a45a8ff 4249 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 4250 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 4251 */
bogdanm 0:9b334a45a8ff 4252 }
bogdanm 0:9b334a45a8ff 4253 /**
bogdanm 0:9b334a45a8ff 4254 * @brief Input Capture callback in non blocking mode
bogdanm 0:9b334a45a8ff 4255 * @param htim : TIM IC handle
bogdanm 0:9b334a45a8ff 4256 * @retval None
bogdanm 0:9b334a45a8ff 4257 */
bogdanm 0:9b334a45a8ff 4258 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 4259 {
bogdanm 0:9b334a45a8ff 4260 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 4261 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 4262 */
bogdanm 0:9b334a45a8ff 4263 }
bogdanm 0:9b334a45a8ff 4264
bogdanm 0:9b334a45a8ff 4265 /**
bogdanm 0:9b334a45a8ff 4266 * @brief PWM Pulse finished callback in non blocking mode
bogdanm 0:9b334a45a8ff 4267 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 4268 * @retval None
bogdanm 0:9b334a45a8ff 4269 */
bogdanm 0:9b334a45a8ff 4270 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 4271 {
bogdanm 0:9b334a45a8ff 4272 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 4273 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 4274 */
bogdanm 0:9b334a45a8ff 4275 }
bogdanm 0:9b334a45a8ff 4276
bogdanm 0:9b334a45a8ff 4277 /**
bogdanm 0:9b334a45a8ff 4278 * @brief Hall Trigger detection callback in non blocking mode
bogdanm 0:9b334a45a8ff 4279 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 4280 * @retval None
bogdanm 0:9b334a45a8ff 4281 */
bogdanm 0:9b334a45a8ff 4282 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 4283 {
bogdanm 0:9b334a45a8ff 4284 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 4285 the HAL_TIM_TriggerCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 4286 */
bogdanm 0:9b334a45a8ff 4287 }
bogdanm 0:9b334a45a8ff 4288
bogdanm 0:9b334a45a8ff 4289 /**
bogdanm 0:9b334a45a8ff 4290 * @brief Timer error callback in non blocking mode
bogdanm 0:9b334a45a8ff 4291 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 4292 * @retval None
bogdanm 0:9b334a45a8ff 4293 */
bogdanm 0:9b334a45a8ff 4294 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 4295 {
bogdanm 0:9b334a45a8ff 4296 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 4297 the HAL_TIM_ErrorCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 4298 */
bogdanm 0:9b334a45a8ff 4299 }
bogdanm 0:9b334a45a8ff 4300
bogdanm 0:9b334a45a8ff 4301 /**
bogdanm 0:9b334a45a8ff 4302 * @}
bogdanm 0:9b334a45a8ff 4303 */
bogdanm 0:9b334a45a8ff 4304
bogdanm 0:9b334a45a8ff 4305 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
bogdanm 0:9b334a45a8ff 4306 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 4307 *
bogdanm 0:9b334a45a8ff 4308 @verbatim
bogdanm 0:9b334a45a8ff 4309 ==============================================================================
bogdanm 0:9b334a45a8ff 4310 ##### Peripheral State functions #####
bogdanm 0:9b334a45a8ff 4311 ==============================================================================
bogdanm 0:9b334a45a8ff 4312 [..]
bogdanm 0:9b334a45a8ff 4313 This subsection permit to get in run-time the status of the peripheral
bogdanm 0:9b334a45a8ff 4314 and the data flow.
bogdanm 0:9b334a45a8ff 4315
bogdanm 0:9b334a45a8ff 4316 @endverbatim
bogdanm 0:9b334a45a8ff 4317 * @{
bogdanm 0:9b334a45a8ff 4318 */
bogdanm 0:9b334a45a8ff 4319
bogdanm 0:9b334a45a8ff 4320 /**
bogdanm 0:9b334a45a8ff 4321 * @brief Return the TIM Base state
bogdanm 0:9b334a45a8ff 4322 * @param htim : TIM Base handle
bogdanm 0:9b334a45a8ff 4323 * @retval HAL state
bogdanm 0:9b334a45a8ff 4324 */
bogdanm 0:9b334a45a8ff 4325 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 4326 {
bogdanm 0:9b334a45a8ff 4327 return htim->State;
bogdanm 0:9b334a45a8ff 4328 }
bogdanm 0:9b334a45a8ff 4329
bogdanm 0:9b334a45a8ff 4330 /**
bogdanm 0:9b334a45a8ff 4331 * @brief Return the TIM OC state
bogdanm 0:9b334a45a8ff 4332 * @param htim : TIM Ouput Compare handle
bogdanm 0:9b334a45a8ff 4333 * @retval HAL state
bogdanm 0:9b334a45a8ff 4334 */
bogdanm 0:9b334a45a8ff 4335 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 4336 {
bogdanm 0:9b334a45a8ff 4337 return htim->State;
bogdanm 0:9b334a45a8ff 4338 }
bogdanm 0:9b334a45a8ff 4339
bogdanm 0:9b334a45a8ff 4340 /**
bogdanm 0:9b334a45a8ff 4341 * @brief Return the TIM PWM state
bogdanm 0:9b334a45a8ff 4342 * @param htim : TIM handle
bogdanm 0:9b334a45a8ff 4343 * @retval HAL state
bogdanm 0:9b334a45a8ff 4344 */
bogdanm 0:9b334a45a8ff 4345 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 4346 {
bogdanm 0:9b334a45a8ff 4347 return htim->State;
bogdanm 0:9b334a45a8ff 4348 }
bogdanm 0:9b334a45a8ff 4349
bogdanm 0:9b334a45a8ff 4350 /**
bogdanm 0:9b334a45a8ff 4351 * @brief Return the TIM Input Capture state
bogdanm 0:9b334a45a8ff 4352 * @param htim : TIM IC handle
bogdanm 0:9b334a45a8ff 4353 * @retval HAL state
bogdanm 0:9b334a45a8ff 4354 */
bogdanm 0:9b334a45a8ff 4355 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 4356 {
bogdanm 0:9b334a45a8ff 4357 return htim->State;
bogdanm 0:9b334a45a8ff 4358 }
bogdanm 0:9b334a45a8ff 4359
bogdanm 0:9b334a45a8ff 4360 /**
bogdanm 0:9b334a45a8ff 4361 * @brief Return the TIM One Pulse Mode state
bogdanm 0:9b334a45a8ff 4362 * @param htim : TIM OPM handle
bogdanm 0:9b334a45a8ff 4363 * @retval HAL state
bogdanm 0:9b334a45a8ff 4364 */
bogdanm 0:9b334a45a8ff 4365 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 4366 {
bogdanm 0:9b334a45a8ff 4367 return htim->State;
bogdanm 0:9b334a45a8ff 4368 }
bogdanm 0:9b334a45a8ff 4369
bogdanm 0:9b334a45a8ff 4370 /**
bogdanm 0:9b334a45a8ff 4371 * @brief Return the TIM Encoder Mode state
bogdanm 0:9b334a45a8ff 4372 * @param htim : TIM Encoder handle
bogdanm 0:9b334a45a8ff 4373 * @retval HAL state
bogdanm 0:9b334a45a8ff 4374 */
bogdanm 0:9b334a45a8ff 4375 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
bogdanm 0:9b334a45a8ff 4376 {
bogdanm 0:9b334a45a8ff 4377 return htim->State;
bogdanm 0:9b334a45a8ff 4378 }
bogdanm 0:9b334a45a8ff 4379
bogdanm 0:9b334a45a8ff 4380 /**
bogdanm 0:9b334a45a8ff 4381 * @}
bogdanm 0:9b334a45a8ff 4382 */
bogdanm 0:9b334a45a8ff 4383
bogdanm 0:9b334a45a8ff 4384 /**
bogdanm 0:9b334a45a8ff 4385 * @}
bogdanm 0:9b334a45a8ff 4386 */
bogdanm 0:9b334a45a8ff 4387
bogdanm 0:9b334a45a8ff 4388 /** @addtogroup TIM_Private_Functions TIM_Private_Functions
bogdanm 0:9b334a45a8ff 4389 * @{
bogdanm 0:9b334a45a8ff 4390 */
bogdanm 0:9b334a45a8ff 4391
bogdanm 0:9b334a45a8ff 4392 /**
bogdanm 0:9b334a45a8ff 4393 * @brief TIM DMA error callback
bogdanm 0:9b334a45a8ff 4394 * @param hdma : pointer to DMA handle.
bogdanm 0:9b334a45a8ff 4395 * @retval None
bogdanm 0:9b334a45a8ff 4396 */
bogdanm 0:9b334a45a8ff 4397 void TIM_DMAError(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 4398 {
bogdanm 0:9b334a45a8ff 4399 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm 0:9b334a45a8ff 4400
bogdanm 0:9b334a45a8ff 4401 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 4402
bogdanm 0:9b334a45a8ff 4403 HAL_TIM_ErrorCallback(htim);
bogdanm 0:9b334a45a8ff 4404 }
bogdanm 0:9b334a45a8ff 4405
bogdanm 0:9b334a45a8ff 4406 /**
bogdanm 0:9b334a45a8ff 4407 * @brief TIM DMA Delay Pulse complete callback.
bogdanm 0:9b334a45a8ff 4408 * @param hdma : pointer to DMA handle.
bogdanm 0:9b334a45a8ff 4409 * @retval None
bogdanm 0:9b334a45a8ff 4410 */
bogdanm 0:9b334a45a8ff 4411 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 4412 {
bogdanm 0:9b334a45a8ff 4413 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm 0:9b334a45a8ff 4414
bogdanm 0:9b334a45a8ff 4415 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 4416
bogdanm 0:9b334a45a8ff 4417 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm 0:9b334a45a8ff 4418 {
bogdanm 0:9b334a45a8ff 4419 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm 0:9b334a45a8ff 4420 }
bogdanm 0:9b334a45a8ff 4421 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm 0:9b334a45a8ff 4422 {
bogdanm 0:9b334a45a8ff 4423 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm 0:9b334a45a8ff 4424 }
bogdanm 0:9b334a45a8ff 4425 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm 0:9b334a45a8ff 4426 {
bogdanm 0:9b334a45a8ff 4427 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm 0:9b334a45a8ff 4428 }
bogdanm 0:9b334a45a8ff 4429 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm 0:9b334a45a8ff 4430 {
bogdanm 0:9b334a45a8ff 4431 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm 0:9b334a45a8ff 4432 }
bogdanm 0:9b334a45a8ff 4433
bogdanm 0:9b334a45a8ff 4434 HAL_TIM_PWM_PulseFinishedCallback(htim);
bogdanm 0:9b334a45a8ff 4435
bogdanm 0:9b334a45a8ff 4436 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm 0:9b334a45a8ff 4437 }
bogdanm 0:9b334a45a8ff 4438 /**
bogdanm 0:9b334a45a8ff 4439 * @brief TIM DMA Capture complete callback.
bogdanm 0:9b334a45a8ff 4440 * @param hdma : pointer to DMA handle.
bogdanm 0:9b334a45a8ff 4441 * @retval None
bogdanm 0:9b334a45a8ff 4442 */
bogdanm 0:9b334a45a8ff 4443 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 4444 {
bogdanm 0:9b334a45a8ff 4445 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm 0:9b334a45a8ff 4446
bogdanm 0:9b334a45a8ff 4447 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 4448
bogdanm 0:9b334a45a8ff 4449 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
bogdanm 0:9b334a45a8ff 4450 {
bogdanm 0:9b334a45a8ff 4451 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
bogdanm 0:9b334a45a8ff 4452 }
bogdanm 0:9b334a45a8ff 4453 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
bogdanm 0:9b334a45a8ff 4454 {
bogdanm 0:9b334a45a8ff 4455 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
bogdanm 0:9b334a45a8ff 4456 }
bogdanm 0:9b334a45a8ff 4457 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
bogdanm 0:9b334a45a8ff 4458 {
bogdanm 0:9b334a45a8ff 4459 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
bogdanm 0:9b334a45a8ff 4460 }
bogdanm 0:9b334a45a8ff 4461 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
bogdanm 0:9b334a45a8ff 4462 {
bogdanm 0:9b334a45a8ff 4463 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
bogdanm 0:9b334a45a8ff 4464 }
bogdanm 0:9b334a45a8ff 4465
bogdanm 0:9b334a45a8ff 4466 HAL_TIM_IC_CaptureCallback(htim);
bogdanm 0:9b334a45a8ff 4467
bogdanm 0:9b334a45a8ff 4468 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
bogdanm 0:9b334a45a8ff 4469 }
bogdanm 0:9b334a45a8ff 4470
bogdanm 0:9b334a45a8ff 4471 /**
bogdanm 0:9b334a45a8ff 4472 * @brief TIM DMA Period Elapse complete callback.
bogdanm 0:9b334a45a8ff 4473 * @param hdma : pointer to DMA handle.
bogdanm 0:9b334a45a8ff 4474 * @retval None
bogdanm 0:9b334a45a8ff 4475 */
bogdanm 0:9b334a45a8ff 4476 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 4477 {
bogdanm 0:9b334a45a8ff 4478 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm 0:9b334a45a8ff 4479
bogdanm 0:9b334a45a8ff 4480 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 4481
bogdanm 0:9b334a45a8ff 4482 HAL_TIM_PeriodElapsedCallback(htim);
bogdanm 0:9b334a45a8ff 4483 }
bogdanm 0:9b334a45a8ff 4484
bogdanm 0:9b334a45a8ff 4485 /**
bogdanm 0:9b334a45a8ff 4486 * @brief TIM DMA Trigger callback.
bogdanm 0:9b334a45a8ff 4487 * @param hdma : pointer to DMA handle.
bogdanm 0:9b334a45a8ff 4488 * @retval None
bogdanm 0:9b334a45a8ff 4489 */
bogdanm 0:9b334a45a8ff 4490 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 4491 {
bogdanm 0:9b334a45a8ff 4492 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm 0:9b334a45a8ff 4493
bogdanm 0:9b334a45a8ff 4494 htim->State= HAL_TIM_STATE_READY;
bogdanm 0:9b334a45a8ff 4495
bogdanm 0:9b334a45a8ff 4496 HAL_TIM_TriggerCallback(htim);
bogdanm 0:9b334a45a8ff 4497 }
bogdanm 0:9b334a45a8ff 4498
bogdanm 0:9b334a45a8ff 4499 /**
bogdanm 0:9b334a45a8ff 4500 * @brief Time Base configuration
bogdanm 0:9b334a45a8ff 4501 * @param TIMx : TIM periheral
bogdanm 0:9b334a45a8ff 4502 * @param Structure : TIM Base configuration structure
bogdanm 0:9b334a45a8ff 4503 * @retval None
bogdanm 0:9b334a45a8ff 4504 */
bogdanm 0:9b334a45a8ff 4505 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
bogdanm 0:9b334a45a8ff 4506 {
bogdanm 0:9b334a45a8ff 4507 uint32_t tmpcr1 = 0;
bogdanm 0:9b334a45a8ff 4508 tmpcr1 = TIMx->CR1;
bogdanm 0:9b334a45a8ff 4509
bogdanm 0:9b334a45a8ff 4510 /* Set TIM Time Base Unit parameters ---------------------------------------*/
bogdanm 0:9b334a45a8ff 4511 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
bogdanm 0:9b334a45a8ff 4512 {
bogdanm 0:9b334a45a8ff 4513 /* Select the Counter Mode */
bogdanm 0:9b334a45a8ff 4514 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
bogdanm 0:9b334a45a8ff 4515 tmpcr1 |= Structure->CounterMode;
bogdanm 0:9b334a45a8ff 4516 }
bogdanm 0:9b334a45a8ff 4517
bogdanm 0:9b334a45a8ff 4518 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
bogdanm 0:9b334a45a8ff 4519 {
bogdanm 0:9b334a45a8ff 4520 /* Set the clock division */
bogdanm 0:9b334a45a8ff 4521 tmpcr1 &= ~TIM_CR1_CKD;
bogdanm 0:9b334a45a8ff 4522 tmpcr1 |= (uint32_t)Structure->ClockDivision;
bogdanm 0:9b334a45a8ff 4523 }
bogdanm 0:9b334a45a8ff 4524
bogdanm 0:9b334a45a8ff 4525 TIMx->CR1 = tmpcr1;
bogdanm 0:9b334a45a8ff 4526
bogdanm 0:9b334a45a8ff 4527 /* Set the Autoreload value */
bogdanm 0:9b334a45a8ff 4528 TIMx->ARR = (uint32_t)Structure->Period ;
bogdanm 0:9b334a45a8ff 4529
bogdanm 0:9b334a45a8ff 4530 /* Set the Prescaler value */
bogdanm 0:9b334a45a8ff 4531 TIMx->PSC = (uint32_t)Structure->Prescaler;
bogdanm 0:9b334a45a8ff 4532
bogdanm 0:9b334a45a8ff 4533 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
bogdanm 0:9b334a45a8ff 4534 {
bogdanm 0:9b334a45a8ff 4535 /* Set the Repetition Counter value */
bogdanm 0:9b334a45a8ff 4536 TIMx->RCR = Structure->RepetitionCounter;
bogdanm 0:9b334a45a8ff 4537 }
bogdanm 0:9b334a45a8ff 4538
bogdanm 0:9b334a45a8ff 4539 /* Generate an update event to reload the Prescaler
bogdanm 0:9b334a45a8ff 4540 and the repetition counter(only for TIM1 and TIM8) value immediatly */
bogdanm 0:9b334a45a8ff 4541 TIMx->EGR = TIM_EGR_UG;
bogdanm 0:9b334a45a8ff 4542 }
bogdanm 0:9b334a45a8ff 4543
bogdanm 0:9b334a45a8ff 4544 /**
bogdanm 0:9b334a45a8ff 4545 * @brief Time Ouput Compare 1 configuration
bogdanm 0:9b334a45a8ff 4546 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 4547 * @param OC_Config : The ouput configuration structure
bogdanm 0:9b334a45a8ff 4548 * @retval None
bogdanm 0:9b334a45a8ff 4549 */
bogdanm 0:9b334a45a8ff 4550 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
bogdanm 0:9b334a45a8ff 4551 {
bogdanm 0:9b334a45a8ff 4552 uint32_t tmpccmrx = 0;
bogdanm 0:9b334a45a8ff 4553 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 4554 uint32_t tmpcr2 = 0;
bogdanm 0:9b334a45a8ff 4555
bogdanm 0:9b334a45a8ff 4556 /* Disable the Channel 1: Reset the CC1E Bit */
bogdanm 0:9b334a45a8ff 4557 TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm 0:9b334a45a8ff 4558
bogdanm 0:9b334a45a8ff 4559 /* Get the TIMx CCER register value */
bogdanm 0:9b334a45a8ff 4560 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 4561 /* Get the TIMx CR2 register value */
bogdanm 0:9b334a45a8ff 4562 tmpcr2 = TIMx->CR2;
bogdanm 0:9b334a45a8ff 4563
bogdanm 0:9b334a45a8ff 4564 /* Get the TIMx CCMR1 register value */
bogdanm 0:9b334a45a8ff 4565 tmpccmrx = TIMx->CCMR1;
bogdanm 0:9b334a45a8ff 4566
bogdanm 0:9b334a45a8ff 4567 /* Reset the Output Compare Mode Bits */
bogdanm 0:9b334a45a8ff 4568 tmpccmrx &= ~TIM_CCMR1_OC1M;
bogdanm 0:9b334a45a8ff 4569 tmpccmrx &= ~TIM_CCMR1_CC1S;
bogdanm 0:9b334a45a8ff 4570 /* Select the Output Compare Mode */
bogdanm 0:9b334a45a8ff 4571 tmpccmrx |= OC_Config->OCMode;
bogdanm 0:9b334a45a8ff 4572
bogdanm 0:9b334a45a8ff 4573 /* Reset the Output Polarity level */
bogdanm 0:9b334a45a8ff 4574 tmpccer &= ~TIM_CCER_CC1P;
bogdanm 0:9b334a45a8ff 4575 /* Set the Output Compare Polarity */
bogdanm 0:9b334a45a8ff 4576 tmpccer |= OC_Config->OCPolarity;
bogdanm 0:9b334a45a8ff 4577
bogdanm 0:9b334a45a8ff 4578 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
bogdanm 0:9b334a45a8ff 4579 {
bogdanm 0:9b334a45a8ff 4580 /* Check parameters */
bogdanm 0:9b334a45a8ff 4581 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm 0:9b334a45a8ff 4582
bogdanm 0:9b334a45a8ff 4583 /* Reset the Output N Polarity level */
bogdanm 0:9b334a45a8ff 4584 tmpccer &= ~TIM_CCER_CC1NP;
bogdanm 0:9b334a45a8ff 4585 /* Set the Output N Polarity */
bogdanm 0:9b334a45a8ff 4586 tmpccer |= OC_Config->OCNPolarity;
bogdanm 0:9b334a45a8ff 4587 /* Reset the Output N State */
bogdanm 0:9b334a45a8ff 4588 tmpccer &= ~TIM_CCER_CC1NE;
bogdanm 0:9b334a45a8ff 4589 }
bogdanm 0:9b334a45a8ff 4590
bogdanm 0:9b334a45a8ff 4591 if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm 0:9b334a45a8ff 4592 {
bogdanm 0:9b334a45a8ff 4593 /* Check parameters */
bogdanm 0:9b334a45a8ff 4594 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm 0:9b334a45a8ff 4595 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm 0:9b334a45a8ff 4596
bogdanm 0:9b334a45a8ff 4597 /* Reset the Output Compare and Output Compare N IDLE State */
bogdanm 0:9b334a45a8ff 4598 tmpcr2 &= ~TIM_CR2_OIS1;
bogdanm 0:9b334a45a8ff 4599 tmpcr2 &= ~TIM_CR2_OIS1N;
bogdanm 0:9b334a45a8ff 4600 /* Set the Output Idle state */
bogdanm 0:9b334a45a8ff 4601 tmpcr2 |= OC_Config->OCIdleState;
bogdanm 0:9b334a45a8ff 4602 /* Set the Output N Idle state */
bogdanm 0:9b334a45a8ff 4603 tmpcr2 |= OC_Config->OCNIdleState;
bogdanm 0:9b334a45a8ff 4604 }
bogdanm 0:9b334a45a8ff 4605 /* Write to TIMx CR2 */
bogdanm 0:9b334a45a8ff 4606 TIMx->CR2 = tmpcr2;
bogdanm 0:9b334a45a8ff 4607
bogdanm 0:9b334a45a8ff 4608 /* Write to TIMx CCMR1 */
bogdanm 0:9b334a45a8ff 4609 TIMx->CCMR1 = tmpccmrx;
bogdanm 0:9b334a45a8ff 4610
bogdanm 0:9b334a45a8ff 4611 /* Set the Capture Compare Register value */
bogdanm 0:9b334a45a8ff 4612 TIMx->CCR1 = OC_Config->Pulse;
bogdanm 0:9b334a45a8ff 4613
bogdanm 0:9b334a45a8ff 4614 /* Write to TIMx CCER */
bogdanm 0:9b334a45a8ff 4615 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 4616 }
bogdanm 0:9b334a45a8ff 4617
bogdanm 0:9b334a45a8ff 4618 /**
bogdanm 0:9b334a45a8ff 4619 * @brief Time Ouput Compare 2 configuration
bogdanm 0:9b334a45a8ff 4620 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 4621 * @param OC_Config : The ouput configuration structure
bogdanm 0:9b334a45a8ff 4622 * @retval None
bogdanm 0:9b334a45a8ff 4623 */
bogdanm 0:9b334a45a8ff 4624 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
bogdanm 0:9b334a45a8ff 4625 {
bogdanm 0:9b334a45a8ff 4626 uint32_t tmpccmrx = 0;
bogdanm 0:9b334a45a8ff 4627 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 4628 uint32_t tmpcr2 = 0;
bogdanm 0:9b334a45a8ff 4629
bogdanm 0:9b334a45a8ff 4630 /* Disable the Channel 2: Reset the CC2E Bit */
bogdanm 0:9b334a45a8ff 4631 TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm 0:9b334a45a8ff 4632
bogdanm 0:9b334a45a8ff 4633 /* Get the TIMx CCER register value */
bogdanm 0:9b334a45a8ff 4634 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 4635 /* Get the TIMx CR2 register value */
bogdanm 0:9b334a45a8ff 4636 tmpcr2 = TIMx->CR2;
bogdanm 0:9b334a45a8ff 4637
bogdanm 0:9b334a45a8ff 4638 /* Get the TIMx CCMR1 register value */
bogdanm 0:9b334a45a8ff 4639 tmpccmrx = TIMx->CCMR1;
bogdanm 0:9b334a45a8ff 4640
bogdanm 0:9b334a45a8ff 4641 /* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm 0:9b334a45a8ff 4642 tmpccmrx &= ~TIM_CCMR1_OC2M;
bogdanm 0:9b334a45a8ff 4643 tmpccmrx &= ~TIM_CCMR1_CC2S;
bogdanm 0:9b334a45a8ff 4644
bogdanm 0:9b334a45a8ff 4645 /* Select the Output Compare Mode */
bogdanm 0:9b334a45a8ff 4646 tmpccmrx |= (OC_Config->OCMode << 8);
bogdanm 0:9b334a45a8ff 4647
bogdanm 0:9b334a45a8ff 4648 /* Reset the Output Polarity level */
bogdanm 0:9b334a45a8ff 4649 tmpccer &= ~TIM_CCER_CC2P;
bogdanm 0:9b334a45a8ff 4650 /* Set the Output Compare Polarity */
bogdanm 0:9b334a45a8ff 4651 tmpccer |= (OC_Config->OCPolarity << 4);
bogdanm 0:9b334a45a8ff 4652
bogdanm 0:9b334a45a8ff 4653 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
bogdanm 0:9b334a45a8ff 4654 {
bogdanm 0:9b334a45a8ff 4655 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm 0:9b334a45a8ff 4656 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm 0:9b334a45a8ff 4657 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm 0:9b334a45a8ff 4658
bogdanm 0:9b334a45a8ff 4659 /* Reset the Output N Polarity level */
bogdanm 0:9b334a45a8ff 4660 tmpccer &= ~TIM_CCER_CC2NP;
bogdanm 0:9b334a45a8ff 4661 /* Set the Output N Polarity */
bogdanm 0:9b334a45a8ff 4662 tmpccer |= (OC_Config->OCNPolarity << 4);
bogdanm 0:9b334a45a8ff 4663 /* Reset the Output N State */
bogdanm 0:9b334a45a8ff 4664 tmpccer &= ~TIM_CCER_CC2NE;
bogdanm 0:9b334a45a8ff 4665
bogdanm 0:9b334a45a8ff 4666 }
bogdanm 0:9b334a45a8ff 4667
bogdanm 0:9b334a45a8ff 4668 if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm 0:9b334a45a8ff 4669 {
bogdanm 0:9b334a45a8ff 4670 /* Check parameters */
bogdanm 0:9b334a45a8ff 4671 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm 0:9b334a45a8ff 4672 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm 0:9b334a45a8ff 4673
bogdanm 0:9b334a45a8ff 4674 /* Reset the Output Compare and Output Compare N IDLE State */
bogdanm 0:9b334a45a8ff 4675 tmpcr2 &= ~TIM_CR2_OIS2;
bogdanm 0:9b334a45a8ff 4676 tmpcr2 &= ~TIM_CR2_OIS2N;
bogdanm 0:9b334a45a8ff 4677 /* Set the Output Idle state */
bogdanm 0:9b334a45a8ff 4678 tmpcr2 |= (OC_Config->OCIdleState << 2);
bogdanm 0:9b334a45a8ff 4679 /* Set the Output N Idle state */
bogdanm 0:9b334a45a8ff 4680 tmpcr2 |= (OC_Config->OCNIdleState << 2);
bogdanm 0:9b334a45a8ff 4681 }
bogdanm 0:9b334a45a8ff 4682
bogdanm 0:9b334a45a8ff 4683 /* Write to TIMx CR2 */
bogdanm 0:9b334a45a8ff 4684 TIMx->CR2 = tmpcr2;
bogdanm 0:9b334a45a8ff 4685
bogdanm 0:9b334a45a8ff 4686 /* Write to TIMx CCMR1 */
bogdanm 0:9b334a45a8ff 4687 TIMx->CCMR1 = tmpccmrx;
bogdanm 0:9b334a45a8ff 4688
bogdanm 0:9b334a45a8ff 4689 /* Set the Capture Compare Register value */
bogdanm 0:9b334a45a8ff 4690 TIMx->CCR2 = OC_Config->Pulse;
bogdanm 0:9b334a45a8ff 4691
bogdanm 0:9b334a45a8ff 4692 /* Write to TIMx CCER */
bogdanm 0:9b334a45a8ff 4693 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 4694 }
bogdanm 0:9b334a45a8ff 4695
bogdanm 0:9b334a45a8ff 4696 /**
bogdanm 0:9b334a45a8ff 4697 * @brief Time Ouput Compare 3 configuration
bogdanm 0:9b334a45a8ff 4698 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 4699 * @param OC_Config : The ouput configuration structure
bogdanm 0:9b334a45a8ff 4700 * @retval None
bogdanm 0:9b334a45a8ff 4701 */
bogdanm 0:9b334a45a8ff 4702 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
bogdanm 0:9b334a45a8ff 4703 {
bogdanm 0:9b334a45a8ff 4704 uint32_t tmpccmrx = 0;
bogdanm 0:9b334a45a8ff 4705 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 4706 uint32_t tmpcr2 = 0;
bogdanm 0:9b334a45a8ff 4707
bogdanm 0:9b334a45a8ff 4708 /* Disable the Channel 3: Reset the CC2E Bit */
bogdanm 0:9b334a45a8ff 4709 TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm 0:9b334a45a8ff 4710
bogdanm 0:9b334a45a8ff 4711 /* Get the TIMx CCER register value */
bogdanm 0:9b334a45a8ff 4712 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 4713 /* Get the TIMx CR2 register value */
bogdanm 0:9b334a45a8ff 4714 tmpcr2 = TIMx->CR2;
bogdanm 0:9b334a45a8ff 4715
bogdanm 0:9b334a45a8ff 4716 /* Get the TIMx CCMR2 register value */
bogdanm 0:9b334a45a8ff 4717 tmpccmrx = TIMx->CCMR2;
bogdanm 0:9b334a45a8ff 4718
bogdanm 0:9b334a45a8ff 4719 /* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm 0:9b334a45a8ff 4720 tmpccmrx &= ~TIM_CCMR2_OC3M;
bogdanm 0:9b334a45a8ff 4721 tmpccmrx &= ~TIM_CCMR2_CC3S;
bogdanm 0:9b334a45a8ff 4722 /* Select the Output Compare Mode */
bogdanm 0:9b334a45a8ff 4723 tmpccmrx |= OC_Config->OCMode;
bogdanm 0:9b334a45a8ff 4724
bogdanm 0:9b334a45a8ff 4725 /* Reset the Output Polarity level */
bogdanm 0:9b334a45a8ff 4726 tmpccer &= ~TIM_CCER_CC3P;
bogdanm 0:9b334a45a8ff 4727 /* Set the Output Compare Polarity */
bogdanm 0:9b334a45a8ff 4728 tmpccer |= (OC_Config->OCPolarity << 8);
bogdanm 0:9b334a45a8ff 4729
bogdanm 0:9b334a45a8ff 4730 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
bogdanm 0:9b334a45a8ff 4731 {
bogdanm 0:9b334a45a8ff 4732 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
bogdanm 0:9b334a45a8ff 4733 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm 0:9b334a45a8ff 4734 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm 0:9b334a45a8ff 4735
bogdanm 0:9b334a45a8ff 4736 /* Reset the Output N Polarity level */
bogdanm 0:9b334a45a8ff 4737 tmpccer &= ~TIM_CCER_CC3NP;
bogdanm 0:9b334a45a8ff 4738 /* Set the Output N Polarity */
bogdanm 0:9b334a45a8ff 4739 tmpccer |= (OC_Config->OCNPolarity << 8);
bogdanm 0:9b334a45a8ff 4740 /* Reset the Output N State */
bogdanm 0:9b334a45a8ff 4741 tmpccer &= ~TIM_CCER_CC3NE;
bogdanm 0:9b334a45a8ff 4742 }
bogdanm 0:9b334a45a8ff 4743
bogdanm 0:9b334a45a8ff 4744 if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm 0:9b334a45a8ff 4745 {
bogdanm 0:9b334a45a8ff 4746 /* Check parameters */
bogdanm 0:9b334a45a8ff 4747 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
bogdanm 0:9b334a45a8ff 4748 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm 0:9b334a45a8ff 4749
bogdanm 0:9b334a45a8ff 4750 /* Reset the Output Compare and Output Compare N IDLE State */
bogdanm 0:9b334a45a8ff 4751 tmpcr2 &= ~TIM_CR2_OIS3;
bogdanm 0:9b334a45a8ff 4752 tmpcr2 &= ~TIM_CR2_OIS3N;
bogdanm 0:9b334a45a8ff 4753 /* Set the Output Idle state */
bogdanm 0:9b334a45a8ff 4754 tmpcr2 |= (OC_Config->OCIdleState << 4);
bogdanm 0:9b334a45a8ff 4755 /* Set the Output N Idle state */
bogdanm 0:9b334a45a8ff 4756 tmpcr2 |= (OC_Config->OCNIdleState << 4);
bogdanm 0:9b334a45a8ff 4757 }
bogdanm 0:9b334a45a8ff 4758
bogdanm 0:9b334a45a8ff 4759 /* Write to TIMx CR2 */
bogdanm 0:9b334a45a8ff 4760 TIMx->CR2 = tmpcr2;
bogdanm 0:9b334a45a8ff 4761
bogdanm 0:9b334a45a8ff 4762 /* Write to TIMx CCMR2 */
bogdanm 0:9b334a45a8ff 4763 TIMx->CCMR2 = tmpccmrx;
bogdanm 0:9b334a45a8ff 4764
bogdanm 0:9b334a45a8ff 4765 /* Set the Capture Compare Register value */
bogdanm 0:9b334a45a8ff 4766 TIMx->CCR3 = OC_Config->Pulse;
bogdanm 0:9b334a45a8ff 4767
bogdanm 0:9b334a45a8ff 4768 /* Write to TIMx CCER */
bogdanm 0:9b334a45a8ff 4769 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 4770 }
bogdanm 0:9b334a45a8ff 4771
bogdanm 0:9b334a45a8ff 4772 /**
bogdanm 0:9b334a45a8ff 4773 * @brief Time Ouput Compare 4 configuration
bogdanm 0:9b334a45a8ff 4774 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 4775 * @param OC_Config : The ouput configuration structure
bogdanm 0:9b334a45a8ff 4776 * @retval None
bogdanm 0:9b334a45a8ff 4777 */
bogdanm 0:9b334a45a8ff 4778 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
bogdanm 0:9b334a45a8ff 4779 {
bogdanm 0:9b334a45a8ff 4780 uint32_t tmpccmrx = 0;
bogdanm 0:9b334a45a8ff 4781 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 4782 uint32_t tmpcr2 = 0;
bogdanm 0:9b334a45a8ff 4783
bogdanm 0:9b334a45a8ff 4784 /* Disable the Channel 4: Reset the CC4E Bit */
bogdanm 0:9b334a45a8ff 4785 TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm 0:9b334a45a8ff 4786
bogdanm 0:9b334a45a8ff 4787 /* Get the TIMx CCER register value */
bogdanm 0:9b334a45a8ff 4788 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 4789 /* Get the TIMx CR2 register value */
bogdanm 0:9b334a45a8ff 4790 tmpcr2 = TIMx->CR2;
bogdanm 0:9b334a45a8ff 4791
bogdanm 0:9b334a45a8ff 4792 /* Get the TIMx CCMR2 register value */
bogdanm 0:9b334a45a8ff 4793 tmpccmrx = TIMx->CCMR2;
bogdanm 0:9b334a45a8ff 4794
bogdanm 0:9b334a45a8ff 4795 /* Reset the Output Compare mode and Capture/Compare selection Bits */
bogdanm 0:9b334a45a8ff 4796 tmpccmrx &= ~TIM_CCMR2_OC4M;
bogdanm 0:9b334a45a8ff 4797 tmpccmrx &= ~TIM_CCMR2_CC4S;
bogdanm 0:9b334a45a8ff 4798
bogdanm 0:9b334a45a8ff 4799 /* Select the Output Compare Mode */
bogdanm 0:9b334a45a8ff 4800 tmpccmrx |= (OC_Config->OCMode << 8);
bogdanm 0:9b334a45a8ff 4801
bogdanm 0:9b334a45a8ff 4802 /* Reset the Output Polarity level */
bogdanm 0:9b334a45a8ff 4803 tmpccer &= ~TIM_CCER_CC4P;
bogdanm 0:9b334a45a8ff 4804 /* Set the Output Compare Polarity */
bogdanm 0:9b334a45a8ff 4805 tmpccer |= (OC_Config->OCPolarity << 12);
bogdanm 0:9b334a45a8ff 4806
bogdanm 0:9b334a45a8ff 4807 if(IS_TIM_BREAK_INSTANCE(TIMx))
bogdanm 0:9b334a45a8ff 4808 {
bogdanm 0:9b334a45a8ff 4809 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
bogdanm 0:9b334a45a8ff 4810
bogdanm 0:9b334a45a8ff 4811 /* Reset the Output Compare IDLE State */
bogdanm 0:9b334a45a8ff 4812 tmpcr2 &= ~TIM_CR2_OIS4;
bogdanm 0:9b334a45a8ff 4813 /* Set the Output Idle state */
bogdanm 0:9b334a45a8ff 4814 tmpcr2 |= (OC_Config->OCIdleState << 6);
bogdanm 0:9b334a45a8ff 4815 }
bogdanm 0:9b334a45a8ff 4816
bogdanm 0:9b334a45a8ff 4817 /* Write to TIMx CR2 */
bogdanm 0:9b334a45a8ff 4818 TIMx->CR2 = tmpcr2;
bogdanm 0:9b334a45a8ff 4819
bogdanm 0:9b334a45a8ff 4820 /* Write to TIMx CCMR2 */
bogdanm 0:9b334a45a8ff 4821 TIMx->CCMR2 = tmpccmrx;
bogdanm 0:9b334a45a8ff 4822
bogdanm 0:9b334a45a8ff 4823 /* Set the Capture Compare Register value */
bogdanm 0:9b334a45a8ff 4824 TIMx->CCR4 = OC_Config->Pulse;
bogdanm 0:9b334a45a8ff 4825
bogdanm 0:9b334a45a8ff 4826 /* Write to TIMx CCER */
bogdanm 0:9b334a45a8ff 4827 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 4828 }
bogdanm 0:9b334a45a8ff 4829
bogdanm 0:9b334a45a8ff 4830 void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
bogdanm 0:9b334a45a8ff 4831 TIM_SlaveConfigTypeDef * sSlaveConfig)
bogdanm 0:9b334a45a8ff 4832 {
bogdanm 0:9b334a45a8ff 4833 uint32_t tmpsmcr = 0;
bogdanm 0:9b334a45a8ff 4834 uint32_t tmpccmr1 = 0;
bogdanm 0:9b334a45a8ff 4835 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 4836
bogdanm 0:9b334a45a8ff 4837 /* Get the TIMx SMCR register value */
bogdanm 0:9b334a45a8ff 4838 tmpsmcr = htim->Instance->SMCR;
bogdanm 0:9b334a45a8ff 4839
bogdanm 0:9b334a45a8ff 4840 /* Reset the Trigger Selection Bits */
bogdanm 0:9b334a45a8ff 4841 tmpsmcr &= ~TIM_SMCR_TS;
bogdanm 0:9b334a45a8ff 4842 /* Set the Input Trigger source */
bogdanm 0:9b334a45a8ff 4843 tmpsmcr |= sSlaveConfig->InputTrigger;
bogdanm 0:9b334a45a8ff 4844
bogdanm 0:9b334a45a8ff 4845 /* Reset the slave mode Bits */
bogdanm 0:9b334a45a8ff 4846 tmpsmcr &= ~TIM_SMCR_SMS;
bogdanm 0:9b334a45a8ff 4847 /* Set the slave mode */
bogdanm 0:9b334a45a8ff 4848 tmpsmcr |= sSlaveConfig->SlaveMode;
bogdanm 0:9b334a45a8ff 4849
bogdanm 0:9b334a45a8ff 4850 /* Write to TIMx SMCR */
bogdanm 0:9b334a45a8ff 4851 htim->Instance->SMCR = tmpsmcr;
bogdanm 0:9b334a45a8ff 4852
bogdanm 0:9b334a45a8ff 4853 /* Configure the trigger prescaler, filter, and polarity */
bogdanm 0:9b334a45a8ff 4854 switch (sSlaveConfig->InputTrigger)
bogdanm 0:9b334a45a8ff 4855 {
bogdanm 0:9b334a45a8ff 4856 case TIM_TS_ETRF:
bogdanm 0:9b334a45a8ff 4857 {
bogdanm 0:9b334a45a8ff 4858 /* Check the parameters */
bogdanm 0:9b334a45a8ff 4859 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4860 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
bogdanm 0:9b334a45a8ff 4861 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm 0:9b334a45a8ff 4862 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm 0:9b334a45a8ff 4863 /* Configure the ETR Trigger source */
bogdanm 0:9b334a45a8ff 4864 TIM_ETR_SetConfig(htim->Instance,
bogdanm 0:9b334a45a8ff 4865 sSlaveConfig->TriggerPrescaler,
bogdanm 0:9b334a45a8ff 4866 sSlaveConfig->TriggerPolarity,
bogdanm 0:9b334a45a8ff 4867 sSlaveConfig->TriggerFilter);
bogdanm 0:9b334a45a8ff 4868 }
bogdanm 0:9b334a45a8ff 4869 break;
bogdanm 0:9b334a45a8ff 4870
bogdanm 0:9b334a45a8ff 4871 case TIM_TS_TI1F_ED:
bogdanm 0:9b334a45a8ff 4872 {
bogdanm 0:9b334a45a8ff 4873 /* Check the parameters */
bogdanm 0:9b334a45a8ff 4874 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4875 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm 0:9b334a45a8ff 4876
bogdanm 0:9b334a45a8ff 4877 /* Disable the Channel 1: Reset the CC1E Bit */
bogdanm 0:9b334a45a8ff 4878 tmpccer = htim->Instance->CCER;
bogdanm 0:9b334a45a8ff 4879 htim->Instance->CCER &= ~TIM_CCER_CC1E;
bogdanm 0:9b334a45a8ff 4880 tmpccmr1 = htim->Instance->CCMR1;
bogdanm 0:9b334a45a8ff 4881
bogdanm 0:9b334a45a8ff 4882 /* Set the filter */
bogdanm 0:9b334a45a8ff 4883 tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm 0:9b334a45a8ff 4884 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
bogdanm 0:9b334a45a8ff 4885
bogdanm 0:9b334a45a8ff 4886 /* Write to TIMx CCMR1 and CCER registers */
bogdanm 0:9b334a45a8ff 4887 htim->Instance->CCMR1 = tmpccmr1;
bogdanm 0:9b334a45a8ff 4888 htim->Instance->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 4889
bogdanm 0:9b334a45a8ff 4890 }
bogdanm 0:9b334a45a8ff 4891 break;
bogdanm 0:9b334a45a8ff 4892
bogdanm 0:9b334a45a8ff 4893 case TIM_TS_TI1FP1:
bogdanm 0:9b334a45a8ff 4894 {
bogdanm 0:9b334a45a8ff 4895 /* Check the parameters */
bogdanm 0:9b334a45a8ff 4896 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4897 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm 0:9b334a45a8ff 4898 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm 0:9b334a45a8ff 4899
bogdanm 0:9b334a45a8ff 4900 /* Configure TI1 Filter and Polarity */
bogdanm 0:9b334a45a8ff 4901 TIM_TI1_ConfigInputStage(htim->Instance,
bogdanm 0:9b334a45a8ff 4902 sSlaveConfig->TriggerPolarity,
bogdanm 0:9b334a45a8ff 4903 sSlaveConfig->TriggerFilter);
bogdanm 0:9b334a45a8ff 4904 }
bogdanm 0:9b334a45a8ff 4905 break;
bogdanm 0:9b334a45a8ff 4906
bogdanm 0:9b334a45a8ff 4907 case TIM_TS_TI2FP2:
bogdanm 0:9b334a45a8ff 4908 {
bogdanm 0:9b334a45a8ff 4909 /* Check the parameters */
bogdanm 0:9b334a45a8ff 4910 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4911 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
bogdanm 0:9b334a45a8ff 4912 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
bogdanm 0:9b334a45a8ff 4913
bogdanm 0:9b334a45a8ff 4914 /* Configure TI2 Filter and Polarity */
bogdanm 0:9b334a45a8ff 4915 TIM_TI2_ConfigInputStage(htim->Instance,
bogdanm 0:9b334a45a8ff 4916 sSlaveConfig->TriggerPolarity,
bogdanm 0:9b334a45a8ff 4917 sSlaveConfig->TriggerFilter);
bogdanm 0:9b334a45a8ff 4918 }
bogdanm 0:9b334a45a8ff 4919 break;
bogdanm 0:9b334a45a8ff 4920
bogdanm 0:9b334a45a8ff 4921 case TIM_TS_ITR0:
bogdanm 0:9b334a45a8ff 4922 {
bogdanm 0:9b334a45a8ff 4923 /* Check the parameter */
bogdanm 0:9b334a45a8ff 4924 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4925 }
bogdanm 0:9b334a45a8ff 4926 break;
bogdanm 0:9b334a45a8ff 4927
bogdanm 0:9b334a45a8ff 4928 case TIM_TS_ITR1:
bogdanm 0:9b334a45a8ff 4929 {
bogdanm 0:9b334a45a8ff 4930 /* Check the parameter */
bogdanm 0:9b334a45a8ff 4931 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4932 }
bogdanm 0:9b334a45a8ff 4933 break;
bogdanm 0:9b334a45a8ff 4934
bogdanm 0:9b334a45a8ff 4935 case TIM_TS_ITR2:
bogdanm 0:9b334a45a8ff 4936 {
bogdanm 0:9b334a45a8ff 4937 /* Check the parameter */
bogdanm 0:9b334a45a8ff 4938 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4939 }
bogdanm 0:9b334a45a8ff 4940 break;
bogdanm 0:9b334a45a8ff 4941
bogdanm 0:9b334a45a8ff 4942 case TIM_TS_ITR3:
bogdanm 0:9b334a45a8ff 4943 {
bogdanm 0:9b334a45a8ff 4944 /* Check the parameter */
bogdanm 0:9b334a45a8ff 4945 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
bogdanm 0:9b334a45a8ff 4946 }
bogdanm 0:9b334a45a8ff 4947 break;
bogdanm 0:9b334a45a8ff 4948
bogdanm 0:9b334a45a8ff 4949 default:
bogdanm 0:9b334a45a8ff 4950 break;
bogdanm 0:9b334a45a8ff 4951 }
bogdanm 0:9b334a45a8ff 4952 }
bogdanm 0:9b334a45a8ff 4953
bogdanm 0:9b334a45a8ff 4954 /**
bogdanm 0:9b334a45a8ff 4955 * @brief Configure the TI1 as Input.
bogdanm 0:9b334a45a8ff 4956 * @param TIMx to select the TIM peripheral.
bogdanm 0:9b334a45a8ff 4957 * @param TIM_ICPolarity : The Input Polarity.
bogdanm 0:9b334a45a8ff 4958 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 4959 * @arg TIM_ICPOLARITY_RISING
bogdanm 0:9b334a45a8ff 4960 * @arg TIM_ICPOLARITY_FALLING
bogdanm 0:9b334a45a8ff 4961 * @arg TIM_ICPOLARITY_BOTHEDGE
bogdanm 0:9b334a45a8ff 4962 * @param TIM_ICSelection : specifies the input to be used.
bogdanm 0:9b334a45a8ff 4963 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 4964 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1.
bogdanm 0:9b334a45a8ff 4965 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2.
bogdanm 0:9b334a45a8ff 4966 * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC.
bogdanm 0:9b334a45a8ff 4967 * @param TIM_ICFilter : Specifies the Input Capture Filter.
bogdanm 0:9b334a45a8ff 4968 * This parameter must be a value between 0x00 and 0x0F.
bogdanm 0:9b334a45a8ff 4969 * @retval None
bogdanm 0:9b334a45a8ff 4970 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
bogdanm 0:9b334a45a8ff 4971 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
bogdanm 0:9b334a45a8ff 4972 * protected against un-initialized filter and polarity values.
bogdanm 0:9b334a45a8ff 4973 */
bogdanm 0:9b334a45a8ff 4974 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm 0:9b334a45a8ff 4975 uint32_t TIM_ICFilter)
bogdanm 0:9b334a45a8ff 4976 {
bogdanm 0:9b334a45a8ff 4977 uint32_t tmpccmr1 = 0;
bogdanm 0:9b334a45a8ff 4978 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 4979
bogdanm 0:9b334a45a8ff 4980 /* Disable the Channel 1: Reset the CC1E Bit */
bogdanm 0:9b334a45a8ff 4981 TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm 0:9b334a45a8ff 4982 tmpccmr1 = TIMx->CCMR1;
bogdanm 0:9b334a45a8ff 4983 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 4984
bogdanm 0:9b334a45a8ff 4985 /* Select the Input */
bogdanm 0:9b334a45a8ff 4986 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
bogdanm 0:9b334a45a8ff 4987 {
bogdanm 0:9b334a45a8ff 4988 tmpccmr1 &= ~TIM_CCMR1_CC1S;
bogdanm 0:9b334a45a8ff 4989 tmpccmr1 |= TIM_ICSelection;
bogdanm 0:9b334a45a8ff 4990 }
bogdanm 0:9b334a45a8ff 4991 else
bogdanm 0:9b334a45a8ff 4992 {
bogdanm 0:9b334a45a8ff 4993 tmpccmr1 |= TIM_CCMR1_CC1S_0;
bogdanm 0:9b334a45a8ff 4994 }
bogdanm 0:9b334a45a8ff 4995
bogdanm 0:9b334a45a8ff 4996 /* Set the filter */
bogdanm 0:9b334a45a8ff 4997 tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm 0:9b334a45a8ff 4998 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
bogdanm 0:9b334a45a8ff 4999
bogdanm 0:9b334a45a8ff 5000 /* Select the Polarity and set the CC1E Bit */
bogdanm 0:9b334a45a8ff 5001 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
bogdanm 0:9b334a45a8ff 5002 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
bogdanm 0:9b334a45a8ff 5003
bogdanm 0:9b334a45a8ff 5004 /* Write to TIMx CCMR1 and CCER registers */
bogdanm 0:9b334a45a8ff 5005 TIMx->CCMR1 = tmpccmr1;
bogdanm 0:9b334a45a8ff 5006 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 5007 }
bogdanm 0:9b334a45a8ff 5008
bogdanm 0:9b334a45a8ff 5009 /**
bogdanm 0:9b334a45a8ff 5010 * @brief Configure the Polarity and Filter for TI1.
bogdanm 0:9b334a45a8ff 5011 * @param TIMx to select the TIM peripheral.
bogdanm 0:9b334a45a8ff 5012 * @param TIM_ICPolarity : The Input Polarity.
bogdanm 0:9b334a45a8ff 5013 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 5014 * @arg TIM_ICPOLARITY_RISING
bogdanm 0:9b334a45a8ff 5015 * @arg TIM_ICPOLARITY_FALLING
bogdanm 0:9b334a45a8ff 5016 * @arg TIM_ICPOLARITY_BOTHEDGE
bogdanm 0:9b334a45a8ff 5017 * @param TIM_ICFilter : Specifies the Input Capture Filter.
bogdanm 0:9b334a45a8ff 5018 * This parameter must be a value between 0x00 and 0x0F.
bogdanm 0:9b334a45a8ff 5019 * @retval None
bogdanm 0:9b334a45a8ff 5020 */
bogdanm 0:9b334a45a8ff 5021 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm 0:9b334a45a8ff 5022 {
bogdanm 0:9b334a45a8ff 5023 uint32_t tmpccmr1 = 0;
bogdanm 0:9b334a45a8ff 5024 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 5025
bogdanm 0:9b334a45a8ff 5026 /* Disable the Channel 1: Reset the CC1E Bit */
bogdanm 0:9b334a45a8ff 5027 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 5028 TIMx->CCER &= ~TIM_CCER_CC1E;
bogdanm 0:9b334a45a8ff 5029 tmpccmr1 = TIMx->CCMR1;
bogdanm 0:9b334a45a8ff 5030
bogdanm 0:9b334a45a8ff 5031 /* Set the filter */
bogdanm 0:9b334a45a8ff 5032 tmpccmr1 &= ~TIM_CCMR1_IC1F;
bogdanm 0:9b334a45a8ff 5033 tmpccmr1 |= (TIM_ICFilter << 4);
bogdanm 0:9b334a45a8ff 5034
bogdanm 0:9b334a45a8ff 5035 /* Select the Polarity and set the CC1E Bit */
bogdanm 0:9b334a45a8ff 5036 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
bogdanm 0:9b334a45a8ff 5037 tmpccer |= TIM_ICPolarity;
bogdanm 0:9b334a45a8ff 5038
bogdanm 0:9b334a45a8ff 5039 /* Write to TIMx CCMR1 and CCER registers */
bogdanm 0:9b334a45a8ff 5040 TIMx->CCMR1 = tmpccmr1;
bogdanm 0:9b334a45a8ff 5041 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 5042 }
bogdanm 0:9b334a45a8ff 5043
bogdanm 0:9b334a45a8ff 5044 /**
bogdanm 0:9b334a45a8ff 5045 * @brief Configure the TI2 as Input.
bogdanm 0:9b334a45a8ff 5046 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 5047 * @param TIM_ICPolarity : The Input Polarity.
bogdanm 0:9b334a45a8ff 5048 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 5049 * @arg TIM_ICPOLARITY_RISING
bogdanm 0:9b334a45a8ff 5050 * @arg TIM_ICPOLARITY_FALLING
bogdanm 0:9b334a45a8ff 5051 * @arg TIM_ICPOLARITY_BOTHEDGE
bogdanm 0:9b334a45a8ff 5052 * @param TIM_ICSelection : specifies the input to be used.
bogdanm 0:9b334a45a8ff 5053 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 5054 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2.
bogdanm 0:9b334a45a8ff 5055 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1.
bogdanm 0:9b334a45a8ff 5056 * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC.
bogdanm 0:9b334a45a8ff 5057 * @param TIM_ICFilter : Specifies the Input Capture Filter.
bogdanm 0:9b334a45a8ff 5058 * This parameter must be a value between 0x00 and 0x0F.
bogdanm 0:9b334a45a8ff 5059 * @retval None
bogdanm 0:9b334a45a8ff 5060 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
bogdanm 0:9b334a45a8ff 5061 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
bogdanm 0:9b334a45a8ff 5062 * protected against un-initialized filter and polarity values.
bogdanm 0:9b334a45a8ff 5063 */
bogdanm 0:9b334a45a8ff 5064 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm 0:9b334a45a8ff 5065 uint32_t TIM_ICFilter)
bogdanm 0:9b334a45a8ff 5066 {
bogdanm 0:9b334a45a8ff 5067 uint32_t tmpccmr1 = 0;
bogdanm 0:9b334a45a8ff 5068 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 5069
bogdanm 0:9b334a45a8ff 5070 /* Disable the Channel 2: Reset the CC2E Bit */
bogdanm 0:9b334a45a8ff 5071 TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm 0:9b334a45a8ff 5072 tmpccmr1 = TIMx->CCMR1;
bogdanm 0:9b334a45a8ff 5073 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 5074
bogdanm 0:9b334a45a8ff 5075 /* Select the Input */
bogdanm 0:9b334a45a8ff 5076 tmpccmr1 &= ~TIM_CCMR1_CC2S;
bogdanm 0:9b334a45a8ff 5077 tmpccmr1 |= (TIM_ICSelection << 8);
bogdanm 0:9b334a45a8ff 5078
bogdanm 0:9b334a45a8ff 5079 /* Set the filter */
bogdanm 0:9b334a45a8ff 5080 tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm 0:9b334a45a8ff 5081 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
bogdanm 0:9b334a45a8ff 5082
bogdanm 0:9b334a45a8ff 5083 /* Select the Polarity and set the CC2E Bit */
bogdanm 0:9b334a45a8ff 5084 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
bogdanm 0:9b334a45a8ff 5085 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
bogdanm 0:9b334a45a8ff 5086
bogdanm 0:9b334a45a8ff 5087 /* Write to TIMx CCMR1 and CCER registers */
bogdanm 0:9b334a45a8ff 5088 TIMx->CCMR1 = tmpccmr1 ;
bogdanm 0:9b334a45a8ff 5089 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 5090 }
bogdanm 0:9b334a45a8ff 5091
bogdanm 0:9b334a45a8ff 5092 /**
bogdanm 0:9b334a45a8ff 5093 * @brief Configure the Polarity and Filter for TI2.
bogdanm 0:9b334a45a8ff 5094 * @param TIMx to select the TIM peripheral.
bogdanm 0:9b334a45a8ff 5095 * @param TIM_ICPolarity : The Input Polarity.
bogdanm 0:9b334a45a8ff 5096 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 5097 * @arg TIM_ICPOLARITY_RISING
bogdanm 0:9b334a45a8ff 5098 * @arg TIM_ICPOLARITY_FALLING
bogdanm 0:9b334a45a8ff 5099 * @arg TIM_ICPOLARITY_BOTHEDGE
bogdanm 0:9b334a45a8ff 5100 * @param TIM_ICFilter : Specifies the Input Capture Filter.
bogdanm 0:9b334a45a8ff 5101 * This parameter must be a value between 0x00 and 0x0F.
bogdanm 0:9b334a45a8ff 5102 * @retval None
bogdanm 0:9b334a45a8ff 5103 */
bogdanm 0:9b334a45a8ff 5104 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
bogdanm 0:9b334a45a8ff 5105 {
bogdanm 0:9b334a45a8ff 5106 uint32_t tmpccmr1 = 0;
bogdanm 0:9b334a45a8ff 5107 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 5108
bogdanm 0:9b334a45a8ff 5109 /* Disable the Channel 2: Reset the CC2E Bit */
bogdanm 0:9b334a45a8ff 5110 TIMx->CCER &= ~TIM_CCER_CC2E;
bogdanm 0:9b334a45a8ff 5111 tmpccmr1 = TIMx->CCMR1;
bogdanm 0:9b334a45a8ff 5112 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 5113
bogdanm 0:9b334a45a8ff 5114 /* Set the filter */
bogdanm 0:9b334a45a8ff 5115 tmpccmr1 &= ~TIM_CCMR1_IC2F;
bogdanm 0:9b334a45a8ff 5116 tmpccmr1 |= (TIM_ICFilter << 12);
bogdanm 0:9b334a45a8ff 5117
bogdanm 0:9b334a45a8ff 5118 /* Select the Polarity and set the CC2E Bit */
bogdanm 0:9b334a45a8ff 5119 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
bogdanm 0:9b334a45a8ff 5120 tmpccer |= (TIM_ICPolarity << 4);
bogdanm 0:9b334a45a8ff 5121
bogdanm 0:9b334a45a8ff 5122 /* Write to TIMx CCMR1 and CCER registers */
bogdanm 0:9b334a45a8ff 5123 TIMx->CCMR1 = tmpccmr1 ;
bogdanm 0:9b334a45a8ff 5124 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 5125 }
bogdanm 0:9b334a45a8ff 5126
bogdanm 0:9b334a45a8ff 5127 /**
bogdanm 0:9b334a45a8ff 5128 * @brief Configure the TI3 as Input.
bogdanm 0:9b334a45a8ff 5129 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 5130 * @param TIM_ICPolarity : The Input Polarity.
bogdanm 0:9b334a45a8ff 5131 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 5132 * @arg TIM_ICPOLARITY_RISING
bogdanm 0:9b334a45a8ff 5133 * @arg TIM_ICPOLARITY_FALLING
bogdanm 0:9b334a45a8ff 5134 * @arg TIM_ICPOLARITY_BOTHEDGE
bogdanm 0:9b334a45a8ff 5135 * @param TIM_ICSelection : specifies the input to be used.
bogdanm 0:9b334a45a8ff 5136 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 5137 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3.
bogdanm 0:9b334a45a8ff 5138 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4.
bogdanm 0:9b334a45a8ff 5139 * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC.
bogdanm 0:9b334a45a8ff 5140 * @param TIM_ICFilter : Specifies the Input Capture Filter.
bogdanm 0:9b334a45a8ff 5141 * This parameter must be a value between 0x00 and 0x0F.
bogdanm 0:9b334a45a8ff 5142 * @retval None
bogdanm 0:9b334a45a8ff 5143 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
bogdanm 0:9b334a45a8ff 5144 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
bogdanm 0:9b334a45a8ff 5145 * protected against un-initialized filter and polarity values.
bogdanm 0:9b334a45a8ff 5146 */
bogdanm 0:9b334a45a8ff 5147 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm 0:9b334a45a8ff 5148 uint32_t TIM_ICFilter)
bogdanm 0:9b334a45a8ff 5149 {
bogdanm 0:9b334a45a8ff 5150 uint32_t tmpccmr2 = 0;
bogdanm 0:9b334a45a8ff 5151 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 5152
bogdanm 0:9b334a45a8ff 5153 /* Disable the Channel 3: Reset the CC3E Bit */
bogdanm 0:9b334a45a8ff 5154 TIMx->CCER &= ~TIM_CCER_CC3E;
bogdanm 0:9b334a45a8ff 5155 tmpccmr2 = TIMx->CCMR2;
bogdanm 0:9b334a45a8ff 5156 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 5157
bogdanm 0:9b334a45a8ff 5158 /* Select the Input */
bogdanm 0:9b334a45a8ff 5159 tmpccmr2 &= ~TIM_CCMR2_CC3S;
bogdanm 0:9b334a45a8ff 5160 tmpccmr2 |= TIM_ICSelection;
bogdanm 0:9b334a45a8ff 5161
bogdanm 0:9b334a45a8ff 5162 /* Set the filter */
bogdanm 0:9b334a45a8ff 5163 tmpccmr2 &= ~TIM_CCMR2_IC3F;
bogdanm 0:9b334a45a8ff 5164 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
bogdanm 0:9b334a45a8ff 5165
bogdanm 0:9b334a45a8ff 5166 /* Select the Polarity and set the CC3E Bit */
bogdanm 0:9b334a45a8ff 5167 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
bogdanm 0:9b334a45a8ff 5168 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
bogdanm 0:9b334a45a8ff 5169
bogdanm 0:9b334a45a8ff 5170 /* Write to TIMx CCMR2 and CCER registers */
bogdanm 0:9b334a45a8ff 5171 TIMx->CCMR2 = tmpccmr2;
bogdanm 0:9b334a45a8ff 5172 TIMx->CCER = tmpccer;
bogdanm 0:9b334a45a8ff 5173 }
bogdanm 0:9b334a45a8ff 5174
bogdanm 0:9b334a45a8ff 5175 /**
bogdanm 0:9b334a45a8ff 5176 * @brief Configure the TI4 as Input.
bogdanm 0:9b334a45a8ff 5177 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 5178 * @param TIM_ICPolarity : The Input Polarity.
bogdanm 0:9b334a45a8ff 5179 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 5180 * @arg TIM_ICPOLARITY_RISING
bogdanm 0:9b334a45a8ff 5181 * @arg TIM_ICPOLARITY_FALLING
bogdanm 0:9b334a45a8ff 5182 * @arg TIM_ICPOLARITY_BOTHEDGE
bogdanm 0:9b334a45a8ff 5183 * @param TIM_ICSelection : specifies the input to be used.
bogdanm 0:9b334a45a8ff 5184 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 5185 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4.
bogdanm 0:9b334a45a8ff 5186 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3.
bogdanm 0:9b334a45a8ff 5187 * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC.
bogdanm 0:9b334a45a8ff 5188 * @param TIM_ICFilter : Specifies the Input Capture Filter.
bogdanm 0:9b334a45a8ff 5189 * This parameter must be a value between 0x00 and 0x0F.
bogdanm 0:9b334a45a8ff 5190 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
bogdanm 0:9b334a45a8ff 5191 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
bogdanm 0:9b334a45a8ff 5192 * protected against un-initialized filter and polarity values.
bogdanm 0:9b334a45a8ff 5193 * @retval None
bogdanm 0:9b334a45a8ff 5194 */
bogdanm 0:9b334a45a8ff 5195 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
bogdanm 0:9b334a45a8ff 5196 uint32_t TIM_ICFilter)
bogdanm 0:9b334a45a8ff 5197 {
bogdanm 0:9b334a45a8ff 5198 uint32_t tmpccmr2 = 0;
bogdanm 0:9b334a45a8ff 5199 uint32_t tmpccer = 0;
bogdanm 0:9b334a45a8ff 5200
bogdanm 0:9b334a45a8ff 5201 /* Disable the Channel 4: Reset the CC4E Bit */
bogdanm 0:9b334a45a8ff 5202 TIMx->CCER &= ~TIM_CCER_CC4E;
bogdanm 0:9b334a45a8ff 5203 tmpccmr2 = TIMx->CCMR2;
bogdanm 0:9b334a45a8ff 5204 tmpccer = TIMx->CCER;
bogdanm 0:9b334a45a8ff 5205
bogdanm 0:9b334a45a8ff 5206 /* Select the Input */
bogdanm 0:9b334a45a8ff 5207 tmpccmr2 &= ~TIM_CCMR2_CC4S;
bogdanm 0:9b334a45a8ff 5208 tmpccmr2 |= (TIM_ICSelection << 8);
bogdanm 0:9b334a45a8ff 5209
bogdanm 0:9b334a45a8ff 5210 /* Set the filter */
bogdanm 0:9b334a45a8ff 5211 tmpccmr2 &= ~TIM_CCMR2_IC4F;
bogdanm 0:9b334a45a8ff 5212 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
bogdanm 0:9b334a45a8ff 5213
bogdanm 0:9b334a45a8ff 5214 /* Select the Polarity and set the CC4E Bit */
bogdanm 0:9b334a45a8ff 5215 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
bogdanm 0:9b334a45a8ff 5216 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
bogdanm 0:9b334a45a8ff 5217
bogdanm 0:9b334a45a8ff 5218 /* Write to TIMx CCMR2 and CCER registers */
bogdanm 0:9b334a45a8ff 5219 TIMx->CCMR2 = tmpccmr2;
bogdanm 0:9b334a45a8ff 5220 TIMx->CCER = tmpccer ;
bogdanm 0:9b334a45a8ff 5221 }
bogdanm 0:9b334a45a8ff 5222
bogdanm 0:9b334a45a8ff 5223 /**
bogdanm 0:9b334a45a8ff 5224 * @brief Selects the Input Trigger source
bogdanm 0:9b334a45a8ff 5225 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 5226 * @param InputTriggerSource : The Input Trigger source.
bogdanm 0:9b334a45a8ff 5227 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 5228 * @arg TIM_TS_ITR0 : Internal Trigger 0
bogdanm 0:9b334a45a8ff 5229 * @arg TIM_TS_ITR1 : Internal Trigger 1
bogdanm 0:9b334a45a8ff 5230 * @arg TIM_TS_ITR2 : Internal Trigger 2
bogdanm 0:9b334a45a8ff 5231 * @arg TIM_TS_ITR3 : Internal Trigger 3
bogdanm 0:9b334a45a8ff 5232 * @arg TIM_TS_TI1F_ED : TI1 Edge Detector
bogdanm 0:9b334a45a8ff 5233 * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
bogdanm 0:9b334a45a8ff 5234 * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
bogdanm 0:9b334a45a8ff 5235 * @arg TIM_TS_ETRF : External Trigger input
bogdanm 0:9b334a45a8ff 5236 * @retval None
bogdanm 0:9b334a45a8ff 5237 */
bogdanm 0:9b334a45a8ff 5238 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
bogdanm 0:9b334a45a8ff 5239 {
bogdanm 0:9b334a45a8ff 5240 uint32_t tmpsmcr = 0;
bogdanm 0:9b334a45a8ff 5241
bogdanm 0:9b334a45a8ff 5242 /* Get the TIMx SMCR register value */
bogdanm 0:9b334a45a8ff 5243 tmpsmcr = TIMx->SMCR;
bogdanm 0:9b334a45a8ff 5244 /* Reset the TS Bits */
bogdanm 0:9b334a45a8ff 5245 tmpsmcr &= ~TIM_SMCR_TS;
bogdanm 0:9b334a45a8ff 5246 /* Set the Input Trigger source and the slave mode*/
bogdanm 0:9b334a45a8ff 5247 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
bogdanm 0:9b334a45a8ff 5248 /* Write to TIMx SMCR */
bogdanm 0:9b334a45a8ff 5249 TIMx->SMCR = tmpsmcr;
bogdanm 0:9b334a45a8ff 5250 }
bogdanm 0:9b334a45a8ff 5251 /**
bogdanm 0:9b334a45a8ff 5252 * @brief Configures the TIMx External Trigger (ETR).
bogdanm 0:9b334a45a8ff 5253 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 5254 * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
bogdanm 0:9b334a45a8ff 5255 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 5256 * @arg TIM_ExtTRGPSC_DIV1 : ETRP Prescaler OFF.
bogdanm 0:9b334a45a8ff 5257 * @arg TIM_ExtTRGPSC_DIV2 : ETRP frequency divided by 2.
bogdanm 0:9b334a45a8ff 5258 * @arg TIM_ExtTRGPSC_DIV4 : ETRP frequency divided by 4.
bogdanm 0:9b334a45a8ff 5259 * @arg TIM_ExtTRGPSC_DIV8 : ETRP frequency divided by 8.
bogdanm 0:9b334a45a8ff 5260 * @param TIM_ExtTRGPolarity : The external Trigger Polarity.
bogdanm 0:9b334a45a8ff 5261 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 5262 * @arg TIM_ExtTRGPolarity_Inverted : active low or falling edge active.
bogdanm 0:9b334a45a8ff 5263 * @arg TIM_ExtTRGPolarity_NonInverted : active high or rising edge active.
bogdanm 0:9b334a45a8ff 5264 * @param ExtTRGFilter : External Trigger Filter.
bogdanm 0:9b334a45a8ff 5265 * This parameter must be a value between 0x00 and 0x0F
bogdanm 0:9b334a45a8ff 5266 * @retval None
bogdanm 0:9b334a45a8ff 5267 */
bogdanm 0:9b334a45a8ff 5268 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm 0:9b334a45a8ff 5269 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
bogdanm 0:9b334a45a8ff 5270 {
bogdanm 0:9b334a45a8ff 5271 uint32_t tmpsmcr = 0;
bogdanm 0:9b334a45a8ff 5272
bogdanm 0:9b334a45a8ff 5273 tmpsmcr = TIMx->SMCR;
bogdanm 0:9b334a45a8ff 5274
bogdanm 0:9b334a45a8ff 5275 /* Reset the ETR Bits */
bogdanm 0:9b334a45a8ff 5276 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
bogdanm 0:9b334a45a8ff 5277
bogdanm 0:9b334a45a8ff 5278 /* Set the Prescaler, the Filter value and the Polarity */
bogdanm 0:9b334a45a8ff 5279 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
bogdanm 0:9b334a45a8ff 5280
bogdanm 0:9b334a45a8ff 5281 /* Write to TIMx SMCR */
bogdanm 0:9b334a45a8ff 5282 TIMx->SMCR = tmpsmcr;
bogdanm 0:9b334a45a8ff 5283 }
bogdanm 0:9b334a45a8ff 5284
bogdanm 0:9b334a45a8ff 5285 /**
bogdanm 0:9b334a45a8ff 5286 * @brief Enables or disables the TIM Capture Compare Channel x.
bogdanm 0:9b334a45a8ff 5287 * @param TIMx to select the TIM peripheral
bogdanm 0:9b334a45a8ff 5288 * @param Channel : specifies the TIM Channel
bogdanm 0:9b334a45a8ff 5289 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 5290 * @arg TIM_CHANNEL_1 : TIM Channel 1
bogdanm 0:9b334a45a8ff 5291 * @arg TIM_CHANNEL_2 : TIM Channel 2
bogdanm 0:9b334a45a8ff 5292 * @arg TIM_CHANNEL_3 : TIM Channel 3
bogdanm 0:9b334a45a8ff 5293 * @arg TIM_CHANNEL_4 : TIM Channel 4
bogdanm 0:9b334a45a8ff 5294 * @param ChannelState : specifies the TIM Channel CCxE bit new state.
bogdanm 0:9b334a45a8ff 5295 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
bogdanm 0:9b334a45a8ff 5296 * @retval None
bogdanm 0:9b334a45a8ff 5297 */
bogdanm 0:9b334a45a8ff 5298 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
bogdanm 0:9b334a45a8ff 5299 {
bogdanm 0:9b334a45a8ff 5300 uint32_t tmp = 0;
bogdanm 0:9b334a45a8ff 5301
bogdanm 0:9b334a45a8ff 5302 /* Check the parameters */
bogdanm 0:9b334a45a8ff 5303 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
bogdanm 0:9b334a45a8ff 5304 assert_param(IS_TIM_CHANNELS(Channel));
bogdanm 0:9b334a45a8ff 5305
bogdanm 0:9b334a45a8ff 5306 tmp = TIM_CCER_CC1E << Channel;
bogdanm 0:9b334a45a8ff 5307
bogdanm 0:9b334a45a8ff 5308 /* Reset the CCxE Bit */
bogdanm 0:9b334a45a8ff 5309 TIMx->CCER &= ~tmp;
bogdanm 0:9b334a45a8ff 5310
bogdanm 0:9b334a45a8ff 5311 /* Set or reset the CCxE Bit */
bogdanm 0:9b334a45a8ff 5312 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
bogdanm 0:9b334a45a8ff 5313 }
bogdanm 0:9b334a45a8ff 5314
bogdanm 0:9b334a45a8ff 5315
bogdanm 0:9b334a45a8ff 5316 /**
bogdanm 0:9b334a45a8ff 5317 * @}
bogdanm 0:9b334a45a8ff 5318 */
bogdanm 0:9b334a45a8ff 5319
bogdanm 0:9b334a45a8ff 5320 #endif /* HAL_TIM_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 5321 /**
bogdanm 0:9b334a45a8ff 5322 * @}
bogdanm 0:9b334a45a8ff 5323 */
bogdanm 0:9b334a45a8ff 5324
bogdanm 0:9b334a45a8ff 5325 /**
bogdanm 0:9b334a45a8ff 5326 * @}
bogdanm 0:9b334a45a8ff 5327 */
bogdanm 0:9b334a45a8ff 5328 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/