en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f0xx_hal_rcc.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.3.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief RCC HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 @verbatim
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 ##### RCC specific features #####
bogdanm 0:9b334a45a8ff 16 ==============================================================================
bogdanm 0:9b334a45a8ff 17 [..]
bogdanm 0:9b334a45a8ff 18 After reset the device is running from Internal High Speed oscillator
bogdanm 0:9b334a45a8ff 19 (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
bogdanm 0:9b334a45a8ff 20 and all peripherals are off except internal SRAM, Flash and JTAG.
bogdanm 0:9b334a45a8ff 21 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
bogdanm 0:9b334a45a8ff 22 all peripherals mapped on these busses are running at HSI speed.
bogdanm 0:9b334a45a8ff 23 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
bogdanm 0:9b334a45a8ff 24 (+) All GPIOs are in input floating state, except the JTAG pins which
bogdanm 0:9b334a45a8ff 25 are assigned to be used for debug purpose.
bogdanm 0:9b334a45a8ff 26 [..] Once the device started from reset, the user application has to:
bogdanm 0:9b334a45a8ff 27 (+) Configure the clock source to be used to drive the System clock
bogdanm 0:9b334a45a8ff 28 (if the application needs higher frequency/performance)
bogdanm 0:9b334a45a8ff 29 (+) Configure the System clock frequency and Flash settings
bogdanm 0:9b334a45a8ff 30 (+) Configure the AHB and APB busses prescalers
bogdanm 0:9b334a45a8ff 31 (+) Enable the clock for the peripheral(s) to be used
bogdanm 0:9b334a45a8ff 32 (+) Configure the clock source(s) for peripherals whose clocks are not
bogdanm 0:9b334a45a8ff 33 derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..)
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 ##### RCC Limitations #####
bogdanm 0:9b334a45a8ff 36 ==============================================================================
bogdanm 0:9b334a45a8ff 37 [..]
bogdanm 0:9b334a45a8ff 38 A delay between an RCC peripheral clock enable and the effective peripheral
bogdanm 0:9b334a45a8ff 39 enabling should be taken into account in order to manage the peripheral read/write
bogdanm 0:9b334a45a8ff 40 from/to registers.
bogdanm 0:9b334a45a8ff 41 (+) This delay depends on the peripheral mapping.
bogdanm 0:9b334a45a8ff 42 (++) AHB & APB peripherals, 1 dummy read is necessary
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 [..]
bogdanm 0:9b334a45a8ff 45 Workarounds:
bogdanm 0:9b334a45a8ff 46 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
bogdanm 0:9b334a45a8ff 47 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 @endverbatim
bogdanm 0:9b334a45a8ff 50 ******************************************************************************
bogdanm 0:9b334a45a8ff 51 * @attention
bogdanm 0:9b334a45a8ff 52 *
bogdanm 0:9b334a45a8ff 53 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 54 *
bogdanm 0:9b334a45a8ff 55 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 56 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 57 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 58 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 59 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 60 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 61 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 62 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 63 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 64 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 65 *
bogdanm 0:9b334a45a8ff 66 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 67 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 69 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 72 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 73 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 74 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 75 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 76 *
bogdanm 0:9b334a45a8ff 77 ******************************************************************************
bogdanm 0:9b334a45a8ff 78 */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 81 #include "stm32f0xx_hal.h"
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 0:9b334a45a8ff 84 * @{
bogdanm 0:9b334a45a8ff 85 */
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 /** @defgroup RCC RCC
bogdanm 0:9b334a45a8ff 88 * @brief RCC HAL module driver
bogdanm 0:9b334a45a8ff 89 * @{
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 #ifdef HAL_RCC_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 95 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 96 /** @defgroup RCC_Private_Constants RCC Private Constants
bogdanm 0:9b334a45a8ff 97 * @{
bogdanm 0:9b334a45a8ff 98 */
bogdanm 0:9b334a45a8ff 99 /**
bogdanm 0:9b334a45a8ff 100 * @}
bogdanm 0:9b334a45a8ff 101 */
bogdanm 0:9b334a45a8ff 102 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 103 /** @defgroup RCC_Private_Macros RCC Private Macros
bogdanm 0:9b334a45a8ff 104 * @{
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
bogdanm 0:9b334a45a8ff 108 #define MCO1_GPIO_PORT GPIOA
bogdanm 0:9b334a45a8ff 109 #define MCO1_PIN GPIO_PIN_8
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 /**
bogdanm 0:9b334a45a8ff 112 * @}
bogdanm 0:9b334a45a8ff 113 */
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 116 /** @defgroup RCC_Private_Variables RCC Private Variables
bogdanm 0:9b334a45a8ff 117 * @{
bogdanm 0:9b334a45a8ff 118 */
bogdanm 0:9b334a45a8ff 119 const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm 0:9b334a45a8ff 120 /**
bogdanm 0:9b334a45a8ff 121 * @}
bogdanm 0:9b334a45a8ff 122 */
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 125 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 /** @defgroup RCC_Exported_Functions RCC Exported Functions
bogdanm 0:9b334a45a8ff 128 * @{
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 132 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 133 *
bogdanm 0:9b334a45a8ff 134 @verbatim
bogdanm 0:9b334a45a8ff 135 ===============================================================================
bogdanm 0:9b334a45a8ff 136 ##### Initialization and de-initialization function #####
bogdanm 0:9b334a45a8ff 137 ===============================================================================
bogdanm 0:9b334a45a8ff 138 [..]
bogdanm 0:9b334a45a8ff 139 This section provides functions allowing to configure the internal/external oscillators
bogdanm 0:9b334a45a8ff 140 (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK,
bogdanm 0:9b334a45a8ff 141 AHB and APB1).
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 [..] Internal/external clock and PLL configuration
bogdanm 0:9b334a45a8ff 144 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
bogdanm 0:9b334a45a8ff 145 the PLL as System clock source.
bogdanm 0:9b334a45a8ff 146 The HSI clock can be used also to clock the USART and I2C peripherals.
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock
bogdanm 0:9b334a45a8ff 149 the ADC peripheral.
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
bogdanm 0:9b334a45a8ff 152 clock source.
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
bogdanm 0:9b334a45a8ff 155 through the PLL as System clock source. Can be used also as RTC clock source.
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks:
bogdanm 0:9b334a45a8ff 160 (++) The first output is used to generate the high speed system clock (up to 48 MHz)
bogdanm 0:9b334a45a8ff 161 (++) The second output is used to generate the clock for the USB FS (48 MHz)
bogdanm 0:9b334a45a8ff 162 (++) The third output may be used to generate the clock for the TIM, I2C and USART
bogdanm 0:9b334a45a8ff 163 peripherals (up to 48 MHz)
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
bogdanm 0:9b334a45a8ff 166 and if a HSE clock failure occurs(HSE used directly or through PLL as System
bogdanm 0:9b334a45a8ff 167 clock source), the System clockis automatically switched to HSI and an interrupt
bogdanm 0:9b334a45a8ff 168 is generated if enabled. The interrupt is linked to the Cortex-M0 NMI
bogdanm 0:9b334a45a8ff 169 (Non-Maskable Interrupt) exception vector.
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
bogdanm 0:9b334a45a8ff 172 clock (divided by 2) output on pin (such as PA8 pin).
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 [..] System, AHB and APB busses clocks configuration
bogdanm 0:9b334a45a8ff 175 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
bogdanm 0:9b334a45a8ff 176 HSE and PLL.
bogdanm 0:9b334a45a8ff 177 The AHB clock (HCLK) is derived from System clock through configurable
bogdanm 0:9b334a45a8ff 178 prescaler and used to clock the CPU, memory and peripherals mapped
bogdanm 0:9b334a45a8ff 179 on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived
bogdanm 0:9b334a45a8ff 180 from AHB clock through configurable prescalers and used to clock
bogdanm 0:9b334a45a8ff 181 the peripherals mapped on these busses. You can use
bogdanm 0:9b334a45a8ff 182 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
bogdanm 0:9b334a45a8ff 185 (++) The FLASH program/erase clock which is always HSI 8MHz clock.
bogdanm 0:9b334a45a8ff 186 (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
bogdanm 0:9b334a45a8ff 187 (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
bogdanm 0:9b334a45a8ff 188 (++) The I2C clock which can be derived as well from HSI 8MHz clock.
bogdanm 0:9b334a45a8ff 189 (++) The ADC clock which is derived from PLL output.
bogdanm 0:9b334a45a8ff 190 (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
bogdanm 0:9b334a45a8ff 191 (HSE divided by a programmable prescaler). The System clock (SYSCLK)
bogdanm 0:9b334a45a8ff 192 frequency must be higher or equal to the RTC clock frequency.
bogdanm 0:9b334a45a8ff 193 (++) IWDG clock which is always the LSI clock.
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz,
bogdanm 0:9b334a45a8ff 196 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
bogdanm 0:9b334a45a8ff 197 +-----------------------------------------------+
bogdanm 0:9b334a45a8ff 198 | Latency | SYSCLK clock frequency (MHz) |
bogdanm 0:9b334a45a8ff 199 |---------------|-------------------------------|
bogdanm 0:9b334a45a8ff 200 |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
bogdanm 0:9b334a45a8ff 201 |---------------|-------------------------------|
bogdanm 0:9b334a45a8ff 202 |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
bogdanm 0:9b334a45a8ff 203 +-----------------------------------------------+
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
bogdanm 0:9b334a45a8ff 206 prefetch is disabled.
bogdanm 0:9b334a45a8ff 207 @endverbatim
bogdanm 0:9b334a45a8ff 208 * @{
bogdanm 0:9b334a45a8ff 209 */
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 /**
bogdanm 0:9b334a45a8ff 212 * @brief Resets the RCC clock configuration to the default reset state.
bogdanm 0:9b334a45a8ff 213 * @note The default reset state of the clock configuration is given below:
bogdanm 0:9b334a45a8ff 214 * - HSI ON and used as system clock source
bogdanm 0:9b334a45a8ff 215 * - HSE and PLL OFF
bogdanm 0:9b334a45a8ff 216 * - AHB, APB1 prescaler set to 1.
bogdanm 0:9b334a45a8ff 217 * - CSS and MCO1 OFF
bogdanm 0:9b334a45a8ff 218 * - All interrupts disabled
bogdanm 0:9b334a45a8ff 219 * @note This function doesn't modify the configuration of the
bogdanm 0:9b334a45a8ff 220 * - Peripheral clocks
bogdanm 0:9b334a45a8ff 221 * - LSI, LSE and RTC clocks
bogdanm 0:9b334a45a8ff 222 * @retval None
bogdanm 0:9b334a45a8ff 223 */
bogdanm 0:9b334a45a8ff 224 void HAL_RCC_DeInit(void)
bogdanm 0:9b334a45a8ff 225 {
bogdanm 0:9b334a45a8ff 226 /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
bogdanm 0:9b334a45a8ff 227 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
bogdanm 0:9b334a45a8ff 230 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO);
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232 /* Reset HSEON, CSSON, PLLON bits */
bogdanm 0:9b334a45a8ff 233 CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 /* Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 236 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 /* Reset CFGR register */
bogdanm 0:9b334a45a8ff 239 CLEAR_REG(RCC->CFGR);
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 /* Reset CFGR2 register */
bogdanm 0:9b334a45a8ff 242 CLEAR_REG(RCC->CFGR2);
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 /* Reset CFGR3 register */
bogdanm 0:9b334a45a8ff 245 CLEAR_REG(RCC->CFGR3);
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 /* Disable all interrupts */
bogdanm 0:9b334a45a8ff 248 CLEAR_REG(RCC->CIR);
bogdanm 0:9b334a45a8ff 249 }
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /**
bogdanm 0:9b334a45a8ff 252 * @brief Initializes the RCC Oscillators according to the specified parameters in the
bogdanm 0:9b334a45a8ff 253 * RCC_OscInitTypeDef.
bogdanm 0:9b334a45a8ff 254 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 255 * contains the configuration information for the RCC Oscillators.
bogdanm 0:9b334a45a8ff 256 * @note The PLL is not disabled when used as system clock.
bogdanm 0:9b334a45a8ff 257 * @retval HAL status
bogdanm 0:9b334a45a8ff 258 */
bogdanm 0:9b334a45a8ff 259 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm 0:9b334a45a8ff 260 {
bogdanm 0:9b334a45a8ff 261 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 262
bogdanm 0:9b334a45a8ff 263 /* Check the parameters */
bogdanm 0:9b334a45a8ff 264 assert_param(RCC_OscInitStruct != NULL);
bogdanm 0:9b334a45a8ff 265 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 /*------------------------------- HSE Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 268 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
bogdanm 0:9b334a45a8ff 269 {
bogdanm 0:9b334a45a8ff 270 /* Check the parameters */
bogdanm 0:9b334a45a8ff 271 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
bogdanm 0:9b334a45a8ff 274 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm 0:9b334a45a8ff 275 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
bogdanm 0:9b334a45a8ff 276 {
bogdanm 0:9b334a45a8ff 277 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
bogdanm 0:9b334a45a8ff 278 {
bogdanm 0:9b334a45a8ff 279 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 280 }
bogdanm 0:9b334a45a8ff 281 }
bogdanm 0:9b334a45a8ff 282 else
bogdanm 0:9b334a45a8ff 283 {
bogdanm 0:9b334a45a8ff 284 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
bogdanm 0:9b334a45a8ff 285 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 288 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290 /* Wait till HSE is disabled */
bogdanm 0:9b334a45a8ff 291 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm 0:9b334a45a8ff 292 {
bogdanm 0:9b334a45a8ff 293 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 294 {
bogdanm 0:9b334a45a8ff 295 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 296 }
bogdanm 0:9b334a45a8ff 297 }
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 /* Set the new HSE configuration ---------------------------------------*/
bogdanm 0:9b334a45a8ff 300 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 /* Check the HSE State */
bogdanm 0:9b334a45a8ff 303 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
bogdanm 0:9b334a45a8ff 304 {
bogdanm 0:9b334a45a8ff 305 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 306 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /* Wait till HSE is ready */
bogdanm 0:9b334a45a8ff 309 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm 0:9b334a45a8ff 310 {
bogdanm 0:9b334a45a8ff 311 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 312 {
bogdanm 0:9b334a45a8ff 313 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 314 }
bogdanm 0:9b334a45a8ff 315 }
bogdanm 0:9b334a45a8ff 316 }
bogdanm 0:9b334a45a8ff 317 else
bogdanm 0:9b334a45a8ff 318 {
bogdanm 0:9b334a45a8ff 319 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 320 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 /* Wait till HSE is bypassed or disabled */
bogdanm 0:9b334a45a8ff 323 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm 0:9b334a45a8ff 324 {
bogdanm 0:9b334a45a8ff 325 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 326 {
bogdanm 0:9b334a45a8ff 327 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 328 }
bogdanm 0:9b334a45a8ff 329 }
bogdanm 0:9b334a45a8ff 330 }
bogdanm 0:9b334a45a8ff 331 }
bogdanm 0:9b334a45a8ff 332 }
bogdanm 0:9b334a45a8ff 333 /*----------------------------- HSI Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 334 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
bogdanm 0:9b334a45a8ff 335 {
bogdanm 0:9b334a45a8ff 336 /* Check the parameters */
bogdanm 0:9b334a45a8ff 337 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
bogdanm 0:9b334a45a8ff 338 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
bogdanm 0:9b334a45a8ff 341 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm 0:9b334a45a8ff 342 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
bogdanm 0:9b334a45a8ff 343 {
bogdanm 0:9b334a45a8ff 344 /* When HSI is used as system clock it will not disabled */
bogdanm 0:9b334a45a8ff 345 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
bogdanm 0:9b334a45a8ff 346 {
bogdanm 0:9b334a45a8ff 347 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 348 }
bogdanm 0:9b334a45a8ff 349 /* Otherwise, just the calibration is allowed */
bogdanm 0:9b334a45a8ff 350 else
bogdanm 0:9b334a45a8ff 351 {
bogdanm 0:9b334a45a8ff 352 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm 0:9b334a45a8ff 353 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm 0:9b334a45a8ff 354 }
bogdanm 0:9b334a45a8ff 355 }
bogdanm 0:9b334a45a8ff 356 else
bogdanm 0:9b334a45a8ff 357 {
bogdanm 0:9b334a45a8ff 358 /* Check the HSI State */
bogdanm 0:9b334a45a8ff 359 if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
bogdanm 0:9b334a45a8ff 360 {
bogdanm 0:9b334a45a8ff 361 /* Enable the Internal High Speed oscillator (HSI). */
bogdanm 0:9b334a45a8ff 362 __HAL_RCC_HSI_ENABLE();
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 365 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 /* Wait till HSI is ready */
bogdanm 0:9b334a45a8ff 368 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 369 {
bogdanm 0:9b334a45a8ff 370 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 371 {
bogdanm 0:9b334a45a8ff 372 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 373 }
bogdanm 0:9b334a45a8ff 374 }
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm 0:9b334a45a8ff 377 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm 0:9b334a45a8ff 378 }
bogdanm 0:9b334a45a8ff 379 else
bogdanm 0:9b334a45a8ff 380 {
bogdanm 0:9b334a45a8ff 381 /* Disable the Internal High Speed oscillator (HSI). */
bogdanm 0:9b334a45a8ff 382 __HAL_RCC_HSI_DISABLE();
bogdanm 0:9b334a45a8ff 383
bogdanm 0:9b334a45a8ff 384 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 385 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 /* Wait till HSI is disabled */
bogdanm 0:9b334a45a8ff 388 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
bogdanm 0:9b334a45a8ff 389 {
bogdanm 0:9b334a45a8ff 390 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 391 {
bogdanm 0:9b334a45a8ff 392 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 393 }
bogdanm 0:9b334a45a8ff 394 }
bogdanm 0:9b334a45a8ff 395 }
bogdanm 0:9b334a45a8ff 396 }
bogdanm 0:9b334a45a8ff 397 }
bogdanm 0:9b334a45a8ff 398 /*------------------------------ LSI Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 399 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
bogdanm 0:9b334a45a8ff 400 {
bogdanm 0:9b334a45a8ff 401 /* Check the parameters */
bogdanm 0:9b334a45a8ff 402 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 /* Check the LSI State */
bogdanm 0:9b334a45a8ff 405 if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
bogdanm 0:9b334a45a8ff 406 {
bogdanm 0:9b334a45a8ff 407 /* Enable the Internal Low Speed oscillator (LSI). */
bogdanm 0:9b334a45a8ff 408 __HAL_RCC_LSI_ENABLE();
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 411 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 /* Wait till LSI is ready */
bogdanm 0:9b334a45a8ff 414 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 415 {
bogdanm 0:9b334a45a8ff 416 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 417 {
bogdanm 0:9b334a45a8ff 418 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 419 }
bogdanm 0:9b334a45a8ff 420 }
bogdanm 0:9b334a45a8ff 421 }
bogdanm 0:9b334a45a8ff 422 else
bogdanm 0:9b334a45a8ff 423 {
bogdanm 0:9b334a45a8ff 424 /* Disable the Internal Low Speed oscillator (LSI). */
bogdanm 0:9b334a45a8ff 425 __HAL_RCC_LSI_DISABLE();
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 428 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 /* Wait till LSI is disabled */
bogdanm 0:9b334a45a8ff 431 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
bogdanm 0:9b334a45a8ff 432 {
bogdanm 0:9b334a45a8ff 433 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 434 {
bogdanm 0:9b334a45a8ff 435 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 436 }
bogdanm 0:9b334a45a8ff 437 }
bogdanm 0:9b334a45a8ff 438 }
bogdanm 0:9b334a45a8ff 439 }
bogdanm 0:9b334a45a8ff 440 /*------------------------------ LSE Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 441 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
bogdanm 0:9b334a45a8ff 442 {
bogdanm 0:9b334a45a8ff 443 /* Check the parameters */
bogdanm 0:9b334a45a8ff 444 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /* Enable Power Clock*/
bogdanm 0:9b334a45a8ff 447 __HAL_RCC_PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 /* Enable write access to Backup domain */
bogdanm 0:9b334a45a8ff 450 SET_BIT(PWR->CR, PWR_CR_DBP);
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 /* Wait for Backup domain Write protection disable */
bogdanm 0:9b334a45a8ff 453 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm 0:9b334a45a8ff 456 {
bogdanm 0:9b334a45a8ff 457 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 458 {
bogdanm 0:9b334a45a8ff 459 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 460 }
bogdanm 0:9b334a45a8ff 461 }
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
bogdanm 0:9b334a45a8ff 464 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 467 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /* Wait till LSE is disabled */
bogdanm 0:9b334a45a8ff 470 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm 0:9b334a45a8ff 471 {
bogdanm 0:9b334a45a8ff 472 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 473 {
bogdanm 0:9b334a45a8ff 474 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 475 }
bogdanm 0:9b334a45a8ff 476 }
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 /* Set the new LSE configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 479 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
bogdanm 0:9b334a45a8ff 480 /* Check the LSE State */
bogdanm 0:9b334a45a8ff 481 if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
bogdanm 0:9b334a45a8ff 482 {
bogdanm 0:9b334a45a8ff 483 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 484 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 487 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm 0:9b334a45a8ff 488 {
bogdanm 0:9b334a45a8ff 489 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 490 {
bogdanm 0:9b334a45a8ff 491 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 492 }
bogdanm 0:9b334a45a8ff 493 }
bogdanm 0:9b334a45a8ff 494 }
bogdanm 0:9b334a45a8ff 495 else
bogdanm 0:9b334a45a8ff 496 {
bogdanm 0:9b334a45a8ff 497 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 498 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 /* Wait till LSE is disabled */
bogdanm 0:9b334a45a8ff 501 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm 0:9b334a45a8ff 502 {
bogdanm 0:9b334a45a8ff 503 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 504 {
bogdanm 0:9b334a45a8ff 505 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 506 }
bogdanm 0:9b334a45a8ff 507 }
bogdanm 0:9b334a45a8ff 508 }
bogdanm 0:9b334a45a8ff 509 }
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 /*----------------------------- HSI14 Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 512 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
bogdanm 0:9b334a45a8ff 513 {
bogdanm 0:9b334a45a8ff 514 /* Check the parameters */
bogdanm 0:9b334a45a8ff 515 assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
bogdanm 0:9b334a45a8ff 516 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 /* Check the HSI14 State */
bogdanm 0:9b334a45a8ff 519 if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
bogdanm 0:9b334a45a8ff 520 {
bogdanm 0:9b334a45a8ff 521 /* Disable ADC control of the Internal High Speed oscillator HSI14 */
bogdanm 0:9b334a45a8ff 522 __HAL_RCC_HSI14ADC_DISABLE();
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /* Enable the Internal High Speed oscillator (HSI). */
bogdanm 0:9b334a45a8ff 525 __HAL_RCC_HSI14_ENABLE();
bogdanm 0:9b334a45a8ff 526
bogdanm 0:9b334a45a8ff 527 /* Get timeout */
bogdanm 0:9b334a45a8ff 528 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /* Wait till HSI is ready */
bogdanm 0:9b334a45a8ff 531 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
bogdanm 0:9b334a45a8ff 532 {
bogdanm 0:9b334a45a8ff 533 if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 534 {
bogdanm 0:9b334a45a8ff 535 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 536 }
bogdanm 0:9b334a45a8ff 537 }
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
bogdanm 0:9b334a45a8ff 540 __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
bogdanm 0:9b334a45a8ff 541 }
bogdanm 0:9b334a45a8ff 542 else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
bogdanm 0:9b334a45a8ff 543 {
bogdanm 0:9b334a45a8ff 544 /* Enable ADC control of the Internal High Speed oscillator HSI14 */
bogdanm 0:9b334a45a8ff 545 __HAL_RCC_HSI14ADC_ENABLE();
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
bogdanm 0:9b334a45a8ff 548 __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
bogdanm 0:9b334a45a8ff 549 }
bogdanm 0:9b334a45a8ff 550 else
bogdanm 0:9b334a45a8ff 551 {
bogdanm 0:9b334a45a8ff 552 /* Disable ADC control of the Internal High Speed oscillator HSI14 */
bogdanm 0:9b334a45a8ff 553 __HAL_RCC_HSI14ADC_DISABLE();
bogdanm 0:9b334a45a8ff 554
bogdanm 0:9b334a45a8ff 555 /* Disable the Internal High Speed oscillator (HSI). */
bogdanm 0:9b334a45a8ff 556 __HAL_RCC_HSI14_DISABLE();
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558 /* Get timeout */
bogdanm 0:9b334a45a8ff 559 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 /* Wait till HSI is ready */
bogdanm 0:9b334a45a8ff 562 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
bogdanm 0:9b334a45a8ff 563 {
bogdanm 0:9b334a45a8ff 564 if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 565 {
bogdanm 0:9b334a45a8ff 566 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 567 }
bogdanm 0:9b334a45a8ff 568 }
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570 }
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 #if defined(RCC_CR2_HSI48ON)
bogdanm 0:9b334a45a8ff 573 /*----------------------------- HSI48 Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 574 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
bogdanm 0:9b334a45a8ff 575 {
bogdanm 0:9b334a45a8ff 576 /* Check the parameters */
bogdanm 0:9b334a45a8ff 577 assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /* When the HSI48 is used as system clock it is not allowed to be disabled */
bogdanm 0:9b334a45a8ff 580 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||
bogdanm 0:9b334a45a8ff 581 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
bogdanm 0:9b334a45a8ff 582 {
bogdanm 0:9b334a45a8ff 583 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))
bogdanm 0:9b334a45a8ff 584 {
bogdanm 0:9b334a45a8ff 585 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 586 }
bogdanm 0:9b334a45a8ff 587 }
bogdanm 0:9b334a45a8ff 588 else
bogdanm 0:9b334a45a8ff 589 {
bogdanm 0:9b334a45a8ff 590 /* Check the HSI State */
bogdanm 0:9b334a45a8ff 591 if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
bogdanm 0:9b334a45a8ff 592 {
bogdanm 0:9b334a45a8ff 593 /* Enable the Internal High Speed oscillator (HSI48). */
bogdanm 0:9b334a45a8ff 594 __HAL_RCC_HSI48_ENABLE();
bogdanm 0:9b334a45a8ff 595
bogdanm 0:9b334a45a8ff 596 /* Get timeout */
bogdanm 0:9b334a45a8ff 597 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 598
bogdanm 0:9b334a45a8ff 599 /* Wait till HSI is ready */
bogdanm 0:9b334a45a8ff 600 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
bogdanm 0:9b334a45a8ff 601 {
bogdanm 0:9b334a45a8ff 602 if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 603 {
bogdanm 0:9b334a45a8ff 604 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 605 }
bogdanm 0:9b334a45a8ff 606 }
bogdanm 0:9b334a45a8ff 607 }
bogdanm 0:9b334a45a8ff 608 else
bogdanm 0:9b334a45a8ff 609 {
bogdanm 0:9b334a45a8ff 610 /* Disable the Internal High Speed oscillator (HSI48). */
bogdanm 0:9b334a45a8ff 611 __HAL_RCC_HSI48_DISABLE();
bogdanm 0:9b334a45a8ff 612
bogdanm 0:9b334a45a8ff 613 /* Get timeout */
bogdanm 0:9b334a45a8ff 614 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 /* Wait till HSI is ready */
bogdanm 0:9b334a45a8ff 617 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
bogdanm 0:9b334a45a8ff 618 {
bogdanm 0:9b334a45a8ff 619 if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 620 {
bogdanm 0:9b334a45a8ff 621 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 622 }
bogdanm 0:9b334a45a8ff 623 }
bogdanm 0:9b334a45a8ff 624 }
bogdanm 0:9b334a45a8ff 625 }
bogdanm 0:9b334a45a8ff 626 }
bogdanm 0:9b334a45a8ff 627 #endif /* RCC_CR2_HSI48ON */
bogdanm 0:9b334a45a8ff 628
bogdanm 0:9b334a45a8ff 629 /*-------------------------------- PLL Configuration -----------------------*/
bogdanm 0:9b334a45a8ff 630 /* Check the parameters */
bogdanm 0:9b334a45a8ff 631 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
bogdanm 0:9b334a45a8ff 632 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
bogdanm 0:9b334a45a8ff 633 {
bogdanm 0:9b334a45a8ff 634 /* Check if the PLL is used as system clock or not */
bogdanm 0:9b334a45a8ff 635 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm 0:9b334a45a8ff 636 {
bogdanm 0:9b334a45a8ff 637 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
bogdanm 0:9b334a45a8ff 638 {
bogdanm 0:9b334a45a8ff 639 /* Check the parameters */
bogdanm 0:9b334a45a8ff 640 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
bogdanm 0:9b334a45a8ff 641 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
bogdanm 0:9b334a45a8ff 642 assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 /* Disable the main PLL. */
bogdanm 0:9b334a45a8ff 645 __HAL_RCC_PLL_DISABLE();
bogdanm 0:9b334a45a8ff 646
bogdanm 0:9b334a45a8ff 647 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 648 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 649
bogdanm 0:9b334a45a8ff 650 /* Wait till PLL is disabled */
bogdanm 0:9b334a45a8ff 651 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm 0:9b334a45a8ff 652 {
bogdanm 0:9b334a45a8ff 653 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 654 {
bogdanm 0:9b334a45a8ff 655 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 656 }
bogdanm 0:9b334a45a8ff 657 }
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 /* Configure the main PLL clock source, predivider and multiplication factor. */
bogdanm 0:9b334a45a8ff 660 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
bogdanm 0:9b334a45a8ff 661 RCC_OscInitStruct->PLL.PREDIV,
bogdanm 0:9b334a45a8ff 662 RCC_OscInitStruct->PLL.PLLMUL);
bogdanm 0:9b334a45a8ff 663 /* Enable the main PLL. */
bogdanm 0:9b334a45a8ff 664 __HAL_RCC_PLL_ENABLE();
bogdanm 0:9b334a45a8ff 665
bogdanm 0:9b334a45a8ff 666 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 667 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 668
bogdanm 0:9b334a45a8ff 669 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 670 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 671 {
bogdanm 0:9b334a45a8ff 672 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 675 }
bogdanm 0:9b334a45a8ff 676 }
bogdanm 0:9b334a45a8ff 677 }
bogdanm 0:9b334a45a8ff 678 else
bogdanm 0:9b334a45a8ff 679 {
bogdanm 0:9b334a45a8ff 680 /* Disable the main PLL. */
bogdanm 0:9b334a45a8ff 681 __HAL_RCC_PLL_DISABLE();
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 684 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 685
bogdanm 0:9b334a45a8ff 686 /* Wait till PLL is disabled */
bogdanm 0:9b334a45a8ff 687 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm 0:9b334a45a8ff 688 {
bogdanm 0:9b334a45a8ff 689 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 690 {
bogdanm 0:9b334a45a8ff 691 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 692 }
bogdanm 0:9b334a45a8ff 693 }
bogdanm 0:9b334a45a8ff 694 }
bogdanm 0:9b334a45a8ff 695 }
bogdanm 0:9b334a45a8ff 696 else
bogdanm 0:9b334a45a8ff 697 {
bogdanm 0:9b334a45a8ff 698 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 699 }
bogdanm 0:9b334a45a8ff 700 }
bogdanm 0:9b334a45a8ff 701
bogdanm 0:9b334a45a8ff 702 return HAL_OK;
bogdanm 0:9b334a45a8ff 703 }
bogdanm 0:9b334a45a8ff 704
bogdanm 0:9b334a45a8ff 705 /**
bogdanm 0:9b334a45a8ff 706 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
bogdanm 0:9b334a45a8ff 707 * parameters in the RCC_ClkInitStruct.
bogdanm 0:9b334a45a8ff 708 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 709 * contains the configuration information for the RCC peripheral.
bogdanm 0:9b334a45a8ff 710 * @param FLatency: FLASH Latency
bogdanm 0:9b334a45a8ff 711 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 712 * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
bogdanm 0:9b334a45a8ff 713 * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle
bogdanm 0:9b334a45a8ff 714 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
bogdanm 0:9b334a45a8ff 715 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
bogdanm 0:9b334a45a8ff 716 *
bogdanm 0:9b334a45a8ff 717 * @note The HSI is used (enabled by hardware) as system clock source after
bogdanm 0:9b334a45a8ff 718 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
bogdanm 0:9b334a45a8ff 719 * of failure of the HSE used directly or indirectly as system clock
bogdanm 0:9b334a45a8ff 720 * (if the Clock Security System CSS is enabled).
bogdanm 0:9b334a45a8ff 721 *
bogdanm 0:9b334a45a8ff 722 * @note A switch from one clock source to another occurs only if the target
bogdanm 0:9b334a45a8ff 723 * clock source is ready (clock stable after startup delay or PLL locked).
bogdanm 0:9b334a45a8ff 724 * If a clock source which is not yet ready is selected, the switch will
bogdanm 0:9b334a45a8ff 725 * occur when the clock source will be ready.
bogdanm 0:9b334a45a8ff 726 * You can use HAL_RCC_GetClockConfig() function to know which clock is
bogdanm 0:9b334a45a8ff 727 * currently used as system clock source.
bogdanm 0:9b334a45a8ff 728 * @retval HAL status
bogdanm 0:9b334a45a8ff 729 */
bogdanm 0:9b334a45a8ff 730 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
bogdanm 0:9b334a45a8ff 731 {
bogdanm 0:9b334a45a8ff 732 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 733
bogdanm 0:9b334a45a8ff 734 /* Check the parameters */
bogdanm 0:9b334a45a8ff 735 assert_param(RCC_ClkInitStruct != NULL);
bogdanm 0:9b334a45a8ff 736 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
bogdanm 0:9b334a45a8ff 737 assert_param(IS_FLASH_LATENCY(FLatency));
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
bogdanm 0:9b334a45a8ff 740 must be correctly programmed according to the frequency of the CPU clock
bogdanm 0:9b334a45a8ff 741 (HCLK) of the device. */
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743 /* Increasing the CPU frequency */
bogdanm 0:9b334a45a8ff 744 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
bogdanm 0:9b334a45a8ff 745 {
bogdanm 0:9b334a45a8ff 746 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
bogdanm 0:9b334a45a8ff 747 __HAL_FLASH_SET_LATENCY(FLatency);
bogdanm 0:9b334a45a8ff 748
bogdanm 0:9b334a45a8ff 749 /* Check that the new number of wait states is taken into account to access the Flash
bogdanm 0:9b334a45a8ff 750 memory by reading the FLASH_ACR register */
bogdanm 0:9b334a45a8ff 751 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
bogdanm 0:9b334a45a8ff 752 {
bogdanm 0:9b334a45a8ff 753 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 754 }
bogdanm 0:9b334a45a8ff 755
bogdanm 0:9b334a45a8ff 756 /*-------------------------- HCLK Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 757 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
bogdanm 0:9b334a45a8ff 758 {
bogdanm 0:9b334a45a8ff 759 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
bogdanm 0:9b334a45a8ff 760 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
bogdanm 0:9b334a45a8ff 761 }
bogdanm 0:9b334a45a8ff 762
bogdanm 0:9b334a45a8ff 763 /*------------------------- SYSCLK Configuration ---------------------------*/
bogdanm 0:9b334a45a8ff 764 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
bogdanm 0:9b334a45a8ff 765 {
bogdanm 0:9b334a45a8ff 766 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
bogdanm 0:9b334a45a8ff 767
bogdanm 0:9b334a45a8ff 768 /* HSE is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 769 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 770 {
bogdanm 0:9b334a45a8ff 771 /* Check the HSE ready flag */
bogdanm 0:9b334a45a8ff 772 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm 0:9b334a45a8ff 773 {
bogdanm 0:9b334a45a8ff 774 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 775 }
bogdanm 0:9b334a45a8ff 776 }
bogdanm 0:9b334a45a8ff 777 /* PLL is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 778 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 779 {
bogdanm 0:9b334a45a8ff 780 /* Check the PLL ready flag */
bogdanm 0:9b334a45a8ff 781 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 782 {
bogdanm 0:9b334a45a8ff 783 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 784 }
bogdanm 0:9b334a45a8ff 785 }
bogdanm 0:9b334a45a8ff 786 #if defined(RCC_CR2_HSI48ON)
bogdanm 0:9b334a45a8ff 787 /* HSI48 is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 788 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
bogdanm 0:9b334a45a8ff 789 {
bogdanm 0:9b334a45a8ff 790 /* Check the HSI48 ready flag */
bogdanm 0:9b334a45a8ff 791 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
bogdanm 0:9b334a45a8ff 792 {
bogdanm 0:9b334a45a8ff 793 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 794 }
bogdanm 0:9b334a45a8ff 795 }
bogdanm 0:9b334a45a8ff 796 #endif /* RCC_CR2_HSI48ON */
bogdanm 0:9b334a45a8ff 797 /* HSI is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 798 else
bogdanm 0:9b334a45a8ff 799 {
bogdanm 0:9b334a45a8ff 800 /* Check the HSI ready flag */
bogdanm 0:9b334a45a8ff 801 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 802 {
bogdanm 0:9b334a45a8ff 803 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 804 }
bogdanm 0:9b334a45a8ff 805 }
bogdanm 0:9b334a45a8ff 806 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
bogdanm 0:9b334a45a8ff 807
bogdanm 0:9b334a45a8ff 808 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 809 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 810
bogdanm 0:9b334a45a8ff 811 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 812 {
bogdanm 0:9b334a45a8ff 813 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm 0:9b334a45a8ff 814 {
bogdanm 0:9b334a45a8ff 815 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 816 {
bogdanm 0:9b334a45a8ff 817 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 818 }
bogdanm 0:9b334a45a8ff 819 }
bogdanm 0:9b334a45a8ff 820 }
bogdanm 0:9b334a45a8ff 821 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 822 {
bogdanm 0:9b334a45a8ff 823 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm 0:9b334a45a8ff 824 {
bogdanm 0:9b334a45a8ff 825 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 826 {
bogdanm 0:9b334a45a8ff 827 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 828 }
bogdanm 0:9b334a45a8ff 829 }
bogdanm 0:9b334a45a8ff 830 }
bogdanm 0:9b334a45a8ff 831 #if defined(RCC_CR2_HSI48ON)
bogdanm 0:9b334a45a8ff 832 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
bogdanm 0:9b334a45a8ff 833 {
bogdanm 0:9b334a45a8ff 834 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48)
bogdanm 0:9b334a45a8ff 835 {
bogdanm 0:9b334a45a8ff 836 if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 837 {
bogdanm 0:9b334a45a8ff 838 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 839 }
bogdanm 0:9b334a45a8ff 840 }
bogdanm 0:9b334a45a8ff 841 }
bogdanm 0:9b334a45a8ff 842 #endif /* RCC_CR2_HSI48ON */
bogdanm 0:9b334a45a8ff 843 else
bogdanm 0:9b334a45a8ff 844 {
bogdanm 0:9b334a45a8ff 845 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm 0:9b334a45a8ff 846 {
bogdanm 0:9b334a45a8ff 847 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 848 {
bogdanm 0:9b334a45a8ff 849 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 850 }
bogdanm 0:9b334a45a8ff 851 }
bogdanm 0:9b334a45a8ff 852 }
bogdanm 0:9b334a45a8ff 853 }
bogdanm 0:9b334a45a8ff 854 }
bogdanm 0:9b334a45a8ff 855 /* Decreasing the CPU frequency */
bogdanm 0:9b334a45a8ff 856 else
bogdanm 0:9b334a45a8ff 857 {
bogdanm 0:9b334a45a8ff 858 /*-------------------------- HCLK Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 859 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
bogdanm 0:9b334a45a8ff 860 {
bogdanm 0:9b334a45a8ff 861 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
bogdanm 0:9b334a45a8ff 862 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
bogdanm 0:9b334a45a8ff 863 }
bogdanm 0:9b334a45a8ff 864
bogdanm 0:9b334a45a8ff 865 /*------------------------- SYSCLK Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 866 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
bogdanm 0:9b334a45a8ff 867 {
bogdanm 0:9b334a45a8ff 868 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
bogdanm 0:9b334a45a8ff 869
bogdanm 0:9b334a45a8ff 870 /* HSE is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 871 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 872 {
bogdanm 0:9b334a45a8ff 873 /* Check the HSE ready flag */
bogdanm 0:9b334a45a8ff 874 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm 0:9b334a45a8ff 875 {
bogdanm 0:9b334a45a8ff 876 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 877 }
bogdanm 0:9b334a45a8ff 878 }
bogdanm 0:9b334a45a8ff 879 /* PLL is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 880 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 881 {
bogdanm 0:9b334a45a8ff 882 /* Check the PLL ready flag */
bogdanm 0:9b334a45a8ff 883 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 884 {
bogdanm 0:9b334a45a8ff 885 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 886 }
bogdanm 0:9b334a45a8ff 887 }
bogdanm 0:9b334a45a8ff 888 #if defined(RCC_CR2_HSI48ON)
bogdanm 0:9b334a45a8ff 889 /* HSI48 is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 890 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
bogdanm 0:9b334a45a8ff 891 {
bogdanm 0:9b334a45a8ff 892 /* Check the HSI48 ready flag */
bogdanm 0:9b334a45a8ff 893 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
bogdanm 0:9b334a45a8ff 894 {
bogdanm 0:9b334a45a8ff 895 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 896 }
bogdanm 0:9b334a45a8ff 897 }
bogdanm 0:9b334a45a8ff 898 #endif /* RCC_CR2_HSI48ON */
bogdanm 0:9b334a45a8ff 899 /* HSI is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 900 else
bogdanm 0:9b334a45a8ff 901 {
bogdanm 0:9b334a45a8ff 902 /* Check the HSI ready flag */
bogdanm 0:9b334a45a8ff 903 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 904 {
bogdanm 0:9b334a45a8ff 905 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 906 }
bogdanm 0:9b334a45a8ff 907 }
bogdanm 0:9b334a45a8ff 908 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
bogdanm 0:9b334a45a8ff 909
bogdanm 0:9b334a45a8ff 910 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 911 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 912
bogdanm 0:9b334a45a8ff 913 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 914 {
bogdanm 0:9b334a45a8ff 915 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm 0:9b334a45a8ff 916 {
bogdanm 0:9b334a45a8ff 917 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 918 {
bogdanm 0:9b334a45a8ff 919 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 920 }
bogdanm 0:9b334a45a8ff 921 }
bogdanm 0:9b334a45a8ff 922 }
bogdanm 0:9b334a45a8ff 923 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 924 {
bogdanm 0:9b334a45a8ff 925 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm 0:9b334a45a8ff 926 {
bogdanm 0:9b334a45a8ff 927 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 928 {
bogdanm 0:9b334a45a8ff 929 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 930 }
bogdanm 0:9b334a45a8ff 931 }
bogdanm 0:9b334a45a8ff 932 }
bogdanm 0:9b334a45a8ff 933 #if defined(RCC_CR2_HSI48ON)
bogdanm 0:9b334a45a8ff 934 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
bogdanm 0:9b334a45a8ff 935 {
bogdanm 0:9b334a45a8ff 936 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48)
bogdanm 0:9b334a45a8ff 937 {
bogdanm 0:9b334a45a8ff 938 if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 939 {
bogdanm 0:9b334a45a8ff 940 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 941 }
bogdanm 0:9b334a45a8ff 942 }
bogdanm 0:9b334a45a8ff 943 }
bogdanm 0:9b334a45a8ff 944 #endif /* RCC_CR2_HSI48ON */
bogdanm 0:9b334a45a8ff 945 else
bogdanm 0:9b334a45a8ff 946 {
bogdanm 0:9b334a45a8ff 947 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm 0:9b334a45a8ff 948 {
bogdanm 0:9b334a45a8ff 949 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 950 {
bogdanm 0:9b334a45a8ff 951 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 952 }
bogdanm 0:9b334a45a8ff 953 }
bogdanm 0:9b334a45a8ff 954 }
bogdanm 0:9b334a45a8ff 955 }
bogdanm 0:9b334a45a8ff 956
bogdanm 0:9b334a45a8ff 957 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
bogdanm 0:9b334a45a8ff 958 __HAL_FLASH_SET_LATENCY(FLatency);
bogdanm 0:9b334a45a8ff 959
bogdanm 0:9b334a45a8ff 960 /* Check that the new number of wait states is taken into account to access the Flash
bogdanm 0:9b334a45a8ff 961 memory by reading the FLASH_ACR register */
bogdanm 0:9b334a45a8ff 962 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
bogdanm 0:9b334a45a8ff 963 {
bogdanm 0:9b334a45a8ff 964 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 965 }
bogdanm 0:9b334a45a8ff 966 }
bogdanm 0:9b334a45a8ff 967
bogdanm 0:9b334a45a8ff 968 /*-------------------------- PCLK1 Configuration ---------------------------*/
bogdanm 0:9b334a45a8ff 969 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
bogdanm 0:9b334a45a8ff 970 {
bogdanm 0:9b334a45a8ff 971 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
bogdanm 0:9b334a45a8ff 972 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
bogdanm 0:9b334a45a8ff 973 }
bogdanm 0:9b334a45a8ff 974
bogdanm 0:9b334a45a8ff 975 /* Configure the source of time base considering new system clocks settings*/
bogdanm 0:9b334a45a8ff 976 HAL_InitTick (TICK_INT_PRIORITY);
bogdanm 0:9b334a45a8ff 977
bogdanm 0:9b334a45a8ff 978 return HAL_OK;
bogdanm 0:9b334a45a8ff 979 }
bogdanm 0:9b334a45a8ff 980
bogdanm 0:9b334a45a8ff 981 /**
bogdanm 0:9b334a45a8ff 982 * @}
bogdanm 0:9b334a45a8ff 983 */
bogdanm 0:9b334a45a8ff 984
bogdanm 0:9b334a45a8ff 985 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
bogdanm 0:9b334a45a8ff 986 * @brief RCC clocks control functions
bogdanm 0:9b334a45a8ff 987 *
bogdanm 0:9b334a45a8ff 988 @verbatim
bogdanm 0:9b334a45a8ff 989 ===============================================================================
bogdanm 0:9b334a45a8ff 990 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 991 ===============================================================================
bogdanm 0:9b334a45a8ff 992 [..]
bogdanm 0:9b334a45a8ff 993 This subsection provides a set of functions allowing to control the RCC Clocks
bogdanm 0:9b334a45a8ff 994 frequencies.
bogdanm 0:9b334a45a8ff 995
bogdanm 0:9b334a45a8ff 996 @endverbatim
bogdanm 0:9b334a45a8ff 997 * @{
bogdanm 0:9b334a45a8ff 998 */
bogdanm 0:9b334a45a8ff 999
bogdanm 0:9b334a45a8ff 1000 /**
bogdanm 0:9b334a45a8ff 1001 * @brief Selects the clock source to output on MCO pin.
bogdanm 0:9b334a45a8ff 1002 * @note MCO pin should be configured in alternate function mode.
bogdanm 0:9b334a45a8ff 1003 * @param RCC_MCOx: specifies the output direction for the clock source.
bogdanm 0:9b334a45a8ff 1004 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1005 * @arg RCC_MCO: Clock source to output on MCO1 pin(PA8).
bogdanm 0:9b334a45a8ff 1006 * @param RCC_MCOSource: specifies the clock source to output.
bogdanm 0:9b334a45a8ff 1007 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1008 * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm 0:9b334a45a8ff 1009 * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm 0:9b334a45a8ff 1010 * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm 0:9b334a45a8ff 1011 * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm 0:9b334a45a8ff 1012 * @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock (not applicable to STM32F05x devices)
bogdanm 0:9b334a45a8ff 1013 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm 0:9b334a45a8ff 1014 * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm 0:9b334a45a8ff 1015 * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
bogdanm 0:9b334a45a8ff 1016 * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
bogdanm 0:9b334a45a8ff 1017 * @param RCC_MCODiv: specifies the MCO DIV.
bogdanm 0:9b334a45a8ff 1018 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1019 * @arg RCC_MCODIV_1: no division applied to MCO clock
bogdanm 0:9b334a45a8ff 1020 * @retval None
bogdanm 0:9b334a45a8ff 1021 */
bogdanm 0:9b334a45a8ff 1022 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
bogdanm 0:9b334a45a8ff 1023 {
bogdanm 0:9b334a45a8ff 1024 GPIO_InitTypeDef gpio;
bogdanm 0:9b334a45a8ff 1025
bogdanm 0:9b334a45a8ff 1026 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1027 assert_param(IS_RCC_MCO(RCC_MCOx));
bogdanm 0:9b334a45a8ff 1028 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
bogdanm 0:9b334a45a8ff 1029 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
bogdanm 0:9b334a45a8ff 1030
bogdanm 0:9b334a45a8ff 1031 /* MCO Clock Enable */
bogdanm 0:9b334a45a8ff 1032 MCO1_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 1033
bogdanm 0:9b334a45a8ff 1034 /* Configure the MCO1 pin in alternate function mode */
bogdanm 0:9b334a45a8ff 1035 gpio.Pin = MCO1_PIN;
bogdanm 0:9b334a45a8ff 1036 gpio.Mode = GPIO_MODE_AF_PP;
bogdanm 0:9b334a45a8ff 1037 gpio.Speed = GPIO_SPEED_HIGH;
bogdanm 0:9b334a45a8ff 1038 gpio.Pull = GPIO_NOPULL;
bogdanm 0:9b334a45a8ff 1039 gpio.Alternate = GPIO_AF0_MCO;
bogdanm 0:9b334a45a8ff 1040 HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
bogdanm 0:9b334a45a8ff 1041
bogdanm 0:9b334a45a8ff 1042 /* Configure the MCO clock source */
bogdanm 0:9b334a45a8ff 1043 __HAL_RCC_MCO_CONFIG(RCC_MCOSource, RCC_MCODiv);
bogdanm 0:9b334a45a8ff 1044 }
bogdanm 0:9b334a45a8ff 1045
bogdanm 0:9b334a45a8ff 1046 /**
bogdanm 0:9b334a45a8ff 1047 * @brief Enables the Clock Security System.
bogdanm 0:9b334a45a8ff 1048 * @note If a failure is detected on the HSE oscillator clock, this oscillator
bogdanm 0:9b334a45a8ff 1049 * is automatically disabled and an interrupt is generated to inform the
bogdanm 0:9b334a45a8ff 1050 * software about the failure (Clock Security System Interrupt, CSSI),
bogdanm 0:9b334a45a8ff 1051 * allowing the MCU to perform rescue operations. The CSSI is linked to
bogdanm 0:9b334a45a8ff 1052 * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
bogdanm 0:9b334a45a8ff 1053 * @retval None
bogdanm 0:9b334a45a8ff 1054 */
bogdanm 0:9b334a45a8ff 1055 void HAL_RCC_EnableCSS(void)
bogdanm 0:9b334a45a8ff 1056 {
bogdanm 0:9b334a45a8ff 1057 SET_BIT(RCC->CR, RCC_CR_CSSON) ;
bogdanm 0:9b334a45a8ff 1058 }
bogdanm 0:9b334a45a8ff 1059
bogdanm 0:9b334a45a8ff 1060 /**
bogdanm 0:9b334a45a8ff 1061 * @brief Disables the Clock Security System.
bogdanm 0:9b334a45a8ff 1062 * @retval None
bogdanm 0:9b334a45a8ff 1063 */
bogdanm 0:9b334a45a8ff 1064 void HAL_RCC_DisableCSS(void)
bogdanm 0:9b334a45a8ff 1065 {
bogdanm 0:9b334a45a8ff 1066 CLEAR_BIT(RCC->CR, RCC_CR_CSSON) ;
bogdanm 0:9b334a45a8ff 1067 }
bogdanm 0:9b334a45a8ff 1068
bogdanm 0:9b334a45a8ff 1069 /**
bogdanm 0:9b334a45a8ff 1070 * @brief Returns the SYSCLK frequency
bogdanm 0:9b334a45a8ff 1071 *
bogdanm 0:9b334a45a8ff 1072 * @note The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 1073 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 1074 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 1075 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 1076 * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
bogdanm 0:9b334a45a8ff 1077 * divided by PREDIV factor(**)
bogdanm 0:9b334a45a8ff 1078 * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
bogdanm 0:9b334a45a8ff 1079 * divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based
bogdanm 0:9b334a45a8ff 1080 * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the
bogdanm 0:9b334a45a8ff 1081 * PLL factor .
bogdanm 0:9b334a45a8ff 1082 * @note (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
bogdanm 0:9b334a45a8ff 1083 * 8 MHz) but the real value may vary depending on the variations
bogdanm 0:9b334a45a8ff 1084 * in voltage and temperature.
bogdanm 0:9b334a45a8ff 1085 * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
bogdanm 0:9b334a45a8ff 1086 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm 0:9b334a45a8ff 1087 * frequency of the crystal used. Otherwise, this function may
bogdanm 0:9b334a45a8ff 1088 * have wrong result.
bogdanm 0:9b334a45a8ff 1089 *
bogdanm 0:9b334a45a8ff 1090 * @note The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 1091 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 1092 *
bogdanm 0:9b334a45a8ff 1093 * @note This function can be used by the user application to compute the
bogdanm 0:9b334a45a8ff 1094 * baudrate for the communication peripherals or configure other parameters.
bogdanm 0:9b334a45a8ff 1095 *
bogdanm 0:9b334a45a8ff 1096 * @note Each time SYSCLK changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 1097 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 1098 *
bogdanm 0:9b334a45a8ff 1099 *
bogdanm 0:9b334a45a8ff 1100 * @retval SYSCLK frequency
bogdanm 0:9b334a45a8ff 1101 */
bogdanm 0:9b334a45a8ff 1102 uint32_t HAL_RCC_GetSysClockFreq(void)
bogdanm 0:9b334a45a8ff 1103 {
bogdanm 0:9b334a45a8ff 1104 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9,
bogdanm 0:9b334a45a8ff 1105 10, 11, 12, 13, 14, 15, 16, 16};
bogdanm 0:9b334a45a8ff 1106 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8,
bogdanm 0:9b334a45a8ff 1107 9,10, 11, 12, 13, 14, 15, 16};
bogdanm 0:9b334a45a8ff 1108
bogdanm 0:9b334a45a8ff 1109 uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0;
bogdanm 0:9b334a45a8ff 1110 uint32_t sysclockfreq = 0;
bogdanm 0:9b334a45a8ff 1111
bogdanm 0:9b334a45a8ff 1112 tmpreg = RCC->CFGR;
bogdanm 0:9b334a45a8ff 1113
bogdanm 0:9b334a45a8ff 1114 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1115 switch (tmpreg & RCC_CFGR_SWS)
bogdanm 0:9b334a45a8ff 1116 {
bogdanm 0:9b334a45a8ff 1117 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
bogdanm 0:9b334a45a8ff 1118 {
bogdanm 0:9b334a45a8ff 1119 sysclockfreq = HSE_VALUE;
bogdanm 0:9b334a45a8ff 1120 break;
bogdanm 0:9b334a45a8ff 1121 }
bogdanm 0:9b334a45a8ff 1122 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
bogdanm 0:9b334a45a8ff 1123 {
bogdanm 0:9b334a45a8ff 1124 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
bogdanm 0:9b334a45a8ff 1125 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
bogdanm 0:9b334a45a8ff 1126 if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
bogdanm 0:9b334a45a8ff 1127 {
bogdanm 0:9b334a45a8ff 1128 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
bogdanm 0:9b334a45a8ff 1129 pllclk = (HSE_VALUE/prediv) * pllmul;
bogdanm 0:9b334a45a8ff 1130 }
bogdanm 0:9b334a45a8ff 1131 #if defined(RCC_CR2_HSI48ON)
bogdanm 0:9b334a45a8ff 1132 else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48)
bogdanm 0:9b334a45a8ff 1133 {
bogdanm 0:9b334a45a8ff 1134 /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */
bogdanm 0:9b334a45a8ff 1135 pllclk = (HSI48_VALUE/prediv) * pllmul;
bogdanm 0:9b334a45a8ff 1136 }
bogdanm 0:9b334a45a8ff 1137 #endif /* RCC_CR2_HSI48ON */
bogdanm 0:9b334a45a8ff 1138 else
bogdanm 0:9b334a45a8ff 1139 {
bogdanm 0:9b334a45a8ff 1140 #if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
bogdanm 0:9b334a45a8ff 1141 /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
bogdanm 0:9b334a45a8ff 1142 pllclk = (HSI_VALUE/prediv) * pllmul;
bogdanm 0:9b334a45a8ff 1143 #else
bogdanm 0:9b334a45a8ff 1144 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
bogdanm 0:9b334a45a8ff 1145 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
bogdanm 0:9b334a45a8ff 1146 #endif
bogdanm 0:9b334a45a8ff 1147 }
bogdanm 0:9b334a45a8ff 1148 sysclockfreq = pllclk;
bogdanm 0:9b334a45a8ff 1149 break;
bogdanm 0:9b334a45a8ff 1150 }
bogdanm 0:9b334a45a8ff 1151 #if defined(RCC_CR2_HSI48ON)
bogdanm 0:9b334a45a8ff 1152 case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */
bogdanm 0:9b334a45a8ff 1153 {
bogdanm 0:9b334a45a8ff 1154 sysclockfreq = HSI48_VALUE;
bogdanm 0:9b334a45a8ff 1155 break;
bogdanm 0:9b334a45a8ff 1156 }
bogdanm 0:9b334a45a8ff 1157 #endif /* RCC_CR2_HSI48ON */
bogdanm 0:9b334a45a8ff 1158 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
bogdanm 0:9b334a45a8ff 1159 default: /* HSI used as system clock */
bogdanm 0:9b334a45a8ff 1160 {
bogdanm 0:9b334a45a8ff 1161 sysclockfreq = HSI_VALUE;
bogdanm 0:9b334a45a8ff 1162 break;
bogdanm 0:9b334a45a8ff 1163 }
bogdanm 0:9b334a45a8ff 1164 }
bogdanm 0:9b334a45a8ff 1165 return sysclockfreq;
bogdanm 0:9b334a45a8ff 1166 }
bogdanm 0:9b334a45a8ff 1167
bogdanm 0:9b334a45a8ff 1168 /**
bogdanm 0:9b334a45a8ff 1169 * @brief Returns the HCLK frequency
bogdanm 0:9b334a45a8ff 1170 * @note Each time HCLK changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 1171 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 1172 *
bogdanm 0:9b334a45a8ff 1173 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
bogdanm 0:9b334a45a8ff 1174 * and updated within this function
bogdanm 0:9b334a45a8ff 1175 * @retval HCLK frequency
bogdanm 0:9b334a45a8ff 1176 */
bogdanm 0:9b334a45a8ff 1177 uint32_t HAL_RCC_GetHCLKFreq(void)
bogdanm 0:9b334a45a8ff 1178 {
bogdanm 0:9b334a45a8ff 1179 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
bogdanm 0:9b334a45a8ff 1180 return SystemCoreClock;
bogdanm 0:9b334a45a8ff 1181 }
bogdanm 0:9b334a45a8ff 1182
bogdanm 0:9b334a45a8ff 1183 /**
bogdanm 0:9b334a45a8ff 1184 * @brief Returns the PCLK1 frequency
bogdanm 0:9b334a45a8ff 1185 * @note Each time PCLK1 changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 1186 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 1187 * @retval PCLK1 frequency
bogdanm 0:9b334a45a8ff 1188 */
bogdanm 0:9b334a45a8ff 1189 uint32_t HAL_RCC_GetPCLK1Freq(void)
bogdanm 0:9b334a45a8ff 1190 {
bogdanm 0:9b334a45a8ff 1191 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
bogdanm 0:9b334a45a8ff 1192 return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]);
bogdanm 0:9b334a45a8ff 1193 }
bogdanm 0:9b334a45a8ff 1194
bogdanm 0:9b334a45a8ff 1195 /**
bogdanm 0:9b334a45a8ff 1196 * @brief Configures the RCC_OscInitStruct according to the internal
bogdanm 0:9b334a45a8ff 1197 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 1198 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 1199 * will be configured.
bogdanm 0:9b334a45a8ff 1200 * @retval None
bogdanm 0:9b334a45a8ff 1201 */
bogdanm 0:9b334a45a8ff 1202 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm 0:9b334a45a8ff 1203 {
bogdanm 0:9b334a45a8ff 1204 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1205 assert_param(RCC_OscInitStruct != NULL);
bogdanm 0:9b334a45a8ff 1206
bogdanm 0:9b334a45a8ff 1207 /* Set all possible values for the Oscillator type parameter ---------------*/
bogdanm 0:9b334a45a8ff 1208 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
bogdanm 0:9b334a45a8ff 1209 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI14;
bogdanm 0:9b334a45a8ff 1210 #if defined(RCC_CR2_HSI48ON)
bogdanm 0:9b334a45a8ff 1211 RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
bogdanm 0:9b334a45a8ff 1212 #endif /* RCC_CR2_HSI48ON */
bogdanm 0:9b334a45a8ff 1213
bogdanm 0:9b334a45a8ff 1214 /* Get the HSE configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1215 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
bogdanm 0:9b334a45a8ff 1216 {
bogdanm 0:9b334a45a8ff 1217 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
bogdanm 0:9b334a45a8ff 1218 }
bogdanm 0:9b334a45a8ff 1219 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
bogdanm 0:9b334a45a8ff 1220 {
bogdanm 0:9b334a45a8ff 1221 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
bogdanm 0:9b334a45a8ff 1222 }
bogdanm 0:9b334a45a8ff 1223 else
bogdanm 0:9b334a45a8ff 1224 {
bogdanm 0:9b334a45a8ff 1225 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
bogdanm 0:9b334a45a8ff 1226 }
bogdanm 0:9b334a45a8ff 1227
bogdanm 0:9b334a45a8ff 1228 /* Get the HSI configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1229 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
bogdanm 0:9b334a45a8ff 1230 {
bogdanm 0:9b334a45a8ff 1231 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
bogdanm 0:9b334a45a8ff 1232 }
bogdanm 0:9b334a45a8ff 1233 else
bogdanm 0:9b334a45a8ff 1234 {
bogdanm 0:9b334a45a8ff 1235 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
bogdanm 0:9b334a45a8ff 1236 }
bogdanm 0:9b334a45a8ff 1237
bogdanm 0:9b334a45a8ff 1238 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber);
bogdanm 0:9b334a45a8ff 1239
bogdanm 0:9b334a45a8ff 1240 /* Get the LSE configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1241 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
bogdanm 0:9b334a45a8ff 1242 {
bogdanm 0:9b334a45a8ff 1243 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
bogdanm 0:9b334a45a8ff 1244 }
bogdanm 0:9b334a45a8ff 1245 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
bogdanm 0:9b334a45a8ff 1246 {
bogdanm 0:9b334a45a8ff 1247 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
bogdanm 0:9b334a45a8ff 1248 }
bogdanm 0:9b334a45a8ff 1249 else
bogdanm 0:9b334a45a8ff 1250 {
bogdanm 0:9b334a45a8ff 1251 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
bogdanm 0:9b334a45a8ff 1252 }
bogdanm 0:9b334a45a8ff 1253
bogdanm 0:9b334a45a8ff 1254 /* Get the LSI configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1255 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
bogdanm 0:9b334a45a8ff 1256 {
bogdanm 0:9b334a45a8ff 1257 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
bogdanm 0:9b334a45a8ff 1258 }
bogdanm 0:9b334a45a8ff 1259 else
bogdanm 0:9b334a45a8ff 1260 {
bogdanm 0:9b334a45a8ff 1261 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
bogdanm 0:9b334a45a8ff 1262 }
bogdanm 0:9b334a45a8ff 1263
bogdanm 0:9b334a45a8ff 1264 /* Get the PLL configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1265 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
bogdanm 0:9b334a45a8ff 1266 {
bogdanm 0:9b334a45a8ff 1267 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 1268 }
bogdanm 0:9b334a45a8ff 1269 else
bogdanm 0:9b334a45a8ff 1270 {
bogdanm 0:9b334a45a8ff 1271 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
bogdanm 0:9b334a45a8ff 1272 }
bogdanm 0:9b334a45a8ff 1273 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
bogdanm 0:9b334a45a8ff 1274 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
bogdanm 0:9b334a45a8ff 1275 RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
bogdanm 0:9b334a45a8ff 1276
bogdanm 0:9b334a45a8ff 1277 /* Get the HSI14 configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1278 if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON)
bogdanm 0:9b334a45a8ff 1279 {
bogdanm 0:9b334a45a8ff 1280 RCC_OscInitStruct->HSI14State = RCC_HSI_ON;
bogdanm 0:9b334a45a8ff 1281 }
bogdanm 0:9b334a45a8ff 1282 else
bogdanm 0:9b334a45a8ff 1283 {
bogdanm 0:9b334a45a8ff 1284 RCC_OscInitStruct->HSI14State = RCC_HSI_OFF;
bogdanm 0:9b334a45a8ff 1285 }
bogdanm 0:9b334a45a8ff 1286
bogdanm 0:9b334a45a8ff 1287 RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_CR2_HSI14TRIM_BitNumber);
bogdanm 0:9b334a45a8ff 1288
bogdanm 0:9b334a45a8ff 1289 #if defined(RCC_CR2_HSI48ON)
bogdanm 0:9b334a45a8ff 1290 /* Get the HSI48 configuration if any-----------------------------------------*/
bogdanm 0:9b334a45a8ff 1291 RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE();
bogdanm 0:9b334a45a8ff 1292 #endif /* RCC_CR2_HSI48ON */
bogdanm 0:9b334a45a8ff 1293 }
bogdanm 0:9b334a45a8ff 1294
bogdanm 0:9b334a45a8ff 1295 /**
bogdanm 0:9b334a45a8ff 1296 * @brief Get the RCC_ClkInitStruct according to the internal
bogdanm 0:9b334a45a8ff 1297 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 1298 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
bogdanm 0:9b334a45a8ff 1299 * contains the current clock configuration.
bogdanm 0:9b334a45a8ff 1300 * @param pFLatency: Pointer on the Flash Latency.
bogdanm 0:9b334a45a8ff 1301 * @retval None
bogdanm 0:9b334a45a8ff 1302 */
bogdanm 0:9b334a45a8ff 1303 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
bogdanm 0:9b334a45a8ff 1304 {
bogdanm 0:9b334a45a8ff 1305 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1306 assert_param(RCC_ClkInitStruct != NULL);
bogdanm 0:9b334a45a8ff 1307 assert_param(pFLatency != NULL);
bogdanm 0:9b334a45a8ff 1308
bogdanm 0:9b334a45a8ff 1309 /* Set all possible values for the Clock type parameter --------------------*/
bogdanm 0:9b334a45a8ff 1310 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1;
bogdanm 0:9b334a45a8ff 1311
bogdanm 0:9b334a45a8ff 1312 /* Get the SYSCLK configuration --------------------------------------------*/
bogdanm 0:9b334a45a8ff 1313 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
bogdanm 0:9b334a45a8ff 1314
bogdanm 0:9b334a45a8ff 1315 /* Get the HCLK configuration ----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1316 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
bogdanm 0:9b334a45a8ff 1317
bogdanm 0:9b334a45a8ff 1318 /* Get the APB1 configuration ----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1319 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);
bogdanm 0:9b334a45a8ff 1320 /* Get the Flash Wait State (Latency) configuration ------------------------*/
bogdanm 0:9b334a45a8ff 1321 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
bogdanm 0:9b334a45a8ff 1322 }
bogdanm 0:9b334a45a8ff 1323
bogdanm 0:9b334a45a8ff 1324 /**
bogdanm 0:9b334a45a8ff 1325 * @brief This function handles the RCC CSS interrupt request.
bogdanm 0:9b334a45a8ff 1326 * @note This API should be called under the NMI_Handler().
bogdanm 0:9b334a45a8ff 1327 * @retval None
bogdanm 0:9b334a45a8ff 1328 */
bogdanm 0:9b334a45a8ff 1329 void HAL_RCC_NMI_IRQHandler(void)
bogdanm 0:9b334a45a8ff 1330 {
bogdanm 0:9b334a45a8ff 1331 /* Check RCC CSSF flag */
bogdanm 0:9b334a45a8ff 1332 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
bogdanm 0:9b334a45a8ff 1333 {
bogdanm 0:9b334a45a8ff 1334 /* RCC Clock Security System interrupt user callback */
bogdanm 0:9b334a45a8ff 1335 HAL_RCC_CSSCallback();
bogdanm 0:9b334a45a8ff 1336
bogdanm 0:9b334a45a8ff 1337 /* Clear RCC CSS pending bit */
bogdanm 0:9b334a45a8ff 1338 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
bogdanm 0:9b334a45a8ff 1339 }
bogdanm 0:9b334a45a8ff 1340 }
bogdanm 0:9b334a45a8ff 1341
bogdanm 0:9b334a45a8ff 1342 /**
bogdanm 0:9b334a45a8ff 1343 * @brief RCC Clock Security System interrupt callback
bogdanm 0:9b334a45a8ff 1344 * @retval none
bogdanm 0:9b334a45a8ff 1345 */
bogdanm 0:9b334a45a8ff 1346 __weak void HAL_RCC_CSSCallback(void)
bogdanm 0:9b334a45a8ff 1347 {
bogdanm 0:9b334a45a8ff 1348 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1349 the HAL_RCC_CSSCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1350 */
bogdanm 0:9b334a45a8ff 1351 }
bogdanm 0:9b334a45a8ff 1352
bogdanm 0:9b334a45a8ff 1353 /**
bogdanm 0:9b334a45a8ff 1354 * @}
bogdanm 0:9b334a45a8ff 1355 */
bogdanm 0:9b334a45a8ff 1356
bogdanm 0:9b334a45a8ff 1357 /**
bogdanm 0:9b334a45a8ff 1358 * @}
bogdanm 0:9b334a45a8ff 1359 */
bogdanm 0:9b334a45a8ff 1360
bogdanm 0:9b334a45a8ff 1361 #endif /* HAL_RCC_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1362 /**
bogdanm 0:9b334a45a8ff 1363 * @}
bogdanm 0:9b334a45a8ff 1364 */
bogdanm 0:9b334a45a8ff 1365
bogdanm 0:9b334a45a8ff 1366 /**
bogdanm 0:9b334a45a8ff 1367 * @}
bogdanm 0:9b334a45a8ff 1368 */
bogdanm 0:9b334a45a8ff 1369
bogdanm 0:9b334a45a8ff 1370 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/