en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f0xx_hal_i2s.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.3.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief I2S HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + IO operation functions
bogdanm 0:9b334a45a8ff 12 * + Peripheral State and Errors functions
bogdanm 0:9b334a45a8ff 13 @verbatim
bogdanm 0:9b334a45a8ff 14 ===============================================================================
bogdanm 0:9b334a45a8ff 15 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 16 ===============================================================================
bogdanm 0:9b334a45a8ff 17 [..]
bogdanm 0:9b334a45a8ff 18 The I2S HAL driver can be used as follow:
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 (#) Declare a I2S_HandleTypeDef handle structure.
bogdanm 0:9b334a45a8ff 21 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
bogdanm 0:9b334a45a8ff 22 (##) Enable the SPIx interface clock.
bogdanm 0:9b334a45a8ff 23 (##) I2S pins configuration:
bogdanm 0:9b334a45a8ff 24 (+++) Enable the clock for the I2S GPIOs.
bogdanm 0:9b334a45a8ff 25 (+++) Configure these I2S pins as alternate function pull-up.
bogdanm 0:9b334a45a8ff 26 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
bogdanm 0:9b334a45a8ff 27 and HAL_I2S_Receive_IT() APIs).
bogdanm 0:9b334a45a8ff 28 (+++) Configure the I2Sx interrupt priority.
bogdanm 0:9b334a45a8ff 29 (+++) Enable the NVIC I2S IRQ handle.
bogdanm 0:9b334a45a8ff 30 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
bogdanm 0:9b334a45a8ff 31 and HAL_I2S_Receive_DMA() APIs:
bogdanm 0:9b334a45a8ff 32 (+++) Declare a DMA handle structure for the Tx/Rx Channel.
bogdanm 0:9b334a45a8ff 33 (+++) Enable the DMAx interface clock.
bogdanm 0:9b334a45a8ff 34 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
bogdanm 0:9b334a45a8ff 35 (+++) Configure the DMA Tx/Rx Channel.
bogdanm 0:9b334a45a8ff 36 (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
bogdanm 0:9b334a45a8ff 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
bogdanm 0:9b334a45a8ff 38 DMA Tx/Rx Channel.
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
bogdanm 0:9b334a45a8ff 41 using HAL_I2S_Init() function.
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 -@- The specific I2S interrupts (Transmission complete interrupt,
bogdanm 0:9b334a45a8ff 44 RXNE interrupt and Error Interrupts) will be managed using the macros
bogdanm 0:9b334a45a8ff 45 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
bogdanm 0:9b334a45a8ff 46 -@- Make sure that either:
bogdanm 0:9b334a45a8ff 47 (+@) External clock source is configured after setting correctly
bogdanm 0:9b334a45a8ff 48 the define constant EXTERNAL_CLOCK_VALUE in the stm32f0xx_hal_conf.h file.
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 (#) Three mode of operations are available within this driver :
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 *** Polling mode IO operation ***
bogdanm 0:9b334a45a8ff 53 =================================
bogdanm 0:9b334a45a8ff 54 [..]
bogdanm 0:9b334a45a8ff 55 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
bogdanm 0:9b334a45a8ff 56 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 *** Interrupt mode IO operation ***
bogdanm 0:9b334a45a8ff 59 ===================================
bogdanm 0:9b334a45a8ff 60 [..]
bogdanm 0:9b334a45a8ff 61 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
bogdanm 0:9b334a45a8ff 62 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 63 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm 0:9b334a45a8ff 64 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 65 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm 0:9b334a45a8ff 66 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
bogdanm 0:9b334a45a8ff 67 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 68 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm 0:9b334a45a8ff 69 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 70 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm 0:9b334a45a8ff 71 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm 0:9b334a45a8ff 72 add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 *** DMA mode IO operation ***
bogdanm 0:9b334a45a8ff 75 ==============================
bogdanm 0:9b334a45a8ff 76 [..]
bogdanm 0:9b334a45a8ff 77 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
bogdanm 0:9b334a45a8ff 78 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 79 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm 0:9b334a45a8ff 80 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 81 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm 0:9b334a45a8ff 82 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
bogdanm 0:9b334a45a8ff 83 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 84 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm 0:9b334a45a8ff 85 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 86 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm 0:9b334a45a8ff 87 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm 0:9b334a45a8ff 88 add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm 0:9b334a45a8ff 89 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
bogdanm 0:9b334a45a8ff 90 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
bogdanm 0:9b334a45a8ff 91 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 *** I2S HAL driver macros list ***
bogdanm 0:9b334a45a8ff 94 =============================================
bogdanm 0:9b334a45a8ff 95 [..]
bogdanm 0:9b334a45a8ff 96 Below the list of most used macros in I2S HAL driver.
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
bogdanm 0:9b334a45a8ff 99 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
bogdanm 0:9b334a45a8ff 100 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
bogdanm 0:9b334a45a8ff 101 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
bogdanm 0:9b334a45a8ff 102 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 [..]
bogdanm 0:9b334a45a8ff 105 (@) You can refer to the I2S HAL driver header file for more useful macros
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 @endverbatim
bogdanm 0:9b334a45a8ff 108 ******************************************************************************
bogdanm 0:9b334a45a8ff 109 * @attention
bogdanm 0:9b334a45a8ff 110 *
bogdanm 0:9b334a45a8ff 111 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 112 *
bogdanm 0:9b334a45a8ff 113 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 114 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 115 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 116 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 117 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 118 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 119 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 120 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 121 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 122 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 123 *
bogdanm 0:9b334a45a8ff 124 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 125 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 126 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 127 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 128 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 129 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 130 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 131 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 132 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 133 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 134 *
bogdanm 0:9b334a45a8ff 135 ******************************************************************************
bogdanm 0:9b334a45a8ff 136 */
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 139 #include "stm32f0xx_hal.h"
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 #ifdef HAL_I2S_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 #if defined(STM32F031x6) || defined(STM32F038xx) || \
bogdanm 0:9b334a45a8ff 144 defined(STM32F051x8) || defined(STM32F058xx) || \
bogdanm 0:9b334a45a8ff 145 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
bogdanm 0:9b334a45a8ff 146 defined(STM32F042x6) || defined(STM32F048xx) || \
bogdanm 0:9b334a45a8ff 147 defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 0:9b334a45a8ff 150 * @{
bogdanm 0:9b334a45a8ff 151 */
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 /** @defgroup I2S I2S
bogdanm 0:9b334a45a8ff 154 * @brief I2S HAL module driver
bogdanm 0:9b334a45a8ff 155 * @{
bogdanm 0:9b334a45a8ff 156 */
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 159 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 160 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 161 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 162 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 163 /** @defgroup I2S_Private_Functions I2S Private Functions
bogdanm 0:9b334a45a8ff 164 * @{
bogdanm 0:9b334a45a8ff 165 */
bogdanm 0:9b334a45a8ff 166 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 167 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 168 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 169 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 170 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 171 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
bogdanm 0:9b334a45a8ff 172 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
bogdanm 0:9b334a45a8ff 173 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 174 /**
bogdanm 0:9b334a45a8ff 175 * @}
bogdanm 0:9b334a45a8ff 176 */
bogdanm 0:9b334a45a8ff 177
bogdanm 0:9b334a45a8ff 178 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /** @defgroup I2S_Exported_Functions I2S Exported Functions
bogdanm 0:9b334a45a8ff 181 * @{
bogdanm 0:9b334a45a8ff 182 */
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 185 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 186 *
bogdanm 0:9b334a45a8ff 187 @verbatim
bogdanm 0:9b334a45a8ff 188 ===============================================================================
bogdanm 0:9b334a45a8ff 189 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 190 ===============================================================================
bogdanm 0:9b334a45a8ff 191 [..] This subsection provides a set of functions allowing to initialize and
bogdanm 0:9b334a45a8ff 192 de-initialiaze the I2Sx peripheral in simplex mode:
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 (+) User must Implement HAL_I2S_MspInit() function in which he configures
bogdanm 0:9b334a45a8ff 195 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 (+) Call the function HAL_I2S_Init() to configure the selected device with
bogdanm 0:9b334a45a8ff 198 the selected configuration:
bogdanm 0:9b334a45a8ff 199 (++) Mode
bogdanm 0:9b334a45a8ff 200 (++) Standard
bogdanm 0:9b334a45a8ff 201 (++) Data Format
bogdanm 0:9b334a45a8ff 202 (++) MCLK Output
bogdanm 0:9b334a45a8ff 203 (++) Audio frequency
bogdanm 0:9b334a45a8ff 204 (++) Polarity
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
bogdanm 0:9b334a45a8ff 207 of the selected I2Sx periperal.
bogdanm 0:9b334a45a8ff 208 @endverbatim
bogdanm 0:9b334a45a8ff 209 * @{
bogdanm 0:9b334a45a8ff 210 */
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 /**
bogdanm 0:9b334a45a8ff 213 * @brief Initializes the I2S according to the specified parameters
bogdanm 0:9b334a45a8ff 214 * in the I2S_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 215 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 216 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 217 * @retval HAL status
bogdanm 0:9b334a45a8ff 218 */
bogdanm 0:9b334a45a8ff 219 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 220 {
bogdanm 0:9b334a45a8ff 221 uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
bogdanm 0:9b334a45a8ff 222 uint32_t tmp = 0, i2sclk = 0;
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 /* Check the I2S handle allocation */
bogdanm 0:9b334a45a8ff 225 if(hi2s == NULL)
bogdanm 0:9b334a45a8ff 226 {
bogdanm 0:9b334a45a8ff 227 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 228 }
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /* Check the I2S parameters */
bogdanm 0:9b334a45a8ff 231 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
bogdanm 0:9b334a45a8ff 232 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
bogdanm 0:9b334a45a8ff 233 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
bogdanm 0:9b334a45a8ff 234 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
bogdanm 0:9b334a45a8ff 235 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
bogdanm 0:9b334a45a8ff 236 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
bogdanm 0:9b334a45a8ff 237 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 if(hi2s->State == HAL_I2S_STATE_RESET)
bogdanm 0:9b334a45a8ff 240 {
bogdanm 0:9b334a45a8ff 241 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 242 hi2s->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
bogdanm 0:9b334a45a8ff 245 HAL_I2S_MspInit(hi2s);
bogdanm 0:9b334a45a8ff 246 }
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 hi2s->State = HAL_I2S_STATE_BUSY;
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
bogdanm 0:9b334a45a8ff 251 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
bogdanm 0:9b334a45a8ff 252 hi2s->Instance->I2SCFGR &= (uint16_t)(~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
bogdanm 0:9b334a45a8ff 253 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
bogdanm 0:9b334a45a8ff 254 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
bogdanm 0:9b334a45a8ff 255 hi2s->Instance->I2SPR = 0x0002;
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /* Get the I2SCFGR register value */
bogdanm 0:9b334a45a8ff 258 tmpreg = hi2s->Instance->I2SCFGR;
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
bogdanm 0:9b334a45a8ff 261 if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
bogdanm 0:9b334a45a8ff 262 {
bogdanm 0:9b334a45a8ff 263 i2sodd = (uint16_t)0;
bogdanm 0:9b334a45a8ff 264 i2sdiv = (uint16_t)2;
bogdanm 0:9b334a45a8ff 265 }
bogdanm 0:9b334a45a8ff 266 /* If the requested audio frequency is not the default, compute the prescaler */
bogdanm 0:9b334a45a8ff 267 else
bogdanm 0:9b334a45a8ff 268 {
bogdanm 0:9b334a45a8ff 269 /* Check the frame length (For the Prescaler computing) *******************/
bogdanm 0:9b334a45a8ff 270 if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
bogdanm 0:9b334a45a8ff 271 {
bogdanm 0:9b334a45a8ff 272 /* Packet length is 16 bits */
bogdanm 0:9b334a45a8ff 273 packetlength = 1;
bogdanm 0:9b334a45a8ff 274 }
bogdanm 0:9b334a45a8ff 275 else
bogdanm 0:9b334a45a8ff 276 {
bogdanm 0:9b334a45a8ff 277 /* Packet length is 32 bits */
bogdanm 0:9b334a45a8ff 278 packetlength = 2;
bogdanm 0:9b334a45a8ff 279 }
bogdanm 0:9b334a45a8ff 280
bogdanm 0:9b334a45a8ff 281 /* Get I2S source Clock frequency ****************************************/
bogdanm 0:9b334a45a8ff 282 i2sclk = HAL_RCC_GetSysClockFreq();
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /* Compute the Real divider depending on the MCLK output state, with a floating point */
bogdanm 0:9b334a45a8ff 285 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
bogdanm 0:9b334a45a8ff 286 {
bogdanm 0:9b334a45a8ff 287 /* MCLK output is enabled */
bogdanm 0:9b334a45a8ff 288 tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
bogdanm 0:9b334a45a8ff 289 }
bogdanm 0:9b334a45a8ff 290 else
bogdanm 0:9b334a45a8ff 291 {
bogdanm 0:9b334a45a8ff 292 /* MCLK output is disabled */
bogdanm 0:9b334a45a8ff 293 tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
bogdanm 0:9b334a45a8ff 294 }
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 /* Remove the flatting point */
bogdanm 0:9b334a45a8ff 297 tmp = tmp / 10;
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 /* Check the parity of the divider */
bogdanm 0:9b334a45a8ff 300 i2sodd = (uint32_t)(tmp & (uint32_t)1);
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 /* Compute the i2sdiv prescaler */
bogdanm 0:9b334a45a8ff 303 i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
bogdanm 0:9b334a45a8ff 306 i2sodd = (uint32_t) (i2sodd << 8);
bogdanm 0:9b334a45a8ff 307 }
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /* Test if the divider is 1 or 0 or greater than 0xFF */
bogdanm 0:9b334a45a8ff 310 if((i2sdiv < 2) || (i2sdiv > 0xFF))
bogdanm 0:9b334a45a8ff 311 {
bogdanm 0:9b334a45a8ff 312 /* Set the default values */
bogdanm 0:9b334a45a8ff 313 i2sdiv = 2;
bogdanm 0:9b334a45a8ff 314 i2sodd = 0;
bogdanm 0:9b334a45a8ff 315 }
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 /* Write to SPIx I2SPR register the computed value */
bogdanm 0:9b334a45a8ff 318 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 /* Configure the I2S with the I2S_InitStruct values */
bogdanm 0:9b334a45a8ff 321 tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 /* Write to SPIx I2SCFGR */
bogdanm 0:9b334a45a8ff 324 hi2s->Instance->I2SCFGR = tmpreg;
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 327 hi2s->State= HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 return HAL_OK;
bogdanm 0:9b334a45a8ff 330 }
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /**
bogdanm 0:9b334a45a8ff 333 * @brief DeInitializes the I2S peripheral
bogdanm 0:9b334a45a8ff 334 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 335 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 336 * @retval HAL status
bogdanm 0:9b334a45a8ff 337 */
bogdanm 0:9b334a45a8ff 338 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 339 {
bogdanm 0:9b334a45a8ff 340 /* Check the I2S handle allocation */
bogdanm 0:9b334a45a8ff 341 if(hi2s == NULL)
bogdanm 0:9b334a45a8ff 342 {
bogdanm 0:9b334a45a8ff 343 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 344 }
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 /* Check the parameters */
bogdanm 0:9b334a45a8ff 347 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 hi2s->State = HAL_I2S_STATE_BUSY;
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 /* Disable the I2S Peripheral Clock */
bogdanm 0:9b334a45a8ff 352 __HAL_I2S_DISABLE(hi2s);
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm 0:9b334a45a8ff 355 HAL_I2S_MspDeInit(hi2s);
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 358 hi2s->State = HAL_I2S_STATE_RESET;
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360 /* Release Lock */
bogdanm 0:9b334a45a8ff 361 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 return HAL_OK;
bogdanm 0:9b334a45a8ff 364 }
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 /**
bogdanm 0:9b334a45a8ff 367 * @brief I2S MSP Init
bogdanm 0:9b334a45a8ff 368 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 369 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 370 * @retval None
bogdanm 0:9b334a45a8ff 371 */
bogdanm 0:9b334a45a8ff 372 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 373 {
bogdanm 0:9b334a45a8ff 374 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 375 the HAL_I2S_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 376 */
bogdanm 0:9b334a45a8ff 377 }
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 /**
bogdanm 0:9b334a45a8ff 380 * @brief I2S MSP DeInit
bogdanm 0:9b334a45a8ff 381 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 382 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 383 * @retval None
bogdanm 0:9b334a45a8ff 384 */
bogdanm 0:9b334a45a8ff 385 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 386 {
bogdanm 0:9b334a45a8ff 387 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 388 the HAL_I2S_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 389 */
bogdanm 0:9b334a45a8ff 390 }
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 /**
bogdanm 0:9b334a45a8ff 393 * @}
bogdanm 0:9b334a45a8ff 394 */
bogdanm 0:9b334a45a8ff 395
bogdanm 0:9b334a45a8ff 396 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
bogdanm 0:9b334a45a8ff 397 * @brief Data transfers functions
bogdanm 0:9b334a45a8ff 398 *
bogdanm 0:9b334a45a8ff 399 @verbatim
bogdanm 0:9b334a45a8ff 400 ===============================================================================
bogdanm 0:9b334a45a8ff 401 ##### IO operation functions #####
bogdanm 0:9b334a45a8ff 402 ===============================================================================
bogdanm 0:9b334a45a8ff 403 [..]
bogdanm 0:9b334a45a8ff 404 This subsection provides a set of functions allowing to manage the I2S data
bogdanm 0:9b334a45a8ff 405 transfers.
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 (#) There are two modes of transfer:
bogdanm 0:9b334a45a8ff 408 (++) Blocking mode : The communication is performed in the polling mode.
bogdanm 0:9b334a45a8ff 409 The status of all data processing is returned by the same function
bogdanm 0:9b334a45a8ff 410 after finishing transfer.
bogdanm 0:9b334a45a8ff 411 (++) No-Blocking mode : The communication is performed using Interrupts
bogdanm 0:9b334a45a8ff 412 or DMA. These functions return the status of the transfer startup.
bogdanm 0:9b334a45a8ff 413 The end of the data processing will be indicated through the
bogdanm 0:9b334a45a8ff 414 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
bogdanm 0:9b334a45a8ff 415 using DMA mode.
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 (#) Blocking mode functions are :
bogdanm 0:9b334a45a8ff 418 (++) HAL_I2S_Transmit()
bogdanm 0:9b334a45a8ff 419 (++) HAL_I2S_Receive()
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 (#) No-Blocking mode functions with Interrupt are :
bogdanm 0:9b334a45a8ff 422 (++) HAL_I2S_Transmit_IT()
bogdanm 0:9b334a45a8ff 423 (++) HAL_I2S_Receive_IT()
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 (#) No-Blocking mode functions with DMA are :
bogdanm 0:9b334a45a8ff 426 (++) HAL_I2S_Transmit_DMA()
bogdanm 0:9b334a45a8ff 427 (++) HAL_I2S_Receive_DMA()
bogdanm 0:9b334a45a8ff 428
bogdanm 0:9b334a45a8ff 429 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
bogdanm 0:9b334a45a8ff 430 (++) HAL_I2S_TxCpltCallback()
bogdanm 0:9b334a45a8ff 431 (++) HAL_I2S_RxCpltCallback()
bogdanm 0:9b334a45a8ff 432 (++) HAL_I2S_ErrorCallback()
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 @endverbatim
bogdanm 0:9b334a45a8ff 435 * @{
bogdanm 0:9b334a45a8ff 436 */
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 /**
bogdanm 0:9b334a45a8ff 439 * @brief Transmit an amount of data in blocking mode
bogdanm 0:9b334a45a8ff 440 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 441 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 442 * @param pData: a 16-bit pointer to data buffer.
bogdanm 0:9b334a45a8ff 443 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 444 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 445 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 446 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 447 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 448 * @param Timeout: Timeout duration
bogdanm 0:9b334a45a8ff 449 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 450 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 451 * @retval HAL status
bogdanm 0:9b334a45a8ff 452 */
bogdanm 0:9b334a45a8ff 453 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 454 {
bogdanm 0:9b334a45a8ff 455 if((pData == NULL ) || (Size == 0))
bogdanm 0:9b334a45a8ff 456 {
bogdanm 0:9b334a45a8ff 457 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 458 }
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /* Process Locked */
bogdanm 0:9b334a45a8ff 461 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 464 {
bogdanm 0:9b334a45a8ff 465 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 466 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 467 {
bogdanm 0:9b334a45a8ff 468 hi2s->TxXferSize = (Size << 1);
bogdanm 0:9b334a45a8ff 469 hi2s->TxXferCount = (Size << 1);
bogdanm 0:9b334a45a8ff 470 }
bogdanm 0:9b334a45a8ff 471 else
bogdanm 0:9b334a45a8ff 472 {
bogdanm 0:9b334a45a8ff 473 hi2s->TxXferSize = Size;
bogdanm 0:9b334a45a8ff 474 hi2s->TxXferCount = Size;
bogdanm 0:9b334a45a8ff 475 }
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 /* Set state and reset error code */
bogdanm 0:9b334a45a8ff 478 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 479 hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm 0:9b334a45a8ff 480 hi2s->pTxBuffPtr = pData;
bogdanm 0:9b334a45a8ff 481
bogdanm 0:9b334a45a8ff 482 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 483 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 484 {
bogdanm 0:9b334a45a8ff 485 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 486 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 487 }
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 while(hi2s->TxXferCount > 0)
bogdanm 0:9b334a45a8ff 490 {
bogdanm 0:9b334a45a8ff 491 /* Wait until TXE flag is set */
bogdanm 0:9b334a45a8ff 492 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 493 {
bogdanm 0:9b334a45a8ff 494 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 495 }
bogdanm 0:9b334a45a8ff 496 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
bogdanm 0:9b334a45a8ff 497 hi2s->TxXferCount--;
bogdanm 0:9b334a45a8ff 498 }
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 /* Wait until TXE flag is set, to confirm the end of the transcation */
bogdanm 0:9b334a45a8ff 501 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 502 {
bogdanm 0:9b334a45a8ff 503 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 504 }
bogdanm 0:9b334a45a8ff 505 /* Wait until Busy flag is reset */
bogdanm 0:9b334a45a8ff 506 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 507 {
bogdanm 0:9b334a45a8ff 508 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 509 }
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 514 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 return HAL_OK;
bogdanm 0:9b334a45a8ff 517 }
bogdanm 0:9b334a45a8ff 518 else
bogdanm 0:9b334a45a8ff 519 {
bogdanm 0:9b334a45a8ff 520 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 521 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 522 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 523 }
bogdanm 0:9b334a45a8ff 524 }
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 /**
bogdanm 0:9b334a45a8ff 527 * @brief Receive an amount of data in blocking mode
bogdanm 0:9b334a45a8ff 528 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 529 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 530 * @param pData: a 16-bit pointer to data buffer.
bogdanm 0:9b334a45a8ff 531 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 532 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 533 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 534 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 535 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 536 * @param Timeout: Timeout duration
bogdanm 0:9b334a45a8ff 537 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 538 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 539 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
bogdanm 0:9b334a45a8ff 540 * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
bogdanm 0:9b334a45a8ff 541 * @retval HAL status
bogdanm 0:9b334a45a8ff 542 */
bogdanm 0:9b334a45a8ff 543 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 544 {
bogdanm 0:9b334a45a8ff 545 if((pData == NULL ) || (Size == 0))
bogdanm 0:9b334a45a8ff 546 {
bogdanm 0:9b334a45a8ff 547 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 548 }
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 /* Process Locked */
bogdanm 0:9b334a45a8ff 551 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 552
bogdanm 0:9b334a45a8ff 553 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 554 {
bogdanm 0:9b334a45a8ff 555 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 556 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 557 {
bogdanm 0:9b334a45a8ff 558 hi2s->RxXferSize = (Size << 1);
bogdanm 0:9b334a45a8ff 559 hi2s->RxXferCount = (Size << 1);
bogdanm 0:9b334a45a8ff 560 }
bogdanm 0:9b334a45a8ff 561 else
bogdanm 0:9b334a45a8ff 562 {
bogdanm 0:9b334a45a8ff 563 hi2s->RxXferSize = Size;
bogdanm 0:9b334a45a8ff 564 hi2s->RxXferCount = Size;
bogdanm 0:9b334a45a8ff 565 }
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 /* Set state and reset error code */
bogdanm 0:9b334a45a8ff 568 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 569 hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm 0:9b334a45a8ff 570 hi2s->pRxBuffPtr = pData;
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 573 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 574 {
bogdanm 0:9b334a45a8ff 575 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 576 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 577 }
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /* Receive data */
bogdanm 0:9b334a45a8ff 580 while(hi2s->RxXferCount > 0)
bogdanm 0:9b334a45a8ff 581 {
bogdanm 0:9b334a45a8ff 582 /* Wait until RXNE flag is set */
bogdanm 0:9b334a45a8ff 583 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 584 {
bogdanm 0:9b334a45a8ff 585 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 586 }
bogdanm 0:9b334a45a8ff 587
bogdanm 0:9b334a45a8ff 588 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
bogdanm 0:9b334a45a8ff 589 hi2s->RxXferCount--;
bogdanm 0:9b334a45a8ff 590 }
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 593
bogdanm 0:9b334a45a8ff 594 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 595 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 return HAL_OK;
bogdanm 0:9b334a45a8ff 598 }
bogdanm 0:9b334a45a8ff 599 else
bogdanm 0:9b334a45a8ff 600 {
bogdanm 0:9b334a45a8ff 601 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 602 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 603 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 604 }
bogdanm 0:9b334a45a8ff 605 }
bogdanm 0:9b334a45a8ff 606
bogdanm 0:9b334a45a8ff 607 /**
bogdanm 0:9b334a45a8ff 608 * @brief Transmit an amount of data in non-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 609 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 610 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 611 * @param pData: a 16-bit pointer to data buffer.
bogdanm 0:9b334a45a8ff 612 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 613 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 614 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 615 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 616 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 617 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 618 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 619 * @retval HAL status
bogdanm 0:9b334a45a8ff 620 */
bogdanm 0:9b334a45a8ff 621 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
bogdanm 0:9b334a45a8ff 622 {
bogdanm 0:9b334a45a8ff 623 if((pData == NULL) || (Size == 0))
bogdanm 0:9b334a45a8ff 624 {
bogdanm 0:9b334a45a8ff 625 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 626 }
bogdanm 0:9b334a45a8ff 627
bogdanm 0:9b334a45a8ff 628 /* Process Locked */
bogdanm 0:9b334a45a8ff 629 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 630
bogdanm 0:9b334a45a8ff 631 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 632 {
bogdanm 0:9b334a45a8ff 633 hi2s->pTxBuffPtr = pData;
bogdanm 0:9b334a45a8ff 634 hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm 0:9b334a45a8ff 635 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 638 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 639 {
bogdanm 0:9b334a45a8ff 640 hi2s->TxXferSize = (Size << 1);
bogdanm 0:9b334a45a8ff 641 hi2s->TxXferCount = (Size << 1);
bogdanm 0:9b334a45a8ff 642 }
bogdanm 0:9b334a45a8ff 643 else
bogdanm 0:9b334a45a8ff 644 {
bogdanm 0:9b334a45a8ff 645 hi2s->TxXferSize = Size;
bogdanm 0:9b334a45a8ff 646 hi2s->TxXferCount = Size;
bogdanm 0:9b334a45a8ff 647 }
bogdanm 0:9b334a45a8ff 648
bogdanm 0:9b334a45a8ff 649 /* Enable TXE and ERR interrupt */
bogdanm 0:9b334a45a8ff 650 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 651
bogdanm 0:9b334a45a8ff 652 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 653 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 654 {
bogdanm 0:9b334a45a8ff 655 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 656 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 657 }
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 660 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 661
bogdanm 0:9b334a45a8ff 662 return HAL_OK;
bogdanm 0:9b334a45a8ff 663 }
bogdanm 0:9b334a45a8ff 664 else
bogdanm 0:9b334a45a8ff 665 {
bogdanm 0:9b334a45a8ff 666 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 667 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 668 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 669 }
bogdanm 0:9b334a45a8ff 670 }
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 /**
bogdanm 0:9b334a45a8ff 673 * @brief Receive an amount of data in non-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 674 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 675 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 676 * @param pData: a 16-bit pointer to the Receive data buffer.
bogdanm 0:9b334a45a8ff 677 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 678 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 679 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 680 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 681 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 682 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 683 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 684 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
bogdanm 0:9b334a45a8ff 685 * between Master and Slave otherwise the I2S interrupt should be optimized.
bogdanm 0:9b334a45a8ff 686 * @retval HAL status
bogdanm 0:9b334a45a8ff 687 */
bogdanm 0:9b334a45a8ff 688 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
bogdanm 0:9b334a45a8ff 689 {
bogdanm 0:9b334a45a8ff 690 if((pData == NULL) || (Size == 0))
bogdanm 0:9b334a45a8ff 691 {
bogdanm 0:9b334a45a8ff 692 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 693 }
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 /* Process Locked */
bogdanm 0:9b334a45a8ff 696 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 697
bogdanm 0:9b334a45a8ff 698 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 699 {
bogdanm 0:9b334a45a8ff 700 hi2s->pRxBuffPtr = pData;
bogdanm 0:9b334a45a8ff 701 hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm 0:9b334a45a8ff 702 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 705 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 706 {
bogdanm 0:9b334a45a8ff 707 hi2s->RxXferSize = (Size << 1);
bogdanm 0:9b334a45a8ff 708 hi2s->RxXferCount = (Size << 1);
bogdanm 0:9b334a45a8ff 709 }
bogdanm 0:9b334a45a8ff 710 else
bogdanm 0:9b334a45a8ff 711 {
bogdanm 0:9b334a45a8ff 712 hi2s->RxXferSize = Size;
bogdanm 0:9b334a45a8ff 713 hi2s->RxXferCount = Size;
bogdanm 0:9b334a45a8ff 714 }
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 /* Enable TXE and ERR interrupt */
bogdanm 0:9b334a45a8ff 717 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 718
bogdanm 0:9b334a45a8ff 719 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 720 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 721 {
bogdanm 0:9b334a45a8ff 722 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 723 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 724 }
bogdanm 0:9b334a45a8ff 725
bogdanm 0:9b334a45a8ff 726 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 727 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 728
bogdanm 0:9b334a45a8ff 729 return HAL_OK;
bogdanm 0:9b334a45a8ff 730 }
bogdanm 0:9b334a45a8ff 731 else
bogdanm 0:9b334a45a8ff 732 {
bogdanm 0:9b334a45a8ff 733 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 734 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 735 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 736 }
bogdanm 0:9b334a45a8ff 737 }
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 /**
bogdanm 0:9b334a45a8ff 740 * @brief Transmit an amount of data in non-blocking mode with DMA
bogdanm 0:9b334a45a8ff 741 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 742 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 743 * @param pData: a 16-bit pointer to the Transmit data buffer.
bogdanm 0:9b334a45a8ff 744 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 745 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 746 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 747 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 748 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 749 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 750 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 751 * @retval HAL status
bogdanm 0:9b334a45a8ff 752 */
bogdanm 0:9b334a45a8ff 753 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
bogdanm 0:9b334a45a8ff 754 {
bogdanm 0:9b334a45a8ff 755 if((pData == NULL) || (Size == 0))
bogdanm 0:9b334a45a8ff 756 {
bogdanm 0:9b334a45a8ff 757 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 758 }
bogdanm 0:9b334a45a8ff 759
bogdanm 0:9b334a45a8ff 760 /* Process Locked */
bogdanm 0:9b334a45a8ff 761 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 762
bogdanm 0:9b334a45a8ff 763 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 764 {
bogdanm 0:9b334a45a8ff 765 hi2s->pTxBuffPtr = pData;
bogdanm 0:9b334a45a8ff 766 hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm 0:9b334a45a8ff 767 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 768
bogdanm 0:9b334a45a8ff 769 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 770 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 771 {
bogdanm 0:9b334a45a8ff 772 hi2s->TxXferSize = (Size << 1);
bogdanm 0:9b334a45a8ff 773 hi2s->TxXferCount = (Size << 1);
bogdanm 0:9b334a45a8ff 774 }
bogdanm 0:9b334a45a8ff 775 else
bogdanm 0:9b334a45a8ff 776 {
bogdanm 0:9b334a45a8ff 777 hi2s->TxXferSize = Size;
bogdanm 0:9b334a45a8ff 778 hi2s->TxXferCount = Size;
bogdanm 0:9b334a45a8ff 779 }
bogdanm 0:9b334a45a8ff 780
bogdanm 0:9b334a45a8ff 781 /* Set the I2S Tx DMA Half transfert complete callback */
bogdanm 0:9b334a45a8ff 782 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784 /* Set the I2S Tx DMA transfert complete callback */
bogdanm 0:9b334a45a8ff 785 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
bogdanm 0:9b334a45a8ff 786
bogdanm 0:9b334a45a8ff 787 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 788 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
bogdanm 0:9b334a45a8ff 789
bogdanm 0:9b334a45a8ff 790 /* Enable the Tx DMA Channel */
bogdanm 0:9b334a45a8ff 791 HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
bogdanm 0:9b334a45a8ff 792
bogdanm 0:9b334a45a8ff 793 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 794 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 795 {
bogdanm 0:9b334a45a8ff 796 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 797 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 798 }
bogdanm 0:9b334a45a8ff 799
bogdanm 0:9b334a45a8ff 800 /* Check if the I2S Tx request is already enabled */
bogdanm 0:9b334a45a8ff 801 if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
bogdanm 0:9b334a45a8ff 802 {
bogdanm 0:9b334a45a8ff 803 /* Enable Tx DMA Request */
bogdanm 0:9b334a45a8ff 804 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
bogdanm 0:9b334a45a8ff 805 }
bogdanm 0:9b334a45a8ff 806
bogdanm 0:9b334a45a8ff 807 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 808 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 809
bogdanm 0:9b334a45a8ff 810 return HAL_OK;
bogdanm 0:9b334a45a8ff 811 }
bogdanm 0:9b334a45a8ff 812 else
bogdanm 0:9b334a45a8ff 813 {
bogdanm 0:9b334a45a8ff 814 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 815 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 816 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 817 }
bogdanm 0:9b334a45a8ff 818 }
bogdanm 0:9b334a45a8ff 819
bogdanm 0:9b334a45a8ff 820 /**
bogdanm 0:9b334a45a8ff 821 * @brief Receive an amount of data in non-blocking mode with DMA
bogdanm 0:9b334a45a8ff 822 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 823 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 824 * @param pData: a 16-bit pointer to the Receive data buffer.
bogdanm 0:9b334a45a8ff 825 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 826 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 827 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 828 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 829 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 830 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 831 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 832 * @retval HAL status
bogdanm 0:9b334a45a8ff 833 */
bogdanm 0:9b334a45a8ff 834 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
bogdanm 0:9b334a45a8ff 835 {
bogdanm 0:9b334a45a8ff 836 if((pData == NULL) || (Size == 0))
bogdanm 0:9b334a45a8ff 837 {
bogdanm 0:9b334a45a8ff 838 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 839 }
bogdanm 0:9b334a45a8ff 840
bogdanm 0:9b334a45a8ff 841 /* Process Locked */
bogdanm 0:9b334a45a8ff 842 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 845 {
bogdanm 0:9b334a45a8ff 846 hi2s->pRxBuffPtr = pData;
bogdanm 0:9b334a45a8ff 847 hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm 0:9b334a45a8ff 848 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 849
bogdanm 0:9b334a45a8ff 850 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 851 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 852 {
bogdanm 0:9b334a45a8ff 853 hi2s->RxXferSize = (Size << 1);
bogdanm 0:9b334a45a8ff 854 hi2s->RxXferCount = (Size << 1);
bogdanm 0:9b334a45a8ff 855 }
bogdanm 0:9b334a45a8ff 856 else
bogdanm 0:9b334a45a8ff 857 {
bogdanm 0:9b334a45a8ff 858 hi2s->RxXferSize = Size;
bogdanm 0:9b334a45a8ff 859 hi2s->RxXferCount = Size;
bogdanm 0:9b334a45a8ff 860 }
bogdanm 0:9b334a45a8ff 861
bogdanm 0:9b334a45a8ff 862
bogdanm 0:9b334a45a8ff 863 /* Set the I2S Rx DMA Half transfert complete callback */
bogdanm 0:9b334a45a8ff 864 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
bogdanm 0:9b334a45a8ff 865
bogdanm 0:9b334a45a8ff 866 /* Set the I2S Rx DMA transfert complete callback */
bogdanm 0:9b334a45a8ff 867 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
bogdanm 0:9b334a45a8ff 868
bogdanm 0:9b334a45a8ff 869 /* Set the DMA error callback */
bogdanm 0:9b334a45a8ff 870 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
bogdanm 0:9b334a45a8ff 871
bogdanm 0:9b334a45a8ff 872 /* Check if Master Receiver mode is selected */
bogdanm 0:9b334a45a8ff 873 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm 0:9b334a45a8ff 874 {
bogdanm 0:9b334a45a8ff 875 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
bogdanm 0:9b334a45a8ff 876 access to the SPI_SR register. */
bogdanm 0:9b334a45a8ff 877 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm 0:9b334a45a8ff 878 }
bogdanm 0:9b334a45a8ff 879
bogdanm 0:9b334a45a8ff 880 /* Enable the Rx DMA Channel */
bogdanm 0:9b334a45a8ff 881 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
bogdanm 0:9b334a45a8ff 882
bogdanm 0:9b334a45a8ff 883 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 884 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 885 {
bogdanm 0:9b334a45a8ff 886 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 887 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 888 }
bogdanm 0:9b334a45a8ff 889
bogdanm 0:9b334a45a8ff 890 /* Check if the I2S Rx request is already enabled */
bogdanm 0:9b334a45a8ff 891 if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
bogdanm 0:9b334a45a8ff 892 {
bogdanm 0:9b334a45a8ff 893 /* Enable Rx DMA Request */
bogdanm 0:9b334a45a8ff 894 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
bogdanm 0:9b334a45a8ff 895 }
bogdanm 0:9b334a45a8ff 896
bogdanm 0:9b334a45a8ff 897 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 898 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 899
bogdanm 0:9b334a45a8ff 900 return HAL_OK;
bogdanm 0:9b334a45a8ff 901 }
bogdanm 0:9b334a45a8ff 902 else
bogdanm 0:9b334a45a8ff 903 {
bogdanm 0:9b334a45a8ff 904 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 905 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 906 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 907 }
bogdanm 0:9b334a45a8ff 908 }
bogdanm 0:9b334a45a8ff 909
bogdanm 0:9b334a45a8ff 910 /**
bogdanm 0:9b334a45a8ff 911 * @brief Pauses the audio stream playing from the Media.
bogdanm 0:9b334a45a8ff 912 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 913 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 914 * @retval HAL status
bogdanm 0:9b334a45a8ff 915 */
bogdanm 0:9b334a45a8ff 916 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 917 {
bogdanm 0:9b334a45a8ff 918 /* Process Locked */
bogdanm 0:9b334a45a8ff 919 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 920
bogdanm 0:9b334a45a8ff 921 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm 0:9b334a45a8ff 922 {
bogdanm 0:9b334a45a8ff 923 /* Disable the I2S DMA Tx request */
bogdanm 0:9b334a45a8ff 924 hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 925 }
bogdanm 0:9b334a45a8ff 926 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm 0:9b334a45a8ff 927 {
bogdanm 0:9b334a45a8ff 928 /* Disable the I2S DMA Rx request */
bogdanm 0:9b334a45a8ff 929 hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 930 }
bogdanm 0:9b334a45a8ff 931
bogdanm 0:9b334a45a8ff 932 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 933 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 934
bogdanm 0:9b334a45a8ff 935 return HAL_OK;
bogdanm 0:9b334a45a8ff 936 }
bogdanm 0:9b334a45a8ff 937
bogdanm 0:9b334a45a8ff 938 /**
bogdanm 0:9b334a45a8ff 939 * @brief Resumes the audio stream playing from the Media.
bogdanm 0:9b334a45a8ff 940 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 941 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 942 * @retval HAL status
bogdanm 0:9b334a45a8ff 943 */
bogdanm 0:9b334a45a8ff 944 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 945 {
bogdanm 0:9b334a45a8ff 946 /* Process Locked */
bogdanm 0:9b334a45a8ff 947 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 948
bogdanm 0:9b334a45a8ff 949 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm 0:9b334a45a8ff 950 {
bogdanm 0:9b334a45a8ff 951 /* Enable the I2S DMA Tx request */
bogdanm 0:9b334a45a8ff 952 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
bogdanm 0:9b334a45a8ff 953 }
bogdanm 0:9b334a45a8ff 954 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm 0:9b334a45a8ff 955 {
bogdanm 0:9b334a45a8ff 956 /* Enable the I2S DMA Rx request */
bogdanm 0:9b334a45a8ff 957 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
bogdanm 0:9b334a45a8ff 958 }
bogdanm 0:9b334a45a8ff 959
bogdanm 0:9b334a45a8ff 960 /* If the I2S peripheral is still not enabled, enable it */
bogdanm 0:9b334a45a8ff 961 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
bogdanm 0:9b334a45a8ff 962 {
bogdanm 0:9b334a45a8ff 963 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 964 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 965 }
bogdanm 0:9b334a45a8ff 966
bogdanm 0:9b334a45a8ff 967 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 968 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 969
bogdanm 0:9b334a45a8ff 970 return HAL_OK;
bogdanm 0:9b334a45a8ff 971 }
bogdanm 0:9b334a45a8ff 972
bogdanm 0:9b334a45a8ff 973 /**
bogdanm 0:9b334a45a8ff 974 * @brief Resumes the audio stream playing from the Media.
bogdanm 0:9b334a45a8ff 975 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 976 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 977 * @retval HAL status
bogdanm 0:9b334a45a8ff 978 */
bogdanm 0:9b334a45a8ff 979 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 980 {
bogdanm 0:9b334a45a8ff 981 /* Process Locked */
bogdanm 0:9b334a45a8ff 982 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 983
bogdanm 0:9b334a45a8ff 984 /* Disable the I2S Tx/Rx DMA requests */
bogdanm 0:9b334a45a8ff 985 hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 986 hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 987
bogdanm 0:9b334a45a8ff 988 /* Abort the I2S DMA tx channel */
bogdanm 0:9b334a45a8ff 989 if(hi2s->hdmatx != NULL)
bogdanm 0:9b334a45a8ff 990 {
bogdanm 0:9b334a45a8ff 991 /* Disable the I2S DMA channel */
bogdanm 0:9b334a45a8ff 992 __HAL_DMA_DISABLE(hi2s->hdmatx);
bogdanm 0:9b334a45a8ff 993 HAL_DMA_Abort(hi2s->hdmatx);
bogdanm 0:9b334a45a8ff 994 }
bogdanm 0:9b334a45a8ff 995 /* Abort the I2S DMA rx channel */
bogdanm 0:9b334a45a8ff 996 if(hi2s->hdmarx != NULL)
bogdanm 0:9b334a45a8ff 997 {
bogdanm 0:9b334a45a8ff 998 /* Disable the I2S DMA channel */
bogdanm 0:9b334a45a8ff 999 __HAL_DMA_DISABLE(hi2s->hdmarx);
bogdanm 0:9b334a45a8ff 1000 HAL_DMA_Abort(hi2s->hdmarx);
bogdanm 0:9b334a45a8ff 1001 }
bogdanm 0:9b334a45a8ff 1002
bogdanm 0:9b334a45a8ff 1003 /* Disable I2S peripheral */
bogdanm 0:9b334a45a8ff 1004 __HAL_I2S_DISABLE(hi2s);
bogdanm 0:9b334a45a8ff 1005
bogdanm 0:9b334a45a8ff 1006 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1007
bogdanm 0:9b334a45a8ff 1008 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1009 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 1010
bogdanm 0:9b334a45a8ff 1011 return HAL_OK;
bogdanm 0:9b334a45a8ff 1012 }
bogdanm 0:9b334a45a8ff 1013
bogdanm 0:9b334a45a8ff 1014 /**
bogdanm 0:9b334a45a8ff 1015 * @brief This function handles I2S interrupt request.
bogdanm 0:9b334a45a8ff 1016 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1017 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1018 * @retval None
bogdanm 0:9b334a45a8ff 1019 */
bogdanm 0:9b334a45a8ff 1020 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1021 {
bogdanm 0:9b334a45a8ff 1022 uint32_t i2ssr = hi2s->Instance->SR;
bogdanm 0:9b334a45a8ff 1023
bogdanm 0:9b334a45a8ff 1024 /* I2S in mode Receiver ------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1025 if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
bogdanm 0:9b334a45a8ff 1026 ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
bogdanm 0:9b334a45a8ff 1027 {
bogdanm 0:9b334a45a8ff 1028 I2S_Receive_IT(hi2s);
bogdanm 0:9b334a45a8ff 1029 return;
bogdanm 0:9b334a45a8ff 1030 }
bogdanm 0:9b334a45a8ff 1031
bogdanm 0:9b334a45a8ff 1032 /* I2S in mode Tramitter -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1033 if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
bogdanm 0:9b334a45a8ff 1034 {
bogdanm 0:9b334a45a8ff 1035 I2S_Transmit_IT(hi2s);
bogdanm 0:9b334a45a8ff 1036 return;
bogdanm 0:9b334a45a8ff 1037 }
bogdanm 0:9b334a45a8ff 1038
bogdanm 0:9b334a45a8ff 1039 /* I2S Overrun error interrupt occured ---------------------------------*/
bogdanm 0:9b334a45a8ff 1040 if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
bogdanm 0:9b334a45a8ff 1041 {
bogdanm 0:9b334a45a8ff 1042 /* Disable RXNE and ERR interrupt */
bogdanm 0:9b334a45a8ff 1043 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 1044
bogdanm 0:9b334a45a8ff 1045 /* Set the I2S State ready */
bogdanm 0:9b334a45a8ff 1046 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1047
bogdanm 0:9b334a45a8ff 1048 /* Set the error code and execute error callback*/
bogdanm 0:9b334a45a8ff 1049 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
bogdanm 0:9b334a45a8ff 1050 HAL_I2S_ErrorCallback(hi2s);
bogdanm 0:9b334a45a8ff 1051 }
bogdanm 0:9b334a45a8ff 1052
bogdanm 0:9b334a45a8ff 1053 /* I2S Underrun error interrupt occured --------------------------------*/
bogdanm 0:9b334a45a8ff 1054 if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
bogdanm 0:9b334a45a8ff 1055 {
bogdanm 0:9b334a45a8ff 1056 /* Disable TXE and ERR interrupt */
bogdanm 0:9b334a45a8ff 1057 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 1058
bogdanm 0:9b334a45a8ff 1059 /* Set the I2S State ready */
bogdanm 0:9b334a45a8ff 1060 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1061
bogdanm 0:9b334a45a8ff 1062 /* Set the error code and execute error callback*/
bogdanm 0:9b334a45a8ff 1063 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
bogdanm 0:9b334a45a8ff 1064 HAL_I2S_ErrorCallback(hi2s);
bogdanm 0:9b334a45a8ff 1065 }
bogdanm 0:9b334a45a8ff 1066 }
bogdanm 0:9b334a45a8ff 1067
bogdanm 0:9b334a45a8ff 1068 /**
bogdanm 0:9b334a45a8ff 1069 * @brief Tx Transfer Half completed callbacks
bogdanm 0:9b334a45a8ff 1070 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1071 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1072 * @retval None
bogdanm 0:9b334a45a8ff 1073 */
bogdanm 0:9b334a45a8ff 1074 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1075 {
bogdanm 0:9b334a45a8ff 1076 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1077 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1078 */
bogdanm 0:9b334a45a8ff 1079 }
bogdanm 0:9b334a45a8ff 1080
bogdanm 0:9b334a45a8ff 1081 /**
bogdanm 0:9b334a45a8ff 1082 * @brief Tx Transfer completed callbacks
bogdanm 0:9b334a45a8ff 1083 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1084 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1085 * @retval None
bogdanm 0:9b334a45a8ff 1086 */
bogdanm 0:9b334a45a8ff 1087 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1088 {
bogdanm 0:9b334a45a8ff 1089 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1090 the HAL_I2S_TxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1091 */
bogdanm 0:9b334a45a8ff 1092 }
bogdanm 0:9b334a45a8ff 1093
bogdanm 0:9b334a45a8ff 1094 /**
bogdanm 0:9b334a45a8ff 1095 * @brief Rx Transfer half completed callbacks
bogdanm 0:9b334a45a8ff 1096 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1097 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1098 * @retval None
bogdanm 0:9b334a45a8ff 1099 */
bogdanm 0:9b334a45a8ff 1100 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1101 {
bogdanm 0:9b334a45a8ff 1102 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1103 the HAL_I2S_RxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1104 */
bogdanm 0:9b334a45a8ff 1105 }
bogdanm 0:9b334a45a8ff 1106
bogdanm 0:9b334a45a8ff 1107 /**
bogdanm 0:9b334a45a8ff 1108 * @brief Rx Transfer completed callbacks
bogdanm 0:9b334a45a8ff 1109 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1110 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1111 * @retval None
bogdanm 0:9b334a45a8ff 1112 */
bogdanm 0:9b334a45a8ff 1113 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1114 {
bogdanm 0:9b334a45a8ff 1115 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1116 the HAL_I2S_RxCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1117 */
bogdanm 0:9b334a45a8ff 1118 }
bogdanm 0:9b334a45a8ff 1119
bogdanm 0:9b334a45a8ff 1120 /**
bogdanm 0:9b334a45a8ff 1121 * @brief I2S error callbacks
bogdanm 0:9b334a45a8ff 1122 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1123 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1124 * @retval None
bogdanm 0:9b334a45a8ff 1125 */
bogdanm 0:9b334a45a8ff 1126 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1127 {
bogdanm 0:9b334a45a8ff 1128 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1129 the HAL_I2S_ErrorCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1130 */
bogdanm 0:9b334a45a8ff 1131 }
bogdanm 0:9b334a45a8ff 1132
bogdanm 0:9b334a45a8ff 1133 /**
bogdanm 0:9b334a45a8ff 1134 * @}
bogdanm 0:9b334a45a8ff 1135 */
bogdanm 0:9b334a45a8ff 1136
bogdanm 0:9b334a45a8ff 1137 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm 0:9b334a45a8ff 1138 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 1139 *
bogdanm 0:9b334a45a8ff 1140 @verbatim
bogdanm 0:9b334a45a8ff 1141 ===============================================================================
bogdanm 0:9b334a45a8ff 1142 ##### Peripheral State and Errors functions #####
bogdanm 0:9b334a45a8ff 1143 ===============================================================================
bogdanm 0:9b334a45a8ff 1144 [..]
bogdanm 0:9b334a45a8ff 1145 This subsection permits to get in run-time the status of the peripheral
bogdanm 0:9b334a45a8ff 1146 and the data flow.
bogdanm 0:9b334a45a8ff 1147
bogdanm 0:9b334a45a8ff 1148 @endverbatim
bogdanm 0:9b334a45a8ff 1149 * @{
bogdanm 0:9b334a45a8ff 1150 */
bogdanm 0:9b334a45a8ff 1151
bogdanm 0:9b334a45a8ff 1152 /**
bogdanm 0:9b334a45a8ff 1153 * @brief Return the I2S state
bogdanm 0:9b334a45a8ff 1154 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1155 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1156 * @retval HAL state
bogdanm 0:9b334a45a8ff 1157 */
bogdanm 0:9b334a45a8ff 1158 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1159 {
bogdanm 0:9b334a45a8ff 1160 return hi2s->State;
bogdanm 0:9b334a45a8ff 1161 }
bogdanm 0:9b334a45a8ff 1162
bogdanm 0:9b334a45a8ff 1163 /**
bogdanm 0:9b334a45a8ff 1164 * @brief Return the I2S error code
bogdanm 0:9b334a45a8ff 1165 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1166 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1167 * @retval I2S Error Code
bogdanm 0:9b334a45a8ff 1168 */
bogdanm 0:9b334a45a8ff 1169 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1170 {
bogdanm 0:9b334a45a8ff 1171 return hi2s->ErrorCode;
bogdanm 0:9b334a45a8ff 1172 }
bogdanm 0:9b334a45a8ff 1173 /**
bogdanm 0:9b334a45a8ff 1174 * @}
bogdanm 0:9b334a45a8ff 1175 */
bogdanm 0:9b334a45a8ff 1176
bogdanm 0:9b334a45a8ff 1177 /**
bogdanm 0:9b334a45a8ff 1178 * @}
bogdanm 0:9b334a45a8ff 1179 */
bogdanm 0:9b334a45a8ff 1180
bogdanm 0:9b334a45a8ff 1181 /** @addtogroup I2S_Private_Functions I2S Private Functions
bogdanm 0:9b334a45a8ff 1182 * @{
bogdanm 0:9b334a45a8ff 1183 */
bogdanm 0:9b334a45a8ff 1184 /**
bogdanm 0:9b334a45a8ff 1185 * @brief DMA I2S transmit process complete callback
bogdanm 0:9b334a45a8ff 1186 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1187 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 1188 * @retval None
bogdanm 0:9b334a45a8ff 1189 */
bogdanm 0:9b334a45a8ff 1190 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 1191 {
bogdanm 0:9b334a45a8ff 1192 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
bogdanm 0:9b334a45a8ff 1193
bogdanm 0:9b334a45a8ff 1194 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 1195 {
bogdanm 0:9b334a45a8ff 1196 /* Disable Tx DMA Request */
bogdanm 0:9b334a45a8ff 1197 hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 1198
bogdanm 0:9b334a45a8ff 1199 hi2s->TxXferCount = 0;
bogdanm 0:9b334a45a8ff 1200 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1201 }
bogdanm 0:9b334a45a8ff 1202 HAL_I2S_TxCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1203 }
bogdanm 0:9b334a45a8ff 1204
bogdanm 0:9b334a45a8ff 1205 /**
bogdanm 0:9b334a45a8ff 1206 * @brief DMA I2S transmit process half complete callback
bogdanm 0:9b334a45a8ff 1207 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1208 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 1209 * @retval None
bogdanm 0:9b334a45a8ff 1210 */
bogdanm 0:9b334a45a8ff 1211 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 1212 {
bogdanm 0:9b334a45a8ff 1213 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
bogdanm 0:9b334a45a8ff 1214
bogdanm 0:9b334a45a8ff 1215 HAL_I2S_TxHalfCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1216 }
bogdanm 0:9b334a45a8ff 1217
bogdanm 0:9b334a45a8ff 1218 /**
bogdanm 0:9b334a45a8ff 1219 * @brief DMA I2S receive process complete callback
bogdanm 0:9b334a45a8ff 1220 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1221 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 1222 * @retval None
bogdanm 0:9b334a45a8ff 1223 */
bogdanm 0:9b334a45a8ff 1224 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 1225 {
bogdanm 0:9b334a45a8ff 1226 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm 0:9b334a45a8ff 1227
bogdanm 0:9b334a45a8ff 1228 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 1229 {
bogdanm 0:9b334a45a8ff 1230 /* Disable Rx DMA Request */
bogdanm 0:9b334a45a8ff 1231 hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 1232 hi2s->RxXferCount = 0;
bogdanm 0:9b334a45a8ff 1233 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1234 }
bogdanm 0:9b334a45a8ff 1235 HAL_I2S_RxCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1236 }
bogdanm 0:9b334a45a8ff 1237
bogdanm 0:9b334a45a8ff 1238 /**
bogdanm 0:9b334a45a8ff 1239 * @brief DMA I2S receive process half complete callback
bogdanm 0:9b334a45a8ff 1240 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1241 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 1242 * @retval None
bogdanm 0:9b334a45a8ff 1243 */
bogdanm 0:9b334a45a8ff 1244 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 1245 {
bogdanm 0:9b334a45a8ff 1246 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
bogdanm 0:9b334a45a8ff 1247
bogdanm 0:9b334a45a8ff 1248 HAL_I2S_RxHalfCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1249 }
bogdanm 0:9b334a45a8ff 1250
bogdanm 0:9b334a45a8ff 1251 /**
bogdanm 0:9b334a45a8ff 1252 * @brief DMA I2S communication error callback
bogdanm 0:9b334a45a8ff 1253 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1254 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 1255 * @retval None
bogdanm 0:9b334a45a8ff 1256 */
bogdanm 0:9b334a45a8ff 1257 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 1258 {
bogdanm 0:9b334a45a8ff 1259 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm 0:9b334a45a8ff 1260
bogdanm 0:9b334a45a8ff 1261 /* Disable Rx and Tx DMA Request */
bogdanm 0:9b334a45a8ff 1262 hi2s->Instance->CR2 &= (uint16_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
bogdanm 0:9b334a45a8ff 1263 hi2s->TxXferCount = 0;
bogdanm 0:9b334a45a8ff 1264 hi2s->RxXferCount = 0;
bogdanm 0:9b334a45a8ff 1265
bogdanm 0:9b334a45a8ff 1266 hi2s->State= HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1267
bogdanm 0:9b334a45a8ff 1268 /* Set the error code and execute error callback*/
bogdanm 0:9b334a45a8ff 1269 hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
bogdanm 0:9b334a45a8ff 1270 HAL_I2S_ErrorCallback(hi2s);
bogdanm 0:9b334a45a8ff 1271 }
bogdanm 0:9b334a45a8ff 1272
bogdanm 0:9b334a45a8ff 1273 /**
bogdanm 0:9b334a45a8ff 1274 * @brief Transmit an amount of data in non-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 1275 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1276 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1277 * @retval None
bogdanm 0:9b334a45a8ff 1278 */
bogdanm 0:9b334a45a8ff 1279 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1280 {
bogdanm 0:9b334a45a8ff 1281 /* Transmit data */
bogdanm 0:9b334a45a8ff 1282 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
bogdanm 0:9b334a45a8ff 1283 hi2s->TxXferCount--;
bogdanm 0:9b334a45a8ff 1284
bogdanm 0:9b334a45a8ff 1285 if(hi2s->TxXferCount == 0)
bogdanm 0:9b334a45a8ff 1286 {
bogdanm 0:9b334a45a8ff 1287 /* Disable TXE and ERR interrupt */
bogdanm 0:9b334a45a8ff 1288 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 1289
bogdanm 0:9b334a45a8ff 1290 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1291 HAL_I2S_TxCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1292 }
bogdanm 0:9b334a45a8ff 1293 }
bogdanm 0:9b334a45a8ff 1294
bogdanm 0:9b334a45a8ff 1295 /**
bogdanm 0:9b334a45a8ff 1296 * @brief Receive an amount of data in non-blocking mode with Interrupt
bogdanm 0:9b334a45a8ff 1297 * @param hi2s: I2S handle
bogdanm 0:9b334a45a8ff 1298 * @retval None
bogdanm 0:9b334a45a8ff 1299 */
bogdanm 0:9b334a45a8ff 1300 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1301 {
bogdanm 0:9b334a45a8ff 1302 /* Receive data */
bogdanm 0:9b334a45a8ff 1303 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
bogdanm 0:9b334a45a8ff 1304 hi2s->RxXferCount--;
bogdanm 0:9b334a45a8ff 1305
bogdanm 0:9b334a45a8ff 1306 if(hi2s->RxXferCount == 0)
bogdanm 0:9b334a45a8ff 1307 {
bogdanm 0:9b334a45a8ff 1308 /* Disable RXNE and ERR interrupt */
bogdanm 0:9b334a45a8ff 1309 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 1310
bogdanm 0:9b334a45a8ff 1311 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1312 HAL_I2S_RxCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1313 }
bogdanm 0:9b334a45a8ff 1314 }
bogdanm 0:9b334a45a8ff 1315
bogdanm 0:9b334a45a8ff 1316
bogdanm 0:9b334a45a8ff 1317 /**
bogdanm 0:9b334a45a8ff 1318 * @brief This function handles I2S Communication Timeout.
bogdanm 0:9b334a45a8ff 1319 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1320 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1321 * @param Flag: Flag checked
bogdanm 0:9b334a45a8ff 1322 * @param State: Value of the flag expected
bogdanm 0:9b334a45a8ff 1323 * @param Timeout: Duration of the timeout
bogdanm 0:9b334a45a8ff 1324 * @retval HAL status
bogdanm 0:9b334a45a8ff 1325 */
bogdanm 0:9b334a45a8ff 1326 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 1327 {
bogdanm 0:9b334a45a8ff 1328 uint32_t tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1329
bogdanm 0:9b334a45a8ff 1330 /* Wait until flag is set */
bogdanm 0:9b334a45a8ff 1331 if(State == RESET)
bogdanm 0:9b334a45a8ff 1332 {
bogdanm 0:9b334a45a8ff 1333 while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
bogdanm 0:9b334a45a8ff 1334 {
bogdanm 0:9b334a45a8ff 1335 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 1336 {
bogdanm 0:9b334a45a8ff 1337 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
bogdanm 0:9b334a45a8ff 1338 {
bogdanm 0:9b334a45a8ff 1339 /* Set the I2S State ready */
bogdanm 0:9b334a45a8ff 1340 hi2s->State= HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1341
bogdanm 0:9b334a45a8ff 1342 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1343 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 1344
bogdanm 0:9b334a45a8ff 1345 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1346 }
bogdanm 0:9b334a45a8ff 1347 }
bogdanm 0:9b334a45a8ff 1348 }
bogdanm 0:9b334a45a8ff 1349 }
bogdanm 0:9b334a45a8ff 1350 else
bogdanm 0:9b334a45a8ff 1351 {
bogdanm 0:9b334a45a8ff 1352 while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
bogdanm 0:9b334a45a8ff 1353 {
bogdanm 0:9b334a45a8ff 1354 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 1355 {
bogdanm 0:9b334a45a8ff 1356 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
bogdanm 0:9b334a45a8ff 1357 {
bogdanm 0:9b334a45a8ff 1358 /* Set the I2S State ready */
bogdanm 0:9b334a45a8ff 1359 hi2s->State= HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1360
bogdanm 0:9b334a45a8ff 1361 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1362 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 1363
bogdanm 0:9b334a45a8ff 1364 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1365 }
bogdanm 0:9b334a45a8ff 1366 }
bogdanm 0:9b334a45a8ff 1367 }
bogdanm 0:9b334a45a8ff 1368 }
bogdanm 0:9b334a45a8ff 1369 return HAL_OK;
bogdanm 0:9b334a45a8ff 1370 }
bogdanm 0:9b334a45a8ff 1371
bogdanm 0:9b334a45a8ff 1372 /**
bogdanm 0:9b334a45a8ff 1373 * @}
bogdanm 0:9b334a45a8ff 1374 */
bogdanm 0:9b334a45a8ff 1375
bogdanm 0:9b334a45a8ff 1376 /**
bogdanm 0:9b334a45a8ff 1377 * @}
bogdanm 0:9b334a45a8ff 1378 */
bogdanm 0:9b334a45a8ff 1379
bogdanm 0:9b334a45a8ff 1380 /**
bogdanm 0:9b334a45a8ff 1381 * @}
bogdanm 0:9b334a45a8ff 1382 */
bogdanm 0:9b334a45a8ff 1383
bogdanm 0:9b334a45a8ff 1384 #endif /* defined(STM32F031x6) || defined(STM32F038xx) || */
bogdanm 0:9b334a45a8ff 1385 /* defined(STM32F051x8) || defined(STM32F058xx) || */
bogdanm 0:9b334a45a8ff 1386 /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
bogdanm 0:9b334a45a8ff 1387 /* defined(STM32F042x6) || defined(STM32F048xx) || */
bogdanm 0:9b334a45a8ff 1388 /* defined(STM32F091xC) || defined(STM32F098xx) */
bogdanm 0:9b334a45a8ff 1389
bogdanm 0:9b334a45a8ff 1390 #endif /* HAL_I2S_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1391
bogdanm 0:9b334a45a8ff 1392 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/