en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
bogdanm 0:9b334a45a8ff 5 * based on core_cm3.h, V1.20
bogdanm 0:9b334a45a8ff 6 */
bogdanm 0:9b334a45a8ff 7
bogdanm 0:9b334a45a8ff 8 #ifndef __ARM7_CORE_H__
bogdanm 0:9b334a45a8ff 9 #define __ARM7_CORE_H__
bogdanm 0:9b334a45a8ff 10
bogdanm 0:9b334a45a8ff 11 #include "vector_defns.h"
bogdanm 0:9b334a45a8ff 12
bogdanm 0:9b334a45a8ff 13 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 14 extern "C" {
bogdanm 0:9b334a45a8ff 15 #endif
bogdanm 0:9b334a45a8ff 16
bogdanm 0:9b334a45a8ff 17 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
bogdanm 0:9b334a45a8ff 18 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
bogdanm 0:9b334a45a8ff 19 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
bogdanm 0:9b334a45a8ff 20
bogdanm 0:9b334a45a8ff 21 #define __CORTEX_M (0x03) /*!< Cortex core */
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 /**
bogdanm 0:9b334a45a8ff 24 * Lint configuration \n
bogdanm 0:9b334a45a8ff 25 * ----------------------- \n
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * The following Lint messages will be suppressed and not shown: \n
bogdanm 0:9b334a45a8ff 28 * \n
bogdanm 0:9b334a45a8ff 29 * --- Error 10: --- \n
bogdanm 0:9b334a45a8ff 30 * register uint32_t __regBasePri __asm("basepri"); \n
bogdanm 0:9b334a45a8ff 31 * Error 10: Expecting ';' \n
bogdanm 0:9b334a45a8ff 32 * \n
bogdanm 0:9b334a45a8ff 33 * --- Error 530: --- \n
bogdanm 0:9b334a45a8ff 34 * return(__regBasePri); \n
bogdanm 0:9b334a45a8ff 35 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
bogdanm 0:9b334a45a8ff 36 * \n
bogdanm 0:9b334a45a8ff 37 * --- Error 550: --- \n
bogdanm 0:9b334a45a8ff 38 * __regBasePri = (basePri & 0x1ff); \n
bogdanm 0:9b334a45a8ff 39 * } \n
bogdanm 0:9b334a45a8ff 40 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
bogdanm 0:9b334a45a8ff 41 * \n
bogdanm 0:9b334a45a8ff 42 * --- Error 754: --- \n
bogdanm 0:9b334a45a8ff 43 * uint32_t RESERVED0[24]; \n
bogdanm 0:9b334a45a8ff 44 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
bogdanm 0:9b334a45a8ff 45 * \n
bogdanm 0:9b334a45a8ff 46 * --- Error 750: --- \n
bogdanm 0:9b334a45a8ff 47 * #define __CM3_CORE_H__ \n
bogdanm 0:9b334a45a8ff 48 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
bogdanm 0:9b334a45a8ff 49 * \n
bogdanm 0:9b334a45a8ff 50 * --- Error 528: --- \n
bogdanm 0:9b334a45a8ff 51 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
bogdanm 0:9b334a45a8ff 52 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
bogdanm 0:9b334a45a8ff 53 * \n
bogdanm 0:9b334a45a8ff 54 * --- Error 751: --- \n
bogdanm 0:9b334a45a8ff 55 * } InterruptType_Type; \n
bogdanm 0:9b334a45a8ff 56 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
bogdanm 0:9b334a45a8ff 57 * \n
bogdanm 0:9b334a45a8ff 58 * \n
bogdanm 0:9b334a45a8ff 59 * Note: To re-enable a Message, insert a space before 'lint' * \n
bogdanm 0:9b334a45a8ff 60 *
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /*lint -save */
bogdanm 0:9b334a45a8ff 64 /*lint -e10 */
bogdanm 0:9b334a45a8ff 65 /*lint -e530 */
bogdanm 0:9b334a45a8ff 66 /*lint -e550 */
bogdanm 0:9b334a45a8ff 67 /*lint -e754 */
bogdanm 0:9b334a45a8ff 68 /*lint -e750 */
bogdanm 0:9b334a45a8ff 69 /*lint -e528 */
bogdanm 0:9b334a45a8ff 70 /*lint -e751 */
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 #include <stdint.h> /* Include standard types */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 75 /**
bogdanm 0:9b334a45a8ff 76 * @brief Return the Main Stack Pointer (current ARM7 stack)
bogdanm 0:9b334a45a8ff 77 *
bogdanm 0:9b334a45a8ff 78 * @param none
bogdanm 0:9b334a45a8ff 79 * @return uint32_t Main Stack Pointer
bogdanm 0:9b334a45a8ff 80 *
bogdanm 0:9b334a45a8ff 81 * Return the current value of the MSP (main stack pointer)
bogdanm 0:9b334a45a8ff 82 * Cortex processor register
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84 extern uint32_t __get_MSP(void);
bogdanm 0:9b334a45a8ff 85 #endif
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 #if defined (__ICCARM__)
bogdanm 0:9b334a45a8ff 89 #include <intrinsics.h> /* IAR Intrinsics */
bogdanm 0:9b334a45a8ff 90 #endif
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 #ifndef __NVIC_PRIO_BITS
bogdanm 0:9b334a45a8ff 94 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
bogdanm 0:9b334a45a8ff 95 #endif
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 typedef struct
bogdanm 0:9b334a45a8ff 98 {
bogdanm 0:9b334a45a8ff 99 uint32_t IRQStatus;
bogdanm 0:9b334a45a8ff 100 uint32_t FIQStatus;
bogdanm 0:9b334a45a8ff 101 uint32_t RawIntr;
bogdanm 0:9b334a45a8ff 102 uint32_t IntSelect;
bogdanm 0:9b334a45a8ff 103 uint32_t IntEnable;
bogdanm 0:9b334a45a8ff 104 uint32_t IntEnClr;
bogdanm 0:9b334a45a8ff 105 uint32_t SoftInt;
bogdanm 0:9b334a45a8ff 106 uint32_t SoftIntClr;
bogdanm 0:9b334a45a8ff 107 uint32_t Protection;
bogdanm 0:9b334a45a8ff 108 uint32_t SWPriorityMask;
bogdanm 0:9b334a45a8ff 109 uint32_t RESERVED0[54];
bogdanm 0:9b334a45a8ff 110 uint32_t VectAddr[32];
bogdanm 0:9b334a45a8ff 111 uint32_t RESERVED1[32];
bogdanm 0:9b334a45a8ff 112 uint32_t VectPriority[32];
bogdanm 0:9b334a45a8ff 113 uint32_t RESERVED2[800];
bogdanm 0:9b334a45a8ff 114 uint32_t Address;
bogdanm 0:9b334a45a8ff 115 } NVIC_TypeDef;
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 #define NVIC_BASE (0xFFFFF000)
bogdanm 0:9b334a45a8ff 118 #define NVIC (( NVIC_TypeDef *) NVIC_BASE)
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121
bogdanm 0:9b334a45a8ff 122 /**
bogdanm 0:9b334a45a8ff 123 * IO definitions
bogdanm 0:9b334a45a8ff 124 *
bogdanm 0:9b334a45a8ff 125 * define access restrictions to peripheral registers
bogdanm 0:9b334a45a8ff 126 */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 129 #define __I volatile /*!< defines 'read only' permissions */
bogdanm 0:9b334a45a8ff 130 #else
bogdanm 0:9b334a45a8ff 131 #define __I volatile const /*!< defines 'read only' permissions */
bogdanm 0:9b334a45a8ff 132 #endif
bogdanm 0:9b334a45a8ff 133 #define __O volatile /*!< defines 'write only' permissions */
bogdanm 0:9b334a45a8ff 134 #define __IO volatile /*!< defines 'read / write' permissions */
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 141 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 0:9b334a45a8ff 142 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 #elif defined ( __ICCARM__ )
bogdanm 0:9b334a45a8ff 145 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 0:9b334a45a8ff 146 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 #elif defined ( __GNUC__ )
bogdanm 0:9b334a45a8ff 149 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 0:9b334a45a8ff 150 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 #elif defined ( __TASKING__ )
bogdanm 0:9b334a45a8ff 153 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 0:9b334a45a8ff 154 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 #endif
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 /* ################### Compiler specific Intrinsics ########################### */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
bogdanm 0:9b334a45a8ff 162 /* ARM armcc specific functions */
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 #define __enable_fault_irq __enable_fiq
bogdanm 0:9b334a45a8ff 165 #define __disable_fault_irq __disable_fiq
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 #define __NOP __nop
bogdanm 0:9b334a45a8ff 168 //#define __WFI __wfi
bogdanm 0:9b334a45a8ff 169 //#define __WFE __wfe
bogdanm 0:9b334a45a8ff 170 //#define __SEV __sev
bogdanm 0:9b334a45a8ff 171 //#define __ISB() __isb(0)
bogdanm 0:9b334a45a8ff 172 //#define __DSB() __dsb(0)
bogdanm 0:9b334a45a8ff 173 //#define __DMB() __dmb(0)
bogdanm 0:9b334a45a8ff 174 //#define __REV __rev
bogdanm 0:9b334a45a8ff 175 //#define __RBIT __rbit
bogdanm 0:9b334a45a8ff 176 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
bogdanm 0:9b334a45a8ff 177 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
bogdanm 0:9b334a45a8ff 178 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
bogdanm 0:9b334a45a8ff 179 #define __STREXB(value, ptr) __strex(value, ptr)
bogdanm 0:9b334a45a8ff 180 #define __STREXH(value, ptr) __strex(value, ptr)
bogdanm 0:9b334a45a8ff 181 #define __STREXW(value, ptr) __strex(value, ptr)
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 #define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
bogdanm 0:9b334a45a8ff 184 LPC_VIC->IntEnClr = 0xffffffff
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 #define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
bogdanm 0:9b334a45a8ff 191 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
bogdanm 0:9b334a45a8ff 192 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 static __INLINE void __enable_irq() {
bogdanm 0:9b334a45a8ff 197 unsigned long temp;
bogdanm 0:9b334a45a8ff 198 __asm__ __volatile__("mrs %0, cpsr\n"
bogdanm 0:9b334a45a8ff 199 "bic %0, %0, #0x80\n"
bogdanm 0:9b334a45a8ff 200 "msr cpsr_c, %0"
bogdanm 0:9b334a45a8ff 201 : "=r" (temp)
bogdanm 0:9b334a45a8ff 202 :
bogdanm 0:9b334a45a8ff 203 : "memory");
bogdanm 0:9b334a45a8ff 204 }
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 static __INLINE void __disable_irq() {
bogdanm 0:9b334a45a8ff 207 unsigned long old,temp;
bogdanm 0:9b334a45a8ff 208 __asm__ __volatile__("mrs %0, cpsr\n"
bogdanm 0:9b334a45a8ff 209 "orr %1, %0, #0xc0\n"
bogdanm 0:9b334a45a8ff 210 "msr cpsr_c, %1"
bogdanm 0:9b334a45a8ff 211 : "=r" (old), "=r" (temp)
bogdanm 0:9b334a45a8ff 212 :
bogdanm 0:9b334a45a8ff 213 : "memory");
bogdanm 0:9b334a45a8ff 214 // return (old & 0x80) == 0;
bogdanm 0:9b334a45a8ff 215 }
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 static __INLINE void __NOP() { __ASM volatile ("nop"); }
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
bogdanm 0:9b334a45a8ff 220 /* TASKING carm specific functions */
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 /*
bogdanm 0:9b334a45a8ff 223 * The CMSIS functions have been implemented as intrinsics in the compiler.
bogdanm 0:9b334a45a8ff 224 * Please use "carm -?i" to get an up to date list of all instrinsics,
bogdanm 0:9b334a45a8ff 225 * Including the CMSIS ones.
bogdanm 0:9b334a45a8ff 226 */
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 #endif
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 /**
bogdanm 0:9b334a45a8ff 232 * @brief Enable Interrupt in NVIC Interrupt Controller
bogdanm 0:9b334a45a8ff 233 *
bogdanm 0:9b334a45a8ff 234 * @param IRQn_Type IRQn specifies the interrupt number
bogdanm 0:9b334a45a8ff 235 * @return none
bogdanm 0:9b334a45a8ff 236 *
bogdanm 0:9b334a45a8ff 237 * Enable a device specific interupt in the NVIC interrupt controller.
bogdanm 0:9b334a45a8ff 238 * The interrupt number cannot be a negative value.
bogdanm 0:9b334a45a8ff 239 */
bogdanm 0:9b334a45a8ff 240 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 241 {
bogdanm 0:9b334a45a8ff 242 NVIC->IntEnable = 1 << (uint32_t)IRQn;
bogdanm 0:9b334a45a8ff 243 }
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 /**
bogdanm 0:9b334a45a8ff 247 * @brief Disable the interrupt line for external interrupt specified
bogdanm 0:9b334a45a8ff 248 *
bogdanm 0:9b334a45a8ff 249 * @param IRQn_Type IRQn is the positive number of the external interrupt
bogdanm 0:9b334a45a8ff 250 * @return none
bogdanm 0:9b334a45a8ff 251 *
bogdanm 0:9b334a45a8ff 252 * Disable a device specific interupt in the NVIC interrupt controller.
bogdanm 0:9b334a45a8ff 253 * The interrupt number cannot be a negative value.
bogdanm 0:9b334a45a8ff 254 */
bogdanm 0:9b334a45a8ff 255 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 256 {
bogdanm 0:9b334a45a8ff 257 NVIC->IntEnClr = 1 << (uint32_t)IRQn;
bogdanm 0:9b334a45a8ff 258 }
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 static __INLINE uint32_t __get_IPSR(void)
bogdanm 0:9b334a45a8ff 261 {
bogdanm 0:9b334a45a8ff 262 unsigned i;
bogdanm 0:9b334a45a8ff 263
bogdanm 0:9b334a45a8ff 264 for(i = 0; i < 32; i ++)
bogdanm 0:9b334a45a8ff 265 if(NVIC->Address == NVIC->VectAddr[i])
bogdanm 0:9b334a45a8ff 266 return i;
bogdanm 0:9b334a45a8ff 267 return 1; // 1 is an invalid entry in the interrupt table on LPC2368
bogdanm 0:9b334a45a8ff 268 }
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 271 }
bogdanm 0:9b334a45a8ff 272 #endif
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 #endif /* __ARM7_CORE_H__ */
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 /*lint -restore */