mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/bitfields.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	#ifndef MBED_BITFIELDS_H
bogdanm	0:9b334a45a8ff	2	#define MBED_BITFIELDS_H
bogdanm	0:9b334a45a8ff	3
bogdanm	0:9b334a45a8ff	4	//! Massage x for use in bitfield name.
bogdanm	0:9b334a45a8ff	5	#define BFN_PREP(x, name) ( ((x)<<name##_SHIFT) & name##_MASK )
bogdanm	0:9b334a45a8ff	6
bogdanm	0:9b334a45a8ff	7	//! Get the value of bitfield name from y. Equivalent to (var=) y.name
bogdanm	0:9b334a45a8ff	8	#define BFN_GET(y, name) ( ((y) & name##_MASK)>>name##_SHIFT )
bogdanm	0:9b334a45a8ff	9
bogdanm	0:9b334a45a8ff	10	//! Set bitfield name from y to x: y.name= x.
bogdanm	0:9b334a45a8ff	11	#define BFN_SET(y, x, name) (y = ((y)&~name##_MASK) \| BFN_PREP(x,name) )
bogdanm	0:9b334a45a8ff	12
bogdanm	0:9b334a45a8ff	13
bogdanm	0:9b334a45a8ff	14	/* SYSMEMREMAP, address 0x4004 8000 */
bogdanm	0:9b334a45a8ff	15	#define SYSMEMREMAP_MAP_MASK 0x0003 // System memory remap
bogdanm	0:9b334a45a8ff	16	#define SYSMEMREMAP_MAP_SHIFT 0
bogdanm	0:9b334a45a8ff	17
bogdanm	0:9b334a45a8ff	18	/* PRESETCTRL, address 0x4004 8004 */
bogdanm	0:9b334a45a8ff	19	#define PRESETCTRL_SSP0_RST_N (1 << 0) // SPI0 reset control
bogdanm	0:9b334a45a8ff	20	#define PRESETCTRL_I2C_RST_N (1 << 1) // I2C reset control
bogdanm	0:9b334a45a8ff	21	#define PRESETCTRL_SSP1_RST_N (1 << 2) // SPI1 reset control
bogdanm	0:9b334a45a8ff	22	#define PRESETCTRL_CAN_RST_N (1 << 3) // C_CAN reset control. See Section 3.1 for part specific details.
bogdanm	0:9b334a45a8ff	23
bogdanm	0:9b334a45a8ff	24	/* SYSPLLCTRL, address 0x4004 8008 */
bogdanm	0:9b334a45a8ff	25	#define SYSPLLCTRL_MSEL_MASK 0x001F // Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32.
bogdanm	0:9b334a45a8ff	26	#define SYSPLLCTRL_MSEL_SHIFT 0
bogdanm	0:9b334a45a8ff	27	#define SYSPLLCTRL_PSEL_MASK 0x0060 // Post divider ratio P. The division ratio is 2 P.
bogdanm	0:9b334a45a8ff	28	#define SYSPLLCTRL_PSEL_SHIFT 5
bogdanm	0:9b334a45a8ff	29
bogdanm	0:9b334a45a8ff	30	/* SYSPLLSTAT, address 0x4004 800C */
bogdanm	0:9b334a45a8ff	31	#define SYSPLLSTAT_LOCK (1 << 0) // PLL lock status
bogdanm	0:9b334a45a8ff	32
bogdanm	0:9b334a45a8ff	33	/* SYSOSCCTRL, address 0x4004 8020 */
bogdanm	0:9b334a45a8ff	34	#define SYSOSCCTRL_BYPASS (1 << 0) // Bypass system oscillator
bogdanm	0:9b334a45a8ff	35	#define SYSOSCCTRL_FREQRANGE (1 << 1) // Determines frequency range for Low-power oscillator.
bogdanm	0:9b334a45a8ff	36
bogdanm	0:9b334a45a8ff	37	/* WDTOSCCTRL, address 0x4004 8024 */
bogdanm	0:9b334a45a8ff	38	#define WDTOSCCTRL_DIVSEL_MASK 0x001F // Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 (1 + DIVSEL)) 00000: 2 (1 + DIVSEL) = 2 00001: 2 (1 + DIVSEL) = 4 to 11111: 2 (1 + DIVSEL) = 64
bogdanm	0:9b334a45a8ff	39	#define WDTOSCCTRL_DIVSEL_SHIFT 0
bogdanm	0:9b334a45a8ff	40	#define WDTOSCCTRL_FREQSEL_MASK 0x01E0 // Select watchdog oscillator analog output frequency (Fclkana).
bogdanm	0:9b334a45a8ff	41	#define WDTOSCCTRL_FREQSEL_SHIFT 5
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	/* IRCCTRL, address 0x4004 8028 */
bogdanm	0:9b334a45a8ff	44	#define IRCCTRL_TRIM_MASK 0x00FF // Trim value
bogdanm	0:9b334a45a8ff	45	#define IRCCTRL_TRIM_SHIFT 0
bogdanm	0:9b334a45a8ff	46
bogdanm	0:9b334a45a8ff	47	/* SYSRSTSTAT, address 0x4004 8030 */
bogdanm	0:9b334a45a8ff	48	#define SYSRSTSTAT_POR (1 << 0) // POR reset status
bogdanm	0:9b334a45a8ff	49	#define SYSRSTSTAT_EXTRST (1 << 1) // Status of the external RESET pin.
bogdanm	0:9b334a45a8ff	50	#define SYSRSTSTAT_WDT (1 << 2) // Status of the Watchdog reset
bogdanm	0:9b334a45a8ff	51	#define SYSRSTSTAT_BOD (1 << 3) // Status of the Brown-out detect reset
bogdanm	0:9b334a45a8ff	52	#define SYSRSTSTAT_SYSRST (1 << 4) // Status of the software system reset
bogdanm	0:9b334a45a8ff	53
bogdanm	0:9b334a45a8ff	54	/* SYSPLLCLKSEL, address 0x4004 8040 */
bogdanm	0:9b334a45a8ff	55	#define SYSPLLCLKSEL_SEL_MASK 0x0003 // System PLL clock source
bogdanm	0:9b334a45a8ff	56	#define SYSPLLCLKSEL_SEL_SHIFT 0
bogdanm	0:9b334a45a8ff	57
bogdanm	0:9b334a45a8ff	58	/* SYSPLLCLKUEN, address 0x4004 8044 */
bogdanm	0:9b334a45a8ff	59	#define SYSPLLCLKUEN_ENA (1 << 0) // Enable system PLL clock source update
bogdanm	0:9b334a45a8ff	60
bogdanm	0:9b334a45a8ff	61	/* MAINCLKSEL, address 0x4004 8070 */
bogdanm	0:9b334a45a8ff	62	#define MAINCLKSEL_SEL_MASK 0x0003 // Clock source for main clock
bogdanm	0:9b334a45a8ff	63	#define MAINCLKSEL_SEL_SHIFT 0
bogdanm	0:9b334a45a8ff	64
bogdanm	0:9b334a45a8ff	65	/* MAINCLKUEN, address 0x4004 8074 */
bogdanm	0:9b334a45a8ff	66	#define MAINCLKUEN_ENA (1 << 0) // Enable main clock source update 0
bogdanm	0:9b334a45a8ff	67
bogdanm	0:9b334a45a8ff	68	/* SYSAHBCLKDIV, address 0x4004 8078 */
bogdanm	0:9b334a45a8ff	69	#define SYSAHBCLKDIV_DIV_MASK 0x00FF // System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
bogdanm	0:9b334a45a8ff	70	#define SYSAHBCLKDIV_DIV_SHIFT 0
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	/* SYSAHBCLKCTRL, address 0x4004 8080 */
bogdanm	0:9b334a45a8ff	73	#define SYSAHBCLKCTRL_SYS (1 << 0) // Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only.
bogdanm	0:9b334a45a8ff	74	#define SYSAHBCLKCTRL_ROM (1 << 1) // Enables clock for ROM.
bogdanm	0:9b334a45a8ff	75	#define SYSAHBCLKCTRL_RAM (1 << 2) // Enables clock for RAM.
bogdanm	0:9b334a45a8ff	76	#define SYSAHBCLKCTRL_FLASHREG (1 << 3) // Enables clock for flash register interface.
bogdanm	0:9b334a45a8ff	77	#define SYSAHBCLKCTRL_FLASHARRAY (1 << 4) // Enables clock for flash array access.
bogdanm	0:9b334a45a8ff	78	#define SYSAHBCLKCTRL_I2C (1 << 5) // Enables clock for I2C.
bogdanm	0:9b334a45a8ff	79	#define SYSAHBCLKCTRL_GPIO (1 << 6) // Enables clock for GPIO.
bogdanm	0:9b334a45a8ff	80	#define SYSAHBCLKCTRL_CT16B0 (1 << 7) // Enables clock for 16-bit counter/timer 0.
bogdanm	0:9b334a45a8ff	81	#define SYSAHBCLKCTRL_CT16B1 (1 << 8) // Enables clock for 16-bit counter/timer 1.
bogdanm	0:9b334a45a8ff	82	#define SYSAHBCLKCTRL_CT32B0 (1 << 9) // Enables clock for 32-bit counter/timer 0.
bogdanm	0:9b334a45a8ff	83	#define SYSAHBCLKCTRL_CT32B1 (1 << 10) // Enables clock for 32-bit counter/timer 1.
bogdanm	0:9b334a45a8ff	84	#define SYSAHBCLKCTRL_SSP0 (1 << 11) // Enables clock for SPI0.
bogdanm	0:9b334a45a8ff	85	#define SYSAHBCLKCTRL_UART (1 << 12) // Enables clock for UART. See Section 3.1 for part specific details.
bogdanm	0:9b334a45a8ff	86	#define SYSAHBCLKCTRL_ADC (1 << 13) // Enables clock for ADC.
bogdanm	0:9b334a45a8ff	87	#define SYSAHBCLKCTRL_WDT (1 << 15) // Enables clock for WDT.
bogdanm	0:9b334a45a8ff	88	#define SYSAHBCLKCTRL_IOCON (1 << 16) // Enables clock for I/O configuration block.
bogdanm	0:9b334a45a8ff	89	#define SYSAHBCLKCTRL_CAN (1 << 17) // Enables clock for C_CAN. See Section 3.1 for part specific details.
bogdanm	0:9b334a45a8ff	90	#define SYSAHBCLKCTRL_SSP1 (1 << 18) // Enables clock for SPI1.
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	/* SSP0CLKDIV, address 0x4004 8094 */
bogdanm	0:9b334a45a8ff	93	#define SSP0CLKDIV_DIV_MASK 0x00FF // SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255.
bogdanm	0:9b334a45a8ff	94	#define SSP0CLKDIV_DIV_SHIFT 0
bogdanm	0:9b334a45a8ff	95
bogdanm	0:9b334a45a8ff	96	/* UARTCLKDIV, address 0x4004 8098 */
bogdanm	0:9b334a45a8ff	97	#define UARTCLKDIV_DIV_MASK 0x00FF // UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255.
bogdanm	0:9b334a45a8ff	98	#define UARTCLKDIV_DIV_SHIFT 0
bogdanm	0:9b334a45a8ff	99
bogdanm	0:9b334a45a8ff	100	/* SSP1CLKDIV, address 0x4004 809C */
bogdanm	0:9b334a45a8ff	101	#define SSP1CLKDIV_DIV_MASK 0x00FF // SPI1_PCLK clock divider values 0: Disable SPI1_PCLK. 1: Divide by 1. to 255: Divide by 255.
bogdanm	0:9b334a45a8ff	102	#define SSP1CLKDIV_DIV_SHIFT 0
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	/* WDTCLKSEL, address 0x4004 80D0 */
bogdanm	0:9b334a45a8ff	105	#define WDTCLKSEL_SEL_MASK 0x0003 // WDT clock source
bogdanm	0:9b334a45a8ff	106	#define WDTCLKSEL_SEL_SHIFT 0
bogdanm	0:9b334a45a8ff	107
bogdanm	0:9b334a45a8ff	108	/* WDTCLKUEN, address 0x4004 80D4 */
bogdanm	0:9b334a45a8ff	109	#define WDTCLKUEN_ENA (1 << 0) // Enable WDT clock source update
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111	/* WDTCLKDIV, address 0x4004 80D8 */
bogdanm	0:9b334a45a8ff	112	#define WDTCLKDIV_DIV_MASK 0x00FF // WDT clock divider values 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255.
bogdanm	0:9b334a45a8ff	113	#define WDTCLKDIV_DIV_SHIFT 0
bogdanm	0:9b334a45a8ff	114
bogdanm	0:9b334a45a8ff	115	/* CLKOUTCLKSEL, address 0x4004 80E0 */
bogdanm	0:9b334a45a8ff	116	#define CLKOUTCLKSEL_SEL_MASK 0x0003 // CLKOUT clock source
bogdanm	0:9b334a45a8ff	117	#define CLKOUTCLKSEL_SEL_SHIFT 0
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	/* CLKOUTUEN, address 0x4004 80E4 */
bogdanm	0:9b334a45a8ff	120	#define CLKOUTUEN_ENA (1 << 0) // Enable CLKOUT clock source update 0
bogdanm	0:9b334a45a8ff	121
bogdanm	0:9b334a45a8ff	122	/* CLKOUTCLKDIV, address 0x4004 80E8 */
bogdanm	0:9b334a45a8ff	123	#define CLKOUTCLKDIV_DIV_MASK 0x00FF // Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255.
bogdanm	0:9b334a45a8ff	124	#define CLKOUTCLKDIV_DIV_SHIFT 0
bogdanm	0:9b334a45a8ff	125
bogdanm	0:9b334a45a8ff	126	/* PIOPORCAP0, address 0x4004 8100 */
bogdanm	0:9b334a45a8ff	127	#define PIOPORCAP0_CAPPIO0_N_MASK 0x0FFF // Raw reset status input PIO0_n: PIO0_11 to PIO0_0
bogdanm	0:9b334a45a8ff	128	#define PIOPORCAP0_CAPPIO0_N_SHIFT 0
bogdanm	0:9b334a45a8ff	129	#define PIOPORCAP0_CAPPIO1_N_MASK 0xFFF000 // Raw reset status input PIO1_n: PIO1_11 to PIO1_0
bogdanm	0:9b334a45a8ff	130	#define PIOPORCAP0_CAPPIO1_N_SHIFT 12
bogdanm	0:9b334a45a8ff	131	#define PIOPORCAP0_CAPPIO2_N_MASK 0xFF000000 // Raw reset status input PIO2_n: PIO2_7 to PIO2_0
bogdanm	0:9b334a45a8ff	132	#define PIOPORCAP0_CAPPIO2_N_SHIFT 24
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	/* PIOPORCAP1, address 0x4004 8104 */
bogdanm	0:9b334a45a8ff	135	#define PIOPORCAP1_CAPPIO2_8 (1 << 0) // Raw reset status input PIO2_8
bogdanm	0:9b334a45a8ff	136	#define PIOPORCAP1_CAPPIO2_9 (1 << 1) // Raw reset status input PIO2_9
bogdanm	0:9b334a45a8ff	137	#define PIOPORCAP1_CAPPIO2_10 (1 << 2) // Raw reset status input PIO2_10
bogdanm	0:9b334a45a8ff	138	#define PIOPORCAP1_CAPPIO2_11 (1 << 3) // Raw reset status input PIO2_11
bogdanm	0:9b334a45a8ff	139	#define PIOPORCAP1_CAPPIO3_0 (1 << 4) // Raw reset status input PIO3_0
bogdanm	0:9b334a45a8ff	140	#define PIOPORCAP1_CAPPIO3_1 (1 << 5) // Raw reset status input PIO3_1
bogdanm	0:9b334a45a8ff	141	#define PIOPORCAP1_CAPPIO3_2 (1 << 6) // Raw reset status input PIO3_2
bogdanm	0:9b334a45a8ff	142	#define PIOPORCAP1_CAPPIO3_3 (1 << 7) // Raw reset status input PIO3_3
bogdanm	0:9b334a45a8ff	143	#define PIOPORCAP1_CAPPIO3_4 (1 << 8) // Raw reset status input PIO3_4
bogdanm	0:9b334a45a8ff	144	#define PIOPORCAP1_CAPPIO3_5 (1 << 9) // Raw reset status input PIO3_5
bogdanm	0:9b334a45a8ff	145
bogdanm	0:9b334a45a8ff	146	/* BODCTRL, address 0x4004 8150 */
bogdanm	0:9b334a45a8ff	147	#define BODCTRL_BODRSTLEV_MASK 0x0003 // BOD reset level
bogdanm	0:9b334a45a8ff	148	#define BODCTRL_BODRSTLEV_SHIFT 0
bogdanm	0:9b334a45a8ff	149	#define BODCTRL_BODINTVAL_MASK 0x000C // BOD interrupt level
bogdanm	0:9b334a45a8ff	150	#define BODCTRL_BODINTVAL_SHIFT 2
bogdanm	0:9b334a45a8ff	151	#define BODCTRL_BODRSTENA (1 << 4) // BOD reset enable
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	/* SYSTCKCAL, address 0x4004 8154 */
bogdanm	0:9b334a45a8ff	154	#define SYSTCKCAL_CAL_MASK 0x3FFFFFF // System tick timer calibration value
bogdanm	0:9b334a45a8ff	155	#define SYSTCKCAL_CAL_SHIFT 0
bogdanm	0:9b334a45a8ff	156
bogdanm	0:9b334a45a8ff	157	/* NMISRC, address 0x4004 8174 */
bogdanm	0:9b334a45a8ff	158	#define NMISRC_IRQNO_MASK 0x001F // The IRQ number of the interrupt that acts as the Non-Maskable Interrupt 0 (NMI) if bit 31 in this register is 1. See Table 54 for the list of interrupt sources and their IRQ numbers.
bogdanm	0:9b334a45a8ff	159	#define NMISRC_IRQNO_SHIFT 0
bogdanm	0:9b334a45a8ff	160	#define NMISRC_NMIEN (1 << 31) // Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	/* STARTAPRP0, address 0x4004 8200 */
bogdanm	0:9b334a45a8ff	163	#define STARTAPRP0_APRPIO0_N_MASK 0x0FFF // Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge
bogdanm	0:9b334a45a8ff	164	#define STARTAPRP0_APRPIO0_N_SHIFT 0
bogdanm	0:9b334a45a8ff	165	#define STARTAPRP0_APRPIO1_0 (1 << 12) // Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge Reserved. Do not write a 1 to reserved bits in this register.
bogdanm	0:9b334a45a8ff	166
bogdanm	0:9b334a45a8ff	167	/* STARTERP0, address 0x4004 8204 */
bogdanm	0:9b334a45a8ff	168	#define STARTERP0_ERPIO0_N_MASK 0x0FFF // Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled
bogdanm	0:9b334a45a8ff	169	#define STARTERP0_ERPIO0_N_SHIFT 0
bogdanm	0:9b334a45a8ff	170	#define STARTERP0_ERPIO1_0 (1 << 12) // Enable start signal for start logic input PIO1_0 0 = Disabled 1 = Enabled Reserved. Do not write a 1 to reserved bits in this register.
bogdanm	0:9b334a45a8ff	171
bogdanm	0:9b334a45a8ff	172	/* STARTRSRP0CLR, address 0x4004 8208 */
bogdanm	0:9b334a45a8ff	173	#define STARTRSRP0CLR_RSRPIO0_N_MASK 0x0FFF // Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.
bogdanm	0:9b334a45a8ff	174	#define STARTRSRP0CLR_RSRPIO0_N_SHIFT 0
bogdanm	0:9b334a45a8ff	175	#define STARTRSRP0CLR_RSRPIO1_0 (1 << 12) // Start signal reset for start logic input PIO1_0 0 = Do nothing. 1 = Writing 1 resets the start signal.
bogdanm	0:9b334a45a8ff	176
bogdanm	0:9b334a45a8ff	177	/* STARTSRP0, address 0x4004 820C */
bogdanm	0:9b334a45a8ff	178	#define STARTSRP0_SRPIO0_N_MASK 0x0FFF // Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.
bogdanm	0:9b334a45a8ff	179	#define STARTSRP0_SRPIO0_N_SHIFT 0
bogdanm	0:9b334a45a8ff	180	#define STARTSRP0_SRPIO1_0 (1 << 12) // Start signal status for start logic input PIO1_0 0 = No start signal received. 1 = Start signal pending.
bogdanm	0:9b334a45a8ff	181
bogdanm	0:9b334a45a8ff	182	/* PDSLEEPCFG, address 0x4004 8230 */
bogdanm	0:9b334a45a8ff	183	#define PDSLEEPCFG_BOD_PD (1 << 3) // BOD power-down control in Deep-sleep mode, see Table 40.
bogdanm	0:9b334a45a8ff	184	#define PDSLEEPCFG_WDTOSC_PD (1 << 6) // Watchdog oscillator power control in Deep-sleep mode, see Table 40.
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	/* PDAWAKECFG, address 0x4004 8234 */
bogdanm	0:9b334a45a8ff	187	#define PDAWAKECFG_IRCOUT_PD (1 << 0) // IRC oscillator output wake-up configuration
bogdanm	0:9b334a45a8ff	188	#define PDAWAKECFG_IRC_PD (1 << 1) // IRC oscillator power-down wake-up configuration
bogdanm	0:9b334a45a8ff	189	#define PDAWAKECFG_FLASH_PD (1 << 2) // Flash wake-up configuration
bogdanm	0:9b334a45a8ff	190	#define PDAWAKECFG_BOD_PD (1 << 3) // BOD wake-up configuration
bogdanm	0:9b334a45a8ff	191	#define PDAWAKECFG_ADC_PD (1 << 4) // ADC wake-up configuration
bogdanm	0:9b334a45a8ff	192	#define PDAWAKECFG_SYSOSC_PD (1 << 5) // System oscillator wake-up configuration
bogdanm	0:9b334a45a8ff	193	#define PDAWAKECFG_WDTOSC_PD (1 << 6) // Watchdog oscillator wake-up configuration
bogdanm	0:9b334a45a8ff	194	#define PDAWAKECFG_SYSPLL_PD (1 << 7) // System PLL wake-up configuration
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	/* PDRUNCFG, address 0x4004 8238 */
bogdanm	0:9b334a45a8ff	197	#define PDRUNCFG_IRCOUT_PD (1 << 0) // IRC oscillator output power-down
bogdanm	0:9b334a45a8ff	198	#define PDRUNCFG_IRC_PD (1 << 1) // IRC oscillator power-down
bogdanm	0:9b334a45a8ff	199	#define PDRUNCFG_FLASH_PD (1 << 2) // Flash power-down
bogdanm	0:9b334a45a8ff	200	#define PDRUNCFG_BOD_PD (1 << 3) // BOD power-down
bogdanm	0:9b334a45a8ff	201	#define PDRUNCFG_ADC_PD (1 << 4) // ADC power-down
bogdanm	0:9b334a45a8ff	202	#define PDRUNCFG_SYSOSC_PD (1 << 5) // System oscillator power-down
bogdanm	0:9b334a45a8ff	203	#define PDRUNCFG_WDTOSC_PD (1 << 6) // Watchdog oscillator power-down
bogdanm	0:9b334a45a8ff	204	#define PDRUNCFG_SYSPLL_PD (1 << 7) // System PLL power-down
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	/* DEVICE_ID, address 0x4004 83F4 */
bogdanm	0:9b334a45a8ff	207	#define DEVICE_ID_DEVICEID_MASK 0xFFFFFFFF // Part ID numbers for LPC111x/LPC11Cxx parts
bogdanm	0:9b334a45a8ff	208	#define DEVICE_ID_DEVICEID_SHIFT 0
bogdanm	0:9b334a45a8ff	209
bogdanm	0:9b334a45a8ff	210	/* FLASHCFG, address 0x4003 C010 */
bogdanm	0:9b334a45a8ff	211	#define FLASHCFG_FLASHTIM_MASK 0x0003 // Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
bogdanm	0:9b334a45a8ff	212	#define FLASHCFG_FLASHTIM_SHIFT 0
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	/* PCON, address 0x4003 8000 */
bogdanm	0:9b334a45a8ff	215	#define PCON_DPDEN (1 << 1) // Deep power-down mode enable
bogdanm	0:9b334a45a8ff	216	#define PCON_SLEEPFLAG (1 << 8) // Sleep mode flag
bogdanm	0:9b334a45a8ff	217	#define PCON_DPDFLAG (1 << 11) // Deep power-down flag
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	/* GPREG0 - GPREG3, address 0x4003 8004 to 0x4003 8010 */
bogdanm	0:9b334a45a8ff	220	#define GPREGn_GPDATA_MASK 0xFFFFFFFF // Data retained during Deep power-down mode.
bogdanm	0:9b334a45a8ff	221	#define GPREGn_GPDATA_SHIFT 0
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	/* GPREG4, address 0x4003 8014 */
bogdanm	0:9b334a45a8ff	224	#define GPREG4_WAKEUPHYS (1 << 10) // WAKEUP pin hysteresis enable
bogdanm	0:9b334a45a8ff	225	#define GPREG4_GPDATA_MASK 0xFFFFF800 // Data retained during Deep power-down mode.
bogdanm	0:9b334a45a8ff	226	#define GPREG4_GPDATA_SHIFT 11
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	/* IOCON_PIO2_6, address 0x4004 4000 */
bogdanm	0:9b334a45a8ff	229	#define IOCON_PIO2_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	230	#define IOCON_PIO2_6_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	231	#define IOCON_PIO2_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	232	#define IOCON_PIO2_6_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	233	#define IOCON_PIO2_6_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	234	#define IOCON_PIO2_6_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	235
bogdanm	0:9b334a45a8ff	236	/* IOCON_PIO2_0, address 0x4004 4008 */
bogdanm	0:9b334a45a8ff	237	#define IOCON_PIO2_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	238	#define IOCON_PIO2_0_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	239	#define IOCON_PIO2_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	240	#define IOCON_PIO2_0_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	241	#define IOCON_PIO2_0_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	242	#define IOCON_PIO2_0_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	243
bogdanm	0:9b334a45a8ff	244	/* IOCON_RESET_PIO0_0, address 0x4004 400C */
bogdanm	0:9b334a45a8ff	245	#define IOCON_RESET_PIO0_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	246	#define IOCON_RESET_PIO0_0_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	247	#define IOCON_RESET_PIO0_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	248	#define IOCON_RESET_PIO0_0_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	249	#define IOCON_RESET_PIO0_0_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	250	#define IOCON_RESET_PIO0_0_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	251
bogdanm	0:9b334a45a8ff	252	/* IOCON_PIO0_1, address 0x4004 4010 */
bogdanm	0:9b334a45a8ff	253	#define IOCON_PIO0_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	254	#define IOCON_PIO0_1_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	255	#define IOCON_PIO0_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	256	#define IOCON_PIO0_1_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	257	#define IOCON_PIO0_1_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	258	#define IOCON_PIO0_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	259
bogdanm	0:9b334a45a8ff	260	/* IOCON_PIO1_8, address 0x4004 4014 */
bogdanm	0:9b334a45a8ff	261	#define IOCON_PIO1_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	262	#define IOCON_PIO1_8_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	263	#define IOCON_PIO1_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	264	#define IOCON_PIO1_8_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	265	#define IOCON_PIO1_8_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	266	#define IOCON_PIO1_8_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	/* IOCON_PIO0_2, address 0x4004 401C */
bogdanm	0:9b334a45a8ff	269	#define IOCON_PIO0_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	270	#define IOCON_PIO0_2_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	271	#define IOCON_PIO0_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	272	#define IOCON_PIO0_2_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	273	#define IOCON_PIO0_2_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	274	#define IOCON_PIO0_2_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	275
bogdanm	0:9b334a45a8ff	276	/* IOCON_PIO2_7, address 0x4004 4020 */
bogdanm	0:9b334a45a8ff	277	#define IOCON_PIO2_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	278	#define IOCON_PIO2_7_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	279	#define IOCON_PIO2_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	280	#define IOCON_PIO2_7_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	281	#define IOCON_PIO2_7_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	282	#define IOCON_PIO2_7_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	/* IOCON_PIO2_8, address 0x4004 4024 */
bogdanm	0:9b334a45a8ff	285	#define IOCON_PIO2_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	286	#define IOCON_PIO2_8_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	287	#define IOCON_PIO2_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	288	#define IOCON_PIO2_8_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	289	#define IOCON_PIO2_8_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	290	#define IOCON_PIO2_8_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/* IOCON_PIO2_1, address 0x4004 4028 */
bogdanm	0:9b334a45a8ff	293	#define IOCON_PIO2_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	294	#define IOCON_PIO2_1_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	295	#define IOCON_PIO2_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	296	#define IOCON_PIO2_1_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	297	#define IOCON_PIO2_1_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	298	#define IOCON_PIO2_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	299
bogdanm	0:9b334a45a8ff	300	/* IOCON_PIO0_3, address 0x4004 402C */
bogdanm	0:9b334a45a8ff	301	#define IOCON_PIO0_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	302	#define IOCON_PIO0_3_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	303	#define IOCON_PIO0_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	304	#define IOCON_PIO0_3_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	305	#define IOCON_PIO0_3_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	306	#define IOCON_PIO0_3_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	307
bogdanm	0:9b334a45a8ff	308	/* IOCON_PIO0_4, address 0x4004 4030 */
bogdanm	0:9b334a45a8ff	309	#define IOCON_PIO0_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	310	#define IOCON_PIO0_4_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	311	#define IOCON_PIO0_4_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, 00 default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
bogdanm	0:9b334a45a8ff	312	#define IOCON_PIO0_4_I2CMODE_SHIFT 8
bogdanm	0:9b334a45a8ff	313
bogdanm	0:9b334a45a8ff	314	/* IOCON_PIO0_5, address 0x4004 4034 */
bogdanm	0:9b334a45a8ff	315	#define IOCON_PIO0_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	316	#define IOCON_PIO0_5_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	317	#define IOCON_PIO0_5_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
bogdanm	0:9b334a45a8ff	318	#define IOCON_PIO0_5_I2CMODE_SHIFT 8
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320	/* IOCON_PIO1_9, address 0x4004 4038 */
bogdanm	0:9b334a45a8ff	321	#define IOCON_PIO1_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	322	#define IOCON_PIO1_9_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	323	#define IOCON_PIO1_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	324	#define IOCON_PIO1_9_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	325	#define IOCON_PIO1_9_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	326	#define IOCON_PIO1_9_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	327
bogdanm	0:9b334a45a8ff	328	/* IOCON_PIO3_4, address 0x4004 403C */
bogdanm	0:9b334a45a8ff	329	#define IOCON_PIO3_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	330	#define IOCON_PIO3_4_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	331	#define IOCON_PIO3_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	332	#define IOCON_PIO3_4_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	333	#define IOCON_PIO3_4_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	334	#define IOCON_PIO3_4_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	/* IOCON_PIO2_4, address 0x4004 4040 */
bogdanm	0:9b334a45a8ff	337	#define IOCON_PIO2_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	338	#define IOCON_PIO2_4_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	339	#define IOCON_PIO2_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	340	#define IOCON_PIO2_4_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	341	#define IOCON_PIO2_4_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	342	#define IOCON_PIO2_4_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	/* IOCON_PIO2_5, address 0x4004 4044 */
bogdanm	0:9b334a45a8ff	345	#define IOCON_PIO2_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	346	#define IOCON_PIO2_5_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	347	#define IOCON_PIO2_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	348	#define IOCON_PIO2_5_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	349	#define IOCON_PIO2_5_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	350	#define IOCON_PIO2_5_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/* IOCON_PIO3_5, address 0x4004 4048 */
bogdanm	0:9b334a45a8ff	353	#define IOCON_PIO3_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	354	#define IOCON_PIO3_5_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	355	#define IOCON_PIO3_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	356	#define IOCON_PIO3_5_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	357	#define IOCON_PIO3_5_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	358	#define IOCON_PIO3_5_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	359
bogdanm	0:9b334a45a8ff	360	/* IOCON_PIO0_6, address 0x4004 404C */
bogdanm	0:9b334a45a8ff	361	#define IOCON_PIO0_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	362	#define IOCON_PIO0_6_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	363	#define IOCON_PIO0_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	364	#define IOCON_PIO0_6_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	365	#define IOCON_PIO0_6_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	366	#define IOCON_PIO0_6_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/* IOCON_PIO0_7, address 0x4004 4050 */
bogdanm	0:9b334a45a8ff	369	#define IOCON_PIO0_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	370	#define IOCON_PIO0_7_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	371	#define IOCON_PIO0_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	372	#define IOCON_PIO0_7_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	373	#define IOCON_PIO0_7_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	374	#define IOCON_PIO0_7_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	375
bogdanm	0:9b334a45a8ff	376	/* IOCON_PIO2_9, address 0x4004 4054 */
bogdanm	0:9b334a45a8ff	377	#define IOCON_PIO2_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	378	#define IOCON_PIO2_9_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	379	#define IOCON_PIO2_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	380	#define IOCON_PIO2_9_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	381	#define IOCON_PIO2_9_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	382	#define IOCON_PIO2_9_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	383
bogdanm	0:9b334a45a8ff	384	/* IOCON_PIO2_10, address 0x4004 4058 */
bogdanm	0:9b334a45a8ff	385	#define IOCON_PIO2_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	386	#define IOCON_PIO2_10_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	387	#define IOCON_PIO2_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	388	#define IOCON_PIO2_10_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	389	#define IOCON_PIO2_10_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	390	#define IOCON_PIO2_10_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	/* IOCON_PIO2_2, address 0x4004 405C */
bogdanm	0:9b334a45a8ff	393	#define IOCON_PIO2_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	394	#define IOCON_PIO2_2_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	395	#define IOCON_PIO2_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	396	#define IOCON_PIO2_2_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	397	#define IOCON_PIO2_2_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	398	#define IOCON_PIO2_2_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	399
bogdanm	0:9b334a45a8ff	400	/* IOCON_PIO0_8, address 0x4004 4060 */
bogdanm	0:9b334a45a8ff	401	#define IOCON_PIO0_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	402	#define IOCON_PIO0_8_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	403	#define IOCON_PIO0_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	404	#define IOCON_PIO0_8_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	405	#define IOCON_PIO0_8_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	406	#define IOCON_PIO0_8_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	407
bogdanm	0:9b334a45a8ff	408	/* IOCON_PIO0_9, address 0x4004 4064 */
bogdanm	0:9b334a45a8ff	409	#define IOCON_PIO0_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	410	#define IOCON_PIO0_9_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	411	#define IOCON_PIO0_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	412	#define IOCON_PIO0_9_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	413	#define IOCON_PIO0_9_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	414	#define IOCON_PIO0_9_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416	/* IOCON_SWCLK_PIO0_10, address 0x4004 4068 */
bogdanm	0:9b334a45a8ff	417	#define IOCON_SWCLK_PIO0_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	418	#define IOCON_SWCLK_PIO0_10_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	419	#define IOCON_SWCLK_PIO0_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	420	#define IOCON_SWCLK_PIO0_10_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	421	#define IOCON_SWCLK_PIO0_10_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	422	#define IOCON_SWCLK_PIO0_10_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424	/* IOCON_PIO1_10, address 0x4004 406C */
bogdanm	0:9b334a45a8ff	425	#define IOCON_PIO1_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	426	#define IOCON_PIO1_10_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	427	#define IOCON_PIO1_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	428	#define IOCON_PIO1_10_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	429	#define IOCON_PIO1_10_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	430	#define IOCON_PIO1_10_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	431	#define IOCON_PIO1_10_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/* IOCON_PIO2_11, address 0x4004 4070 */
bogdanm	0:9b334a45a8ff	434	#define IOCON_PIO2_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	435	#define IOCON_PIO2_11_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	436	#define IOCON_PIO2_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	437	#define IOCON_PIO2_11_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	438	#define IOCON_PIO2_11_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	439	#define IOCON_PIO2_11_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	440
bogdanm	0:9b334a45a8ff	441	/* IOCON_R_PIO0_11, address 0x4004 4074 */
bogdanm	0:9b334a45a8ff	442	#define IOCON_R_PIO0_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	443	#define IOCON_R_PIO0_11_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	444	#define IOCON_R_PIO0_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	445	#define IOCON_R_PIO0_11_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	446	#define IOCON_R_PIO0_11_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	447	#define IOCON_R_PIO0_11_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	448	#define IOCON_R_PIO0_11_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	/* IOCON_R_PIO1_0, address 0x4004 4078 */
bogdanm	0:9b334a45a8ff	451	#define IOCON_R_PIO1_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	452	#define IOCON_R_PIO1_0_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	453	#define IOCON_R_PIO1_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	454	#define IOCON_R_PIO1_0_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	455	#define IOCON_R_PIO1_0_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	456	#define IOCON_R_PIO1_0_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	457	#define IOCON_R_PIO1_0_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	/* IOCON_R_PIO1_1, address 0x4004 407C */
bogdanm	0:9b334a45a8ff	460	#define IOCON_R_PIO1_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	461	#define IOCON_R_PIO1_1_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	462	#define IOCON_R_PIO1_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	463	#define IOCON_R_PIO1_1_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	464	#define IOCON_R_PIO1_1_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	465	#define IOCON_R_PIO1_1_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	466	#define IOCON_R_PIO1_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	467
bogdanm	0:9b334a45a8ff	468	/* IOCON_R_PIO1_2, address 0x4004 4080 */
bogdanm	0:9b334a45a8ff	469	#define IOCON_R_PIO1_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	470	#define IOCON_R_PIO1_2_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	471	#define IOCON_R_PIO1_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	472	#define IOCON_R_PIO1_2_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	473	#define IOCON_R_PIO1_2_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	474	#define IOCON_R_PIO1_2_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	475	#define IOCON_R_PIO1_2_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	476
bogdanm	0:9b334a45a8ff	477	/* IOCON_PIO3_0, address 0x4004 4084 */
bogdanm	0:9b334a45a8ff	478	#define IOCON_PIO3_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	479	#define IOCON_PIO3_0_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	480	#define IOCON_PIO3_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	481	#define IOCON_PIO3_0_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	482	#define IOCON_PIO3_0_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	483	#define IOCON_PIO3_0_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485	/* IOCON_PIO3_1, address 0x4004 4088 */
bogdanm	0:9b334a45a8ff	486	#define IOCON_PIO3_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	487	#define IOCON_PIO3_1_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	488	#define IOCON_PIO3_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	489	#define IOCON_PIO3_1_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	490	#define IOCON_PIO3_1_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	491	#define IOCON_PIO3_1_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	492
bogdanm	0:9b334a45a8ff	493	/* IOCON_PIO2_3, address 0x4004 408C */
bogdanm	0:9b334a45a8ff	494	#define IOCON_PIO2_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	495	#define IOCON_PIO2_3_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	496	#define IOCON_PIO2_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	497	#define IOCON_PIO2_3_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	498	#define IOCON_PIO2_3_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	499	#define IOCON_PIO2_3_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	500
bogdanm	0:9b334a45a8ff	501	/* IOCON_SWDIO_PIO1_3, address 0x4004 4090 */
bogdanm	0:9b334a45a8ff	502	#define IOCON_SWDIO_PIO1_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	503	#define IOCON_SWDIO_PIO1_3_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	504	#define IOCON_SWDIO_PIO1_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	505	#define IOCON_SWDIO_PIO1_3_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	506	#define IOCON_SWDIO_PIO1_3_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	507	#define IOCON_SWDIO_PIO1_3_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	508	#define IOCON_SWDIO_PIO1_3_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	509
bogdanm	0:9b334a45a8ff	510	/* IOCON_PIO1_4, address 0x4004 4094 */
bogdanm	0:9b334a45a8ff	511	#define IOCON_PIO1_4_FUNC_MASK 0x0007 // Selects pin function. This pin functions as WAKEUP pin if the 000 LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.
bogdanm	0:9b334a45a8ff	512	#define IOCON_PIO1_4_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	513	#define IOCON_PIO1_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	514	#define IOCON_PIO1_4_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	515	#define IOCON_PIO1_4_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	516	#define IOCON_PIO1_4_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	517	#define IOCON_PIO1_4_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	518
bogdanm	0:9b334a45a8ff	519	/* IOCON_PIO1_11, address 0x4004 4098 */
bogdanm	0:9b334a45a8ff	520	#define IOCON_PIO1_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	521	#define IOCON_PIO1_11_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	522	#define IOCON_PIO1_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	523	#define IOCON_PIO1_11_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	524	#define IOCON_PIO1_11_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	525	#define IOCON_PIO1_11_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	526	#define IOCON_PIO1_11_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	527
bogdanm	0:9b334a45a8ff	528	/* IOCON_PIO3_2, address 0x4004 409C */
bogdanm	0:9b334a45a8ff	529	#define IOCON_PIO3_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	530	#define IOCON_PIO3_2_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	531	#define IOCON_PIO3_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	532	#define IOCON_PIO3_2_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	533	#define IOCON_PIO3_2_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	534	#define IOCON_PIO3_2_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	/* IOCON_PIO1_5, address 0x4004 40A0 */
bogdanm	0:9b334a45a8ff	537	#define IOCON_PIO1_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	538	#define IOCON_PIO1_5_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	539	#define IOCON_PIO1_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	540	#define IOCON_PIO1_5_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	541	#define IOCON_PIO1_5_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	542	#define IOCON_PIO1_5_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	/* IOCON_PIO1_6, address 0x4004 40A4 */
bogdanm	0:9b334a45a8ff	545	#define IOCON_PIO1_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	546	#define IOCON_PIO1_6_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	547	#define IOCON_PIO1_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	548	#define IOCON_PIO1_6_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	549	#define IOCON_PIO1_6_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	550	#define IOCON_PIO1_6_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552	/* IOCON_PIO1_7, address 0x4004 40A8 */
bogdanm	0:9b334a45a8ff	553	#define IOCON_PIO1_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	554	#define IOCON_PIO1_7_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	555	#define IOCON_PIO1_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	556	#define IOCON_PIO1_7_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	557	#define IOCON_PIO1_7_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	558	#define IOCON_PIO1_7_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	/* IOCON_PIO3_3, address 0x4004 40AC */
bogdanm	0:9b334a45a8ff	561	#define IOCON_PIO3_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	562	#define IOCON_PIO3_3_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	563	#define IOCON_PIO3_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	564	#define IOCON_PIO3_3_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	565	#define IOCON_PIO3_3_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	566	#define IOCON_PIO3_3_OD (1 << 10) // Selects pseudo open-drain mode. See Section 7.1 for part specific details.
bogdanm	0:9b334a45a8ff	567
bogdanm	0:9b334a45a8ff	568	/* IOCON_SCK_LOC, address 0x4004 40B0 */
bogdanm	0:9b334a45a8ff	569	#define IOCON_SCK_LOC_SCKLOC_MASK 0x0003 // Selects pin location for SCK0 function.
bogdanm	0:9b334a45a8ff	570	#define IOCON_SCK_LOC_SCKLOC_SHIFT 0
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	/* IOCON_DSR_LOC, address 0x4004 40B4 */
bogdanm	0:9b334a45a8ff	573	#define IOCON_DSR_LOC_DSRLOC_MASK 0x0003 // elects pin location for DSR function.
bogdanm	0:9b334a45a8ff	574	#define IOCON_DSR_LOC_DSRLOC_SHIFT 0
bogdanm	0:9b334a45a8ff	575
bogdanm	0:9b334a45a8ff	576	/* IOCON_DCD_LOC, address 0x4004 40B8 */
bogdanm	0:9b334a45a8ff	577	#define IOCON_DCD_LOC_DCDLOC_MASK 0x0003 // Selects pin location for DCD function.
bogdanm	0:9b334a45a8ff	578	#define IOCON_DCD_LOC_DCDLOC_SHIFT 0
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580	/* IOCON_RI_LOC, address 0x4004 40BC */
bogdanm	0:9b334a45a8ff	581	#define IOCON_RI_LOC_RILOC_MASK 0x0003 // Selects pin location for RI function.
bogdanm	0:9b334a45a8ff	582	#define IOCON_RI_LOC_RILOC_SHIFT 0
bogdanm	0:9b334a45a8ff	583
bogdanm	0:9b334a45a8ff	584	/* IOCON_PIO2_6, address 0x4004 4000 */
bogdanm	0:9b334a45a8ff	585	#define IOCON_PIO2_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	586	#define IOCON_PIO2_6_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	587	#define IOCON_PIO2_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	588	#define IOCON_PIO2_6_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	589	#define IOCON_PIO2_6_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	590	#define IOCON_PIO2_6_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	/* IOCON_PIO2_0, address 0x4004 4008 */
bogdanm	0:9b334a45a8ff	593	#define IOCON_PIO2_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	594	#define IOCON_PIO2_0_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	595	#define IOCON_PIO2_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	596	#define IOCON_PIO2_0_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	597	#define IOCON_PIO2_0_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	598	#define IOCON_PIO2_0_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	599
bogdanm	0:9b334a45a8ff	600	/* IOCON_RESET_PIO0_0, address 0x4004 400C */
bogdanm	0:9b334a45a8ff	601	#define IOCON_RESET_PIO0_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	602	#define IOCON_RESET_PIO0_0_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	603	#define IOCON_RESET_PIO0_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	604	#define IOCON_RESET_PIO0_0_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	605	#define IOCON_RESET_PIO0_0_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	606	#define IOCON_RESET_PIO0_0_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	607
bogdanm	0:9b334a45a8ff	608	/* IOCON_PIO0_1, address 0x4004 4010 */
bogdanm	0:9b334a45a8ff	609	#define IOCON_PIO0_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	610	#define IOCON_PIO0_1_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	611	#define IOCON_PIO0_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	612	#define IOCON_PIO0_1_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	613	#define IOCON_PIO0_1_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	614	#define IOCON_PIO0_1_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	615
bogdanm	0:9b334a45a8ff	616	/* IOCON_PIO1_8, address 0x4004 4014 */
bogdanm	0:9b334a45a8ff	617	#define IOCON_PIO1_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	618	#define IOCON_PIO1_8_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	619	#define IOCON_PIO1_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	620	#define IOCON_PIO1_8_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	621	#define IOCON_PIO1_8_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	622	#define IOCON_PIO1_8_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	623
bogdanm	0:9b334a45a8ff	624	/* IOCON_PIO0_2, address 0x4004 401C */
bogdanm	0:9b334a45a8ff	625	#define IOCON_PIO0_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	626	#define IOCON_PIO0_2_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	627	#define IOCON_PIO0_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	628	#define IOCON_PIO0_2_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	629	#define IOCON_PIO0_2_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	630	#define IOCON_PIO0_2_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	631
bogdanm	0:9b334a45a8ff	632	/* IOCON_PIO2_7, address 0x4004 4020 */
bogdanm	0:9b334a45a8ff	633	#define IOCON_PIO2_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	634	#define IOCON_PIO2_7_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	635	#define IOCON_PIO2_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	636	#define IOCON_PIO2_7_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	637	#define IOCON_PIO2_7_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	638	#define IOCON_PIO2_7_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	/* IOCON_PIO2_8, address 0x4004 4024 */
bogdanm	0:9b334a45a8ff	641	#define IOCON_PIO2_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	642	#define IOCON_PIO2_8_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	643	#define IOCON_PIO2_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	644	#define IOCON_PIO2_8_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	645	#define IOCON_PIO2_8_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	646	#define IOCON_PIO2_8_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	/* IOCON_PIO2_1, address 0x4004 4028 */
bogdanm	0:9b334a45a8ff	649	#define IOCON_PIO2_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	650	#define IOCON_PIO2_1_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	651	#define IOCON_PIO2_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	652	#define IOCON_PIO2_1_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	653	#define IOCON_PIO2_1_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	654	#define IOCON_PIO2_1_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	655
bogdanm	0:9b334a45a8ff	656	/* IOCON_PIO0_3, address 0x4004 402C */
bogdanm	0:9b334a45a8ff	657	#define IOCON_PIO0_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	658	#define IOCON_PIO0_3_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	659	#define IOCON_PIO0_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	660	#define IOCON_PIO0_3_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	661	#define IOCON_PIO0_3_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	662	#define IOCON_PIO0_3_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	/* IOCON_PIO0_4, address 0x4004 4030 */
bogdanm	0:9b334a45a8ff	665	#define IOCON_PIO0_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	666	#define IOCON_PIO0_4_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	667	#define IOCON_PIO0_4_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, 00 default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
bogdanm	0:9b334a45a8ff	668	#define IOCON_PIO0_4_I2CMODE_SHIFT 8
bogdanm	0:9b334a45a8ff	669
bogdanm	0:9b334a45a8ff	670	/* IOCON_PIO0_5, address 0x4004 4034 */
bogdanm	0:9b334a45a8ff	671	#define IOCON_PIO0_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	672	#define IOCON_PIO0_5_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	673	#define IOCON_PIO0_5_I2CMODE_MASK 0x0300 // Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).
bogdanm	0:9b334a45a8ff	674	#define IOCON_PIO0_5_I2CMODE_SHIFT 8
bogdanm	0:9b334a45a8ff	675
bogdanm	0:9b334a45a8ff	676	/* IOCON_PIO1_9, address 0x4004 4038 */
bogdanm	0:9b334a45a8ff	677	#define IOCON_PIO1_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	678	#define IOCON_PIO1_9_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	679	#define IOCON_PIO1_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	680	#define IOCON_PIO1_9_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	681	#define IOCON_PIO1_9_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	682	#define IOCON_PIO1_9_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	683
bogdanm	0:9b334a45a8ff	684	/* IOCON_PIO3_4, address 0x4004 403C */
bogdanm	0:9b334a45a8ff	685	#define IOCON_PIO3_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	686	#define IOCON_PIO3_4_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	687	#define IOCON_PIO3_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	688	#define IOCON_PIO3_4_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	689	#define IOCON_PIO3_4_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	690	#define IOCON_PIO3_4_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692	/* IOCON_PIO2_4, address 0x4004 4040 */
bogdanm	0:9b334a45a8ff	693	#define IOCON_PIO2_4_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	694	#define IOCON_PIO2_4_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	695	#define IOCON_PIO2_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	696	#define IOCON_PIO2_4_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	697	#define IOCON_PIO2_4_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	698	#define IOCON_PIO2_4_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	/* IOCON_PIO2_5, address 0x4004 4044 */
bogdanm	0:9b334a45a8ff	701	#define IOCON_PIO2_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	702	#define IOCON_PIO2_5_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	703	#define IOCON_PIO2_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	704	#define IOCON_PIO2_5_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	705	#define IOCON_PIO2_5_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	706	#define IOCON_PIO2_5_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	/* IOCON_PIO3_5, address 0x4004 4048 */
bogdanm	0:9b334a45a8ff	709	#define IOCON_PIO3_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	710	#define IOCON_PIO3_5_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	711	#define IOCON_PIO3_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	712	#define IOCON_PIO3_5_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	713	#define IOCON_PIO3_5_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	714	#define IOCON_PIO3_5_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	715
bogdanm	0:9b334a45a8ff	716	/* IOCON_PIO0_6, address 0x4004 404C */
bogdanm	0:9b334a45a8ff	717	#define IOCON_PIO0_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	718	#define IOCON_PIO0_6_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	719	#define IOCON_PIO0_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	720	#define IOCON_PIO0_6_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	721	#define IOCON_PIO0_6_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	722	#define IOCON_PIO0_6_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	/* IOCON_PIO0_7, address 0x4004 4050 */
bogdanm	0:9b334a45a8ff	725	#define IOCON_PIO0_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	726	#define IOCON_PIO0_7_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	727	#define IOCON_PIO0_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	728	#define IOCON_PIO0_7_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	729	#define IOCON_PIO0_7_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	730	#define IOCON_PIO0_7_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	731
bogdanm	0:9b334a45a8ff	732	/* IOCON_PIO2_9, address 0x4004 4054 */
bogdanm	0:9b334a45a8ff	733	#define IOCON_PIO2_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	734	#define IOCON_PIO2_9_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	735	#define IOCON_PIO2_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	736	#define IOCON_PIO2_9_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	737	#define IOCON_PIO2_9_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	738	#define IOCON_PIO2_9_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	/* IOCON_PIO2_10, address 0x4004 4058 */
bogdanm	0:9b334a45a8ff	741	#define IOCON_PIO2_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	742	#define IOCON_PIO2_10_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	743	#define IOCON_PIO2_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	744	#define IOCON_PIO2_10_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	745	#define IOCON_PIO2_10_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	746	#define IOCON_PIO2_10_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	747
bogdanm	0:9b334a45a8ff	748	/* IOCON_PIO2_2, address 0x4004 405C */
bogdanm	0:9b334a45a8ff	749	#define IOCON_PIO2_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	750	#define IOCON_PIO2_2_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	751	#define IOCON_PIO2_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	752	#define IOCON_PIO2_2_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	753	#define IOCON_PIO2_2_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	754	#define IOCON_PIO2_2_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	755
bogdanm	0:9b334a45a8ff	756	/* IOCON_PIO0_8, address 0x4004 4060 */
bogdanm	0:9b334a45a8ff	757	#define IOCON_PIO0_8_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	758	#define IOCON_PIO0_8_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	759	#define IOCON_PIO0_8_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	760	#define IOCON_PIO0_8_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	761	#define IOCON_PIO0_8_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	762	#define IOCON_PIO0_8_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	763
bogdanm	0:9b334a45a8ff	764	/* IOCON_PIO0_9, address 0x4004 4064 */
bogdanm	0:9b334a45a8ff	765	#define IOCON_PIO0_9_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	766	#define IOCON_PIO0_9_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	767	#define IOCON_PIO0_9_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	768	#define IOCON_PIO0_9_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	769	#define IOCON_PIO0_9_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	770	#define IOCON_PIO0_9_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	771
bogdanm	0:9b334a45a8ff	772	/* IOCON_SWCLK_PIO0_10, address 0x4004 4068 */
bogdanm	0:9b334a45a8ff	773	#define IOCON_SWCLK_PIO0_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	774	#define IOCON_SWCLK_PIO0_10_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	775	#define IOCON_SWCLK_PIO0_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	776	#define IOCON_SWCLK_PIO0_10_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	777	#define IOCON_SWCLK_PIO0_10_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	778	#define IOCON_SWCLK_PIO0_10_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	779
bogdanm	0:9b334a45a8ff	780	/* IOCON_PIO1_10, address 0x4004 406C */
bogdanm	0:9b334a45a8ff	781	#define IOCON_PIO1_10_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	782	#define IOCON_PIO1_10_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	783	#define IOCON_PIO1_10_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	784	#define IOCON_PIO1_10_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	785	#define IOCON_PIO1_10_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	786	#define IOCON_PIO1_10_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	787	#define IOCON_PIO1_10_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	788
bogdanm	0:9b334a45a8ff	789	/* IOCON_PIO2_11, address 0x4004 4070 */
bogdanm	0:9b334a45a8ff	790	#define IOCON_PIO2_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	791	#define IOCON_PIO2_11_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	792	#define IOCON_PIO2_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	793	#define IOCON_PIO2_11_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	794	#define IOCON_PIO2_11_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	795	#define IOCON_PIO2_11_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	/* IOCON_R_PIO0_11, address 0x4004 4074 */
bogdanm	0:9b334a45a8ff	798	#define IOCON_R_PIO0_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	799	#define IOCON_R_PIO0_11_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	800	#define IOCON_R_PIO0_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	801	#define IOCON_R_PIO0_11_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	802	#define IOCON_R_PIO0_11_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	803	#define IOCON_R_PIO0_11_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	804	#define IOCON_R_PIO0_11_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	805
bogdanm	0:9b334a45a8ff	806	/* IOCON_R_PIO1_0, address 0x4004 4078 */
bogdanm	0:9b334a45a8ff	807	#define IOCON_R_PIO1_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	808	#define IOCON_R_PIO1_0_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	809	#define IOCON_R_PIO1_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	810	#define IOCON_R_PIO1_0_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	811	#define IOCON_R_PIO1_0_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	812	#define IOCON_R_PIO1_0_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	813	#define IOCON_R_PIO1_0_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	814
bogdanm	0:9b334a45a8ff	815	/* IOCON_R_PIO1_1, address 0x4004 407C */
bogdanm	0:9b334a45a8ff	816	#define IOCON_R_PIO1_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	817	#define IOCON_R_PIO1_1_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	818	#define IOCON_R_PIO1_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	819	#define IOCON_R_PIO1_1_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	820	#define IOCON_R_PIO1_1_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	821	#define IOCON_R_PIO1_1_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	822	#define IOCON_R_PIO1_1_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	/* IOCON_R_PIO1_2, address 0x4004 4080 */
bogdanm	0:9b334a45a8ff	825	#define IOCON_R_PIO1_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	826	#define IOCON_R_PIO1_2_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	827	#define IOCON_R_PIO1_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	828	#define IOCON_R_PIO1_2_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	829	#define IOCON_R_PIO1_2_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	830	#define IOCON_R_PIO1_2_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	831	#define IOCON_R_PIO1_2_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	832
bogdanm	0:9b334a45a8ff	833	/* IOCON_PIO3_0, address 0x4004 4084 */
bogdanm	0:9b334a45a8ff	834	#define IOCON_PIO3_0_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	835	#define IOCON_PIO3_0_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	836	#define IOCON_PIO3_0_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	837	#define IOCON_PIO3_0_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	838	#define IOCON_PIO3_0_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	839	#define IOCON_PIO3_0_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	840
bogdanm	0:9b334a45a8ff	841	/* IOCON_PIO3_1, address 0x4004 4088 */
bogdanm	0:9b334a45a8ff	842	#define IOCON_PIO3_1_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	843	#define IOCON_PIO3_1_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	844	#define IOCON_PIO3_1_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	845	#define IOCON_PIO3_1_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	846	#define IOCON_PIO3_1_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	847	#define IOCON_PIO3_1_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	848
bogdanm	0:9b334a45a8ff	849	/* IOCON_PIO2_3, address 0x4004 408C */
bogdanm	0:9b334a45a8ff	850	#define IOCON_PIO2_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	851	#define IOCON_PIO2_3_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	852	#define IOCON_PIO2_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	853	#define IOCON_PIO2_3_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	854	#define IOCON_PIO2_3_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	855	#define IOCON_PIO2_3_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	/* IOCON_SWDIO_PIO1_3, address 0x4004 4090 */
bogdanm	0:9b334a45a8ff	858	#define IOCON_SWDIO_PIO1_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	859	#define IOCON_SWDIO_PIO1_3_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	860	#define IOCON_SWDIO_PIO1_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	861	#define IOCON_SWDIO_PIO1_3_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	862	#define IOCON_SWDIO_PIO1_3_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	863	#define IOCON_SWDIO_PIO1_3_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	864	#define IOCON_SWDIO_PIO1_3_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	865
bogdanm	0:9b334a45a8ff	866	/* IOCON_PIO1_4, address 0x4004 4094 */
bogdanm	0:9b334a45a8ff	867	#define IOCON_PIO1_4_FUNC_MASK 0x0007 // Selects pin function. This pin functions as WAKEUP pin if the 000 LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.
bogdanm	0:9b334a45a8ff	868	#define IOCON_PIO1_4_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	869	#define IOCON_PIO1_4_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	870	#define IOCON_PIO1_4_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	871	#define IOCON_PIO1_4_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	872	#define IOCON_PIO1_4_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	873	#define IOCON_PIO1_4_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	874
bogdanm	0:9b334a45a8ff	875	/* IOCON_PIO1_11, address 0x4004 4098 */
bogdanm	0:9b334a45a8ff	876	#define IOCON_PIO1_11_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	877	#define IOCON_PIO1_11_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	878	#define IOCON_PIO1_11_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	879	#define IOCON_PIO1_11_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	880	#define IOCON_PIO1_11_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	881	#define IOCON_PIO1_11_ADMODE (1 << 7) // Selects Analog/Digital mode
bogdanm	0:9b334a45a8ff	882	#define IOCON_PIO1_11_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	883
bogdanm	0:9b334a45a8ff	884	/* IOCON_PIO3_2, address 0x4004 409C */
bogdanm	0:9b334a45a8ff	885	#define IOCON_PIO3_2_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	886	#define IOCON_PIO3_2_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	887	#define IOCON_PIO3_2_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	888	#define IOCON_PIO3_2_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	889	#define IOCON_PIO3_2_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	890	#define IOCON_PIO3_2_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892	/* IOCON_PIO1_5, address 0x4004 40A0 */
bogdanm	0:9b334a45a8ff	893	#define IOCON_PIO1_5_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	894	#define IOCON_PIO1_5_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	895	#define IOCON_PIO1_5_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	896	#define IOCON_PIO1_5_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	897	#define IOCON_PIO1_5_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	898	#define IOCON_PIO1_5_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	899
bogdanm	0:9b334a45a8ff	900	/* IOCON_PIO1_6, address 0x4004 40A4 */
bogdanm	0:9b334a45a8ff	901	#define IOCON_PIO1_6_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	902	#define IOCON_PIO1_6_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	903	#define IOCON_PIO1_6_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	904	#define IOCON_PIO1_6_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	905	#define IOCON_PIO1_6_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	906	#define IOCON_PIO1_6_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	907
bogdanm	0:9b334a45a8ff	908	/* IOCON_PIO1_7, address 0x4004 40A8 */
bogdanm	0:9b334a45a8ff	909	#define IOCON_PIO1_7_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	910	#define IOCON_PIO1_7_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	911	#define IOCON_PIO1_7_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	912	#define IOCON_PIO1_7_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	913	#define IOCON_PIO1_7_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	914	#define IOCON_PIO1_7_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	915
bogdanm	0:9b334a45a8ff	916	/* IOCON_PIO3_3, address 0x4004 40AC */
bogdanm	0:9b334a45a8ff	917	#define IOCON_PIO3_3_FUNC_MASK 0x0007 // Selects pin function. All other values are reserved.
bogdanm	0:9b334a45a8ff	918	#define IOCON_PIO3_3_FUNC_SHIFT 0
bogdanm	0:9b334a45a8ff	919	#define IOCON_PIO3_3_MODE_MASK 0x0018 // Selects function mode (on-chip pull-up/pull-down resistor control).
bogdanm	0:9b334a45a8ff	920	#define IOCON_PIO3_3_MODE_SHIFT 3
bogdanm	0:9b334a45a8ff	921	#define IOCON_PIO3_3_HYS (1 << 5) // Hysteresis.
bogdanm	0:9b334a45a8ff	922	#define IOCON_PIO3_3_OD (1 << 10) // Selects pseudo open-drain mode.
bogdanm	0:9b334a45a8ff	923
bogdanm	0:9b334a45a8ff	924	/* IOCON_SCK0_LOC, address 0x4004 40B0 */
bogdanm	0:9b334a45a8ff	925	#define IOCON_SCK0_LOC_SCKLOC_MASK 0x0003 // Selects pin location for SCK0 function.
bogdanm	0:9b334a45a8ff	926	#define IOCON_SCK0_LOC_SCKLOC_SHIFT 0
bogdanm	0:9b334a45a8ff	927
bogdanm	0:9b334a45a8ff	928	/* IOCON_DSR_LOC, address 0x4004 40B4 */
bogdanm	0:9b334a45a8ff	929	#define IOCON_DSR_LOC_DSRLOC_MASK 0x0003 // elects pin location for DSR function.
bogdanm	0:9b334a45a8ff	930	#define IOCON_DSR_LOC_DSRLOC_SHIFT 0
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	/* IOCON_DCD_LOC, address 0x4004 40B8 */
bogdanm	0:9b334a45a8ff	933	#define IOCON_DCD_LOC_DCDLOC_MASK 0x0003 // Selects pin location for DCD function.
bogdanm	0:9b334a45a8ff	934	#define IOCON_DCD_LOC_DCDLOC_SHIFT 0
bogdanm	0:9b334a45a8ff	935
bogdanm	0:9b334a45a8ff	936	/* IOCON_RI_LOC, address 0x4004 40BC */
bogdanm	0:9b334a45a8ff	937	#define IOCON_RI_LOC_RILOC_MASK 0x0003 // Selects pin location for RI function.
bogdanm	0:9b334a45a8ff	938	#define IOCON_RI_LOC_RILOC_SHIFT 0
bogdanm	0:9b334a45a8ff	939
bogdanm	0:9b334a45a8ff	940	/* IOCON_SSEL1_LOC, address 0x4004 4018 */
bogdanm	0:9b334a45a8ff	941	#define IOCON_SSEL1_LOC_SSEL1LOC_MASK 0x0003 // Selects pin location for SSEL1 function.
bogdanm	0:9b334a45a8ff	942	#define IOCON_SSEL1_LOC_SSEL1LOC_SHIFT 0
bogdanm	0:9b334a45a8ff	943
bogdanm	0:9b334a45a8ff	944	/* IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0 */
bogdanm	0:9b334a45a8ff	945	#define IOCON_CT16B0_CAP0_LOC_CT16B0_CAP0LOC_MASK 0x0003 // Selects pin location for CT16B0_CAP0 function.
bogdanm	0:9b334a45a8ff	946	#define IOCON_CT16B0_CAP0_LOC_CT16B0_CAP0LOC_SHIFT 0
bogdanm	0:9b334a45a8ff	947
bogdanm	0:9b334a45a8ff	948	/* IOCON_SCK1_LOC, address 0x4004 40C4 */
bogdanm	0:9b334a45a8ff	949	#define IOCON_SCK1_LOC_SCK1LOC_MASK 0x0003 // Selects pin location for SCK1 function.
bogdanm	0:9b334a45a8ff	950	#define IOCON_SCK1_LOC_SCK1LOC_SHIFT 0
bogdanm	0:9b334a45a8ff	951
bogdanm	0:9b334a45a8ff	952	/* IOCON_MISO1_LOC, address 0x4004 40C8 */
bogdanm	0:9b334a45a8ff	953	#define IOCON_MISO1_LOC_MISO1LOC_MASK 0x0003 // Selects pin location for the MISO1 function.
bogdanm	0:9b334a45a8ff	954	#define IOCON_MISO1_LOC_MISO1LOC_SHIFT 0
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	/* IOCON_MOSI1_LOC, address 0x4004 40CC */
bogdanm	0:9b334a45a8ff	957	#define IOCON_MOSI1_LOC_MOSI1LOC_MASK 0x0003 // Selects pin location for the MOSI1 function.
bogdanm	0:9b334a45a8ff	958	#define IOCON_MOSI1_LOC_MOSI1LOC_SHIFT 0
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960	/* IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0 */
bogdanm	0:9b334a45a8ff	961	#define IOCON_CT32B0_CAP0_LOC_CT32B0_CAP0LOC_MASK 0x0003 // Selects pin location for the CT32B0_CAP0 function.
bogdanm	0:9b334a45a8ff	962	#define IOCON_CT32B0_CAP0_LOC_CT32B0_CAP0LOC_SHIFT 0
bogdanm	0:9b334a45a8ff	963
bogdanm	0:9b334a45a8ff	964	/* IOCON_RXD_LOC, address 0x4004 40D4 */
bogdanm	0:9b334a45a8ff	965	#define IOCON_RXD_LOC_RXDLOC_MASK 0x0003 // Selects pin location for the RXD function.
bogdanm	0:9b334a45a8ff	966	#define IOCON_RXD_LOC_RXDLOC_SHIFT 0
bogdanm	0:9b334a45a8ff	967
bogdanm	0:9b334a45a8ff	968	/* GPIO0DIR, address 0x5000 8000 to GPIO3DIR, address 0x5003 8000 */
bogdanm	0:9b334a45a8ff	969	#define GPIO0DIR_IO_MASK 0x0FFF // Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.
bogdanm	0:9b334a45a8ff	970	#define GPIO0DIR_IO_SHIFT 0
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/* GPIO0IS, address 0x5000 8004 to GPIO3IS, address 0x5003 8004 */
bogdanm	0:9b334a45a8ff	973	#define GPIO0IS_ISENSE_MASK 0x0FFF // Selects interrupt on pin x as level or edge sensitive (x = 0 to 0x00 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.
bogdanm	0:9b334a45a8ff	974	#define GPIO0IS_ISENSE_SHIFT 0
bogdanm	0:9b334a45a8ff	975
bogdanm	0:9b334a45a8ff	976	/* GPIO0IBE, address 0x5000 8008 to GPIO3IBE, address 0x5003 8008 */
bogdanm	0:9b334a45a8ff	977	#define GPIO0IBE_IBE_MASK 0x0FFF // Selects interrupt on pin x to be triggered on both edges (x = 0 0x00 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.
bogdanm	0:9b334a45a8ff	978	#define GPIO0IBE_IBE_SHIFT 0
bogdanm	0:9b334a45a8ff	979
bogdanm	0:9b334a45a8ff	980	/* GPIO0IEV, address 0x5000 800C to GPIO3IEV, address 0x5003 800C */
bogdanm	0:9b334a45a8ff	981	#define GPIO0IEV_IEV_MASK 0x0FFF // Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 175), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 175), rising edges or HIGH level on pin PIOn_x trigger an interrupt.
bogdanm	0:9b334a45a8ff	982	#define GPIO0IEV_IEV_SHIFT 0
bogdanm	0:9b334a45a8ff	983
bogdanm	0:9b334a45a8ff	984	/* GPIO0IE, address 0x5000 8010 to GPIO3IE, address 0x5003 8010 */
bogdanm	0:9b334a45a8ff	985	#define GPIO0IE_MASK_MASK 0x0FFF // Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.
bogdanm	0:9b334a45a8ff	986	#define GPIO0IE_MASK_SHIFT 0
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988	/* GPIO0RIS, address 0x5000 8014 to GPIO3RIS, address 0x5003 8014 */
bogdanm	0:9b334a45a8ff	989	#define GPIO0RIS_RAWST_MASK 0x0FFF // Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.
bogdanm	0:9b334a45a8ff	990	#define GPIO0RIS_RAWST_SHIFT 0
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992	/* GPIO0MIS, address 0x5000 8018 to GPIO3MIS, address 0x5003 8018 */
bogdanm	0:9b334a45a8ff	993	#define GPIO0MIS_MASK_MASK 0x0FFF // Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.
bogdanm	0:9b334a45a8ff	994	#define GPIO0MIS_MASK_SHIFT 0
bogdanm	0:9b334a45a8ff	995
bogdanm	0:9b334a45a8ff	996	/* GPIO0IC, address 0x5000 801C to GPIO3IC, address 0x5003 801C */
bogdanm	0:9b334a45a8ff	997	#define GPIO0IC_CLR_MASK 0x0FFF // Selects interrupt on pin x to be cleared (x = 0 to 11). Clears 0x00 the interrupt edge detection logic. This register is write-only. Remark: The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.
bogdanm	0:9b334a45a8ff	998	#define GPIO0IC_CLR_SHIFT 0
bogdanm	0:9b334a45a8ff	999
bogdanm	0:9b334a45a8ff	1000	/* U0IIR - address 0x4004 8008, Read Only */
bogdanm	0:9b334a45a8ff	1001	#define U0IIR_INTSTATUS (1 << 0) // Interrupt status. Note that U0IIR[0] is active low. The pending interrupt can be determined by evaluating U0IIR[3:1].
bogdanm	0:9b334a45a8ff	1002	#define U0IIR_INTID_MASK 0x000E // Interrupt identification. U0IER[3:1] identifies an interrupt 0 corresponding to the UART Rx FIFO. All other combinations of U0IER[3:1] not listed below are reserved (100,101,111).
bogdanm	0:9b334a45a8ff	1003	#define U0IIR_INTID_SHIFT 1
bogdanm	0:9b334a45a8ff	1004	#define U0IIR_FIFOENABLE_MASK 0x00C0 // These bits are equivalent to U0FCR[0].
bogdanm	0:9b334a45a8ff	1005	#define U0IIR_FIFOENABLE_SHIFT 6
bogdanm	0:9b334a45a8ff	1006	#define U0IIR_ABEOINT (1 << 8) // End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
bogdanm	0:9b334a45a8ff	1007	#define U0IIR_ABTOINT (1 << 9) // Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bogdanm	0:9b334a45a8ff	1008
bogdanm	0:9b334a45a8ff	1009	/* U0FCR - address 0x4000 8008, Write Only */
bogdanm	0:9b334a45a8ff	1010	#define U0FCR_FIFOEN (1 << 0) // FIFO Enable
bogdanm	0:9b334a45a8ff	1011	#define U0FCR_RXFIFORES (1 << 1) // RX FIFO Reset
bogdanm	0:9b334a45a8ff	1012	#define U0FCR_TXFIFORES (1 << 2) // TX FIFO Reset
bogdanm	0:9b334a45a8ff	1013	#define U0FCR_RXTL_MASK 0x00C0 // RX Trigger Level. These two bits determine how many 0 receiver UART FIFO characters must be written before an interrupt is activated.
bogdanm	0:9b334a45a8ff	1014	#define U0FCR_RXTL_SHIFT 6
bogdanm	0:9b334a45a8ff	1015
bogdanm	0:9b334a45a8ff	1016	/* U0LCR - address 0x4000 800C */
bogdanm	0:9b334a45a8ff	1017	#define U0LCR_WLS_MASK 0x0003 // Word Length Select
bogdanm	0:9b334a45a8ff	1018	#define U0LCR_WLS_SHIFT 0
bogdanm	0:9b334a45a8ff	1019	#define U0LCR_SBS (1 << 2) // Stop Bit Select
bogdanm	0:9b334a45a8ff	1020	#define U0LCR_PE (1 << 3) // Parity Enable
bogdanm	0:9b334a45a8ff	1021	#define U0LCR_PS_MASK 0x0030 // Parity Select 0x0 Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x1 Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x2 Forced 1 stick parity. 0x3 Forced 0 stick parity.
bogdanm	0:9b334a45a8ff	1022	#define U0LCR_PS_SHIFT 4
bogdanm	0:9b334a45a8ff	1023	#define U0LCR_BC (1 << 6) // Break Control
bogdanm	0:9b334a45a8ff	1024	#define U0LCR_DLAB (1 << 7) // Divisor Latch Access Bit
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/* U0MCR - address 0x4000 8010 */
bogdanm	0:9b334a45a8ff	1027	#define U0MCR_DTRC (1 << 0) // DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.
bogdanm	0:9b334a45a8ff	1028	#define U0MCR_RTSC (1 << 1) // RTS Control. Source for modem output pin RTS. This bit reads as 0 0 when modem loopback mode is active.
bogdanm	0:9b334a45a8ff	1029	#define U0MCR_LMS (1 << 4) // Loopback Mode Select. The modem loopback mode provides a 0 mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the U0MSR will be driven by the lower four bits of the U0MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of U0MCR.
bogdanm	0:9b334a45a8ff	1030	#define U0MCR_RTSEN (1 << 6) // RTS flow control
bogdanm	0:9b334a45a8ff	1031	#define U0MCR_CTSEN (1 << 7) // CTS flow control
bogdanm	0:9b334a45a8ff	1032
bogdanm	0:9b334a45a8ff	1033	/* U0LSR - address 0x4000 8014, Read Only */
bogdanm	0:9b334a45a8ff	1034	#define U0LSR_RDR (1 << 0) // Receiver Data Ready. U0LSR[0] is set when the U0RBR holds 0 an unread character and is cleared when the UART RBR FIFO is empty.
bogdanm	0:9b334a45a8ff	1035	#define U0LSR_OE (1 << 1) // Overrun Error. The overrun error condition is set as soon as it 0 occurs. A U0LSR read clears U0LSR[1]. U0LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost.
bogdanm	0:9b334a45a8ff	1036	#define U0LSR_PE (1 << 2) // Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A U0LSR read clears U0LSR[2]. Time of parity error detection is dependent on U0FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO.
bogdanm	0:9b334a45a8ff	1037	#define U0LSR_FE (1 << 3) // Framing Error. When the stop bit of a received character is a 0 logic 0, a framing error occurs. A U0LSR read clears U0LSR[3]. The time of the framing error detection is dependent on U0FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO.
bogdanm	0:9b334a45a8ff	1038	#define U0LSR_BI (1 << 4) // Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A U0LSR read clears this status bit. The time of break detection is dependent on U0FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO.
bogdanm	0:9b334a45a8ff	1039	#define U0LSR_THRE (1 << 5) // Transmitter Holding Register Empty. THRE is set immediately 1 upon detection of an empty UART THR and is cleared on a U0THR write.
bogdanm	0:9b334a45a8ff	1040	#define U0LSR_TEMT (1 << 6) // Transmitter Empty. TEMT is set when both U0THR and 1 U0TSR are empty; TEMT is cleared when either the U0TSR or the U0THR contain valid data. This bit is updated as soon as 50 % of the first stop bit has been transmitted or a byte has been written into the THR.
bogdanm	0:9b334a45a8ff	1041	#define U0LSR_RXFE (1 << 7) // Error in RX FIFO. U0LSR[7] is set when a character with a RX 0 error such as framing error, parity error or break interrupt, is loaded into the U0RBR. This bit is cleared when the U0LSR register is read and there are no subsequent errors in the UART FIFO.
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	/* U0MSR - address 0x4000 8018 */
bogdanm	0:9b334a45a8ff	1044	#define U0MSR_DCTS (1 << 0) // Delta CTS. Set upon state change of input CTS. Cleared on a U0MSR read. 0 No change detected on modem input CTS. 1 State change detected on modem input CTS.
bogdanm	0:9b334a45a8ff	1045	#define U0MSR_DDSR (1 << 1) // Delta DSR. Set upon state change of input DSR. Cleared on a U0MSR read. 0 No change detected on modem input DSR. 1 State change detected on modem input DSR.
bogdanm	0:9b334a45a8ff	1046	#define U0MSR_TERI (1 << 2) // Trailing Edge RI. Set upon low to high transition of input RI. Cleared 0 on a U0MSR read. 0 No change detected on modem input, RI. 1 Low-to-high transition detected on RI.
bogdanm	0:9b334a45a8ff	1047	#define U0MSR_DDCD (1 << 3) // Delta DCD. Set upon state change of input DCD. Cleared on a U0MSR read. 0 No change detected on modem input DCD. 1 State change detected on modem input DCD.
bogdanm	0:9b334a45a8ff	1048	#define U0MSR_CTS (1 << 4) // Clear To Send State. Complement of input signal CTS. This bit is connected to U0MCR[1] in modem loopback mode.
bogdanm	0:9b334a45a8ff	1049	#define U0MSR_DSR (1 << 5) // Data Set Ready State. Complement of input signal DSR. This bit is connected to U0MCR[0] in modem loopback mode.
bogdanm	0:9b334a45a8ff	1050	#define U0MSR_RI (1 << 6) // Ring Indicator State. Complement of input RI. This bit is connected to U0MCR[2] in modem loopback mode.
bogdanm	0:9b334a45a8ff	1051	#define U0MSR_DCD (1 << 7) // Data Carrier Detect State. Complement of input DCD. This bit is connected to U0MCR[3] in modem loopback mode.
bogdanm	0:9b334a45a8ff	1052
bogdanm	0:9b334a45a8ff	1053	/* U0SCR - address 0x4000 801C */
bogdanm	0:9b334a45a8ff	1054	#define U0SCR_PAD_MASK 0x00FF // A readable, writable byte.
bogdanm	0:9b334a45a8ff	1055	#define U0SCR_PAD_SHIFT 0
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057	/* U0ACR - address 0x4000 8020 */
bogdanm	0:9b334a45a8ff	1058	#define U0ACR_START (1 << 0) // Start bit. This bit is automatically cleared after auto-baud completion.
bogdanm	0:9b334a45a8ff	1059	#define U0ACR_MODE (1 << 1) // Auto-baud mode select
bogdanm	0:9b334a45a8ff	1060	#define U0ACR_AUTORESTART (1 << 2) // Restart enable
bogdanm	0:9b334a45a8ff	1061	#define U0ACR_ABEOINTCLR (1 << 8) // End of auto-baud interrupt clear (write only accessible)
bogdanm	0:9b334a45a8ff	1062	#define U0ACR_ABTOINTCLR (1 << 9) // Auto-baud time-out interrupt clear (write only accessible)
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	/* U0TER - address 0x4000 8030 */
bogdanm	0:9b334a45a8ff	1065	#define U0TER_TXEN (1 << 7) // When this bit is 1, as it is after a Reset, data written to the THR 1 is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. Reserved
bogdanm	0:9b334a45a8ff	1066
bogdanm	0:9b334a45a8ff	1067	/* U0RS485CTRL - address 0x4000 804C */
bogdanm	0:9b334a45a8ff	1068	#define U0RS485CTRL_NMMEN (1 << 0) // NMM enable.
bogdanm	0:9b334a45a8ff	1069	#define U0RS485CTRL_RXDIS (1 << 1) // Receiver enable.
bogdanm	0:9b334a45a8ff	1070	#define U0RS485CTRL_AADEN (1 << 2) // AAD enable.
bogdanm	0:9b334a45a8ff	1071	#define U0RS485CTRL_SEL (1 << 3) // Select direction control pin
bogdanm	0:9b334a45a8ff	1072	#define U0RS485CTRL_DCTRL (1 << 4) // Auto direction control enable.
bogdanm	0:9b334a45a8ff	1073	#define U0RS485CTRL_OINV (1 << 5) // Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
bogdanm	0:9b334a45a8ff	1074
bogdanm	0:9b334a45a8ff	1075	/* U0RS485ADRMATCH - address 0x4000 8050 */
bogdanm	0:9b334a45a8ff	1076	#define U0RS485ADRMATCH_ADRMATCH_MASK 0x00FF // Contains the address match value. 0
bogdanm	0:9b334a45a8ff	1077	#define U0RS485ADRMATCH_ADRMATCH_SHIFT 0
bogdanm	0:9b334a45a8ff	1078
bogdanm	0:9b334a45a8ff	1079	/* U0RS485DLY - address 0x4000 8054 */
bogdanm	0:9b334a45a8ff	1080	#define U0RS485DLY_DLY_MASK 0x00FF // Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.
bogdanm	0:9b334a45a8ff	1081	#define U0RS485DLY_DLY_SHIFT 0
bogdanm	0:9b334a45a8ff	1082
bogdanm	0:9b334a45a8ff	1083	/* SSP0CR0 - address 0x4004 0000, SSP1CR0 - address 0x4005 8000 */
bogdanm	0:9b334a45a8ff	1084	#define SSP0CR0_DSS_MASK 0x000F // Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
bogdanm	0:9b334a45a8ff	1085	#define SSP0CR0_DSS_SHIFT 0
bogdanm	0:9b334a45a8ff	1086	#define SSP0CR0_FRF_MASK 0x0030 // Frame Format.
bogdanm	0:9b334a45a8ff	1087	#define SSP0CR0_FRF_SHIFT 4
bogdanm	0:9b334a45a8ff	1088	#define SSP0CR0_CPOL (1 << 6) // Clock Out Polarity. This bit is only used in SPI mode.
bogdanm	0:9b334a45a8ff	1089	#define SSP0CR0_CPHA (1 << 7) // Clock Out Phase. This bit is only used in SPI mode.
bogdanm	0:9b334a45a8ff	1090	#define SSP0CR0_SCR_MASK 0xFF00 // Serial Clock Rate. The number of prescaler output clocks per 0x00 bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR [SCR+1]). Reserved
bogdanm	0:9b334a45a8ff	1091	#define SSP0CR0_SCR_SHIFT 8
bogdanm	0:9b334a45a8ff	1092
bogdanm	0:9b334a45a8ff	1093	/* SSP0CR1 - address 0x4004 0004, SSP1CR1 - address 0x4005 8004 */
bogdanm	0:9b334a45a8ff	1094	#define SSP0CR1_LBM (1 << 0) // Loop Back Mode.
bogdanm	0:9b334a45a8ff	1095	#define SSP0CR1_SSE (1 << 1) // SPI Enable.
bogdanm	0:9b334a45a8ff	1096	#define SSP0CR1_MS (1 << 2) // Master/Slave Mode.This bit can only be written when the SSE bit is 0.
bogdanm	0:9b334a45a8ff	1097	#define SSP0CR1_SOD (1 << 3) // Slave Output Disable. This bit is relevant only in slave 0 mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO).
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	/* SSP0DR - address 0x4004 0008, SSP1DR - address 0x4005 8008 */
bogdanm	0:9b334a45a8ff	1100	#define SSP0DR_DATA_MASK 0xFFFF // Write: software can write data to be sent in a future frame to this 0x0000 register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. Reserved.
bogdanm	0:9b334a45a8ff	1101	#define SSP0DR_DATA_SHIFT 0
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	/* SSP0SR - address 0x4004 000C, SSP1SR - address 0x4005 800C */
bogdanm	0:9b334a45a8ff	1104	#define SSP0SR_TFE (1 << 0) // Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
bogdanm	0:9b334a45a8ff	1105	#define SSP0SR_TNF (1 << 1) // Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
bogdanm	0:9b334a45a8ff	1106	#define SSP0SR_RNE (1 << 2) // Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
bogdanm	0:9b334a45a8ff	1107	#define SSP0SR_RFF (1 << 3) // Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
bogdanm	0:9b334a45a8ff	1108	#define SSP0SR_BSY (1 << 4) // Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
bogdanm	0:9b334a45a8ff	1109
bogdanm	0:9b334a45a8ff	1110	/* SSP0CPSR - address 0x4004 0010, SSP1CPSR - address 0x4005 8010 */
bogdanm	0:9b334a45a8ff	1111	#define SSP0CPSR_CPSDVSR_MASK 0x00FF // This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.
bogdanm	0:9b334a45a8ff	1112	#define SSP0CPSR_CPSDVSR_SHIFT 0
bogdanm	0:9b334a45a8ff	1113
bogdanm	0:9b334a45a8ff	1114	/* SSP0IMSC - address 0x4004 0014, SSP1IMSC - address 0x4005 8014 */
bogdanm	0:9b334a45a8ff	1115	#define SSP0IMSC_RORIM (1 << 0) // Software should set this bit to enable interrupt when a Receive 0 Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
bogdanm	0:9b334a45a8ff	1116	#define SSP0IMSC_RTIM (1 << 1) // Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
bogdanm	0:9b334a45a8ff	1117	#define SSP0IMSC_RXIM (1 << 2) // Software should set this bit to enable interrupt when the Rx FIFO is at 0 least half full.
bogdanm	0:9b334a45a8ff	1118	#define SSP0IMSC_TXIM (1 << 3) // Software should set this bit to enable interrupt when the Tx FIFO is at 0 least half empty.
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	/* SSP0RIS - address 0x4004 0018, SSP1RIS - address 0x4005 8018 */
bogdanm	0:9b334a45a8ff	1121	#define SSP0RIS_RORRIS (1 << 0) // This bit is 1 if another frame was completely received while the 0 RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
bogdanm	0:9b334a45a8ff	1122	#define SSP0RIS_RTRIS (1 << 1) // This bit is 1 if the Rx FIFO is not empty, and has not been read 0 for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
bogdanm	0:9b334a45a8ff	1123	#define SSP0RIS_RXRIS (1 << 2) // This bit is 1 if the Rx FIFO is at least half full.
bogdanm	0:9b334a45a8ff	1124	#define SSP0RIS_TXRIS (1 << 3) // This bit is 1 if the Tx FIFO is at least half empty.
bogdanm	0:9b334a45a8ff	1125
bogdanm	0:9b334a45a8ff	1126	/* SSP0MIS - address 0x4004 001C, SSP1MIS - address 0x4005 801C */
bogdanm	0:9b334a45a8ff	1127	#define SSP0MIS_RORMIS (1 << 0) // This bit is 1 if another frame was completely received while the 0 RxFIFO was full, and this interrupt is enabled.
bogdanm	0:9b334a45a8ff	1128	#define SSP0MIS_RTMIS (1 << 1) // This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
bogdanm	0:9b334a45a8ff	1129	#define SSP0MIS_RXMIS (1 << 2) // This bit is 1 if the Rx FIFO is at least half full, and this interrupt 0 is enabled.
bogdanm	0:9b334a45a8ff	1130	#define SSP0MIS_TXMIS (1 << 3) // This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.
bogdanm	0:9b334a45a8ff	1131
bogdanm	0:9b334a45a8ff	1132	/* SSP0ICR - address 0x4004 0020, SSP1ICR - address 0x4005 8020 */
bogdanm	0:9b334a45a8ff	1133	#define SSP0ICR_RORIC (1 << 0) // Writing a 1 to this bit clears the "frame was received when RxFIFO was full" interrupt.
bogdanm	0:9b334a45a8ff	1134	#define SSP0ICR_RTIC (1 << 1) // Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).
bogdanm	0:9b334a45a8ff	1135
bogdanm	0:9b334a45a8ff	1136	/* I2C0CONSET - address 0x4000 0000 */
bogdanm	0:9b334a45a8ff	1137	#define I2C0CONSET_AA (1 << 2) // Assert acknowledge flag.
bogdanm	0:9b334a45a8ff	1138	#define I2C0CONSET_SI (1 << 3) // I2C interrupt flag.
bogdanm	0:9b334a45a8ff	1139	#define I2C0CONSET_STO (1 << 4) // STOP flag.
bogdanm	0:9b334a45a8ff	1140	#define I2C0CONSET_STA (1 << 5) // START flag.
bogdanm	0:9b334a45a8ff	1141	#define I2C0CONSET_I2EN (1 << 6) // I2C interface enable. Reserved. The value read from a reserved bit is not defined.
bogdanm	0:9b334a45a8ff	1142
bogdanm	0:9b334a45a8ff	1143	/* I2C0STAT - 0x4000 0004 */
bogdanm	0:9b334a45a8ff	1144	#define I2C0STAT_STATUS_MASK 0x00F8 // These bits give the actual status information about the I2 C interface. Reserved. The value read from a reserved bit is not defined.
bogdanm	0:9b334a45a8ff	1145	#define I2C0STAT_STATUS_SHIFT 3
bogdanm	0:9b334a45a8ff	1146
bogdanm	0:9b334a45a8ff	1147	/* I2C0DAT - 0x4000 0008 */
bogdanm	0:9b334a45a8ff	1148	#define I2C0DAT_DATA_MASK 0x00FF // This register holds data values that have been received or are to 0 be transmitted. Reserved. The value read from a reserved bit is not defined.
bogdanm	0:9b334a45a8ff	1149	#define I2C0DAT_DATA_SHIFT 0
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	/* I2C0ADR0 - 0x4000 000C */
bogdanm	0:9b334a45a8ff	1152	#define I2C0ADR0_GC (1 << 0) // General Call enable bit.
bogdanm	0:9b334a45a8ff	1153	#define I2C0ADR0_ADDRESS_MASK 0x00FE // The I2C device address for slave mode. Reserved. The value read from a reserved bit is not defined.
bogdanm	0:9b334a45a8ff	1154	#define I2C0ADR0_ADDRESS_SHIFT 1
bogdanm	0:9b334a45a8ff	1155
bogdanm	0:9b334a45a8ff	1156	/* I2C0SCLH - address 0x4000 0010 */
bogdanm	0:9b334a45a8ff	1157	#define I2C0SCLH_SCLH_MASK 0xFFFF // Count for SCL HIGH time period selection.
bogdanm	0:9b334a45a8ff	1158	#define I2C0SCLH_SCLH_SHIFT 0
bogdanm	0:9b334a45a8ff	1159
bogdanm	0:9b334a45a8ff	1160	/* I2C0SCLL - 0x4000 0014 */
bogdanm	0:9b334a45a8ff	1161	#define I2C0SCLL_SCLL_MASK 0xFFFF // Count for SCL low time period selection.
bogdanm	0:9b334a45a8ff	1162	#define I2C0SCLL_SCLL_SHIFT 0
bogdanm	0:9b334a45a8ff	1163
bogdanm	0:9b334a45a8ff	1164	/* I2C0CONCLR - 0x4000 0018 */
bogdanm	0:9b334a45a8ff	1165	#define I2C0CONCLR_AAC (1 << 2) // Assert acknowledge Clear bit.
bogdanm	0:9b334a45a8ff	1166	#define I2C0CONCLR_SIC (1 << 3) // I2C interrupt Clear bit.
bogdanm	0:9b334a45a8ff	1167	#define I2C0CONCLR_STAC (1 << 5) // START flag Clear bit.
bogdanm	0:9b334a45a8ff	1168	#define I2C0CONCLR_I2ENC (1 << 6) // I2C interface Disable bit. Reserved. The value read from a reserved bit is not defined.
bogdanm	0:9b334a45a8ff	1169
bogdanm	0:9b334a45a8ff	1170	/* I2C0MMCTRL - 0x4000 001C */
bogdanm	0:9b334a45a8ff	1171	#define I2C0MMCTRL_MM_ENA (1 << 0) // Monitor mode enable.
bogdanm	0:9b334a45a8ff	1172	#define I2C0MMCTRL_ENA_SCL (1 << 1) // SCL output enable.
bogdanm	0:9b334a45a8ff	1173
bogdanm	0:9b334a45a8ff	1174	/* I2C0DATA_BUFFER - 0x4000 002C */
bogdanm	0:9b334a45a8ff	1175	#define I2C0DATA_BUFFER_DATA_MASK 0x00FF // This register holds contents of the 8 MSBs of the DAT shift register. Reserved. The value read from a reserved bit is not defined.
bogdanm	0:9b334a45a8ff	1176	#define I2C0DATA_BUFFER_DATA_SHIFT 0
bogdanm	0:9b334a45a8ff	1177
bogdanm	0:9b334a45a8ff	1178	/* CANCNTL, address 0x4005 0000 */
bogdanm	0:9b334a45a8ff	1179	#define CANCNTL_INIT (1 << 0) // Initialization
bogdanm	0:9b334a45a8ff	1180	#define CANCNTL_IE (1 << 1) // Module interrupt enable
bogdanm	0:9b334a45a8ff	1181	#define CANCNTL_SIE (1 << 2) // Status change interrupt enable
bogdanm	0:9b334a45a8ff	1182	#define CANCNTL_EIE (1 << 3) // Error interrupt enable
bogdanm	0:9b334a45a8ff	1183	#define CANCNTL_DAR (1 << 5) // Disable automatic retransmission
bogdanm	0:9b334a45a8ff	1184	#define CANCNTL_CCE (1 << 6) // Configuration change enable
bogdanm	0:9b334a45a8ff	1185	#define CANCNTL_TEST (1 << 7) // Test mode enable
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	/* CANSTAT, address 0x4005 0004 */
bogdanm	0:9b334a45a8ff	1188	#define CANSTAT_LEC_MASK 0x0007 // Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to `0' when a message has been transferred (reception or transmission) without error. The unused code `111' may be written by the CPU to check for updates.
bogdanm	0:9b334a45a8ff	1189	#define CANSTAT_LEC_SHIFT 0
bogdanm	0:9b334a45a8ff	1190	#define CANSTAT_TXOK (1 << 3) // Transmitted a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
bogdanm	0:9b334a45a8ff	1191	#define CANSTAT_RXOK (1 << 4) // Received a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
bogdanm	0:9b334a45a8ff	1192	#define CANSTAT_EPASS (1 << 5) // Error passive
bogdanm	0:9b334a45a8ff	1193	#define CANSTAT_EWARN (1 << 6) // Warning status
bogdanm	0:9b334a45a8ff	1194	#define CANSTAT_BOFF (1 << 7) // Busoff status
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	/* CANEC, address 0x4005 0008 */
bogdanm	0:9b334a45a8ff	1197	#define CANEC_TEC_MASK 0x00FF // Transmit error counter Current value of the transmit error counter (maximum value 255)
bogdanm	0:9b334a45a8ff	1198	#define CANEC_TEC_SHIFT 0
bogdanm	0:9b334a45a8ff	1199	#define CANEC_REC_MASK 0x7F00 // Receive error counter Current value of the receive error counter (maximum value 127).
bogdanm	0:9b334a45a8ff	1200	#define CANEC_REC_SHIFT 8
bogdanm	0:9b334a45a8ff	1201	#define CANEC_RP (1 << 15) // Receive error passive
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	/* CANBT, address 0x4005 000C */
bogdanm	0:9b334a45a8ff	1204	#define CANBT_BRP_MASK 0x003F // Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63.[1]
bogdanm	0:9b334a45a8ff	1205	#define CANBT_BRP_SHIFT 0
bogdanm	0:9b334a45a8ff	1206	#define CANBT_SJW_MASK 0x00C0 // (Re)synchronization jump width Valid programmed values are 0 to 3.[1]
bogdanm	0:9b334a45a8ff	1207	#define CANBT_SJW_SHIFT 6
bogdanm	0:9b334a45a8ff	1208	#define CANBT_TSEG1_MASK 0x0F00 // Time segment before the sample point Valid values are 1 to 15.[1]
bogdanm	0:9b334a45a8ff	1209	#define CANBT_TSEG1_SHIFT 8
bogdanm	0:9b334a45a8ff	1210	#define CANBT_TSEG2_MASK 0x7000 // Time segment after the sample point Valid values are 0 to 7.[1]
bogdanm	0:9b334a45a8ff	1211	#define CANBT_TSEG2_SHIFT 12
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	/* CANINT, address 0x4005 0010 */
bogdanm	0:9b334a45a8ff	1214	#define CANINT_INTID_MASK 0xFFFF // 0x0000 = No interrupt is pending. 0 0x0001 - 0x0020 = Number of message object which caused the interrupt. 0x0021 - 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 - 0xFFFF = Unused
bogdanm	0:9b334a45a8ff	1215	#define CANINT_INTID_SHIFT 0
bogdanm	0:9b334a45a8ff	1216
bogdanm	0:9b334a45a8ff	1217	/* CANTEST, address 0x4005 0014 */
bogdanm	0:9b334a45a8ff	1218	#define CANTEST_BASIC (1 << 2) // Basic mode
bogdanm	0:9b334a45a8ff	1219	#define CANTEST_SILENT (1 << 3) // Silent mode
bogdanm	0:9b334a45a8ff	1220	#define CANTEST_LBACK (1 << 4) // Loop back mode
bogdanm	0:9b334a45a8ff	1221	#define CANTEST_TX_MASK 0x0060 // Control of CAN_TXD pins
bogdanm	0:9b334a45a8ff	1222	#define CANTEST_TX_SHIFT 5
bogdanm	0:9b334a45a8ff	1223	#define CANTEST_RX (1 << 7) // Monitors the actual value of the CAN_RXD pin.
bogdanm	0:9b334a45a8ff	1224
bogdanm	0:9b334a45a8ff	1225	/* CANBRPE, address 0x4005 0018 */
bogdanm	0:9b334a45a8ff	1226	#define CANBRPE_BRPE_MASK 0x000F // Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0 to 15.
bogdanm	0:9b334a45a8ff	1227	#define CANBRPE_BRPE_SHIFT 0
bogdanm	0:9b334a45a8ff	1228
bogdanm	0:9b334a45a8ff	1229	/* CANIF1_CMDREQ, address 0x4005 0020 and CANIF2_CMDREQ, address 0x4005 0080 */
bogdanm	0:9b334a45a8ff	1230	#define CANIFn_CMDREQ_MN_MASK 0x003F // Message number 0x01 - 0x20 = Valid message numbers. The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 - 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]
bogdanm	0:9b334a45a8ff	1231	#define CANIFn_CMDREQ_MN_SHIFT 0
bogdanm	0:9b334a45a8ff	1232	#define CANIFn_CMDREQ_BUSY (1 << 15) // BUSY flag
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	/* CANIF1_CMDMSK, address 0x4005 0024 and CANIF2_CMDMSK, address 0x4005 0084 */
bogdanm	0:9b334a45a8ff	1235	#define CANIFn_CMDMSK_DATA_B (1 << 0) // Access data bytes 4-7
bogdanm	0:9b334a45a8ff	1236	#define CANIFn_CMDMSK_DATA_A (1 << 1) // Access data bytes 0-3
bogdanm	0:9b334a45a8ff	1237	#define CANIFn_CMDMSK_TXRQST (1 << 2) // Access transmission request bit (Write direction)
bogdanm	0:9b334a45a8ff	1238	#define CANIFn_CMDMSK_NEWDAT (1 << 2) // Access new data bit (Read direction)
bogdanm	0:9b334a45a8ff	1239	#define CANIFn_CMDMSK_CLRINTPND (1 << 3) // This bit is ignored in the write direction.
bogdanm	0:9b334a45a8ff	1240	#define CANIFn_CMDMSK_CTRL (1 << 4) // Access control bits
bogdanm	0:9b334a45a8ff	1241	#define CANIFn_CMDMSK_ARB (1 << 5) // Access arbitration bits
bogdanm	0:9b334a45a8ff	1242	#define CANIFn_CMDMSK_MASK (1 << 6) // Access mask bits
bogdanm	0:9b334a45a8ff	1243	#define CANIFn_CMDMSK_WR (1 << 7) // Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.
bogdanm	0:9b334a45a8ff	1244	#define CANIFn_CMDMSK_RD (0 << 7) // Read transfer Read data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	/* CANIF1_MSK1, address 0x4005 0028 and CANIF2_MASK1, address 0x4005 0088 */
bogdanm	0:9b334a45a8ff	1247	#define CANIFn_MSK1_MSK_MASK 0xFFFF // Identifier mask
bogdanm	0:9b334a45a8ff	1248	#define CANIFn_MSK1_MSK_SHIFT 0
bogdanm	0:9b334a45a8ff	1249
bogdanm	0:9b334a45a8ff	1250	/* CANIF1_MSK2, address 0x4005 002C and CANIF2_MASK2, address 0x4005 008C */
bogdanm	0:9b334a45a8ff	1251	#define CANIFn_MSK2_MSK_MASK 0x1FFF // Identifier mask
bogdanm	0:9b334a45a8ff	1252	#define CANIFn_MSK2_MSK_SHIFT 0
bogdanm	0:9b334a45a8ff	1253	#define CANIFn_MSK2_MDIR (1 << 14) // Mask message direction
bogdanm	0:9b334a45a8ff	1254	#define CANIFn_MSK2_MXTD (1 << 15) // Mask extend identifier
bogdanm	0:9b334a45a8ff	1255
bogdanm	0:9b334a45a8ff	1256	/* CANIF1_ARB1, address 0x4005 0030 and CANIF2_ARB1, address 0x4005 0090 */
bogdanm	0:9b334a45a8ff	1257	#define CANIFn_ARB1_ID_MASK 0xFFFF // Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)
bogdanm	0:9b334a45a8ff	1258	#define CANIFn_ARB1_ID_SHIFT 0
bogdanm	0:9b334a45a8ff	1259
bogdanm	0:9b334a45a8ff	1260	/* CANIF1_ARB2, address 0x4005 0034 and CANIF2_ARB2, address 0x4005 0094 */
bogdanm	0:9b334a45a8ff	1261	#define CANIFn_ARB2_ID_MASK 0x1FFF // Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)
bogdanm	0:9b334a45a8ff	1262	#define CANIFn_ARB2_ID_SHIFT 0
bogdanm	0:9b334a45a8ff	1263	#define CANIFn_ARB2_DIR (1 << 13) // Message direction
bogdanm	0:9b334a45a8ff	1264	#define CANIFn_ARB2_XTD (1 << 14) // Extend identifier
bogdanm	0:9b334a45a8ff	1265	#define CANIFn_ARB2_MSGVAL (1 << 15) // Message valid Remark: The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267	/* CANIF1_MCTRL, address 0x4005 0038 and CANIF2_MCTRL, address 0x4005 0098 */
bogdanm	0:9b334a45a8ff	1268	#define CANIFn_MCTRL_DLC_MASK 0x000F // Data length code Remark: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 - 1000 = Data frame has 0 - 8 data bytes. 1001 - 1111 = Data frame has 8 data bytes.
bogdanm	0:9b334a45a8ff	1269	#define CANIFn_MCTRL_DLC_SHIFT 0
bogdanm	0:9b334a45a8ff	1270	#define CANIFn_MCTRL_EOB (1 << 7) // End of buffer
bogdanm	0:9b334a45a8ff	1271	#define CANIFn_MCTRL_TXRQST (1 << 8) // Transmit request
bogdanm	0:9b334a45a8ff	1272	#define CANIFn_MCTRL_RMTEN (1 << 9) // Remote enable
bogdanm	0:9b334a45a8ff	1273	#define CANIFn_MCTRL_RXIE (1 << 10) // Receive interrupt enable
bogdanm	0:9b334a45a8ff	1274	#define CANIFn_MCTRL_TXIE (1 << 11) // Transmit interrupt enable
bogdanm	0:9b334a45a8ff	1275	#define CANIFn_MCTRL_UMASK (1 << 12) // Use acceptance mask Remark: If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.
bogdanm	0:9b334a45a8ff	1276	#define CANIFn_MCTRL_INTPND (1 << 13) // Interrupt pending
bogdanm	0:9b334a45a8ff	1277	#define CANIFn_MCTRL_MSGLST (1 << 14) // Message lost (only valid for message objects in the direction receive).
bogdanm	0:9b334a45a8ff	1278	#define CANIFn_MCTRL_NEWDAT (1 << 15) // New data
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/* CANIF1_DA1, address 0x4005 003C and CANIF2_DA1, address 0x4005 009C */
bogdanm	0:9b334a45a8ff	1281	#define CANIFn_DA1_DATA0_MASK 0x00FF // Data byte 0
bogdanm	0:9b334a45a8ff	1282	#define CANIFn_DA1_DATA0_SHIFT 0
bogdanm	0:9b334a45a8ff	1283	#define CANIFn_DA1_DATA1_MASK 0xFF00 // Data byte 1
bogdanm	0:9b334a45a8ff	1284	#define CANIFn_DA1_DATA1_SHIFT 8
bogdanm	0:9b334a45a8ff	1285
bogdanm	0:9b334a45a8ff	1286	/* CANIF1_DA2, address 0x4005 0040 and CANIF2_DA2, address 0x4005 00A0 */
bogdanm	0:9b334a45a8ff	1287	#define CANIFn_DA2_DATA2_MASK 0x00FF // Data byte 2
bogdanm	0:9b334a45a8ff	1288	#define CANIFn_DA2_DATA2_SHIFT 0
bogdanm	0:9b334a45a8ff	1289	#define CANIFn_DA2_DATA3_MASK 0xFF00 // Data byte 3
bogdanm	0:9b334a45a8ff	1290	#define CANIFn_DA2_DATA3_SHIFT 8
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	/* CANIF1_DB1, address 0x4005 0044 and CANIF2_DB1, address 0x4005 00A4 */
bogdanm	0:9b334a45a8ff	1293	#define CANIFn_DB1_DATA4_MASK 0x00FF // Data byte 4
bogdanm	0:9b334a45a8ff	1294	#define CANIFn_DB1_DATA4_SHIFT 0
bogdanm	0:9b334a45a8ff	1295	#define CANIFn_DB1_DATA5_MASK 0xFF00 // Data byte 5
bogdanm	0:9b334a45a8ff	1296	#define CANIFn_DB1_DATA5_SHIFT 8
bogdanm	0:9b334a45a8ff	1297
bogdanm	0:9b334a45a8ff	1298	/* CANIF1_DB2, address 0x4005 0048 and CANIF2_DB2, address 0x4005 00A8 */
bogdanm	0:9b334a45a8ff	1299	#define CANIFn_DB2_DATA6_MASK 0x00FF // Data byte 6
bogdanm	0:9b334a45a8ff	1300	#define CANIFn_DB2_DATA6_SHIFT 0
bogdanm	0:9b334a45a8ff	1301	#define CANIFn_DB2_DATA7_MASK 0xFF00 // Data byte 7
bogdanm	0:9b334a45a8ff	1302	#define CANIFn_DB2_DATA7_SHIFT 8
bogdanm	0:9b334a45a8ff	1303
bogdanm	0:9b334a45a8ff	1304	/* CANTXREQ1, address 0x4005 0100 */
bogdanm	0:9b334a45a8ff	1305	#define CANTXREQ1_TXRQST_MASK 0xFFFF // Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. Reserved
bogdanm	0:9b334a45a8ff	1306	#define CANTXREQ1_TXRQST_SHIFT 0
bogdanm	0:9b334a45a8ff	1307
bogdanm	0:9b334a45a8ff	1308	/* CANTXREQ2, address 0x4005 0104 */
bogdanm	0:9b334a45a8ff	1309	#define CANTXREQ2_TXRQST_MASK 0xFFFF // Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. Reserved
bogdanm	0:9b334a45a8ff	1310	#define CANTXREQ2_TXRQST_SHIFT 0
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	/* CANND1, address 0x4005 0120 */
bogdanm	0:9b334a45a8ff	1313	#define CANND1_NEWDAT_MASK 0xFFFF // New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.
bogdanm	0:9b334a45a8ff	1314	#define CANND1_NEWDAT_SHIFT 0
bogdanm	0:9b334a45a8ff	1315
bogdanm	0:9b334a45a8ff	1316	/* CANND2, address 0x4005 0124 */
bogdanm	0:9b334a45a8ff	1317	#define CANND2_NEWDAT_MASK 0xFFFF // New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.
bogdanm	0:9b334a45a8ff	1318	#define CANND2_NEWDAT_SHIFT 0
bogdanm	0:9b334a45a8ff	1319
bogdanm	0:9b334a45a8ff	1320	/* CANIR1, address 0x4005 0140 */
bogdanm	0:9b334a45a8ff	1321	#define CANIR1_INTPND_INTERRUPT_MASK 0xFFFF // pending bits of message objects 16 to 1. essage object is ignored by the message essage object is the source of an interrupt. Reserved
bogdanm	0:9b334a45a8ff	1322	#define CANIR1_INTPND_INTERRUPT_SHIFT 0
bogdanm	0:9b334a45a8ff	1323
bogdanm	0:9b334a45a8ff	1324	/* CANIR2, addresses 0x4005 0144 */
bogdanm	0:9b334a45a8ff	1325	#define CANIR2_INTPND_MASK 0xFFFF // Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt. Reserved
bogdanm	0:9b334a45a8ff	1326	#define CANIR2_INTPND_SHIFT 0
bogdanm	0:9b334a45a8ff	1327
bogdanm	0:9b334a45a8ff	1328	/* CANMSGV1, addresses 0x4005 0160 */
bogdanm	0:9b334a45a8ff	1329	#define CANMSGV1_MSGVAL_MASK 0xFFFF // Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. Reserved
bogdanm	0:9b334a45a8ff	1330	#define CANMSGV1_MSGVAL_SHIFT 0
bogdanm	0:9b334a45a8ff	1331
bogdanm	0:9b334a45a8ff	1332	/* CANMSGV2, address 0x4005 0164 */
bogdanm	0:9b334a45a8ff	1333	#define CANMSGV2_MSGVAL_MASK 0xFFFF // Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. Reserved
bogdanm	0:9b334a45a8ff	1334	#define CANMSGV2_MSGVAL_SHIFT 0
bogdanm	0:9b334a45a8ff	1335
bogdanm	0:9b334a45a8ff	1336	/* CANCLKDIV, address 0x4005 0180 */
bogdanm	0:9b334a45a8ff	1337	#define CANCLKDIV_CLKDIVVAL_MASK 0x000F // Clock divider value. CAN_CLK = PCLK/(CLKDIVVAL +1) 0000: CAN_CLK = PCLK divided by 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = PCLK divided by 3 0011: CAN_CLK = PCLK divided by 4. ... 1111: CAN_CLK = PCLK divided by 16.
bogdanm	0:9b334a45a8ff	1338	#define CANCLKDIV_CLKDIVVAL_SHIFT 0
bogdanm	0:9b334a45a8ff	1339
bogdanm	0:9b334a45a8ff	1340	/* TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000 */
bogdanm	0:9b334a45a8ff	1341	#define TMR16B0IR_MR0 (1 << 0) // Interrupt flag for match channel 0.
bogdanm	0:9b334a45a8ff	1342	#define TMR16B0IR_MR1 (1 << 1) // Interrupt flag for match channel 1.
bogdanm	0:9b334a45a8ff	1343	#define TMR16B0IR_MR2 (1 << 2) // Interrupt flag for match channel 2.
bogdanm	0:9b334a45a8ff	1344	#define TMR16B0IR_MR3 (1 << 3) // Interrupt flag for match channel 3.
bogdanm	0:9b334a45a8ff	1345	#define TMR16B0IR_CR0 (1 << 4) // Interrupt flag for capture channel 0 event.
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	/* TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR - address 0x4001 0004 */
bogdanm	0:9b334a45a8ff	1348	#define TMR16B0TCR_CEN (1 << 0) // Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
bogdanm	0:9b334a45a8ff	1349	#define TMR16B0TCR_CRST (1 << 1) // Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
bogdanm	0:9b334a45a8ff	1350
bogdanm	0:9b334a45a8ff	1351	/* TMR16B0TC, address 0x4000 C008 and TMR16B1TC 0x4001 0008 */
bogdanm	0:9b334a45a8ff	1352	#define TMR16B0TC_TC_MASK 0xFFFF // Timer counter value.
bogdanm	0:9b334a45a8ff	1353	#define TMR16B0TC_TC_SHIFT 0
bogdanm	0:9b334a45a8ff	1354
bogdanm	0:9b334a45a8ff	1355	/* TMR16B0PR, address 0x4000 C00C and TMR16B1PR 0x4001 000C */
bogdanm	0:9b334a45a8ff	1356	#define TMR16B0PR_PR_MASK 0xFFFF // Prescale max value.
bogdanm	0:9b334a45a8ff	1357	#define TMR16B0PR_PR_SHIFT 0
bogdanm	0:9b334a45a8ff	1358
bogdanm	0:9b334a45a8ff	1359	/* TMR16B0PC, address 0x4001 C010 and TMR16B1PC 0x4000 0010 */
bogdanm	0:9b334a45a8ff	1360	#define TMR16B0PC_PC_MASK 0xFFFF // Prescale counter value.
bogdanm	0:9b334a45a8ff	1361	#define TMR16B0PC_PC_SHIFT 0
bogdanm	0:9b334a45a8ff	1362
bogdanm	0:9b334a45a8ff	1363	/* TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014 */
bogdanm	0:9b334a45a8ff	1364	#define TMR16B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1365	#define TMR16B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
bogdanm	0:9b334a45a8ff	1366	#define TMR16B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1367	#define TMR16B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1368	#define TMR16B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
bogdanm	0:9b334a45a8ff	1369	#define TMR16B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1370	#define TMR16B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1371	#define TMR16B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
bogdanm	0:9b334a45a8ff	1372	#define TMR16B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1373	#define TMR16B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1374	#define TMR16B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
bogdanm	0:9b334a45a8ff	1375	#define TMR16B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1376
bogdanm	0:9b334a45a8ff	1377	/* TMR16B0MR0 to 3, addresses 0x4000 C018 to 24 and TMR16B1MR0 to 3, addresses 0x4001 0018 to 24 */
bogdanm	0:9b334a45a8ff	1378	#define TMR16B0MR0_to_3_MATCH_MASK 0xFFFF // Timer counter match value.
bogdanm	0:9b334a45a8ff	1379	#define TMR16B0MR0_to_3_MATCH_SHIFT 0
bogdanm	0:9b334a45a8ff	1380
bogdanm	0:9b334a45a8ff	1381	/* TMR16B0CCR - address 0x4000 C028 and TMR16B1CCR - address 0x4001 0028 */
bogdanm	0:9b334a45a8ff	1382	#define TMR16B0CCR_CAP0RE (1 << 0) // Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
bogdanm	0:9b334a45a8ff	1383	#define TMR16B0CCR_CAP0FE (1 << 1) // Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
bogdanm	0:9b334a45a8ff	1384	#define TMR16B0CCR_CAP0I (1 << 2) // Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.
bogdanm	0:9b334a45a8ff	1385
bogdanm	0:9b334a45a8ff	1386	/* TMR16B0CR0, address 0x4000 C02C and TMR16B1CR0, address 0x4001 002C */
bogdanm	0:9b334a45a8ff	1387	#define TMR16B0CR0_CAP_MASK 0xFFFF // Timer counter capture value.
bogdanm	0:9b334a45a8ff	1388	#define TMR16B0CR0_CAP_SHIFT 0
bogdanm	0:9b334a45a8ff	1389
bogdanm	0:9b334a45a8ff	1390	/* TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address 0x4001 003C */
bogdanm	0:9b334a45a8ff	1391	#define TMR16B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1392	#define TMR16B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1393	#define TMR16B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output match channel 2, whether or not 0 this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1394	#define TMR16B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output of match channel 3. When a match 0 occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.
bogdanm	0:9b334a45a8ff	1395	#define TMR16B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
bogdanm	0:9b334a45a8ff	1396	#define TMR16B0EMR_EMC0_SHIFT 4
bogdanm	0:9b334a45a8ff	1397	#define TMR16B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
bogdanm	0:9b334a45a8ff	1398	#define TMR16B0EMR_EMC1_SHIFT 6
bogdanm	0:9b334a45a8ff	1399	#define TMR16B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
bogdanm	0:9b334a45a8ff	1400	#define TMR16B0EMR_EMC2_SHIFT 8
bogdanm	0:9b334a45a8ff	1401	#define TMR16B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
bogdanm	0:9b334a45a8ff	1402	#define TMR16B0EMR_EMC3_SHIFT 10
bogdanm	0:9b334a45a8ff	1403
bogdanm	0:9b334a45a8ff	1404	/* TMR16B0CTCR - address 0x4000 C070 and TMR16B1CTCR - address 0x4001 0070 */
bogdanm	0:9b334a45a8ff	1405	#define TMR16B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK 00 edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
bogdanm	0:9b334a45a8ff	1406	#define TMR16B0CTCR_CTM_SHIFT 0
bogdanm	0:9b334a45a8ff	1407
bogdanm	0:9b334a45a8ff	1408	/* TMR16B0PWMC - address 0x4000 C074 and TMR16B1PWMC- address 0x4001 0074 */
bogdanm	0:9b334a45a8ff	1409	#define TMR16B0PWMC_PWMEN0 (1 << 0) // PWM channel0 enable
bogdanm	0:9b334a45a8ff	1410	#define TMR16B0PWMC_PWMEN1 (1 << 1) // PWM channel1 enable
bogdanm	0:9b334a45a8ff	1411	#define TMR16B0PWMC_PWMEN2 (1 << 2) // PWM channel2 enable
bogdanm	0:9b334a45a8ff	1412	#define TMR16B0PWMC_PWMEN3 (1 << 3) // PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.
bogdanm	0:9b334a45a8ff	1413
bogdanm	0:9b334a45a8ff	1414	/* TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000 */
bogdanm	0:9b334a45a8ff	1415	#define TMR16B0IR_MR0INT (1 << 0) // Interrupt flag for match channel 0.
bogdanm	0:9b334a45a8ff	1416	#define TMR16B0IR_MR1INT (1 << 1) // Interrupt flag for match channel 1.
bogdanm	0:9b334a45a8ff	1417	#define TMR16B0IR_MR2INT (1 << 2) // Interrupt flag for match channel 2.
bogdanm	0:9b334a45a8ff	1418	#define TMR16B0IR_MR3INT (1 << 3) // Interrupt flag for match channel 3.
bogdanm	0:9b334a45a8ff	1419	#define TMR16B0IR_CR0INT (1 << 4) // Interrupt flag for capture channel 0 event.
bogdanm	0:9b334a45a8ff	1420	#define TMR16B0IR_CR1INT (1 << 5) // Interrupt flag for capture channel 1 event.
bogdanm	0:9b334a45a8ff	1421
bogdanm	0:9b334a45a8ff	1422	/* TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR - address 0x4001 0004 */
bogdanm	0:9b334a45a8ff	1423	#define TMR16B0TCR_CEN (1 << 0) // Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
bogdanm	0:9b334a45a8ff	1424	#define TMR16B0TCR_CRST (1 << 1) // Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
bogdanm	0:9b334a45a8ff	1425
bogdanm	0:9b334a45a8ff	1426	/* TMR16B0TC, address 0x4000 C008 and TMR16B1TC 0x4001 0008 */
bogdanm	0:9b334a45a8ff	1427	#define TMR16B0TC_TC_MASK 0xFFFF // Timer counter value.
bogdanm	0:9b334a45a8ff	1428	#define TMR16B0TC_TC_SHIFT 0
bogdanm	0:9b334a45a8ff	1429
bogdanm	0:9b334a45a8ff	1430	/* TMR16B0PR, address 0x4000 C00C and TMR16B1PR 0x4001 000C */
bogdanm	0:9b334a45a8ff	1431	#define TMR16B0PR_PR_MASK 0xFFFF // Prescale max value.
bogdanm	0:9b334a45a8ff	1432	#define TMR16B0PR_PR_SHIFT 0
bogdanm	0:9b334a45a8ff	1433
bogdanm	0:9b334a45a8ff	1434	/* TMR16B0PC, address 0x4001 C010 and TMR16B1PC 0x4000 0010 */
bogdanm	0:9b334a45a8ff	1435	#define TMR16B0PC_PC_MASK 0xFFFF // Prescale counter value.
bogdanm	0:9b334a45a8ff	1436	#define TMR16B0PC_PC_SHIFT 0
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	/* TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014 */
bogdanm	0:9b334a45a8ff	1439	#define TMR16B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1440	#define TMR16B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
bogdanm	0:9b334a45a8ff	1441	#define TMR16B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1442	#define TMR16B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1443	#define TMR16B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
bogdanm	0:9b334a45a8ff	1444	#define TMR16B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1445	#define TMR16B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1446	#define TMR16B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
bogdanm	0:9b334a45a8ff	1447	#define TMR16B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1448	#define TMR16B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1449	#define TMR16B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
bogdanm	0:9b334a45a8ff	1450	#define TMR16B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1451
bogdanm	0:9b334a45a8ff	1452	/* TMR16B0MR0 to 3, addresses 0x4000 C018 to 24 and TMR16B1MR0 to 3, addresses 0x4001 0018 to 24 */
bogdanm	0:9b334a45a8ff	1453	#define TMR16B0MR0_to_3_MATCH_MASK 0xFFFF // Timer counter match value.
bogdanm	0:9b334a45a8ff	1454	#define TMR16B0MR0_to_3_MATCH_SHIFT 0
bogdanm	0:9b334a45a8ff	1455
bogdanm	0:9b334a45a8ff	1456	/* TMR16B0CCR - address 0x4000 C028 and TMR16B1CCR - address 0x4001 0028 */
bogdanm	0:9b334a45a8ff	1457	#define TMR16B0CCR_CAP0RE (1 << 0) // Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
bogdanm	0:9b334a45a8ff	1458	#define TMR16B0CCR_CAP0FE (1 << 1) // Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
bogdanm	0:9b334a45a8ff	1459	#define TMR16B0CCR_CAP0I (1 << 2) // Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.
bogdanm	0:9b334a45a8ff	1460	#define TMR16B0CCR_CAP1RE (1 << 3) // Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.
bogdanm	0:9b334a45a8ff	1461	#define TMR16B0CCR_CAP1FE (1 << 4) // Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will 0 cause CR1 to be loaded with the contents of TC.
bogdanm	0:9b334a45a8ff	1462	#define TMR16B0CCR_CAP1I (1 << 5) // Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt.
bogdanm	0:9b334a45a8ff	1463
bogdanm	0:9b334a45a8ff	1464	/* TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address 0x4001 003C */
bogdanm	0:9b334a45a8ff	1465	#define TMR16B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1466	#define TMR16B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, 0 whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1467	#define TMR16B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output match channel 2, whether or not 0 this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1468	#define TMR16B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output of match channel 3. When a match 0 occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.
bogdanm	0:9b334a45a8ff	1469	#define TMR16B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
bogdanm	0:9b334a45a8ff	1470	#define TMR16B0EMR_EMC0_SHIFT 4
bogdanm	0:9b334a45a8ff	1471	#define TMR16B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
bogdanm	0:9b334a45a8ff	1472	#define TMR16B0EMR_EMC1_SHIFT 6
bogdanm	0:9b334a45a8ff	1473	#define TMR16B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
bogdanm	0:9b334a45a8ff	1474	#define TMR16B0EMR_EMC2_SHIFT 8
bogdanm	0:9b334a45a8ff	1475	#define TMR16B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
bogdanm	0:9b334a45a8ff	1476	#define TMR16B0EMR_EMC3_SHIFT 10
bogdanm	0:9b334a45a8ff	1477
bogdanm	0:9b334a45a8ff	1478	/* TMR16B0CTCR - address 0x4000 C070 and TMR16B1CTCR - address 0x4001 0070 */
bogdanm	0:9b334a45a8ff	1479	#define TMR16B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK 00 edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).
bogdanm	0:9b334a45a8ff	1480	#define TMR16B0CTCR_CTM_SHIFT 0
bogdanm	0:9b334a45a8ff	1481	#define TMR16B0CTCR_SELCC_MASK 0x00E0 // When bit 4 is one, these bits select which capture input edge 0 will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.
bogdanm	0:9b334a45a8ff	1482	#define TMR16B0CTCR_SELCC_SHIFT 5
bogdanm	0:9b334a45a8ff	1483
bogdanm	0:9b334a45a8ff	1484	/* TMR16B0PWMC - address 0x4000 C074 and TMR16B1PWMC- address 0x4001 0074 */
bogdanm	0:9b334a45a8ff	1485	#define TMR16B0PWMC_PWMEN0 (1 << 0) // PWM channel0 enable
bogdanm	0:9b334a45a8ff	1486	#define TMR16B0PWMC_PWMEN1 (1 << 1) // PWM channel1 enable
bogdanm	0:9b334a45a8ff	1487	#define TMR16B0PWMC_PWMEN2 (1 << 2) // PWM channel2 enable
bogdanm	0:9b334a45a8ff	1488	#define TMR16B0PWMC_PWMEN3 (1 << 3) // PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.
bogdanm	0:9b334a45a8ff	1489
bogdanm	0:9b334a45a8ff	1490	/* TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000 */
bogdanm	0:9b334a45a8ff	1491	#define TMR32B0IR_MR0_INTERRUPT (1 << 0) // Interrupt flag for match channel 0.
bogdanm	0:9b334a45a8ff	1492	#define TMR32B0IR_MR1_INTERRUPT (1 << 1) // Interrupt flag for match channel 1.
bogdanm	0:9b334a45a8ff	1493	#define TMR32B0IR_MR2_INTERRUPT (1 << 2) // Interrupt flag for match channel 2.
bogdanm	0:9b334a45a8ff	1494	#define TMR32B0IR_MR3_INTERRUPT (1 << 3) // Interrupt flag for match channel 3.
bogdanm	0:9b334a45a8ff	1495	#define TMR32B0IR_CR0_INTERRUPT (1 << 4) // Interrupt flag for capture channel 0 event.
bogdanm	0:9b334a45a8ff	1496
bogdanm	0:9b334a45a8ff	1497	/* TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR - address 0x4001 8004 */
bogdanm	0:9b334a45a8ff	1498	#define TMR32B0TCR_CEN (1 << 0) // When one, the Timer Counter and Prescale Counter are 0 enabled for counting. When zero, the counters are disabled.
bogdanm	0:9b334a45a8ff	1499	#define TMR32B0TCR_CRST (1 << 1) // When one, the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
bogdanm	0:9b334a45a8ff	1500
bogdanm	0:9b334a45a8ff	1501	/* TMR32B0TC, address 0x4001 4008 and TMR32B1TC 0x4001 8008 */
bogdanm	0:9b334a45a8ff	1502	#define TMR32B0TC_TC_MASK 0xFFFFFFFF // Timer counter value.
bogdanm	0:9b334a45a8ff	1503	#define TMR32B0TC_TC_SHIFT 0
bogdanm	0:9b334a45a8ff	1504
bogdanm	0:9b334a45a8ff	1505	/* TMR32B0PR, address 0x4001 400C and TMR32B1PR 0x4001 800C */
bogdanm	0:9b334a45a8ff	1506	#define TMR32B0PR_PR_MASK 0xFFFFFFFF // Prescale value.
bogdanm	0:9b334a45a8ff	1507	#define TMR32B0PR_PR_SHIFT 0
bogdanm	0:9b334a45a8ff	1508
bogdanm	0:9b334a45a8ff	1509	/* TMR32B0PC, address 0x4001 4010 and TMR32B1PC 0x4001 8010 */
bogdanm	0:9b334a45a8ff	1510	#define TMR32B0PC_PC_MASK 0xFFFFFFFF // Prescale counter value.
bogdanm	0:9b334a45a8ff	1511	#define TMR32B0PC_PC_SHIFT 0
bogdanm	0:9b334a45a8ff	1512
bogdanm	0:9b334a45a8ff	1513	/* TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014 */
bogdanm	0:9b334a45a8ff	1514	#define TMR32B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1515	#define TMR32B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
bogdanm	0:9b334a45a8ff	1516	#define TMR32B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1517	#define TMR32B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1518	#define TMR32B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
bogdanm	0:9b334a45a8ff	1519	#define TMR32B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1520	#define TMR32B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1521	#define TMR32B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
bogdanm	0:9b334a45a8ff	1522	#define TMR32B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1523	#define TMR32B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1524	#define TMR32B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
bogdanm	0:9b334a45a8ff	1525	#define TMR32B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1526
bogdanm	0:9b334a45a8ff	1527	/* TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and TMR32B1MR0 to 3, addresses 0x4001 8018 to 24 */
bogdanm	0:9b334a45a8ff	1528	#define TMR32B0MRn_MATCH_MASK 0xFFFFFFFF // Timer counter match value.
bogdanm	0:9b334a45a8ff	1529	#define TMR32B0MRn_MATCH_SHIFT 0
bogdanm	0:9b334a45a8ff	1530
bogdanm	0:9b334a45a8ff	1531	/* TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address 0x4001 8028 */
bogdanm	0:9b334a45a8ff	1532	#define TMR32B0CCR_CAP0RE (1 << 0) // Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
bogdanm	0:9b334a45a8ff	1533	#define TMR32B0CCR_CAP0FE (1 << 1) // Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
bogdanm	0:9b334a45a8ff	1534	#define TMR32B0CCR_CAP0I (1 << 2) // Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
bogdanm	0:9b334a45a8ff	1535
bogdanm	0:9b334a45a8ff	1536	/* TMR32B0CR0, addresses 0x4001 402C and TMR32B1CR0, addresses 0x4001 802C */
bogdanm	0:9b334a45a8ff	1537	#define TMR32B0CR0_CAP_MASK 0xFFFFFFFF // Timer counter capture value.
bogdanm	0:9b334a45a8ff	1538	#define TMR32B0CR0_CAP_SHIFT 0
bogdanm	0:9b334a45a8ff	1539
bogdanm	0:9b334a45a8ff	1540	/* TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C */
bogdanm	0:9b334a45a8ff	1541	#define TMR32B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1542	#define TMR32B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1543	#define TMR32B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1544	#define TMR32B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1545	#define TMR32B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
bogdanm	0:9b334a45a8ff	1546	#define TMR32B0EMR_EMC0_SHIFT 4
bogdanm	0:9b334a45a8ff	1547	#define TMR32B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
bogdanm	0:9b334a45a8ff	1548	#define TMR32B0EMR_EMC1_SHIFT 6
bogdanm	0:9b334a45a8ff	1549	#define TMR32B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
bogdanm	0:9b334a45a8ff	1550	#define TMR32B0EMR_EMC2_SHIFT 8
bogdanm	0:9b334a45a8ff	1551	#define TMR32B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
bogdanm	0:9b334a45a8ff	1552	#define TMR32B0EMR_EMC3_SHIFT 10
bogdanm	0:9b334a45a8ff	1553
bogdanm	0:9b334a45a8ff	1554	/* TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR - address 0x4001 8070 */
bogdanm	0:9b334a45a8ff	1555	#define TMR32B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
bogdanm	0:9b334a45a8ff	1556	#define TMR32B0CTCR_CTM_SHIFT 0
bogdanm	0:9b334a45a8ff	1557	#define TMR32B0CTCR_CIS_MASK 0x000C // Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
bogdanm	0:9b334a45a8ff	1558	#define TMR32B0CTCR_CIS_SHIFT 2
bogdanm	0:9b334a45a8ff	1559
bogdanm	0:9b334a45a8ff	1560	/* TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC - 0x4001 8074 */
bogdanm	0:9b334a45a8ff	1561	#define TMR32B0PWMC_PWMEN0 (1 << 0) // PWM channel 0 enable
bogdanm	0:9b334a45a8ff	1562	#define TMR32B0PWMC_PWMEN1 (1 << 1) // PWM channel 1 enable
bogdanm	0:9b334a45a8ff	1563	#define TMR32B0PWMC_PWMEN2 (1 << 2) // PWM channel 2 enable
bogdanm	0:9b334a45a8ff	1564	#define TMR32B0PWMC_PWMEN3 (1 << 3) // PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.
bogdanm	0:9b334a45a8ff	1565
bogdanm	0:9b334a45a8ff	1566	/* TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000 */
bogdanm	0:9b334a45a8ff	1567	#define TMR32B0IR_MR0INT (1 << 0) // Interrupt flag for match channel 0.
bogdanm	0:9b334a45a8ff	1568	#define TMR32B0IR_MR1INT (1 << 1) // Interrupt flag for match channel 1.
bogdanm	0:9b334a45a8ff	1569	#define TMR32B0IR_MR2INT (1 << 2) // Interrupt flag for match channel 2.
bogdanm	0:9b334a45a8ff	1570	#define TMR32B0IR_MR3INT (1 << 3) // Interrupt flag for match channel 3.
bogdanm	0:9b334a45a8ff	1571	#define TMR32B0IR_CR0INT (1 << 4) // Interrupt flag for capture channel 0 event.
bogdanm	0:9b334a45a8ff	1572	#define TMR32B0IR_CR1INT (1 << 5) // Interrupt flag for capture channel 1 event.
bogdanm	0:9b334a45a8ff	1573
bogdanm	0:9b334a45a8ff	1574	/* TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR - address 0x4001 8004 */
bogdanm	0:9b334a45a8ff	1575	#define TMR32B0TCR_CEN (1 << 0) // When one, the Timer Counter and Prescale Counter are 0 enabled for counting. When zero, the counters are disabled.
bogdanm	0:9b334a45a8ff	1576	#define TMR32B0TCR_CRST (1 << 1) // When one, the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
bogdanm	0:9b334a45a8ff	1577
bogdanm	0:9b334a45a8ff	1578	/* TMR32B0TC, address 0x4001 4008 and TMR32B1TC 0x4001 8008 */
bogdanm	0:9b334a45a8ff	1579	#define TMR32B0TC_TC_MASK 0xFFFFFFFF // Timer counter value.
bogdanm	0:9b334a45a8ff	1580	#define TMR32B0TC_TC_SHIFT 0
bogdanm	0:9b334a45a8ff	1581
bogdanm	0:9b334a45a8ff	1582	/* TMR32B0PR, address 0x4001 400C and TMR32B1PR 0x4001 800C */
bogdanm	0:9b334a45a8ff	1583	#define TMR32B0PR_PR_MASK 0xFFFFFFFF // Prescale value.
bogdanm	0:9b334a45a8ff	1584	#define TMR32B0PR_PR_SHIFT 0
bogdanm	0:9b334a45a8ff	1585
bogdanm	0:9b334a45a8ff	1586	/* TMR32B0PC, address 0x4001 4010 and TMR32B1PC 0x4001 8010 */
bogdanm	0:9b334a45a8ff	1587	#define TMR32B0PC_PC_MASK 0xFFFFFFFF // Prescale counter value.
bogdanm	0:9b334a45a8ff	1588	#define TMR32B0PC_PC_SHIFT 0
bogdanm	0:9b334a45a8ff	1589
bogdanm	0:9b334a45a8ff	1590	/* TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014 */
bogdanm	0:9b334a45a8ff	1591	#define TMR32B0MCR_MR0I (1 << 0) // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1592	#define TMR32B0MCR_MR0R (1 << 1) // Reset on MR0: the TC will be reset if MR0 matches it.
bogdanm	0:9b334a45a8ff	1593	#define TMR32B0MCR_MR0S (1 << 2) // Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1594	#define TMR32B0MCR_MR1I (1 << 3) // Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1595	#define TMR32B0MCR_MR1R (1 << 4) // Reset on MR1: the TC will be reset if MR1 matches it.
bogdanm	0:9b334a45a8ff	1596	#define TMR32B0MCR_MR1S (1 << 5) // Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1597	#define TMR32B0MCR_MR2I (1 << 6) // Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1598	#define TMR32B0MCR_MR2R (1 << 7) // Reset on MR2: the TC will be reset if MR2 matches it.
bogdanm	0:9b334a45a8ff	1599	#define TMR32B0MCR_MR2S (1 << 8) // Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1600	#define TMR32B0MCR_MR3I (1 << 9) // Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
bogdanm	0:9b334a45a8ff	1601	#define TMR32B0MCR_MR3R (1 << 10) // Reset on MR3: the TC will be reset if MR3 matches it.
bogdanm	0:9b334a45a8ff	1602	#define TMR32B0MCR_MR3S (1 << 11) // Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches 0 the TC.
bogdanm	0:9b334a45a8ff	1603
bogdanm	0:9b334a45a8ff	1604	/* TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and TMR32B1MR0 to 3, addresses 0x4001 8018 to 24 */
bogdanm	0:9b334a45a8ff	1605	#define TMR32B0MRn_MATCH_MASK 0xFFFFFFFF // Timer counter match value.
bogdanm	0:9b334a45a8ff	1606	#define TMR32B0MRn_MATCH_SHIFT 0
bogdanm	0:9b334a45a8ff	1607
bogdanm	0:9b334a45a8ff	1608	/* TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address 0x4001 8028 */
bogdanm	0:9b334a45a8ff	1609	#define TMR32B0CCR_CAP0RE (1 << 0) // Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.
bogdanm	0:9b334a45a8ff	1610	#define TMR32B0CCR_CAP0FE (1 << 1) // Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will 0 cause CR0 to be loaded with the contents of TC.
bogdanm	0:9b334a45a8ff	1611	#define TMR32B0CCR_CAP0I (1 << 2) // Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.
bogdanm	0:9b334a45a8ff	1612	#define TMR32B0CCR_CAP1RE (1 << 3) // Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.
bogdanm	0:9b334a45a8ff	1613	#define TMR32B0CCR_CAP1FE (1 << 4) // Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will 0 cause CR1 to be loaded with the contents of TC.
bogdanm	0:9b334a45a8ff	1614	#define TMR32B0CCR_CAP1I (1 << 5) // Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt.
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616	/* TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C */
bogdanm	0:9b334a45a8ff	1617	#define TMR32B0EMR_EM0 (1 << 0) // External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1618	#define TMR32B0EMR_EM1 (1 << 1) // External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1619	#define TMR32B0EMR_EM2 (1 << 2) // External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this 0 output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1620	#define TMR32B0EMR_EM3 (1 << 3) // External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
bogdanm	0:9b334a45a8ff	1621	#define TMR32B0EMR_EMC0_MASK 0x0030 // External Match Control 0. Determines the functionality of External Match 0.
bogdanm	0:9b334a45a8ff	1622	#define TMR32B0EMR_EMC0_SHIFT 4
bogdanm	0:9b334a45a8ff	1623	#define TMR32B0EMR_EMC1_MASK 0x00C0 // External Match Control 1. Determines the functionality of External Match 1.
bogdanm	0:9b334a45a8ff	1624	#define TMR32B0EMR_EMC1_SHIFT 6
bogdanm	0:9b334a45a8ff	1625	#define TMR32B0EMR_EMC2_MASK 0x0300 // External Match Control 2. Determines the functionality of External Match 2.
bogdanm	0:9b334a45a8ff	1626	#define TMR32B0EMR_EMC2_SHIFT 8
bogdanm	0:9b334a45a8ff	1627	#define TMR32B0EMR_EMC3_MASK 0x0C00 // External Match Control 3. Determines the functionality of External Match 3.
bogdanm	0:9b334a45a8ff	1628	#define TMR32B0EMR_EMC3_SHIFT 10
bogdanm	0:9b334a45a8ff	1629
bogdanm	0:9b334a45a8ff	1630	/* TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR - address 0x4001 8070 */
bogdanm	0:9b334a45a8ff	1631	#define TMR32B0CTCR_CTM_MASK 0x0003 // Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge
bogdanm	0:9b334a45a8ff	1632	#define TMR32B0CTCR_CTM_SHIFT 0
bogdanm	0:9b334a45a8ff	1633	#define TMR32B0CTCR_CIS_MASK 0x000C // Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:
bogdanm	0:9b334a45a8ff	1634	#define TMR32B0CTCR_CIS_SHIFT 2
bogdanm	0:9b334a45a8ff	1635	#define TMR32B0CTCR_ENCC (1 << 4) // Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
bogdanm	0:9b334a45a8ff	1636	#define TMR32B0CTCR_SELCC_MASK 0x00E0 // When bit 4 is one, these bits select which capture input edge 0 will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.
bogdanm	0:9b334a45a8ff	1637	#define TMR32B0CTCR_SELCC_SHIFT 5
bogdanm	0:9b334a45a8ff	1638
bogdanm	0:9b334a45a8ff	1639	/* TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC - 0x4001 8074 */
bogdanm	0:9b334a45a8ff	1640	#define TMR32B0PWMC_PWMEN0 (1 << 0) // PWM channel 0 enable
bogdanm	0:9b334a45a8ff	1641	#define TMR32B0PWMC_PWMEN1 (1 << 1) // PWM channel 1 enable
bogdanm	0:9b334a45a8ff	1642	#define TMR32B0PWMC_PWMEN2 (1 << 2) // PWM channel 2 enable
bogdanm	0:9b334a45a8ff	1643	#define TMR32B0PWMC_PWMEN3 (1 << 3) // PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	/* WDMOD - 0x4000 4000 */
bogdanm	0:9b334a45a8ff	1646	#define WDMOD_WDEN (1 << 0) // Watchdog enable bit. This bit is Set Only. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one.
bogdanm	0:9b334a45a8ff	1647	#define WDMOD_WDRESET (1 << 1) // Watchdog reset enable bit. This bit is Set Only.
bogdanm	0:9b334a45a8ff	1648	#define WDMOD_WDTOF (1 << 2) // Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1.
bogdanm	0:9b334a45a8ff	1649	#define WDMOD_WDINT (1 << 3) // Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.
bogdanm	0:9b334a45a8ff	1650	#define WDMOD_WDPROTECT (1 << 4) // Watchdog update mode. This bit is Set Only.
bogdanm	0:9b334a45a8ff	1651
bogdanm	0:9b334a45a8ff	1652	/* WDTC - 0x4000 4004 */
bogdanm	0:9b334a45a8ff	1653	#define WDTC_COUNT_MASK 0xFFFFFF // Watchdog time-out interval.
bogdanm	0:9b334a45a8ff	1654	#define WDTC_COUNT_SHIFT 0
bogdanm	0:9b334a45a8ff	1655
bogdanm	0:9b334a45a8ff	1656	/* WDFEED - 0x4000 4008 */
bogdanm	0:9b334a45a8ff	1657	#define WDFEED_FEED_MASK 0x00FF // Feed value should be 0xAA followed by 0x55.
bogdanm	0:9b334a45a8ff	1658	#define WDFEED_FEED_SHIFT 0
bogdanm	0:9b334a45a8ff	1659
bogdanm	0:9b334a45a8ff	1660	/* WDTV - 0x4000 400C */
bogdanm	0:9b334a45a8ff	1661	#define WDTV_COUNT_MASK 0xFFFFFF // Counter timer value.
bogdanm	0:9b334a45a8ff	1662	#define WDTV_COUNT_SHIFT 0
bogdanm	0:9b334a45a8ff	1663
bogdanm	0:9b334a45a8ff	1664	/* WDWARNINT - 0x4000 4014 */
bogdanm	0:9b334a45a8ff	1665	#define WDWARNINT_WARNINT_MASK 0x03FF // Watchdog warning interrupt compare value.
bogdanm	0:9b334a45a8ff	1666	#define WDWARNINT_WARNINT_SHIFT 0
bogdanm	0:9b334a45a8ff	1667
bogdanm	0:9b334a45a8ff	1668	/* WDWINDOW - 0x4000 4018 */
bogdanm	0:9b334a45a8ff	1669	#define WDWINDOW_WINDOW_MASK 0xFFFFFF // Watchdog window value.
bogdanm	0:9b334a45a8ff	1670	#define WDWINDOW_WINDOW_SHIFT 0
bogdanm	0:9b334a45a8ff	1671
bogdanm	0:9b334a45a8ff	1672	/* WDMOD - address 0x4000 4000 */
bogdanm	0:9b334a45a8ff	1673	#define WDMOD_WDEN (1 << 0) // WDEN Watchdog enable bit (Set Only). When 1, the watchdog timer is running. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one. The clock source lock feature is not available on all parts, see Section 23.1).
bogdanm	0:9b334a45a8ff	1674	#define WDMOD_WDRESET_WDRESET (1 << 1) // Watchdog reset enable bit (Set Only). When 1, og time-out will cause a chip reset.
bogdanm	0:9b334a45a8ff	1675	#define WDMOD_WDTOF (1 << 2) // WDTOF Watchdog time-out flag. Set when the watchdog
bogdanm	0:9b334a45a8ff	1676	#define WDMOD_WDINT (1 << 3) // WDINT Watchdog interrupt flag (Read Only, not clearable by software).
bogdanm	0:9b334a45a8ff	1677
bogdanm	0:9b334a45a8ff	1678	/* WDTC - address 0x4000 4004 */
bogdanm	0:9b334a45a8ff	1679	#define WDTC_COUNT_MASK 0xFFFFFF // Watchdog time-out interval.
bogdanm	0:9b334a45a8ff	1680	#define WDTC_COUNT_SHIFT 0
bogdanm	0:9b334a45a8ff	1681
bogdanm	0:9b334a45a8ff	1682	/* WDFEED - address 0x4000 4008 */
bogdanm	0:9b334a45a8ff	1683	#define WDFEED_FEED_MASK 0x00FF // Feed value should be 0xAA followed by 0x55.
bogdanm	0:9b334a45a8ff	1684	#define WDFEED_FEED_SHIFT 0
bogdanm	0:9b334a45a8ff	1685
bogdanm	0:9b334a45a8ff	1686	/* WDTV - address 0x4000 000C */
bogdanm	0:9b334a45a8ff	1687	#define WDTV_COUNT_MASK 0xFFFFFF // Counter timer value.
bogdanm	0:9b334a45a8ff	1688	#define WDTV_COUNT_SHIFT 0
bogdanm	0:9b334a45a8ff	1689
bogdanm	0:9b334a45a8ff	1690	/* SYST_CSR - 0xE000 E010 */
bogdanm	0:9b334a45a8ff	1691	#define SYST_CSR_ENABLE (1 << 0) // System Tick counter enable. When 1, the counter is enabled. When 0, the counter is disabled.
bogdanm	0:9b334a45a8ff	1692	#define SYST_CSR_TICKINT (1 << 1) // System Tick interrupt enable. When 1, the System Tick interrupt 0 is enabled. When 0, the System Tick interrupt is disabled. When enabled, the interrupt is generated when the System Tick counter counts down to 0.
bogdanm	0:9b334a45a8ff	1693	#define SYST_CSR_CLKSOURCE (1 << 2) // System Tick clock source selection. When 1, the system clock (CPU) clock is selected. When 0, the system clock/2 is selected as the reference clock.
bogdanm	0:9b334a45a8ff	1694	#define SYST_CSR_COUNTFLAG (1 << 16) // Returns 1 if the SysTick timer counted to 0 since the last read of this register. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bogdanm	0:9b334a45a8ff	1695
bogdanm	0:9b334a45a8ff	1696	/* SYST_RVR - 0xE000 E014 */
bogdanm	0:9b334a45a8ff	1697	#define SYST_RVR_RELOAD_MASK 0xFFFFFF // This is the value that is loaded into the System Tick counter when it 0 counts down to 0.
bogdanm	0:9b334a45a8ff	1698	#define SYST_RVR_RELOAD_SHIFT 0
bogdanm	0:9b334a45a8ff	1699
bogdanm	0:9b334a45a8ff	1700	/* SYST_CVR - 0xE000 E018 */
bogdanm	0:9b334a45a8ff	1701	#define SYST_CVR_CURRENT_MASK 0xFFFFFF // Reading this register returns the current value of the System Tick counter. Writing any value clears the System Tick counter and the COUNTFLAG bit in STCTRL.
bogdanm	0:9b334a45a8ff	1702	#define SYST_CVR_CURRENT_SHIFT 0
bogdanm	0:9b334a45a8ff	1703
bogdanm	0:9b334a45a8ff	1704	/* SYST_CALIB - 0xE000 E01C */
bogdanm	0:9b334a45a8ff	1705	#define SYST_CALIB_TENMS_MASK 0xFFFFFF // See Table 461.
bogdanm	0:9b334a45a8ff	1706	#define SYST_CALIB_TENMS_SHIFT 0
bogdanm	0:9b334a45a8ff	1707	#define SYST_CALIB_SKEW (1 << 30) // See Table 461.
bogdanm	0:9b334a45a8ff	1708	#define SYST_CALIB_NOREF (1 << 31) // See Table 461.
bogdanm	0:9b334a45a8ff	1709
bogdanm	0:9b334a45a8ff	1710	/* AD0CR - address 0x4001 C000 */
bogdanm	0:9b334a45a8ff	1711	#define AD0CR_SEL_MASK 0x00FF // Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin 0x00 AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01).
bogdanm	0:9b334a45a8ff	1712	#define AD0CR_SEL_SHIFT 0
bogdanm	0:9b334a45a8ff	1713	#define AD0CR_CLKDIV_MASK 0xFF00 // The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which 0 should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
bogdanm	0:9b334a45a8ff	1714	#define AD0CR_CLKDIV_SHIFT 8
bogdanm	0:9b334a45a8ff	1715	#define AD0CR_BURST (1 << 16) // Burst mode Remark: If BURST is set to 1, the ADGINTEN bit in the AD0INTEN register (Table 365) must be set to 0.
bogdanm	0:9b334a45a8ff	1716	#define AD0CR_CLKS_MASK 0xE0000 // This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
bogdanm	0:9b334a45a8ff	1717	#define AD0CR_CLKS_SHIFT 17
bogdanm	0:9b334a45a8ff	1718	#define AD0CR_START_MASK 0x7000000 // When the BURST bit is 0, these bits control whether and when an A/D conversion is started:
bogdanm	0:9b334a45a8ff	1719	#define AD0CR_START_SHIFT 24
bogdanm	0:9b334a45a8ff	1720	#define AD0CR_EDGE (1 << 27) // This bit is significant only when the START field contains 010-111. In these cases:
bogdanm	0:9b334a45a8ff	1721
bogdanm	0:9b334a45a8ff	1722	/* AD0GDR - address 0x4001 C004 */
bogdanm	0:9b334a45a8ff	1723	#define AD0GDR_V_VREF_MASK 0xFFC0 // When DONE is 1, this field contains a binary fraction representing X the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
bogdanm	0:9b334a45a8ff	1724	#define AD0GDR_V_VREF_SHIFT 6
bogdanm	0:9b334a45a8ff	1725	#define AD0GDR_CHN_MASK 0x7000000 // These bits contain the channel from which the result bits V_VREF X were converted.
bogdanm	0:9b334a45a8ff	1726	#define AD0GDR_CHN_SHIFT 24
bogdanm	0:9b334a45a8ff	1727	#define AD0GDR_OVERRUN (1 << 30) // This bit is 1 in burst mode if the results of one or more conversions 0 was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.
bogdanm	0:9b334a45a8ff	1728	#define AD0GDR_DONE (1 << 31) // This bit is set to 1 when an A/D conversion completes. It is cleared 0 when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
bogdanm	0:9b334a45a8ff	1729
bogdanm	0:9b334a45a8ff	1730	/* AD0INTEN - address 0x4001 C00C */
bogdanm	0:9b334a45a8ff	1731	#define AD0INTEN_ADINTEN_MASK 0x00FF // These bits allow control over which A/D channels generate 0x00 interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
bogdanm	0:9b334a45a8ff	1732	#define AD0INTEN_ADINTEN_SHIFT 0
bogdanm	0:9b334a45a8ff	1733	#define AD0INTEN_ADGINTEN (1 << 8) // When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. Remark: This bit must be set to 0 in burst mode (BURST = 1 in the AD0CR register). Reserved. Unused, always 0.
bogdanm	0:9b334a45a8ff	1734
bogdanm	0:9b334a45a8ff	1735	/* AD0DR0 to AD0DR7 - addresses 0x4001 C010 to 0x4001 C02C */
bogdanm	0:9b334a45a8ff	1736	#define AD0DRn_V_VREF_MASK 0xFFC0 // When DONE is 1, this field contains a binary fraction representing the NA voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. Reserved.
bogdanm	0:9b334a45a8ff	1737	#define AD0DRn_V_VREF_SHIFT 6
bogdanm	0:9b334a45a8ff	1738	#define AD0DRn_OVERRUN (1 << 30) // This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.
bogdanm	0:9b334a45a8ff	1739	#define AD0DRn_DONE (1 << 31) // This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bogdanm	0:9b334a45a8ff	1740
bogdanm	0:9b334a45a8ff	1741	/* AD0STAT - address 0x4001 C030 */
bogdanm	0:9b334a45a8ff	1742	#define AD0STAT_DONE_MASK 0x00FF // These bits mirror the DONE status flags that appear in the result register for each A/D channel n.
bogdanm	0:9b334a45a8ff	1743	#define AD0STAT_DONE_SHIFT 0
bogdanm	0:9b334a45a8ff	1744	#define AD0STAT_OVERRUN_MASK 0xFF00 // These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
bogdanm	0:9b334a45a8ff	1745	#define AD0STAT_OVERRUN_SHIFT 8
bogdanm	0:9b334a45a8ff	1746	#define AD0STAT_ADINT (1 << 16) // This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. Reserved. Unused, always 0.
bogdanm	0:9b334a45a8ff	1747
bogdanm	0:9b334a45a8ff	1748	/* FLASHCFG, address 0x4003 C010 */
bogdanm	0:9b334a45a8ff	1749	#define FLASHCFG_FLASHTIM_MASK 0x0003 // Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
bogdanm	0:9b334a45a8ff	1750	#define FLASHCFG_FLASHTIM_SHIFT 0
bogdanm	0:9b334a45a8ff	1751
bogdanm	0:9b334a45a8ff	1752	/* FMSSTART - 0x4003 C020 */
bogdanm	0:9b334a45a8ff	1753	#define FMSSTART_START_MASK 0x1FFFF // Signature generation start address (corresponds to AHB byte address bits[20:4]).
bogdanm	0:9b334a45a8ff	1754	#define FMSSTART_START_SHIFT 0
bogdanm	0:9b334a45a8ff	1755
bogdanm	0:9b334a45a8ff	1756	/* FMSSTOP - 0x4003 C024 */
bogdanm	0:9b334a45a8ff	1757	#define FMSSTOP_STOP_MASK 0x1FFFF // BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).
bogdanm	0:9b334a45a8ff	1758	#define FMSSTOP_STOP_SHIFT 0
bogdanm	0:9b334a45a8ff	1759	#define FMSSTOP_SIG_START (1 << 17) // Start control bit for signature generation.
bogdanm	0:9b334a45a8ff	1760
bogdanm	0:9b334a45a8ff	1761	/* FMSTAT - 0x4003 CFE0 */
bogdanm	0:9b334a45a8ff	1762	#define FMSTAT_SIG_DONE (1 << 2) // When 1, a previously started signature generation has 0 completed. See FMSTATCLR register description for clearing this flag.
bogdanm	0:9b334a45a8ff	1763
bogdanm	0:9b334a45a8ff	1764	/* FMSTATCLR - 0x0x4003 CFE8 */
bogdanm	0:9b334a45a8ff	1765	#define FMSTATCLR_SIG_DONE_CLR (1 << 2) // Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.
bogdanm	0:9b334a45a8ff	1766
bogdanm	0:9b334a45a8ff	1767
bogdanm	0:9b334a45a8ff	1768	#endif

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Type:	Library
Created:	16 May 2016
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targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/bitfields.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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