en 129
fix LPC812 PWM
Fork of
mbed-dev
by 
mbed official
targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 80:bdf1132a57cf
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /* MPS2 CMSIS Library |
| bogdanm | 0:9b334a45a8ff | 2 | * |
| bogdanm | 0:9b334a45a8ff | 3 | * Copyright (c) 2006-2015 ARM Limited |
| bogdanm | 0:9b334a45a8ff | 4 | * All rights reserved. |
| bogdanm | 0:9b334a45a8ff | 5 | * |
| bogdanm | 0:9b334a45a8ff | 6 | * Redistribution and use in source and binary forms, with or without |
| bogdanm | 0:9b334a45a8ff | 7 | * modification, are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 8 | * |
| bogdanm | 0:9b334a45a8ff | 9 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 10 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 11 | * |
| bogdanm | 0:9b334a45a8ff | 12 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 13 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 14 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 15 | * |
| bogdanm | 0:9b334a45a8ff | 16 | * 3. Neither the name of the copyright holder nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 17 | * may be used to endorse or promote products derived from this software without |
| bogdanm | 0:9b334a45a8ff | 18 | * specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 19 | * |
| bogdanm | 0:9b334a45a8ff | 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 21 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| bogdanm | 0:9b334a45a8ff | 23 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| bogdanm | 0:9b334a45a8ff | 24 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| bogdanm | 0:9b334a45a8ff | 25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| bogdanm | 0:9b334a45a8ff | 26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| bogdanm | 0:9b334a45a8ff | 27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| bogdanm | 0:9b334a45a8ff | 28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| bogdanm | 0:9b334a45a8ff | 29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| bogdanm | 0:9b334a45a8ff | 30 | * POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 31 | ******************************************************************************* |
| bogdanm | 0:9b334a45a8ff | 32 | * @file CMSDK_CM7.h |
| bogdanm | 0:9b334a45a8ff | 33 | * @brief CMSIS Core Peripheral Access Layer Header File for |
| bogdanm | 0:9b334a45a8ff | 34 | * CMSDK_CM7 Device |
| bogdanm | 0:9b334a45a8ff | 35 | * @version V1.00 |
| bogdanm | 0:9b334a45a8ff | 36 | * @date 27. August 2014 |
| bogdanm | 0:9b334a45a8ff | 37 | * |
| bogdanm | 0:9b334a45a8ff | 38 | * @note configured for CM7 without FPU |
| bogdanm | 0:9b334a45a8ff | 39 | * |
| bogdanm | 0:9b334a45a8ff | 40 | *******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | |
| bogdanm | 0:9b334a45a8ff | 43 | #ifndef CMSDK_CM7_H |
| bogdanm | 0:9b334a45a8ff | 44 | #define CMSDK_CM7_H |
| bogdanm | 0:9b334a45a8ff | 45 | |
| bogdanm | 0:9b334a45a8ff | 46 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 47 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 48 | #endif |
| bogdanm | 0:9b334a45a8ff | 49 | |
| bogdanm | 0:9b334a45a8ff | 50 | |
| bogdanm | 0:9b334a45a8ff | 51 | /* ------------------------- Interrupt Number Definition ------------------------ */ |
| bogdanm | 0:9b334a45a8ff | 52 | |
| bogdanm | 0:9b334a45a8ff | 53 | typedef enum IRQn |
| bogdanm | 0:9b334a45a8ff | 54 | { |
| bogdanm | 0:9b334a45a8ff | 55 | /* ------------------- CM7 Processor Exceptions Numbers --------------------- */ |
| bogdanm | 0:9b334a45a8ff | 56 | NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 57 | // HardFault_IRQn = -13, /* 3 HardFault Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 58 | MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 59 | BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 60 | UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 61 | SVCall_IRQn = -5, /* 11 SV Call Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 62 | DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 63 | PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 64 | SysTick_IRQn = -1, /* 15 System Tick Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 65 | |
| bogdanm | 0:9b334a45a8ff | 66 | /* ---------------------- CMSDK_CM7 Specific Interrupt Numbers -------------- */ |
| bogdanm | 0:9b334a45a8ff | 67 | UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 68 | UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 69 | UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 70 | UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 71 | UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 72 | UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 73 | PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 74 | PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 75 | TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 76 | TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 77 | DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 78 | SPI_IRQn = 11, /* SPI Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 79 | UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 80 | ETHERNET_IRQn = 13, /* Ethernet Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 81 | I2S_IRQn = 14, /* I2S Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 82 | TSC_IRQn = 15, /* Touch Screen Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 83 | // DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 84 | PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */ |
| bogdanm | 0:9b334a45a8ff | 85 | PORT0_1_IRQn = 17, /* There are 16 pins in total */ |
| bogdanm | 0:9b334a45a8ff | 86 | PORT0_2_IRQn = 18, |
| bogdanm | 0:9b334a45a8ff | 87 | PORT0_3_IRQn = 19, |
| bogdanm | 0:9b334a45a8ff | 88 | PORT0_4_IRQn = 20, |
| bogdanm | 0:9b334a45a8ff | 89 | PORT0_5_IRQn = 21, |
| bogdanm | 0:9b334a45a8ff | 90 | PORT0_6_IRQn = 22, |
| bogdanm | 0:9b334a45a8ff | 91 | PORT0_7_IRQn = 23, |
| bogdanm | 0:9b334a45a8ff | 92 | PORT0_8_IRQn = 24, |
| bogdanm | 0:9b334a45a8ff | 93 | PORT0_9_IRQn = 25, |
| bogdanm | 0:9b334a45a8ff | 94 | PORT0_10_IRQn = 26, |
| bogdanm | 0:9b334a45a8ff | 95 | PORT0_11_IRQn = 27, |
| bogdanm | 0:9b334a45a8ff | 96 | PORT0_12_IRQn = 28, |
| bogdanm | 0:9b334a45a8ff | 97 | PORT0_13_IRQn = 29, |
| bogdanm | 0:9b334a45a8ff | 98 | PORT0_14_IRQn = 30, |
| bogdanm | 0:9b334a45a8ff | 99 | PORT0_15_IRQn = 31, |
| bogdanm | 0:9b334a45a8ff | 100 | } IRQn_Type; |
| bogdanm | 0:9b334a45a8ff | 101 | |
| bogdanm | 0:9b334a45a8ff | 102 | |
| bogdanm | 0:9b334a45a8ff | 103 | /* ================================================================================ */ |
| bogdanm | 0:9b334a45a8ff | 104 | /* ================ Processor and Core Peripheral Section ================ */ |
| bogdanm | 0:9b334a45a8ff | 105 | /* ================================================================================ */ |
| bogdanm | 0:9b334a45a8ff | 106 | |
| bogdanm | 0:9b334a45a8ff | 107 | /* -------- Configuration of the CM7 Processor and Core Peripherals --------- */ |
| bogdanm | 0:9b334a45a8ff | 108 | #define __CM4_REV 0x0000 /* Core revision r0p0 */ |
| bogdanm | 0:9b334a45a8ff | 109 | #define __MPU_PRESENT 1 /* MPU present or not */ |
| bogdanm | 0:9b334a45a8ff | 110 | #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ |
| bogdanm | 0:9b334a45a8ff | 111 | #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ |
| bogdanm | 0:9b334a45a8ff | 112 | #define __FPU_PRESENT 1 /* no FPU present */ |
| bogdanm | 0:9b334a45a8ff | 113 | #define __FPU_DP 1 /* unused */ |
| bogdanm | 0:9b334a45a8ff | 114 | #define __ICACHE_PRESENT 1 |
| bogdanm | 0:9b334a45a8ff | 115 | #define __DCACHE_PRESENT 1 |
| bogdanm | 0:9b334a45a8ff | 116 | |
| bogdanm | 0:9b334a45a8ff | 117 | #include "core_CM7.h" /* Processor and core peripherals */ |
| bogdanm | 0:9b334a45a8ff | 118 | #include "system_CMSDK_CM7.h" /* System Header */ |
| bogdanm | 0:9b334a45a8ff | 119 | |
| bogdanm | 0:9b334a45a8ff | 120 | |
| bogdanm | 0:9b334a45a8ff | 121 | /* ================================================================================ */ |
| bogdanm | 0:9b334a45a8ff | 122 | /* ================ Device Specific Peripheral Section ================ */ |
| bogdanm | 0:9b334a45a8ff | 123 | /* ================================================================================ */ |
| bogdanm | 0:9b334a45a8ff | 124 | |
| bogdanm | 0:9b334a45a8ff | 125 | /* ------------------- Start of section using anonymous unions ------------------ */ |
| bogdanm | 0:9b334a45a8ff | 126 | #if defined (__CC_ARM) |
| bogdanm | 0:9b334a45a8ff | 127 | #pragma push |
| bogdanm | 0:9b334a45a8ff | 128 | #pragma anon_unions |
| bogdanm | 0:9b334a45a8ff | 129 | #elif defined (__ICCARM__) |
| bogdanm | 0:9b334a45a8ff | 130 | #pragma language=extended |
| bogdanm | 0:9b334a45a8ff | 131 | #elif defined (__GNUC__) |
| bogdanm | 0:9b334a45a8ff | 132 | /* anonymous unions are enabled by default */ |
| bogdanm | 0:9b334a45a8ff | 133 | #elif defined (__TMS470__) |
| bogdanm | 0:9b334a45a8ff | 134 | /* anonymous unions are enabled by default */ |
| bogdanm | 0:9b334a45a8ff | 135 | #elif defined (__TASKING__) |
| bogdanm | 0:9b334a45a8ff | 136 | #pragma warning 586 |
| bogdanm | 0:9b334a45a8ff | 137 | #elif defined (__CSMC__) |
| bogdanm | 0:9b334a45a8ff | 138 | /* anonymous unions are enabled by default */ |
| bogdanm | 0:9b334a45a8ff | 139 | #else |
| bogdanm | 0:9b334a45a8ff | 140 | #warning Not supported compiler type |
| bogdanm | 0:9b334a45a8ff | 141 | #endif |
| bogdanm | 0:9b334a45a8ff | 142 | |
| bogdanm | 0:9b334a45a8ff | 143 | /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ |
| bogdanm | 0:9b334a45a8ff | 144 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 145 | { |
| bogdanm | 0:9b334a45a8ff | 146 | __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ |
| bogdanm | 0:9b334a45a8ff | 147 | __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ |
| bogdanm | 0:9b334a45a8ff | 148 | __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ |
| bogdanm | 0:9b334a45a8ff | 149 | union { |
| bogdanm | 0:9b334a45a8ff | 150 | __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ |
| bogdanm | 0:9b334a45a8ff | 151 | __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 152 | }; |
| bogdanm | 0:9b334a45a8ff | 153 | __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ |
| bogdanm | 0:9b334a45a8ff | 154 | |
| bogdanm | 0:9b334a45a8ff | 155 | } CMSDK_UART_TypeDef; |
| bogdanm | 0:9b334a45a8ff | 156 | |
| bogdanm | 0:9b334a45a8ff | 157 | /* CMSDK_UART DATA Register Definitions */ |
| bogdanm | 0:9b334a45a8ff | 158 | |
| bogdanm | 0:9b334a45a8ff | 159 | #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ |
| bogdanm | 0:9b334a45a8ff | 160 | #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ |
| bogdanm | 0:9b334a45a8ff | 161 | |
| bogdanm | 0:9b334a45a8ff | 162 | #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ |
| bogdanm | 0:9b334a45a8ff | 163 | #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ |
| bogdanm | 0:9b334a45a8ff | 164 | |
| bogdanm | 0:9b334a45a8ff | 165 | #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ |
| bogdanm | 0:9b334a45a8ff | 166 | #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ |
| bogdanm | 0:9b334a45a8ff | 167 | |
| bogdanm | 0:9b334a45a8ff | 168 | #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ |
| bogdanm | 0:9b334a45a8ff | 169 | #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ |
| bogdanm | 0:9b334a45a8ff | 170 | |
| bogdanm | 0:9b334a45a8ff | 171 | #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ |
| bogdanm | 0:9b334a45a8ff | 172 | #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ |
| bogdanm | 0:9b334a45a8ff | 173 | |
| bogdanm | 0:9b334a45a8ff | 174 | #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ |
| bogdanm | 0:9b334a45a8ff | 175 | #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ |
| bogdanm | 0:9b334a45a8ff | 176 | |
| bogdanm | 0:9b334a45a8ff | 177 | #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ |
| bogdanm | 0:9b334a45a8ff | 178 | #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ |
| bogdanm | 0:9b334a45a8ff | 179 | |
| bogdanm | 0:9b334a45a8ff | 180 | #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ |
| bogdanm | 0:9b334a45a8ff | 181 | #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ |
| bogdanm | 0:9b334a45a8ff | 182 | |
| bogdanm | 0:9b334a45a8ff | 183 | #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ |
| bogdanm | 0:9b334a45a8ff | 184 | #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ |
| bogdanm | 0:9b334a45a8ff | 185 | |
| bogdanm | 0:9b334a45a8ff | 186 | #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ |
| bogdanm | 0:9b334a45a8ff | 187 | #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ |
| bogdanm | 0:9b334a45a8ff | 188 | |
| bogdanm | 0:9b334a45a8ff | 189 | #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ |
| bogdanm | 0:9b334a45a8ff | 190 | #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ |
| bogdanm | 0:9b334a45a8ff | 191 | |
| bogdanm | 0:9b334a45a8ff | 192 | #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ |
| bogdanm | 0:9b334a45a8ff | 193 | #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ |
| bogdanm | 0:9b334a45a8ff | 194 | |
| bogdanm | 0:9b334a45a8ff | 195 | #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ |
| bogdanm | 0:9b334a45a8ff | 196 | #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ |
| bogdanm | 0:9b334a45a8ff | 197 | |
| bogdanm | 0:9b334a45a8ff | 198 | #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ |
| bogdanm | 0:9b334a45a8ff | 199 | #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ |
| bogdanm | 0:9b334a45a8ff | 200 | |
| bogdanm | 0:9b334a45a8ff | 201 | #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ |
| bogdanm | 0:9b334a45a8ff | 202 | #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ |
| bogdanm | 0:9b334a45a8ff | 203 | |
| bogdanm | 0:9b334a45a8ff | 204 | #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ |
| bogdanm | 0:9b334a45a8ff | 205 | #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ |
| bogdanm | 0:9b334a45a8ff | 206 | |
| bogdanm | 0:9b334a45a8ff | 207 | #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ |
| bogdanm | 0:9b334a45a8ff | 208 | #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ |
| bogdanm | 0:9b334a45a8ff | 209 | |
| bogdanm | 0:9b334a45a8ff | 210 | |
| bogdanm | 0:9b334a45a8ff | 211 | /*----------------------------- Timer (TIMER) -------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 212 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 213 | { |
| bogdanm | 0:9b334a45a8ff | 214 | __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ |
| bogdanm | 0:9b334a45a8ff | 215 | __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ |
| bogdanm | 0:9b334a45a8ff | 216 | __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ |
| bogdanm | 0:9b334a45a8ff | 217 | union { |
| bogdanm | 0:9b334a45a8ff | 218 | __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ |
| bogdanm | 0:9b334a45a8ff | 219 | __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 220 | }; |
| bogdanm | 0:9b334a45a8ff | 221 | |
| bogdanm | 0:9b334a45a8ff | 222 | } CMSDK_TIMER_TypeDef; |
| bogdanm | 0:9b334a45a8ff | 223 | |
| bogdanm | 0:9b334a45a8ff | 224 | /* CMSDK_TIMER CTRL Register Definitions */ |
| bogdanm | 0:9b334a45a8ff | 225 | |
| bogdanm | 0:9b334a45a8ff | 226 | #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ |
| bogdanm | 0:9b334a45a8ff | 227 | #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ |
| bogdanm | 0:9b334a45a8ff | 228 | |
| bogdanm | 0:9b334a45a8ff | 229 | #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ |
| bogdanm | 0:9b334a45a8ff | 230 | #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ |
| bogdanm | 0:9b334a45a8ff | 231 | |
| bogdanm | 0:9b334a45a8ff | 232 | #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ |
| bogdanm | 0:9b334a45a8ff | 233 | #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ |
| bogdanm | 0:9b334a45a8ff | 234 | |
| bogdanm | 0:9b334a45a8ff | 235 | #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ |
| bogdanm | 0:9b334a45a8ff | 236 | #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ |
| bogdanm | 0:9b334a45a8ff | 237 | |
| bogdanm | 0:9b334a45a8ff | 238 | #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ |
| bogdanm | 0:9b334a45a8ff | 239 | #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ |
| bogdanm | 0:9b334a45a8ff | 240 | |
| bogdanm | 0:9b334a45a8ff | 241 | #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ |
| bogdanm | 0:9b334a45a8ff | 242 | #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ |
| bogdanm | 0:9b334a45a8ff | 243 | |
| bogdanm | 0:9b334a45a8ff | 244 | #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ |
| bogdanm | 0:9b334a45a8ff | 245 | #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ |
| bogdanm | 0:9b334a45a8ff | 246 | |
| bogdanm | 0:9b334a45a8ff | 247 | #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ |
| bogdanm | 0:9b334a45a8ff | 248 | #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ |
| bogdanm | 0:9b334a45a8ff | 249 | |
| bogdanm | 0:9b334a45a8ff | 250 | |
| bogdanm | 0:9b334a45a8ff | 251 | /*------------- Timer (TIM) --------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 252 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 253 | { |
| bogdanm | 0:9b334a45a8ff | 254 | __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ |
| bogdanm | 0:9b334a45a8ff | 255 | __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ |
| bogdanm | 0:9b334a45a8ff | 256 | __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ |
| bogdanm | 0:9b334a45a8ff | 257 | __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ |
| bogdanm | 0:9b334a45a8ff | 258 | __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ |
| bogdanm | 0:9b334a45a8ff | 259 | __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ |
| bogdanm | 0:9b334a45a8ff | 260 | __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ |
| bogdanm | 0:9b334a45a8ff | 261 | uint32_t RESERVED0; |
| bogdanm | 0:9b334a45a8ff | 262 | __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ |
| bogdanm | 0:9b334a45a8ff | 263 | __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ |
| bogdanm | 0:9b334a45a8ff | 264 | __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ |
| bogdanm | 0:9b334a45a8ff | 265 | __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ |
| bogdanm | 0:9b334a45a8ff | 266 | __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ |
| bogdanm | 0:9b334a45a8ff | 267 | __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ |
| bogdanm | 0:9b334a45a8ff | 268 | __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ |
| bogdanm | 0:9b334a45a8ff | 269 | uint32_t RESERVED1[945]; |
| bogdanm | 0:9b334a45a8ff | 270 | __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ |
| bogdanm | 0:9b334a45a8ff | 271 | __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ |
| bogdanm | 0:9b334a45a8ff | 272 | } CMSDK_DUALTIMER_BOTH_TypeDef; |
| bogdanm | 0:9b334a45a8ff | 273 | |
| bogdanm | 0:9b334a45a8ff | 274 | #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ |
| bogdanm | 0:9b334a45a8ff | 275 | #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ |
| bogdanm | 0:9b334a45a8ff | 276 | |
| bogdanm | 0:9b334a45a8ff | 277 | #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ |
| bogdanm | 0:9b334a45a8ff | 278 | #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ |
| bogdanm | 0:9b334a45a8ff | 279 | |
| bogdanm | 0:9b334a45a8ff | 280 | #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ |
| bogdanm | 0:9b334a45a8ff | 281 | #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ |
| bogdanm | 0:9b334a45a8ff | 282 | |
| bogdanm | 0:9b334a45a8ff | 283 | #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ |
| bogdanm | 0:9b334a45a8ff | 284 | #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ |
| bogdanm | 0:9b334a45a8ff | 285 | |
| bogdanm | 0:9b334a45a8ff | 286 | #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ |
| bogdanm | 0:9b334a45a8ff | 287 | #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ |
| bogdanm | 0:9b334a45a8ff | 288 | |
| bogdanm | 0:9b334a45a8ff | 289 | #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ |
| bogdanm | 0:9b334a45a8ff | 290 | #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ |
| bogdanm | 0:9b334a45a8ff | 291 | |
| bogdanm | 0:9b334a45a8ff | 292 | #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ |
| bogdanm | 0:9b334a45a8ff | 293 | #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ |
| bogdanm | 0:9b334a45a8ff | 294 | |
| bogdanm | 0:9b334a45a8ff | 295 | #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ |
| bogdanm | 0:9b334a45a8ff | 296 | #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ |
| bogdanm | 0:9b334a45a8ff | 297 | |
| bogdanm | 0:9b334a45a8ff | 298 | #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ |
| bogdanm | 0:9b334a45a8ff | 299 | #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ |
| bogdanm | 0:9b334a45a8ff | 300 | |
| bogdanm | 0:9b334a45a8ff | 301 | #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ |
| bogdanm | 0:9b334a45a8ff | 302 | #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ |
| bogdanm | 0:9b334a45a8ff | 303 | |
| bogdanm | 0:9b334a45a8ff | 304 | #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ |
| bogdanm | 0:9b334a45a8ff | 305 | #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ |
| bogdanm | 0:9b334a45a8ff | 306 | |
| bogdanm | 0:9b334a45a8ff | 307 | #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ |
| bogdanm | 0:9b334a45a8ff | 308 | #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ |
| bogdanm | 0:9b334a45a8ff | 309 | |
| bogdanm | 0:9b334a45a8ff | 310 | #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ |
| bogdanm | 0:9b334a45a8ff | 311 | #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ |
| bogdanm | 0:9b334a45a8ff | 312 | |
| bogdanm | 0:9b334a45a8ff | 313 | #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ |
| bogdanm | 0:9b334a45a8ff | 314 | #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ |
| bogdanm | 0:9b334a45a8ff | 315 | |
| bogdanm | 0:9b334a45a8ff | 316 | #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ |
| bogdanm | 0:9b334a45a8ff | 317 | #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ |
| bogdanm | 0:9b334a45a8ff | 318 | |
| bogdanm | 0:9b334a45a8ff | 319 | #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ |
| bogdanm | 0:9b334a45a8ff | 320 | #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ |
| bogdanm | 0:9b334a45a8ff | 321 | |
| bogdanm | 0:9b334a45a8ff | 322 | #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ |
| bogdanm | 0:9b334a45a8ff | 323 | #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ |
| bogdanm | 0:9b334a45a8ff | 324 | |
| bogdanm | 0:9b334a45a8ff | 325 | #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ |
| bogdanm | 0:9b334a45a8ff | 326 | #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ |
| bogdanm | 0:9b334a45a8ff | 327 | |
| bogdanm | 0:9b334a45a8ff | 328 | #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ |
| bogdanm | 0:9b334a45a8ff | 329 | #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ |
| bogdanm | 0:9b334a45a8ff | 330 | |
| bogdanm | 0:9b334a45a8ff | 331 | #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ |
| bogdanm | 0:9b334a45a8ff | 332 | #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ |
| bogdanm | 0:9b334a45a8ff | 333 | |
| bogdanm | 0:9b334a45a8ff | 334 | #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ |
| bogdanm | 0:9b334a45a8ff | 335 | #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ |
| bogdanm | 0:9b334a45a8ff | 336 | |
| bogdanm | 0:9b334a45a8ff | 337 | #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ |
| bogdanm | 0:9b334a45a8ff | 338 | #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ |
| bogdanm | 0:9b334a45a8ff | 339 | |
| bogdanm | 0:9b334a45a8ff | 340 | #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ |
| bogdanm | 0:9b334a45a8ff | 341 | #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ |
| bogdanm | 0:9b334a45a8ff | 342 | |
| bogdanm | 0:9b334a45a8ff | 343 | #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ |
| bogdanm | 0:9b334a45a8ff | 344 | #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ |
| bogdanm | 0:9b334a45a8ff | 345 | |
| bogdanm | 0:9b334a45a8ff | 346 | |
| bogdanm | 0:9b334a45a8ff | 347 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 348 | { |
| bogdanm | 0:9b334a45a8ff | 349 | __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ |
| bogdanm | 0:9b334a45a8ff | 350 | __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ |
| bogdanm | 0:9b334a45a8ff | 351 | __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ |
| bogdanm | 0:9b334a45a8ff | 352 | __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ |
| bogdanm | 0:9b334a45a8ff | 353 | __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ |
| bogdanm | 0:9b334a45a8ff | 354 | __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ |
| bogdanm | 0:9b334a45a8ff | 355 | __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ |
| bogdanm | 0:9b334a45a8ff | 356 | } CMSDK_DUALTIMER_SINGLE_TypeDef; |
| bogdanm | 0:9b334a45a8ff | 357 | |
| bogdanm | 0:9b334a45a8ff | 358 | #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ |
| bogdanm | 0:9b334a45a8ff | 359 | #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ |
| bogdanm | 0:9b334a45a8ff | 360 | |
| bogdanm | 0:9b334a45a8ff | 361 | #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ |
| bogdanm | 0:9b334a45a8ff | 362 | #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ |
| bogdanm | 0:9b334a45a8ff | 363 | |
| bogdanm | 0:9b334a45a8ff | 364 | #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ |
| bogdanm | 0:9b334a45a8ff | 365 | #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ |
| bogdanm | 0:9b334a45a8ff | 366 | |
| bogdanm | 0:9b334a45a8ff | 367 | #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ |
| bogdanm | 0:9b334a45a8ff | 368 | #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ |
| bogdanm | 0:9b334a45a8ff | 369 | |
| bogdanm | 0:9b334a45a8ff | 370 | #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ |
| bogdanm | 0:9b334a45a8ff | 371 | #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ |
| bogdanm | 0:9b334a45a8ff | 372 | |
| bogdanm | 0:9b334a45a8ff | 373 | #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ |
| bogdanm | 0:9b334a45a8ff | 374 | #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ |
| bogdanm | 0:9b334a45a8ff | 375 | |
| bogdanm | 0:9b334a45a8ff | 376 | #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ |
| bogdanm | 0:9b334a45a8ff | 377 | #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ |
| bogdanm | 0:9b334a45a8ff | 378 | |
| bogdanm | 0:9b334a45a8ff | 379 | #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ |
| bogdanm | 0:9b334a45a8ff | 380 | #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ |
| bogdanm | 0:9b334a45a8ff | 381 | |
| bogdanm | 0:9b334a45a8ff | 382 | #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ |
| bogdanm | 0:9b334a45a8ff | 383 | #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ |
| bogdanm | 0:9b334a45a8ff | 384 | |
| bogdanm | 0:9b334a45a8ff | 385 | #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ |
| bogdanm | 0:9b334a45a8ff | 386 | #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ |
| bogdanm | 0:9b334a45a8ff | 387 | |
| bogdanm | 0:9b334a45a8ff | 388 | #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ |
| bogdanm | 0:9b334a45a8ff | 389 | #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ |
| bogdanm | 0:9b334a45a8ff | 390 | |
| bogdanm | 0:9b334a45a8ff | 391 | #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ |
| bogdanm | 0:9b334a45a8ff | 392 | #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ |
| bogdanm | 0:9b334a45a8ff | 393 | |
| bogdanm | 0:9b334a45a8ff | 394 | |
| bogdanm | 0:9b334a45a8ff | 395 | /*-------------------- General Purpose Input Output (GPIO) -------------------*/ |
| bogdanm | 0:9b334a45a8ff | 396 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 397 | { |
| bogdanm | 0:9b334a45a8ff | 398 | __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ |
| bogdanm | 0:9b334a45a8ff | 399 | __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ |
| bogdanm | 0:9b334a45a8ff | 400 | uint32_t RESERVED0[2]; |
| bogdanm | 0:9b334a45a8ff | 401 | __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ |
| bogdanm | 0:9b334a45a8ff | 402 | __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 403 | __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ |
| bogdanm | 0:9b334a45a8ff | 404 | __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 405 | __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ |
| bogdanm | 0:9b334a45a8ff | 406 | __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 407 | __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ |
| bogdanm | 0:9b334a45a8ff | 408 | __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 409 | __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ |
| bogdanm | 0:9b334a45a8ff | 410 | __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 411 | union { |
| bogdanm | 0:9b334a45a8ff | 412 | __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ |
| bogdanm | 0:9b334a45a8ff | 413 | __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 414 | }; |
| bogdanm | 0:9b334a45a8ff | 415 | uint32_t RESERVED1[241]; |
| bogdanm | 0:9b334a45a8ff | 416 | __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ |
| bogdanm | 0:9b334a45a8ff | 417 | __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ |
| bogdanm | 0:9b334a45a8ff | 418 | } CMSDK_GPIO_TypeDef; |
| bogdanm | 0:9b334a45a8ff | 419 | |
| bogdanm | 0:9b334a45a8ff | 420 | #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ |
| bogdanm | 0:9b334a45a8ff | 421 | #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ |
| bogdanm | 0:9b334a45a8ff | 422 | |
| bogdanm | 0:9b334a45a8ff | 423 | #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ |
| bogdanm | 0:9b334a45a8ff | 424 | #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ |
| bogdanm | 0:9b334a45a8ff | 425 | |
| bogdanm | 0:9b334a45a8ff | 426 | #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ |
| bogdanm | 0:9b334a45a8ff | 427 | #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ |
| bogdanm | 0:9b334a45a8ff | 428 | |
| bogdanm | 0:9b334a45a8ff | 429 | #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ |
| bogdanm | 0:9b334a45a8ff | 430 | #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ |
| bogdanm | 0:9b334a45a8ff | 431 | |
| bogdanm | 0:9b334a45a8ff | 432 | #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ |
| bogdanm | 0:9b334a45a8ff | 433 | #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ |
| bogdanm | 0:9b334a45a8ff | 434 | |
| bogdanm | 0:9b334a45a8ff | 435 | #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ |
| bogdanm | 0:9b334a45a8ff | 436 | #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ |
| bogdanm | 0:9b334a45a8ff | 437 | |
| bogdanm | 0:9b334a45a8ff | 438 | #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ |
| bogdanm | 0:9b334a45a8ff | 439 | #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ |
| bogdanm | 0:9b334a45a8ff | 440 | |
| bogdanm | 0:9b334a45a8ff | 441 | #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ |
| bogdanm | 0:9b334a45a8ff | 442 | #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ |
| bogdanm | 0:9b334a45a8ff | 443 | |
| bogdanm | 0:9b334a45a8ff | 444 | #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ |
| bogdanm | 0:9b334a45a8ff | 445 | #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ |
| bogdanm | 0:9b334a45a8ff | 446 | |
| bogdanm | 0:9b334a45a8ff | 447 | #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ |
| bogdanm | 0:9b334a45a8ff | 448 | #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ |
| bogdanm | 0:9b334a45a8ff | 449 | |
| bogdanm | 0:9b334a45a8ff | 450 | #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ |
| bogdanm | 0:9b334a45a8ff | 451 | #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ |
| bogdanm | 0:9b334a45a8ff | 452 | |
| bogdanm | 0:9b334a45a8ff | 453 | #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ |
| bogdanm | 0:9b334a45a8ff | 454 | #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ |
| bogdanm | 0:9b334a45a8ff | 455 | |
| bogdanm | 0:9b334a45a8ff | 456 | #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ |
| bogdanm | 0:9b334a45a8ff | 457 | #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ |
| bogdanm | 0:9b334a45a8ff | 458 | |
| bogdanm | 0:9b334a45a8ff | 459 | #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ |
| bogdanm | 0:9b334a45a8ff | 460 | #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ |
| bogdanm | 0:9b334a45a8ff | 461 | |
| bogdanm | 0:9b334a45a8ff | 462 | #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ |
| bogdanm | 0:9b334a45a8ff | 463 | #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ |
| bogdanm | 0:9b334a45a8ff | 464 | |
| bogdanm | 0:9b334a45a8ff | 465 | #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ |
| bogdanm | 0:9b334a45a8ff | 466 | #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ |
| bogdanm | 0:9b334a45a8ff | 467 | |
| bogdanm | 0:9b334a45a8ff | 468 | |
| bogdanm | 0:9b334a45a8ff | 469 | /*------------- System Control (SYSCON) --------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 470 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 471 | { |
| bogdanm | 0:9b334a45a8ff | 472 | __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ |
| bogdanm | 0:9b334a45a8ff | 473 | __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ |
| bogdanm | 0:9b334a45a8ff | 474 | __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ |
| bogdanm | 0:9b334a45a8ff | 475 | __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ |
| bogdanm | 0:9b334a45a8ff | 476 | __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ |
| bogdanm | 0:9b334a45a8ff | 477 | } CMSDK_SYSCON_TypeDef; |
| bogdanm | 0:9b334a45a8ff | 478 | |
| bogdanm | 0:9b334a45a8ff | 479 | #define CMSDK_SYSCON_REMAP_Pos 0 |
| bogdanm | 0:9b334a45a8ff | 480 | #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ |
| bogdanm | 0:9b334a45a8ff | 481 | |
| bogdanm | 0:9b334a45a8ff | 482 | #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 |
| bogdanm | 0:9b334a45a8ff | 483 | #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ |
| bogdanm | 0:9b334a45a8ff | 484 | |
| bogdanm | 0:9b334a45a8ff | 485 | #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 |
| bogdanm | 0:9b334a45a8ff | 486 | #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ |
| bogdanm | 0:9b334a45a8ff | 487 | |
| bogdanm | 0:9b334a45a8ff | 488 | #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 |
| bogdanm | 0:9b334a45a8ff | 489 | #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ |
| bogdanm | 0:9b334a45a8ff | 490 | |
| bogdanm | 0:9b334a45a8ff | 491 | #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 |
| bogdanm | 0:9b334a45a8ff | 492 | #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ |
| bogdanm | 0:9b334a45a8ff | 493 | |
| bogdanm | 0:9b334a45a8ff | 494 | #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 |
| bogdanm | 0:9b334a45a8ff | 495 | #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ |
| bogdanm | 0:9b334a45a8ff | 496 | |
| bogdanm | 0:9b334a45a8ff | 497 | #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 |
| bogdanm | 0:9b334a45a8ff | 498 | #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ |
| bogdanm | 0:9b334a45a8ff | 499 | |
| bogdanm | 0:9b334a45a8ff | 500 | #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 |
| bogdanm | 0:9b334a45a8ff | 501 | #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ |
| bogdanm | 0:9b334a45a8ff | 502 | |
| bogdanm | 0:9b334a45a8ff | 503 | #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 |
| bogdanm | 0:9b334a45a8ff | 504 | #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ |
| bogdanm | 0:9b334a45a8ff | 505 | |
| bogdanm | 0:9b334a45a8ff | 506 | #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 |
| bogdanm | 0:9b334a45a8ff | 507 | #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ |
| bogdanm | 0:9b334a45a8ff | 508 | |
| bogdanm | 0:9b334a45a8ff | 509 | |
| bogdanm | 0:9b334a45a8ff | 510 | /*------------- PL230 uDMA (PL230) --------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 511 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 512 | { |
| bogdanm | 0:9b334a45a8ff | 513 | __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ |
| bogdanm | 0:9b334a45a8ff | 514 | __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ |
| bogdanm | 0:9b334a45a8ff | 515 | __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ |
| bogdanm | 0:9b334a45a8ff | 516 | __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ |
| bogdanm | 0:9b334a45a8ff | 517 | __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ |
| bogdanm | 0:9b334a45a8ff | 518 | __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ |
| bogdanm | 0:9b334a45a8ff | 519 | __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ |
| bogdanm | 0:9b334a45a8ff | 520 | __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 521 | __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ |
| bogdanm | 0:9b334a45a8ff | 522 | __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 523 | __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ |
| bogdanm | 0:9b334a45a8ff | 524 | __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 525 | __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ |
| bogdanm | 0:9b334a45a8ff | 526 | __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 527 | __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ |
| bogdanm | 0:9b334a45a8ff | 528 | __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 529 | uint32_t RESERVED0[3]; |
| bogdanm | 0:9b334a45a8ff | 530 | __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ |
| bogdanm | 0:9b334a45a8ff | 531 | |
| bogdanm | 0:9b334a45a8ff | 532 | } CMSDK_PL230_TypeDef; |
| bogdanm | 0:9b334a45a8ff | 533 | |
| bogdanm | 0:9b334a45a8ff | 534 | #define PL230_DMA_CHNL_BITS 0 |
| bogdanm | 0:9b334a45a8ff | 535 | |
| bogdanm | 0:9b334a45a8ff | 536 | #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */ |
| bogdanm | 0:9b334a45a8ff | 537 | #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */ |
| bogdanm | 0:9b334a45a8ff | 538 | |
| bogdanm | 0:9b334a45a8ff | 539 | #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */ |
| bogdanm | 0:9b334a45a8ff | 540 | #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */ |
| bogdanm | 0:9b334a45a8ff | 541 | |
| bogdanm | 0:9b334a45a8ff | 542 | #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ |
| bogdanm | 0:9b334a45a8ff | 543 | #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ |
| bogdanm | 0:9b334a45a8ff | 544 | |
| bogdanm | 0:9b334a45a8ff | 545 | #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ |
| bogdanm | 0:9b334a45a8ff | 546 | #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ |
| bogdanm | 0:9b334a45a8ff | 547 | |
| bogdanm | 0:9b334a45a8ff | 548 | #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */ |
| bogdanm | 0:9b334a45a8ff | 549 | #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */ |
| bogdanm | 0:9b334a45a8ff | 550 | |
| bogdanm | 0:9b334a45a8ff | 551 | #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */ |
| bogdanm | 0:9b334a45a8ff | 552 | #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */ |
| bogdanm | 0:9b334a45a8ff | 553 | |
| bogdanm | 0:9b334a45a8ff | 554 | #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */ |
| bogdanm | 0:9b334a45a8ff | 555 | #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */ |
| bogdanm | 0:9b334a45a8ff | 556 | |
| bogdanm | 0:9b334a45a8ff | 557 | #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */ |
| bogdanm | 0:9b334a45a8ff | 558 | #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */ |
| bogdanm | 0:9b334a45a8ff | 559 | |
| bogdanm | 0:9b334a45a8ff | 560 | #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */ |
| bogdanm | 0:9b334a45a8ff | 561 | #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */ |
| bogdanm | 0:9b334a45a8ff | 562 | |
| bogdanm | 0:9b334a45a8ff | 563 | #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */ |
| bogdanm | 0:9b334a45a8ff | 564 | #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */ |
| bogdanm | 0:9b334a45a8ff | 565 | |
| bogdanm | 0:9b334a45a8ff | 566 | #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ |
| bogdanm | 0:9b334a45a8ff | 567 | #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ |
| bogdanm | 0:9b334a45a8ff | 568 | |
| bogdanm | 0:9b334a45a8ff | 569 | #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ |
| bogdanm | 0:9b334a45a8ff | 570 | #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ |
| bogdanm | 0:9b334a45a8ff | 571 | |
| bogdanm | 0:9b334a45a8ff | 572 | #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */ |
| bogdanm | 0:9b334a45a8ff | 573 | #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */ |
| bogdanm | 0:9b334a45a8ff | 574 | |
| bogdanm | 0:9b334a45a8ff | 575 | #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */ |
| bogdanm | 0:9b334a45a8ff | 576 | #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */ |
| bogdanm | 0:9b334a45a8ff | 577 | |
| bogdanm | 0:9b334a45a8ff | 578 | #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */ |
| bogdanm | 0:9b334a45a8ff | 579 | #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ |
| bogdanm | 0:9b334a45a8ff | 580 | |
| bogdanm | 0:9b334a45a8ff | 581 | #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ |
| bogdanm | 0:9b334a45a8ff | 582 | #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ |
| bogdanm | 0:9b334a45a8ff | 583 | |
| bogdanm | 0:9b334a45a8ff | 584 | #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */ |
| bogdanm | 0:9b334a45a8ff | 585 | #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */ |
| bogdanm | 0:9b334a45a8ff | 586 | |
| bogdanm | 0:9b334a45a8ff | 587 | #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */ |
| bogdanm | 0:9b334a45a8ff | 588 | #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */ |
| bogdanm | 0:9b334a45a8ff | 589 | |
| bogdanm | 0:9b334a45a8ff | 590 | #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */ |
| bogdanm | 0:9b334a45a8ff | 591 | #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ |
| bogdanm | 0:9b334a45a8ff | 592 | |
| bogdanm | 0:9b334a45a8ff | 593 | #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ |
| bogdanm | 0:9b334a45a8ff | 594 | #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ |
| bogdanm | 0:9b334a45a8ff | 595 | |
| bogdanm | 0:9b334a45a8ff | 596 | #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */ |
| bogdanm | 0:9b334a45a8ff | 597 | #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */ |
| bogdanm | 0:9b334a45a8ff | 598 | |
| bogdanm | 0:9b334a45a8ff | 599 | #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */ |
| bogdanm | 0:9b334a45a8ff | 600 | #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ |
| bogdanm | 0:9b334a45a8ff | 601 | |
| bogdanm | 0:9b334a45a8ff | 602 | #define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */ |
| bogdanm | 0:9b334a45a8ff | 603 | #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */ |
| bogdanm | 0:9b334a45a8ff | 604 | |
| bogdanm | 0:9b334a45a8ff | 605 | |
| bogdanm | 0:9b334a45a8ff | 606 | /*------------------- Watchdog ----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 607 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 608 | { |
| bogdanm | 0:9b334a45a8ff | 609 | |
| bogdanm | 0:9b334a45a8ff | 610 | __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ |
| bogdanm | 0:9b334a45a8ff | 611 | __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ |
| bogdanm | 0:9b334a45a8ff | 612 | __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ |
| bogdanm | 0:9b334a45a8ff | 613 | __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ |
| bogdanm | 0:9b334a45a8ff | 614 | __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ |
| bogdanm | 0:9b334a45a8ff | 615 | __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ |
| bogdanm | 0:9b334a45a8ff | 616 | uint32_t RESERVED0[762]; |
| bogdanm | 0:9b334a45a8ff | 617 | __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ |
| bogdanm | 0:9b334a45a8ff | 618 | uint32_t RESERVED1[191]; |
| bogdanm | 0:9b334a45a8ff | 619 | __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ |
| bogdanm | 0:9b334a45a8ff | 620 | __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ |
| bogdanm | 0:9b334a45a8ff | 621 | }CMSDK_WATCHDOG_TypeDef; |
| bogdanm | 0:9b334a45a8ff | 622 | |
| bogdanm | 0:9b334a45a8ff | 623 | #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ |
| bogdanm | 0:9b334a45a8ff | 624 | #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ |
| bogdanm | 0:9b334a45a8ff | 625 | |
| bogdanm | 0:9b334a45a8ff | 626 | #define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ |
| bogdanm | 0:9b334a45a8ff | 627 | #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */ |
| bogdanm | 0:9b334a45a8ff | 628 | |
| bogdanm | 0:9b334a45a8ff | 629 | #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ |
| bogdanm | 0:9b334a45a8ff | 630 | #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ |
| bogdanm | 0:9b334a45a8ff | 631 | |
| bogdanm | 0:9b334a45a8ff | 632 | #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ |
| bogdanm | 0:9b334a45a8ff | 633 | #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ |
| bogdanm | 0:9b334a45a8ff | 634 | |
| bogdanm | 0:9b334a45a8ff | 635 | #define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ |
| bogdanm | 0:9b334a45a8ff | 636 | #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ |
| bogdanm | 0:9b334a45a8ff | 637 | |
| bogdanm | 0:9b334a45a8ff | 638 | #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ |
| bogdanm | 0:9b334a45a8ff | 639 | #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ |
| bogdanm | 0:9b334a45a8ff | 640 | |
| bogdanm | 0:9b334a45a8ff | 641 | #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ |
| bogdanm | 0:9b334a45a8ff | 642 | #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ |
| bogdanm | 0:9b334a45a8ff | 643 | |
| bogdanm | 0:9b334a45a8ff | 644 | #define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ |
| bogdanm | 0:9b334a45a8ff | 645 | #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */ |
| bogdanm | 0:9b334a45a8ff | 646 | |
| bogdanm | 0:9b334a45a8ff | 647 | #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ |
| bogdanm | 0:9b334a45a8ff | 648 | #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ |
| bogdanm | 0:9b334a45a8ff | 649 | |
| bogdanm | 0:9b334a45a8ff | 650 | #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ |
| bogdanm | 0:9b334a45a8ff | 651 | #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ |
| bogdanm | 0:9b334a45a8ff | 652 | |
| bogdanm | 0:9b334a45a8ff | 653 | |
| bogdanm | 0:9b334a45a8ff | 654 | |
| bogdanm | 0:9b334a45a8ff | 655 | /* -------------------- End of section using anonymous unions ------------------- */ |
| bogdanm | 0:9b334a45a8ff | 656 | #if defined (__CC_ARM) |
| bogdanm | 0:9b334a45a8ff | 657 | #pragma pop |
| bogdanm | 0:9b334a45a8ff | 658 | #elif defined (__ICCARM__) |
| bogdanm | 0:9b334a45a8ff | 659 | /* leave anonymous unions enabled */ |
| bogdanm | 0:9b334a45a8ff | 660 | #elif defined (__GNUC__) |
| bogdanm | 0:9b334a45a8ff | 661 | /* anonymous unions are enabled by default */ |
| bogdanm | 0:9b334a45a8ff | 662 | #elif defined (__TMS470__) |
| bogdanm | 0:9b334a45a8ff | 663 | /* anonymous unions are enabled by default */ |
| bogdanm | 0:9b334a45a8ff | 664 | #elif defined (__TASKING__) |
| bogdanm | 0:9b334a45a8ff | 665 | #pragma warning restore |
| bogdanm | 0:9b334a45a8ff | 666 | #elif defined (__CSMC__) |
| bogdanm | 0:9b334a45a8ff | 667 | /* anonymous unions are enabled by default */ |
| bogdanm | 0:9b334a45a8ff | 668 | #else |
| bogdanm | 0:9b334a45a8ff | 669 | #warning Not supported compiler type |
| bogdanm | 0:9b334a45a8ff | 670 | #endif |
| bogdanm | 0:9b334a45a8ff | 671 | |
| bogdanm | 0:9b334a45a8ff | 672 | |
| bogdanm | 0:9b334a45a8ff | 673 | |
| bogdanm | 0:9b334a45a8ff | 674 | |
| bogdanm | 0:9b334a45a8ff | 675 | /* ================================================================================ */ |
| bogdanm | 0:9b334a45a8ff | 676 | /* ================ Peripheral memory map ================ */ |
| bogdanm | 0:9b334a45a8ff | 677 | /* ================================================================================ */ |
| bogdanm | 0:9b334a45a8ff | 678 | |
| bogdanm | 0:9b334a45a8ff | 679 | /* Peripheral and SRAM base address */ |
| bogdanm | 0:9b334a45a8ff | 680 | #define CMSDK_FLASH_BASE (0x00000000UL) |
| bogdanm | 0:9b334a45a8ff | 681 | #define CMSDK_SRAM_BASE (0x20000000UL) |
| bogdanm | 0:9b334a45a8ff | 682 | #define CMSDK_PERIPH_BASE (0x40000000UL) |
| bogdanm | 0:9b334a45a8ff | 683 | |
| bogdanm | 0:9b334a45a8ff | 684 | #define CMSDK_RAM_BASE (0x20000000UL) |
| bogdanm | 0:9b334a45a8ff | 685 | #define CMSDK_APB_BASE (0x40000000UL) |
| bogdanm | 0:9b334a45a8ff | 686 | #define CMSDK_AHB_BASE (0x40010000UL) |
| bogdanm | 0:9b334a45a8ff | 687 | |
| bogdanm | 0:9b334a45a8ff | 688 | /* APB peripherals */ |
| bogdanm | 0:9b334a45a8ff | 689 | #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) |
| bogdanm | 0:9b334a45a8ff | 690 | #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) |
| bogdanm | 0:9b334a45a8ff | 691 | #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) |
| bogdanm | 0:9b334a45a8ff | 692 | #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) |
| bogdanm | 0:9b334a45a8ff | 693 | #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) |
| bogdanm | 0:9b334a45a8ff | 694 | #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) |
| bogdanm | 0:9b334a45a8ff | 695 | #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) |
| bogdanm | 0:9b334a45a8ff | 696 | #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) |
| bogdanm | 0:9b334a45a8ff | 697 | #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) |
| bogdanm | 0:9b334a45a8ff | 698 | #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) |
| bogdanm | 0:9b334a45a8ff | 699 | |
| bogdanm | 0:9b334a45a8ff | 700 | /* AHB peripherals */ |
| bogdanm | 0:9b334a45a8ff | 701 | #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) |
| bogdanm | 0:9b334a45a8ff | 702 | #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) |
| bogdanm | 0:9b334a45a8ff | 703 | #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) |
| bogdanm | 0:9b334a45a8ff | 704 | #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) |
| bogdanm | 0:9b334a45a8ff | 705 | #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) |
| bogdanm | 0:9b334a45a8ff | 706 | |
| bogdanm | 0:9b334a45a8ff | 707 | |
| bogdanm | 0:9b334a45a8ff | 708 | /* ================================================================================ */ |
| bogdanm | 0:9b334a45a8ff | 709 | /* ================ Peripheral declaration ================ */ |
| bogdanm | 0:9b334a45a8ff | 710 | /* ================================================================================ */ |
| bogdanm | 0:9b334a45a8ff | 711 | |
| bogdanm | 0:9b334a45a8ff | 712 | #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) |
| bogdanm | 0:9b334a45a8ff | 713 | #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) |
| bogdanm | 0:9b334a45a8ff | 714 | #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) |
| bogdanm | 0:9b334a45a8ff | 715 | #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) |
| bogdanm | 0:9b334a45a8ff | 716 | #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) |
| bogdanm | 0:9b334a45a8ff | 717 | #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) |
| bogdanm | 0:9b334a45a8ff | 718 | #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) |
| bogdanm | 0:9b334a45a8ff | 719 | #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) |
| bogdanm | 0:9b334a45a8ff | 720 | #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) |
| bogdanm | 0:9b334a45a8ff | 721 | #define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) |
| bogdanm | 0:9b334a45a8ff | 722 | #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) |
| bogdanm | 0:9b334a45a8ff | 723 | #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) |
| bogdanm | 0:9b334a45a8ff | 724 | #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) |
| bogdanm | 0:9b334a45a8ff | 725 | #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) |
| bogdanm | 0:9b334a45a8ff | 726 | #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) |
| bogdanm | 0:9b334a45a8ff | 727 | |
| bogdanm | 0:9b334a45a8ff | 728 | |
| bogdanm | 0:9b334a45a8ff | 729 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 730 | } |
| bogdanm | 0:9b334a45a8ff | 731 | #endif |
| bogdanm | 0:9b334a45a8ff | 732 | |
| bogdanm | 0:9b334a45a8ff | 733 | #endif /* CMSDK_CM7_H */ |