mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim_ex.c@124:6a4a5b7d7324, 2016-05-09 (annotated)

Committer:: mbed_official
Date:: Mon May 09 18:30:12 2016 +0100
Revision:: 124:6a4a5b7d7324
Parent:: 0:9b334a45a8ff

Synchronized with git revision ad75bdcde34d7da9d54b7669010c7fb968a99c7c



Full URL: https://github.com/mbedmicro/mbed/commit/ad75bdcde34d7da9d54b7669010c7fb968a99c7c/



[STMF1] Stm32f1_hal_cube update

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f1xx_hal_tim_ex.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	124:6a4a5b7d7324	5	* @version V1.0.4
mbed_official	124:6a4a5b7d7324	6	* @date 29-April-2016
bogdanm	0:9b334a45a8ff	7	* @brief TIM HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Timer Extended peripheral:
bogdanm	0:9b334a45a8ff	10	* + Time Hall Sensor Interface Initialization
bogdanm	0:9b334a45a8ff	11	* + Time Hall Sensor Interface Start
bogdanm	0:9b334a45a8ff	12	* + Time Complementary signal bread and dead time configuration
bogdanm	0:9b334a45a8ff	13	* + Time Master and Slave synchronization configuration
bogdanm	0:9b334a45a8ff	14	* + Timer remapping capabilities configuration
bogdanm	0:9b334a45a8ff	15	@verbatim
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	##### TIMER Extended features #####
bogdanm	0:9b334a45a8ff	18	==============================================================================
bogdanm	0:9b334a45a8ff	19	[..]
bogdanm	0:9b334a45a8ff	20	The Timer Extended features include:
bogdanm	0:9b334a45a8ff	21	(#) Complementary outputs with programmable dead-time for :
bogdanm	0:9b334a45a8ff	22	(++) Output Compare
bogdanm	0:9b334a45a8ff	23	(++) PWM generation (Edge and Center-aligned Mode)
bogdanm	0:9b334a45a8ff	24	(++) One-pulse mode output
bogdanm	0:9b334a45a8ff	25	(#) Synchronization circuit to control the timer with external signals and to
bogdanm	0:9b334a45a8ff	26	interconnect several timers together.
bogdanm	0:9b334a45a8ff	27	(#) Break input to put the timer output signals in reset state or in a known state.
bogdanm	0:9b334a45a8ff	28	(#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
bogdanm	0:9b334a45a8ff	29	positioning purposes
bogdanm	0:9b334a45a8ff	30
bogdanm	0:9b334a45a8ff	31	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	32	==============================================================================
bogdanm	0:9b334a45a8ff	33	[..]
bogdanm	0:9b334a45a8ff	34	(#) Initialize the TIM low level resources by implementing the following functions
bogdanm	0:9b334a45a8ff	35	depending from feature used :
bogdanm	0:9b334a45a8ff	36	(++) Complementary Output Compare : HAL_TIM_OC_MspInit()
bogdanm	0:9b334a45a8ff	37	(++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
bogdanm	0:9b334a45a8ff	38	(++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
bogdanm	0:9b334a45a8ff	39	(++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
bogdanm	0:9b334a45a8ff	40
bogdanm	0:9b334a45a8ff	41	(#) Initialize the TIM low level resources :
bogdanm	0:9b334a45a8ff	42	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	43	(##) TIM pins configuration
bogdanm	0:9b334a45a8ff	44	(+++) Enable the clock for the TIM GPIOs using the following function:
mbed_official	124:6a4a5b7d7324	45	__HAL_RCC_GPIOx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	46	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	(#) The external Clock can be configured, if needed (the default clock is the
bogdanm	0:9b334a45a8ff	49	internal clock from the APBx), using the following function:
bogdanm	0:9b334a45a8ff	50	HAL_TIM_ConfigClockSource, the clock configuration should be done before
bogdanm	0:9b334a45a8ff	51	any start function.
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	(#) Configure the TIM in the desired functioning mode using one of the
bogdanm	0:9b334a45a8ff	54	initialization function of this driver:
bogdanm	0:9b334a45a8ff	55	(++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
bogdanm	0:9b334a45a8ff	56	Timer Hall Sensor Interface and the commutation event with the corresponding
bogdanm	0:9b334a45a8ff	57	Interrupt and DMA request if needed (Note that One Timer is used to interface
bogdanm	0:9b334a45a8ff	58	with the Hall sensor Interface and another Timer should be used to use
bogdanm	0:9b334a45a8ff	59	the commutation event).
bogdanm	0:9b334a45a8ff	60
bogdanm	0:9b334a45a8ff	61	(#) Activate the TIM peripheral using one of the start functions:
bogdanm	0:9b334a45a8ff	62	(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
bogdanm	0:9b334a45a8ff	63	(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
bogdanm	0:9b334a45a8ff	64	(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
bogdanm	0:9b334a45a8ff	65	(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67
bogdanm	0:9b334a45a8ff	68	@endverbatim
bogdanm	0:9b334a45a8ff	69	******************************************************************************
bogdanm	0:9b334a45a8ff	70	* @attention
bogdanm	0:9b334a45a8ff	71	*
mbed_official	124:6a4a5b7d7324	72	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	73	*
bogdanm	0:9b334a45a8ff	74	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	75	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	76	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	77	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	78	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	79	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	80	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	81	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	82	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	83	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	84	*
bogdanm	0:9b334a45a8ff	85	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	86	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	87	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	88	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	89	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	90	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	91	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	92	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	93	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	94	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	95	*
bogdanm	0:9b334a45a8ff	96	******************************************************************************
bogdanm	0:9b334a45a8ff	97	*/
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	100	#include "stm32f1xx_hal.h"
bogdanm	0:9b334a45a8ff	101
bogdanm	0:9b334a45a8ff	102	/** @addtogroup STM32F1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	103	* @{
bogdanm	0:9b334a45a8ff	104	*/
bogdanm	0:9b334a45a8ff	105
bogdanm	0:9b334a45a8ff	106	/** @defgroup TIMEx TIMEx
bogdanm	0:9b334a45a8ff	107	* @brief TIM Extended HAL module driver
bogdanm	0:9b334a45a8ff	108	* @{
bogdanm	0:9b334a45a8ff	109	*/
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111	#ifdef HAL_TIM_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	112
bogdanm	0:9b334a45a8ff	113	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	114	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	115	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	116	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	117	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	#if defined (STM32F100xB) \|\| defined (STM32F100xE) \|\| \
bogdanm	0:9b334a45a8ff	120	defined (STM32F103x6) \|\| defined (STM32F103xB) \|\| defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| \
bogdanm	0:9b334a45a8ff	121	defined (STM32F105xC) \|\| defined (STM32F107xC)
bogdanm	0:9b334a45a8ff	122	/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
bogdanm	0:9b334a45a8ff	123	* @{
bogdanm	0:9b334a45a8ff	124	*/
bogdanm	0:9b334a45a8ff	125	static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
bogdanm	0:9b334a45a8ff	126	/**
bogdanm	0:9b334a45a8ff	127	* @}
bogdanm	0:9b334a45a8ff	128	*/
bogdanm	0:9b334a45a8ff	129	#endif /* defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| */
bogdanm	0:9b334a45a8ff	130	/* defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| */
bogdanm	0:9b334a45a8ff	131	/* defined(STM32F105xC) \|\| defined(STM32F107xC) */
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
bogdanm	0:9b334a45a8ff	136	* @{
bogdanm	0:9b334a45a8ff	137	*/
bogdanm	0:9b334a45a8ff	138
bogdanm	0:9b334a45a8ff	139
bogdanm	0:9b334a45a8ff	140	/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
bogdanm	0:9b334a45a8ff	141	* @brief Timer Hall Sensor functions
bogdanm	0:9b334a45a8ff	142	*
bogdanm	0:9b334a45a8ff	143	@verbatim
bogdanm	0:9b334a45a8ff	144	==============================================================================
bogdanm	0:9b334a45a8ff	145	##### Timer Hall Sensor functions #####
bogdanm	0:9b334a45a8ff	146	==============================================================================
bogdanm	0:9b334a45a8ff	147	[..]
bogdanm	0:9b334a45a8ff	148	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	149	(+) Initialize and configure TIM HAL Sensor.
bogdanm	0:9b334a45a8ff	150	(+) De-initialize TIM HAL Sensor.
bogdanm	0:9b334a45a8ff	151	(+) Start the Hall Sensor Interface.
bogdanm	0:9b334a45a8ff	152	(+) Stop the Hall Sensor Interface.
bogdanm	0:9b334a45a8ff	153	(+) Start the Hall Sensor Interface and enable interrupts.
bogdanm	0:9b334a45a8ff	154	(+) Stop the Hall Sensor Interface and disable interrupts.
bogdanm	0:9b334a45a8ff	155	(+) Start the Hall Sensor Interface and enable DMA transfers.
bogdanm	0:9b334a45a8ff	156	(+) Stop the Hall Sensor Interface and disable DMA transfers.
bogdanm	0:9b334a45a8ff	157
bogdanm	0:9b334a45a8ff	158	@endverbatim
bogdanm	0:9b334a45a8ff	159	* @{
bogdanm	0:9b334a45a8ff	160	*/
bogdanm	0:9b334a45a8ff	161	/**
bogdanm	0:9b334a45a8ff	162	* @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
bogdanm	0:9b334a45a8ff	163	* @param htim : TIM Encoder Interface handle
bogdanm	0:9b334a45a8ff	164	* @param sConfig : TIM Hall Sensor configuration structure
bogdanm	0:9b334a45a8ff	165	* @retval HAL status
bogdanm	0:9b334a45a8ff	166	*/
bogdanm	0:9b334a45a8ff	167	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef htim, TIM_HallSensor_InitTypeDef sConfig)
bogdanm	0:9b334a45a8ff	168	{
bogdanm	0:9b334a45a8ff	169	TIM_OC_InitTypeDef OC_Config;
bogdanm	0:9b334a45a8ff	170
bogdanm	0:9b334a45a8ff	171	/* Check the TIM handle allocation */
bogdanm	0:9b334a45a8ff	172	if(htim == NULL)
bogdanm	0:9b334a45a8ff	173	{
bogdanm	0:9b334a45a8ff	174	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	175	}
bogdanm	0:9b334a45a8ff	176
bogdanm	0:9b334a45a8ff	177	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	178	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
bogdanm	0:9b334a45a8ff	179	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
bogdanm	0:9b334a45a8ff	180	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
bogdanm	0:9b334a45a8ff	181	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
bogdanm	0:9b334a45a8ff	182	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	if(htim->State == HAL_TIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	185	{
bogdanm	0:9b334a45a8ff	186	/* Allocate lock resource and initialize it */
mbed_official	124:6a4a5b7d7324	187	htim->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	188
bogdanm	0:9b334a45a8ff	189	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
bogdanm	0:9b334a45a8ff	190	HAL_TIMEx_HallSensor_MspInit(htim);
bogdanm	0:9b334a45a8ff	191	}
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	/* Set the TIM state */
bogdanm	0:9b334a45a8ff	194	htim->State= HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	/* Configure the Time base in the Encoder Mode */
bogdanm	0:9b334a45a8ff	197	TIM_Base_SetConfig(htim->Instance, &htim->Init);
bogdanm	0:9b334a45a8ff	198
bogdanm	0:9b334a45a8ff	199	/* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
bogdanm	0:9b334a45a8ff	200	TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202	/* Reset the IC1PSC Bits */
bogdanm	0:9b334a45a8ff	203	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
bogdanm	0:9b334a45a8ff	204	/* Set the IC1PSC value */
bogdanm	0:9b334a45a8ff	205	htim->Instance->CCMR1 \|= sConfig->IC1Prescaler;
bogdanm	0:9b334a45a8ff	206
bogdanm	0:9b334a45a8ff	207	/* Enable the Hall sensor interface (XOR function of the three inputs) */
bogdanm	0:9b334a45a8ff	208	htim->Instance->CR2 \|= TIM_CR2_TI1S;
bogdanm	0:9b334a45a8ff	209
bogdanm	0:9b334a45a8ff	210	/* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
bogdanm	0:9b334a45a8ff	211	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	212	htim->Instance->SMCR \|= TIM_TS_TI1F_ED;
bogdanm	0:9b334a45a8ff	213
bogdanm	0:9b334a45a8ff	214	/* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
bogdanm	0:9b334a45a8ff	215	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
bogdanm	0:9b334a45a8ff	216	htim->Instance->SMCR \|= TIM_SLAVEMODE_RESET;
bogdanm	0:9b334a45a8ff	217
bogdanm	0:9b334a45a8ff	218	/* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
bogdanm	0:9b334a45a8ff	219	OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
bogdanm	0:9b334a45a8ff	220	OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
bogdanm	0:9b334a45a8ff	221	OC_Config.OCMode = TIM_OCMODE_PWM2;
bogdanm	0:9b334a45a8ff	222	OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
bogdanm	0:9b334a45a8ff	223	OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
bogdanm	0:9b334a45a8ff	224	OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
bogdanm	0:9b334a45a8ff	225	OC_Config.Pulse = sConfig->Commutation_Delay;
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227	TIM_OC2_SetConfig(htim->Instance, &OC_Config);
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	/* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
bogdanm	0:9b334a45a8ff	230	register to 101 */
bogdanm	0:9b334a45a8ff	231	htim->Instance->CR2 &= ~TIM_CR2_MMS;
bogdanm	0:9b334a45a8ff	232	htim->Instance->CR2 \|= TIM_TRGO_OC2REF;
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	/* Initialize the TIM state*/
bogdanm	0:9b334a45a8ff	235	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	236
bogdanm	0:9b334a45a8ff	237	return HAL_OK;
bogdanm	0:9b334a45a8ff	238	}
bogdanm	0:9b334a45a8ff	239
bogdanm	0:9b334a45a8ff	240	/**
bogdanm	0:9b334a45a8ff	241	* @brief DeInitializes the TIM Hall Sensor interface
bogdanm	0:9b334a45a8ff	242	* @param htim : TIM Hall Sensor handle
bogdanm	0:9b334a45a8ff	243	* @retval HAL status
bogdanm	0:9b334a45a8ff	244	*/
bogdanm	0:9b334a45a8ff	245	HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	246	{
bogdanm	0:9b334a45a8ff	247	/* Check the parameters */
bogdanm	0:9b334a45a8ff	248	assert_param(IS_TIM_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	251
bogdanm	0:9b334a45a8ff	252	/* Disable the TIM Peripheral Clock */
bogdanm	0:9b334a45a8ff	253	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	254
bogdanm	0:9b334a45a8ff	255	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
bogdanm	0:9b334a45a8ff	256	HAL_TIMEx_HallSensor_MspDeInit(htim);
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	/* Change TIM state */
bogdanm	0:9b334a45a8ff	259	htim->State = HAL_TIM_STATE_RESET;
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	/* Release Lock */
bogdanm	0:9b334a45a8ff	262	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	263
bogdanm	0:9b334a45a8ff	264	return HAL_OK;
bogdanm	0:9b334a45a8ff	265	}
bogdanm	0:9b334a45a8ff	266
bogdanm	0:9b334a45a8ff	267	/**
bogdanm	0:9b334a45a8ff	268	* @brief Initializes the TIM Hall Sensor MSP.
bogdanm	0:9b334a45a8ff	269	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	270	* @retval None
bogdanm	0:9b334a45a8ff	271	*/
bogdanm	0:9b334a45a8ff	272	__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	273	{
mbed_official	124:6a4a5b7d7324	274	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	275	UNUSED(htim);
bogdanm	0:9b334a45a8ff	276	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	277	the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	278	*/
bogdanm	0:9b334a45a8ff	279	}
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	/**
bogdanm	0:9b334a45a8ff	282	* @brief DeInitializes TIM Hall Sensor MSP.
bogdanm	0:9b334a45a8ff	283	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	284	* @retval None
bogdanm	0:9b334a45a8ff	285	*/
bogdanm	0:9b334a45a8ff	286	__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	287	{
mbed_official	124:6a4a5b7d7324	288	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	289	UNUSED(htim);
bogdanm	0:9b334a45a8ff	290	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	291	the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	292	*/
bogdanm	0:9b334a45a8ff	293	}
bogdanm	0:9b334a45a8ff	294
bogdanm	0:9b334a45a8ff	295	/**
bogdanm	0:9b334a45a8ff	296	* @brief Starts the TIM Hall Sensor Interface.
bogdanm	0:9b334a45a8ff	297	* @param htim : TIM Hall Sensor handle
bogdanm	0:9b334a45a8ff	298	* @retval HAL status
bogdanm	0:9b334a45a8ff	299	*/
bogdanm	0:9b334a45a8ff	300	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	301	{
bogdanm	0:9b334a45a8ff	302	/* Check the parameters */
bogdanm	0:9b334a45a8ff	303	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	304
bogdanm	0:9b334a45a8ff	305	/* Enable the Input Capture channel 1
bogdanm	0:9b334a45a8ff	306	(in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm	0:9b334a45a8ff	307	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	308
bogdanm	0:9b334a45a8ff	309	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	310	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	/* Return function status */
bogdanm	0:9b334a45a8ff	313	return HAL_OK;
bogdanm	0:9b334a45a8ff	314	}
bogdanm	0:9b334a45a8ff	315
bogdanm	0:9b334a45a8ff	316	/**
bogdanm	0:9b334a45a8ff	317	* @brief Stops the TIM Hall sensor Interface.
bogdanm	0:9b334a45a8ff	318	* @param htim : TIM Hall Sensor handle
bogdanm	0:9b334a45a8ff	319	* @retval HAL status
bogdanm	0:9b334a45a8ff	320	*/
bogdanm	0:9b334a45a8ff	321	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	322	{
bogdanm	0:9b334a45a8ff	323	/* Check the parameters */
bogdanm	0:9b334a45a8ff	324	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	325
bogdanm	0:9b334a45a8ff	326	/* Disable the Input Capture channel 1
bogdanm	0:9b334a45a8ff	327	(in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm	0:9b334a45a8ff	328	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	331	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	/* Return function status */
bogdanm	0:9b334a45a8ff	334	return HAL_OK;
bogdanm	0:9b334a45a8ff	335	}
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	/**
bogdanm	0:9b334a45a8ff	338	* @brief Starts the TIM Hall Sensor Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	339	* @param htim : TIM Hall Sensor handle
bogdanm	0:9b334a45a8ff	340	* @retval HAL status
bogdanm	0:9b334a45a8ff	341	*/
bogdanm	0:9b334a45a8ff	342	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	343	{
bogdanm	0:9b334a45a8ff	344	/* Check the parameters */
bogdanm	0:9b334a45a8ff	345	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	346
bogdanm	0:9b334a45a8ff	347	/* Enable the capture compare Interrupts 1 event */
bogdanm	0:9b334a45a8ff	348	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	349
bogdanm	0:9b334a45a8ff	350	/* Enable the Input Capture channel 1
bogdanm	0:9b334a45a8ff	351	(in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm	0:9b334a45a8ff	352	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	353
bogdanm	0:9b334a45a8ff	354	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	355	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	356
bogdanm	0:9b334a45a8ff	357	/* Return function status */
bogdanm	0:9b334a45a8ff	358	return HAL_OK;
bogdanm	0:9b334a45a8ff	359	}
bogdanm	0:9b334a45a8ff	360
bogdanm	0:9b334a45a8ff	361	/**
bogdanm	0:9b334a45a8ff	362	* @brief Stops the TIM Hall Sensor Interface in interrupt mode.
bogdanm	0:9b334a45a8ff	363	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	364	* @retval HAL status
bogdanm	0:9b334a45a8ff	365	*/
bogdanm	0:9b334a45a8ff	366	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	367	{
bogdanm	0:9b334a45a8ff	368	/* Check the parameters */
bogdanm	0:9b334a45a8ff	369	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	/* Disable the Input Capture channel 1
bogdanm	0:9b334a45a8ff	372	(in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm	0:9b334a45a8ff	373	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	374
bogdanm	0:9b334a45a8ff	375	/* Disable the capture compare Interrupts event */
bogdanm	0:9b334a45a8ff	376	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	377
bogdanm	0:9b334a45a8ff	378	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	379	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	/* Return function status */
bogdanm	0:9b334a45a8ff	382	return HAL_OK;
bogdanm	0:9b334a45a8ff	383	}
bogdanm	0:9b334a45a8ff	384
bogdanm	0:9b334a45a8ff	385	/**
bogdanm	0:9b334a45a8ff	386	* @brief Starts the TIM Hall Sensor Interface in DMA mode.
bogdanm	0:9b334a45a8ff	387	* @param htim : TIM Hall Sensor handle
bogdanm	0:9b334a45a8ff	388	* @param pData : The destination Buffer address.
bogdanm	0:9b334a45a8ff	389	* @param Length : The length of data to be transferred from TIM peripheral to memory.
bogdanm	0:9b334a45a8ff	390	* @retval HAL status
bogdanm	0:9b334a45a8ff	391	*/
bogdanm	0:9b334a45a8ff	392	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	393	{
bogdanm	0:9b334a45a8ff	394	/* Check the parameters */
bogdanm	0:9b334a45a8ff	395	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	398	{
bogdanm	0:9b334a45a8ff	399	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	400	}
bogdanm	0:9b334a45a8ff	401	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	402	{
bogdanm	0:9b334a45a8ff	403	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	404	{
bogdanm	0:9b334a45a8ff	405	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	406	}
bogdanm	0:9b334a45a8ff	407	else
bogdanm	0:9b334a45a8ff	408	{
bogdanm	0:9b334a45a8ff	409	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	410	}
bogdanm	0:9b334a45a8ff	411	}
bogdanm	0:9b334a45a8ff	412	/* Enable the Input Capture channel 1
bogdanm	0:9b334a45a8ff	413	(in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm	0:9b334a45a8ff	414	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416	/* Set the DMA Input Capture 1 Callback */
bogdanm	0:9b334a45a8ff	417	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
bogdanm	0:9b334a45a8ff	418	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	419	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	/* Enable the DMA channel for Capture 1*/
bogdanm	0:9b334a45a8ff	422	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424	/* Enable the capture compare 1 Interrupt */
bogdanm	0:9b334a45a8ff	425	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	428	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	/* Return function status */
bogdanm	0:9b334a45a8ff	431	return HAL_OK;
bogdanm	0:9b334a45a8ff	432	}
bogdanm	0:9b334a45a8ff	433
bogdanm	0:9b334a45a8ff	434	/**
bogdanm	0:9b334a45a8ff	435	* @brief Stops the TIM Hall Sensor Interface in DMA mode.
bogdanm	0:9b334a45a8ff	436	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	437	* @retval HAL status
bogdanm	0:9b334a45a8ff	438	*/
bogdanm	0:9b334a45a8ff	439	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	440	{
bogdanm	0:9b334a45a8ff	441	/* Check the parameters */
bogdanm	0:9b334a45a8ff	442	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	443
bogdanm	0:9b334a45a8ff	444	/* Disable the Input Capture channel 1
bogdanm	0:9b334a45a8ff	445	(in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
bogdanm	0:9b334a45a8ff	446	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	/* Disable the capture compare Interrupts 1 event */
bogdanm	0:9b334a45a8ff	450	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	451
bogdanm	0:9b334a45a8ff	452	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	453	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	454
bogdanm	0:9b334a45a8ff	455	/* Return function status */
bogdanm	0:9b334a45a8ff	456	return HAL_OK;
bogdanm	0:9b334a45a8ff	457	}
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	/**
bogdanm	0:9b334a45a8ff	460	* @}
bogdanm	0:9b334a45a8ff	461	*/
bogdanm	0:9b334a45a8ff	462
mbed_official	124:6a4a5b7d7324	463	#if defined (STM32F100xB) \|\| defined (STM32F100xE) \|\| \
mbed_official	124:6a4a5b7d7324	464	defined (STM32F103x6) \|\| defined (STM32F103xB) \|\| defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| \
mbed_official	124:6a4a5b7d7324	465	defined (STM32F105xC) \|\| defined (STM32F107xC)
mbed_official	124:6a4a5b7d7324	466
bogdanm	0:9b334a45a8ff	467	/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
bogdanm	0:9b334a45a8ff	468	* @brief Timer Complementary Output Compare functions
bogdanm	0:9b334a45a8ff	469	*
bogdanm	0:9b334a45a8ff	470	@verbatim
bogdanm	0:9b334a45a8ff	471	==============================================================================
bogdanm	0:9b334a45a8ff	472	##### Timer Complementary Output Compare functions #####
bogdanm	0:9b334a45a8ff	473	==============================================================================
bogdanm	0:9b334a45a8ff	474	[..]
bogdanm	0:9b334a45a8ff	475	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	476	(+) Start the Complementary Output Compare/PWM.
bogdanm	0:9b334a45a8ff	477	(+) Stop the Complementary Output Compare/PWM.
bogdanm	0:9b334a45a8ff	478	(+) Start the Complementary Output Compare/PWM and enable interrupts.
bogdanm	0:9b334a45a8ff	479	(+) Stop the Complementary Output Compare/PWM and disable interrupts.
bogdanm	0:9b334a45a8ff	480	(+) Start the Complementary Output Compare/PWM and enable DMA transfers.
bogdanm	0:9b334a45a8ff	481	(+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
bogdanm	0:9b334a45a8ff	482
bogdanm	0:9b334a45a8ff	483	@endverbatim
bogdanm	0:9b334a45a8ff	484	* @{
bogdanm	0:9b334a45a8ff	485	*/
bogdanm	0:9b334a45a8ff	486
bogdanm	0:9b334a45a8ff	487	/**
bogdanm	0:9b334a45a8ff	488	* @brief Starts the TIM Output Compare signal generation on the complementary
bogdanm	0:9b334a45a8ff	489	* output.
bogdanm	0:9b334a45a8ff	490	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	491	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	492	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	493	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	494	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	495	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	496	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	497	* @retval HAL status
bogdanm	0:9b334a45a8ff	498	*/
bogdanm	0:9b334a45a8ff	499	HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	500	{
bogdanm	0:9b334a45a8ff	501	/* Check the parameters */
bogdanm	0:9b334a45a8ff	502	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	503
bogdanm	0:9b334a45a8ff	504	/* Enable the Capture compare channel N */
bogdanm	0:9b334a45a8ff	505	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	506
bogdanm	0:9b334a45a8ff	507	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	508	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	509
bogdanm	0:9b334a45a8ff	510	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	511	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	512
bogdanm	0:9b334a45a8ff	513	/* Return function status */
bogdanm	0:9b334a45a8ff	514	return HAL_OK;
bogdanm	0:9b334a45a8ff	515	}
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	/**
bogdanm	0:9b334a45a8ff	518	* @brief Stops the TIM Output Compare signal generation on the complementary
bogdanm	0:9b334a45a8ff	519	* output.
bogdanm	0:9b334a45a8ff	520	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	521	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	522	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	523	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	524	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	525	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	526	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	527	* @retval HAL status
bogdanm	0:9b334a45a8ff	528	*/
bogdanm	0:9b334a45a8ff	529	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	530	{
bogdanm	0:9b334a45a8ff	531	/* Check the parameters */
bogdanm	0:9b334a45a8ff	532	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	533
bogdanm	0:9b334a45a8ff	534	/* Disable the Capture compare channel N */
bogdanm	0:9b334a45a8ff	535	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	536
bogdanm	0:9b334a45a8ff	537	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	538	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	539
bogdanm	0:9b334a45a8ff	540	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	541	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543	/* Return function status */
bogdanm	0:9b334a45a8ff	544	return HAL_OK;
bogdanm	0:9b334a45a8ff	545	}
bogdanm	0:9b334a45a8ff	546
bogdanm	0:9b334a45a8ff	547	/**
bogdanm	0:9b334a45a8ff	548	* @brief Starts the TIM Output Compare signal generation in interrupt mode
bogdanm	0:9b334a45a8ff	549	* on the complementary output.
bogdanm	0:9b334a45a8ff	550	* @param htim : TIM OC handle
bogdanm	0:9b334a45a8ff	551	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	552	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	553	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	554	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	555	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	556	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	557	* @retval HAL status
bogdanm	0:9b334a45a8ff	558	*/
bogdanm	0:9b334a45a8ff	559	HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	560	{
bogdanm	0:9b334a45a8ff	561	/* Check the parameters */
bogdanm	0:9b334a45a8ff	562	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	563
bogdanm	0:9b334a45a8ff	564	switch (Channel)
bogdanm	0:9b334a45a8ff	565	{
bogdanm	0:9b334a45a8ff	566	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	567	{
bogdanm	0:9b334a45a8ff	568	/* Enable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	569	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	570	}
bogdanm	0:9b334a45a8ff	571	break;
bogdanm	0:9b334a45a8ff	572
bogdanm	0:9b334a45a8ff	573	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	574	{
bogdanm	0:9b334a45a8ff	575	/* Enable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	576	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	577	}
bogdanm	0:9b334a45a8ff	578	break;
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	581	{
bogdanm	0:9b334a45a8ff	582	/* Enable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	583	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	584	}
bogdanm	0:9b334a45a8ff	585	break;
bogdanm	0:9b334a45a8ff	586
bogdanm	0:9b334a45a8ff	587	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	588	{
bogdanm	0:9b334a45a8ff	589	/* Enable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	590	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	591	}
bogdanm	0:9b334a45a8ff	592	break;
bogdanm	0:9b334a45a8ff	593
bogdanm	0:9b334a45a8ff	594	default:
bogdanm	0:9b334a45a8ff	595	break;
bogdanm	0:9b334a45a8ff	596	}
bogdanm	0:9b334a45a8ff	597
bogdanm	0:9b334a45a8ff	598	/* Enable the TIM Break interrupt */
bogdanm	0:9b334a45a8ff	599	__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/* Enable the Capture compare channel N */
bogdanm	0:9b334a45a8ff	602	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	603
bogdanm	0:9b334a45a8ff	604	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	605	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	608	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	/* Return function status */
bogdanm	0:9b334a45a8ff	611	return HAL_OK;
bogdanm	0:9b334a45a8ff	612	}
bogdanm	0:9b334a45a8ff	613
bogdanm	0:9b334a45a8ff	614	/**
bogdanm	0:9b334a45a8ff	615	* @brief Stops the TIM Output Compare signal generation in interrupt mode
bogdanm	0:9b334a45a8ff	616	* on the complementary output.
bogdanm	0:9b334a45a8ff	617	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	618	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	619	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	620	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	621	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	622	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	623	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	624	* @retval HAL status
bogdanm	0:9b334a45a8ff	625	*/
bogdanm	0:9b334a45a8ff	626	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	627	{
bogdanm	0:9b334a45a8ff	628	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	629
bogdanm	0:9b334a45a8ff	630	/* Check the parameters */
bogdanm	0:9b334a45a8ff	631	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	632
bogdanm	0:9b334a45a8ff	633	switch (Channel)
bogdanm	0:9b334a45a8ff	634	{
bogdanm	0:9b334a45a8ff	635	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	636	{
bogdanm	0:9b334a45a8ff	637	/* Disable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	638	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	639	}
bogdanm	0:9b334a45a8ff	640	break;
bogdanm	0:9b334a45a8ff	641
bogdanm	0:9b334a45a8ff	642	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	643	{
bogdanm	0:9b334a45a8ff	644	/* Disable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	645	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	646	}
bogdanm	0:9b334a45a8ff	647	break;
bogdanm	0:9b334a45a8ff	648
bogdanm	0:9b334a45a8ff	649	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	650	{
bogdanm	0:9b334a45a8ff	651	/* Disable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	652	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	653	}
bogdanm	0:9b334a45a8ff	654	break;
bogdanm	0:9b334a45a8ff	655
bogdanm	0:9b334a45a8ff	656	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	657	{
bogdanm	0:9b334a45a8ff	658	/* Disable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	659	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	660	}
bogdanm	0:9b334a45a8ff	661	break;
bogdanm	0:9b334a45a8ff	662
bogdanm	0:9b334a45a8ff	663	default:
bogdanm	0:9b334a45a8ff	664	break;
bogdanm	0:9b334a45a8ff	665	}
bogdanm	0:9b334a45a8ff	666
bogdanm	0:9b334a45a8ff	667	/* Disable the Capture compare channel N */
bogdanm	0:9b334a45a8ff	668	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	669
bogdanm	0:9b334a45a8ff	670	/* Disable the TIM Break interrupt (only if no more channel is active) */
bogdanm	0:9b334a45a8ff	671	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	672	if ((tmpccer & (TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE)) == RESET)
bogdanm	0:9b334a45a8ff	673	{
bogdanm	0:9b334a45a8ff	674	__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	675	}
bogdanm	0:9b334a45a8ff	676
bogdanm	0:9b334a45a8ff	677	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	678	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	679
bogdanm	0:9b334a45a8ff	680	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	681	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	682
bogdanm	0:9b334a45a8ff	683	/* Return function status */
bogdanm	0:9b334a45a8ff	684	return HAL_OK;
bogdanm	0:9b334a45a8ff	685	}
bogdanm	0:9b334a45a8ff	686
bogdanm	0:9b334a45a8ff	687	/**
bogdanm	0:9b334a45a8ff	688	* @brief Starts the TIM Output Compare signal generation in DMA mode
bogdanm	0:9b334a45a8ff	689	* on the complementary output.
bogdanm	0:9b334a45a8ff	690	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	691	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	692	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	693	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	694	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	695	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	696	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	697	* @param pData : The source Buffer address.
bogdanm	0:9b334a45a8ff	698	* @param Length : The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	699	* @retval HAL status
bogdanm	0:9b334a45a8ff	700	*/
bogdanm	0:9b334a45a8ff	701	HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	702	{
bogdanm	0:9b334a45a8ff	703	/* Check the parameters */
bogdanm	0:9b334a45a8ff	704	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	705
bogdanm	0:9b334a45a8ff	706	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	707	{
bogdanm	0:9b334a45a8ff	708	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	709	}
bogdanm	0:9b334a45a8ff	710	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	713	{
bogdanm	0:9b334a45a8ff	714	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	715	}
bogdanm	0:9b334a45a8ff	716	else
bogdanm	0:9b334a45a8ff	717	{
bogdanm	0:9b334a45a8ff	718	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	719	}
bogdanm	0:9b334a45a8ff	720	}
bogdanm	0:9b334a45a8ff	721	switch (Channel)
bogdanm	0:9b334a45a8ff	722	{
bogdanm	0:9b334a45a8ff	723	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	724	{
bogdanm	0:9b334a45a8ff	725	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	726	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	727
bogdanm	0:9b334a45a8ff	728	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	729	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	732	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	733
bogdanm	0:9b334a45a8ff	734	/* Enable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	735	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	736	}
bogdanm	0:9b334a45a8ff	737	break;
bogdanm	0:9b334a45a8ff	738
bogdanm	0:9b334a45a8ff	739	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	740	{
bogdanm	0:9b334a45a8ff	741	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	742	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	745	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	746
bogdanm	0:9b334a45a8ff	747	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	748	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	749
bogdanm	0:9b334a45a8ff	750	/* Enable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	751	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	752	}
bogdanm	0:9b334a45a8ff	753	break;
bogdanm	0:9b334a45a8ff	754
bogdanm	0:9b334a45a8ff	755	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	756	{
bogdanm	0:9b334a45a8ff	757	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	758	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	761	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	762
bogdanm	0:9b334a45a8ff	763	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	764	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	765
bogdanm	0:9b334a45a8ff	766	/* Enable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	767	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	768	}
bogdanm	0:9b334a45a8ff	769	break;
bogdanm	0:9b334a45a8ff	770
bogdanm	0:9b334a45a8ff	771	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	772	{
bogdanm	0:9b334a45a8ff	773	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	774	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	775
bogdanm	0:9b334a45a8ff	776	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	777	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	778
bogdanm	0:9b334a45a8ff	779	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	780	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	781
bogdanm	0:9b334a45a8ff	782	/* Enable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	783	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	784	}
bogdanm	0:9b334a45a8ff	785	break;
bogdanm	0:9b334a45a8ff	786
bogdanm	0:9b334a45a8ff	787	default:
bogdanm	0:9b334a45a8ff	788	break;
bogdanm	0:9b334a45a8ff	789	}
bogdanm	0:9b334a45a8ff	790
bogdanm	0:9b334a45a8ff	791	/* Enable the Capture compare channel N */
bogdanm	0:9b334a45a8ff	792	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	793
bogdanm	0:9b334a45a8ff	794	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	795	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	798	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	/* Return function status */
bogdanm	0:9b334a45a8ff	801	return HAL_OK;
bogdanm	0:9b334a45a8ff	802	}
bogdanm	0:9b334a45a8ff	803
bogdanm	0:9b334a45a8ff	804	/**
bogdanm	0:9b334a45a8ff	805	* @brief Stops the TIM Output Compare signal generation in DMA mode
bogdanm	0:9b334a45a8ff	806	* on the complementary output.
bogdanm	0:9b334a45a8ff	807	* @param htim : TIM Output Compare handle
bogdanm	0:9b334a45a8ff	808	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	809	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	810	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	811	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	812	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	813	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	814	* @retval HAL status
bogdanm	0:9b334a45a8ff	815	*/
bogdanm	0:9b334a45a8ff	816	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	817	{
bogdanm	0:9b334a45a8ff	818	/* Check the parameters */
bogdanm	0:9b334a45a8ff	819	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	switch (Channel)
bogdanm	0:9b334a45a8ff	822	{
bogdanm	0:9b334a45a8ff	823	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	824	{
bogdanm	0:9b334a45a8ff	825	/* Disable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	826	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	827	}
bogdanm	0:9b334a45a8ff	828	break;
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	831	{
bogdanm	0:9b334a45a8ff	832	/* Disable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	833	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	834	}
bogdanm	0:9b334a45a8ff	835	break;
bogdanm	0:9b334a45a8ff	836
bogdanm	0:9b334a45a8ff	837	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	838	{
bogdanm	0:9b334a45a8ff	839	/* Disable the TIM Output Compare DMA request */
bogdanm	0:9b334a45a8ff	840	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	841	}
bogdanm	0:9b334a45a8ff	842	break;
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	845	{
bogdanm	0:9b334a45a8ff	846	/* Disable the TIM Output Compare interrupt */
bogdanm	0:9b334a45a8ff	847	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	848	}
bogdanm	0:9b334a45a8ff	849	break;
bogdanm	0:9b334a45a8ff	850
bogdanm	0:9b334a45a8ff	851	default:
bogdanm	0:9b334a45a8ff	852	break;
bogdanm	0:9b334a45a8ff	853	}
bogdanm	0:9b334a45a8ff	854
bogdanm	0:9b334a45a8ff	855	/* Disable the Capture compare channel N */
bogdanm	0:9b334a45a8ff	856	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	859	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	860
bogdanm	0:9b334a45a8ff	861	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	862	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	863
bogdanm	0:9b334a45a8ff	864	/* Change the htim state */
bogdanm	0:9b334a45a8ff	865	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	866
bogdanm	0:9b334a45a8ff	867	/* Return function status */
bogdanm	0:9b334a45a8ff	868	return HAL_OK;
bogdanm	0:9b334a45a8ff	869	}
bogdanm	0:9b334a45a8ff	870
bogdanm	0:9b334a45a8ff	871	/**
bogdanm	0:9b334a45a8ff	872	* @}
bogdanm	0:9b334a45a8ff	873	*/
bogdanm	0:9b334a45a8ff	874
bogdanm	0:9b334a45a8ff	875	/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
bogdanm	0:9b334a45a8ff	876	* @brief Timer Complementary PWM functions
bogdanm	0:9b334a45a8ff	877	*
bogdanm	0:9b334a45a8ff	878	@verbatim
bogdanm	0:9b334a45a8ff	879	==============================================================================
bogdanm	0:9b334a45a8ff	880	##### Timer Complementary PWM functions #####
bogdanm	0:9b334a45a8ff	881	==============================================================================
bogdanm	0:9b334a45a8ff	882	[..]
bogdanm	0:9b334a45a8ff	883	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	884	(+) Start the Complementary PWM.
bogdanm	0:9b334a45a8ff	885	(+) Stop the Complementary PWM.
bogdanm	0:9b334a45a8ff	886	(+) Start the Complementary PWM and enable interrupts.
bogdanm	0:9b334a45a8ff	887	(+) Stop the Complementary PWM and disable interrupts.
bogdanm	0:9b334a45a8ff	888	(+) Start the Complementary PWM and enable DMA transfers.
bogdanm	0:9b334a45a8ff	889	(+) Stop the Complementary PWM and disable DMA transfers.
bogdanm	0:9b334a45a8ff	890	(+) Start the Complementary Input Capture measurement.
bogdanm	0:9b334a45a8ff	891	(+) Stop the Complementary Input Capture.
bogdanm	0:9b334a45a8ff	892	(+) Start the Complementary Input Capture and enable interrupts.
bogdanm	0:9b334a45a8ff	893	(+) Stop the Complementary Input Capture and disable interrupts.
bogdanm	0:9b334a45a8ff	894	(+) Start the Complementary Input Capture and enable DMA transfers.
bogdanm	0:9b334a45a8ff	895	(+) Stop the Complementary Input Capture and disable DMA transfers.
bogdanm	0:9b334a45a8ff	896	(+) Start the Complementary One Pulse generation.
bogdanm	0:9b334a45a8ff	897	(+) Stop the Complementary One Pulse.
bogdanm	0:9b334a45a8ff	898	(+) Start the Complementary One Pulse and enable interrupts.
bogdanm	0:9b334a45a8ff	899	(+) Stop the Complementary One Pulse and disable interrupts.
bogdanm	0:9b334a45a8ff	900
bogdanm	0:9b334a45a8ff	901	@endverbatim
bogdanm	0:9b334a45a8ff	902	* @{
bogdanm	0:9b334a45a8ff	903	*/
bogdanm	0:9b334a45a8ff	904
bogdanm	0:9b334a45a8ff	905	/**
bogdanm	0:9b334a45a8ff	906	* @brief Starts the PWM signal generation on the complementary output.
bogdanm	0:9b334a45a8ff	907	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	908	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	909	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	910	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	911	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	912	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	913	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	914	* @retval HAL status
bogdanm	0:9b334a45a8ff	915	*/
bogdanm	0:9b334a45a8ff	916	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	917	{
bogdanm	0:9b334a45a8ff	918	/* Check the parameters */
bogdanm	0:9b334a45a8ff	919	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	920
bogdanm	0:9b334a45a8ff	921	/* Enable the complementary PWM output */
bogdanm	0:9b334a45a8ff	922	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	923
bogdanm	0:9b334a45a8ff	924	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	925	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	926
bogdanm	0:9b334a45a8ff	927	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	928	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	929
bogdanm	0:9b334a45a8ff	930	/* Return function status */
bogdanm	0:9b334a45a8ff	931	return HAL_OK;
bogdanm	0:9b334a45a8ff	932	}
bogdanm	0:9b334a45a8ff	933
bogdanm	0:9b334a45a8ff	934	/**
bogdanm	0:9b334a45a8ff	935	* @brief Stops the PWM signal generation on the complementary output.
bogdanm	0:9b334a45a8ff	936	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	937	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	938	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	939	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	940	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	941	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	942	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	943	* @retval HAL status
bogdanm	0:9b334a45a8ff	944	*/
bogdanm	0:9b334a45a8ff	945	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	946	{
bogdanm	0:9b334a45a8ff	947	/* Check the parameters */
bogdanm	0:9b334a45a8ff	948	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950	/* Disable the complementary PWM output */
bogdanm	0:9b334a45a8ff	951	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	952
bogdanm	0:9b334a45a8ff	953	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	954	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	957	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	/* Return function status */
bogdanm	0:9b334a45a8ff	960	return HAL_OK;
bogdanm	0:9b334a45a8ff	961	}
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	/**
bogdanm	0:9b334a45a8ff	964	* @brief Starts the PWM signal generation in interrupt mode on the
bogdanm	0:9b334a45a8ff	965	* complementary output.
bogdanm	0:9b334a45a8ff	966	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	967	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	968	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	969	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	970	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	971	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	972	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	973	* @retval HAL status
bogdanm	0:9b334a45a8ff	974	*/
bogdanm	0:9b334a45a8ff	975	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	976	{
bogdanm	0:9b334a45a8ff	977	/* Check the parameters */
bogdanm	0:9b334a45a8ff	978	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	979
bogdanm	0:9b334a45a8ff	980	switch (Channel)
bogdanm	0:9b334a45a8ff	981	{
bogdanm	0:9b334a45a8ff	982	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	983	{
bogdanm	0:9b334a45a8ff	984	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	985	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	986	}
bogdanm	0:9b334a45a8ff	987	break;
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	990	{
bogdanm	0:9b334a45a8ff	991	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	992	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	993	}
bogdanm	0:9b334a45a8ff	994	break;
bogdanm	0:9b334a45a8ff	995
bogdanm	0:9b334a45a8ff	996	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	997	{
bogdanm	0:9b334a45a8ff	998	/* Enable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	999	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1000	}
bogdanm	0:9b334a45a8ff	1001	break;
bogdanm	0:9b334a45a8ff	1002
bogdanm	0:9b334a45a8ff	1003	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1004	{
bogdanm	0:9b334a45a8ff	1005	/* Enable the TIM Capture/Compare 4 interrupt */
bogdanm	0:9b334a45a8ff	1006	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1007	}
bogdanm	0:9b334a45a8ff	1008	break;
bogdanm	0:9b334a45a8ff	1009
bogdanm	0:9b334a45a8ff	1010	default:
bogdanm	0:9b334a45a8ff	1011	break;
bogdanm	0:9b334a45a8ff	1012	}
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	/* Enable the TIM Break interrupt */
bogdanm	0:9b334a45a8ff	1015	__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	1016
bogdanm	0:9b334a45a8ff	1017	/* Enable the complementary PWM output */
bogdanm	0:9b334a45a8ff	1018	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	1021	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1024	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/* Return function status */
bogdanm	0:9b334a45a8ff	1027	return HAL_OK;
bogdanm	0:9b334a45a8ff	1028	}
bogdanm	0:9b334a45a8ff	1029
bogdanm	0:9b334a45a8ff	1030	/**
bogdanm	0:9b334a45a8ff	1031	* @brief Stops the PWM signal generation in interrupt mode on the
bogdanm	0:9b334a45a8ff	1032	* complementary output.
bogdanm	0:9b334a45a8ff	1033	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1034	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1035	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1036	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1037	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1038	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1039	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1040	* @retval HAL status
bogdanm	0:9b334a45a8ff	1041	*/
bogdanm	0:9b334a45a8ff	1042	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1043	{
bogdanm	0:9b334a45a8ff	1044	uint32_t tmpccer = 0;
bogdanm	0:9b334a45a8ff	1045
bogdanm	0:9b334a45a8ff	1046	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1047	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	switch (Channel)
bogdanm	0:9b334a45a8ff	1050	{
bogdanm	0:9b334a45a8ff	1051	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1052	{
bogdanm	0:9b334a45a8ff	1053	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1054	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1055	}
bogdanm	0:9b334a45a8ff	1056	break;
bogdanm	0:9b334a45a8ff	1057
bogdanm	0:9b334a45a8ff	1058	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1059	{
bogdanm	0:9b334a45a8ff	1060	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1061	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1062	}
bogdanm	0:9b334a45a8ff	1063	break;
bogdanm	0:9b334a45a8ff	1064
bogdanm	0:9b334a45a8ff	1065	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1066	{
bogdanm	0:9b334a45a8ff	1067	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1068	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
bogdanm	0:9b334a45a8ff	1069	}
bogdanm	0:9b334a45a8ff	1070	break;
bogdanm	0:9b334a45a8ff	1071
bogdanm	0:9b334a45a8ff	1072	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1073	{
bogdanm	0:9b334a45a8ff	1074	/* Disable the TIM Capture/Compare 3 interrupt */
bogdanm	0:9b334a45a8ff	1075	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
bogdanm	0:9b334a45a8ff	1076	}
bogdanm	0:9b334a45a8ff	1077	break;
bogdanm	0:9b334a45a8ff	1078
bogdanm	0:9b334a45a8ff	1079	default:
bogdanm	0:9b334a45a8ff	1080	break;
bogdanm	0:9b334a45a8ff	1081	}
bogdanm	0:9b334a45a8ff	1082
bogdanm	0:9b334a45a8ff	1083	/* Disable the complementary PWM output */
bogdanm	0:9b334a45a8ff	1084	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	1085
bogdanm	0:9b334a45a8ff	1086	/* Disable the TIM Break interrupt (only if no more channel is active) */
bogdanm	0:9b334a45a8ff	1087	tmpccer = htim->Instance->CCER;
bogdanm	0:9b334a45a8ff	1088	if ((tmpccer & (TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE)) == RESET)
bogdanm	0:9b334a45a8ff	1089	{
bogdanm	0:9b334a45a8ff	1090	__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
bogdanm	0:9b334a45a8ff	1091	}
bogdanm	0:9b334a45a8ff	1092
bogdanm	0:9b334a45a8ff	1093	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1094	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1095
bogdanm	0:9b334a45a8ff	1096	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1097	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	/* Return function status */
bogdanm	0:9b334a45a8ff	1100	return HAL_OK;
bogdanm	0:9b334a45a8ff	1101	}
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	/**
bogdanm	0:9b334a45a8ff	1104	* @brief Starts the TIM PWM signal generation in DMA mode on the
bogdanm	0:9b334a45a8ff	1105	* complementary output
bogdanm	0:9b334a45a8ff	1106	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1107	* @param Channel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	1108	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1109	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1110	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1111	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1112	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1113	* @param pData : The source Buffer address.
bogdanm	0:9b334a45a8ff	1114	* @param Length : The length of data to be transferred from memory to TIM peripheral
bogdanm	0:9b334a45a8ff	1115	* @retval HAL status
bogdanm	0:9b334a45a8ff	1116	*/
bogdanm	0:9b334a45a8ff	1117	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
bogdanm	0:9b334a45a8ff	1118	{
bogdanm	0:9b334a45a8ff	1119	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1120	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1121
bogdanm	0:9b334a45a8ff	1122	if((htim->State == HAL_TIM_STATE_BUSY))
bogdanm	0:9b334a45a8ff	1123	{
bogdanm	0:9b334a45a8ff	1124	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1125	}
bogdanm	0:9b334a45a8ff	1126	else if((htim->State == HAL_TIM_STATE_READY))
bogdanm	0:9b334a45a8ff	1127	{
bogdanm	0:9b334a45a8ff	1128	if(((uint32_t)pData == 0 ) && (Length > 0))
bogdanm	0:9b334a45a8ff	1129	{
bogdanm	0:9b334a45a8ff	1130	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1131	}
bogdanm	0:9b334a45a8ff	1132	else
bogdanm	0:9b334a45a8ff	1133	{
bogdanm	0:9b334a45a8ff	1134	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1135	}
bogdanm	0:9b334a45a8ff	1136	}
bogdanm	0:9b334a45a8ff	1137	switch (Channel)
bogdanm	0:9b334a45a8ff	1138	{
bogdanm	0:9b334a45a8ff	1139	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1140	{
bogdanm	0:9b334a45a8ff	1141	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1142	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1143
bogdanm	0:9b334a45a8ff	1144	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1145	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1146
bogdanm	0:9b334a45a8ff	1147	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1148	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
bogdanm	0:9b334a45a8ff	1149
bogdanm	0:9b334a45a8ff	1150	/* Enable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1151	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1152	}
bogdanm	0:9b334a45a8ff	1153	break;
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1156	{
bogdanm	0:9b334a45a8ff	1157	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1158	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1159
bogdanm	0:9b334a45a8ff	1160	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1161	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1162
bogdanm	0:9b334a45a8ff	1163	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1164	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
bogdanm	0:9b334a45a8ff	1165
bogdanm	0:9b334a45a8ff	1166	/* Enable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1167	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1168	}
bogdanm	0:9b334a45a8ff	1169	break;
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1172	{
bogdanm	0:9b334a45a8ff	1173	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1174	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1177	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1178
bogdanm	0:9b334a45a8ff	1179	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1180	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	/* Enable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1183	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1184	}
bogdanm	0:9b334a45a8ff	1185	break;
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1188	{
bogdanm	0:9b334a45a8ff	1189	/* Set the DMA Period elapsed callback */
bogdanm	0:9b334a45a8ff	1190	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
bogdanm	0:9b334a45a8ff	1191
bogdanm	0:9b334a45a8ff	1192	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1193	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
bogdanm	0:9b334a45a8ff	1194
bogdanm	0:9b334a45a8ff	1195	/* Enable the DMA channel */
bogdanm	0:9b334a45a8ff	1196	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
bogdanm	0:9b334a45a8ff	1197
bogdanm	0:9b334a45a8ff	1198	/* Enable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1199	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1200	}
bogdanm	0:9b334a45a8ff	1201	break;
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	default:
bogdanm	0:9b334a45a8ff	1204	break;
bogdanm	0:9b334a45a8ff	1205	}
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	/* Enable the complementary PWM output */
bogdanm	0:9b334a45a8ff	1208	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	1211	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1214	__HAL_TIM_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1215
bogdanm	0:9b334a45a8ff	1216	/* Return function status */
bogdanm	0:9b334a45a8ff	1217	return HAL_OK;
bogdanm	0:9b334a45a8ff	1218	}
bogdanm	0:9b334a45a8ff	1219
bogdanm	0:9b334a45a8ff	1220	/**
bogdanm	0:9b334a45a8ff	1221	* @brief Stops the TIM PWM signal generation in DMA mode on the complementary
bogdanm	0:9b334a45a8ff	1222	* output
bogdanm	0:9b334a45a8ff	1223	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1224	* @param Channel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1225	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1226	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1227	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1228	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	0:9b334a45a8ff	1229	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	0:9b334a45a8ff	1230	* @retval HAL status
bogdanm	0:9b334a45a8ff	1231	*/
bogdanm	0:9b334a45a8ff	1232	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
bogdanm	0:9b334a45a8ff	1233	{
bogdanm	0:9b334a45a8ff	1234	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1235	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	switch (Channel)
bogdanm	0:9b334a45a8ff	1238	{
bogdanm	0:9b334a45a8ff	1239	case TIM_CHANNEL_1:
bogdanm	0:9b334a45a8ff	1240	{
bogdanm	0:9b334a45a8ff	1241	/* Disable the TIM Capture/Compare 1 DMA request */
bogdanm	0:9b334a45a8ff	1242	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
bogdanm	0:9b334a45a8ff	1243	}
bogdanm	0:9b334a45a8ff	1244	break;
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	case TIM_CHANNEL_2:
bogdanm	0:9b334a45a8ff	1247	{
bogdanm	0:9b334a45a8ff	1248	/* Disable the TIM Capture/Compare 2 DMA request */
bogdanm	0:9b334a45a8ff	1249	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
bogdanm	0:9b334a45a8ff	1250	}
bogdanm	0:9b334a45a8ff	1251	break;
bogdanm	0:9b334a45a8ff	1252
bogdanm	0:9b334a45a8ff	1253	case TIM_CHANNEL_3:
bogdanm	0:9b334a45a8ff	1254	{
bogdanm	0:9b334a45a8ff	1255	/* Disable the TIM Capture/Compare 3 DMA request */
bogdanm	0:9b334a45a8ff	1256	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
bogdanm	0:9b334a45a8ff	1257	}
bogdanm	0:9b334a45a8ff	1258	break;
bogdanm	0:9b334a45a8ff	1259
bogdanm	0:9b334a45a8ff	1260	case TIM_CHANNEL_4:
bogdanm	0:9b334a45a8ff	1261	{
bogdanm	0:9b334a45a8ff	1262	/* Disable the TIM Capture/Compare 4 DMA request */
bogdanm	0:9b334a45a8ff	1263	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
bogdanm	0:9b334a45a8ff	1264	}
bogdanm	0:9b334a45a8ff	1265	break;
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267	default:
bogdanm	0:9b334a45a8ff	1268	break;
bogdanm	0:9b334a45a8ff	1269	}
bogdanm	0:9b334a45a8ff	1270
bogdanm	0:9b334a45a8ff	1271	/* Disable the complementary PWM output */
bogdanm	0:9b334a45a8ff	1272	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1275	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1276
bogdanm	0:9b334a45a8ff	1277	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1278	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/* Change the htim state */
bogdanm	0:9b334a45a8ff	1281	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1282
bogdanm	0:9b334a45a8ff	1283	/* Return function status */
bogdanm	0:9b334a45a8ff	1284	return HAL_OK;
bogdanm	0:9b334a45a8ff	1285	}
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	/**
bogdanm	0:9b334a45a8ff	1288	* @}
bogdanm	0:9b334a45a8ff	1289	*/
bogdanm	0:9b334a45a8ff	1290
bogdanm	0:9b334a45a8ff	1291	/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
bogdanm	0:9b334a45a8ff	1292	* @brief Timer Complementary One Pulse functions
bogdanm	0:9b334a45a8ff	1293	*
bogdanm	0:9b334a45a8ff	1294	@verbatim
bogdanm	0:9b334a45a8ff	1295	==============================================================================
bogdanm	0:9b334a45a8ff	1296	##### Timer Complementary One Pulse functions #####
bogdanm	0:9b334a45a8ff	1297	==============================================================================
bogdanm	0:9b334a45a8ff	1298	[..]
bogdanm	0:9b334a45a8ff	1299	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1300	(+) Start the Complementary One Pulse generation.
bogdanm	0:9b334a45a8ff	1301	(+) Stop the Complementary One Pulse.
bogdanm	0:9b334a45a8ff	1302	(+) Start the Complementary One Pulse and enable interrupts.
bogdanm	0:9b334a45a8ff	1303	(+) Stop the Complementary One Pulse and disable interrupts.
bogdanm	0:9b334a45a8ff	1304
bogdanm	0:9b334a45a8ff	1305	@endverbatim
bogdanm	0:9b334a45a8ff	1306	* @{
bogdanm	0:9b334a45a8ff	1307	*/
bogdanm	0:9b334a45a8ff	1308
bogdanm	0:9b334a45a8ff	1309	/**
bogdanm	0:9b334a45a8ff	1310	* @brief Starts the TIM One Pulse signal generation on the complemetary
bogdanm	0:9b334a45a8ff	1311	* output.
bogdanm	0:9b334a45a8ff	1312	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	1313	* @param OutputChannel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	1314	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1315	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1316	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1317	* @retval HAL status
bogdanm	0:9b334a45a8ff	1318	*/
bogdanm	0:9b334a45a8ff	1319	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	1320	{
bogdanm	0:9b334a45a8ff	1321	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1322	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm	0:9b334a45a8ff	1323
bogdanm	0:9b334a45a8ff	1324	/* Enable the complementary One Pulse output */
bogdanm	0:9b334a45a8ff	1325	TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	1328	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1329
bogdanm	0:9b334a45a8ff	1330	/* Return function status */
bogdanm	0:9b334a45a8ff	1331	return HAL_OK;
bogdanm	0:9b334a45a8ff	1332	}
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	/**
bogdanm	0:9b334a45a8ff	1335	* @brief Stops the TIM One Pulse signal generation on the complementary
bogdanm	0:9b334a45a8ff	1336	* output.
bogdanm	0:9b334a45a8ff	1337	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	1338	* @param OutputChannel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1339	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1340	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1341	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1342	* @retval HAL status
bogdanm	0:9b334a45a8ff	1343	*/
bogdanm	0:9b334a45a8ff	1344	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	1345	{
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1348	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm	0:9b334a45a8ff	1349
bogdanm	0:9b334a45a8ff	1350	/* Disable the complementary One Pulse output */
bogdanm	0:9b334a45a8ff	1351	TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	1352
bogdanm	0:9b334a45a8ff	1353	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1354	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1355
bogdanm	0:9b334a45a8ff	1356	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1357	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1358
bogdanm	0:9b334a45a8ff	1359	/* Return function status */
bogdanm	0:9b334a45a8ff	1360	return HAL_OK;
bogdanm	0:9b334a45a8ff	1361	}
bogdanm	0:9b334a45a8ff	1362
bogdanm	0:9b334a45a8ff	1363	/**
bogdanm	0:9b334a45a8ff	1364	* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
bogdanm	0:9b334a45a8ff	1365	* complementary channel.
bogdanm	0:9b334a45a8ff	1366	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	1367	* @param OutputChannel : TIM Channel to be enabled
bogdanm	0:9b334a45a8ff	1368	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1369	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1370	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1371	* @retval HAL status
bogdanm	0:9b334a45a8ff	1372	*/
bogdanm	0:9b334a45a8ff	1373	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	1374	{
bogdanm	0:9b334a45a8ff	1375	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1376	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm	0:9b334a45a8ff	1377
bogdanm	0:9b334a45a8ff	1378	/* Enable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1379	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1380
bogdanm	0:9b334a45a8ff	1381	/* Enable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1382	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1383
bogdanm	0:9b334a45a8ff	1384	/* Enable the complementary One Pulse output */
bogdanm	0:9b334a45a8ff	1385	TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	/* Enable the Main Ouput */
bogdanm	0:9b334a45a8ff	1388	__HAL_TIM_MOE_ENABLE(htim);
bogdanm	0:9b334a45a8ff	1389
bogdanm	0:9b334a45a8ff	1390	/* Return function status */
bogdanm	0:9b334a45a8ff	1391	return HAL_OK;
bogdanm	0:9b334a45a8ff	1392	}
bogdanm	0:9b334a45a8ff	1393
bogdanm	0:9b334a45a8ff	1394	/**
bogdanm	0:9b334a45a8ff	1395	* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
bogdanm	0:9b334a45a8ff	1396	* complementary channel.
bogdanm	0:9b334a45a8ff	1397	* @param htim : TIM One Pulse handle
bogdanm	0:9b334a45a8ff	1398	* @param OutputChannel : TIM Channel to be disabled
bogdanm	0:9b334a45a8ff	1399	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1400	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	0:9b334a45a8ff	1401	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	0:9b334a45a8ff	1402	* @retval HAL status
bogdanm	0:9b334a45a8ff	1403	*/
bogdanm	0:9b334a45a8ff	1404	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
bogdanm	0:9b334a45a8ff	1405	{
bogdanm	0:9b334a45a8ff	1406	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1407	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	/* Disable the TIM Capture/Compare 1 interrupt */
bogdanm	0:9b334a45a8ff	1410	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
bogdanm	0:9b334a45a8ff	1411
bogdanm	0:9b334a45a8ff	1412	/* Disable the TIM Capture/Compare 2 interrupt */
bogdanm	0:9b334a45a8ff	1413	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	/* Disable the complementary One Pulse output */
bogdanm	0:9b334a45a8ff	1416	TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
bogdanm	0:9b334a45a8ff	1417
bogdanm	0:9b334a45a8ff	1418	/* Disable the Main Ouput */
bogdanm	0:9b334a45a8ff	1419	__HAL_TIM_MOE_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	1422	__HAL_TIM_DISABLE(htim);
bogdanm	0:9b334a45a8ff	1423
bogdanm	0:9b334a45a8ff	1424	/* Return function status */
bogdanm	0:9b334a45a8ff	1425	return HAL_OK;
bogdanm	0:9b334a45a8ff	1426	}
bogdanm	0:9b334a45a8ff	1427
bogdanm	0:9b334a45a8ff	1428	/**
bogdanm	0:9b334a45a8ff	1429	* @}
bogdanm	0:9b334a45a8ff	1430	*/
bogdanm	0:9b334a45a8ff	1431
bogdanm	0:9b334a45a8ff	1432	#endif /* defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| */
bogdanm	0:9b334a45a8ff	1433	/* defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| */
bogdanm	0:9b334a45a8ff	1434	/* defined(STM32F105xC) \|\| defined(STM32F107xC) */
bogdanm	0:9b334a45a8ff	1435
bogdanm	0:9b334a45a8ff	1436	/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1437	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	1438	*
bogdanm	0:9b334a45a8ff	1439	@verbatim
bogdanm	0:9b334a45a8ff	1440	==============================================================================
bogdanm	0:9b334a45a8ff	1441	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	1442	==============================================================================
bogdanm	0:9b334a45a8ff	1443	[..]
bogdanm	0:9b334a45a8ff	1444	This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1445	(+) Configure the commutation event in case of use of the Hall sensor interface.
bogdanm	0:9b334a45a8ff	1446	(+) Configure Complementary channels, break features and dead time.
bogdanm	0:9b334a45a8ff	1447	(+) Configure Master synchronization.
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	@endverbatim
bogdanm	0:9b334a45a8ff	1450	* @{
bogdanm	0:9b334a45a8ff	1451	*/
bogdanm	0:9b334a45a8ff	1452
bogdanm	0:9b334a45a8ff	1453	#if defined (STM32F100xB) \|\| defined (STM32F100xE) \|\| \
bogdanm	0:9b334a45a8ff	1454	defined (STM32F103x6) \|\| defined (STM32F103xB) \|\| defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| \
bogdanm	0:9b334a45a8ff	1455	defined (STM32F105xC) \|\| defined (STM32F107xC)
bogdanm	0:9b334a45a8ff	1456
bogdanm	0:9b334a45a8ff	1457	/**
bogdanm	0:9b334a45a8ff	1458	* @brief Configure the TIM commutation event sequence.
bogdanm	0:9b334a45a8ff	1459	* @note: this function is mandatory to use the commutation event in order to
bogdanm	0:9b334a45a8ff	1460	* update the configuration at each commutation detection on the TRGI input of the Timer,
bogdanm	0:9b334a45a8ff	1461	* the typical use of this feature is with the use of another Timer(interface Timer)
bogdanm	0:9b334a45a8ff	1462	* configured in Hall sensor interface, this interface Timer will generate the
bogdanm	0:9b334a45a8ff	1463	* commutation at its TRGO output (connected to Timer used in this function) each time
bogdanm	0:9b334a45a8ff	1464	* the TI1 of the Interface Timer detect a commutation at its input TI1.
bogdanm	0:9b334a45a8ff	1465	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1466	* @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
bogdanm	0:9b334a45a8ff	1467	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1468	* @arg TIM_TS_ITR0: Internal trigger 0 selected
bogdanm	0:9b334a45a8ff	1469	* @arg TIM_TS_ITR1: Internal trigger 1 selected
bogdanm	0:9b334a45a8ff	1470	* @arg TIM_TS_ITR2: Internal trigger 2 selected
bogdanm	0:9b334a45a8ff	1471	* @arg TIM_TS_ITR3: Internal trigger 3 selected
bogdanm	0:9b334a45a8ff	1472	* @arg TIM_TS_NONE: No trigger is needed
bogdanm	0:9b334a45a8ff	1473	* @param CommutationSource : the Commutation Event source
bogdanm	0:9b334a45a8ff	1474	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1475	* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
bogdanm	0:9b334a45a8ff	1476	* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
bogdanm	0:9b334a45a8ff	1477	* @retval HAL status
bogdanm	0:9b334a45a8ff	1478	*/
bogdanm	0:9b334a45a8ff	1479	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
bogdanm	0:9b334a45a8ff	1480	{
bogdanm	0:9b334a45a8ff	1481	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1482	assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1483	assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
bogdanm	0:9b334a45a8ff	1484
bogdanm	0:9b334a45a8ff	1485	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	1486
bogdanm	0:9b334a45a8ff	1487	if ((InputTrigger == TIM_TS_ITR0) \|\| (InputTrigger == TIM_TS_ITR1) \|\|
bogdanm	0:9b334a45a8ff	1488	(InputTrigger == TIM_TS_ITR2) \|\| (InputTrigger == TIM_TS_ITR3))
bogdanm	0:9b334a45a8ff	1489	{
bogdanm	0:9b334a45a8ff	1490	/* Select the Input trigger */
bogdanm	0:9b334a45a8ff	1491	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	1492	htim->Instance->SMCR \|= InputTrigger;
bogdanm	0:9b334a45a8ff	1493	}
bogdanm	0:9b334a45a8ff	1494
bogdanm	0:9b334a45a8ff	1495	/* Select the Capture Compare preload feature */
bogdanm	0:9b334a45a8ff	1496	htim->Instance->CR2 \|= TIM_CR2_CCPC;
bogdanm	0:9b334a45a8ff	1497	/* Select the Commutation event source */
bogdanm	0:9b334a45a8ff	1498	htim->Instance->CR2 &= ~TIM_CR2_CCUS;
bogdanm	0:9b334a45a8ff	1499	htim->Instance->CR2 \|= CommutationSource;
bogdanm	0:9b334a45a8ff	1500
bogdanm	0:9b334a45a8ff	1501	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1502
bogdanm	0:9b334a45a8ff	1503	return HAL_OK;
bogdanm	0:9b334a45a8ff	1504	}
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	/**
bogdanm	0:9b334a45a8ff	1507	* @brief Configure the TIM commutation event sequence with interrupt.
bogdanm	0:9b334a45a8ff	1508	* @note: this function is mandatory to use the commutation event in order to
bogdanm	0:9b334a45a8ff	1509	* update the configuration at each commutation detection on the TRGI input of the Timer,
bogdanm	0:9b334a45a8ff	1510	* the typical use of this feature is with the use of another Timer(interface Timer)
bogdanm	0:9b334a45a8ff	1511	* configured in Hall sensor interface, this interface Timer will generate the
bogdanm	0:9b334a45a8ff	1512	* commutation at its TRGO output (connected to Timer used in this function) each time
bogdanm	0:9b334a45a8ff	1513	* the TI1 of the Interface Timer detect a commutation at its input TI1.
bogdanm	0:9b334a45a8ff	1514	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1515	* @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
bogdanm	0:9b334a45a8ff	1516	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1517	* @arg TIM_TS_ITR0: Internal trigger 0 selected
bogdanm	0:9b334a45a8ff	1518	* @arg TIM_TS_ITR1: Internal trigger 1 selected
bogdanm	0:9b334a45a8ff	1519	* @arg TIM_TS_ITR2: Internal trigger 2 selected
bogdanm	0:9b334a45a8ff	1520	* @arg TIM_TS_ITR3: Internal trigger 3 selected
bogdanm	0:9b334a45a8ff	1521	* @arg TIM_TS_NONE: No trigger is needed
bogdanm	0:9b334a45a8ff	1522	* @param CommutationSource : the Commutation Event source
bogdanm	0:9b334a45a8ff	1523	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1524	* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
bogdanm	0:9b334a45a8ff	1525	* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
bogdanm	0:9b334a45a8ff	1526	* @retval HAL status
bogdanm	0:9b334a45a8ff	1527	*/
bogdanm	0:9b334a45a8ff	1528	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
bogdanm	0:9b334a45a8ff	1529	{
bogdanm	0:9b334a45a8ff	1530	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1531	assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1532	assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
bogdanm	0:9b334a45a8ff	1533
bogdanm	0:9b334a45a8ff	1534	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	1535
bogdanm	0:9b334a45a8ff	1536	if ((InputTrigger == TIM_TS_ITR0) \|\| (InputTrigger == TIM_TS_ITR1) \|\|
bogdanm	0:9b334a45a8ff	1537	(InputTrigger == TIM_TS_ITR2) \|\| (InputTrigger == TIM_TS_ITR3))
bogdanm	0:9b334a45a8ff	1538	{
bogdanm	0:9b334a45a8ff	1539	/* Select the Input trigger */
bogdanm	0:9b334a45a8ff	1540	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	1541	htim->Instance->SMCR \|= InputTrigger;
bogdanm	0:9b334a45a8ff	1542	}
bogdanm	0:9b334a45a8ff	1543
bogdanm	0:9b334a45a8ff	1544	/* Select the Capture Compare preload feature */
bogdanm	0:9b334a45a8ff	1545	htim->Instance->CR2 \|= TIM_CR2_CCPC;
bogdanm	0:9b334a45a8ff	1546	/* Select the Commutation event source */
bogdanm	0:9b334a45a8ff	1547	htim->Instance->CR2 &= ~TIM_CR2_CCUS;
bogdanm	0:9b334a45a8ff	1548	htim->Instance->CR2 \|= CommutationSource;
bogdanm	0:9b334a45a8ff	1549
bogdanm	0:9b334a45a8ff	1550	/* Enable the Commutation Interrupt Request */
bogdanm	0:9b334a45a8ff	1551	__HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
bogdanm	0:9b334a45a8ff	1552
bogdanm	0:9b334a45a8ff	1553	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1554
bogdanm	0:9b334a45a8ff	1555	return HAL_OK;
bogdanm	0:9b334a45a8ff	1556	}
bogdanm	0:9b334a45a8ff	1557
bogdanm	0:9b334a45a8ff	1558	/**
bogdanm	0:9b334a45a8ff	1559	* @brief Configure the TIM commutation event sequence with DMA.
bogdanm	0:9b334a45a8ff	1560	* @note: this function is mandatory to use the commutation event in order to
bogdanm	0:9b334a45a8ff	1561	* update the configuration at each commutation detection on the TRGI input of the Timer,
bogdanm	0:9b334a45a8ff	1562	* the typical use of this feature is with the use of another Timer(interface Timer)
bogdanm	0:9b334a45a8ff	1563	* configured in Hall sensor interface, this interface Timer will generate the
bogdanm	0:9b334a45a8ff	1564	* commutation at its TRGO output (connected to Timer used in this function) each time
bogdanm	0:9b334a45a8ff	1565	* the TI1 of the Interface Timer detect a commutation at its input TI1.
bogdanm	0:9b334a45a8ff	1566	* @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
bogdanm	0:9b334a45a8ff	1567	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1568	* @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
bogdanm	0:9b334a45a8ff	1569	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1570	* @arg TIM_TS_ITR0: Internal trigger 0 selected
bogdanm	0:9b334a45a8ff	1571	* @arg TIM_TS_ITR1: Internal trigger 1 selected
bogdanm	0:9b334a45a8ff	1572	* @arg TIM_TS_ITR2: Internal trigger 2 selected
bogdanm	0:9b334a45a8ff	1573	* @arg TIM_TS_ITR3: Internal trigger 3 selected
bogdanm	0:9b334a45a8ff	1574	* @arg TIM_TS_NONE: No trigger is needed
bogdanm	0:9b334a45a8ff	1575	* @param CommutationSource : the Commutation Event source
bogdanm	0:9b334a45a8ff	1576	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1577	* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
bogdanm	0:9b334a45a8ff	1578	* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
bogdanm	0:9b334a45a8ff	1579	* @retval HAL status
bogdanm	0:9b334a45a8ff	1580	*/
bogdanm	0:9b334a45a8ff	1581	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
bogdanm	0:9b334a45a8ff	1582	{
bogdanm	0:9b334a45a8ff	1583	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1584	assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1585	assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
bogdanm	0:9b334a45a8ff	1586
bogdanm	0:9b334a45a8ff	1587	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	1588
bogdanm	0:9b334a45a8ff	1589	if ((InputTrigger == TIM_TS_ITR0) \|\| (InputTrigger == TIM_TS_ITR1) \|\|
bogdanm	0:9b334a45a8ff	1590	(InputTrigger == TIM_TS_ITR2) \|\| (InputTrigger == TIM_TS_ITR3))
bogdanm	0:9b334a45a8ff	1591	{
bogdanm	0:9b334a45a8ff	1592	/* Select the Input trigger */
bogdanm	0:9b334a45a8ff	1593	htim->Instance->SMCR &= ~TIM_SMCR_TS;
bogdanm	0:9b334a45a8ff	1594	htim->Instance->SMCR \|= InputTrigger;
bogdanm	0:9b334a45a8ff	1595	}
bogdanm	0:9b334a45a8ff	1596
bogdanm	0:9b334a45a8ff	1597	/* Select the Capture Compare preload feature */
bogdanm	0:9b334a45a8ff	1598	htim->Instance->CR2 \|= TIM_CR2_CCPC;
bogdanm	0:9b334a45a8ff	1599	/* Select the Commutation event source */
bogdanm	0:9b334a45a8ff	1600	htim->Instance->CR2 &= ~TIM_CR2_CCUS;
bogdanm	0:9b334a45a8ff	1601	htim->Instance->CR2 \|= CommutationSource;
bogdanm	0:9b334a45a8ff	1602
bogdanm	0:9b334a45a8ff	1603	/* Enable the Commutation DMA Request */
bogdanm	0:9b334a45a8ff	1604	/* Set the DMA Commutation Callback */
bogdanm	0:9b334a45a8ff	1605	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
bogdanm	0:9b334a45a8ff	1606	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1607	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	/* Enable the Commutation DMA Request */
bogdanm	0:9b334a45a8ff	1610	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
bogdanm	0:9b334a45a8ff	1611
bogdanm	0:9b334a45a8ff	1612	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1613
bogdanm	0:9b334a45a8ff	1614	return HAL_OK;
bogdanm	0:9b334a45a8ff	1615	}
bogdanm	0:9b334a45a8ff	1616
bogdanm	0:9b334a45a8ff	1617	/**
bogdanm	0:9b334a45a8ff	1618	* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
bogdanm	0:9b334a45a8ff	1619	* and the AOE(automatic output enable).
bogdanm	0:9b334a45a8ff	1620	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1621	* @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	1622	* contains the BDTR Register configuration information for the TIM peripheral.
bogdanm	0:9b334a45a8ff	1623	* @retval HAL status
bogdanm	0:9b334a45a8ff	1624	*/
bogdanm	0:9b334a45a8ff	1625	HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
bogdanm	0:9b334a45a8ff	1626	TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
bogdanm	0:9b334a45a8ff	1627	{
bogdanm	0:9b334a45a8ff	1628	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1629	assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1630	assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
bogdanm	0:9b334a45a8ff	1631	assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
bogdanm	0:9b334a45a8ff	1632	assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
bogdanm	0:9b334a45a8ff	1633	assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
bogdanm	0:9b334a45a8ff	1634	assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
bogdanm	0:9b334a45a8ff	1635	assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
bogdanm	0:9b334a45a8ff	1636	assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
bogdanm	0:9b334a45a8ff	1637
bogdanm	0:9b334a45a8ff	1638	/* Process Locked */
bogdanm	0:9b334a45a8ff	1639	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	1640
bogdanm	0:9b334a45a8ff	1641	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1642
bogdanm	0:9b334a45a8ff	1643	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
bogdanm	0:9b334a45a8ff	1644	the OSSI State, the dead time value and the Automatic Output Enable Bit */
bogdanm	0:9b334a45a8ff	1645	htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode \|
bogdanm	0:9b334a45a8ff	1646	sBreakDeadTimeConfig->OffStateIDLEMode \|
bogdanm	0:9b334a45a8ff	1647	sBreakDeadTimeConfig->LockLevel \|
bogdanm	0:9b334a45a8ff	1648	sBreakDeadTimeConfig->DeadTime \|
bogdanm	0:9b334a45a8ff	1649	sBreakDeadTimeConfig->BreakState \|
bogdanm	0:9b334a45a8ff	1650	sBreakDeadTimeConfig->BreakPolarity \|
bogdanm	0:9b334a45a8ff	1651	sBreakDeadTimeConfig->AutomaticOutput;
bogdanm	0:9b334a45a8ff	1652
bogdanm	0:9b334a45a8ff	1653
bogdanm	0:9b334a45a8ff	1654	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1655
bogdanm	0:9b334a45a8ff	1656	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1657
bogdanm	0:9b334a45a8ff	1658	return HAL_OK;
bogdanm	0:9b334a45a8ff	1659	}
bogdanm	0:9b334a45a8ff	1660
bogdanm	0:9b334a45a8ff	1661	#endif /* defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| */
bogdanm	0:9b334a45a8ff	1662	/* defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| */
bogdanm	0:9b334a45a8ff	1663	/* defined(STM32F105xC) \|\| defined(STM32F107xC) */
bogdanm	0:9b334a45a8ff	1664
bogdanm	0:9b334a45a8ff	1665	/**
bogdanm	0:9b334a45a8ff	1666	* @brief Configures the TIM in master mode.
bogdanm	0:9b334a45a8ff	1667	* @param htim : TIM handle.
bogdanm	0:9b334a45a8ff	1668	* @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that
bogdanm	0:9b334a45a8ff	1669	* contains the selected trigger output (TRGO) and the Master/Slave
bogdanm	0:9b334a45a8ff	1670	* mode.
bogdanm	0:9b334a45a8ff	1671	* @retval HAL status
bogdanm	0:9b334a45a8ff	1672	*/
bogdanm	0:9b334a45a8ff	1673	HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef htim, TIM_MasterConfigTypeDef sMasterConfig)
bogdanm	0:9b334a45a8ff	1674	{
bogdanm	0:9b334a45a8ff	1675	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1676	assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
bogdanm	0:9b334a45a8ff	1677	assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
bogdanm	0:9b334a45a8ff	1678	assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
bogdanm	0:9b334a45a8ff	1679
bogdanm	0:9b334a45a8ff	1680	__HAL_LOCK(htim);
bogdanm	0:9b334a45a8ff	1681
bogdanm	0:9b334a45a8ff	1682	htim->State = HAL_TIM_STATE_BUSY;
bogdanm	0:9b334a45a8ff	1683
bogdanm	0:9b334a45a8ff	1684	/* Reset the MMS Bits */
bogdanm	0:9b334a45a8ff	1685	htim->Instance->CR2 &= ~TIM_CR2_MMS;
bogdanm	0:9b334a45a8ff	1686	/* Select the TRGO source */
bogdanm	0:9b334a45a8ff	1687	htim->Instance->CR2 \|= sMasterConfig->MasterOutputTrigger;
bogdanm	0:9b334a45a8ff	1688
bogdanm	0:9b334a45a8ff	1689	/* Reset the MSM Bit */
bogdanm	0:9b334a45a8ff	1690	htim->Instance->SMCR &= ~TIM_SMCR_MSM;
bogdanm	0:9b334a45a8ff	1691	/* Set or Reset the MSM Bit */
bogdanm	0:9b334a45a8ff	1692	htim->Instance->SMCR \|= sMasterConfig->MasterSlaveMode;
bogdanm	0:9b334a45a8ff	1693
bogdanm	0:9b334a45a8ff	1694	htim->State = HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1695
bogdanm	0:9b334a45a8ff	1696	__HAL_UNLOCK(htim);
bogdanm	0:9b334a45a8ff	1697
bogdanm	0:9b334a45a8ff	1698	return HAL_OK;
bogdanm	0:9b334a45a8ff	1699	}
bogdanm	0:9b334a45a8ff	1700
bogdanm	0:9b334a45a8ff	1701	/**
bogdanm	0:9b334a45a8ff	1702	* @}
bogdanm	0:9b334a45a8ff	1703	*/
bogdanm	0:9b334a45a8ff	1704
bogdanm	0:9b334a45a8ff	1705	/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
bogdanm	0:9b334a45a8ff	1706	* @brief Extension Callbacks functions
bogdanm	0:9b334a45a8ff	1707	*
bogdanm	0:9b334a45a8ff	1708	@verbatim
bogdanm	0:9b334a45a8ff	1709	==============================================================================
bogdanm	0:9b334a45a8ff	1710	##### Extension Callbacks functions #####
bogdanm	0:9b334a45a8ff	1711	==============================================================================
bogdanm	0:9b334a45a8ff	1712	[..]
bogdanm	0:9b334a45a8ff	1713	This section provides Extension TIM callback functions:
bogdanm	0:9b334a45a8ff	1714	(+) Timer Commutation callback
bogdanm	0:9b334a45a8ff	1715	(+) Timer Break callback
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	@endverbatim
bogdanm	0:9b334a45a8ff	1718	* @{
bogdanm	0:9b334a45a8ff	1719	*/
bogdanm	0:9b334a45a8ff	1720
bogdanm	0:9b334a45a8ff	1721	/**
bogdanm	0:9b334a45a8ff	1722	* @brief Hall commutation changed callback in non blocking mode
bogdanm	0:9b334a45a8ff	1723	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1724	* @retval None
bogdanm	0:9b334a45a8ff	1725	*/
bogdanm	0:9b334a45a8ff	1726	__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1727	{
mbed_official	124:6a4a5b7d7324	1728	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1729	UNUSED(htim);
bogdanm	0:9b334a45a8ff	1730	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1731	the HAL_TIMEx_CommutationCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1732	*/
bogdanm	0:9b334a45a8ff	1733	}
bogdanm	0:9b334a45a8ff	1734
bogdanm	0:9b334a45a8ff	1735	/**
bogdanm	0:9b334a45a8ff	1736	* @brief Hall Break detection callback in non blocking mode
bogdanm	0:9b334a45a8ff	1737	* @param htim : TIM handle
bogdanm	0:9b334a45a8ff	1738	* @retval None
bogdanm	0:9b334a45a8ff	1739	*/
bogdanm	0:9b334a45a8ff	1740	__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1741	{
mbed_official	124:6a4a5b7d7324	1742	/* Prevent unused argument(s) compilation warning */
mbed_official	124:6a4a5b7d7324	1743	UNUSED(htim);
bogdanm	0:9b334a45a8ff	1744	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1745	the HAL_TIMEx_BreakCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1746	*/
bogdanm	0:9b334a45a8ff	1747	}
bogdanm	0:9b334a45a8ff	1748
bogdanm	0:9b334a45a8ff	1749	/**
bogdanm	0:9b334a45a8ff	1750	* @brief TIM DMA Commutation callback.
bogdanm	0:9b334a45a8ff	1751	* @param hdma : pointer to DMA handle.
bogdanm	0:9b334a45a8ff	1752	* @retval None
bogdanm	0:9b334a45a8ff	1753	*/
bogdanm	0:9b334a45a8ff	1754	void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1755	{
bogdanm	0:9b334a45a8ff	1756	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1757
bogdanm	0:9b334a45a8ff	1758	htim->State= HAL_TIM_STATE_READY;
bogdanm	0:9b334a45a8ff	1759
bogdanm	0:9b334a45a8ff	1760	HAL_TIMEx_CommutationCallback(htim);
bogdanm	0:9b334a45a8ff	1761	}
bogdanm	0:9b334a45a8ff	1762
bogdanm	0:9b334a45a8ff	1763	/**
bogdanm	0:9b334a45a8ff	1764	* @}
bogdanm	0:9b334a45a8ff	1765	*/
bogdanm	0:9b334a45a8ff	1766
bogdanm	0:9b334a45a8ff	1767	#if defined (STM32F100xB) \|\| defined (STM32F100xE) \|\| \
bogdanm	0:9b334a45a8ff	1768	defined (STM32F103x6) \|\| defined (STM32F103xB) \|\| defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| \
bogdanm	0:9b334a45a8ff	1769	defined (STM32F105xC) \|\| defined (STM32F107xC)
bogdanm	0:9b334a45a8ff	1770
bogdanm	0:9b334a45a8ff	1771	/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
bogdanm	0:9b334a45a8ff	1772	* @brief Extension Peripheral State functions
bogdanm	0:9b334a45a8ff	1773	*
bogdanm	0:9b334a45a8ff	1774	@verbatim
bogdanm	0:9b334a45a8ff	1775	==============================================================================
bogdanm	0:9b334a45a8ff	1776	##### Extension Peripheral State functions #####
bogdanm	0:9b334a45a8ff	1777	==============================================================================
bogdanm	0:9b334a45a8ff	1778	[..]
bogdanm	0:9b334a45a8ff	1779	This subsection permit to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	1780	and the data flow.
bogdanm	0:9b334a45a8ff	1781
bogdanm	0:9b334a45a8ff	1782	@endverbatim
bogdanm	0:9b334a45a8ff	1783	* @{
bogdanm	0:9b334a45a8ff	1784	*/
bogdanm	0:9b334a45a8ff	1785
bogdanm	0:9b334a45a8ff	1786	/**
bogdanm	0:9b334a45a8ff	1787	* @brief Return the TIM Hall Sensor interface state
bogdanm	0:9b334a45a8ff	1788	* @param htim : TIM Hall Sensor handle
bogdanm	0:9b334a45a8ff	1789	* @retval HAL state
bogdanm	0:9b334a45a8ff	1790	*/
bogdanm	0:9b334a45a8ff	1791	HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
bogdanm	0:9b334a45a8ff	1792	{
bogdanm	0:9b334a45a8ff	1793	return htim->State;
bogdanm	0:9b334a45a8ff	1794	}
bogdanm	0:9b334a45a8ff	1795
bogdanm	0:9b334a45a8ff	1796	/**
bogdanm	0:9b334a45a8ff	1797	* @}
bogdanm	0:9b334a45a8ff	1798	*/
bogdanm	0:9b334a45a8ff	1799	#endif /* defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| */
bogdanm	0:9b334a45a8ff	1800	/* defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| */
bogdanm	0:9b334a45a8ff	1801	/* defined(STM32F105xC) \|\| defined(STM32F107xC) */
bogdanm	0:9b334a45a8ff	1802
bogdanm	0:9b334a45a8ff	1803	/**
bogdanm	0:9b334a45a8ff	1804	* @}
bogdanm	0:9b334a45a8ff	1805	*/
bogdanm	0:9b334a45a8ff	1806
bogdanm	0:9b334a45a8ff	1807	#if defined (STM32F100xB) \|\| defined (STM32F100xE) \|\| \
bogdanm	0:9b334a45a8ff	1808	defined (STM32F103x6) \|\| defined (STM32F103xB) \|\| defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| \
bogdanm	0:9b334a45a8ff	1809	defined (STM32F105xC) \|\| defined (STM32F107xC)
bogdanm	0:9b334a45a8ff	1810
bogdanm	0:9b334a45a8ff	1811	/** @addtogroup TIMEx_Private_Functions
bogdanm	0:9b334a45a8ff	1812	* @{
bogdanm	0:9b334a45a8ff	1813	*/
bogdanm	0:9b334a45a8ff	1814
bogdanm	0:9b334a45a8ff	1815	/**
bogdanm	0:9b334a45a8ff	1816	* @brief Enables or disables the TIM Capture Compare Channel xN.
bogdanm	0:9b334a45a8ff	1817	* @param TIMx to select the TIM peripheral
bogdanm	0:9b334a45a8ff	1818	* @param Channel : specifies the TIM Channel
bogdanm	0:9b334a45a8ff	1819	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1820	* @arg TIM_Channel_1: TIM Channel 1
bogdanm	0:9b334a45a8ff	1821	* @arg TIM_Channel_2: TIM Channel 2
bogdanm	0:9b334a45a8ff	1822	* @arg TIM_Channel_3: TIM Channel 3
bogdanm	0:9b334a45a8ff	1823	* @param ChannelNState : specifies the TIM Channel CCxNE bit new state.
bogdanm	0:9b334a45a8ff	1824	* This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
bogdanm	0:9b334a45a8ff	1825	* @retval None
bogdanm	0:9b334a45a8ff	1826	*/
bogdanm	0:9b334a45a8ff	1827	static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
bogdanm	0:9b334a45a8ff	1828	{
bogdanm	0:9b334a45a8ff	1829	uint32_t tmp = 0;
bogdanm	0:9b334a45a8ff	1830
bogdanm	0:9b334a45a8ff	1831	tmp = TIM_CCER_CC1NE << Channel;
bogdanm	0:9b334a45a8ff	1832
bogdanm	0:9b334a45a8ff	1833	/* Reset the CCxNE Bit */
bogdanm	0:9b334a45a8ff	1834	TIMx->CCER &= ~tmp;
bogdanm	0:9b334a45a8ff	1835
bogdanm	0:9b334a45a8ff	1836	/* Set or reset the CCxNE Bit */
bogdanm	0:9b334a45a8ff	1837	TIMx->CCER \|= (uint32_t)(ChannelNState << Channel);
bogdanm	0:9b334a45a8ff	1838	}
bogdanm	0:9b334a45a8ff	1839
bogdanm	0:9b334a45a8ff	1840	/**
bogdanm	0:9b334a45a8ff	1841	* @}
bogdanm	0:9b334a45a8ff	1842	*/
bogdanm	0:9b334a45a8ff	1843
bogdanm	0:9b334a45a8ff	1844	#endif /* defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| */
bogdanm	0:9b334a45a8ff	1845	/* defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| */
bogdanm	0:9b334a45a8ff	1846	/* defined(STM32F105xC) \|\| defined(STM32F107xC) */
bogdanm	0:9b334a45a8ff	1847
bogdanm	0:9b334a45a8ff	1848	#endif /* HAL_TIM_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1849	/**
bogdanm	0:9b334a45a8ff	1850	* @}
bogdanm	0:9b334a45a8ff	1851	*/
bogdanm	0:9b334a45a8ff	1852
bogdanm	0:9b334a45a8ff	1853	/**
bogdanm	0:9b334a45a8ff	1854	* @}
bogdanm	0:9b334a45a8ff	1855	*/
bogdanm	0:9b334a45a8ff	1856
bogdanm	0:9b334a45a8ff	1857	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim_ex.c@124:6a4a5b7d7324, 2016-05-09 (annotated)

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