en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sram.c@124:6a4a5b7d7324, 2016-05-09 (annotated)

Committer:
mbed_official
Date:
Mon May 09 18:30:12 2016 +0100
Revision:
124:6a4a5b7d7324
Parent:
0:9b334a45a8ff 
Synchronized with git revision ad75bdcde34d7da9d54b7669010c7fb968a99c7c



Full URL: https://github.com/mbedmicro/mbed/commit/ad75bdcde34d7da9d54b7669010c7fb968a99c7c/



[STMF1] Stm32f1_hal_cube update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_sram.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 124:6a4a5b7d7324 5 * @version V1.0.4
mbed_official 124:6a4a5b7d7324 6 * @date 29-April-2016
bogdanm 0:9b334a45a8ff 7 * @brief SRAM HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides a generic firmware to drive SRAM memories
bogdanm 0:9b334a45a8ff 9 * mounted as external device.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 @verbatim
bogdanm 0:9b334a45a8ff 12 ==============================================================================
bogdanm 0:9b334a45a8ff 13 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 [..]
bogdanm 0:9b334a45a8ff 16 This driver is a generic layered driver which contains a set of APIs used to
bogdanm 0:9b334a45a8ff 17 control SRAM memories. It uses the FSMC layer functions to interface
bogdanm 0:9b334a45a8ff 18 with SRAM devices.
bogdanm 0:9b334a45a8ff 19 The following sequence should be followed to configure the FSMC to interface
bogdanm 0:9b334a45a8ff 20 with SRAM/PSRAM memories:
bogdanm 0:9b334a45a8ff 21
bogdanm 0:9b334a45a8ff 22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
bogdanm 0:9b334a45a8ff 23 SRAM_HandleTypeDef hsram; and:
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
bogdanm 0:9b334a45a8ff 26 values of the structure member.
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
bogdanm 0:9b334a45a8ff 29 base register instance for NOR or SRAM device
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
bogdanm 0:9b334a45a8ff 32 base register instance for NOR or SRAM extended mode
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
bogdanm 0:9b334a45a8ff 35 mode timings; for example:
bogdanm 0:9b334a45a8ff 36 FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
bogdanm 0:9b334a45a8ff 37 and fill its fields with the allowed values of the structure member.
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
bogdanm 0:9b334a45a8ff 40 performs the following sequence:
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
bogdanm 0:9b334a45a8ff 43 (##) Control register configuration using the FSMC NORSRAM interface function
bogdanm 0:9b334a45a8ff 44 FSMC_NORSRAM_Init()
bogdanm 0:9b334a45a8ff 45 (##) Timing register configuration using the FSMC NORSRAM interface function
bogdanm 0:9b334a45a8ff 46 FSMC_NORSRAM_Timing_Init()
bogdanm 0:9b334a45a8ff 47 (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
bogdanm 0:9b334a45a8ff 48 FSMC_NORSRAM_Extended_Timing_Init()
bogdanm 0:9b334a45a8ff 49 (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 (#) At this stage you can perform read/write accesses from/to the memory connected
bogdanm 0:9b334a45a8ff 52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
bogdanm 0:9b334a45a8ff 53 following APIs:
bogdanm 0:9b334a45a8ff 54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
bogdanm 0:9b334a45a8ff 55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
bogdanm 0:9b334a45a8ff 58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 (#) You can continuously monitor the SRAM device HAL state by calling the function
bogdanm 0:9b334a45a8ff 61 HAL_SRAM_GetState()
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 @endverbatim
bogdanm 0:9b334a45a8ff 64 ******************************************************************************
bogdanm 0:9b334a45a8ff 65 * @attention
bogdanm 0:9b334a45a8ff 66 *
mbed_official 124:6a4a5b7d7324 67 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 68 *
bogdanm 0:9b334a45a8ff 69 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 70 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 71 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 72 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 73 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 74 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 75 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 77 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 78 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 79 *
bogdanm 0:9b334a45a8ff 80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 90 *
bogdanm 0:9b334a45a8ff 91 ******************************************************************************
bogdanm 0:9b334a45a8ff 92 */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 95 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 98 * @{
bogdanm 0:9b334a45a8ff 99 */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 #ifdef HAL_SRAM_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 /** @defgroup SRAM SRAM
bogdanm 0:9b334a45a8ff 106 * @brief SRAM driver modules
bogdanm 0:9b334a45a8ff 107 * @{
bogdanm 0:9b334a45a8ff 108 */
bogdanm 0:9b334a45a8ff 109 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 110 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 111 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 112 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 113 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 114 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
bogdanm 0:9b334a45a8ff 117 * @{
bogdanm 0:9b334a45a8ff 118 */
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 121 * @brief Initialization and Configuration functions.
bogdanm 0:9b334a45a8ff 122 *
bogdanm 0:9b334a45a8ff 123 @verbatim
bogdanm 0:9b334a45a8ff 124 ==============================================================================
bogdanm 0:9b334a45a8ff 125 ##### SRAM Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 126 ==============================================================================
bogdanm 0:9b334a45a8ff 127 [..] This section provides functions allowing to initialize/de-initialize
bogdanm 0:9b334a45a8ff 128 the SRAM memory
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 @endverbatim
bogdanm 0:9b334a45a8ff 131 * @{
bogdanm 0:9b334a45a8ff 132 */
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /**
bogdanm 0:9b334a45a8ff 135 * @brief Performs the SRAM device initialization sequence
bogdanm 0:9b334a45a8ff 136 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 137 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 138 * @param Timing: Pointer to SRAM control timing structure
bogdanm 0:9b334a45a8ff 139 * @param ExtTiming: Pointer to SRAM extended mode timing structure
bogdanm 0:9b334a45a8ff 140 * @retval HAL status
bogdanm 0:9b334a45a8ff 141 */
bogdanm 0:9b334a45a8ff 142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
bogdanm 0:9b334a45a8ff 143 {
bogdanm 0:9b334a45a8ff 144 /* Check the SRAM handle parameter */
bogdanm 0:9b334a45a8ff 145 if(hsram == NULL)
bogdanm 0:9b334a45a8ff 146 {
bogdanm 0:9b334a45a8ff 147 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 148 }
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 if(hsram->State == HAL_SRAM_STATE_RESET)
bogdanm 0:9b334a45a8ff 151 {
bogdanm 0:9b334a45a8ff 152 /* Allocate lock resource and initialize it */
mbed_official 124:6a4a5b7d7324 153 hsram->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 156 HAL_SRAM_MspInit(hsram);
bogdanm 0:9b334a45a8ff 157 }
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 /* Initialize SRAM control Interface */
bogdanm 0:9b334a45a8ff 160 FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 /* Initialize SRAM timing Interface */
bogdanm 0:9b334a45a8ff 163 FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /* Initialize SRAM extended mode timing Interface */
bogdanm 0:9b334a45a8ff 166 FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 /* Enable the NORSRAM device */
bogdanm 0:9b334a45a8ff 169 __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 return HAL_OK;
bogdanm 0:9b334a45a8ff 172 }
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /**
bogdanm 0:9b334a45a8ff 175 * @brief Performs the SRAM device De-initialization sequence.
bogdanm 0:9b334a45a8ff 176 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 177 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 178 * @retval HAL status
bogdanm 0:9b334a45a8ff 179 */
bogdanm 0:9b334a45a8ff 180 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
bogdanm 0:9b334a45a8ff 181 {
bogdanm 0:9b334a45a8ff 182 /* De-Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 183 HAL_SRAM_MspDeInit(hsram);
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /* Configure the SRAM registers with their reset values */
bogdanm 0:9b334a45a8ff 186 FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 hsram->State = HAL_SRAM_STATE_RESET;
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /* Release Lock */
bogdanm 0:9b334a45a8ff 191 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 return HAL_OK;
bogdanm 0:9b334a45a8ff 194 }
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 /**
bogdanm 0:9b334a45a8ff 197 * @brief SRAM MSP Init.
bogdanm 0:9b334a45a8ff 198 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 199 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 200 * @retval None
bogdanm 0:9b334a45a8ff 201 */
bogdanm 0:9b334a45a8ff 202 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
bogdanm 0:9b334a45a8ff 203 {
mbed_official 124:6a4a5b7d7324 204 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 205 UNUSED(hsram);
bogdanm 0:9b334a45a8ff 206 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 207 the HAL_SRAM_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 208 */
bogdanm 0:9b334a45a8ff 209 }
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 /**
bogdanm 0:9b334a45a8ff 212 * @brief SRAM MSP DeInit.
bogdanm 0:9b334a45a8ff 213 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 214 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 215 * @retval None
bogdanm 0:9b334a45a8ff 216 */
bogdanm 0:9b334a45a8ff 217 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
bogdanm 0:9b334a45a8ff 218 {
mbed_official 124:6a4a5b7d7324 219 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 220 UNUSED(hsram);
bogdanm 0:9b334a45a8ff 221 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 222 the HAL_SRAM_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 223 */
bogdanm 0:9b334a45a8ff 224 }
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /**
bogdanm 0:9b334a45a8ff 227 * @brief DMA transfer complete callback.
bogdanm 0:9b334a45a8ff 228 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 229 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 230 * @retval None
bogdanm 0:9b334a45a8ff 231 */
bogdanm 0:9b334a45a8ff 232 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 233 {
mbed_official 124:6a4a5b7d7324 234 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 235 UNUSED(hdma);
bogdanm 0:9b334a45a8ff 236 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 237 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 238 */
bogdanm 0:9b334a45a8ff 239 }
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 /**
bogdanm 0:9b334a45a8ff 242 * @brief DMA transfer complete error callback.
bogdanm 0:9b334a45a8ff 243 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 244 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 245 * @retval None
bogdanm 0:9b334a45a8ff 246 */
bogdanm 0:9b334a45a8ff 247 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 248 {
mbed_official 124:6a4a5b7d7324 249 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 250 UNUSED(hdma);
bogdanm 0:9b334a45a8ff 251 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 252 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 253 */
bogdanm 0:9b334a45a8ff 254 }
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 /**
bogdanm 0:9b334a45a8ff 257 * @}
bogdanm 0:9b334a45a8ff 258 */
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
bogdanm 0:9b334a45a8ff 261 * @brief Input Output and memory control functions
bogdanm 0:9b334a45a8ff 262 *
bogdanm 0:9b334a45a8ff 263 @verbatim
bogdanm 0:9b334a45a8ff 264 ==============================================================================
bogdanm 0:9b334a45a8ff 265 ##### SRAM Input and Output functions #####
bogdanm 0:9b334a45a8ff 266 ==============================================================================
bogdanm 0:9b334a45a8ff 267 [..]
bogdanm 0:9b334a45a8ff 268 This section provides functions allowing to use and control the SRAM memory
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 @endverbatim
bogdanm 0:9b334a45a8ff 271 * @{
bogdanm 0:9b334a45a8ff 272 */
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /**
bogdanm 0:9b334a45a8ff 275 * @brief Reads 8-bit buffer from SRAM memory.
bogdanm 0:9b334a45a8ff 276 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 277 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 278 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 279 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 280 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 281 * @retval HAL status
bogdanm 0:9b334a45a8ff 282 */
bogdanm 0:9b334a45a8ff 283 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 284 {
bogdanm 0:9b334a45a8ff 285 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 /* Process Locked */
bogdanm 0:9b334a45a8ff 288 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 291 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 /* Read data from memory */
bogdanm 0:9b334a45a8ff 294 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 295 {
bogdanm 0:9b334a45a8ff 296 *pDstBuffer = *(__IO uint8_t *)psramaddress;
bogdanm 0:9b334a45a8ff 297 pDstBuffer++;
bogdanm 0:9b334a45a8ff 298 psramaddress++;
bogdanm 0:9b334a45a8ff 299 }
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 302 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 /* Process unlocked */
bogdanm 0:9b334a45a8ff 305 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 return HAL_OK;
bogdanm 0:9b334a45a8ff 308 }
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 /**
bogdanm 0:9b334a45a8ff 311 * @brief Writes 8-bit buffer to SRAM memory.
bogdanm 0:9b334a45a8ff 312 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 313 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 314 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 315 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 316 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 317 * @retval HAL status
bogdanm 0:9b334a45a8ff 318 */
bogdanm 0:9b334a45a8ff 319 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 320 {
bogdanm 0:9b334a45a8ff 321 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 /* Check the SRAM controller state */
bogdanm 0:9b334a45a8ff 324 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
bogdanm 0:9b334a45a8ff 325 {
bogdanm 0:9b334a45a8ff 326 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 327 }
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /* Process Locked */
bogdanm 0:9b334a45a8ff 330 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 333 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /* Write data to memory */
bogdanm 0:9b334a45a8ff 336 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 337 {
bogdanm 0:9b334a45a8ff 338 *(__IO uint8_t *)psramaddress = *pSrcBuffer;
bogdanm 0:9b334a45a8ff 339 pSrcBuffer++;
bogdanm 0:9b334a45a8ff 340 psramaddress++;
bogdanm 0:9b334a45a8ff 341 }
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 344 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 /* Process unlocked */
bogdanm 0:9b334a45a8ff 347 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 return HAL_OK;
bogdanm 0:9b334a45a8ff 350 }
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 /**
bogdanm 0:9b334a45a8ff 353 * @brief Reads 16-bit buffer from SRAM memory.
bogdanm 0:9b334a45a8ff 354 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 355 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 356 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 357 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 358 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 359 * @retval HAL status
bogdanm 0:9b334a45a8ff 360 */
bogdanm 0:9b334a45a8ff 361 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 362 {
bogdanm 0:9b334a45a8ff 363 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /* Process Locked */
bogdanm 0:9b334a45a8ff 366 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 369 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 /* Read data from memory */
bogdanm 0:9b334a45a8ff 372 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 373 {
bogdanm 0:9b334a45a8ff 374 *pDstBuffer = *(__IO uint16_t *)psramaddress;
bogdanm 0:9b334a45a8ff 375 pDstBuffer++;
bogdanm 0:9b334a45a8ff 376 psramaddress++;
bogdanm 0:9b334a45a8ff 377 }
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 380 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /* Process unlocked */
bogdanm 0:9b334a45a8ff 383 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 return HAL_OK;
bogdanm 0:9b334a45a8ff 386 }
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 /**
bogdanm 0:9b334a45a8ff 389 * @brief Writes 16-bit buffer to SRAM memory.
bogdanm 0:9b334a45a8ff 390 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 391 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 392 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 393 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 394 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 395 * @retval HAL status
bogdanm 0:9b334a45a8ff 396 */
bogdanm 0:9b334a45a8ff 397 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 398 {
bogdanm 0:9b334a45a8ff 399 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /* Check the SRAM controller state */
bogdanm 0:9b334a45a8ff 402 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
bogdanm 0:9b334a45a8ff 403 {
bogdanm 0:9b334a45a8ff 404 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 405 }
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /* Process Locked */
bogdanm 0:9b334a45a8ff 408 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 411 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 /* Write data to memory */
bogdanm 0:9b334a45a8ff 414 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 415 {
bogdanm 0:9b334a45a8ff 416 *(__IO uint16_t *)psramaddress = *pSrcBuffer;
bogdanm 0:9b334a45a8ff 417 pSrcBuffer++;
bogdanm 0:9b334a45a8ff 418 psramaddress++;
bogdanm 0:9b334a45a8ff 419 }
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 422 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /* Process unlocked */
bogdanm 0:9b334a45a8ff 425 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 return HAL_OK;
bogdanm 0:9b334a45a8ff 428 }
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 /**
bogdanm 0:9b334a45a8ff 431 * @brief Reads 32-bit buffer from SRAM memory.
bogdanm 0:9b334a45a8ff 432 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 433 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 434 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 435 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 436 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 437 * @retval HAL status
bogdanm 0:9b334a45a8ff 438 */
bogdanm 0:9b334a45a8ff 439 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 440 {
bogdanm 0:9b334a45a8ff 441 /* Process Locked */
bogdanm 0:9b334a45a8ff 442 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 445 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 /* Read data from memory */
bogdanm 0:9b334a45a8ff 448 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 449 {
bogdanm 0:9b334a45a8ff 450 *pDstBuffer = *(__IO uint32_t *)pAddress;
bogdanm 0:9b334a45a8ff 451 pDstBuffer++;
bogdanm 0:9b334a45a8ff 452 pAddress++;
bogdanm 0:9b334a45a8ff 453 }
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 456 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 /* Process unlocked */
bogdanm 0:9b334a45a8ff 459 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 return HAL_OK;
bogdanm 0:9b334a45a8ff 462 }
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /**
bogdanm 0:9b334a45a8ff 465 * @brief Writes 32-bit buffer to SRAM memory.
bogdanm 0:9b334a45a8ff 466 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 467 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 468 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 469 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 470 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 471 * @retval HAL status
bogdanm 0:9b334a45a8ff 472 */
bogdanm 0:9b334a45a8ff 473 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 474 {
bogdanm 0:9b334a45a8ff 475 /* Check the SRAM controller state */
bogdanm 0:9b334a45a8ff 476 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
bogdanm 0:9b334a45a8ff 477 {
bogdanm 0:9b334a45a8ff 478 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 479 }
bogdanm 0:9b334a45a8ff 480
bogdanm 0:9b334a45a8ff 481 /* Process Locked */
bogdanm 0:9b334a45a8ff 482 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 485 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 /* Write data to memory */
bogdanm 0:9b334a45a8ff 488 for(; BufferSize != 0; BufferSize--)
bogdanm 0:9b334a45a8ff 489 {
bogdanm 0:9b334a45a8ff 490 *(__IO uint32_t *)pAddress = *pSrcBuffer;
bogdanm 0:9b334a45a8ff 491 pSrcBuffer++;
bogdanm 0:9b334a45a8ff 492 pAddress++;
bogdanm 0:9b334a45a8ff 493 }
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 496 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 /* Process unlocked */
bogdanm 0:9b334a45a8ff 499 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 500
bogdanm 0:9b334a45a8ff 501 return HAL_OK;
bogdanm 0:9b334a45a8ff 502 }
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504 /**
bogdanm 0:9b334a45a8ff 505 * @brief Reads a Words data from the SRAM memory using DMA transfer.
bogdanm 0:9b334a45a8ff 506 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 507 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 508 * @param pAddress: Pointer to read start address
bogdanm 0:9b334a45a8ff 509 * @param pDstBuffer: Pointer to destination buffer
bogdanm 0:9b334a45a8ff 510 * @param BufferSize: Size of the buffer to read from memory
bogdanm 0:9b334a45a8ff 511 * @retval HAL status
bogdanm 0:9b334a45a8ff 512 */
bogdanm 0:9b334a45a8ff 513 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 514 {
bogdanm 0:9b334a45a8ff 515 /* Process Locked */
bogdanm 0:9b334a45a8ff 516 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 519 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 520
bogdanm 0:9b334a45a8ff 521 /* Configure DMA user callbacks */
bogdanm 0:9b334a45a8ff 522 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
bogdanm 0:9b334a45a8ff 523 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 /* Enable the DMA Channel */
bogdanm 0:9b334a45a8ff 526 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
bogdanm 0:9b334a45a8ff 527
bogdanm 0:9b334a45a8ff 528 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 529 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 /* Process unlocked */
bogdanm 0:9b334a45a8ff 532 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 return HAL_OK;
bogdanm 0:9b334a45a8ff 535 }
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 /**
bogdanm 0:9b334a45a8ff 538 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
bogdanm 0:9b334a45a8ff 539 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 540 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 541 * @param pAddress: Pointer to write start address
bogdanm 0:9b334a45a8ff 542 * @param pSrcBuffer: Pointer to source buffer to write
bogdanm 0:9b334a45a8ff 543 * @param BufferSize: Size of the buffer to write to memory
bogdanm 0:9b334a45a8ff 544 * @retval HAL status
bogdanm 0:9b334a45a8ff 545 */
bogdanm 0:9b334a45a8ff 546 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
bogdanm 0:9b334a45a8ff 547 {
bogdanm 0:9b334a45a8ff 548 /* Check the SRAM controller state */
bogdanm 0:9b334a45a8ff 549 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
bogdanm 0:9b334a45a8ff 550 {
bogdanm 0:9b334a45a8ff 551 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 552 }
bogdanm 0:9b334a45a8ff 553
bogdanm 0:9b334a45a8ff 554 /* Process Locked */
bogdanm 0:9b334a45a8ff 555 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 558 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 /* Configure DMA user callbacks */
bogdanm 0:9b334a45a8ff 561 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
bogdanm 0:9b334a45a8ff 562 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 /* Enable the DMA Channel */
bogdanm 0:9b334a45a8ff 565 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 568 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 569
bogdanm 0:9b334a45a8ff 570 /* Process unlocked */
bogdanm 0:9b334a45a8ff 571 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573 return HAL_OK;
bogdanm 0:9b334a45a8ff 574 }
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 /**
bogdanm 0:9b334a45a8ff 577 * @}
bogdanm 0:9b334a45a8ff 578 */
bogdanm 0:9b334a45a8ff 579
bogdanm 0:9b334a45a8ff 580 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
bogdanm 0:9b334a45a8ff 581 * @brief Control functions
bogdanm 0:9b334a45a8ff 582 *
bogdanm 0:9b334a45a8ff 583 @verbatim
bogdanm 0:9b334a45a8ff 584 ==============================================================================
bogdanm 0:9b334a45a8ff 585 ##### SRAM Control functions #####
bogdanm 0:9b334a45a8ff 586 ==============================================================================
bogdanm 0:9b334a45a8ff 587 [..]
bogdanm 0:9b334a45a8ff 588 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 589 the SRAM interface.
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 @endverbatim
bogdanm 0:9b334a45a8ff 592 * @{
bogdanm 0:9b334a45a8ff 593 */
bogdanm 0:9b334a45a8ff 594
bogdanm 0:9b334a45a8ff 595 /**
bogdanm 0:9b334a45a8ff 596 * @brief Enables dynamically SRAM write operation.
bogdanm 0:9b334a45a8ff 597 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 598 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 599 * @retval HAL status
bogdanm 0:9b334a45a8ff 600 */
bogdanm 0:9b334a45a8ff 601 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
bogdanm 0:9b334a45a8ff 602 {
bogdanm 0:9b334a45a8ff 603 /* Process Locked */
bogdanm 0:9b334a45a8ff 604 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 605
bogdanm 0:9b334a45a8ff 606 /* Enable write operation */
bogdanm 0:9b334a45a8ff 607 FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
bogdanm 0:9b334a45a8ff 608
bogdanm 0:9b334a45a8ff 609 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 610 hsram->State = HAL_SRAM_STATE_READY;
bogdanm 0:9b334a45a8ff 611
bogdanm 0:9b334a45a8ff 612 /* Process unlocked */
bogdanm 0:9b334a45a8ff 613 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 614
bogdanm 0:9b334a45a8ff 615 return HAL_OK;
bogdanm 0:9b334a45a8ff 616 }
bogdanm 0:9b334a45a8ff 617
bogdanm 0:9b334a45a8ff 618 /**
bogdanm 0:9b334a45a8ff 619 * @brief Disables dynamically SRAM write operation.
bogdanm 0:9b334a45a8ff 620 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 621 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 622 * @retval HAL status
bogdanm 0:9b334a45a8ff 623 */
bogdanm 0:9b334a45a8ff 624 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
bogdanm 0:9b334a45a8ff 625 {
bogdanm 0:9b334a45a8ff 626 /* Process Locked */
bogdanm 0:9b334a45a8ff 627 __HAL_LOCK(hsram);
bogdanm 0:9b334a45a8ff 628
bogdanm 0:9b334a45a8ff 629 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 630 hsram->State = HAL_SRAM_STATE_BUSY;
bogdanm 0:9b334a45a8ff 631
bogdanm 0:9b334a45a8ff 632 /* Disable write operation */
bogdanm 0:9b334a45a8ff 633 FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
bogdanm 0:9b334a45a8ff 634
bogdanm 0:9b334a45a8ff 635 /* Update the SRAM controller state */
bogdanm 0:9b334a45a8ff 636 hsram->State = HAL_SRAM_STATE_PROTECTED;
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638 /* Process unlocked */
bogdanm 0:9b334a45a8ff 639 __HAL_UNLOCK(hsram);
bogdanm 0:9b334a45a8ff 640
bogdanm 0:9b334a45a8ff 641 return HAL_OK;
bogdanm 0:9b334a45a8ff 642 }
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 /**
bogdanm 0:9b334a45a8ff 645 * @}
bogdanm 0:9b334a45a8ff 646 */
bogdanm 0:9b334a45a8ff 647
bogdanm 0:9b334a45a8ff 648 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
bogdanm 0:9b334a45a8ff 649 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 650 *
bogdanm 0:9b334a45a8ff 651 @verbatim
bogdanm 0:9b334a45a8ff 652 ==============================================================================
bogdanm 0:9b334a45a8ff 653 ##### SRAM State functions #####
bogdanm 0:9b334a45a8ff 654 ==============================================================================
bogdanm 0:9b334a45a8ff 655 [..]
bogdanm 0:9b334a45a8ff 656 This subsection permits to get in run-time the status of the SRAM controller
bogdanm 0:9b334a45a8ff 657 and the data flow.
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 @endverbatim
bogdanm 0:9b334a45a8ff 660 * @{
bogdanm 0:9b334a45a8ff 661 */
bogdanm 0:9b334a45a8ff 662
bogdanm 0:9b334a45a8ff 663 /**
bogdanm 0:9b334a45a8ff 664 * @brief Returns the SRAM controller state
bogdanm 0:9b334a45a8ff 665 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 666 * the configuration information for SRAM module.
bogdanm 0:9b334a45a8ff 667 * @retval HAL state
bogdanm 0:9b334a45a8ff 668 */
bogdanm 0:9b334a45a8ff 669 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
bogdanm 0:9b334a45a8ff 670 {
bogdanm 0:9b334a45a8ff 671 return hsram->State;
bogdanm 0:9b334a45a8ff 672 }
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 /**
bogdanm 0:9b334a45a8ff 675 * @}
bogdanm 0:9b334a45a8ff 676 */
bogdanm 0:9b334a45a8ff 677
bogdanm 0:9b334a45a8ff 678 /**
bogdanm 0:9b334a45a8ff 679 * @}
bogdanm 0:9b334a45a8ff 680 */
bogdanm 0:9b334a45a8ff 681
bogdanm 0:9b334a45a8ff 682 /**
bogdanm 0:9b334a45a8ff 683 * @}
bogdanm 0:9b334a45a8ff 684 */
bogdanm 0:9b334a45a8ff 685 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
bogdanm 0:9b334a45a8ff 686 #endif /* HAL_SRAM_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 /**
bogdanm 0:9b334a45a8ff 689 * @}
bogdanm 0:9b334a45a8ff 690 */
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/