en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_wdog.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
50:a417edff4437 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 50:a417edff4437 1 /**************************************************************************//**
mbed_official 50:a417edff4437 2 * @file efm32pg1b_wdog.h
mbed_official 50:a417edff4437 3 * @brief EFM32PG1B_WDOG register and bit field definitions
mbed_official 50:a417edff4437 4 * @version 4.2.0
mbed_official 50:a417edff4437 5 ******************************************************************************
mbed_official 50:a417edff4437 6 * @section License
mbed_official 50:a417edff4437 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
mbed_official 50:a417edff4437 8 ******************************************************************************
mbed_official 50:a417edff4437 9 *
mbed_official 50:a417edff4437 10 * Permission is granted to anyone to use this software for any purpose,
mbed_official 50:a417edff4437 11 * including commercial applications, and to alter it and redistribute it
mbed_official 50:a417edff4437 12 * freely, subject to the following restrictions:
mbed_official 50:a417edff4437 13 *
mbed_official 50:a417edff4437 14 * 1. The origin of this software must not be misrepresented; you must not
mbed_official 50:a417edff4437 15 * claim that you wrote the original software.@n
mbed_official 50:a417edff4437 16 * 2. Altered source versions must be plainly marked as such, and must not be
mbed_official 50:a417edff4437 17 * misrepresented as being the original software.@n
mbed_official 50:a417edff4437 18 * 3. This notice may not be removed or altered from any source distribution.
mbed_official 50:a417edff4437 19 *
mbed_official 50:a417edff4437 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
mbed_official 50:a417edff4437 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
mbed_official 50:a417edff4437 22 * providing the Software "AS IS", with no express or implied warranties of any
mbed_official 50:a417edff4437 23 * kind, including, but not limited to, any implied warranties of
mbed_official 50:a417edff4437 24 * merchantability or fitness for any particular purpose or warranties against
mbed_official 50:a417edff4437 25 * infringement of any proprietary rights of a third party.
mbed_official 50:a417edff4437 26 *
mbed_official 50:a417edff4437 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
mbed_official 50:a417edff4437 28 * incidental, or special damages, or any other relief, or for any claim by
mbed_official 50:a417edff4437 29 * any third party, arising from your use of this Software.
mbed_official 50:a417edff4437 30 *
mbed_official 50:a417edff4437 31 *****************************************************************************/
mbed_official 50:a417edff4437 32 /**************************************************************************//**
mbed_official 50:a417edff4437 33 * @addtogroup Parts
mbed_official 50:a417edff4437 34 * @{
mbed_official 50:a417edff4437 35 ******************************************************************************/
mbed_official 50:a417edff4437 36 /**************************************************************************//**
mbed_official 50:a417edff4437 37 * @defgroup EFM32PG1B_WDOG
mbed_official 50:a417edff4437 38 * @{
mbed_official 50:a417edff4437 39 * @brief EFM32PG1B_WDOG Register Declaration
mbed_official 50:a417edff4437 40 *****************************************************************************/
mbed_official 50:a417edff4437 41 typedef struct
mbed_official 50:a417edff4437 42 {
mbed_official 50:a417edff4437 43 __IO uint32_t CTRL; /**< Control Register */
mbed_official 50:a417edff4437 44 __IO uint32_t CMD; /**< Command Register */
mbed_official 50:a417edff4437 45
mbed_official 50:a417edff4437 46 __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
mbed_official 50:a417edff4437 47
mbed_official 50:a417edff4437 48 WDOG_PCH_TypeDef PCH[2]; /**< PCH */
mbed_official 50:a417edff4437 49
mbed_official 50:a417edff4437 50 uint32_t RESERVED0[2]; /**< Reserved for future use **/
mbed_official 50:a417edff4437 51 __I uint32_t IF; /**< Watchdog Interrupt Flags */
mbed_official 50:a417edff4437 52 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
mbed_official 50:a417edff4437 53 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
mbed_official 50:a417edff4437 54 __IO uint32_t IEN; /**< Interrupt Enable Register */
mbed_official 50:a417edff4437 55 } WDOG_TypeDef; /** @} */
mbed_official 50:a417edff4437 56
mbed_official 50:a417edff4437 57 /**************************************************************************//**
mbed_official 50:a417edff4437 58 * @defgroup EFM32PG1B_WDOG_BitFields
mbed_official 50:a417edff4437 59 * @{
mbed_official 50:a417edff4437 60 *****************************************************************************/
mbed_official 50:a417edff4437 61
mbed_official 50:a417edff4437 62 /* Bit fields for WDOG CTRL */
mbed_official 50:a417edff4437 63 #define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */
mbed_official 50:a417edff4437 64 #define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */
mbed_official 50:a417edff4437 65 #define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */
mbed_official 50:a417edff4437 66 #define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */
mbed_official 50:a417edff4437 67 #define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */
mbed_official 50:a417edff4437 68 #define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 69 #define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 70 #define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
mbed_official 50:a417edff4437 71 #define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */
mbed_official 50:a417edff4437 72 #define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */
mbed_official 50:a417edff4437 73 #define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 74 #define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 75 #define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */
mbed_official 50:a417edff4437 76 #define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */
mbed_official 50:a417edff4437 77 #define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */
mbed_official 50:a417edff4437 78 #define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 79 #define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 80 #define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */
mbed_official 50:a417edff4437 81 #define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */
mbed_official 50:a417edff4437 82 #define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */
mbed_official 50:a417edff4437 83 #define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 84 #define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 85 #define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */
mbed_official 50:a417edff4437 86 #define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */
mbed_official 50:a417edff4437 87 #define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */
mbed_official 50:a417edff4437 88 #define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 89 #define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 90 #define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */
mbed_official 50:a417edff4437 91 #define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */
mbed_official 50:a417edff4437 92 #define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */
mbed_official 50:a417edff4437 93 #define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 94 #define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 95 #define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */
mbed_official 50:a417edff4437 96 #define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */
mbed_official 50:a417edff4437 97 #define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */
mbed_official 50:a417edff4437 98 #define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 99 #define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 100 #define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */
mbed_official 50:a417edff4437 101 #define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */
mbed_official 50:a417edff4437 102 #define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 103 #define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 104 #define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */
mbed_official 50:a417edff4437 105 #define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */
mbed_official 50:a417edff4437 106 #define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 107 #define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */
mbed_official 50:a417edff4437 108 #define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */
mbed_official 50:a417edff4437 109 #define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */
mbed_official 50:a417edff4437 110 #define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 111 #define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */
mbed_official 50:a417edff4437 112 #define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */
mbed_official 50:a417edff4437 113 #define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */
mbed_official 50:a417edff4437 114 #define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */
mbed_official 50:a417edff4437 115 #define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */
mbed_official 50:a417edff4437 116 #define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 117 #define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 118 #define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */
mbed_official 50:a417edff4437 119 #define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */
mbed_official 50:a417edff4437 120 #define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 121 #define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 122 #define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */
mbed_official 50:a417edff4437 123 #define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */
mbed_official 50:a417edff4437 124 #define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */
mbed_official 50:a417edff4437 125 #define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 126 #define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */
mbed_official 50:a417edff4437 127 #define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */
mbed_official 50:a417edff4437 128 #define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 129 #define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */
mbed_official 50:a417edff4437 130 #define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */
mbed_official 50:a417edff4437 131 #define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */
mbed_official 50:a417edff4437 132 #define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */
mbed_official 50:a417edff4437 133 #define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */
mbed_official 50:a417edff4437 134 #define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 135 #define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */
mbed_official 50:a417edff4437 136 #define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */
mbed_official 50:a417edff4437 137 #define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */
mbed_official 50:a417edff4437 138 #define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */
mbed_official 50:a417edff4437 139 #define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */
mbed_official 50:a417edff4437 140
mbed_official 50:a417edff4437 141 /* Bit fields for WDOG CMD */
mbed_official 50:a417edff4437 142 #define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */
mbed_official 50:a417edff4437 143 #define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */
mbed_official 50:a417edff4437 144 #define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */
mbed_official 50:a417edff4437 145 #define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */
mbed_official 50:a417edff4437 146 #define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */
mbed_official 50:a417edff4437 147 #define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */
mbed_official 50:a417edff4437 148 #define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */
mbed_official 50:a417edff4437 149 #define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */
mbed_official 50:a417edff4437 150 #define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */
mbed_official 50:a417edff4437 151 #define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */
mbed_official 50:a417edff4437 152 #define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */
mbed_official 50:a417edff4437 153
mbed_official 50:a417edff4437 154 /* Bit fields for WDOG SYNCBUSY */
mbed_official 50:a417edff4437 155 #define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */
mbed_official 50:a417edff4437 156 #define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */
mbed_official 50:a417edff4437 157 #define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
mbed_official 50:a417edff4437 158 #define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */
mbed_official 50:a417edff4437 159 #define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */
mbed_official 50:a417edff4437 160 #define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
mbed_official 50:a417edff4437 161 #define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
mbed_official 50:a417edff4437 162 #define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
mbed_official 50:a417edff4437 163 #define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */
mbed_official 50:a417edff4437 164 #define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */
mbed_official 50:a417edff4437 165 #define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
mbed_official 50:a417edff4437 166 #define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
mbed_official 50:a417edff4437 167 #define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */
mbed_official 50:a417edff4437 168 #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */
mbed_official 50:a417edff4437 169 #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */
mbed_official 50:a417edff4437 170 #define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
mbed_official 50:a417edff4437 171 #define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
mbed_official 50:a417edff4437 172 #define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */
mbed_official 50:a417edff4437 173 #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */
mbed_official 50:a417edff4437 174 #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */
mbed_official 50:a417edff4437 175 #define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
mbed_official 50:a417edff4437 176 #define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
mbed_official 50:a417edff4437 177
mbed_official 50:a417edff4437 178 /* Bit fields for WDOG PCH_PRSCTRL */
mbed_official 50:a417edff4437 179 #define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 180 #define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 181 #define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */
mbed_official 50:a417edff4437 182 #define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */
mbed_official 50:a417edff4437 183 #define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 184 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 185 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 186 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 187 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 188 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 189 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 190 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 191 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 192 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 193 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 194 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 195 #define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 196 #define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 197 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 198 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 199 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 200 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 201 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 202 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 203 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 204 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 205 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 206 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 207 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 208 #define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 209 #define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS missing event will trigger a watchdog reset */
mbed_official 50:a417edff4437 210 #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */
mbed_official 50:a417edff4437 211 #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */
mbed_official 50:a417edff4437 212 #define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 213 #define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
mbed_official 50:a417edff4437 214
mbed_official 50:a417edff4437 215 /* Bit fields for WDOG IF */
mbed_official 50:a417edff4437 216 #define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */
mbed_official 50:a417edff4437 217 #define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */
mbed_official 50:a417edff4437 218 #define WDOG_IF_TOUT (0x1UL << 0) /**< Wdog Timeout Interrupt Flag */
mbed_official 50:a417edff4437 219 #define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
mbed_official 50:a417edff4437 220 #define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
mbed_official 50:a417edff4437 221 #define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
mbed_official 50:a417edff4437 222 #define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */
mbed_official 50:a417edff4437 223 #define WDOG_IF_WARN (0x1UL << 1) /**< Wdog Warning Timeout Interrupt Flag */
mbed_official 50:a417edff4437 224 #define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
mbed_official 50:a417edff4437 225 #define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
mbed_official 50:a417edff4437 226 #define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
mbed_official 50:a417edff4437 227 #define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */
mbed_official 50:a417edff4437 228 #define WDOG_IF_WIN (0x1UL << 2) /**< Wdog Window Interrupt Flag */
mbed_official 50:a417edff4437 229 #define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
mbed_official 50:a417edff4437 230 #define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
mbed_official 50:a417edff4437 231 #define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
mbed_official 50:a417edff4437 232 #define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */
mbed_official 50:a417edff4437 233 #define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */
mbed_official 50:a417edff4437 234 #define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
mbed_official 50:a417edff4437 235 #define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
mbed_official 50:a417edff4437 236 #define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
mbed_official 50:a417edff4437 237 #define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */
mbed_official 50:a417edff4437 238 #define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */
mbed_official 50:a417edff4437 239 #define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
mbed_official 50:a417edff4437 240 #define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
mbed_official 50:a417edff4437 241 #define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
mbed_official 50:a417edff4437 242 #define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */
mbed_official 50:a417edff4437 243
mbed_official 50:a417edff4437 244 /* Bit fields for WDOG IFS */
mbed_official 50:a417edff4437 245 #define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */
mbed_official 50:a417edff4437 246 #define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */
mbed_official 50:a417edff4437 247 #define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */
mbed_official 50:a417edff4437 248 #define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
mbed_official 50:a417edff4437 249 #define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
mbed_official 50:a417edff4437 250 #define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
mbed_official 50:a417edff4437 251 #define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */
mbed_official 50:a417edff4437 252 #define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */
mbed_official 50:a417edff4437 253 #define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
mbed_official 50:a417edff4437 254 #define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
mbed_official 50:a417edff4437 255 #define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
mbed_official 50:a417edff4437 256 #define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */
mbed_official 50:a417edff4437 257 #define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */
mbed_official 50:a417edff4437 258 #define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
mbed_official 50:a417edff4437 259 #define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
mbed_official 50:a417edff4437 260 #define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
mbed_official 50:a417edff4437 261 #define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */
mbed_official 50:a417edff4437 262 #define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */
mbed_official 50:a417edff4437 263 #define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
mbed_official 50:a417edff4437 264 #define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
mbed_official 50:a417edff4437 265 #define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
mbed_official 50:a417edff4437 266 #define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */
mbed_official 50:a417edff4437 267 #define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */
mbed_official 50:a417edff4437 268 #define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
mbed_official 50:a417edff4437 269 #define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
mbed_official 50:a417edff4437 270 #define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
mbed_official 50:a417edff4437 271 #define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */
mbed_official 50:a417edff4437 272
mbed_official 50:a417edff4437 273 /* Bit fields for WDOG IFC */
mbed_official 50:a417edff4437 274 #define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */
mbed_official 50:a417edff4437 275 #define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */
mbed_official 50:a417edff4437 276 #define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */
mbed_official 50:a417edff4437 277 #define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
mbed_official 50:a417edff4437 278 #define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
mbed_official 50:a417edff4437 279 #define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
mbed_official 50:a417edff4437 280 #define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */
mbed_official 50:a417edff4437 281 #define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */
mbed_official 50:a417edff4437 282 #define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
mbed_official 50:a417edff4437 283 #define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
mbed_official 50:a417edff4437 284 #define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
mbed_official 50:a417edff4437 285 #define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */
mbed_official 50:a417edff4437 286 #define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */
mbed_official 50:a417edff4437 287 #define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
mbed_official 50:a417edff4437 288 #define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
mbed_official 50:a417edff4437 289 #define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
mbed_official 50:a417edff4437 290 #define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */
mbed_official 50:a417edff4437 291 #define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */
mbed_official 50:a417edff4437 292 #define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
mbed_official 50:a417edff4437 293 #define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
mbed_official 50:a417edff4437 294 #define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
mbed_official 50:a417edff4437 295 #define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */
mbed_official 50:a417edff4437 296 #define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */
mbed_official 50:a417edff4437 297 #define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
mbed_official 50:a417edff4437 298 #define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
mbed_official 50:a417edff4437 299 #define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
mbed_official 50:a417edff4437 300 #define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */
mbed_official 50:a417edff4437 301
mbed_official 50:a417edff4437 302 /* Bit fields for WDOG IEN */
mbed_official 50:a417edff4437 303 #define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */
mbed_official 50:a417edff4437 304 #define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */
mbed_official 50:a417edff4437 305 #define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */
mbed_official 50:a417edff4437 306 #define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
mbed_official 50:a417edff4437 307 #define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
mbed_official 50:a417edff4437 308 #define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
mbed_official 50:a417edff4437 309 #define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */
mbed_official 50:a417edff4437 310 #define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */
mbed_official 50:a417edff4437 311 #define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
mbed_official 50:a417edff4437 312 #define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
mbed_official 50:a417edff4437 313 #define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
mbed_official 50:a417edff4437 314 #define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */
mbed_official 50:a417edff4437 315 #define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */
mbed_official 50:a417edff4437 316 #define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
mbed_official 50:a417edff4437 317 #define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
mbed_official 50:a417edff4437 318 #define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
mbed_official 50:a417edff4437 319 #define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */
mbed_official 50:a417edff4437 320 #define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */
mbed_official 50:a417edff4437 321 #define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
mbed_official 50:a417edff4437 322 #define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
mbed_official 50:a417edff4437 323 #define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
mbed_official 50:a417edff4437 324 #define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */
mbed_official 50:a417edff4437 325 #define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */
mbed_official 50:a417edff4437 326 #define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
mbed_official 50:a417edff4437 327 #define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
mbed_official 50:a417edff4437 328 #define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
mbed_official 50:a417edff4437 329 #define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */
mbed_official 50:a417edff4437 330
mbed_official 50:a417edff4437 331 /** @} End of group EFM32PG1B_WDOG */
mbed_official 50:a417edff4437 332 /** @} End of group Parts */
mbed_official 50:a417edff4437 333