en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b200f128gm32.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
50:a417edff4437 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 50:a417edff4437 1 /**************************************************************************//**
mbed_official 50:a417edff4437 2 * @file efm32pg1b200f128gm32.h
mbed_official 50:a417edff4437 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
mbed_official 50:a417edff4437 4 * for EFM32PG1B200F128GM32
mbed_official 50:a417edff4437 5 * @version 4.2.0
mbed_official 50:a417edff4437 6 ******************************************************************************
mbed_official 50:a417edff4437 7 * @section License
mbed_official 50:a417edff4437 8 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
mbed_official 50:a417edff4437 9 ******************************************************************************
mbed_official 50:a417edff4437 10 *
mbed_official 50:a417edff4437 11 * Permission is granted to anyone to use this software for any purpose,
mbed_official 50:a417edff4437 12 * including commercial applications, and to alter it and redistribute it
mbed_official 50:a417edff4437 13 * freely, subject to the following restrictions:
mbed_official 50:a417edff4437 14 *
mbed_official 50:a417edff4437 15 * 1. The origin of this software must not be misrepresented; you must not
mbed_official 50:a417edff4437 16 * claim that you wrote the original software.@n
mbed_official 50:a417edff4437 17 * 2. Altered source versions must be plainly marked as such, and must not be
mbed_official 50:a417edff4437 18 * misrepresented as being the original software.@n
mbed_official 50:a417edff4437 19 * 3. This notice may not be removed or altered from any source distribution.
mbed_official 50:a417edff4437 20 *
mbed_official 50:a417edff4437 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
mbed_official 50:a417edff4437 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
mbed_official 50:a417edff4437 23 * providing the Software "AS IS", with no express or implied warranties of any
mbed_official 50:a417edff4437 24 * kind, including, but not limited to, any implied warranties of
mbed_official 50:a417edff4437 25 * merchantability or fitness for any particular purpose or warranties against
mbed_official 50:a417edff4437 26 * infringement of any proprietary rights of a third party.
mbed_official 50:a417edff4437 27 *
mbed_official 50:a417edff4437 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
mbed_official 50:a417edff4437 29 * incidental, or special damages, or any other relief, or for any claim by
mbed_official 50:a417edff4437 30 * any third party, arising from your use of this Software.
mbed_official 50:a417edff4437 31 *
mbed_official 50:a417edff4437 32 *****************************************************************************/
mbed_official 50:a417edff4437 33
mbed_official 50:a417edff4437 34 #ifndef SILICON_LABS_EFM32PG1B200F128GM32_H
mbed_official 50:a417edff4437 35 #define SILICON_LABS_EFM32PG1B200F128GM32_H
mbed_official 50:a417edff4437 36
mbed_official 50:a417edff4437 37 #ifdef __cplusplus
mbed_official 50:a417edff4437 38 extern "C" {
mbed_official 50:a417edff4437 39 #endif
mbed_official 50:a417edff4437 40
mbed_official 50:a417edff4437 41 /**************************************************************************//**
mbed_official 50:a417edff4437 42 * @addtogroup Parts
mbed_official 50:a417edff4437 43 * @{
mbed_official 50:a417edff4437 44 *****************************************************************************/
mbed_official 50:a417edff4437 45
mbed_official 50:a417edff4437 46 /**************************************************************************//**
mbed_official 50:a417edff4437 47 * @defgroup EFM32PG1B200F128GM32 EFM32PG1B200F128GM32
mbed_official 50:a417edff4437 48 * @{
mbed_official 50:a417edff4437 49 *****************************************************************************/
mbed_official 50:a417edff4437 50
mbed_official 50:a417edff4437 51 /** Interrupt Number Definition */
mbed_official 50:a417edff4437 52 typedef enum IRQn
mbed_official 50:a417edff4437 53 {
mbed_official 50:a417edff4437 54 /****** Cortex-M4 Processor Exceptions Numbers *******************************************/
mbed_official 50:a417edff4437 55 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
mbed_official 50:a417edff4437 56 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
mbed_official 50:a417edff4437 57 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 50:a417edff4437 58 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 50:a417edff4437 59 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 50:a417edff4437 60 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 50:a417edff4437 61 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 50:a417edff4437 62 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 50:a417edff4437 63 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 50:a417edff4437 64
mbed_official 50:a417edff4437 65 /****** EFM32PG1B Peripheral Interrupt Numbers *********************************************/
mbed_official 50:a417edff4437 66
mbed_official 50:a417edff4437 67 EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
mbed_official 50:a417edff4437 68 WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */
mbed_official 50:a417edff4437 69 LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */
mbed_official 50:a417edff4437 70 GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */
mbed_official 50:a417edff4437 71 TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */
mbed_official 50:a417edff4437 72 USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */
mbed_official 50:a417edff4437 73 USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */
mbed_official 50:a417edff4437 74 ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */
mbed_official 50:a417edff4437 75 ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */
mbed_official 50:a417edff4437 76 IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */
mbed_official 50:a417edff4437 77 I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */
mbed_official 50:a417edff4437 78 GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */
mbed_official 50:a417edff4437 79 TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */
mbed_official 50:a417edff4437 80 USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */
mbed_official 50:a417edff4437 81 USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */
mbed_official 50:a417edff4437 82 LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */
mbed_official 50:a417edff4437 83 PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */
mbed_official 50:a417edff4437 84 CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */
mbed_official 50:a417edff4437 85 MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */
mbed_official 50:a417edff4437 86 CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */
mbed_official 50:a417edff4437 87 LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
mbed_official 50:a417edff4437 88 RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */
mbed_official 50:a417edff4437 89 CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */
mbed_official 50:a417edff4437 90 FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */
mbed_official 50:a417edff4437 91 } IRQn_Type;
mbed_official 50:a417edff4437 92
mbed_official 50:a417edff4437 93 /**************************************************************************//**
mbed_official 50:a417edff4437 94 * @defgroup EFM32PG1B200F128GM32_Core EFM32PG1B200F128GM32 Core
mbed_official 50:a417edff4437 95 * @{
mbed_official 50:a417edff4437 96 * @brief Processor and Core Peripheral Section
mbed_official 50:a417edff4437 97 *****************************************************************************/
mbed_official 50:a417edff4437 98 #define __MPU_PRESENT 1 /**< Presence of MPU */
mbed_official 50:a417edff4437 99 #define __FPU_PRESENT 1 /**< Presence of FPU */
mbed_official 50:a417edff4437 100 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
mbed_official 50:a417edff4437 101 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
mbed_official 50:a417edff4437 102
mbed_official 50:a417edff4437 103 /** @} End of group EFM32PG1B200F128GM32_Core */
mbed_official 50:a417edff4437 104
mbed_official 50:a417edff4437 105 /**************************************************************************//**
mbed_official 50:a417edff4437 106 * @defgroup EFM32PG1B200F128GM32_Part EFM32PG1B200F128GM32 Part
mbed_official 50:a417edff4437 107 * @{
mbed_official 50:a417edff4437 108 ******************************************************************************/
mbed_official 50:a417edff4437 109
mbed_official 50:a417edff4437 110 /** Part family */
mbed_official 50:a417edff4437 111 #define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */
mbed_official 50:a417edff4437 112 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
mbed_official 50:a417edff4437 113 #define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */
mbed_official 50:a417edff4437 114 #define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */
mbed_official 50:a417edff4437 115
mbed_official 50:a417edff4437 116 /* If part number is not defined as compiler option, define it */
mbed_official 50:a417edff4437 117 #if !defined(EFM32PG1B200F128GM32)
mbed_official 50:a417edff4437 118 #define EFM32PG1B200F128GM32 1 /**< PEARL Gecko Part */
mbed_official 50:a417edff4437 119 #endif
mbed_official 50:a417edff4437 120
mbed_official 50:a417edff4437 121 /** Configure part number */
mbed_official 50:a417edff4437 122 #define PART_NUMBER "EFM32PG1B200F128GM32" /**< Part Number */
mbed_official 50:a417edff4437 123
mbed_official 50:a417edff4437 124 /** Memory Base addresses and limits */
mbed_official 50:a417edff4437 125 #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
mbed_official 50:a417edff4437 126 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
mbed_official 50:a417edff4437 127 #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
mbed_official 50:a417edff4437 128 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
mbed_official 50:a417edff4437 129 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
mbed_official 50:a417edff4437 130 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */
mbed_official 50:a417edff4437 131 #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */
mbed_official 50:a417edff4437 132 #define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */
mbed_official 50:a417edff4437 133 #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
mbed_official 50:a417edff4437 134 #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */
mbed_official 50:a417edff4437 135 #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */
mbed_official 50:a417edff4437 136 #define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */
mbed_official 50:a417edff4437 137 #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */
mbed_official 50:a417edff4437 138 #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */
mbed_official 50:a417edff4437 139 #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */
mbed_official 50:a417edff4437 140 #define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */
mbed_official 50:a417edff4437 141 #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */
mbed_official 50:a417edff4437 142 #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */
mbed_official 50:a417edff4437 143 #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */
mbed_official 50:a417edff4437 144 #define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */
mbed_official 50:a417edff4437 145 #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */
mbed_official 50:a417edff4437 146 #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */
mbed_official 50:a417edff4437 147 #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */
mbed_official 50:a417edff4437 148 #define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */
mbed_official 50:a417edff4437 149 #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
mbed_official 50:a417edff4437 150 #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */
mbed_official 50:a417edff4437 151 #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */
mbed_official 50:a417edff4437 152 #define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */
mbed_official 50:a417edff4437 153 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
mbed_official 50:a417edff4437 154 #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */
mbed_official 50:a417edff4437 155 #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */
mbed_official 50:a417edff4437 156 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
mbed_official 50:a417edff4437 157 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
mbed_official 50:a417edff4437 158 #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */
mbed_official 50:a417edff4437 159 #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */
mbed_official 50:a417edff4437 160 #define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
mbed_official 50:a417edff4437 161
mbed_official 50:a417edff4437 162 /** Bit banding area */
mbed_official 50:a417edff4437 163 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
mbed_official 50:a417edff4437 164 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
mbed_official 50:a417edff4437 165
mbed_official 50:a417edff4437 166 /** Flash and SRAM limits for EFM32PG1B200F128GM32 */
mbed_official 50:a417edff4437 167 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
mbed_official 50:a417edff4437 168 #define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */
mbed_official 50:a417edff4437 169 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
mbed_official 50:a417edff4437 170 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
mbed_official 50:a417edff4437 171 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
mbed_official 50:a417edff4437 172 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
mbed_official 50:a417edff4437 173 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
mbed_official 50:a417edff4437 174 #define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
mbed_official 50:a417edff4437 175
mbed_official 50:a417edff4437 176 /** AF channels connect the different on-chip peripherals with the af-mux */
mbed_official 50:a417edff4437 177 #define AFCHAN_MAX 72
mbed_official 50:a417edff4437 178 #define AFCHANLOC_MAX 32
mbed_official 50:a417edff4437 179 /** Analog AF channels */
mbed_official 50:a417edff4437 180 #define AFACHAN_MAX 61
mbed_official 50:a417edff4437 181
mbed_official 50:a417edff4437 182 /* Part number capabilities */
mbed_official 50:a417edff4437 183
mbed_official 50:a417edff4437 184 #define TIMER_PRESENT /**< TIMER is available in this part */
mbed_official 50:a417edff4437 185 #define TIMER_COUNT 2 /**< 2 TIMERs available */
mbed_official 50:a417edff4437 186 #define USART_PRESENT /**< USART is available in this part */
mbed_official 50:a417edff4437 187 #define USART_COUNT 2 /**< 2 USARTs available */
mbed_official 50:a417edff4437 188 #define LEUART_PRESENT /**< LEUART is available in this part */
mbed_official 50:a417edff4437 189 #define LEUART_COUNT 1 /**< 1 LEUARTs available */
mbed_official 50:a417edff4437 190 #define LETIMER_PRESENT /**< LETIMER is available in this part */
mbed_official 50:a417edff4437 191 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
mbed_official 50:a417edff4437 192 #define PCNT_PRESENT /**< PCNT is available in this part */
mbed_official 50:a417edff4437 193 #define PCNT_COUNT 1 /**< 1 PCNTs available */
mbed_official 50:a417edff4437 194 #define I2C_PRESENT /**< I2C is available in this part */
mbed_official 50:a417edff4437 195 #define I2C_COUNT 1 /**< 1 I2Cs available */
mbed_official 50:a417edff4437 196 #define ADC_PRESENT /**< ADC is available in this part */
mbed_official 50:a417edff4437 197 #define ADC_COUNT 1 /**< 1 ADCs available */
mbed_official 50:a417edff4437 198 #define ACMP_PRESENT /**< ACMP is available in this part */
mbed_official 50:a417edff4437 199 #define ACMP_COUNT 2 /**< 2 ACMPs available */
mbed_official 50:a417edff4437 200 #define IDAC_PRESENT /**< IDAC is available in this part */
mbed_official 50:a417edff4437 201 #define IDAC_COUNT 1 /**< 1 IDACs available */
mbed_official 50:a417edff4437 202 #define WDOG_PRESENT /**< WDOG is available in this part */
mbed_official 50:a417edff4437 203 #define WDOG_COUNT 1 /**< 1 WDOGs available */
mbed_official 50:a417edff4437 204 #define MSC_PRESENT
mbed_official 50:a417edff4437 205 #define MSC_COUNT 1
mbed_official 50:a417edff4437 206 #define EMU_PRESENT
mbed_official 50:a417edff4437 207 #define EMU_COUNT 1
mbed_official 50:a417edff4437 208 #define RMU_PRESENT
mbed_official 50:a417edff4437 209 #define RMU_COUNT 1
mbed_official 50:a417edff4437 210 #define CMU_PRESENT
mbed_official 50:a417edff4437 211 #define CMU_COUNT 1
mbed_official 50:a417edff4437 212 #define CRYPTO_PRESENT
mbed_official 50:a417edff4437 213 #define CRYPTO_COUNT 1
mbed_official 50:a417edff4437 214 #define GPIO_PRESENT
mbed_official 50:a417edff4437 215 #define GPIO_COUNT 1
mbed_official 50:a417edff4437 216 #define PRS_PRESENT
mbed_official 50:a417edff4437 217 #define PRS_COUNT 1
mbed_official 50:a417edff4437 218 #define LDMA_PRESENT
mbed_official 50:a417edff4437 219 #define LDMA_COUNT 1
mbed_official 50:a417edff4437 220 #define FPUEH_PRESENT
mbed_official 50:a417edff4437 221 #define FPUEH_COUNT 1
mbed_official 50:a417edff4437 222 #define GPCRC_PRESENT
mbed_official 50:a417edff4437 223 #define GPCRC_COUNT 1
mbed_official 50:a417edff4437 224 #define CRYOTIMER_PRESENT
mbed_official 50:a417edff4437 225 #define CRYOTIMER_COUNT 1
mbed_official 50:a417edff4437 226 #define RTCC_PRESENT
mbed_official 50:a417edff4437 227 #define RTCC_COUNT 1
mbed_official 50:a417edff4437 228 #define BOOTLOADER_PRESENT
mbed_official 50:a417edff4437 229 #define BOOTLOADER_COUNT 1
mbed_official 50:a417edff4437 230
mbed_official 50:a417edff4437 231 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 50:a417edff4437 232 #include "system_efm32pg1b.h" /* System Header File */
mbed_official 50:a417edff4437 233
mbed_official 50:a417edff4437 234 /** @} End of group EFM32PG1B200F128GM32_Part */
mbed_official 50:a417edff4437 235
mbed_official 50:a417edff4437 236 /**************************************************************************//**
mbed_official 50:a417edff4437 237 * @defgroup EFM32PG1B200F128GM32_Peripheral_TypeDefs EFM32PG1B200F128GM32 Peripheral TypeDefs
mbed_official 50:a417edff4437 238 * @{
mbed_official 50:a417edff4437 239 * @brief Device Specific Peripheral Register Structures
mbed_official 50:a417edff4437 240 *****************************************************************************/
mbed_official 50:a417edff4437 241
mbed_official 50:a417edff4437 242 #include "efm32pg1b_msc.h"
mbed_official 50:a417edff4437 243 #include "efm32pg1b_emu.h"
mbed_official 50:a417edff4437 244 #include "efm32pg1b_rmu.h"
mbed_official 50:a417edff4437 245 #include "efm32pg1b_cmu.h"
mbed_official 50:a417edff4437 246 #include "efm32pg1b_crypto.h"
mbed_official 50:a417edff4437 247 #include "efm32pg1b_gpio_p.h"
mbed_official 50:a417edff4437 248 #include "efm32pg1b_gpio.h"
mbed_official 50:a417edff4437 249 #include "efm32pg1b_prs_ch.h"
mbed_official 50:a417edff4437 250 #include "efm32pg1b_prs.h"
mbed_official 50:a417edff4437 251 #include "efm32pg1b_ldma_ch.h"
mbed_official 50:a417edff4437 252 #include "efm32pg1b_ldma.h"
mbed_official 50:a417edff4437 253 #include "efm32pg1b_fpueh.h"
mbed_official 50:a417edff4437 254 #include "efm32pg1b_gpcrc.h"
mbed_official 50:a417edff4437 255 #include "efm32pg1b_timer_cc.h"
mbed_official 50:a417edff4437 256 #include "efm32pg1b_timer.h"
mbed_official 50:a417edff4437 257 #include "efm32pg1b_usart.h"
mbed_official 50:a417edff4437 258 #include "efm32pg1b_leuart.h"
mbed_official 50:a417edff4437 259 #include "efm32pg1b_letimer.h"
mbed_official 50:a417edff4437 260 #include "efm32pg1b_cryotimer.h"
mbed_official 50:a417edff4437 261 #include "efm32pg1b_pcnt.h"
mbed_official 50:a417edff4437 262 #include "efm32pg1b_i2c.h"
mbed_official 50:a417edff4437 263 #include "efm32pg1b_adc.h"
mbed_official 50:a417edff4437 264 #include "efm32pg1b_acmp.h"
mbed_official 50:a417edff4437 265 #include "efm32pg1b_idac.h"
mbed_official 50:a417edff4437 266 #include "efm32pg1b_rtcc_cc.h"
mbed_official 50:a417edff4437 267 #include "efm32pg1b_rtcc_ret.h"
mbed_official 50:a417edff4437 268 #include "efm32pg1b_rtcc.h"
mbed_official 50:a417edff4437 269 #include "efm32pg1b_wdog_pch.h"
mbed_official 50:a417edff4437 270 #include "efm32pg1b_wdog.h"
mbed_official 50:a417edff4437 271 #include "efm32pg1b_dma_descriptor.h"
mbed_official 50:a417edff4437 272 #include "efm32pg1b_devinfo.h"
mbed_official 50:a417edff4437 273 #include "efm32pg1b_romtable.h"
mbed_official 50:a417edff4437 274
mbed_official 50:a417edff4437 275 /** @} End of group EFM32PG1B200F128GM32_Peripheral_TypeDefs */
mbed_official 50:a417edff4437 276
mbed_official 50:a417edff4437 277 /**************************************************************************//**
mbed_official 50:a417edff4437 278 * @defgroup EFM32PG1B200F128GM32_Peripheral_Base EFM32PG1B200F128GM32 Peripheral Memory Map
mbed_official 50:a417edff4437 279 * @{
mbed_official 50:a417edff4437 280 *****************************************************************************/
mbed_official 50:a417edff4437 281
mbed_official 50:a417edff4437 282 #define MSC_BASE (0x400E0000UL) /**< MSC base address */
mbed_official 50:a417edff4437 283 #define EMU_BASE (0x400E3000UL) /**< EMU base address */
mbed_official 50:a417edff4437 284 #define RMU_BASE (0x400E5000UL) /**< RMU base address */
mbed_official 50:a417edff4437 285 #define CMU_BASE (0x400E4000UL) /**< CMU base address */
mbed_official 50:a417edff4437 286 #define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
mbed_official 50:a417edff4437 287 #define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
mbed_official 50:a417edff4437 288 #define PRS_BASE (0x400E6000UL) /**< PRS base address */
mbed_official 50:a417edff4437 289 #define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
mbed_official 50:a417edff4437 290 #define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
mbed_official 50:a417edff4437 291 #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
mbed_official 50:a417edff4437 292 #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
mbed_official 50:a417edff4437 293 #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
mbed_official 50:a417edff4437 294 #define USART0_BASE (0x40010000UL) /**< USART0 base address */
mbed_official 50:a417edff4437 295 #define USART1_BASE (0x40010400UL) /**< USART1 base address */
mbed_official 50:a417edff4437 296 #define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
mbed_official 50:a417edff4437 297 #define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
mbed_official 50:a417edff4437 298 #define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
mbed_official 50:a417edff4437 299 #define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
mbed_official 50:a417edff4437 300 #define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
mbed_official 50:a417edff4437 301 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
mbed_official 50:a417edff4437 302 #define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
mbed_official 50:a417edff4437 303 #define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
mbed_official 50:a417edff4437 304 #define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
mbed_official 50:a417edff4437 305 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */
mbed_official 50:a417edff4437 306 #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
mbed_official 50:a417edff4437 307 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
mbed_official 50:a417edff4437 308 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
mbed_official 50:a417edff4437 309 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
mbed_official 50:a417edff4437 310 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
mbed_official 50:a417edff4437 311
mbed_official 50:a417edff4437 312 /** @} End of group EFM32PG1B200F128GM32_Peripheral_Base */
mbed_official 50:a417edff4437 313
mbed_official 50:a417edff4437 314 /**************************************************************************//**
mbed_official 50:a417edff4437 315 * @defgroup EFM32PG1B200F128GM32_Peripheral_Declaration EFM32PG1B200F128GM32 Peripheral Declarations
mbed_official 50:a417edff4437 316 * @{
mbed_official 50:a417edff4437 317 *****************************************************************************/
mbed_official 50:a417edff4437 318
mbed_official 50:a417edff4437 319 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
mbed_official 50:a417edff4437 320 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
mbed_official 50:a417edff4437 321 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
mbed_official 50:a417edff4437 322 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
mbed_official 50:a417edff4437 323 #define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
mbed_official 50:a417edff4437 324 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
mbed_official 50:a417edff4437 325 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
mbed_official 50:a417edff4437 326 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
mbed_official 50:a417edff4437 327 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
mbed_official 50:a417edff4437 328 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
mbed_official 50:a417edff4437 329 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
mbed_official 50:a417edff4437 330 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
mbed_official 50:a417edff4437 331 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
mbed_official 50:a417edff4437 332 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
mbed_official 50:a417edff4437 333 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
mbed_official 50:a417edff4437 334 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
mbed_official 50:a417edff4437 335 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
mbed_official 50:a417edff4437 336 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
mbed_official 50:a417edff4437 337 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
mbed_official 50:a417edff4437 338 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
mbed_official 50:a417edff4437 339 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
mbed_official 50:a417edff4437 340 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
mbed_official 50:a417edff4437 341 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
mbed_official 50:a417edff4437 342 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
mbed_official 50:a417edff4437 343 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
mbed_official 50:a417edff4437 344 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
mbed_official 50:a417edff4437 345 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
mbed_official 50:a417edff4437 346
mbed_official 50:a417edff4437 347 /** @} End of group EFM32PG1B200F128GM32_Peripheral_Declaration */
mbed_official 50:a417edff4437 348
mbed_official 50:a417edff4437 349 /**************************************************************************//**
mbed_official 50:a417edff4437 350 * @defgroup EFM32PG1B200F128GM32_Peripheral_Offsets EFM32PG1B200F128GM32 Peripheral Offsets
mbed_official 50:a417edff4437 351 * @{
mbed_official 50:a417edff4437 352 *****************************************************************************/
mbed_official 50:a417edff4437 353
mbed_official 50:a417edff4437 354 #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
mbed_official 50:a417edff4437 355 #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
mbed_official 50:a417edff4437 356 #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
mbed_official 50:a417edff4437 357 #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
mbed_official 50:a417edff4437 358 #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
mbed_official 50:a417edff4437 359 #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
mbed_official 50:a417edff4437 360 #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
mbed_official 50:a417edff4437 361 #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
mbed_official 50:a417edff4437 362 #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
mbed_official 50:a417edff4437 363 #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
mbed_official 50:a417edff4437 364
mbed_official 50:a417edff4437 365 /** @} End of group EFM32PG1B200F128GM32_Peripheral_Offsets */
mbed_official 50:a417edff4437 366
mbed_official 50:a417edff4437 367
mbed_official 50:a417edff4437 368 /**************************************************************************//**
mbed_official 50:a417edff4437 369 * @defgroup EFM32PG1B200F128GM32_BitFields EFM32PG1B200F128GM32 Bit Fields
mbed_official 50:a417edff4437 370 * @{
mbed_official 50:a417edff4437 371 *****************************************************************************/
mbed_official 50:a417edff4437 372
mbed_official 50:a417edff4437 373 #include "efm32pg1b_prs_signals.h"
mbed_official 50:a417edff4437 374 #include "efm32pg1b_dmareq.h"
mbed_official 50:a417edff4437 375
mbed_official 50:a417edff4437 376 /**************************************************************************//**
mbed_official 50:a417edff4437 377 * @defgroup EFM32PG1B200F128GM32_UNLOCK EFM32PG1B200F128GM32 Unlock Codes
mbed_official 50:a417edff4437 378 * @{
mbed_official 50:a417edff4437 379 *****************************************************************************/
mbed_official 50:a417edff4437 380 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
mbed_official 50:a417edff4437 381 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
mbed_official 50:a417edff4437 382 #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
mbed_official 50:a417edff4437 383 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
mbed_official 50:a417edff4437 384 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
mbed_official 50:a417edff4437 385 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
mbed_official 50:a417edff4437 386 #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
mbed_official 50:a417edff4437 387
mbed_official 50:a417edff4437 388 /** @} End of group EFM32PG1B200F128GM32_UNLOCK */
mbed_official 50:a417edff4437 389
mbed_official 50:a417edff4437 390 /** @} End of group EFM32PG1B200F128GM32_BitFields */
mbed_official 50:a417edff4437 391
mbed_official 50:a417edff4437 392 /**************************************************************************//**
mbed_official 50:a417edff4437 393 * @defgroup EFM32PG1B200F128GM32_Alternate_Function EFM32PG1B200F128GM32 Alternate Function
mbed_official 50:a417edff4437 394 * @{
mbed_official 50:a417edff4437 395 *****************************************************************************/
mbed_official 50:a417edff4437 396
mbed_official 50:a417edff4437 397 #include "efm32pg1b_af_ports.h"
mbed_official 50:a417edff4437 398 #include "efm32pg1b_af_pins.h"
mbed_official 50:a417edff4437 399
mbed_official 50:a417edff4437 400 /** @} End of group EFM32PG1B200F128GM32_Alternate_Function */
mbed_official 50:a417edff4437 401
mbed_official 50:a417edff4437 402 /**************************************************************************//**
mbed_official 50:a417edff4437 403 * @brief Set the value of a bit field within a register.
mbed_official 50:a417edff4437 404 *
mbed_official 50:a417edff4437 405 * @param REG
mbed_official 50:a417edff4437 406 * The register to update
mbed_official 50:a417edff4437 407 * @param MASK
mbed_official 50:a417edff4437 408 * The mask for the bit field to update
mbed_official 50:a417edff4437 409 * @param VALUE
mbed_official 50:a417edff4437 410 * The value to write to the bit field
mbed_official 50:a417edff4437 411 * @param OFFSET
mbed_official 50:a417edff4437 412 * The number of bits that the field is offset within the register.
mbed_official 50:a417edff4437 413 * 0 (zero) means LSB.
mbed_official 50:a417edff4437 414 *****************************************************************************/
mbed_official 50:a417edff4437 415 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
mbed_official 50:a417edff4437 416 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
mbed_official 50:a417edff4437 417
mbed_official 50:a417edff4437 418 /** @} End of group EFM32PG1B200F128GM32 */
mbed_official 50:a417edff4437 419
mbed_official 50:a417edff4437 420 /** @} End of group Parts */
mbed_official 50:a417edff4437 421
mbed_official 50:a417edff4437 422 #ifdef __cplusplus
mbed_official 50:a417edff4437 423 }
mbed_official 50:a417edff4437 424 #endif
mbed_official 50:a417edff4437 425 #endif /* SILICON_LABS_EFM32PG1B200F128GM32_H */